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* -sega/model2.cpp, sega/model2_v.cpp: Various improvements: (#14592) Matthew Daniels2025-12-021-0/+2
* cpu/i960.cpp: fix typo in ROUNDRL instruction (#14299) Matthew Daniels2025-10-081-1/+1
* cpu/i960: Split check_irqs() into two separate functions; fixes MT08347 (#14266) Matthew Daniels2025-10-052-54/+56
* cpu/i960: logr and logrl use base 2; always use correct rounding mode (#14215) Matthew Daniels2025-09-262-25/+32
* cpu/i960: Only trigger interrupts if the input changes to the asserted state.... Matthew Daniels2025-09-222-46/+56
* srcclean Vas Crabb2025-06-251-1/+1
* i960: Make shli produce identical value to shlo because later models where th... AJR2025-06-142-8/+33
* cpu/i960: Reduce padding area size when servicing interrupt (#13667) Matthew Daniels2025-05-041-1/+1
* i960: Further disassembly fixes AJR2025-03-251-3/+3
* i960: Fix disassembly of ADD<cc>, SUB<cc> & SEL<cc> for cc = l, ne, le, o AJR2025-03-241-1/+1
* Revert "i960: don't preserve sign bit when shifting integer left (#13507)" AJR2025-03-211-1/+1
* i960: don't preserve sign bit when shifting integer left (#13507) Matthew Daniels2025-03-211-1/+1
* i960: fix regression with emul opcode hap2024-12-191-1/+1
* cpu/i960, cpu/sharc, cpu/sparc, cpu/v60: Use 32x32=64-bit multiply inlines AJR2024-11-101-1/+1
* Added ATTR_COLD to common lifecycle methods for many files in src/devices. (#... holub2024-09-271-2/+2
* diexec: remove vestigal execute_input_lines() hap2024-09-181-1/+0
* cpu/i960: Corrected disassembly of dcinva instruction. (#11378) Joshua Scoggins2023-06-291-2/+2
* i960: Shift opcode fixes AJR2023-04-221-5/+10
* Interrupt callback rationalization AJR2023-03-111-1/+1
* dsp56156, i960, scudsp: Simplify some bits of code using util::sext AJR2022-11-201-10/+2
* coretmpl.h: Add utility function for sign-extending values of arbitrary width AJR2022-11-011-2/+2
* cpu/i960, cpu/sh: Use rotl_32 and rotr_32 for executing rotate instructions AJR2022-10-291-1/+1
* src/devices/cpu: Remove #include "debugger.h" where no longer necessary AJR2022-04-061-1/+0
* Debugger feature improvements AJR2022-03-271-0/+2
* srcclean and manual tidying up in preparation for 0.242 release Vas Crabb2022-03-271-6/+6
* cpu/i960: Added cycle count adjustment for dmovt instruction. (#9378) Damian Rogers2022-03-101-0/+1
* Added dmovt opcode to i960 cpu (#9341) Damian Rogers2022-03-041-0/+16
* Fun with flags: Allows handlers to have user-defined flags set on Olivier Galibert2021-11-282-31/+45
* -bus/coco/coco_ram.cpp: fix a rather obvious bug in shift/mask Vas Crabb2020-06-251-1/+1
* cpu/i960: Log unimplemented IACs Vas Crabb2020-06-251-2/+7
* srcclean and cleanup (nw) Vas Crabb2020-06-211-3/+3
* emumem: A little more speedup. cache and specific change syntax, and are not... Olivier Galibert2020-05-252-67/+67
* Add partial support for all IAC messages Damian Rogers2020-05-061-0/+21
* i960dasm: rewrote disassembler [SailorSat] Ariane Fugmann2020-05-042-266/+494
* i960dasm: add missing opcodes [SailorSat] Ariane Fugmann2020-04-292-20/+78
* fix #6207 (nw) MetalliC2020-01-231-3/+3
* use C++ library includes (nw) firewave2020-01-221-1/+1
* i960.h: fixed my oversight (nw) Ivan Vangelista2019-11-291-2/+2
* updated my recent commits to initialize bools with false instead of 0, as sug... Ivan Vangelista2019-11-282-3/+3
* i960.cpp: initialized some stuff (nw) Ivan Vangelista2019-11-262-5/+11
* Make many device_execute_interface functions noexcept, including the "informa... AJR2019-11-091-3/+3
* i960: implement logr and expr opcodes (for Model2 Power Sled) MetalliC2019-04-291-0/+12
* diexec: Interrupt API changes (nw) AJR2018-05-181-1/+0
* emumem: Rename direct_read_handler to memory_access_cache. Parametrize the t... Olivier Galibert2018-05-112-9/+9
* i960: Don't lose register values on read stalling [O. Galibert] Olivier Galibert2018-04-051-13/+31
* Reshuffle some stuff: Vas Crabb2018-03-281-2/+2
* don't pass so many naked pointers around (nw) Vas Crabb2018-03-252-3/+3
* Wrote a preliminary TGPx4 interpreter core [Angelo Salese] angelosa2018-03-202-7/+27
* Blind faith fixed long names for almost all CPUs (nw) angelosa2018-03-151-1/+1
* srcclean (nw) Vas Crabb2018-02-252-9/+9