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* -sega/model2.cpp, sega/model2_v.cpp: Various improvements: (#14592) Matthew Daniels2025-12-021-0/+2
| | | | | | | | | * Moved geo_parse() and frame number update to start of vertical blanking (fixes high score scrolling in segawski, 2D palette in dynamcopc, and 3D graphics in bel not displaying after first booting up). * Use exponent to adjust the Z-value scale for Z-sorting. * Merged model2_3d_process_quad() and model2_3d_process_triangle() into a single template function, since most of the code was identical. * Original Model 2 does have FIFO control; it uses the same 315-5673 buffer controller as Model 2A and 2C. * Replaced scanline timer with vertical blanking callback. -cpu/i960: Clear burst stall on reset (fixes Sega Model 2 games hanging on soft reset).
* cpu/i960.cpp: fix typo in ROUNDRL instruction (#14299) Matthew Daniels2025-10-081-1/+1
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* cpu/i960: Split check_irqs() into two separate functions; fixes MT08347 (#14266) Matthew Daniels2025-10-052-54/+56
| | | Pending interrupts are only checked after returning from an interrupt, while executing modpc if it causes the current priority to be lowered, and after receiving a test pending interrupts IAC message
* cpu/i960: logr and logrl use base 2; always use correct rounding mode (#14215) Matthew Daniels2025-09-262-25/+32
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* cpu/i960: Only trigger interrupts if the input changes to the asserted ↵ Matthew Daniels2025-09-222-46/+56
| | | | | | state. (#14186) * namco/namcofl.cpp: Implemented interrupt acknowledge, and drop interrupts on reset. * sega/model2.cpp: Drop interrupts on reset.
* srcclean Vas Crabb2025-06-251-1/+1
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* i960: Make shli produce identical value to shlo because later models where ↵ AJR2025-06-142-8/+33
| | | | | | they may differ are unsupported; distinguish KA and KB device types This effectively reverts commit e3997fb6b2caefaeba23cc6f3d3b67013ece87fb and reinstates 5954767b0b4da0c43f7194c7def4c162fbc8ef78.
* cpu/i960: Reduce padding area size when servicing interrupt (#13667) Matthew Daniels2025-05-041-1/+1
| | | Prevents crash due to stack overflow during ranking screen in Virtual-On
* i960: Further disassembly fixes AJR2025-03-251-3/+3
| | | | | - Enable decoding of a few more reg-type instructions - Add 0x prefix to unary branch destinations
* i960: Fix disassembly of ADD<cc>, SUB<cc> & SEL<cc> for cc = l, ne, le, o AJR2025-03-241-1/+1
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* Revert "i960: don't preserve sign bit when shifting integer left (#13507)" AJR2025-03-211-1/+1
| | | | | | This reverts commit 5954767b0b4da0c43f7194c7def4c162fbc8ef78. This was merged way too hastily based on incomplete information.
* i960: don't preserve sign bit when shifting integer left (#13507) Matthew Daniels2025-03-211-1/+1
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* i960: fix regression with emul opcode hap2024-12-191-1/+1
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* cpu/i960, cpu/sharc, cpu/sparc, cpu/v60: Use 32x32=64-bit multiply inlines AJR2024-11-101-1/+1
| | | | * cpu/v60: Simplify operation of DIVX, DIVUX, MOVD, RVBIT, RVBYTE
* Added ATTR_COLD to common lifecycle methods for many files in src/devices. ↵ holub2024-09-271-2/+2
| | | | (#12822)
* diexec: remove vestigal execute_input_lines() hap2024-09-181-1/+0
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* cpu/i960: Corrected disassembly of dcinva instruction. (#11378) Joshua Scoggins2023-06-291-2/+2
| | | 0xad should be disassembled as dcinva, not 0xac.
* i960: Shift opcode fixes AJR2023-04-221-5/+10
| | | | | - Ensure logically correct results for shift counts >= 32 - Preserve sign for shli
* Interrupt callback rationalization AJR2023-03-111-1/+1
| | | | | | | | | | | - Make CPUs pass interrupt return PC as a second argument to standard_irq_callback - Add interrupt return PC to "Stopped at interrupt" message produced by debugger 'gint' command - Add messages to trace logs whenever interrupts are accepted - Attempt to step over interrupt routines for applicable debugger commands - Eliminate standard_irq_callback_member wrapper method - Update many CPU cores to invoke standard_irq_callback at the start of or during interrupt processing, rather than at the end or when the input line changes - Remove IRQ callbacks for some input lines that never cause interrupts - mb88xx, mcs48: Add IRQ callbacks for internal interrupts
* dsp56156, i960, scudsp: Simplify some bits of code using util::sext AJR2022-11-201-10/+2
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* coretmpl.h: Add utility function for sign-extending values of arbitrary width AJR2022-11-011-2/+2
| | | | | * cpu/ccpu: Simplify code for right-shifting 12-bit values arithmetically * konami/3dom2_te.cpp: Fix probable copy-and-paste error
* cpu/i960, cpu/sh: Use rotl_32 and rotr_32 for executing rotate instructions AJR2022-10-291-1/+1
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* src/devices/cpu: Remove #include "debugger.h" where no longer necessary AJR2022-04-061-1/+0
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* Debugger feature improvements AJR2022-03-271-0/+2
| | | | | | | | - Add 'gbt' and 'gbf' debugger commands to step until a true or false conditional branch has been detected. - Update over 100 of the disassemblers in MAME to output a new STEP_COND flag for all conditional branches. Besides being used for execution of the new 'gbt' and 'gbf' commands, this flag also now helps the debugger 'out' command to properly handle conditional return instructions. - Remove STEP_OVER from many instructions that aren't actually subroutine calls (e.g. DJNZ on Z80). A 'gni' debugger command (go next instruction) has been added to accommodate some of the misuse. - Add instruction flag support to several more disassemblers that lacked them entirely (e.g. st62xx) - Don't pass over delay slots for debugging in ASAP core
* srcclean and manual tidying up in preparation for 0.242 release Vas Crabb2022-03-271-6/+6
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* cpu/i960: Added cycle count adjustment for dmovt instruction. (#9378) Damian Rogers2022-03-101-0/+1
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* Added dmovt opcode to i960 cpu (#9341) Damian Rogers2022-03-041-0/+16
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* Fun with flags: Allows handlers to have user-defined flags set on Olivier Galibert2021-11-282-31/+45
| | | | | | them, which can them be picked up on access with the {read,write}_*_flags variants of the accessors. Example use with the i960 and its burstable rom/ram.
* -bus/coco/coco_ram.cpp: fix a rather obvious bug in shift/mask Vas Crabb2020-06-251-1/+1
| | | | -misc. formatting consistency
* cpu/i960: Log unimplemented IACs Vas Crabb2020-06-251-2/+7
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* srcclean and cleanup (nw) Vas Crabb2020-06-211-3/+3
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* emumem: A little more speedup. cache and specific change syntax, and are ↵ Olivier Galibert2020-05-252-67/+67
| | | | | | | | | | | | | | | | not pointers anymore [O. Galibert] The last(?) two changes are: - Add a template parameter to everything (theoretically the address space width, in practice a level derived from it to keep as much compatibility between widths as possible) so that the shift size becomes a constant. - Change the syntax of declaring and initializing the caches and specifics so that they're embedded in the owner device. Solves lifetime issues and also removes one indirection (looking up the base dispatch pointer through the cache/specific pointer).
* Add partial support for all IAC messages Damian Rogers2020-05-061-0/+21
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* i960dasm: rewrote disassembler [SailorSat] Ariane Fugmann2020-05-042-266/+494
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* i960dasm: add missing opcodes [SailorSat] Ariane Fugmann2020-04-292-20/+78
| | | i960dasm: add missing opcodes [SailorSat]
* fix #6207 (nw) MetalliC2020-01-231-3/+3
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* use C++ library includes (nw) firewave2020-01-221-1/+1
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* i960.h: fixed my oversight (nw) Ivan Vangelista2019-11-291-2/+2
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* updated my recent commits to initialize bools with false instead of 0, as ↵ Ivan Vangelista2019-11-282-3/+3
| | | | suggested (nw)
* i960.cpp: initialized some stuff (nw) Ivan Vangelista2019-11-262-5/+11
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* Make many device_execute_interface functions noexcept, including the ↵ AJR2019-11-091-3/+3
| | | | | | | | "information" overrides. This also covers several time-related functions in attotime, running_machine and emu_timer. (nw) m6805: Calculate min_cycles and max_cycles once at device_start time (Nw) attotime: Add as_khz and as_mhz (nw)
* i960: implement logr and expr opcodes (for Model2 Power Sled) MetalliC2019-04-291-0/+12
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* diexec: Interrupt API changes (nw) AJR2018-05-181-1/+0
| | | | | | - PULSE_LINE is no longer a value. Existing uses have been changed to pulse_input_line with attotime::zero as the second argument. - Formerly only INPUT_LINE_NMI and INPUT_LINE_RESET were allowed with PULSE_LINE. INPUT_LINE_NMI no longer receives special handling; instead, CPU devices must specify which of their input lines are edge-triggered and thus may be used with zero-width pulses by overriding the execute_input_edge_triggered predicate. INPUT_LINE_RESET is still special-cased, however. - execute_default_irq_vector now allows a different default vector to be specified for each input line. This added flexibility may or may not prove useful.
* emumem: Rename direct_read_handler to memory_access_cache. Parametrize the ↵ Olivier Galibert2018-05-112-9/+9
| | | | template on more information (data width, endianness) to make it possible to turn it into an handler cache eventually, and not just a memory block cache. Make it capable of large and unaligned accesses. [O. Galibert]
* i960: Don't lose register values on read stalling [O. Galibert] Olivier Galibert2018-04-051-13/+31
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* Reshuffle some stuff: Vas Crabb2018-03-281-2/+2
| | | | | | * Move around the debugger hooks to get a small but measurable performance increase * Remove emucore from external tools * Improve performance of DSP16 interpreter a little by generating six variants of execution loop
* don't pass so many naked pointers around (nw) Vas Crabb2018-03-252-3/+3
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* Wrote a preliminary TGPx4 interpreter core [Angelo Salese] angelosa2018-03-202-7/+27
| | | | i960.cpp: support burst stall on writes [Angelo Salese]
* Blind faith fixed long names for almost all CPUs (nw) angelosa2018-03-151-1/+1
| | | | mb86235.cpp: renamed pcs_ptr into pcp, and added a file for future interpreter core (nw)
* srcclean (nw) Vas Crabb2018-02-252-9/+9
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