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* src/devices/cpu: Remove #include "debugger.h" where no longer necessary AJR2022-04-067-9/+0
* Debugger feature improvements AJR2022-03-271-4/+4
* devices/*: Removed extra semicolons after function bodies in headers. (#9275) 0kmg2022-02-061-1/+1
* srcclean in preparation for 0.240 Vas Crabb2022-01-231-9/+9
* Fix several issues in DC-based HW (#9150) Angelo Salese2022-01-173-34/+29
* Make debugger 'out' command step over return delay slots on SH architectures AJR2021-09-221-4/+4
* Debugger-related feature removals and cleanup AJR2021-08-152-2/+2
* Eliminate ARRAY_LENGTH template in favor of C++17's std::size AJR2021-02-141-4/+4
* -Switch to building MAME as C++17. Vas Crabb2020-11-152-1/+2
* finally retired the READ8/16/32/64 and WRITE8/16/32/64 macros (nw) Ivan Vangelista2020-06-1810-241/+241
* finished removing read* and write* macros from the mame part of the tree. the... Ivan Vangelista2020-06-162-12/+12
* emumem: A little more speedup. cache and specific change syntax, and are not... Olivier Galibert2020-05-254-18/+23
* devices/cpu: simplified some handlers (nw) Ivan Vangelista2020-03-312-28/+28
* remove unnecessary SuperH 3/4 timers restarts MetalliC2020-02-251-34/+32
* srcclean, manual adjustments (nw) Vas Crabb2020-01-261-1/+1
* sh4.cpp: disable timers at reset (nw) yz70s2020-01-141-0/+14
* sh3: handle INTEVT register MetalliC2019-12-223-27/+35
* cpu\sh2: initialize stuff (nw) Ivan Vangelista2019-12-142-55/+57
* Make many device_execute_interface functions noexcept, including the "informa... AJR2019-11-092-9/+9
* sh2: implement watchdog timer MetalliC2019-11-073-1/+58
* Make devdelegate more like devcb for configuration. This is a Vas Crabb2019-10-262-21/+9
* (nw) removed every remaining AM_ macro I could find in comments, but one in ... Ivan Vangelista2019-10-103-8/+8
* sh2.cpp/sh4.cpp: Don't emit fast RAM accesses when the debugger is enabled [P... Philip Bennett2019-09-242-88/+94
* SH2 clock multiplier docs MetalliC2019-08-293-8/+21
* srcclean (nw) Vas Crabb2019-06-233-48/+48
* mega32x.cpp: refactor and convert read/write handlers to 16-bit space [Angelo... Angelo Salese2019-06-222-7/+7
* sh2.cpp: first pass over SH7604 SoC refactoring [Angelo Salese] Angelo Salese2019-06-214-419/+1012
* (nw) Clean up the mess on master Vas Crabb2019-03-261-1/+1
* Revert "conflict resolution (nw)" andreasnaive2019-03-251-1/+1
* sh2: Fix interpreter for cps3 [O. Galibert] Olivier Galibert2019-01-191-1/+1
* -sh2, sh4, sat_ctrl: Removed MCFG, nw mooglyguy2018-12-094-101/+44
* -mb86235, sh7604, sharc: Removed MCFG macros, nw mooglyguy2018-12-093-21/+0
* as if millions of this pointers suddenly cried out in terror, and were sudden... Vas Crabb2018-06-084-28/+28
* srcclean (nw) Vas Crabb2018-05-271-1/+1
* diexec: Interrupt API changes (nw) AJR2018-05-182-1/+3
* D'oh. (nw) arbee2018-05-161-0/+7
* sh4drc: optimize FPU CMP instructions (nw) arbee2018-05-161-20/+8
* sh4drc: fix SR damage in new CMP implementations (nw) arbee2018-05-151-4/+12
* Start killing off non-diexec PULSE_LINE hacks (nw) AJR2018-05-155-18/+7
* sh4drc: remove remaining CALLC from FRCHG (nw) arbee2018-05-151-5/+13
* sh4drc: optimized some of the previously implemented UML (nw) arbee2018-05-141-23/+11
* sh4drc: UML implementations of FSTS, FLOAT, FTRC, FNEG, FABS, FSCHG, and FRCH... arbee2018-05-141-46/+76
* sh4drc: UML implementations of FLDI0, FLDI1, FCMP_EQ, and FCMP_GT [R. Belmont] arbee2018-05-131-28/+54
* emumem: Rename direct_read_handler to memory_access_cache. Parametrize the t... Olivier Galibert2018-05-116-28/+65
* Make MCFG_DEVICE_ADD and callable device types more flexible: Vas Crabb2018-05-042-6/+11
* srcclean (nw) Vas Crabb2018-04-222-9/+9
* maps: Finish devices/cpu (nw) Olivier Galibert2018-04-205-55/+64
* sh4drc: 8 more UML conversions (nw) arbee2018-04-151-50/+9
* sh4drc: UML version of FMAC, fixed possible error in previous FPU conversion ... arbee2018-04-153-69/+69
* sh4drc: 3 more trivial UML conversions (nw) arbee2018-04-151-21/+6