diff options
| author | 2019-06-23 18:02:43 +1000 | |
|---|---|---|
| committer | 2019-06-23 18:02:43 +1000 | |
| commit | d3af11cb11676ae88e9feb4bac5fa02aff7967a2 (patch) | |
| tree | e4f6c23dbf428c612d656d5069bb08833d543e73 /src/devices/cpu/sh | |
| parent | 12561ec937565b4c53d336f0a5658b015d99af8d (diff) | |
srcclean (nw)
Diffstat (limited to 'src/devices/cpu/sh')
| -rw-r--r-- | src/devices/cpu/sh/sh2.cpp | 28 | ||||
| -rw-r--r-- | src/devices/cpu/sh/sh2.h | 38 | ||||
| -rw-r--r-- | src/devices/cpu/sh/sh2comn.cpp | 30 |
3 files changed, 48 insertions, 48 deletions
diff --git a/src/devices/cpu/sh/sh2.cpp b/src/devices/cpu/sh/sh2.cpp index e00c0e60c57..28a952f0d22 100644 --- a/src/devices/cpu/sh/sh2.cpp +++ b/src/devices/cpu/sh/sh2.cpp @@ -130,8 +130,8 @@ void sh2_device::sh7604_map(address_map &map) // TODO: cps3boot breaks with this enabled. Needs callback // AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM // cache data array - -// map(0xe0000000, 0xe00001ff).mirror(0x1ffffe00).rw(FUNC(sh2_device::sh7604_r), FUNC(sh2_device::sh7604_w)); + +// map(0xe0000000, 0xe00001ff).mirror(0x1ffffe00).rw(FUNC(sh2_device::sh7604_r), FUNC(sh2_device::sh7604_w)); // TODO: internal map takes way too much resources if mirrored with 0x1ffffe00 // we eventually internalize again via trampoline & sh7604_device // Also area 0xffff8000-0xffffbfff is for synchronous DRAM mode, @@ -143,7 +143,7 @@ void sh2_device::sh7604_map(address_map &map) map(0xfffffe03, 0xfffffe03).rw(FUNC(sh2_device::tdr_r), FUNC(sh2_device::tdr_w)); map(0xfffffe04, 0xfffffe04).rw(FUNC(sh2_device::ssr_r), FUNC(sh2_device::ssr_w)); map(0xfffffe05, 0xfffffe05).r(FUNC(sh2_device::rdr_r)); - + // FRC map(0xfffffe10, 0xfffffe10).rw(FUNC(sh2_device::tier_r), FUNC(sh2_device::tier_w)); map(0xfffffe11, 0xfffffe11).rw(FUNC(sh2_device::ftcsr_r), FUNC(sh2_device::ftcsr_w)); @@ -162,7 +162,7 @@ void sh2_device::sh7604_map(address_map &map) map(0xfffffe71, 0xfffffe71).rw(FUNC(sh2_device::drcr_r<0>), FUNC(sh2_device::drcr_w<0>)); map(0xfffffe72, 0xfffffe72).rw(FUNC(sh2_device::drcr_r<1>), FUNC(sh2_device::drcr_w<1>)); - + // WTC map(0xfffffe80, 0xfffffe81).rw(FUNC(sh2_device::wtcnt_r), FUNC(sh2_device::wtcnt_w)); map(0xfffffe82, 0xfffffe83).rw(FUNC(sh2_device::rstcsr_r), FUNC(sh2_device::rstcsr_w)); @@ -170,7 +170,7 @@ void sh2_device::sh7604_map(address_map &map) // standby and cache control map(0xfffffe91, 0xfffffe91).rw(FUNC(sh2_device::sbycr_r), FUNC(sh2_device::sbycr_w)); map(0xfffffe92, 0xfffffe92).rw(FUNC(sh2_device::ccr_r), FUNC(sh2_device::ccr_w)); - + // INTC second section map(0xfffffee0, 0xfffffee1).rw(FUNC(sh2_device::intc_icr_r), FUNC(sh2_device::intc_icr_w)); map(0xfffffee2, 0xfffffee3).rw(FUNC(sh2_device::ipra_r), FUNC(sh2_device::ipra_w)); @@ -198,11 +198,11 @@ void sh2_device::sh7604_map(address_map &map) map(0xffffff94, 0xffffff97).rw(FUNC(sh2_device::dar_r<1>), FUNC(sh2_device::dar_w<1>)); map(0xffffff98, 0xffffff9b).rw(FUNC(sh2_device::dmac_tcr_r<1>), FUNC(sh2_device::dmac_tcr_w<1>)); map(0xffffff9c, 0xffffff9f).rw(FUNC(sh2_device::chcr_r<1>), FUNC(sh2_device::chcr_w<1>)); - + map(0xffffffa0, 0xffffffa3).rw(FUNC(sh2_device::vcrdma_r<0>), FUNC(sh2_device::vcrdma_w<0>)); map(0xffffffa8, 0xffffffab).rw(FUNC(sh2_device::vcrdma_r<1>), FUNC(sh2_device::vcrdma_w<1>)); map(0xffffffb0, 0xffffffb3).rw(FUNC(sh2_device::dmaor_r), FUNC(sh2_device::dmaor_w)); - + // BSC map(0xffffffe0, 0xffffffe3).rw(FUNC(sh2_device::bcr1_r), FUNC(sh2_device::bcr1_w)); map(0xffffffe4, 0xffffffe7).rw(FUNC(sh2_device::bcr2_r), FUNC(sh2_device::bcr2_w)); @@ -575,7 +575,7 @@ void sh2_device::device_start() save_item(NAME(m_irq_vector.divu)); save_item(NAME(m_irq_vector.dmac[0])); save_item(NAME(m_irq_vector.dmac[1])); - + save_item(NAME(m_ipra)); save_item(NAME(m_iprb)); save_item(NAME(m_vcra)); @@ -590,14 +590,14 @@ void sh2_device::device_start() save_item(NAME(m_vecmd)); save_item(NAME(m_nmie)); - + // DIVU save_item(NAME(m_divu_ovf)); save_item(NAME(m_divu_ovfie)); save_item(NAME(m_dvsr)); save_item(NAME(m_dvdntl)); save_item(NAME(m_dvdnth)); - + // WTC save_item(NAME(m_wtcnt)); save_item(NAME(m_wtcsr)); @@ -617,11 +617,11 @@ void sh2_device::device_start() save_item(NAME(m_dmac[1].tcr)); save_item(NAME(m_dmac[0].chcr)); save_item(NAME(m_dmac[1].chcr)); - + // misc save_item(NAME(m_sbycr)); save_item(NAME(m_ccr)); - + // BSC save_item(NAME(m_bcr1)); save_item(NAME(m_bcr2)); @@ -630,7 +630,7 @@ void sh2_device::device_start() save_item(NAME(m_rtcsr)); save_item(NAME(m_rtcor)); save_item(NAME(m_rtcnt)); - + /* for (int i = 0; i < 16; ++i) { @@ -647,7 +647,7 @@ void sh2_device::device_start() save_item(NAME(m_internal_irq_vector)); save_item(NAME(m_dma_timer_active)); save_item(NAME(m_dma_irq)); - + state_add( STATE_GENPC, "PC", m_sh2_state->pc).mask(SH12_AM).callimport(); state_add( STATE_GENPCBASE, "CURPC", m_sh2_state->pc ).callimport().noshow(); diff --git a/src/devices/cpu/sh/sh2.h b/src/devices/cpu/sh/sh2.h index e119d6bc098..1e5abeb795b 100644 --- a/src/devices/cpu/sh/sh2.h +++ b/src/devices/cpu/sh/sh2.h @@ -95,7 +95,7 @@ public: DECLARE_READ8_MEMBER( ssr_r ); DECLARE_WRITE8_MEMBER( ssr_w ); DECLARE_READ8_MEMBER( rdr_r ); - + // FRT / FRC DECLARE_READ8_MEMBER( tier_r ); DECLARE_WRITE8_MEMBER( tier_w ); @@ -110,7 +110,7 @@ public: DECLARE_READ8_MEMBER( tocr_r ); DECLARE_WRITE8_MEMBER( tocr_w ); DECLARE_READ16_MEMBER( frc_icr_r ); - + // INTC DECLARE_READ16_MEMBER( ipra_r ); DECLARE_WRITE16_MEMBER( ipra_w ); @@ -130,7 +130,7 @@ public: DECLARE_WRITE32_MEMBER( vcrdiv_w ); DECLARE_READ16_MEMBER( intc_icr_r ); DECLARE_WRITE16_MEMBER( intc_icr_w ); - + // DIVU DECLARE_READ32_MEMBER( dvsr_r ); DECLARE_WRITE32_MEMBER( dvsr_w ); @@ -143,21 +143,21 @@ public: DECLARE_READ32_MEMBER( dvcr_r ); DECLARE_WRITE32_MEMBER( dvcr_w ); - + // DMAC template <int Channel> READ32_MEMBER(vcrdma_r) { return m_vcrdma[Channel] & 0x7f; } - + template <int Channel> WRITE32_MEMBER(vcrdma_w) { COMBINE_DATA(&m_vcrdma[Channel]); m_irq_vector.dmac[Channel] = m_vcrdma[Channel] & 0x7f; sh2_recalc_irq(); } - - template <int Channel> READ8_MEMBER(drcr_r) { return m_dmac[Channel].drcr & 3; } + + template <int Channel> READ8_MEMBER(drcr_r) { return m_dmac[Channel].drcr & 3; } template <int Channel> WRITE8_MEMBER(drcr_w) { m_dmac[Channel].drcr = data & 3; sh2_recalc_irq(); } template <int Channel> READ32_MEMBER(sar_r) { return m_dmac[Channel].sar; } template <int Channel> WRITE32_MEMBER(sar_w) { COMBINE_DATA(&m_dmac[Channel].sar); } @@ -166,8 +166,8 @@ public: template <int Channel> READ32_MEMBER(dmac_tcr_r) { return m_dmac[Channel].tcr; } template <int Channel> WRITE32_MEMBER(dmac_tcr_w) { COMBINE_DATA(&m_dmac[Channel].tcr); m_dmac[Channel].tcr &= 0xffffff; } template <int Channel> READ32_MEMBER(chcr_r) { return m_dmac[Channel].chcr; } - template <int Channel> WRITE32_MEMBER(chcr_w) - { + template <int Channel> WRITE32_MEMBER(chcr_w) + { uint32_t old; old = m_dmac[Channel].chcr; COMBINE_DATA(&m_dmac[Channel].chcr); @@ -186,19 +186,19 @@ public: sh2_dmac_check(1); } } - + // WTC DECLARE_READ16_MEMBER( wtcnt_r ); DECLARE_WRITE16_MEMBER( wtcnt_w ); DECLARE_READ16_MEMBER( rstcsr_r ); DECLARE_WRITE16_MEMBER( rstcsr_w ); - + // misc DECLARE_READ8_MEMBER( sbycr_r ); DECLARE_WRITE8_MEMBER( sbycr_w ); DECLARE_READ8_MEMBER( ccr_r ); DECLARE_WRITE8_MEMBER( ccr_w ); - + // BSC DECLARE_READ32_MEMBER( bcr1_r ); DECLARE_WRITE32_MEMBER( bcr1_w ); @@ -215,7 +215,7 @@ public: DECLARE_READ32_MEMBER( rtcnt_r ); DECLARE_WRITE32_MEMBER( rtcnt_w ); - + virtual void set_frt_input(int state) override; void sh2_notify_dma_data_available(); void func_fastirq(); @@ -283,16 +283,16 @@ private: uint16_t m_ipra, m_iprb; uint16_t m_vcra, m_vcrb, m_vcrc, m_vcrd, m_vcrwdt, m_vcrdiv, m_intc_icr, m_vcrdma[2]; bool m_vecmd, m_nmie; - + // DIVU bool m_divu_ovf, m_divu_ovfie; uint32_t m_dvsr, m_dvdntl, m_dvdnth; - + // WTC uint8_t m_wtcnt, m_wtcsr; uint8_t m_rstcsr; uint16_t m_wtcw[2]; - + // DMAC struct { uint8_t drcr; @@ -302,13 +302,13 @@ private: uint32_t chcr; } m_dmac[2]; uint8_t m_dmaor; - + // misc uint8_t m_sbycr, m_ccr; - + // BSC uint32_t m_bcr1, m_bcr2, m_wcr, m_mcr, m_rtcsr, m_rtcor, m_rtcnt; - + int8_t m_nmi_line_state; uint64_t m_frc_base; diff --git a/src/devices/cpu/sh/sh2comn.cpp b/src/devices/cpu/sh/sh2comn.cpp index 7a7829e9db9..42ff2e358fb 100644 --- a/src/devices/cpu/sh/sh2comn.cpp +++ b/src/devices/cpu/sh/sh2comn.cpp @@ -510,10 +510,10 @@ READ8_MEMBER( sh2_device::rdr_r ) return 0; } -/* +/* * FRC */ - + READ8_MEMBER( sh2_device::tier_r ) { return m_tier; @@ -529,10 +529,10 @@ WRITE8_MEMBER( sh2_device::tier_w ) READ8_MEMBER( sh2_device::ftcsr_r ) { - // TODO: to be tested + // TODO: to be tested if (!m_ftcsr_read_cb.isnull()) m_ftcsr_read_cb((((m_tier<<24) | (m_ftcsr<<16)) & 0xffff0000) | m_frc); - + return m_ftcsr; } @@ -610,7 +610,7 @@ READ16_MEMBER( sh2_device::frc_icr_r ) return m_frc_icr; } -/* +/* * INTC */ @@ -641,7 +641,7 @@ WRITE16_MEMBER( sh2_device::ipra_w ) m_irq_level.wdt = (m_ipra >> 4) & 0xf; sh2_recalc_irq(); } - + READ16_MEMBER( sh2_device::iprb_r ) { return m_iprb & 0xff00; @@ -729,13 +729,13 @@ WRITE32_MEMBER( sh2_device::vcrdiv_w ) sh2_recalc_irq(); } -/* +/* * DIVU */ READ32_MEMBER( sh2_device::dvcr_r ) { - return (m_divu_ovfie == true ? 2 : 0) | (m_divu_ovf == true ? 1 : 0); + return (m_divu_ovfie == true ? 2 : 0) | (m_divu_ovf == true ? 1 : 0); } WRITE32_MEMBER( sh2_device::dvcr_w ) @@ -835,7 +835,7 @@ WRITE32_MEMBER( sh2_device::dvdntl_w ) } } -/* +/* * WTC */ @@ -907,12 +907,12 @@ READ8_MEMBER( sh2_device::ccr_r ) WRITE8_MEMBER( sh2_device::ccr_w ) { /* - xx-- ---- Way 0/1 - ---x ---- Cache Purge (CP), write only - ---- x--- Two-Way Mode (TW) - ---- -x-- Data Replacement Disable (OD) - ---- --x- Instruction Replacement Disable (ID) - ---- ---x Cache Enable (CE) + xx-- ---- Way 0/1 + ---x ---- Cache Purge (CP), write only + ---- x--- Two-Way Mode (TW) + ---- -x-- Data Replacement Disable (OD) + ---- --x- Instruction Replacement Disable (ID) + ---- ---x Cache Enable (CE) */ m_ccr = data; } |
