| Commit message (Collapse) | Author | Age | Files | Lines |
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Only update LRU values greater than the current LRU value on cache hit
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Handle the precharge of the last active bank in the background and only
pay the penalty on a bank conflict and only pay the remainder of the
wait cycles that haven't elapsed since the last access
Update the read->write wait penalty time for dirty writeback eviction
since wcr1 should contain that value
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Fix a shift error in the wcr1 register values
Add bcr2 plumbing for determining cache line fetch reads based off BCR2.
Area 0 is set via external pins so hardcoding the cv1k value, this is
typically code space though so it only affects timing during copy of
code to main memory
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* Add cv1k SH7709S cache handling behavior for slowdown emulation
- Handles some basic caching for the sh7709s used for cv1k titles so that they run at more appropriate speeds
* sh7709s.cpp: Fix up a couple of timing handling bugs
- Use the writeback flag instead of write flag as the access to external memory is what matters for those
- Fix up the writeback buffer timing, we don't need to precharge twice for writes. Also rolled up the command costs the SDRAM region handling so the writes only need to add trwl to the penalty
- Check for burst mode availability when determining the base cycle cost, only burst ROM and sdram can use burst access to each other area requires 4 separate accesses
* sh7709s.cpp: Add some comments explaining missing/unimplemented features
- Add the non-burst timing table for WCR2
- Updates and adds a couple of extra comments related to the penalties/timing
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