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* fix(sh7604): fix three register access bugs (#15101) JOTEGO2026-03-141-3/+3
| | | | | | | - vcrd_w: read m_vcrd instead of m_vcrc for FOV interrupt vector - dmaor_w: use (old & data & 6) so AE/NMIF flags can actually be cleared - vcrb_r: mask reserved bits 15 and 7 with 0x7f7f, matching vcra/vcrc/vcrwdt Co-authored-by: Jose Tejada <jose.tejada@analog.com>
* sh/sh7709s.cpp: Fix LRU cache replacement updates (#15098) Jesus Ramos2026-03-141-2/+2
| | | Only update LRU values greater than the current LRU value on cache hit
* sh/sh7709s.cpp: Update bank conflict precharge penalty timing (#15087) Jesus Ramos2026-03-122-12/+28
| | | | | | | | Handle the precharge of the last active bank in the background and only pay the penalty on a bank conflict and only pay the remainder of the wait cycles that haven't elapsed since the last access Update the read->write wait penalty time for dirty writeback eviction since wcr1 should contain that value
* sh/sh7709s.cpp: Convert the cpu cycles to bus cycles properly (#15078) Jesus Ramos2026-03-102-76/+47
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* sh/sh7709s.cpp: Fix bug in DRC memory accessor using clobbered IO reg (#15074) Jesus Ramos2026-03-081-11/+22
| | | | | | | Fix a shift error in the wcr1 register values Add bcr2 plumbing for determining cache line fetch reads based off BCR2. Area 0 is set via external pins so hardcoding the cv1k value, this is typically code space though so it only affects timing during copy of code to main memory
* Missing emu.h Olivier Galibert2026-03-081-0/+1
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* cpu/sh: Add cv1k SH7709S cache handling behavior for slowdown emulation (#15054) Jesus Ramos2026-03-074-38/+618
| | | | | | | | | | | | | * Add cv1k SH7709S cache handling behavior for slowdown emulation - Handles some basic caching for the sh7709s used for cv1k titles so that they run at more appropriate speeds * sh7709s.cpp: Fix up a couple of timing handling bugs - Use the writeback flag instead of write flag as the access to external memory is what matters for those - Fix up the writeback buffer timing, we don't need to precharge twice for writes. Also rolled up the command costs the SDRAM region handling so the writes only need to add trwl to the penalty - Check for burst mode availability when determining the base cycle cost, only burst ROM and sdram can use burst access to each other area requires 4 separate accesses * sh7709s.cpp: Add some comments explaining missing/unimplemented features - Add the non-burst timing table for WCR2 - Updates and adds a couple of extra comments related to the penalties/timing
* cpu/sharc: Implemented a bit more functionality and fixed bugs: Vas Crabb2026-03-071-0/+2
| | | | | | | | | * Implemented short word sign extension. * Fixed DAG2 (PM) register display in debugger. * Track AF dependencies when analysing instructions. * Log analysed instructions when logging UML code. * Removed misplaced break in cpu/sharc/sharcfe.cpp. * cpu/uml.h: Let C functions take any pointer/reference parameter.
* More stuff mostly related to recompiling CPUs: Vas Crabb2026-03-064-94/+94
| | | | | | | | | | | | | | | | cpu/drcbearm64.cpp: Don't set the rounding mode on SETFMOD if it hasn't changed. cpu/e132xs.cpp: Skip more unnecessary flag calculations, use pre-calculated PC for updating G0 in memory when possible, better analysis of pre-calculated PC values when delay slots are involved. cpu/sh: Cleaned up register dependency analysis logging, fixed an instruction analysis bug. cpu/sharc: Disassemble unimplemented instructions executed in recompiled code, include tag in more fatal errors, use throw syntax to make it cleared it's an early out.
* -cpu/e132xs: Log analysed instructions in UML log when using recompiler. Vas Crabb2026-03-054-67/+75
| | | | | | | | | | | | -cpu/powerpc: Modernised recompiler front-end code, improved instruction analysis logging. -cpu/sh: Cleaned up instruction analysis logging a little -util/client_ws.hpp, util/server_ws_impl.hpp, capcom/cps2comm.cpp: Updated some use of deprecation ASIO APIs. -nakajima/nakajies.cpp: Use range-based loops.
* Allow recompiling CPU cores to define their own opcode descriptions. Vas Crabb2026-03-0213-500/+673
| | | | | | | | | | | | | | The base opcode description now only has the parts that are used by the base recompiler front-end. CPU cores are free to define their own extensions as they see fit without being limited to pre-defined fields. The base recompiler front-end is now a template, eliminating the virtual member functions. It no longer has any dependencies on libemu, which paves the way to decoupling the recompiler front-ends and allowing the instruction analysis to be tested without the rest of the emulator. Also added a compile-time option to disable ASTAT flag update elision in the SHARC recompiler, and fixed some recompiler front-end bugs.
* cpu/drccache.cpp: Defer allocating to start, allow forcing W^X mode. (#14760) Vas Crabb2026-01-042-19/+28
| | | | | | | | | | | | | | | | | | cpu/drccache.cpp: Added helpers for allocating structures/objects in the cache. cpu/drccache.cpp: Supply desired alignment when allocating cache memory (not fully implemented). cpu/drccache.cpp: Log some statistics on destruction. emu/emuopts.cpp: Added -[no]drc_rwx option to allow forcing W^X mode when writable executable pages are permitted. cpu/mips, cpu/powerpc: Allow DRC cache size to be set externally at configuration time, so systems can override the default. cpu/dspp, cpu/e132xs, cpu/unsp: Don't allocate DRC resources if recompiler is disabled.
* cpu/sh/sh7604.cpp: fix BCR1/BCR2 and VCRDIV accessing angelosa2025-11-161-4/+25
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* srcclean and cleanup Vas Crabb2025-07-271-5/+5
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* sh/sh7604: hookup UBC BARA/BARB r/w angelosa2025-07-022-0/+90
| | | | * fix sound in 32x:aburner
* Fix for SH3/SH4 DRC regression in b26662f1bba6809df145d9e8b3f78f66e3a7c7db, ↵ smf-2025-05-071-1/+2
| | | | which prevented generate_checksum_block() being called for RAM areas. [smf]
* simulate sh3 sci transmitter emptying, fixes ↵ smf-2025-04-281-0/+5
| | | | https://github.com/mamedev/mame/issues/13634
* srcclean in preparation for release. Vas Crabb2025-04-272-18/+18
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* check correct irr0 bits, after the register size was corrected in ↵ smf-2025-04-221-4/+4
| | | | b26662f1bba6809df145d9e8b3f78f66e3a7c7db [smf]
* Implemented specific SH3/SH4 chips & pass the required endian into the ↵ smf-2025-04-1710-2066/+7423
| | | | constructor, SH4 internal registers now work when using big endian. The debugger is now aware that the SH3/SH4 has an MMU. [smf]
* misc cpu: no need to check debug enabled flag manually hap2025-04-114-8/+8
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* cpu/sh: Fixed order of operands in disassembly of MAC.L (fixes MT09114). Vas Crabb2025-02-161-1/+1
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* Demote tautological-compare to a warning again. Vas Crabb2024-11-271-3/+3
| | | | | | | clang on Windows x86-64 is getting upset about code that is making no assumptions about the relative sizes of uint64_t and long. Also, fixed more #include guards.
* dynax/dynax.cpp: Added DIP switches that are sometimes populated to Ougon no ↵ Vas Crabb2024-11-276-23/+21
| | | | | | Pai. Also fixed a bunch more #include guards.
* diexec: Add callback to allow debugger to break into the middle of wait-type ↵ AJR2024-11-172-0/+4
| | | | | | | | | | instructions whose execution time is normally indefinite. When this happens, a special message may be printed to the debug console stating the location of the last actual instruction executed before the wait (if there was one). Note that since the callback ignores the current value of the program counter, this special type of debugger break cannot be entered through breakpoints or instruction stepping commands. The callback also leaves no effect on PC history tracking or trace logs. * cpu/hd61700, cpu/tms32031: Add standard IRQ callback * cpu/m68000gen.py: Change name of invoked executable to bin/python3 * cpu/m6809: Eliminate PC "massaging" for SYNC and similar instructions
* sh_mtu: Add a forgotten update Olivier Galibert2024-10-291-0/+1
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* Added ATTR_COLD to common lifecycle methods for many files in src/devices. ↵ holub2024-09-2725-84/+84
| | | | (#12822)
* diexec: remove vestigal execute_input_lines() hap2024-09-182-2/+0
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* sh: mtu fix Olivier Galibert2024-09-141-3/+3
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* srcclean and cleanup Vas Crabb2024-05-263-42/+42
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* psr540: Start adding the floppy Olivier Galibert2024-05-131-8/+9
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* psr540: Fix midi, finish the screen mapping, add nvram Olivier Galibert2024-05-102-8/+1
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* psr540: Stop the freezing by actually running the sci channels Olivier Galibert2024-05-051-0/+2
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* hd44780: Simplify some code Olivier Galibert2024-05-051-2/+0
| | | | | sh_adc: Remove some debug stuff psr540: Add the buttons
* sh7042: Add dmac, mtu, adc, intc, sci, bsc. Separate A and non-A Olivier Galibert2024-05-0215-91/+2399
| | | | | | | | | | psr540: Add the swx00 New machines marked as MACHINE_NOT_WORKING ------------------------------------------ Yamaha MU500 [Matt, O. Galibert] Yamaha MU1000 [Matt, O. Galibert] Yamaha MU2000 [Matt, O. Galibert]
* srcclean and fix indentation in preparation for MAME 0.264 branch. Vas Crabb2024-03-245-6/+6
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* sh7042: Start introducing the interrupts Olivier Galibert2024-03-184-4/+52
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* Re-add the subcomponents to the swx00 and tweak the adc Olivier Galibert2024-03-051-1/+1
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* Enhance the sh704x. MU128 MSTO, needs interrupts now. Olivier Galibert2024-03-0310-47/+1301
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* srcclean and manual cleanup in preparation for 0.263 release. Vas Crabb2024-02-252-2/+2
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* vl1: Add a lot of stuff. Need to find where the MIDI data error is coming ↵ Olivier Galibert2024-02-191-1/+8
| | | | from though
* New machines marked as MACHINE_NOT_WORKING Olivier Galibert2024-02-184-141/+103
| | | | | ------------------------------------------ Yamaha MU128 [Matt, O. Galibert]
* mu5/15: split the lcd Olivier Galibert2024-02-105-1/+208
| | | | | | | sh7042: Start fleshing it up swx00: Same mu15: Added swp30: readd the scount increment
* New systems marked not working Ivan Vangelista2024-01-041-1/+1
| | | | | | | | | ------------------------------ Cuty Line Limited (ver.1.30) [freaktech] - igs/goldstar.cpp: enabled girls display for cmast91 and other games on same hw, removed 2nd ppi as PCB pics and readme only show one - various files: removed superfluous semicolons
* sh: start adding the sh7042 Olivier Galibert2023-12-172-0/+57
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* sh: remove prefixes Olivier Galibert2023-12-176-204/+208
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* cpu/sh/sh.cpp - Fix MAC_W regression Philip Bennett2023-10-171-2/+2
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* cpu/sh: Improved SH7021 SoC emulation. (#11610) [Ryan Holtz, Phil Bennett] Phil Bennett2023-10-1622-2196/+4594
| | | | | * Added (rudimentary) SH7021 DMA, timers and GPIO, and logging for the rest. * Fixed SH2 NMIs occurring in a delay slot when using the interpreter. * Generally cleaned up code and renamed functions/macros/variables more conventionally.
* cpu/sh: Explicitly #include prefix header (fixes GitHub #11591). Vas Crabb2023-10-032-0/+2
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* namco/namcos12.cpp: Emulated games with CDXA board. (#11558) 9871238791132023-09-2214-0/+3165
| | | | | | | | | | | | | | | * machine/t10mmc.cpp: Added support for T10SBC_CMD_SEEK_10 command. * cpu/sh: Added SH7014 SoC. * machine/icd2061a.cpp: Emulated IC Designs 2061A programmable clock generator. * sound/lc78836m.cpp: Emulated Sanyo LC78836M audio DAC. * namco/namcos12_cdxa.cpp: Emulated Namco System 12 CDXA board. Systems promoted to working ----------------------------- Truck Kyosokyoku (Japan, TKK2/VER.A) [Windy Fairy] New working systems ----------------------------- Um Jammer Lammy NOW! (Japan, UL1/VER.A) [Phil Bennett, Eric Yockey, Windy Fairy]