| Commit message (Collapse) | Author | Age | Files | Lines |
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- vcrd_w: read m_vcrd instead of m_vcrc for FOV interrupt vector
- dmaor_w: use (old & data & 6) so AE/NMIF flags can actually be cleared
- vcrb_r: mask reserved bits 15 and 7 with 0x7f7f, matching vcra/vcrc/vcrwdt
Co-authored-by: Jose Tejada <jose.tejada@analog.com>
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Only update LRU values greater than the current LRU value on cache hit
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Handle the precharge of the last active bank in the background and only
pay the penalty on a bank conflict and only pay the remainder of the
wait cycles that haven't elapsed since the last access
Update the read->write wait penalty time for dirty writeback eviction
since wcr1 should contain that value
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Fix a shift error in the wcr1 register values
Add bcr2 plumbing for determining cache line fetch reads based off BCR2.
Area 0 is set via external pins so hardcoding the cv1k value, this is
typically code space though so it only affects timing during copy of
code to main memory
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* Add cv1k SH7709S cache handling behavior for slowdown emulation
- Handles some basic caching for the sh7709s used for cv1k titles so that they run at more appropriate speeds
* sh7709s.cpp: Fix up a couple of timing handling bugs
- Use the writeback flag instead of write flag as the access to external memory is what matters for those
- Fix up the writeback buffer timing, we don't need to precharge twice for writes. Also rolled up the command costs the SDRAM region handling so the writes only need to add trwl to the penalty
- Check for burst mode availability when determining the base cycle cost, only burst ROM and sdram can use burst access to each other area requires 4 separate accesses
* sh7709s.cpp: Add some comments explaining missing/unimplemented features
- Add the non-burst timing table for WCR2
- Updates and adds a couple of extra comments related to the penalties/timing
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* Implemented short word sign extension.
* Fixed DAG2 (PM) register display in debugger.
* Track AF dependencies when analysing instructions.
* Log analysed instructions when logging UML code.
* Removed misplaced break in cpu/sharc/sharcfe.cpp.
* cpu/uml.h: Let C functions take any pointer/reference parameter.
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cpu/drcbearm64.cpp: Don't set the rounding mode on SETFMOD if it hasn't
changed.
cpu/e132xs.cpp: Skip more unnecessary flag calculations, use
pre-calculated PC for updating G0 in memory when possible, better
analysis of pre-calculated PC values when delay slots are involved.
cpu/sh: Cleaned up register dependency analysis logging, fixed an
instruction analysis bug.
cpu/sharc: Disassemble unimplemented instructions executed in recompiled
code, include tag in more fatal errors, use throw syntax to make it
cleared it's an early out.
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-cpu/powerpc: Modernised recompiler front-end code, improved instruction
analysis logging.
-cpu/sh: Cleaned up instruction analysis logging a little
-util/client_ws.hpp, util/server_ws_impl.hpp, capcom/cps2comm.cpp:
Updated some use of deprecation ASIO APIs.
-nakajima/nakajies.cpp: Use range-based loops.
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The base opcode description now only has the parts that are used by the
base recompiler front-end. CPU cores are free to define their own
extensions as they see fit without being limited to pre-defined fields.
The base recompiler front-end is now a template, eliminating the virtual
member functions. It no longer has any dependencies on libemu, which
paves the way to decoupling the recompiler front-ends and allowing the
instruction analysis to be tested without the rest of the emulator.
Also added a compile-time option to disable ASTAT flag update elision in
the SHARC recompiler, and fixed some recompiler front-end bugs.
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cpu/drccache.cpp: Added helpers for allocating structures/objects in the
cache.
cpu/drccache.cpp: Supply desired alignment when allocating cache memory
(not fully implemented).
cpu/drccache.cpp: Log some statistics on destruction.
emu/emuopts.cpp: Added -[no]drc_rwx option to allow forcing W^X mode
when writable executable pages are permitted.
cpu/mips, cpu/powerpc: Allow DRC cache size to be set externally at
configuration time, so systems can override the default.
cpu/dspp, cpu/e132xs, cpu/unsp: Don't allocate DRC resources if
recompiler is disabled.
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* fix sound in 32x:aburner
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which prevented generate_checksum_block() being called for RAM areas. [smf]
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https://github.com/mamedev/mame/issues/13634
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b26662f1bba6809df145d9e8b3f78f66e3a7c7db [smf]
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constructor, SH4 internal registers now work when using big endian. The debugger is now aware that the SH3/SH4 has an MMU. [smf]
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clang on Windows x86-64 is getting upset about code that is making no
assumptions about the relative sizes of uint64_t and long.
Also, fixed more #include guards.
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Pai.
Also fixed a bunch more #include guards.
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instructions whose execution time is normally indefinite. When this happens, a special message may be printed to the debug console stating the location of the last actual instruction executed before the wait (if there was one).
Note that since the callback ignores the current value of the program counter, this special type of debugger break cannot be entered through breakpoints or instruction stepping commands. The callback also leaves no effect on PC history tracking or trace logs.
* cpu/hd61700, cpu/tms32031: Add standard IRQ callback
* cpu/m68000gen.py: Change name of invoked executable to bin/python3
* cpu/m6809: Eliminate PC "massaging" for SYNC and similar instructions
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(#12822)
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sh_adc: Remove some debug stuff
psr540: Add the buttons
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psr540: Add the swx00
New machines marked as MACHINE_NOT_WORKING
------------------------------------------
Yamaha MU500 [Matt, O. Galibert]
Yamaha MU1000 [Matt, O. Galibert]
Yamaha MU2000 [Matt, O. Galibert]
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from though
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------------------------------------------
Yamaha MU128 [Matt, O. Galibert]
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sh7042: Start fleshing it up
swx00: Same
mu15: Added
swp30: readd the scount increment
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------------------------------
Cuty Line Limited (ver.1.30) [freaktech]
- igs/goldstar.cpp: enabled girls display for cmast91 and other games on same hw, removed 2nd ppi as PCB pics and readme only show one
- various files: removed superfluous semicolons
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* Added (rudimentary) SH7021 DMA, timers and GPIO, and logging for the rest.
* Fixed SH2 NMIs occurring in a delay slot when using the interpreter.
* Generally cleaned up code and renamed functions/macros/variables more conventionally.
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* machine/t10mmc.cpp: Added support for T10SBC_CMD_SEEK_10 command.
* cpu/sh: Added SH7014 SoC.
* machine/icd2061a.cpp: Emulated IC Designs 2061A programmable clock generator.
* sound/lc78836m.cpp: Emulated Sanyo LC78836M audio DAC.
* namco/namcos12_cdxa.cpp: Emulated Namco System 12 CDXA board.
Systems promoted to working
-----------------------------
Truck Kyosokyoku (Japan, TKK2/VER.A) [Windy Fairy]
New working systems
-----------------------------
Um Jammer Lammy NOW! (Japan, UL1/VER.A) [Phil Bennett, Eric Yockey, Windy Fairy]
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