diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/emu/cpu/m68000/68307bus.c | 59 | ||||
-rw-r--r-- | src/emu/cpu/m68000/68307bus.h | 13 | ||||
-rw-r--r-- | src/emu/cpu/m68000/68307ser.c | 175 | ||||
-rw-r--r-- | src/emu/cpu/m68000/68307ser.h | 41 | ||||
-rw-r--r-- | src/emu/cpu/m68000/68307sim.c | 2 | ||||
-rw-r--r-- | src/emu/cpu/m68000/68340sim.c | 270 | ||||
-rw-r--r-- | src/emu/cpu/m68000/68340sim.h | 54 | ||||
-rw-r--r-- | src/emu/cpu/m68000/m68000.h | 4 | ||||
-rw-r--r-- | src/emu/cpu/m68000/m68kcpu.c | 20 | ||||
-rw-r--r-- | src/mame/drivers/bfm_sc4h.c | 67 |
10 files changed, 606 insertions, 99 deletions
diff --git a/src/emu/cpu/m68000/68307bus.c b/src/emu/cpu/m68000/68307bus.c index 801c75deb6d..f551534339e 100644 --- a/src/emu/cpu/m68000/68307bus.c +++ b/src/emu/cpu/m68000/68307bus.c @@ -1,10 +1,11 @@ /* 68307 MBUS module */ +/* all ports on this are 8-bit? */ #include "emu.h" #include "m68kcpu.h" -READ16_HANDLER( m68307_internal_mbus_r ) +READ8_HANDLER( m68307_internal_mbus_r ) { m68ki_cpu_core *m68k = m68k_get_safe_token(&space->device()); m68307_mbus* mbus = m68k->m68307MBUS; @@ -15,22 +16,38 @@ READ16_HANDLER( m68307_internal_mbus_r ) int pc = cpu_get_pc(&space->device()); - switch (offset<<1) + switch (offset) { + case m68307BUS_MADR: + logerror("%08x m68307_internal_mbus_r %08x (MADR - M-Bus Address Register)\n", pc, offset); + return space->machine().rand(); + + case m68307BUS_MFDR: + logerror("%08x m68307_internal_mbus_r %08x (MFDR - M-Bus Frequency Divider Register)\n", pc, offset); + return space->machine().rand(); + + case m68307BUS_MBCR: + logerror("%08x m68307_internal_mbus_r %08x (MFDR - M-Bus Control Register)\n", pc, offset); + return space->machine().rand(); + case m68307BUS_MBSR: - logerror("%08x m68307_internal_mbus_r %08x, (%04x) (MBSR - Status Register)\n", pc, offset*2,mem_mask); + logerror("%08x m68307_internal_mbus_r %08x (MBSR - M-Bus Status Register)\n", pc, offset); + return space->machine().rand(); + + case m68307BUS_MBDR: + logerror("%08x m68307_internal_mbus_r %08x (MBDR - M-Bus Data I/O Register)\n", pc, offset); return space->machine().rand(); default: - logerror("%08x m68307_internal_mbus_r %08x, (%04x)\n", pc, offset*2,mem_mask); - return 0x0000; + logerror("%08x m68307_internal_mbus_r %08x (UNKNOWN / ILLEGAL)\n", pc, offset); + return 0x00; } } - return 0xffff; + return 0xff; } -WRITE16_HANDLER( m68307_internal_mbus_w ) +WRITE8_HANDLER( m68307_internal_mbus_w ) { m68ki_cpu_core *m68k = m68k_get_safe_token(&space->device()); m68307_mbus* mbus = m68k->m68307MBUS; @@ -39,7 +56,33 @@ WRITE16_HANDLER( m68307_internal_mbus_w ) if (mbus) { int pc = cpu_get_pc(&space->device()); - logerror("%08x m68307_internal_mbus_w %08x, %04x (%04x)\n", pc, offset*2,data,mem_mask); + + switch (offset) + { + case m68307BUS_MADR: + logerror("%08x m68307_internal_mbus_w %08x, %02x (MADR - M-Bus Address Register)\n", pc, offset,data); + break; + + case m68307BUS_MFDR: + logerror("%08x m68307_internal_mbus_w %08x, %02x (MFDR - M-Bus Frequency Divider Register)\n", pc, offset,data); + break; + + case m68307BUS_MBCR: + logerror("%08x m68307_internal_mbus_w %08x, %02x (MFDR - M-Bus Control Register)\n", pc, offset,data); + break; + + case m68307BUS_MBSR: + logerror("%08x m68307_internal_mbus_w %08x, %02x (MBSR - M-Bus Status Register)\n", pc, offset,data); + break; + + case m68307BUS_MBDR: + logerror("%08x m68307_internal_mbus_w %08x, %02x (MBDR - M-Bus Data I/O Register)\n", pc, offset,data); + break; + + default: + logerror("%08x m68307_internal_mbus_w %08x, %02x (UNKNOWN / ILLEGAL)\n", pc, offset,data); + break; + } } } diff --git a/src/emu/cpu/m68000/68307bus.h b/src/emu/cpu/m68000/68307bus.h index 201aabe01f4..afce7467c0a 100644 --- a/src/emu/cpu/m68000/68307bus.h +++ b/src/emu/cpu/m68000/68307bus.h @@ -1,8 +1,11 @@ - -#define m68307BUS_MBSR (0x06) - -READ16_HANDLER( m68307_internal_mbus_r ); -WRITE16_HANDLER( m68307_internal_mbus_w ); +#define m68307BUS_MADR (0x01) +#define m68307BUS_MFDR (0x03) +#define m68307BUS_MBCR (0x05) +#define m68307BUS_MBSR (0x07) +#define m68307BUS_MBDR (0x09) + +READ8_HANDLER( m68307_internal_mbus_r ); +WRITE8_HANDLER( m68307_internal_mbus_w ); class m68307_mbus { diff --git a/src/emu/cpu/m68000/68307ser.c b/src/emu/cpu/m68000/68307ser.c index b1be95379bb..3d71f3f6a1f 100644 --- a/src/emu/cpu/m68000/68307ser.c +++ b/src/emu/cpu/m68000/68307ser.c @@ -1,10 +1,19 @@ /* 68307 SERIAL Module */ +/* all ports on this are 8-bit? */ + +/* this is a 68681 'compatible' chip but with only a single channel implemented + (writes to the other channel have no effects) + + for now at least we piggyback on the existing 68307 emulation rather than having + a custom verson here, that may change later if subtle differences exist. + +*/ #include "emu.h" #include "m68kcpu.h" -READ16_HANDLER( m68307_internal_serial_r ) +READ8_HANDLER( m68307_internal_serial_r ) { m68ki_cpu_core *m68k = m68k_get_safe_token(&space->device()); m68307_serial* serial = m68k->m68307SERIAL; @@ -12,32 +21,77 @@ READ16_HANDLER( m68307_internal_serial_r ) if (serial) { - int pc = cpu_get_pc(&space->device()); - - switch (offset<<1) + // if we're piggybacking on the existing 68681 implementation... + if (serial->m_duart68681) + { + if (offset&1) return duart68681_r(serial->m_duart68681, offset>>1); + } + else { - case m68307SER_USR_UCSR: - logerror("%08x m68307_internal_serial_r %08x, (%04x) (USR - Status Register)\n", pc, offset*2,mem_mask); - return space->machine().rand(); - - case m68307SER_URB_UTB: - logerror("%08x m68307_internal_serial_r %08x, (%04x) (URB - Recieve Buffer)\n", pc, offset*2,mem_mask); - return 0xff;//space->machine().rand(); - - case m68307SER_UISR_UIMR: - logerror("%08x m68307_internal_serial_r %08x, (%04x) (UISR - Interrupt Status Register)\n", pc, offset*2,mem_mask); - return space->machine().rand() & 0x87; - default: - logerror("%08x m68307_internal_serial_r %08x, (%04x)\n", pc, offset*2,mem_mask); - break; + int pc = cpu_get_pc(&space->device()); + + switch (offset) + { + case m68307SER_UMR1_UMR2: + logerror("%08x m68307_internal_serial_r %08x (UMR1, UMR2 - UART Mode Register)\n", pc, offset); + return space->machine().rand(); + + case m68307SER_USR_UCSR: + logerror("%08x m68307_internal_serial_r %08x (USR, UCSR - UART Status/Clock Select Register)\n", pc, offset); + return space->machine().rand(); + + case m68307SER_UCR: + logerror("%08x m68307_internal_serial_r %08x (UCR - UART Command Register)\n", pc, offset); + return space->machine().rand(); + + case m68307SER_URB_UTB: + logerror("%08x m68307_internal_serial_r %08x (URB, UTB - UART Recieve/Transmit Buffer)\n", pc, offset); + return 0xff;//space->machine().rand(); + + case m68307SER_UIPCR_UACR: + logerror("%08x m68307_internal_serial_r %08x (UIPCR, UACR - UART Input Port Change Register / UART Control Register)\n", pc, offset); + return 0xff;//space->machine().rand(); + + case m68307SER_UISR_UIMR: + logerror("%08x m68307_internal_serial_r %08x (UISR, UIMR - UART Interrupt Status Register / UART Interrupt Mask Register)\n", pc, offset); + return space->machine().rand() & 0x87; + + case m68307SER_UBG1: + logerror("%08x m68307_internal_serial_r %08x (UBG1 - UART Baud Rate Gen. Precaler MSB)\n", pc, offset); + return space->machine().rand() & 0x87; + + case m68307SER_UBG2: + logerror("%08x m68307_internal_serial_r %08x (UBG1 - UART Baud Rate Gen. Precaler LSB)\n", pc, offset); + return space->machine().rand() & 0x87; + + case m68307SER_UIVR: + logerror("%08x m68307_internal_serial_r %08x (UIVR - UART Interrupt Vector Register)\n", pc, offset); + return space->machine().rand() & 0x87; + + case m68307SER_UIP: + logerror("%08x m68307_internal_serial_r %08x (UIP - UART Register Input Port)\n", pc, offset); + return space->machine().rand() & 0x87; + + case m68307SER_UOP1: + logerror("%08x m68307_internal_serial_r %08x (UOP1 - UART Output Port Bit Set Cmd)\n", pc, offset); + return space->machine().rand() & 0x87; + + case m68307SER_UOP0: + logerror("%08x m68307_internal_serial_r %08x (UOP0 - UART Output Port Bit Reset Cmd)\n", pc, offset); + return space->machine().rand() & 0x87; + + default: + logerror("%08x m68307_internal_serial_r %08x (UNKNOWN / ILLEGAL)\n", pc, offset); + break; + } } } return 0x0000; } -WRITE16_HANDLER( m68307_internal_serial_w ) +WRITE8_HANDLER( m68307_internal_serial_w ) { m68ki_cpu_core *m68k = m68k_get_safe_token(&space->device()); m68307_serial* serial = m68k->m68307SERIAL; @@ -47,29 +101,70 @@ WRITE16_HANDLER( m68307_internal_serial_w ) if (serial) { - switch (offset<<1) + // if we're piggybacking on the existing 68681 implementation... + if (serial->m_duart68681) { - case m68307SER_USR_UCSR: - logerror("%08x m68307_internal_serial_r %08x, (%04x) (UCSR - Clock Select Register)\n", pc, offset*2,mem_mask); - break; - - case m68307SER_URB_UTB: - logerror("%08x m68307_internal_serial_w %08x, %04x (%04x) (UTB - Transmit Buffer)\n", pc, offset*2,data,mem_mask); - break; - - case m68307SER_UISR_UIMR: - logerror("%08x m68307_internal_serial_w %08x, %04x (%04x) (UIMR - Interrupt Mask Register)\n", pc, offset*2,data,mem_mask); - break; - - case m68307SER_UIVR: - logerror("%08x m68307_internal_serial_w %08x, %04x (%04x) (UIVR - Interrupt Vector Register)\n", pc, offset*2,data,mem_mask); - COMBINE_DATA(&serial->m_uivr); - break; - - default: - logerror("%08x m68307_internal_serial_w %08x, %04x (%04x)\n", pc, offset*2,data,mem_mask); + if (offset&1) duart68681_w(serial->m_duart68681, offset>>1, data); + } + else + { + switch (offset) + { + case m68307SER_UMR1_UMR2: + logerror("%08x m68307_internal_serial_w %08x, %02x (UMR1, UMR2 - UART Mode Register)\n", pc, offset,data); + break; + + case m68307SER_USR_UCSR: + logerror("%08x m68307_internal_serial_w %08x, %02x (UCSR - Clock Select Register)\n", pc, offset,data); + break; + + case m68307SER_UCR: + logerror("%08x m68307_internal_serial_w %08x, %02x (UCR - UART Command Register)\n", pc, offset,data); + break; + + case m68307SER_URB_UTB: + logerror("%08x m68307_internal_serial_w %08x, %02x (UTB - Transmit Buffer)\n", pc, offset,data); + break; + + case m68307SER_UIPCR_UACR: + logerror("%08x m68307_internal_serial_w %08x, %02x (UIPCR, UACR - UART Input Port Change Register / UART Control Register)\n", pc, offset,data); + break; + + case m68307SER_UISR_UIMR: + logerror("%08x m68307_internal_serial_w %08x, %02x (UIMR - Interrupt Mask Register)\n", pc, offset,data); + break; + + case m68307SER_UBG1: + logerror("%08x m68307_internal_serial_w %08x, %02x (UBG1 - UART Baud Rate Gen. Precaler MSB)\n", pc, offset,data); + break; + + case m68307SER_UBG2: + logerror("%08x m68307_internal_serial_w %08x, %02x (UBG1 - UART Baud Rate Gen. Precaler LSB)\n", pc, offset,data); + break; + + case m68307SER_UIVR: + logerror("%08x m68307_internal_serial_w %08x, %02x (UIVR - Interrupt Vector Register)\n", pc, offset,data); + serial->m_uivr = data; + break; + + case m68307SER_UIP: + logerror("%08x m68307_internal_serial_w %08x, %02x (UIP - UART Register Input Port)\n", pc, offset,data); + break; + + case m68307SER_UOP1: + logerror("%08x m68307_internal_serial_w %08x, %02x (UOP1 - UART Output Port Bit Set Cmd)\n", pc, offset,data); + break; + + case m68307SER_UOP0: + logerror("%08x m68307_internal_serial_w %08x, %02x (UOP0 - UART Output Port Bit Reset Cmd)\n", pc, offset,data); + break; + + + default: + logerror("%08x m68307_internal_serial_w %08x, %02x (UNKNOWN / ILLEGAL)\n", pc, offset,data); + break; + } } - } } diff --git a/src/emu/cpu/m68000/68307ser.h b/src/emu/cpu/m68000/68307ser.h index 27fbbf33382..52c4c27046a 100644 --- a/src/emu/cpu/m68000/68307ser.h +++ b/src/emu/cpu/m68000/68307ser.h @@ -1,20 +1,37 @@ - -#define m68307SER_USR_UCSR (0x02) -#define m68307SER_URB_UTB (0x06) - -#define m68307SER_UISR_UIMR (0x0a) - -#define m68307SER_UIVR (0x18) - - -READ16_HANDLER( m68307_internal_serial_r ); -WRITE16_HANDLER( m68307_internal_serial_w ); +#include "machine/68681.h" + +#define m68307SER_UMR1_UMR2 (0x01) +#define m68307SER_USR_UCSR (0x03) +#define m68307SER_UCR (0x05) +#define m68307SER_URB_UTB (0x07) +#define m68307SER_UIPCR_UACR (0x09) +#define m68307SER_UISR_UIMR (0x0b) +#define m68307SER_UBG1 (0x0d) +#define m68307SER_UBG2 (0x0f) +// (0x11) +// (0x13) +// (0x15) +// (0x17) +#define m68307SER_UIVR (0x19) +#define m68307SER_UIP (0x1b) +#define m68307SER_UOP1 (0x1d) +#define m68307SER_UOP0 (0x1f) + + +READ8_HANDLER( m68307_internal_serial_r ); +WRITE8_HANDLER( m68307_internal_serial_w ); class m68307_serial { public: void reset(void); - UINT16 m_uivr; + UINT8 m_uivr; + + void m68307ser_set_duart68681(device_t* duart68681) + { + m_duart68681 = duart68681; + } + device_t* m_duart68681; }; diff --git a/src/emu/cpu/m68000/68307sim.c b/src/emu/cpu/m68000/68307sim.c index 302ae4a9ea3..2a59b39c562 100644 --- a/src/emu/cpu/m68000/68307sim.c +++ b/src/emu/cpu/m68000/68307sim.c @@ -37,10 +37,10 @@ READ16_HANDLER( m68307_internal_sim_r ) } } - return 0x0000; } + WRITE16_HANDLER( m68307_internal_sim_w ) { m68ki_cpu_core *m68k = m68k_get_safe_token(&space->device()); diff --git a/src/emu/cpu/m68000/68340sim.c b/src/emu/cpu/m68000/68340sim.c index e5f20f0d6c6..4f8089142f8 100644 --- a/src/emu/cpu/m68000/68340sim.c +++ b/src/emu/cpu/m68000/68340sim.c @@ -13,12 +13,134 @@ READ16_HANDLER( m68340_internal_sim_r ) if (sim) { int pc = cpu_get_pc(&space->device()); - logerror("%08x m68340_internal_sim_r %04x, (%04x)\n", pc, offset*2,mem_mask); + + switch (offset<<1) + { + case m68340SIM_MCR: + logerror("%08x m68340_internal_sim_r %04x, (%04x) (MCR - Module Configuration Register)\n", pc, offset*2,mem_mask); + return space->machine().rand(); + + case m68340SIM_SYNCR: + logerror("%08x m68340_internal_sim_r %04x, (%04x) (SYNCR - Clock Synthesizer Register)\n", pc, offset*2,mem_mask); + return space->machine().rand(); + + case m68340SIM_AVR_RSR: + logerror("%08x m68340_internal_sim_r %04x, (%04x) (AVR, RSR - Auto Vector Register, Reset Status Register)\n", pc, offset*2,mem_mask); + return space->machine().rand(); + + case m68340SIM_SWIV_SYPCR: + logerror("%08x m68340_internal_sim_r %04x, (%04x) (SWIV_SYPCR - Software Interrupt Vector, System Protection Control Register)\n", pc, offset*2,mem_mask); + return space->machine().rand(); + + case m68340SIM_PICR: + logerror("%08x m68340_internal_sim_r %04x, (%04x) (PICR - Periodic Interrupt Control Register)\n", pc, offset*2,mem_mask); + return space->machine().rand(); + + case m68340SIM_PITR: + logerror("%08x m68340_internal_sim_r %04x, (%04x) (PITR - Periodic Interrupt Timer Register)\n", pc, offset*2,mem_mask); + return space->machine().rand(); + + case m68340SIM_SWSR: + logerror("%08x m68340_internal_sim_r %04x, (%04x) (SWSR - Software Service)\n", pc, offset*2,mem_mask); + return space->machine().rand(); + + default: + logerror("%08x m68340_internal_sim_r %04x, (%04x)\n", pc, offset*2,mem_mask); + + + } } return 0x0000; } +READ8_HANDLER( m68340_internal_sim_ports_r ) +{ + offset += 0x10; + m68ki_cpu_core *m68k = m68k_get_safe_token(&space->device()); + m68340_sim* sim = m68k->m68340SIM; + assert(sim != NULL); + + if (sim) + { + int pc = cpu_get_pc(&space->device()); + + switch (offset) + { + case m68340SIM_PORTA: + logerror("%08x m68340_internal_sim_r %04x (PORTA - Port A Data)\n", pc, offset); + return space->machine().rand(); + + case m68340SIM_DDRA: + logerror("%08x m68340_internal_sim_r %04x (DDRA - Port A Data Direction)\n", pc, offset); + return space->machine().rand(); + + case m68340SIM_PPRA1: + logerror("%08x m68340_internal_sim_r %04x (PPRA1 - Port A Pin Assignment 1)\n", pc, offset); + return space->machine().rand(); + + case m68340SIM_PPRA2: + logerror("%08x m68340_internal_sim_r %04x (PPRA2 - Port A Pin Assignment 2)\n", pc, offset); + return space->machine().rand(); + + case m68340SIM_PORTB: + logerror("%08x m68340_internal_sim_r %04x (PORTB - Port B Data 0)\n", pc, offset); + return space->machine().rand(); + + case m68340SIM_PORTB1: + logerror("%08x m68340_internal_sim_r %04x (PORTB1 - Port B Data 1)\n", pc, offset); + return space->machine().rand(); + + case m68340SIM_DDRB: + logerror("%08x m68340_internal_sim_r %04x (DDR - Port B Data Direction)\n", pc, offset); + return space->machine().rand(); + + case m68340SIM_PPARB: + logerror("%08x m68340_internal_sim_r %04x (PPARB - Port B Pin Assignment)\n", pc, offset); + return space->machine().rand(); + + default: + logerror("%08x m68340_internal_sim_r %04x (ILLEGAL?)\n", pc, offset); + return space->machine().rand(); + + } + } + + return 0x00; +} + +READ32_HANDLER( m68340_internal_sim_cs_r ) +{ + offset += m68340SIM_AM_CS0>>2; + + m68ki_cpu_core *m68k = m68k_get_safe_token(&space->device()); + m68340_sim* sim = m68k->m68340SIM; + assert(sim != NULL); + + if (sim) + { + int pc = cpu_get_pc(&space->device()); + + switch (offset<<2) + { + case m68340SIM_AM_CS0: return sim->m_am[0]; + case m68340SIM_BA_CS0: return sim->m_ba[0]; + case m68340SIM_AM_CS1: return sim->m_am[1]; + case m68340SIM_BA_CS1: return sim->m_ba[1]; + case m68340SIM_AM_CS2: return sim->m_am[2]; + case m68340SIM_BA_CS2: return sim->m_ba[2]; + case m68340SIM_AM_CS3: return sim->m_am[3]; + case m68340SIM_BA_CS3: return sim->m_ba[3]; + + default: + logerror("%08x m68340_internal_sim_r %08x, (%08x)\n", pc, offset*4,mem_mask); + + } + } + + return 0x00000000; +} + WRITE16_HANDLER( m68340_internal_sim_w ) { m68ki_cpu_core *m68k = m68k_get_safe_token(&space->device()); @@ -28,10 +150,154 @@ WRITE16_HANDLER( m68340_internal_sim_w ) if (sim) { int pc = cpu_get_pc(&space->device()); - logerror("%08x m68340_internal_sim_w %04x, %04x (%04x)\n", pc, offset*2,data,mem_mask); + + switch (offset<<1) + { + case m68340SIM_MCR: + logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (MCR - Module Configuration Register)\n", pc, offset*2,data,mem_mask); + break; + + case m68340SIM_SYNCR: + logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (SYNCR - Clock Synthesizer Register)\n", pc, offset*2,data,mem_mask); + break; + + + case m68340SIM_AVR_RSR: + logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (AVR, RSR - Auto Vector Register, Reset Status Register)\n", pc, offset*2,data,mem_mask); + break; + + case m68340SIM_SWIV_SYPCR: + logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (SWIV_SYPCR - Software Interrupt Vector, System Protection Control Register)\n", pc, offset*2,data,mem_mask); + break; + + case m68340SIM_PICR: + logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (PICR - Periodic Interrupt Control Register)\n", pc, offset*2,data,mem_mask); + break; + + case m68340SIM_PITR: + logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (PITR - Periodic Interrupt Timer Register)\n", pc, offset*2,data,mem_mask); + break; + + case m68340SIM_SWSR: + // basically watchdog, you must write an alternating pattern of 0x55 / 0xaa to keep the watchdog from resetting the system + //logerror("%08x m68340_internal_sim_w %04x, %04x (%04x) (SWSR - Software Service)\n", pc, offset*2,data,mem_mask); + break; + + default: + logerror("%08x m68340_internal_sim_w %04x, %04x (%04x)\n", pc, offset*2,data,mem_mask); + + } + } +} + +WRITE8_HANDLER( m68340_internal_sim_ports_w ) +{ + offset += 0x10; + m68ki_cpu_core *m68k = m68k_get_safe_token(&space->device()); + m68340_sim* sim = m68k->m68340SIM; + assert(sim != NULL); + + if (sim) + { + int pc = cpu_get_pc(&space->device()); + + switch (offset) + { + case m68340SIM_PORTA: + logerror("%08x m68340_internal_sim_w %04x, %02x (PORTA - Port A Data)\n", pc, offset,data); + break; + + case m68340SIM_DDRA: + logerror("%08x m68340_internal_sim_w %04x, %02x (DDRA - Port A Data Direction)\n", pc, offset,data); + break; + + case m68340SIM_PPRA1: + logerror("%08x m68340_internal_sim_w %04x, %02x (PPRA1 - Port A Pin Assignment 1)\n", pc, offset,data); + break; + + case m68340SIM_PPRA2: + logerror("%08x m68340_internal_sim_w %04x, %02x (PPRA2 - Port A Pin Assignment 2)\n", pc, offset,data); + break; + + case m68340SIM_PORTB: + logerror("%08x m68340_internal_sim_w %04x, %02x (PORTB - Port B Data)\n", pc, offset,data); + break; + + case m68340SIM_PORTB1: + logerror("%08x m68340_internal_sim_w %04x, %02x (PORTB1 - Port B Data - mirror)\n", pc, offset,data); + break; + + case m68340SIM_DDRB: + logerror("%08x m68340_internal_sim_w %04x, %02x (DDR - Port B Data Direction)\n", pc, offset,data); + break; + + case m68340SIM_PPARB: + logerror("%08x m68340_internal_sim_w %04x, %02x (PPARB - Port B Pin Assignment)\n", pc, offset,data); + break; + + default: + logerror("%08x m68340_internal_sim_w %04x, %02x (ILLEGAL?)\n", pc, offset,data); + break; + + } } } +WRITE32_HANDLER( m68340_internal_sim_cs_w ) +{ + offset += m68340SIM_AM_CS0>>2; + m68ki_cpu_core *m68k = m68k_get_safe_token(&space->device()); + m68340_sim* sim = m68k->m68340SIM; + assert(sim != NULL); + + if (sim) + { + int pc = cpu_get_pc(&space->device()); + + switch (offset<<2) + { + case m68340SIM_AM_CS0: + COMBINE_DATA(&sim->m_am[0]); + break; + + case m68340SIM_BA_CS0: + COMBINE_DATA(&sim->m_ba[0]); + break; + + case m68340SIM_AM_CS1: + COMBINE_DATA(&sim->m_am[1]); + break; + + case m68340SIM_BA_CS1: + COMBINE_DATA(&sim->m_ba[1]); + break; + + case m68340SIM_AM_CS2: + COMBINE_DATA(&sim->m_am[2]); + break; + + case m68340SIM_BA_CS2: + COMBINE_DATA(&sim->m_ba[2]); + break; + + case m68340SIM_AM_CS3: + COMBINE_DATA(&sim->m_am[3]); + break; + + case m68340SIM_BA_CS3: + COMBINE_DATA(&sim->m_ba[3]); + break; + + default: + logerror("%08x m68340_internal_sim_w %08x, %08x (%08x)\n", pc, offset*4,data,mem_mask); + break; + + } + } + +} + + void m68340_sim::reset(void) { diff --git a/src/emu/cpu/m68000/68340sim.h b/src/emu/cpu/m68000/68340sim.h index 5999cbd6b84..04efd1030a6 100644 --- a/src/emu/cpu/m68000/68340sim.h +++ b/src/emu/cpu/m68000/68340sim.h @@ -1,10 +1,64 @@ +#define m68340SIM_MCR (0x00) +// (0x02) +#define m68340SIM_SYNCR (0x04) +#define m68340SIM_AVR_RSR (0x06) +// (0x08) +// (0x0a) +// (0x0c) +// (0x0e) +#define m68340SIM_PORTA (0x11) +#define m68340SIM_DDRA (0x13) +#define m68340SIM_PPRA1 (0x15) +#define m68340SIM_PPRA2 (0x17) +#define m68340SIM_PORTB (0x19) +#define m68340SIM_PORTB1 (0x1b) +#define m68340SIM_DDRB (0x1d) +#define m68340SIM_PPARB (0x1f) +#define m68340SIM_SWIV_SYPCR (0x20) +#define m68340SIM_PICR (0x22) +#define m68340SIM_PITR (0x24) +#define m68340SIM_SWSR (0x26) +// (0x28) +// (0x2a) +// (0x2c) +// (0x2e) +// (0x30) +// (0x32) +// (0x34) +// (0x36) +// (0x38) +// (0x3a) +// (0x3c) +// (0x3e) +#define m68340SIM_AM_CS0 (0x40) +#define m68340SIM_BA_CS0 (0x44) +#define m68340SIM_AM_CS1 (0x48) +#define m68340SIM_BA_CS1 (0x4c) +#define m68340SIM_AM_CS2 (0x50) +#define m68340SIM_BA_CS2 (0x54) +#define m68340SIM_AM_CS3 (0x58) +#define m68340SIM_BA_CS3 (0x5c) + + READ16_HANDLER( m68340_internal_sim_r ); WRITE16_HANDLER( m68340_internal_sim_w ); +READ32_HANDLER( m68340_internal_sim_cs_r ); +WRITE32_HANDLER( m68340_internal_sim_cs_w ); +READ8_HANDLER( m68340_internal_sim_ports_r ); +WRITE8_HANDLER( m68340_internal_sim_ports_w ); + + + class m68340_sim { public: + + UINT32 m_am[4]; + UINT32 m_ba[4]; + + void reset(void); }; diff --git a/src/emu/cpu/m68000/m68000.h b/src/emu/cpu/m68000/m68000.h index 90e870fe70f..e1c6dcc9405 100644 --- a/src/emu/cpu/m68000/m68000.h +++ b/src/emu/cpu/m68000/m68000.h @@ -145,11 +145,11 @@ UINT16 m68307_get_cs(device_t *device, offs_t address); void m68307_set_interrupt(device_t *device, int level, int vector); void m68307_timer0_interrupt(legacy_cpu_device *cpudev); void m68307_timer1_interrupt(legacy_cpu_device *cpudev); -void m68307_serial_interrupt(legacy_cpu_device *cpudev); +void m68307_serial_interrupt(legacy_cpu_device *cpudev, int vector); void m68307_mbus_interrupt(legacy_cpu_device *cpudev); void m68307_licr2_interrupt(legacy_cpu_device *cpudev); - +void m68307_set_duart68681(device_t* cpudev, device_t* duart68681); typedef int (*instruction_hook_t)(device_t *device, offs_t curpc); void m68k_set_instruction_hook(device_t *device, instruction_hook_t ihook); diff --git a/src/emu/cpu/m68000/m68kcpu.c b/src/emu/cpu/m68000/m68kcpu.c index 487ad52be23..6322da6ed48 100644 --- a/src/emu/cpu/m68000/m68kcpu.c +++ b/src/emu/cpu/m68000/m68kcpu.c @@ -1790,6 +1790,15 @@ void m68307_set_port_callbacks(device_t *device, m68307_porta_read_callback port m68k->m_m68307_portb_w = portb_w; } +void m68307_set_duart68681(device_t* cpudev, device_t* duart68681) +{ + m68ki_cpu_core *m68k = m68k_get_safe_token(cpudev); + if (m68k->m68307SERIAL) + m68k->m68307SERIAL->m68307ser_set_duart68681(duart68681); +} + + + UINT16 m68307_get_cs(device_t *device, offs_t address) { @@ -1954,11 +1963,10 @@ void m68307_timer1_interrupt(legacy_cpu_device *cpudev) m68307_set_interrupt(cpudev, prioritylevel, vector); } -void m68307_serial_interrupt(legacy_cpu_device *cpudev) +void m68307_serial_interrupt(legacy_cpu_device *cpudev, int vector) { m68ki_cpu_core* m68k = m68k_get_safe_token(cpudev); int prioritylevel = (m68k->m68307SIM->m_picr & 0x0070)>>4; - int vector = (m68k->m68307SERIAL->m_uivr); m68307_set_interrupt(cpudev, prioritylevel, vector); } @@ -2063,9 +2071,9 @@ static WRITE16_HANDLER( m68307_internal_base_w ) //mask = (m68k->m68307_base & 0xe000) >> 13; //if ( m68k->m68307_base & 0x1000 ) mask |= 7; m68k->internal->install_legacy_readwrite_handler(base + 0x000, base + 0x04f, FUNC(m68307_internal_sim_r), FUNC(m68307_internal_sim_w)); - m68k->internal->install_legacy_readwrite_handler(base + 0x100, base + 0x11f, FUNC(m68307_internal_serial_r), FUNC(m68307_internal_serial_w)); + m68k->internal->install_legacy_readwrite_handler(base + 0x100, base + 0x11f, FUNC(m68307_internal_serial_r), FUNC(m68307_internal_serial_w), 0xffff); m68k->internal->install_legacy_readwrite_handler(base + 0x120, base + 0x13f, FUNC(m68307_internal_timer_r), FUNC(m68307_internal_timer_w)); - m68k->internal->install_legacy_readwrite_handler(base + 0x140, base + 0x149, FUNC(m68307_internal_mbus_r), FUNC(m68307_internal_mbus_w)); + m68k->internal->install_legacy_readwrite_handler(base + 0x140, base + 0x149, FUNC(m68307_internal_mbus_r), FUNC(m68307_internal_mbus_w), 0xffff); break; @@ -2741,7 +2749,9 @@ static WRITE32_HANDLER( m68340_internal_base_w ) { int base = m68k->m68340_base & 0xfffff000; - m68k->internal->install_legacy_readwrite_handler(base + 0x000, base + 0x05f, FUNC(m68340_internal_sim_r), FUNC(m68340_internal_sim_w),0xffffffff); + m68k->internal->install_legacy_readwrite_handler(base + 0x000, base + 0x03f, FUNC(m68340_internal_sim_r), FUNC(m68340_internal_sim_w),0xffffffff); + m68k->internal->install_legacy_readwrite_handler(base + 0x010, base + 0x01f, FUNC(m68340_internal_sim_ports_r), FUNC(m68340_internal_sim_ports_w),0xffffffff); + m68k->internal->install_legacy_readwrite_handler(base + 0x040, base + 0x05f, FUNC(m68340_internal_sim_cs_r), FUNC(m68340_internal_sim_cs_w)); m68k->internal->install_legacy_readwrite_handler(base + 0x600, base + 0x67f, FUNC(m68340_internal_timer_r), FUNC(m68340_internal_timer_w)); m68k->internal->install_legacy_readwrite_handler(base + 0x700, base + 0x723, FUNC(m68340_internal_serial_r), FUNC(m68340_internal_serial_w)); m68k->internal->install_legacy_readwrite_handler(base + 0x780, base + 0x7bf, FUNC(m68340_internal_dma_r), FUNC(m68340_internal_dma_w)); diff --git a/src/mame/drivers/bfm_sc4h.c b/src/mame/drivers/bfm_sc4h.c index 311fc2b8ee5..d111ca8cbd1 100644 --- a/src/mame/drivers/bfm_sc4h.c +++ b/src/mame/drivers/bfm_sc4h.c @@ -444,6 +444,8 @@ static MACHINE_START( sc4 ) bfm_sc4_68307_porta_w, bfm_sc4_68307_portb_r, bfm_sc4_68307_portb_w ); + m68307_set_duart68681(machine.device("maincpu"),machine.device("m68307_68681")); + BFM_BD1_init(0); int reels = 6; @@ -521,40 +523,55 @@ static const duart68681_config bfm_sc4_duart68681_config = bfm_sc4_duart_output_w }; -// generate some fake interrupts for force things to go a bit further -// until we have the peripheral hookups working.. -static INTERRUPT_GEN( sc4_fake_int_check ) -{ - int which_int = 0; - static int count = 0; - count++; - if (count>30000) +void m68307_duart_irq_handler(device_t *device, UINT8 vector) +{ + printf("m68307_duart_irq_handler\n"); + m68307_serial_interrupt((legacy_cpu_device*)device->machine().device("maincpu"), vector); +}; + +void m68307_duart_tx(device_t *device, int channel, UINT8 data) +{ + if (channel==0) { - which_int = device->machine().rand() % 5; - - /* - if ( device->machine().input().code_pressed_once(KEYCODE_Q) ) which_int = 1; - if ( device->machine().input().code_pressed_once(KEYCODE_W) ) which_int = 2; - if ( device->machine().input().code_pressed_once(KEYCODE_E) ) which_int = 3; - if ( device->machine().input().code_pressed_once(KEYCODE_R) ) which_int = 4; - if ( device->machine().input().code_pressed_once(KEYCODE_T) ) which_int = 5; - */ - - //if (which_int==1) m68307_timer0_interrupt((legacy_cpu_device*)device->machine().device("maincpu")); - //if (which_int==2) m68307_timer1_interrupt((legacy_cpu_device*)device->machine().device("maincpu")); - if (which_int==3) m68307_serial_interrupt((legacy_cpu_device*)device->machine().device("maincpu")); - //if (which_int==4) m68307_mbus_interrupt((legacy_cpu_device*)device->machine().device("maincpu")); - // if (which_int==5) m68307_licr2_interrupt((legacy_cpu_device*)device->machine().device("maincpu")); + printf("m68307_duart_tx %02x\n",data); } + else + { + printf("(illegal channel 1) m68307_duart_tx %02x\n",data); + } +}; + +UINT8 m68307_duart_input_r(device_t *device) +{ + printf("m68307_duart_input_r\n"); + return 0x00; } +void m68307_duart_output_w(device_t *device, UINT8 data) +{ + printf("m68307_duart_output_w %02x\n", data); +} + + + +static const duart68681_config m68307_duart68681_config = +{ + m68307_duart_irq_handler, + m68307_duart_tx, + m68307_duart_input_r, + m68307_duart_output_w +}; + + MACHINE_CONFIG_START( sc4, sc4_state ) MCFG_CPU_ADD("maincpu", M68307, 16000000) // 68307! (EC000 core) MCFG_CPU_PROGRAM_MAP(sc4_map) - MCFG_CPU_PERIODIC_INT(sc4_fake_int_check,1000) + + // internal duart of the 68307... paired in machine start + MCFG_DUART68681_ADD("m68307_68681", 16000000/4, m68307_duart68681_config) // ?? Mhz MCFG_MACHINE_START( sc4 ) MCFG_MACHINE_RESET( sc4 ) @@ -562,6 +579,8 @@ MACHINE_CONFIG_START( sc4, sc4_state ) /* sound hardware */ MCFG_SPEAKER_STANDARD_MONO("mono") + + MCFG_DUART68681_ADD("duart68681", 16000000/4, bfm_sc4_duart68681_config) // ?? Mhz |