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-rw-r--r--src/emu/cpu/i86/ea.h53
-rw-r--r--src/emu/cpu/i86/i286.c422
-rw-r--r--src/emu/cpu/i86/i86.c385
-rw-r--r--src/emu/cpu/i86/i86.h110
-rw-r--r--src/emu/cpu/i86/i86mem.c24
-rw-r--r--src/emu/cpu/i86/instr186.c104
-rw-r--r--src/emu/cpu/i86/instr186.h34
-rw-r--r--src/emu/cpu/i86/instr286.c260
-rw-r--r--src/emu/cpu/i86/instr286.h18
-rw-r--r--src/emu/cpu/i86/instr86.c1538
-rw-r--r--src/emu/cpu/i86/instr86.h454
-rw-r--r--src/emu/cpu/i86/instrv30.c1311
-rw-r--r--src/emu/cpu/i86/instrv30.h7
-rw-r--r--src/emu/cpu/i86/modrm.h52
-rw-r--r--src/emu/cpu/i86/table186.h516
-rw-r--r--src/emu/cpu/i86/table286.h516
-rw-r--r--src/emu/cpu/i86/table86.h516
-rw-r--r--src/emu/cpu/i86/tablev30.h528
-rw-r--r--src/emu/cpu/i86/v20intf.h13
-rw-r--r--src/emu/cpu/i86/v30.h30
-rw-r--r--src/emu/cpu/i86/v30intf.h11
-rw-r--r--src/emu/cpu/i86/v33intf.h10
22 files changed, 2498 insertions, 4414 deletions
diff --git a/src/emu/cpu/i86/ea.h b/src/emu/cpu/i86/ea.h
index dca12337a5b..313cb02ab92 100644
--- a/src/emu/cpu/i86/ea.h
+++ b/src/emu/cpu/i86/ea.h
@@ -1,34 +1,31 @@
-static unsigned EA;
-static UINT16 EO; /* HJB 12/13/98 effective offset of the address (before segment is added) */
+static unsigned EA_000(i8086_state *cpustate) { cpustate->icount-=7; cpustate->eo=(WORD)(cpustate->regs.w[BX]+cpustate->regs.w[SI]); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
+static unsigned EA_001(i8086_state *cpustate) { cpustate->icount-=8; cpustate->eo=(WORD)(cpustate->regs.w[BX]+cpustate->regs.w[DI]); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
+static unsigned EA_002(i8086_state *cpustate) { cpustate->icount-=8; cpustate->eo=(WORD)(cpustate->regs.w[BP]+cpustate->regs.w[SI]); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
+static unsigned EA_003(i8086_state *cpustate) { cpustate->icount-=7; cpustate->eo=(WORD)(cpustate->regs.w[BP]+cpustate->regs.w[DI]); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
+static unsigned EA_004(i8086_state *cpustate) { cpustate->icount-=5; cpustate->eo=cpustate->regs.w[SI]; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
+static unsigned EA_005(i8086_state *cpustate) { cpustate->icount-=5; cpustate->eo=cpustate->regs.w[DI]; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
+static unsigned EA_006(i8086_state *cpustate) { cpustate->icount-=6; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
+static unsigned EA_007(i8086_state *cpustate) { cpustate->icount-=5; cpustate->eo=cpustate->regs.w[BX]; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
-static unsigned EA_000(void) { i8086_ICount-=7; EO=(WORD)(I.regs.w[BX]+I.regs.w[SI]); EA=DefaultBase(DS)+EO; return EA; }
-static unsigned EA_001(void) { i8086_ICount-=8; EO=(WORD)(I.regs.w[BX]+I.regs.w[DI]); EA=DefaultBase(DS)+EO; return EA; }
-static unsigned EA_002(void) { i8086_ICount-=8; EO=(WORD)(I.regs.w[BP]+I.regs.w[SI]); EA=DefaultBase(SS)+EO; return EA; }
-static unsigned EA_003(void) { i8086_ICount-=7; EO=(WORD)(I.regs.w[BP]+I.regs.w[DI]); EA=DefaultBase(SS)+EO; return EA; }
-static unsigned EA_004(void) { i8086_ICount-=5; EO=I.regs.w[SI]; EA=DefaultBase(DS)+EO; return EA; }
-static unsigned EA_005(void) { i8086_ICount-=5; EO=I.regs.w[DI]; EA=DefaultBase(DS)+EO; return EA; }
-static unsigned EA_006(void) { i8086_ICount-=6; EO=FETCHOP; EO+=FETCHOP<<8; EA=DefaultBase(DS)+EO; return EA; }
-static unsigned EA_007(void) { i8086_ICount-=5; EO=I.regs.w[BX]; EA=DefaultBase(DS)+EO; return EA; }
+static unsigned EA_100(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=(WORD)(cpustate->regs.w[BX]+cpustate->regs.w[SI]+(INT8)FETCHOP); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
+static unsigned EA_101(i8086_state *cpustate) { cpustate->icount-=12; cpustate->eo=(WORD)(cpustate->regs.w[BX]+cpustate->regs.w[DI]+(INT8)FETCHOP); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
+static unsigned EA_102(i8086_state *cpustate) { cpustate->icount-=12; cpustate->eo=(WORD)(cpustate->regs.w[BP]+cpustate->regs.w[SI]+(INT8)FETCHOP); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
+static unsigned EA_103(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=(WORD)(cpustate->regs.w[BP]+cpustate->regs.w[DI]+(INT8)FETCHOP); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
+static unsigned EA_104(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=(WORD)(cpustate->regs.w[SI]+(INT8)FETCHOP); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
+static unsigned EA_105(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=(WORD)(cpustate->regs.w[DI]+(INT8)FETCHOP); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
+static unsigned EA_106(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=(WORD)(cpustate->regs.w[BP]+(INT8)FETCHOP); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
+static unsigned EA_107(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=(WORD)(cpustate->regs.w[BX]+(INT8)FETCHOP); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
-static unsigned EA_100(void) { i8086_ICount-=11; EO=(WORD)(I.regs.w[BX]+I.regs.w[SI]+(INT8)FETCHOP); EA=DefaultBase(DS)+EO; return EA; }
-static unsigned EA_101(void) { i8086_ICount-=12; EO=(WORD)(I.regs.w[BX]+I.regs.w[DI]+(INT8)FETCHOP); EA=DefaultBase(DS)+EO; return EA; }
-static unsigned EA_102(void) { i8086_ICount-=12; EO=(WORD)(I.regs.w[BP]+I.regs.w[SI]+(INT8)FETCHOP); EA=DefaultBase(SS)+EO; return EA; }
-static unsigned EA_103(void) { i8086_ICount-=11; EO=(WORD)(I.regs.w[BP]+I.regs.w[DI]+(INT8)FETCHOP); EA=DefaultBase(SS)+EO; return EA; }
-static unsigned EA_104(void) { i8086_ICount-=9; EO=(WORD)(I.regs.w[SI]+(INT8)FETCHOP); EA=DefaultBase(DS)+EO; return EA; }
-static unsigned EA_105(void) { i8086_ICount-=9; EO=(WORD)(I.regs.w[DI]+(INT8)FETCHOP); EA=DefaultBase(DS)+EO; return EA; }
-static unsigned EA_106(void) { i8086_ICount-=9; EO=(WORD)(I.regs.w[BP]+(INT8)FETCHOP); EA=DefaultBase(SS)+EO; return EA; }
-static unsigned EA_107(void) { i8086_ICount-=9; EO=(WORD)(I.regs.w[BX]+(INT8)FETCHOP); EA=DefaultBase(DS)+EO; return EA; }
+static unsigned EA_200(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BX]+cpustate->regs.w[SI]; cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
+static unsigned EA_201(i8086_state *cpustate) { cpustate->icount-=12; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BX]+cpustate->regs.w[DI]; cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
+static unsigned EA_202(i8086_state *cpustate) { cpustate->icount-=12; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BP]+cpustate->regs.w[SI]; cpustate->ea=DefaultBase(SS)+(WORD)cpustate->eo; return cpustate->ea; }
+static unsigned EA_203(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BP]+cpustate->regs.w[DI]; cpustate->ea=DefaultBase(SS)+(WORD)cpustate->eo; return cpustate->ea; }
+static unsigned EA_204(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[SI]; cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
+static unsigned EA_205(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[DI]; cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
+static unsigned EA_206(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BP]; cpustate->ea=DefaultBase(SS)+(WORD)cpustate->eo; return cpustate->ea; }
+static unsigned EA_207(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BX]; cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
-static unsigned EA_200(void) { i8086_ICount-=11; EO=FETCHOP; EO+=FETCHOP<<8; EO+=I.regs.w[BX]+I.regs.w[SI]; EA=DefaultBase(DS)+(WORD)EO; return EA; }
-static unsigned EA_201(void) { i8086_ICount-=12; EO=FETCHOP; EO+=FETCHOP<<8; EO+=I.regs.w[BX]+I.regs.w[DI]; EA=DefaultBase(DS)+(WORD)EO; return EA; }
-static unsigned EA_202(void) { i8086_ICount-=12; EO=FETCHOP; EO+=FETCHOP<<8; EO+=I.regs.w[BP]+I.regs.w[SI]; EA=DefaultBase(SS)+(WORD)EO; return EA; }
-static unsigned EA_203(void) { i8086_ICount-=11; EO=FETCHOP; EO+=FETCHOP<<8; EO+=I.regs.w[BP]+I.regs.w[DI]; EA=DefaultBase(SS)+(WORD)EO; return EA; }
-static unsigned EA_204(void) { i8086_ICount-=9; EO=FETCHOP; EO+=FETCHOP<<8; EO+=I.regs.w[SI]; EA=DefaultBase(DS)+(WORD)EO; return EA; }
-static unsigned EA_205(void) { i8086_ICount-=9; EO=FETCHOP; EO+=FETCHOP<<8; EO+=I.regs.w[DI]; EA=DefaultBase(DS)+(WORD)EO; return EA; }
-static unsigned EA_206(void) { i8086_ICount-=9; EO=FETCHOP; EO+=FETCHOP<<8; EO+=I.regs.w[BP]; EA=DefaultBase(SS)+(WORD)EO; return EA; }
-static unsigned EA_207(void) { i8086_ICount-=9; EO=FETCHOP; EO+=FETCHOP<<8; EO+=I.regs.w[BX]; EA=DefaultBase(DS)+(WORD)EO; return EA; }
-
-static unsigned (*const GetEA[192])(void)={
+static unsigned (*const GetEA[192])(i8086_state *cpustate)={
EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
diff --git a/src/emu/cpu/i86/i286.c b/src/emu/cpu/i86/i286.c
index 3a80a7bfece..377f62e6837 100644
--- a/src/emu/cpu/i86/i286.c
+++ b/src/emu/cpu/i86/i286.c
@@ -11,11 +11,9 @@
#define LOG(x) do { if (VERBOSE) mame_printf_debug x; } while (0)
/* All post-i286 CPUs have a 16MB address space */
-#define AMASK I.amask
+#define AMASK cpustate->amask
-#define i8086_ICount i80286_ICount
-
#define INPUT_LINE_A20 1
#include "i86.h"
@@ -35,7 +33,8 @@ typedef union
UINT8 b[16]; /* or as 8 bit registers */
} i80286basicregs;
-typedef struct
+typedef struct _i80286_state i80286_state;
+struct _i80286_state
{
i80286basicregs regs;
UINT32 amask; /* address mask */
@@ -71,13 +70,12 @@ typedef struct
INT32 extra_cycles; /* extra cycles for interrupts */
memory_interface mem;
-} i80286_Regs;
-
-static int i80286_ICount;
-
-static i80286_Regs I;
-static unsigned prefix_base; /* base address of the latest prefix segment */
-static char seg_prefix; /* prefix segment indicator */
+ int icount;
+ unsigned prefix_base;
+ char seg_prefix;
+ unsigned ea;
+ UINT16 eo; /* HJB 12/13/98 effective offset of the address (before segment is added) */
+};
#define INT_IRQ 0x01
#define NMI_IRQ 0x02
@@ -93,6 +91,7 @@ static struct i80x86_timing timing;
#define PREFIX86(fname) i80286##fname
#define PREFIX186(fname) i80286##fname
#define PREFIX286(fname) i80286##fname
+#define i8086_state i80286_state
#include "ea.h"
#include "modrm.h"
@@ -131,13 +130,14 @@ static void i80286_urinit(void)
}
}
-static void i80286_set_a20_line(int state)
+static void i80286_set_a20_line(i80286_state *cpustate, int state)
{
- I.amask = state ? 0x00ffffff : 0x000fffff;
+ cpustate->amask = state ? 0x00ffffff : 0x000fffff;
}
static CPU_RESET( i80286 )
{
+ i80286_state *cpustate = device->token;
static int urinit=1;
/* in my docu not all registers are initialized! */
@@ -147,20 +147,20 @@ static CPU_RESET( i80286 )
}
- I.sregs[CS] = 0xf000;
- I.base[CS] = 0xff0000;
+ cpustate->sregs[CS] = 0xf000;
+ cpustate->base[CS] = 0xff0000;
/* temporary, until I have the right reset vector working */
- I.base[CS] = I.sregs[CS] << 4;
- I.pc = 0xffff0;
- I.limit[CS]=I.limit[SS]=I.limit[DS]=I.limit[ES]=0xffff;
- I.sregs[DS]=I.sregs[SS]=I.sregs[ES]=0;
- I.base[DS]=I.base[SS]=I.base[ES]=0;
- I.msw=0xfff0;
- I.flags=2;
- ExpandFlags(I.flags);
- I.idtr.base=0;I.idtr.limit=0x3ff;
-
- CHANGE_PC(I.pc);
+ cpustate->base[CS] = cpustate->sregs[CS] << 4;
+ cpustate->pc = 0xffff0;
+ cpustate->limit[CS]=cpustate->limit[SS]=cpustate->limit[DS]=cpustate->limit[ES]=0xffff;
+ cpustate->sregs[DS]=cpustate->sregs[SS]=cpustate->sregs[ES]=0;
+ cpustate->base[DS]=cpustate->base[SS]=cpustate->base[ES]=0;
+ cpustate->msw=0xfff0;
+ cpustate->flags=2;
+ ExpandFlags(cpustate->flags);
+ cpustate->idtr.base=0;cpustate->idtr.limit=0x3ff;
+
+ CHANGE_PC(cpustate->pc);
}
@@ -168,79 +168,63 @@ static CPU_RESET( i80286 )
/* ASG 971222 -- added these interface functions */
-static CPU_GET_CONTEXT( i80286 )
-{
- if( dst )
- *(i80286_Regs*)dst = I;
-}
-
-static CPU_SET_CONTEXT( i80286 )
-{
- if( src )
- {
- I = *(i80286_Regs*)src;
- if (PM) {
-
- } else {
- I.base[CS] = SegBase(CS);
- I.base[DS] = SegBase(DS);
- I.base[ES] = SegBase(ES);
- I.base[SS] = SegBase(SS);
- }
- CHANGE_PC(I.pc);
- }
-}
-
-static void set_irq_line(int irqline, int state)
+static void set_irq_line(i80286_state *cpustate, int irqline, int state)
{
if (irqline == INPUT_LINE_NMI)
{
- if (I.nmi_state == state)
+ if (cpustate->nmi_state == state)
return;
- I.nmi_state = state;
+ cpustate->nmi_state = state;
/* on a rising edge, signal the NMI */
if (state != CLEAR_LINE)
- PREFIX(_interrupt)(I8086_NMI_INT_VECTOR);
+ PREFIX(_interrupt)(cpustate, I8086_NMI_INT_VECTOR);
}
else
{
- I.irq_state = state;
+ cpustate->irq_state = state;
/* if the IF is set, signal an interrupt */
- if (state != CLEAR_LINE && I.IF)
- PREFIX(_interrupt)(-1);
+ if (state != CLEAR_LINE && cpustate->IF)
+ PREFIX(_interrupt)(cpustate, -1);
}
}
static CPU_EXECUTE( i80286 )
{
+ i80286_state *cpustate = device->token;
+
+ cpustate->base[CS] = SegBase(CS);
+ cpustate->base[DS] = SegBase(DS);
+ cpustate->base[ES] = SegBase(ES);
+ cpustate->base[SS] = SegBase(SS);
+
/* copy over the cycle counts if they're not correct */
if (timing.id != 80286)
timing = i80286_cycles;
/* adjust for any interrupts that came in */
- i80286_ICount = cycles;
- i80286_ICount -= I.extra_cycles;
- I.extra_cycles = 0;
+ cpustate->icount = cycles;
+ cpustate->icount -= cpustate->extra_cycles;
+ cpustate->extra_cycles = 0;
/* run until we're out */
- while(i80286_ICount>0)
+ while(cpustate->icount>0)
{
- LOG(("[%04x:%04x]=%02x\tF:%04x\tAX=%04x\tBX=%04x\tCX=%04x\tDX=%04x %d%d%d%d%d%d%d%d%d\n",I.sregs[CS],I.pc - I.base[CS],ReadByte(I.pc),I.flags,I.regs.w[AX],I.regs.w[BX],I.regs.w[CX],I.regs.w[DX], I.AuxVal?1:0, I.OverVal?1:0, I.SignVal?1:0, I.ZeroVal?1:0, I.CarryVal?1:0, I.ParityVal?1:0,I.TF, I.IF, I.DirVal<0?1:0));
- debugger_instruction_hook(device, I.pc);
+ LOG(("[%04x:%04x]=%02x\tF:%04x\tAX=%04x\tBX=%04x\tCX=%04x\tDX=%04x %d%d%d%d%d%d%d%d%d\n",cpustate->sregs[CS],cpustate->pc - cpustate->base[CS],ReadByte(cpustate->pc),cpustate->flags,cpustate->regs.w[AX],cpustate->regs.w[BX],cpustate->regs.w[CX],cpustate->regs.w[DX], cpustate->AuxVal?1:0, cpustate->OverVal?1:0, cpustate->SignVal?1:0, cpustate->ZeroVal?1:0, cpustate->CarryVal?1:0, cpustate->ParityVal?1:0,cpustate->TF, cpustate->IF, cpustate->DirVal<0?1:0));
+ debugger_instruction_hook(device, cpustate->pc);
- seg_prefix=FALSE;
- I.prevpc = I.pc;
+ cpustate->seg_prefix=FALSE;
+ cpustate->prevpc = cpustate->pc;
TABLE286 // call instruction
}
/* adjust for any interrupts that came in */
- i80286_ICount -= I.extra_cycles;
- I.extra_cycles = 0;
+ cpustate->icount -= cpustate->extra_cycles;
+ cpustate->extra_cycles = 0;
- return cycles - i80286_ICount;
+ return cycles - cpustate->icount;
}
extern int i386_dasm_one(char *buffer, UINT32 eip, const UINT8 *oprom, int mode);
@@ -252,53 +236,55 @@ static CPU_DISASSEMBLE( i80286 )
static CPU_INIT( i80286 )
{
- state_save_register_device_item_array(device, 0, I.regs.w);
- state_save_register_device_item(device, 0, I.amask);
- state_save_register_device_item(device, 0, I.pc);
- state_save_register_device_item(device, 0, I.prevpc);
- state_save_register_device_item(device, 0, I.msw);
- state_save_register_device_item_array(device, 0, I.base);
- state_save_register_device_item_array(device, 0, I.sregs);
- state_save_register_device_item_array(device, 0, I.limit);
- state_save_register_device_item_array(device, 0, I.rights);
- state_save_register_device_item(device, 0, I.gdtr.base);
- state_save_register_device_item(device, 0, I.gdtr.limit);
- state_save_register_device_item(device, 0, I.idtr.base);
- state_save_register_device_item(device, 0, I.idtr.limit);
- state_save_register_device_item(device, 0, I.ldtr.sel);
- state_save_register_device_item(device, 0, I.ldtr.base);
- state_save_register_device_item(device, 0, I.ldtr.limit);
- state_save_register_device_item(device, 0, I.ldtr.rights);
- state_save_register_device_item(device, 0, I.tr.sel);
- state_save_register_device_item(device, 0, I.tr.base);
- state_save_register_device_item(device, 0, I.tr.limit);
- state_save_register_device_item(device, 0, I.tr.rights);
- state_save_register_device_item(device, 0, I.AuxVal);
- state_save_register_device_item(device, 0, I.OverVal);
- state_save_register_device_item(device, 0, I.SignVal);
- state_save_register_device_item(device, 0, I.ZeroVal);
- state_save_register_device_item(device, 0, I.CarryVal);
- state_save_register_device_item(device, 0, I.DirVal);
- state_save_register_device_item(device, 0, I.ParityVal);
- state_save_register_device_item(device, 0, I.TF);
- state_save_register_device_item(device, 0, I.IF);
- state_save_register_device_item(device, 0, I.int_vector);
- state_save_register_device_item(device, 0, I.nmi_state);
- state_save_register_device_item(device, 0, I.irq_state);
- state_save_register_device_item(device, 0, I.extra_cycles);
-
- I.irq_callback = irqcallback;
- I.device = device;
- I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
- I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
+ i80286_state *cpustate = device->token;
+
+ state_save_register_device_item_array(device, 0, cpustate->regs.w);
+ state_save_register_device_item(device, 0, cpustate->amask);
+ state_save_register_device_item(device, 0, cpustate->pc);
+ state_save_register_device_item(device, 0, cpustate->prevpc);
+ state_save_register_device_item(device, 0, cpustate->msw);
+ state_save_register_device_item_array(device, 0, cpustate->base);
+ state_save_register_device_item_array(device, 0, cpustate->sregs);
+ state_save_register_device_item_array(device, 0, cpustate->limit);
+ state_save_register_device_item_array(device, 0, cpustate->rights);
+ state_save_register_device_item(device, 0, cpustate->gdtr.base);
+ state_save_register_device_item(device, 0, cpustate->gdtr.limit);
+ state_save_register_device_item(device, 0, cpustate->idtr.base);
+ state_save_register_device_item(device, 0, cpustate->idtr.limit);
+ state_save_register_device_item(device, 0, cpustate->ldtr.sel);
+ state_save_register_device_item(device, 0, cpustate->ldtr.base);
+ state_save_register_device_item(device, 0, cpustate->ldtr.limit);
+ state_save_register_device_item(device, 0, cpustate->ldtr.rights);
+ state_save_register_device_item(device, 0, cpustate->tr.sel);
+ state_save_register_device_item(device, 0, cpustate->tr.base);
+ state_save_register_device_item(device, 0, cpustate->tr.limit);
+ state_save_register_device_item(device, 0, cpustate->tr.rights);
+ state_save_register_device_item(device, 0, cpustate->AuxVal);
+ state_save_register_device_item(device, 0, cpustate->OverVal);
+ state_save_register_device_item(device, 0, cpustate->SignVal);
+ state_save_register_device_item(device, 0, cpustate->ZeroVal);
+ state_save_register_device_item(device, 0, cpustate->CarryVal);
+ state_save_register_device_item(device, 0, cpustate->DirVal);
+ state_save_register_device_item(device, 0, cpustate->ParityVal);
+ state_save_register_device_item(device, 0, cpustate->TF);
+ state_save_register_device_item(device, 0, cpustate->IF);
+ state_save_register_device_item(device, 0, cpustate->int_vector);
+ state_save_register_device_item(device, 0, cpustate->nmi_state);
+ state_save_register_device_item(device, 0, cpustate->irq_state);
+ state_save_register_device_item(device, 0, cpustate->extra_cycles);
+
+ cpustate->irq_callback = irqcallback;
+ cpustate->device = device;
+ cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
/* If a reset parameter is given, take it as pointer to an address mask */
if( device->static_config )
- I.amask = *(unsigned*)device->static_config;
+ cpustate->amask = *(unsigned*)device->static_config;
else
- I.amask = 0x00ffff;
+ cpustate->amask = 0x00ffff;
- configure_memory_16bit();
+ configure_memory_16bit(cpustate);
}
@@ -311,13 +297,15 @@ static CPU_INIT( i80286 )
static CPU_SET_INFO( i80286 )
{
+ i80286_state *cpustate = device->token;
+
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
- case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(0, info->i); break;
- case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(INPUT_LINE_NMI, info->i); break;
+ case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(cpustate, 0, info->i); break;
+ case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break;
- case CPUINFO_INT_INPUT_STATE + INPUT_LINE_A20: i80286_set_a20_line(info->i); break;
+ case CPUINFO_INT_INPUT_STATE + INPUT_LINE_A20: i80286_set_a20_line(cpustate, info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + I80286_PC:
@@ -327,16 +315,16 @@ static CPU_SET_INFO( i80286 )
}
else
{
- if (info->i - I.base[CS] >= 0x10000)
+ if (info->i - cpustate->base[CS] >= 0x10000)
{
- I.base[CS] = info->i & 0xffff0;
- I.sregs[CS] = I.base[CS] >> 4;
+ cpustate->base[CS] = info->i & 0xffff0;
+ cpustate->sregs[CS] = cpustate->base[CS] >> 4;
}
- I.pc = info->i;
+ cpustate->pc = info->i;
}
break;
- case CPUINFO_INT_REGISTER + I80286_IP: I.pc = I.base[CS] + info->i; break;
+ case CPUINFO_INT_REGISTER + I80286_IP: cpustate->pc = cpustate->base[CS] + info->i; break;
case CPUINFO_INT_SP:
if (PM)
{
@@ -344,33 +332,33 @@ static CPU_SET_INFO( i80286 )
}
else
{
- if (info->i - I.base[SS] < 0x10000)
+ if (info->i - cpustate->base[SS] < 0x10000)
{
- I.regs.w[SP] = info->i - I.base[SS];
+ cpustate->regs.w[SP] = info->i - cpustate->base[SS];
}
else
{
- I.base[SS] = info->i & 0xffff0;
- I.sregs[SS] = I.base[SS] >> 4;
- I.regs.w[SP] = info->i & 0x0000f;
+ cpustate->base[SS] = info->i & 0xffff0;
+ cpustate->sregs[SS] = cpustate->base[SS] >> 4;
+ cpustate->regs.w[SP] = info->i & 0x0000f;
}
}
break;
- case CPUINFO_INT_REGISTER + I80286_SP: I.regs.w[SP] = info->i; break;
- case CPUINFO_INT_REGISTER + I80286_FLAGS: I.flags = info->i; ExpandFlags(info->i); break;
- case CPUINFO_INT_REGISTER + I80286_AX: I.regs.w[AX] = info->i; break;
- case CPUINFO_INT_REGISTER + I80286_CX: I.regs.w[CX] = info->i; break;
- case CPUINFO_INT_REGISTER + I80286_DX: I.regs.w[DX] = info->i; break;
- case CPUINFO_INT_REGISTER + I80286_BX: I.regs.w[BX] = info->i; break;
- case CPUINFO_INT_REGISTER + I80286_BP: I.regs.w[BP] = info->i; break;
- case CPUINFO_INT_REGISTER + I80286_SI: I.regs.w[SI] = info->i; break;
- case CPUINFO_INT_REGISTER + I80286_DI: I.regs.w[DI] = info->i; break;
- case CPUINFO_INT_REGISTER + I80286_ES: I.sregs[ES] = info->i; I.base[ES] = SegBase(ES); break;
- case CPUINFO_INT_REGISTER + I80286_CS: I.sregs[CS] = info->i; I.base[CS] = SegBase(CS); break;
- case CPUINFO_INT_REGISTER + I80286_SS: I.sregs[SS] = info->i; I.base[SS] = SegBase(SS); break;
- case CPUINFO_INT_REGISTER + I80286_DS: I.sregs[DS] = info->i; I.base[DS] = SegBase(DS); break;
- case CPUINFO_INT_REGISTER + I80286_VECTOR: I.int_vector = info->i; break;
+ case CPUINFO_INT_REGISTER + I80286_SP: cpustate->regs.w[SP] = info->i; break;
+ case CPUINFO_INT_REGISTER + I80286_FLAGS: cpustate->flags = info->i; ExpandFlags(info->i); break;
+ case CPUINFO_INT_REGISTER + I80286_AX: cpustate->regs.w[AX] = info->i; break;
+ case CPUINFO_INT_REGISTER + I80286_CX: cpustate->regs.w[CX] = info->i; break;
+ case CPUINFO_INT_REGISTER + I80286_DX: cpustate->regs.w[DX] = info->i; break;
+ case CPUINFO_INT_REGISTER + I80286_BX: cpustate->regs.w[BX] = info->i; break;
+ case CPUINFO_INT_REGISTER + I80286_BP: cpustate->regs.w[BP] = info->i; break;
+ case CPUINFO_INT_REGISTER + I80286_SI: cpustate->regs.w[SI] = info->i; break;
+ case CPUINFO_INT_REGISTER + I80286_DI: cpustate->regs.w[DI] = info->i; break;
+ case CPUINFO_INT_REGISTER + I80286_ES: cpustate->sregs[ES] = info->i; cpustate->base[ES] = SegBase(ES); break;
+ case CPUINFO_INT_REGISTER + I80286_CS: cpustate->sregs[CS] = info->i; cpustate->base[CS] = SegBase(CS); break;
+ case CPUINFO_INT_REGISTER + I80286_SS: cpustate->sregs[SS] = info->i; cpustate->base[SS] = SegBase(SS); break;
+ case CPUINFO_INT_REGISTER + I80286_DS: cpustate->sregs[DS] = info->i; cpustate->base[DS] = SegBase(DS); break;
+ case CPUINFO_INT_REGISTER + I80286_VECTOR: cpustate->int_vector = info->i; break;
}
}
@@ -382,10 +370,12 @@ static CPU_SET_INFO( i80286 )
CPU_GET_INFO( i80286 )
{
+ i80286_state *cpustate = (device != NULL) ? device->token : NULL;
+
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
- case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(I); break;
+ case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(i80286_state); break;
case CPUINFO_INT_INPUT_LINES: info->i = 1; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0xff; break;
case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
@@ -406,107 +396,107 @@ CPU_GET_INFO( i80286 )
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 16; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
- case CPUINFO_INT_INPUT_STATE + 0: info->i = I.irq_state; break;
- case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = I.nmi_state; break;
+ case CPUINFO_INT_INPUT_STATE + 0: info->i = cpustate->irq_state; break;
+ case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = cpustate->nmi_state; break;
- case CPUINFO_INT_PREVIOUSPC: info->i = I.prevpc; break;
+ case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->prevpc; break;
case CPUINFO_INT_PC:
- case CPUINFO_INT_REGISTER + I80286_PC: info->i = I.pc; break;
- case CPUINFO_INT_REGISTER + I80286_IP: info->i = I.pc - I.base[CS]; break;
- case CPUINFO_INT_SP: info->i = I.base[SS] + I.regs.w[SP]; break;
- case CPUINFO_INT_REGISTER + I80286_SP: info->i = I.regs.w[SP]; break;
- case CPUINFO_INT_REGISTER + I80286_FLAGS: I.flags = CompressFlags(); info->i = I.flags; break;
- case CPUINFO_INT_REGISTER + I80286_AX: info->i = I.regs.w[AX]; break;
- case CPUINFO_INT_REGISTER + I80286_CX: info->i = I.regs.w[CX]; break;
- case CPUINFO_INT_REGISTER + I80286_DX: info->i = I.regs.w[DX]; break;
- case CPUINFO_INT_REGISTER + I80286_BX: info->i = I.regs.w[BX]; break;
- case CPUINFO_INT_REGISTER + I80286_BP: info->i = I.regs.w[BP]; break;
- case CPUINFO_INT_REGISTER + I80286_SI: info->i = I.regs.w[SI]; break;
- case CPUINFO_INT_REGISTER + I80286_DI: info->i = I.regs.w[DI]; break;
- case CPUINFO_INT_REGISTER + I80286_ES: info->i = I.sregs[ES]; break;
- case CPUINFO_INT_REGISTER + I80286_CS: info->i = I.sregs[CS]; break;
- case CPUINFO_INT_REGISTER + I80286_SS: info->i = I.sregs[SS]; break;
- case CPUINFO_INT_REGISTER + I80286_DS: info->i = I.sregs[DS]; break;
- case CPUINFO_INT_REGISTER + I80286_VECTOR: info->i = I.int_vector; break;
- case CPUINFO_INT_REGISTER + I80286_MSW: info->i = I.msw; break;
- case CPUINFO_INT_REGISTER + I80286_GDTR_BASE: info->i = I.gdtr.base; break;
- case CPUINFO_INT_REGISTER + I80286_GDTR_LIMIT: info->i = I.gdtr.limit; break;
- case CPUINFO_INT_REGISTER + I80286_IDTR_BASE: info->i = I.idtr.base; break;
- case CPUINFO_INT_REGISTER + I80286_IDTR_LIMIT: info->i = I.idtr.limit; break;
- case CPUINFO_INT_REGISTER + I80286_LDTR_BASE: info->i = I.ldtr.base; break;
- case CPUINFO_INT_REGISTER + I80286_LDTR_LIMIT: info->i = I.ldtr.limit; break;
- case CPUINFO_INT_REGISTER + I80286_TR_BASE: info->i = I.tr.base; break;
- case CPUINFO_INT_REGISTER + I80286_TR_LIMIT: info->i = I.tr.limit; break;
+ case CPUINFO_INT_REGISTER + I80286_PC: info->i = cpustate->pc; break;
+ case CPUINFO_INT_REGISTER + I80286_IP: info->i = cpustate->pc - cpustate->base[CS]; break;
+ case CPUINFO_INT_SP: info->i = cpustate->base[SS] + cpustate->regs.w[SP]; break;
+ case CPUINFO_INT_REGISTER + I80286_SP: info->i = cpustate->regs.w[SP]; break;
+ case CPUINFO_INT_REGISTER + I80286_FLAGS: cpustate->flags = CompressFlags(); info->i = cpustate->flags; break;
+ case CPUINFO_INT_REGISTER + I80286_AX: info->i = cpustate->regs.w[AX]; break;
+ case CPUINFO_INT_REGISTER + I80286_CX: info->i = cpustate->regs.w[CX]; break;
+ case CPUINFO_INT_REGISTER + I80286_DX: info->i = cpustate->regs.w[DX]; break;
+ case CPUINFO_INT_REGISTER + I80286_BX: info->i = cpustate->regs.w[BX]; break;
+ case CPUINFO_INT_REGISTER + I80286_BP: info->i = cpustate->regs.w[BP]; break;
+ case CPUINFO_INT_REGISTER + I80286_SI: info->i = cpustate->regs.w[SI]; break;
+ case CPUINFO_INT_REGISTER + I80286_DI: info->i = cpustate->regs.w[DI]; break;
+ case CPUINFO_INT_REGISTER + I80286_ES: info->i = cpustate->sregs[ES]; break;
+ case CPUINFO_INT_REGISTER + I80286_CS: info->i = cpustate->sregs[CS]; break;
+ case CPUINFO_INT_REGISTER + I80286_SS: info->i = cpustate->sregs[SS]; break;
+ case CPUINFO_INT_REGISTER + I80286_DS: info->i = cpustate->sregs[DS]; break;
+ case CPUINFO_INT_REGISTER + I80286_VECTOR: info->i = cpustate->int_vector; break;
+ case CPUINFO_INT_REGISTER + I80286_MSW: info->i = cpustate->msw; break;
+ case CPUINFO_INT_REGISTER + I80286_GDTR_BASE: info->i = cpustate->gdtr.base; break;
+ case CPUINFO_INT_REGISTER + I80286_GDTR_LIMIT: info->i = cpustate->gdtr.limit; break;
+ case CPUINFO_INT_REGISTER + I80286_IDTR_BASE: info->i = cpustate->idtr.base; break;
+ case CPUINFO_INT_REGISTER + I80286_IDTR_LIMIT: info->i = cpustate->idtr.limit; break;
+ case CPUINFO_INT_REGISTER + I80286_LDTR_BASE: info->i = cpustate->ldtr.base; break;
+ case CPUINFO_INT_REGISTER + I80286_LDTR_LIMIT: info->i = cpustate->ldtr.limit; break;
+ case CPUINFO_INT_REGISTER + I80286_TR_BASE: info->i = cpustate->tr.base; break;
+ case CPUINFO_INT_REGISTER + I80286_TR_LIMIT: info->i = cpustate->tr.limit; break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(i80286); break;
- case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(i80286); break;
- case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(i80286); break;
+ case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(dummy); break;
+ case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(dummy); break;
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i80286); break;
case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(i80286); break;
case CPUINFO_PTR_EXIT: info->exit = NULL; break;
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(i80286); break;
case CPUINFO_PTR_BURN: info->burn = NULL; break;
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i80286); break;
- case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &i80286_ICount; break;
+ case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "80286"); break;
case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "Intel 80286"); break;
case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "1.4"); break;
case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
- case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Real mode i286 emulator v1.4 by Fabrice Frances\n(initial work I.based on David Hedley's pcemu)"); break;
+ case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Real mode i286 emulator v1.4 by Fabrice Frances\n(initial work cpustate->based on David Hedley's pcemu)"); break;
case CPUINFO_STR_FLAGS:
- I.flags = CompressFlags();
+ cpustate->flags = CompressFlags();
sprintf(info->s, "%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
- I.flags & 0x8000 ? '?' : '.',
- I.flags & 0x4000 ? '?' : '.',
- I.flags & 0x2000 ? '?' : '.',
- I.flags & 0x1000 ? '?' : '.',
- I.flags & 0x0800 ? 'O' : '.',
- I.flags & 0x0400 ? 'D' : '.',
- I.flags & 0x0200 ? 'I' : '.',
- I.flags & 0x0100 ? 'T' : '.',
- I.flags & 0x0080 ? 'S' : '.',
- I.flags & 0x0040 ? 'Z' : '.',
- I.flags & 0x0020 ? '?' : '.',
- I.flags & 0x0010 ? 'A' : '.',
- I.flags & 0x0008 ? '?' : '.',
- I.flags & 0x0004 ? 'P' : '.',
- I.flags & 0x0002 ? 'N' : '.',
- I.flags & 0x0001 ? 'C' : '.');
+ cpustate->flags & 0x8000 ? '?' : '.',
+ cpustate->flags & 0x4000 ? '?' : '.',
+ cpustate->flags & 0x2000 ? '?' : '.',
+ cpustate->flags & 0x1000 ? '?' : '.',
+ cpustate->flags & 0x0800 ? 'O' : '.',
+ cpustate->flags & 0x0400 ? 'D' : '.',
+ cpustate->flags & 0x0200 ? 'I' : '.',
+ cpustate->flags & 0x0100 ? 'T' : '.',
+ cpustate->flags & 0x0080 ? 'S' : '.',
+ cpustate->flags & 0x0040 ? 'Z' : '.',
+ cpustate->flags & 0x0020 ? '?' : '.',
+ cpustate->flags & 0x0010 ? 'A' : '.',
+ cpustate->flags & 0x0008 ? '?' : '.',
+ cpustate->flags & 0x0004 ? 'P' : '.',
+ cpustate->flags & 0x0002 ? 'N' : '.',
+ cpustate->flags & 0x0001 ? 'C' : '.');
break;
- case CPUINFO_STR_REGISTER + I80286_PC: sprintf(info->s, "PC:%04X", I.pc); break;
- case CPUINFO_STR_REGISTER + I80286_IP: sprintf(info->s, "IP: %04X", I.pc - I.base[CS]); break;
- case CPUINFO_STR_REGISTER + I80286_SP: sprintf(info->s, "SP: %04X", I.regs.w[SP]); break;
- case CPUINFO_STR_REGISTER + I80286_FLAGS: sprintf(info->s, "F:%04X", I.flags); break;
- case CPUINFO_STR_REGISTER + I80286_AX: sprintf(info->s, "AX:%04X", I.regs.w[AX]); break;
- case CPUINFO_STR_REGISTER + I80286_CX: sprintf(info->s, "CX:%04X", I.regs.w[CX]); break;
- case CPUINFO_STR_REGISTER + I80286_DX: sprintf(info->s, "DX:%04X", I.regs.w[DX]); break;
- case CPUINFO_STR_REGISTER + I80286_BX: sprintf(info->s, "BX:%04X", I.regs.w[BX]); break;
- case CPUINFO_STR_REGISTER + I80286_BP: sprintf(info->s, "BP:%04X", I.regs.w[BP]); break;
- case CPUINFO_STR_REGISTER + I80286_SI: sprintf(info->s, "SI: %04X", I.regs.w[SI]); break;
- case CPUINFO_STR_REGISTER + I80286_DI: sprintf(info->s, "DI: %04X", I.regs.w[DI]); break;
- case CPUINFO_STR_REGISTER + I80286_CS: sprintf(info->s, "CS: %04X %02X", I.sregs[CS], I.rights[CS]); break;
- case CPUINFO_STR_REGISTER + I80286_CS_2: sprintf(info->s, "%06X %04X", I.base[CS], I.limit[CS]); break;
- case CPUINFO_STR_REGISTER + I80286_SS: sprintf(info->s, "SS: %04X %02X", I.sregs[SS], I.rights[SS]); break;
- case CPUINFO_STR_REGISTER + I80286_SS_2: sprintf(info->s, "%06X %04X", I.base[SS], I.limit[SS]); break;
- case CPUINFO_STR_REGISTER + I80286_DS: sprintf(info->s, "DS: %04X %02X", I.sregs[DS], I.rights[DS]); break;
- case CPUINFO_STR_REGISTER + I80286_DS_2: sprintf(info->s, "%06X %04X", I.base[DS], I.limit[DS]); break;
- case CPUINFO_STR_REGISTER + I80286_ES: sprintf(info->s, "ES: %04X %02X", I.sregs[ES], I.rights[ES]); break;
- case CPUINFO_STR_REGISTER + I80286_ES_2: sprintf(info->s, "%06X %04X", I.base[ES], I.limit[ES]); break;
- case CPUINFO_STR_REGISTER + I80286_VECTOR: sprintf(info->s, "V:%02X", I.int_vector); break;
- case CPUINFO_STR_REGISTER + I80286_MSW: sprintf(info->s, "MSW:%04X", I.msw); break;
- case CPUINFO_STR_REGISTER + I80286_TR_BASE: sprintf(info->s, "GDTR: %06X", I.gdtr.base); break;
- case CPUINFO_STR_REGISTER + I80286_TR_LIMIT: sprintf(info->s, "%04X", I.gdtr.limit); break;
- case CPUINFO_STR_REGISTER + I80286_GDTR_BASE: sprintf(info->s, "IDTR: %06X", I.idtr.base); break;
- case CPUINFO_STR_REGISTER + I80286_GDTR_LIMIT: sprintf(info->s, "%04X", I.idtr.limit); break;
- case CPUINFO_STR_REGISTER + I80286_LDTR_BASE: sprintf(info->s, "LDTR:%04X %02X", I.ldtr.sel, I.ldtr.rights); break;
- case CPUINFO_STR_REGISTER + I80286_LDTR_LIMIT: sprintf(info->s, "%06X %04X", I.ldtr.base, I.ldtr.limit); break;
- case CPUINFO_STR_REGISTER + I80286_IDTR_BASE: sprintf(info->s, "IDTR: %06X", I.idtr.base); break;
- case CPUINFO_STR_REGISTER + I80286_IDTR_LIMIT: sprintf(info->s, "%04X", I.idtr.limit); break;
+ case CPUINFO_STR_REGISTER + I80286_PC: sprintf(info->s, "PC:%04X", cpustate->pc); break;
+ case CPUINFO_STR_REGISTER + I80286_IP: sprintf(info->s, "IP: %04X", cpustate->pc - cpustate->base[CS]); break;
+ case CPUINFO_STR_REGISTER + I80286_SP: sprintf(info->s, "SP: %04X", cpustate->regs.w[SP]); break;
+ case CPUINFO_STR_REGISTER + I80286_FLAGS: sprintf(info->s, "F:%04X", cpustate->flags); break;
+ case CPUINFO_STR_REGISTER + I80286_AX: sprintf(info->s, "AX:%04X", cpustate->regs.w[AX]); break;
+ case CPUINFO_STR_REGISTER + I80286_CX: sprintf(info->s, "CX:%04X", cpustate->regs.w[CX]); break;
+ case CPUINFO_STR_REGISTER + I80286_DX: sprintf(info->s, "DX:%04X", cpustate->regs.w[DX]); break;
+ case CPUINFO_STR_REGISTER + I80286_BX: sprintf(info->s, "BX:%04X", cpustate->regs.w[BX]); break;
+ case CPUINFO_STR_REGISTER + I80286_BP: sprintf(info->s, "BP:%04X", cpustate->regs.w[BP]); break;
+ case CPUINFO_STR_REGISTER + I80286_SI: sprintf(info->s, "SI: %04X", cpustate->regs.w[SI]); break;
+ case CPUINFO_STR_REGISTER + I80286_DI: sprintf(info->s, "DI: %04X", cpustate->regs.w[DI]); break;
+ case CPUINFO_STR_REGISTER + I80286_CS: sprintf(info->s, "CS: %04X %02X", cpustate->sregs[CS], cpustate->rights[CS]); break;
+ case CPUINFO_STR_REGISTER + I80286_CS_2: sprintf(info->s, "%06X %04X", cpustate->base[CS], cpustate->limit[CS]); break;
+ case CPUINFO_STR_REGISTER + I80286_SS: sprintf(info->s, "SS: %04X %02X", cpustate->sregs[SS], cpustate->rights[SS]); break;
+ case CPUINFO_STR_REGISTER + I80286_SS_2: sprintf(info->s, "%06X %04X", cpustate->base[SS], cpustate->limit[SS]); break;
+ case CPUINFO_STR_REGISTER + I80286_DS: sprintf(info->s, "DS: %04X %02X", cpustate->sregs[DS], cpustate->rights[DS]); break;
+ case CPUINFO_STR_REGISTER + I80286_DS_2: sprintf(info->s, "%06X %04X", cpustate->base[DS], cpustate->limit[DS]); break;
+ case CPUINFO_STR_REGISTER + I80286_ES: sprintf(info->s, "ES: %04X %02X", cpustate->sregs[ES], cpustate->rights[ES]); break;
+ case CPUINFO_STR_REGISTER + I80286_ES_2: sprintf(info->s, "%06X %04X", cpustate->base[ES], cpustate->limit[ES]); break;
+ case CPUINFO_STR_REGISTER + I80286_VECTOR: sprintf(info->s, "V:%02X", cpustate->int_vector); break;
+ case CPUINFO_STR_REGISTER + I80286_MSW: sprintf(info->s, "MSW:%04X", cpustate->msw); break;
+ case CPUINFO_STR_REGISTER + I80286_TR_BASE: sprintf(info->s, "GDTR: %06X", cpustate->gdtr.base); break;
+ case CPUINFO_STR_REGISTER + I80286_TR_LIMIT: sprintf(info->s, "%04X", cpustate->gdtr.limit); break;
+ case CPUINFO_STR_REGISTER + I80286_GDTR_BASE: sprintf(info->s, "IDTR: %06X", cpustate->idtr.base); break;
+ case CPUINFO_STR_REGISTER + I80286_GDTR_LIMIT: sprintf(info->s, "%04X", cpustate->idtr.limit); break;
+ case CPUINFO_STR_REGISTER + I80286_LDTR_BASE: sprintf(info->s, "LDTR:%04X %02X", cpustate->ldtr.sel, cpustate->ldtr.rights); break;
+ case CPUINFO_STR_REGISTER + I80286_LDTR_LIMIT: sprintf(info->s, "%06X %04X", cpustate->ldtr.base, cpustate->ldtr.limit); break;
+ case CPUINFO_STR_REGISTER + I80286_IDTR_BASE: sprintf(info->s, "IDTR: %06X", cpustate->idtr.base); break;
+ case CPUINFO_STR_REGISTER + I80286_IDTR_LIMIT: sprintf(info->s, "%04X", cpustate->idtr.limit); break;
}
}
diff --git a/src/emu/cpu/i86/i86.c b/src/emu/cpu/i86/i86.c
index a3cbbf66c28..85c572da767 100644
--- a/src/emu/cpu/i86/i86.c
+++ b/src/emu/cpu/i86/i86.c
@@ -31,7 +31,8 @@ typedef union
}
i8086basicregs;
-typedef struct
+typedef struct _i8086_state i8086_state;
+struct _i8086_state
{
i8086basicregs regs;
UINT32 pc;
@@ -40,9 +41,6 @@ typedef struct
UINT16 sregs[4];
UINT16 flags;
cpu_irq_callback irq_callback;
- const device_config *device;
- const address_space *program;
- const address_space *io;
INT32 AuxVal, OverVal, SignVal, ZeroVal, CarryVal, DirVal; /* 0 or non-0 valued flags */
UINT8 ParityVal;
UINT8 TF, IF; /* 0 or 1 valued flags */
@@ -54,8 +52,18 @@ typedef struct
INT32 extra_cycles; /* extra cycles for interrupts */
memory_interface mem;
-}
-i8086_Regs;
+
+ const device_config *device;
+ const address_space *program;
+ const address_space *io;
+ int icount;
+
+ unsigned prefix_base; /* base address of the latest prefix segment */
+ char seg_prefix; /* prefix segment indicator */
+ unsigned ea;
+ UINT16 eo; /* HJB 12/13/98 effective offset of the address (before segment is added) */
+};
+
#include "i86time.c"
@@ -64,16 +72,11 @@ i8086_Regs;
/* cpu state */
/***************************************************************************/
-static int i8086_ICount;
-static i8086_Regs I;
-static unsigned prefix_base; /* base address of the latest prefix segment */
-static char seg_prefix; /* prefix segment indicator */
+static struct i80x86_timing timing;
static UINT8 parity_table[256];
-static struct i80x86_timing timing;
-
/* The interrupt number of a pending external interrupt pending NMI is 2. */
/* For INTR interrupts, the level is caught on the bus during an INTA cycle */
@@ -94,31 +97,33 @@ static struct i80x86_timing timing;
/***************************************************************************/
static void i8086_state_register(const device_config *device)
{
- state_save_register_device_item_array(device, 0, I.regs.w);
- state_save_register_device_item(device, 0, I.pc);
- state_save_register_device_item(device, 0, I.prevpc);
- state_save_register_device_item_array(device, 0, I.base);
- state_save_register_device_item_array(device, 0, I.sregs);
- state_save_register_device_item(device, 0, I.flags);
- state_save_register_device_item(device, 0, I.AuxVal);
- state_save_register_device_item(device, 0, I.OverVal);
- state_save_register_device_item(device, 0, I.SignVal);
- state_save_register_device_item(device, 0, I.ZeroVal);
- state_save_register_device_item(device, 0, I.CarryVal);
- state_save_register_device_item(device, 0, I.DirVal);
- state_save_register_device_item(device, 0, I.ParityVal);
- state_save_register_device_item(device, 0, I.TF);
- state_save_register_device_item(device, 0, I.IF);
- state_save_register_device_item(device, 0, I.MF);
- state_save_register_device_item(device, 0, I.int_vector);
- state_save_register_device_item(device, 0, I.nmi_state);
- state_save_register_device_item(device, 0, I.irq_state);
- state_save_register_device_item(device, 0, I.extra_cycles);
- state_save_register_device_item(device, 0, I.test_state); /* PJB 03/05 */
+ i8086_state *cpustate = device->token;
+ state_save_register_device_item_array(device, 0, cpustate->regs.w);
+ state_save_register_device_item(device, 0, cpustate->pc);
+ state_save_register_device_item(device, 0, cpustate->prevpc);
+ state_save_register_device_item_array(device, 0, cpustate->base);
+ state_save_register_device_item_array(device, 0, cpustate->sregs);
+ state_save_register_device_item(device, 0, cpustate->flags);
+ state_save_register_device_item(device, 0, cpustate->AuxVal);
+ state_save_register_device_item(device, 0, cpustate->OverVal);
+ state_save_register_device_item(device, 0, cpustate->SignVal);
+ state_save_register_device_item(device, 0, cpustate->ZeroVal);
+ state_save_register_device_item(device, 0, cpustate->CarryVal);
+ state_save_register_device_item(device, 0, cpustate->DirVal);
+ state_save_register_device_item(device, 0, cpustate->ParityVal);
+ state_save_register_device_item(device, 0, cpustate->TF);
+ state_save_register_device_item(device, 0, cpustate->IF);
+ state_save_register_device_item(device, 0, cpustate->MF);
+ state_save_register_device_item(device, 0, cpustate->int_vector);
+ state_save_register_device_item(device, 0, cpustate->nmi_state);
+ state_save_register_device_item(device, 0, cpustate->irq_state);
+ state_save_register_device_item(device, 0, cpustate->extra_cycles);
+ state_save_register_device_item(device, 0, cpustate->test_state); /* PJB 03/05 */
}
static CPU_INIT( i8086 )
{
+ i8086_state *cpustate = device->token;
unsigned int i, j, c;
static const BREGS reg_name[8] = {AL, CL, DL, BL, AH, CH, DH, BH};
for (i = 0; i < 256; i++)
@@ -142,41 +147,43 @@ static CPU_INIT( i8086 )
Mod_RM.RM.b[i] = (BREGS) reg_name[i & 7];
}
- I.irq_callback = irqcallback;
- I.device = device;
- I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
- I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
+ cpustate->irq_callback = irqcallback;
+ cpustate->device = device;
+ cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
i8086_state_register(device);
- configure_memory_16bit();
+ configure_memory_16bit(cpustate);
}
#if (HAS_I8088||HAS_I80188)
static CPU_INIT( i8088 )
{
+ i8086_state *cpustate = device->token;
CPU_INIT_CALL(i8086);
- configure_memory_8bit();
+ configure_memory_8bit(cpustate);
}
#endif
static CPU_RESET( i8086 )
{
+ i8086_state *cpustate = device->token;
cpu_irq_callback save_irqcallback;
memory_interface save_mem;
- save_irqcallback = I.irq_callback;
- save_mem = I.mem;
- memset(&I, 0, sizeof (I));
- I.irq_callback = save_irqcallback;
- I.mem = save_mem;
- I.device = device;
- I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
- I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
-
- I.sregs[CS] = 0xf000;
- I.base[CS] = SegBase(CS);
- I.pc = 0xffff0 & AMASK;
- ExpandFlags(I.flags);
+ save_irqcallback = cpustate->irq_callback;
+ save_mem = cpustate->mem;
+ memset(cpustate, 0, sizeof(*cpustate));
+ cpustate->irq_callback = save_irqcallback;
+ cpustate->mem = save_mem;
+ cpustate->device = device;
+ cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
+
+ cpustate->sregs[CS] = 0xf000;
+ cpustate->base[CS] = SegBase(CS);
+ cpustate->pc = 0xffff0 & AMASK;
+ ExpandFlags(cpustate->flags);
}
static CPU_EXIT( i8086 )
@@ -186,81 +193,70 @@ static CPU_EXIT( i8086 )
/* ASG 971222 -- added these interface functions */
-static CPU_GET_CONTEXT( i8086 )
-{
- if (dst)
- *(i8086_Regs *) dst = I;
-}
-
-static CPU_SET_CONTEXT( i8086 )
-{
- if (src)
- {
- I = *(i8086_Regs *)src;
- I.base[CS] = SegBase(CS);
- I.base[DS] = SegBase(DS);
- I.base[ES] = SegBase(ES);
- I.base[SS] = SegBase(SS);
- }
-}
-
-static void set_irq_line(int irqline, int state)
+static void set_irq_line(i8086_state *cpustate, int irqline, int state)
{
if (irqline == INPUT_LINE_NMI)
{
- if (I.nmi_state == state)
+ if (cpustate->nmi_state == state)
return;
- I.nmi_state = state;
+ cpustate->nmi_state = state;
/* on a rising edge, signal the NMI */
if (state != CLEAR_LINE)
- PREFIX(_interrupt)(I8086_NMI_INT_VECTOR);
+ PREFIX(_interrupt)(cpustate, I8086_NMI_INT_VECTOR);
}
else
{
- I.irq_state = state;
+ cpustate->irq_state = state;
/* if the IF is set, signal an interrupt */
- if (state != CLEAR_LINE && I.IF)
- PREFIX(_interrupt)(-1);
+ if (state != CLEAR_LINE && cpustate->IF)
+ PREFIX(_interrupt)(cpustate, -1);
}
}
/* PJB 03/05 */
-static void set_test_line(int state)
+static void set_test_line(i8086_state *cpustate, int state)
{
- I.test_state = !state;
+ cpustate->test_state = !state;
}
static CPU_EXECUTE( i8086 )
{
+ i8086_state *cpustate = device->token;
+
+ cpustate->base[CS] = SegBase(CS);
+ cpustate->base[DS] = SegBase(DS);
+ cpustate->base[ES] = SegBase(ES);
+ cpustate->base[SS] = SegBase(SS);
+
/* copy over the cycle counts if they're not correct */
if (timing.id != 8086)
timing = i8086_cycles;
/* adjust for any interrupts that came in */
- i8086_ICount = cycles;
- i8086_ICount -= I.extra_cycles;
- I.extra_cycles = 0;
+ cpustate->icount = cycles;
+ cpustate->icount -= cpustate->extra_cycles;
+ cpustate->extra_cycles = 0;
/* run until we're out */
- while (i8086_ICount > 0)
+ while (cpustate->icount > 0)
{
LOG(("[%04x:%04x]=%02x\tF:%04x\tAX=%04x\tBX=%04x\tCX=%04x\tDX=%04x %d%d%d%d%d%d%d%d%d\n",
- I.sregs[CS], I.pc - I.base[CS], ReadByte(I.pc), I.flags, I.regs.w[AX], I.regs.w[BX], I.regs.w[CX], I.regs.w[DX], I.AuxVal ? 1 : 0, I.OverVal ? 1 : 0,
- I.SignVal ? 1 : 0, I.ZeroVal ? 1 : 0, I.CarryVal ? 1 : 0, I.ParityVal ? 1 : 0, I.TF, I.IF, I.DirVal < 0 ? 1 : 0));
- debugger_instruction_hook(device, I.pc);
+ cpustate->sregs[CS], cpustate->pc - cpustate->base[CS], ReadByte(cpustate->pc), cpustate->flags, cpustate->regs.w[AX], cpustate->regs.w[BX], cpustate->regs.w[CX], cpustate->regs.w[DX], cpustate->AuxVal ? 1 : 0, cpustate->OverVal ? 1 : 0,
+ cpustate->SignVal ? 1 : 0, cpustate->ZeroVal ? 1 : 0, cpustate->CarryVal ? 1 : 0, cpustate->ParityVal ? 1 : 0, cpustate->TF, cpustate->IF, cpustate->DirVal < 0 ? 1 : 0));
+ debugger_instruction_hook(device, cpustate->pc);
- seg_prefix = FALSE;
- I.prevpc = I.pc;
+ cpustate->seg_prefix = FALSE;
+ cpustate->prevpc = cpustate->pc;
TABLE86;
}
/* adjust for any interrupts that came in */
- i8086_ICount -= I.extra_cycles;
- I.extra_cycles = 0;
+ cpustate->icount -= cpustate->extra_cycles;
+ cpustate->extra_cycles = 0;
- return cycles - i8086_ICount;
+ return cycles - cpustate->icount;
}
@@ -288,32 +284,39 @@ static CPU_DISASSEMBLE( i8086 )
static CPU_EXECUTE( i80186 )
{
+ i8086_state *cpustate = device->token;
+
+ cpustate->base[CS] = SegBase(CS);
+ cpustate->base[DS] = SegBase(DS);
+ cpustate->base[ES] = SegBase(ES);
+ cpustate->base[SS] = SegBase(SS);
+
/* copy over the cycle counts if they're not correct */
if (timing.id != 80186)
timing = i80186_cycles;
/* adjust for any interrupts that came in */
- i8086_ICount = cycles;
- i8086_ICount -= I.extra_cycles;
- I.extra_cycles = 0;
+ cpustate->icount = cycles;
+ cpustate->icount -= cpustate->extra_cycles;
+ cpustate->extra_cycles = 0;
/* run until we're out */
- while (i8086_ICount > 0)
+ while (cpustate->icount > 0)
{
- LOG(("[%04x:%04x]=%02x\tAX=%04x\tBX=%04x\tCX=%04x\tDX=%04x\n", I.sregs[CS], I.pc, ReadByte(I.pc), I.regs.w[AX],
- I.regs.w[BX], I.regs.w[CX], I.regs.w[DX]));
- debugger_instruction_hook(device, I.pc);
+ LOG(("[%04x:%04x]=%02x\tAX=%04x\tBX=%04x\tCX=%04x\tDX=%04x\n", cpustate->sregs[CS], cpustate->pc, ReadByte(cpustate->pc), cpustate->regs.w[AX],
+ cpustate->regs.w[BX], cpustate->regs.w[CX], cpustate->regs.w[DX]));
+ debugger_instruction_hook(device, cpustate->pc);
- seg_prefix = FALSE;
- I.prevpc = I.pc;
+ cpustate->seg_prefix = FALSE;
+ cpustate->prevpc = cpustate->pc;
TABLE186;
}
/* adjust for any interrupts that came in */
- i8086_ICount -= I.extra_cycles;
- I.extra_cycles = 0;
+ cpustate->icount -= cpustate->extra_cycles;
+ cpustate->extra_cycles = 0;
- return cycles - i8086_ICount;
+ return cycles - cpustate->icount;
}
#endif
@@ -326,49 +329,51 @@ static CPU_EXECUTE( i80186 )
static CPU_SET_INFO( i8086 )
{
+ i8086_state *cpustate = device->token;
+
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
- case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(0, info->i); break;
- case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(INPUT_LINE_NMI, info->i); break;
- case CPUINFO_INT_INPUT_STATE + INPUT_LINE_TEST: set_test_line(info->i); break; /* PJB 03/05 */
+ case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(cpustate, 0, info->i); break;
+ case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break;
+ case CPUINFO_INT_INPUT_STATE + INPUT_LINE_TEST: set_test_line(cpustate, info->i); break; /* PJB 03/05 */
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + I8086_PC:
- if (info->i - I.base[CS] >= 0x10000)
+ if (info->i - cpustate->base[CS] >= 0x10000)
{
- I.base[CS] = info->i & 0xffff0;
- I.sregs[CS] = I.base[CS] >> 4;
+ cpustate->base[CS] = info->i & 0xffff0;
+ cpustate->sregs[CS] = cpustate->base[CS] >> 4;
}
- I.pc = info->i;
+ cpustate->pc = info->i;
break;
- case CPUINFO_INT_REGISTER + I8086_IP: I.pc = I.base[CS] + info->i; break;
+ case CPUINFO_INT_REGISTER + I8086_IP: cpustate->pc = cpustate->base[CS] + info->i; break;
case CPUINFO_INT_SP:
- if (info->i - I.base[SS] < 0x10000)
+ if (info->i - cpustate->base[SS] < 0x10000)
{
- I.regs.w[SP] = info->i - I.base[SS];
+ cpustate->regs.w[SP] = info->i - cpustate->base[SS];
}
else
{
- I.base[SS] = info->i & 0xffff0;
- I.sregs[SS] = I.base[SS] >> 4;
- I.regs.w[SP] = info->i & 0x0000f;
+ cpustate->base[SS] = info->i & 0xffff0;
+ cpustate->sregs[SS] = cpustate->base[SS] >> 4;
+ cpustate->regs.w[SP] = info->i & 0x0000f;
}
break;
- case CPUINFO_INT_REGISTER + I8086_SP: I.regs.w[SP] = info->i; break;
- case CPUINFO_INT_REGISTER + I8086_FLAGS: I.flags = info->i; ExpandFlags(info->i); break;
- case CPUINFO_INT_REGISTER + I8086_AX: I.regs.w[AX] = info->i; break;
- case CPUINFO_INT_REGISTER + I8086_CX: I.regs.w[CX] = info->i; break;
- case CPUINFO_INT_REGISTER + I8086_DX: I.regs.w[DX] = info->i; break;
- case CPUINFO_INT_REGISTER + I8086_BX: I.regs.w[BX] = info->i; break;
- case CPUINFO_INT_REGISTER + I8086_BP: I.regs.w[BP] = info->i; break;
- case CPUINFO_INT_REGISTER + I8086_SI: I.regs.w[SI] = info->i; break;
- case CPUINFO_INT_REGISTER + I8086_DI: I.regs.w[DI] = info->i; break;
- case CPUINFO_INT_REGISTER + I8086_ES: I.sregs[ES] = info->i; I.base[ES] = SegBase(ES); break;
- case CPUINFO_INT_REGISTER + I8086_CS: I.sregs[CS] = info->i; I.base[CS] = SegBase(CS); break;
- case CPUINFO_INT_REGISTER + I8086_SS: I.sregs[SS] = info->i; I.base[SS] = SegBase(SS); break;
- case CPUINFO_INT_REGISTER + I8086_DS: I.sregs[DS] = info->i; I.base[DS] = SegBase(DS); break;
- case CPUINFO_INT_REGISTER + I8086_VECTOR: I.int_vector = info->i; break;
+ case CPUINFO_INT_REGISTER + I8086_SP: cpustate->regs.w[SP] = info->i; break;
+ case CPUINFO_INT_REGISTER + I8086_FLAGS: cpustate->flags = info->i; ExpandFlags(info->i); break;
+ case CPUINFO_INT_REGISTER + I8086_AX: cpustate->regs.w[AX] = info->i; break;
+ case CPUINFO_INT_REGISTER + I8086_CX: cpustate->regs.w[CX] = info->i; break;
+ case CPUINFO_INT_REGISTER + I8086_DX: cpustate->regs.w[DX] = info->i; break;
+ case CPUINFO_INT_REGISTER + I8086_BX: cpustate->regs.w[BX] = info->i; break;
+ case CPUINFO_INT_REGISTER + I8086_BP: cpustate->regs.w[BP] = info->i; break;
+ case CPUINFO_INT_REGISTER + I8086_SI: cpustate->regs.w[SI] = info->i; break;
+ case CPUINFO_INT_REGISTER + I8086_DI: cpustate->regs.w[DI] = info->i; break;
+ case CPUINFO_INT_REGISTER + I8086_ES: cpustate->sregs[ES] = info->i; cpustate->base[ES] = SegBase(ES); break;
+ case CPUINFO_INT_REGISTER + I8086_CS: cpustate->sregs[CS] = info->i; cpustate->base[CS] = SegBase(CS); break;
+ case CPUINFO_INT_REGISTER + I8086_SS: cpustate->sregs[SS] = info->i; cpustate->base[SS] = SegBase(SS); break;
+ case CPUINFO_INT_REGISTER + I8086_DS: cpustate->sregs[DS] = info->i; cpustate->base[DS] = SegBase(DS); break;
+ case CPUINFO_INT_REGISTER + I8086_VECTOR: cpustate->int_vector = info->i; break;
}
}
@@ -380,10 +385,12 @@ static CPU_SET_INFO( i8086 )
CPU_GET_INFO( i8086 )
{
+ i8086_state *cpustate = (device != NULL) ? device->token : NULL;
+
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
- case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(I); break;
+ case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(i8086_state); break;
case CPUINFO_INT_INPUT_LINES: info->i = 1; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0xff; break;
case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
@@ -404,88 +411,88 @@ CPU_GET_INFO( i8086 )
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 16; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
- case CPUINFO_INT_INPUT_STATE + 0: info->i = I.irq_state; break;
- case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = I.nmi_state; break;
+ case CPUINFO_INT_INPUT_STATE + 0: info->i = cpustate->irq_state; break;
+ case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = cpustate->nmi_state; break;
- case CPUINFO_INT_INPUT_STATE + INPUT_LINE_TEST: info->i = I.test_state; break; /* PJB 03/05 */
+ case CPUINFO_INT_INPUT_STATE + INPUT_LINE_TEST: info->i = cpustate->test_state; break; /* PJB 03/05 */
- case CPUINFO_INT_PREVIOUSPC: info->i = I.prevpc; break;
+ case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->prevpc; break;
case CPUINFO_INT_PC:
- case CPUINFO_INT_REGISTER + I8086_PC: info->i = I.pc; break;
- case CPUINFO_INT_REGISTER + I8086_IP: info->i = I.pc - I.base[CS]; break;
- case CPUINFO_INT_SP: info->i = I.base[SS] + I.regs.w[SP]; break;
- case CPUINFO_INT_REGISTER + I8086_SP: info->i = I.regs.w[SP]; break;
- case CPUINFO_INT_REGISTER + I8086_FLAGS: I.flags = CompressFlags(); info->i = I.flags; break;
- case CPUINFO_INT_REGISTER + I8086_AX: info->i = I.regs.w[AX]; break;
- case CPUINFO_INT_REGISTER + I8086_CX: info->i = I.regs.w[CX]; break;
- case CPUINFO_INT_REGISTER + I8086_DX: info->i = I.regs.w[DX]; break;
- case CPUINFO_INT_REGISTER + I8086_BX: info->i = I.regs.w[BX]; break;
- case CPUINFO_INT_REGISTER + I8086_BP: info->i = I.regs.w[BP]; break;
- case CPUINFO_INT_REGISTER + I8086_SI: info->i = I.regs.w[SI]; break;
- case CPUINFO_INT_REGISTER + I8086_DI: info->i = I.regs.w[DI]; break;
- case CPUINFO_INT_REGISTER + I8086_ES: info->i = I.sregs[ES]; break;
- case CPUINFO_INT_REGISTER + I8086_CS: info->i = I.sregs[CS]; break;
- case CPUINFO_INT_REGISTER + I8086_SS: info->i = I.sregs[SS]; break;
- case CPUINFO_INT_REGISTER + I8086_DS: info->i = I.sregs[DS]; break;
- case CPUINFO_INT_REGISTER + I8086_VECTOR: info->i = I.int_vector; break;
+ case CPUINFO_INT_REGISTER + I8086_PC: info->i = cpustate->pc; break;
+ case CPUINFO_INT_REGISTER + I8086_IP: info->i = cpustate->pc - cpustate->base[CS]; break;
+ case CPUINFO_INT_SP: info->i = cpustate->base[SS] + cpustate->regs.w[SP]; break;
+ case CPUINFO_INT_REGISTER + I8086_SP: info->i = cpustate->regs.w[SP]; break;
+ case CPUINFO_INT_REGISTER + I8086_FLAGS: cpustate->flags = CompressFlags(); info->i = cpustate->flags; break;
+ case CPUINFO_INT_REGISTER + I8086_AX: info->i = cpustate->regs.w[AX]; break;
+ case CPUINFO_INT_REGISTER + I8086_CX: info->i = cpustate->regs.w[CX]; break;
+ case CPUINFO_INT_REGISTER + I8086_DX: info->i = cpustate->regs.w[DX]; break;
+ case CPUINFO_INT_REGISTER + I8086_BX: info->i = cpustate->regs.w[BX]; break;
+ case CPUINFO_INT_REGISTER + I8086_BP: info->i = cpustate->regs.w[BP]; break;
+ case CPUINFO_INT_REGISTER + I8086_SI: info->i = cpustate->regs.w[SI]; break;
+ case CPUINFO_INT_REGISTER + I8086_DI: info->i = cpustate->regs.w[DI]; break;
+ case CPUINFO_INT_REGISTER + I8086_ES: info->i = cpustate->sregs[ES]; break;
+ case CPUINFO_INT_REGISTER + I8086_CS: info->i = cpustate->sregs[CS]; break;
+ case CPUINFO_INT_REGISTER + I8086_SS: info->i = cpustate->sregs[SS]; break;
+ case CPUINFO_INT_REGISTER + I8086_DS: info->i = cpustate->sregs[DS]; break;
+ case CPUINFO_INT_REGISTER + I8086_VECTOR: info->i = cpustate->int_vector; break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(i8086); break;
- case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(i8086); break;
- case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(i8086); break;
+ case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(dummy); break;
+ case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(dummy); break;
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i8086); break;
case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(i8086); break;
case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(i8086); break;
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(i8086); break;
case CPUINFO_PTR_BURN: info->burn = NULL; break;
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i8086); break;
- case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &i8086_ICount; break;
+ case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "8086"); break;
case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "Intel 80x86"); break;
case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "1.4"); break;
case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
- case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Real mode i286 emulator v1.4 by Fabrice Frances\n(initial work I.based on David Hedley's pcemu)"); break;
+ case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Real mode i286 emulator v1.4 by Fabrice Frances\n(initial work cpustate->based on David Hedley's pcemu)"); break;
case CPUINFO_STR_FLAGS:
- I.flags = CompressFlags();
+ cpustate->flags = CompressFlags();
sprintf(info->s, "%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
- I.flags & 0x8000 ? '?' : '.',
- I.flags & 0x4000 ? '?' : '.',
- I.flags & 0x2000 ? '?' : '.',
- I.flags & 0x1000 ? '?' : '.',
- I.flags & 0x0800 ? 'O' : '.',
- I.flags & 0x0400 ? 'D' : '.',
- I.flags & 0x0200 ? 'I' : '.',
- I.flags & 0x0100 ? 'T' : '.',
- I.flags & 0x0080 ? 'S' : '.',
- I.flags & 0x0040 ? 'Z' : '.',
- I.flags & 0x0020 ? '?' : '.',
- I.flags & 0x0010 ? 'A' : '.',
- I.flags & 0x0008 ? '?' : '.',
- I.flags & 0x0004 ? 'P' : '.',
- I.flags & 0x0002 ? 'N' : '.',
- I.flags & 0x0001 ? 'C' : '.');
+ cpustate->flags & 0x8000 ? '?' : '.',
+ cpustate->flags & 0x4000 ? '?' : '.',
+ cpustate->flags & 0x2000 ? '?' : '.',
+ cpustate->flags & 0x1000 ? '?' : '.',
+ cpustate->flags & 0x0800 ? 'O' : '.',
+ cpustate->flags & 0x0400 ? 'D' : '.',
+ cpustate->flags & 0x0200 ? 'I' : '.',
+ cpustate->flags & 0x0100 ? 'T' : '.',
+ cpustate->flags & 0x0080 ? 'S' : '.',
+ cpustate->flags & 0x0040 ? 'Z' : '.',
+ cpustate->flags & 0x0020 ? '?' : '.',
+ cpustate->flags & 0x0010 ? 'A' : '.',
+ cpustate->flags & 0x0008 ? '?' : '.',
+ cpustate->flags & 0x0004 ? 'P' : '.',
+ cpustate->flags & 0x0002 ? 'N' : '.',
+ cpustate->flags & 0x0001 ? 'C' : '.');
break;
- case CPUINFO_STR_REGISTER + I8086_PC: sprintf(info->s, "PC:%04X", I.pc); break;
- case CPUINFO_STR_REGISTER + I8086_IP: sprintf(info->s, "IP: %04X", I.pc - I.base[CS]); break;
- case CPUINFO_STR_REGISTER + I8086_SP: sprintf(info->s, "SP: %04X", I.regs.w[SP]); break;
- case CPUINFO_STR_REGISTER + I8086_FLAGS: sprintf(info->s, "F:%04X", I.flags); break;
- case CPUINFO_STR_REGISTER + I8086_AX: sprintf(info->s, "AX:%04X", I.regs.w[AX]); break;
- case CPUINFO_STR_REGISTER + I8086_CX: sprintf(info->s, "CX:%04X", I.regs.w[CX]); break;
- case CPUINFO_STR_REGISTER + I8086_DX: sprintf(info->s, "DX:%04X", I.regs.w[DX]); break;
- case CPUINFO_STR_REGISTER + I8086_BX: sprintf(info->s, "BX:%04X", I.regs.w[BX]); break;
- case CPUINFO_STR_REGISTER + I8086_BP: sprintf(info->s, "BP:%04X", I.regs.w[BP]); break;
- case CPUINFO_STR_REGISTER + I8086_SI: sprintf(info->s, "SI: %04X", I.regs.w[SI]); break;
- case CPUINFO_STR_REGISTER + I8086_DI: sprintf(info->s, "DI: %04X", I.regs.w[DI]); break;
- case CPUINFO_STR_REGISTER + I8086_ES: sprintf(info->s, "ES:%04X", I.sregs[ES]); break;
- case CPUINFO_STR_REGISTER + I8086_CS: sprintf(info->s, "CS:%04X", I.sregs[CS]); break;
- case CPUINFO_STR_REGISTER + I8086_SS: sprintf(info->s, "SS:%04X", I.sregs[SS]); break;
- case CPUINFO_STR_REGISTER + I8086_DS: sprintf(info->s, "DS:%04X", I.sregs[DS]); break;
- case CPUINFO_STR_REGISTER + I8086_VECTOR: sprintf(info->s, "V:%02X", I.int_vector); break;
+ case CPUINFO_STR_REGISTER + I8086_PC: sprintf(info->s, "PC:%04X", cpustate->pc); break;
+ case CPUINFO_STR_REGISTER + I8086_IP: sprintf(info->s, "IP: %04X", cpustate->pc - cpustate->base[CS]); break;
+ case CPUINFO_STR_REGISTER + I8086_SP: sprintf(info->s, "SP: %04X", cpustate->regs.w[SP]); break;
+ case CPUINFO_STR_REGISTER + I8086_FLAGS: sprintf(info->s, "F:%04X", cpustate->flags); break;
+ case CPUINFO_STR_REGISTER + I8086_AX: sprintf(info->s, "AX:%04X", cpustate->regs.w[AX]); break;
+ case CPUINFO_STR_REGISTER + I8086_CX: sprintf(info->s, "CX:%04X", cpustate->regs.w[CX]); break;
+ case CPUINFO_STR_REGISTER + I8086_DX: sprintf(info->s, "DX:%04X", cpustate->regs.w[DX]); break;
+ case CPUINFO_STR_REGISTER + I8086_BX: sprintf(info->s, "BX:%04X", cpustate->regs.w[BX]); break;
+ case CPUINFO_STR_REGISTER + I8086_BP: sprintf(info->s, "BP:%04X", cpustate->regs.w[BP]); break;
+ case CPUINFO_STR_REGISTER + I8086_SI: sprintf(info->s, "SI: %04X", cpustate->regs.w[SI]); break;
+ case CPUINFO_STR_REGISTER + I8086_DI: sprintf(info->s, "DI: %04X", cpustate->regs.w[DI]); break;
+ case CPUINFO_STR_REGISTER + I8086_ES: sprintf(info->s, "ES:%04X", cpustate->sregs[ES]); break;
+ case CPUINFO_STR_REGISTER + I8086_CS: sprintf(info->s, "CS:%04X", cpustate->sregs[CS]); break;
+ case CPUINFO_STR_REGISTER + I8086_SS: sprintf(info->s, "SS:%04X", cpustate->sregs[SS]); break;
+ case CPUINFO_STR_REGISTER + I8086_DS: sprintf(info->s, "DS:%04X", cpustate->sregs[DS]); break;
+ case CPUINFO_STR_REGISTER + I8086_VECTOR: sprintf(info->s, "V:%02X", cpustate->int_vector); break;
}
}
diff --git a/src/emu/cpu/i86/i86.h b/src/emu/cpu/i86/i86.h
index 4b0334ca3fd..d5312e374d2 100644
--- a/src/emu/cpu/i86/i86.h
+++ b/src/emu/cpu/i86/i86.h
@@ -27,24 +27,24 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,SIH,SIL,DIH,DIL } BREGS;
/* parameter x = result, y = source 1, z = source 2 */
-#define SetTF(x) (I.TF = (x))
-#define SetIF(x) (I.IF = (x))
-#define SetDF(x) (I.DirVal = (x) ? -1 : 1)
+#define SetTF(x) (cpustate->TF = (x))
+#define SetIF(x) (cpustate->IF = (x))
+#define SetDF(x) (cpustate->DirVal = (x) ? -1 : 1)
-#define SetOFW_Add(x,y,z) (I.OverVal = ((x) ^ (y)) & ((x) ^ (z)) & 0x8000)
-#define SetOFB_Add(x,y,z) (I.OverVal = ((x) ^ (y)) & ((x) ^ (z)) & 0x80)
-#define SetOFW_Sub(x,y,z) (I.OverVal = ((z) ^ (y)) & ((z) ^ (x)) & 0x8000)
-#define SetOFB_Sub(x,y,z) (I.OverVal = ((z) ^ (y)) & ((z) ^ (x)) & 0x80)
+#define SetOFW_Add(x,y,z) (cpustate->OverVal = ((x) ^ (y)) & ((x) ^ (z)) & 0x8000)
+#define SetOFB_Add(x,y,z) (cpustate->OverVal = ((x) ^ (y)) & ((x) ^ (z)) & 0x80)
+#define SetOFW_Sub(x,y,z) (cpustate->OverVal = ((z) ^ (y)) & ((z) ^ (x)) & 0x8000)
+#define SetOFB_Sub(x,y,z) (cpustate->OverVal = ((z) ^ (y)) & ((z) ^ (x)) & 0x80)
-#define SetCFB(x) (I.CarryVal = (x) & 0x100)
-#define SetCFW(x) (I.CarryVal = (x) & 0x10000)
-#define SetAF(x,y,z) (I.AuxVal = ((x) ^ ((y) ^ (z))) & 0x10)
-#define SetSF(x) (I.SignVal = (x))
-#define SetZF(x) (I.ZeroVal = (x))
-#define SetPF(x) (I.ParityVal = (x))
+#define SetCFB(x) (cpustate->CarryVal = (x) & 0x100)
+#define SetCFW(x) (cpustate->CarryVal = (x) & 0x10000)
+#define SetAF(x,y,z) (cpustate->AuxVal = ((x) ^ ((y) ^ (z))) & 0x10)
+#define SetSF(x) (cpustate->SignVal = (x))
+#define SetZF(x) (cpustate->ZeroVal = (x))
+#define SetPF(x) (cpustate->ParityVal = (x))
-#define SetSZPF_Byte(x) (I.ParityVal = I.SignVal = I.ZeroVal = (INT8)(x))
-#define SetSZPF_Word(x) (I.ParityVal = I.SignVal = I.ZeroVal = (INT16)(x))
+#define SetSZPF_Byte(x) (cpustate->ParityVal = cpustate->SignVal = cpustate->ZeroVal = (INT8)(x))
+#define SetSZPF_Word(x) (cpustate->ParityVal = cpustate->SignVal = cpustate->ZeroVal = (INT16)(x))
#define ADDB(dst,src) { unsigned res=dst+src; SetCFB(res); SetOFB_Add(res,src,dst); SetAF(res,src,dst); SetSZPF_Byte(res); dst=(BYTE)res; }
#define ADDW(dst,src) { unsigned res=dst+src; SetCFW(res); SetOFW_Add(res,src,dst); SetAF(res,src,dst); SetSZPF_Word(res); dst=(WORD)res; }
@@ -52,40 +52,40 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,SIH,SIL,DIH,DIL } BREGS;
#define SUBB(dst,src) { unsigned res=dst-src; SetCFB(res); SetOFB_Sub(res,src,dst); SetAF(res,src,dst); SetSZPF_Byte(res); dst=(BYTE)res; }
#define SUBW(dst,src) { unsigned res=dst-src; SetCFW(res); SetOFW_Sub(res,src,dst); SetAF(res,src,dst); SetSZPF_Word(res); dst=(WORD)res; }
-#define ORB(dst,src) dst |= src; I.CarryVal = I.OverVal = I.AuxVal = 0; SetSZPF_Byte(dst)
-#define ORW(dst,src) dst |= src; I.CarryVal = I.OverVal = I.AuxVal = 0; SetSZPF_Word(dst)
+#define ORB(dst,src) dst |= src; cpustate->CarryVal = cpustate->OverVal = cpustate->AuxVal = 0; SetSZPF_Byte(dst)
+#define ORW(dst,src) dst |= src; cpustate->CarryVal = cpustate->OverVal = cpustate->AuxVal = 0; SetSZPF_Word(dst)
-#define ANDB(dst,src) dst &= src; I.CarryVal = I.OverVal = I.AuxVal = 0; SetSZPF_Byte(dst)
-#define ANDW(dst,src) dst &= src; I.CarryVal = I.OverVal = I.AuxVal = 0; SetSZPF_Word(dst)
+#define ANDB(dst,src) dst &= src; cpustate->CarryVal = cpustate->OverVal = cpustate->AuxVal = 0; SetSZPF_Byte(dst)
+#define ANDW(dst,src) dst &= src; cpustate->CarryVal = cpustate->OverVal = cpustate->AuxVal = 0; SetSZPF_Word(dst)
-#define XORB(dst,src) dst ^= src; I.CarryVal = I.OverVal = I.AuxVal = 0; SetSZPF_Byte(dst)
-#define XORW(dst,src) dst ^= src; I.CarryVal = I.OverVal = I.AuxVal = 0; SetSZPF_Word(dst)
+#define XORB(dst,src) dst ^= src; cpustate->CarryVal = cpustate->OverVal = cpustate->AuxVal = 0; SetSZPF_Byte(dst)
+#define XORW(dst,src) dst ^= src; cpustate->CarryVal = cpustate->OverVal = cpustate->AuxVal = 0; SetSZPF_Word(dst)
-#define CF (I.CarryVal != 0)
-#define SF (I.SignVal < 0)
-#define ZF (I.ZeroVal == 0)
-#define PF parity_table[I.ParityVal]
-#define AF (I.AuxVal != 0)
-#define OF (I.OverVal != 0)
-#define DF (I.DirVal < 0)
+#define CF (cpustate->CarryVal != 0)
+#define SF (cpustate->SignVal < 0)
+#define ZF (cpustate->ZeroVal == 0)
+#define PF parity_table[cpustate->ParityVal]
+#define AF (cpustate->AuxVal != 0)
+#define OF (cpustate->OverVal != 0)
+#define DF (cpustate->DirVal < 0)
/************************************************************************/
-#define read_byte(a) (*I.mem.rbyte)(I.program, a)
-#define read_word(a) (*I.mem.rword)(I.program, a)
-#define write_byte(a,d) (*I.mem.wbyte)(I.program, (a),(d))
-#define write_word(a,d) (*I.mem.wword)(I.program, (a),(d))
+#define read_byte(a) (*cpustate->mem.rbyte)(cpustate->program, a)
+#define read_word(a) (*cpustate->mem.rword)(cpustate->program, a)
+#define write_byte(a,d) (*cpustate->mem.wbyte)(cpustate->program, (a),(d))
+#define write_word(a,d) (*cpustate->mem.wword)(cpustate->program, (a),(d))
-#define read_port_byte(a) (*I.mem.rbyte)(I.io, a)
-#define read_port_word(a) (*I.mem.rword)(I.io, a)
-#define write_port_byte(a,d) (*I.mem.wbyte)(I.io, (a),(d))
-#define write_port_word(a,d) (*I.mem.wword)(I.io, (a),(d))
+#define read_port_byte(a) (*cpustate->mem.rbyte)(cpustate->io, a)
+#define read_port_word(a) (*cpustate->mem.rword)(cpustate->io, a)
+#define write_port_byte(a,d) (*cpustate->mem.wbyte)(cpustate->io, (a),(d))
+#define write_port_word(a,d) (*cpustate->mem.wword)(cpustate->io, (a),(d))
/************************************************************************/
-#define SegBase(Seg) (I.sregs[Seg] << 4)
+#define SegBase(Seg) (cpustate->sregs[Seg] << 4)
-#define DefaultBase(Seg) ((seg_prefix && (Seg == DS || Seg == SS)) ? prefix_base : I.base[Seg])
+#define DefaultBase(Seg) ((cpustate->seg_prefix && (Seg == DS || Seg == SS)) ? cpustate->prefix_base : cpustate->base[Seg])
#define GetMemB(Seg,Off) (read_byte((DefaultBase(Seg) + (Off)) & AMASK))
#define GetMemW(Seg,Off) (read_word((DefaultBase(Seg) + (Off)) & AMASK))
@@ -98,32 +98,32 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,SIH,SIL,DIH,DIL } BREGS;
#define WriteByte(ea,val) write_byte((ea) & AMASK, val);
#define WriteWord(ea,val) write_word((ea) & AMASK, val);
-#define FETCH_XOR(a) ((a) ^ I.mem.fetch_xor)
-#define FETCH (memory_raw_read_byte(I.program, FETCH_XOR(I.pc++)))
-#define FETCHOP (memory_decrypted_read_byte(I.program, FETCH_XOR(I.pc++)))
-#define PEEKOP(addr) (memory_decrypted_read_byte(I.program, FETCH_XOR(addr)))
-#define FETCHWORD(var) { var = memory_raw_read_byte(I.program, FETCH_XOR(I.pc)); var += (memory_raw_read_byte(I.program, FETCH_XOR(I.pc + 1)) << 8); I.pc += 2; }
+#define FETCH_XOR(a) ((a) ^ cpustate->mem.fetch_xor)
+#define FETCH (memory_raw_read_byte(cpustate->program, FETCH_XOR(cpustate->pc++)))
+#define FETCHOP (memory_decrypted_read_byte(cpustate->program, FETCH_XOR(cpustate->pc++)))
+#define PEEKOP(addr) (memory_decrypted_read_byte(cpustate->program, FETCH_XOR(addr)))
+#define FETCHWORD(var) { var = memory_raw_read_byte(cpustate->program, FETCH_XOR(cpustate->pc)); var += (memory_raw_read_byte(cpustate->program, FETCH_XOR(cpustate->pc + 1)) << 8); cpustate->pc += 2; }
#define CHANGE_PC(addr)
-#define PUSH(val) { I.regs.w[SP] -= 2; WriteWord(((I.base[SS] + I.regs.w[SP]) & AMASK), val); }
-#define POP(var) { var = ReadWord(((I.base[SS] + I.regs.w[SP]) & AMASK)); I.regs.w[SP] += 2; }
+#define PUSH(val) { cpustate->regs.w[SP] -= 2; WriteWord(((cpustate->base[SS] + cpustate->regs.w[SP]) & AMASK), val); }
+#define POP(var) { var = ReadWord(((cpustate->base[SS] + cpustate->regs.w[SP]) & AMASK)); cpustate->regs.w[SP] += 2; }
/************************************************************************/
#define CompressFlags() (WORD)(CF | (PF << 2) | (AF << 4) | (ZF << 6) \
- | (SF << 7) | (I.TF << 8) | (I.IF << 9) \
+ | (SF << 7) | (cpustate->TF << 8) | (cpustate->IF << 9) \
| (DF << 10) | (OF << 11))
#define ExpandFlags(f) \
{ \
- I.CarryVal = (f) & 1; \
- I.ParityVal = !((f) & 4); \
- I.AuxVal = (f) & 16; \
- I.ZeroVal = !((f) & 64); \
- I.SignVal = ((f) & 128) ? -1 : 0; \
- I.TF = ((f) & 256) >> 8; \
- I.IF = ((f) & 512) >> 9; \
- I.DirVal = ((f) & 1024) ? -1 : 1; \
- I.OverVal = (f) & 2048; \
+ cpustate->CarryVal = (f) & 1; \
+ cpustate->ParityVal = !((f) & 4); \
+ cpustate->AuxVal = (f) & 16; \
+ cpustate->ZeroVal = !((f) & 64); \
+ cpustate->SignVal = ((f) & 128) ? -1 : 0; \
+ cpustate->TF = ((f) & 256) >> 8; \
+ cpustate->IF = ((f) & 512) >> 9; \
+ cpustate->DirVal = ((f) & 1024) ? -1 : 1; \
+ cpustate->OverVal = (f) & 2048; \
}
#endif /* __I86_H__ */
diff --git a/src/emu/cpu/i86/i86mem.c b/src/emu/cpu/i86/i86mem.c
index 003627d16ad..572203b0036 100644
--- a/src/emu/cpu/i86/i86mem.c
+++ b/src/emu/cpu/i86/i86mem.c
@@ -4,14 +4,14 @@
#ifdef I8086
#if (HAS_I8088||HAS_I80188)
-static void configure_memory_8bit(void)
+static void configure_memory_8bit(i8086_state *cpustate)
{
- I.mem.fetch_xor = 0;
+ cpustate->mem.fetch_xor = 0;
- I.mem.rbyte = memory_read_byte_8le;
- I.mem.rword = memory_read_word_8le;
- I.mem.wbyte = memory_write_byte_8le;
- I.mem.wword = memory_write_word_8le;
+ cpustate->mem.rbyte = memory_read_byte_8le;
+ cpustate->mem.rword = memory_read_word_8le;
+ cpustate->mem.wbyte = memory_write_byte_8le;
+ cpustate->mem.wword = memory_write_word_8le;
}
#endif
#endif
@@ -43,12 +43,12 @@ static void write_word_16le(const address_space *space, offs_t addr, UINT16 data
}
}
-static void configure_memory_16bit(void)
+static void configure_memory_16bit(i8086_state *cpustate)
{
- I.mem.fetch_xor = BYTE_XOR_LE(0);
+ cpustate->mem.fetch_xor = BYTE_XOR_LE(0);
- I.mem.rbyte = memory_read_byte_16le;
- I.mem.rword = read_word_16le;
- I.mem.wbyte = memory_write_byte_16le;
- I.mem.wword = write_word_16le;
+ cpustate->mem.rbyte = memory_read_byte_16le;
+ cpustate->mem.rword = read_word_16le;
+ cpustate->mem.wbyte = memory_write_byte_16le;
+ cpustate->mem.wword = write_word_16le;
}
diff --git a/src/emu/cpu/i86/instr186.c b/src/emu/cpu/i86/instr186.c
index a3d4794b9f2..d391bdce04f 100644
--- a/src/emu/cpu/i86/instr186.c
+++ b/src/emu/cpu/i86/instr186.c
@@ -9,53 +9,53 @@
#undef ICOUNT
-#define ICOUNT i8086_ICount
+#define ICOUNT cpustate->icount
-static void PREFIX186(_pusha)(void) /* Opcode 0x60 */
+static void PREFIX186(_pusha)(i8086_state *cpustate) /* Opcode 0x60 */
{
- unsigned tmp=I.regs.w[SP];
+ unsigned tmp=cpustate->regs.w[SP];
ICOUNT -= timing.pusha;
- PUSH(I.regs.w[AX]);
- PUSH(I.regs.w[CX]);
- PUSH(I.regs.w[DX]);
- PUSH(I.regs.w[BX]);
+ PUSH(cpustate->regs.w[AX]);
+ PUSH(cpustate->regs.w[CX]);
+ PUSH(cpustate->regs.w[DX]);
+ PUSH(cpustate->regs.w[BX]);
PUSH(tmp);
- PUSH(I.regs.w[BP]);
- PUSH(I.regs.w[SI]);
- PUSH(I.regs.w[DI]);
+ PUSH(cpustate->regs.w[BP]);
+ PUSH(cpustate->regs.w[SI]);
+ PUSH(cpustate->regs.w[DI]);
}
-static void PREFIX186(_popa)(void) /* Opcode 0x61 */
+static void PREFIX186(_popa)(i8086_state *cpustate) /* Opcode 0x61 */
{
unsigned tmp;
ICOUNT -= timing.popa;
- POP(I.regs.w[DI]);
- POP(I.regs.w[SI]);
- POP(I.regs.w[BP]);
+ POP(cpustate->regs.w[DI]);
+ POP(cpustate->regs.w[SI]);
+ POP(cpustate->regs.w[BP]);
POP(tmp);
- POP(I.regs.w[BX]);
- POP(I.regs.w[DX]);
- POP(I.regs.w[CX]);
- POP(I.regs.w[AX]);
+ POP(cpustate->regs.w[BX]);
+ POP(cpustate->regs.w[DX]);
+ POP(cpustate->regs.w[CX]);
+ POP(cpustate->regs.w[AX]);
}
-static void PREFIX186(_bound)(void) /* Opcode 0x62 */
+static void PREFIX186(_bound)(i8086_state *cpustate) /* Opcode 0x62 */
{
unsigned ModRM = FETCHOP;
int low = (INT16)GetRMWord(ModRM);
int high= (INT16)GetnextRMWord;
int tmp= (INT16)RegWord(ModRM);
if (tmp<low || tmp>high) {
- I.pc-=2;
- PREFIX86(_interrupt)(5);
+ cpustate->pc-=2;
+ PREFIX86(_interrupt)(cpustate, 5);
}
ICOUNT -= timing.bound;
}
-static void PREFIX186(_push_d16)(void) /* Opcode 0x68 */
+static void PREFIX186(_push_d16)(i8086_state *cpustate) /* Opcode 0x68 */
{
unsigned tmp = FETCH;
@@ -64,7 +64,7 @@ static void PREFIX186(_push_d16)(void) /* Opcode 0x68 */
PUSH(tmp);
}
-static void PREFIX186(_imul_d16)(void) /* Opcode 0x69 */
+static void PREFIX186(_imul_d16)(i8086_state *cpustate) /* Opcode 0x69 */
{
DEF_r16w(dst,src);
unsigned src2=FETCH;
@@ -73,12 +73,12 @@ static void PREFIX186(_imul_d16)(void) /* Opcode 0x69 */
ICOUNT -= (ModRM >= 0xc0) ? timing.imul_rri16 : timing.imul_rmi16;
dst = (INT32)((INT16)src)*(INT32)((INT16)src2);
- I.CarryVal = I.OverVal = (((INT32)dst) >> 15 != 0) && (((INT32)dst) >> 15 != -1);
+ cpustate->CarryVal = cpustate->OverVal = (((INT32)dst) >> 15 != 0) && (((INT32)dst) >> 15 != -1);
RegWord(ModRM)=(WORD)dst;
}
-static void PREFIX186(_push_d8)(void) /* Opcode 0x6a */
+static void PREFIX186(_push_d8)(i8086_state *cpustate) /* Opcode 0x6a */
{
unsigned tmp = (WORD)((INT16)((INT8)FETCH));
@@ -86,7 +86,7 @@ static void PREFIX186(_push_d8)(void) /* Opcode 0x6a */
PUSH(tmp);
}
-static void PREFIX186(_imul_d8)(void) /* Opcode 0x6b */
+static void PREFIX186(_imul_d8)(i8086_state *cpustate) /* Opcode 0x6b */
{
DEF_r16w(dst,src);
unsigned src2= (WORD)((INT16)((INT8)FETCH));
@@ -94,72 +94,72 @@ static void PREFIX186(_imul_d8)(void) /* Opcode 0x6b */
ICOUNT -= (ModRM >= 0xc0) ? timing.imul_rri8 : timing.imul_rmi8;
dst = (INT32)((INT16)src)*(INT32)((INT16)src2);
- I.CarryVal = I.OverVal = (((INT32)dst) >> 15 != 0) && (((INT32)dst) >> 15 != -1);
+ cpustate->CarryVal = cpustate->OverVal = (((INT32)dst) >> 15 != 0) && (((INT32)dst) >> 15 != -1);
RegWord(ModRM)=(WORD)dst;
}
-static void PREFIX186(_insb)(void) /* Opcode 0x6c */
+static void PREFIX186(_insb)(i8086_state *cpustate) /* Opcode 0x6c */
{
ICOUNT -= timing.ins8;
- PutMemB(ES,I.regs.w[DI],read_port_byte(I.regs.w[DX]));
- I.regs.w[DI] += I.DirVal;
+ PutMemB(ES,cpustate->regs.w[DI],read_port_byte(cpustate->regs.w[DX]));
+ cpustate->regs.w[DI] += cpustate->DirVal;
}
-static void PREFIX186(_insw)(void) /* Opcode 0x6d */
+static void PREFIX186(_insw)(i8086_state *cpustate) /* Opcode 0x6d */
{
ICOUNT -= timing.ins16;
- PutMemW(ES,I.regs.w[DI],read_port_word(I.regs.w[DX]));
- I.regs.w[DI] += 2 * I.DirVal;
+ PutMemW(ES,cpustate->regs.w[DI],read_port_word(cpustate->regs.w[DX]));
+ cpustate->regs.w[DI] += 2 * cpustate->DirVal;
}
-static void PREFIX186(_outsb)(void) /* Opcode 0x6e */
+static void PREFIX186(_outsb)(i8086_state *cpustate) /* Opcode 0x6e */
{
ICOUNT -= timing.outs8;
- write_port_byte(I.regs.w[DX],GetMemB(DS,I.regs.w[SI]));
- I.regs.w[SI] += I.DirVal; /* GOL 11/27/01 */
+ write_port_byte(cpustate->regs.w[DX],GetMemB(DS,cpustate->regs.w[SI]));
+ cpustate->regs.w[SI] += cpustate->DirVal; /* GOL 11/27/01 */
}
-static void PREFIX186(_outsw)(void) /* Opcode 0x6f */
+static void PREFIX186(_outsw)(i8086_state *cpustate) /* Opcode 0x6f */
{
ICOUNT -= timing.outs16;
- write_port_word(I.regs.w[DX],GetMemW(DS,I.regs.w[SI]));
- I.regs.w[SI] += 2 * I.DirVal; /* GOL 11/27/01 */
+ write_port_word(cpustate->regs.w[DX],GetMemW(DS,cpustate->regs.w[SI]));
+ cpustate->regs.w[SI] += 2 * cpustate->DirVal; /* GOL 11/27/01 */
}
-static void PREFIX186(_rotshft_bd8)(void) /* Opcode 0xc0 */
+static void PREFIX186(_rotshft_bd8)(i8086_state *cpustate) /* Opcode 0xc0 */
{
unsigned ModRM = FETCH;
unsigned count = FETCH;
- PREFIX86(_rotate_shift_Byte)(ModRM,count);
+ PREFIX86(_rotate_shift_Byte)(cpustate,ModRM,count);
}
-static void PREFIX186(_rotshft_wd8)(void) /* Opcode 0xc1 */
+static void PREFIX186(_rotshft_wd8)(i8086_state *cpustate) /* Opcode 0xc1 */
{
unsigned ModRM = FETCH;
unsigned count = FETCH;
- PREFIX86(_rotate_shift_Word)(ModRM,count);
+ PREFIX86(_rotate_shift_Word)(cpustate,ModRM,count);
}
-static void PREFIX186(_enter)(void) /* Opcode 0xc8 */
+static void PREFIX186(_enter)(i8086_state *cpustate) /* Opcode 0xc8 */
{
unsigned nb = FETCH; unsigned i,level;
nb += FETCH << 8;
level = FETCH;
ICOUNT -= (level == 0) ? timing.enter0 : (level == 1) ? timing.enter1 : timing.enter_base + level * timing.enter_count;
- PUSH(I.regs.w[BP]);
- I.regs.w[BP]=I.regs.w[SP];
- I.regs.w[SP] -= nb;
+ PUSH(cpustate->regs.w[BP]);
+ cpustate->regs.w[BP]=cpustate->regs.w[SP];
+ cpustate->regs.w[SP] -= nb;
for (i=1;i<level;i++)
- PUSH(GetMemW(SS,I.regs.w[BP]-i*2));
- if (level) PUSH(I.regs.w[BP]);
+ PUSH(GetMemW(SS,cpustate->regs.w[BP]-i*2));
+ if (level) PUSH(cpustate->regs.w[BP]);
}
-static void PREFIX186(_leave)(void) /* Opcode 0xc9 */
+static void PREFIX186(_leave)(i8086_state *cpustate) /* Opcode 0xc9 */
{
ICOUNT -= timing.leave;
- I.regs.w[SP]=I.regs.w[BP];
- POP(I.regs.w[BP]);
+ cpustate->regs.w[SP]=cpustate->regs.w[BP];
+ POP(cpustate->regs.w[BP]);
}
diff --git a/src/emu/cpu/i86/instr186.h b/src/emu/cpu/i86/instr186.h
index 54de28e18ad..86c8b285c2b 100644
--- a/src/emu/cpu/i86/instr186.h
+++ b/src/emu/cpu/i86/instr186.h
@@ -6,22 +6,22 @@
// file will be included in all cpu variants
// timing value should move to separate array
-static void PREFIX186(_pusha)(void);
-static void PREFIX186(_popa)(void);
-static void PREFIX186(_bound)(void);
-static void PREFIX186(_push_d16)(void);
-static void PREFIX186(_imul_d16)(void);
-static void PREFIX186(_push_d8)(void);
-static void PREFIX186(_imul_d8)(void);
-static void PREFIX186(_rotshft_bd8)(void);
-static void PREFIX186(_rotshft_wd8)(void);
-static void PREFIX186(_enter)(void);
-static void PREFIX186(_leave)(void);
-static void PREFIX186(_insb)(void);
-static void PREFIX186(_insw)(void);
-static void PREFIX186(_outsb)(void);
-static void PREFIX186(_outsw)(void);
+static void PREFIX186(_pusha)(i8086_state *cpustate);
+static void PREFIX186(_popa)(i8086_state *cpustate);
+static void PREFIX186(_bound)(i8086_state *cpustate);
+static void PREFIX186(_push_d16)(i8086_state *cpustate);
+static void PREFIX186(_imul_d16)(i8086_state *cpustate);
+static void PREFIX186(_push_d8)(i8086_state *cpustate);
+static void PREFIX186(_imul_d8)(i8086_state *cpustate);
+static void PREFIX186(_rotshft_bd8)(i8086_state *cpustate);
+static void PREFIX186(_rotshft_wd8)(i8086_state *cpustate);
+static void PREFIX186(_enter)(i8086_state *cpustate);
+static void PREFIX186(_leave)(i8086_state *cpustate);
+static void PREFIX186(_insb)(i8086_state *cpustate);
+static void PREFIX186(_insw)(i8086_state *cpustate);
+static void PREFIX186(_outsb)(i8086_state *cpustate);
+static void PREFIX186(_outsw)(i8086_state *cpustate);
/* changed instructions */
-static void PREFIX186(_repne)(void);
-static void PREFIX186(_repe)(void);
+static void PREFIX186(_repne)(i8086_state *cpustate);
+static void PREFIX186(_repe)(i8086_state *cpustate);
diff --git a/src/emu/cpu/i86/instr286.c b/src/emu/cpu/i86/instr286.c
index 23ae968f4fc..23d14edd5a2 100644
--- a/src/emu/cpu/i86/instr286.c
+++ b/src/emu/cpu/i86/instr286.c
@@ -20,30 +20,30 @@
#define WRITEABLE(a) ((a&0xa)==2)
#define READABLE(a) ( ((a&0xa)==0xa)|| ((a&8)==0) )
-static void i80286_trap2(int number)
+static void i80286_trap2(i80286_state *cpustate,int number)
{
- i80286_interrupt(number);
+ i80286_interrupt(cpustate,number);
}
-static int i80286_selector_okay(UINT16 selector)
+static int i80286_selector_okay(i80286_state *cpustate,UINT16 selector)
{
if (selector&4) {
- return (selector&~7)<I.ldtr.limit;
+ return (selector&~7)<cpustate->ldtr.limit;
} else {
- return (selector&~7)<I.gdtr.limit;
+ return (selector&~7)<cpustate->gdtr.limit;
}
}
-static offs_t i80286_selector_to_address(UINT16 selector)
+static offs_t i80286_selector_to_address(i80286_state *cpustate,UINT16 selector)
{
if (selector&4) {
- return I.ldtr.base+(selector&~7);
+ return cpustate->ldtr.base+(selector&~7);
} else {
- return I.gdtr.base+(selector&~7);
+ return cpustate->gdtr.base+(selector&~7);
}
}
-static void i80286_data_descriptor(int reg, UINT16 selector)
+static void i80286_data_descriptor(i80286_state *cpustate,int reg, UINT16 selector)
{
if (PM) {
UINT16 help;
@@ -53,29 +53,29 @@ static void i80286_data_descriptor(int reg, UINT16 selector)
1,0: requested privileg level
must be higher or same as current privileg level in code selector */
if (selector&4) { /* local descriptor table */
- if (selector>I.ldtr.limit) i80286_trap2(GENERAL_PROTECTION_FAULT);
- I.sregs[reg]=selector;
- I.limit[reg]=ReadWord(I.ldtr.base+(selector&~7));
- I.base[reg]=ReadWord(I.ldtr.base+(selector&~7)+2)
- |(ReadWord(I.ldtr.base+(selector&~7)+4)<<16);
- I.rights[reg]=I.base[reg]>>24;
- I.base[reg]&=0xffffff;
+ if (selector>cpustate->ldtr.limit) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
+ cpustate->sregs[reg]=selector;
+ cpustate->limit[reg]=ReadWord(cpustate->ldtr.base+(selector&~7));
+ cpustate->base[reg]=ReadWord(cpustate->ldtr.base+(selector&~7)+2)
+ |(ReadWord(cpustate->ldtr.base+(selector&~7)+4)<<16);
+ cpustate->rights[reg]=cpustate->base[reg]>>24;
+ cpustate->base[reg]&=0xffffff;
} else { /* global descriptor table */
- if (!(selector&~7)||(selector>I.gdtr.limit)) i80286_trap2(GENERAL_PROTECTION_FAULT);
- I.sregs[reg]=selector;
- I.limit[reg]=ReadWord(I.gdtr.base+(selector&~7));
- I.base[reg]=ReadWord(I.gdtr.base+(selector&~7)+2);
- help=ReadWord(I.gdtr.base+(selector&~7)+4);
- I.rights[reg]=help>>8;
- I.base[reg]|=(help&0xff)<<16;
+ if (!(selector&~7)||(selector>cpustate->gdtr.limit)) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
+ cpustate->sregs[reg]=selector;
+ cpustate->limit[reg]=ReadWord(cpustate->gdtr.base+(selector&~7));
+ cpustate->base[reg]=ReadWord(cpustate->gdtr.base+(selector&~7)+2);
+ help=ReadWord(cpustate->gdtr.base+(selector&~7)+4);
+ cpustate->rights[reg]=help>>8;
+ cpustate->base[reg]|=(help&0xff)<<16;
}
} else {
- I.sregs[reg]=selector;
- I.base[reg]=selector<<4;
+ cpustate->sregs[reg]=selector;
+ cpustate->base[reg]=selector<<4;
}
}
-static void i80286_code_descriptor(UINT16 selector, UINT16 offset)
+static void i80286_code_descriptor(i80286_state *cpustate,UINT16 selector, UINT16 offset)
{
UINT16 word1, word2, word3;
if (PM) {
@@ -85,82 +85,82 @@ static void i80286_code_descriptor(UINT16 selector, UINT16 offset)
1,0: requested privileg level
must be higher or same as current privileg level in code selector */
if (selector&4) { /* local descriptor table */
- if (selector>I.ldtr.limit) i80286_trap2(GENERAL_PROTECTION_FAULT);
- word1=ReadWord(I.ldtr.base+(selector&~7));
- word2=ReadWord(I.ldtr.base+(selector&~7)+2);
- word3=ReadWord(I.ldtr.base+(selector&~7)+4);
+ if (selector>cpustate->ldtr.limit) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
+ word1=ReadWord(cpustate->ldtr.base+(selector&~7));
+ word2=ReadWord(cpustate->ldtr.base+(selector&~7)+2);
+ word3=ReadWord(cpustate->ldtr.base+(selector&~7)+4);
} else { /* global descriptor table */
- if (!(selector&~7)||(selector>I.gdtr.limit)) i80286_trap2(GENERAL_PROTECTION_FAULT);
- word1=ReadWord(I.gdtr.base+(selector&~7));
- word2=ReadWord(I.gdtr.base+(selector&~7)+2);
- word3=ReadWord(I.gdtr.base+(selector&~7)+4);
+ if (!(selector&~7)||(selector>cpustate->gdtr.limit)) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
+ word1=ReadWord(cpustate->gdtr.base+(selector&~7));
+ word2=ReadWord(cpustate->gdtr.base+(selector&~7)+2);
+ word3=ReadWord(cpustate->gdtr.base+(selector&~7)+4);
}
if (word3&0x1000) {
- I.sregs[CS]=selector;
- I.limit[CS]=word1;
- I.base[CS]=word2|((word3&0xff)<<16);
- I.rights[CS]=word3>>8;
- I.pc=I.base[CS]+offset;
+ cpustate->sregs[CS]=selector;
+ cpustate->limit[CS]=word1;
+ cpustate->base[CS]=word2|((word3&0xff)<<16);
+ cpustate->rights[CS]=word3>>8;
+ cpustate->pc=cpustate->base[CS]+offset;
} else { // systemdescriptor
switch (word3&0xf00) {
case 0x400: // call gate
// word3&0x1f words to be copied from stack to stack
- i80286_data_descriptor(CS, word2);
- I.pc=I.base[CS]+word1;
+ i80286_data_descriptor(cpustate, CS, word2);
+ cpustate->pc=cpustate->base[CS]+word1;
break;
case 0x500: // task gate
- i80286_data_descriptor(CS, word2);
- I.pc=I.base[CS]+word1;
+ i80286_data_descriptor(cpustate, CS, word2);
+ cpustate->pc=cpustate->base[CS]+word1;
break;
case 0x600: // interrupt gate
- I.TF = I.IF = 0;
- i80286_data_descriptor(CS, word2);
- I.pc=I.base[CS]+word1;
+ cpustate->TF = cpustate->IF = 0;
+ i80286_data_descriptor(cpustate, CS, word2);
+ cpustate->pc=cpustate->base[CS]+word1;
break;
case 0x700: // trap gate
- i80286_data_descriptor(CS, word2);
- I.pc=I.base[CS]+word1;
+ i80286_data_descriptor(cpustate, CS, word2);
+ cpustate->pc=cpustate->base[CS]+word1;
break;
}
}
} else {
- I.sregs[CS]=selector;
- I.base[CS]=selector<<4;
- I.pc=I.base[CS]+offset;
+ cpustate->sregs[CS]=selector;
+ cpustate->base[CS]=selector<<4;
+ cpustate->pc=cpustate->base[CS]+offset;
}
}
-static void i80286_interrupt_descriptor(UINT16 number)
+static void i80286_interrupt_descriptor(i80286_state *cpustate,UINT16 number)
{
UINT16 word1,word2,word3;
- if ((number<<3)>=I.idtr.limit) {
+ if ((number<<3)>=cpustate->idtr.limit) {
;// go into shutdown mode
return;
}
- PREFIX(_pushf());
- PUSH(I.sregs[CS]);
- PUSH(I.pc - I.base[CS]);
- word1=ReadWord(I.idtr.base+(number<<3));
- word2=ReadWord(I.idtr.base+(number<<3)+2);
- word3=ReadWord(I.idtr.base+(number<<3)+4);
+ PREFIX(_pushf(cpustate));
+ PUSH(cpustate->sregs[CS]);
+ PUSH(cpustate->pc - cpustate->base[CS]);
+ word1=ReadWord(cpustate->idtr.base+(number<<3));
+ word2=ReadWord(cpustate->idtr.base+(number<<3)+2);
+ word3=ReadWord(cpustate->idtr.base+(number<<3)+4);
switch (word3&0xf00) {
case 0x500: // task gate
- i80286_data_descriptor(CS, word2);
- I.pc=I.base[CS]+word1;
+ i80286_data_descriptor(cpustate, CS, word2);
+ cpustate->pc=cpustate->base[CS]+word1;
break;
case 0x600: // interrupt gate
- I.TF = I.IF = 0;
- i80286_data_descriptor(CS, word2);
- I.pc=I.base[CS]+word1;
+ cpustate->TF = cpustate->IF = 0;
+ i80286_data_descriptor(cpustate, CS, word2);
+ cpustate->pc=cpustate->base[CS]+word1;
break;
case 0x700: // trap gate
- i80286_data_descriptor(CS, word2);
- I.pc=I.base[CS]+word1;
+ i80286_data_descriptor(cpustate, CS, word2);
+ cpustate->pc=cpustate->base[CS]+word1;
break;
}
}
-static void PREFIX286(_0fpre)(void)
+static void PREFIX286(_0fpre)(i8086_state *cpustate)
{
unsigned next = FETCHOP;
UINT16 ModRM;
@@ -172,59 +172,59 @@ static void PREFIX286(_0fpre)(void)
ModRM=FETCHOP;
switch (ModRM&0x38) {
case 0: /* sldt */
- if (!PM) i80286_trap2(ILLEGAL_INSTRUCTION);
- PutRMWord(ModRM, I.ldtr.sel);
+ if (!PM) i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
+ PutRMWord(ModRM, cpustate->ldtr.sel);
break;
case 8: /* str */
- if (!PM) i80286_trap2(ILLEGAL_INSTRUCTION);
- PutRMWord(ModRM, I.tr.sel);
+ if (!PM) i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
+ PutRMWord(ModRM, cpustate->tr.sel);
break;
case 0x10: /* lldt */
- if (!PM) i80286_trap2(ILLEGAL_INSTRUCTION);
- if (PM&&(CPL!=0)) i80286_trap2(GENERAL_PROTECTION_FAULT);
- I.ldtr.sel=GetRMWord(ModRM);
- if ((I.ldtr.sel&~7)>=I.gdtr.limit) i80286_trap2(GENERAL_PROTECTION_FAULT);
- I.ldtr.limit=ReadWord(I.gdtr.base+(I.ldtr.sel&~7));
- I.ldtr.base=ReadWord(I.gdtr.base+(I.ldtr.sel&~7)+2)
- |(ReadWord(I.gdtr.base+(I.ldtr.sel&~7)+4)<<16);
- I.ldtr.rights=I.ldtr.base>>24;
- I.ldtr.base&=0xffffff;
+ if (!PM) i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
+ if (PM&&(CPL!=0)) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
+ cpustate->ldtr.sel=GetRMWord(ModRM);
+ if ((cpustate->ldtr.sel&~7)>=cpustate->gdtr.limit) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
+ cpustate->ldtr.limit=ReadWord(cpustate->gdtr.base+(cpustate->ldtr.sel&~7));
+ cpustate->ldtr.base=ReadWord(cpustate->gdtr.base+(cpustate->ldtr.sel&~7)+2)
+ |(ReadWord(cpustate->gdtr.base+(cpustate->ldtr.sel&~7)+4)<<16);
+ cpustate->ldtr.rights=cpustate->ldtr.base>>24;
+ cpustate->ldtr.base&=0xffffff;
break;
case 0x18: /* ltr */
- if (!PM) i80286_trap2(ILLEGAL_INSTRUCTION);
- if (CPL!=0) i80286_trap2(GENERAL_PROTECTION_FAULT);
- I.tr.sel=GetRMWord(ModRM);
- if ((I.tr.sel&~7)>=I.gdtr.limit) i80286_trap2(GENERAL_PROTECTION_FAULT);
- I.tr.limit=ReadWord(I.gdtr.base+(I.tr.sel&~7));
- I.tr.base=ReadWord(I.gdtr.base+(I.tr.sel&~7)+2)
- |(ReadWord(I.gdtr.base+(I.tr.sel&~7)+4)<<16);
- I.tr.rights=I.tr.base>>24;
- I.tr.base&=0xffffff;
+ if (!PM) i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
+ if (CPL!=0) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
+ cpustate->tr.sel=GetRMWord(ModRM);
+ if ((cpustate->tr.sel&~7)>=cpustate->gdtr.limit) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
+ cpustate->tr.limit=ReadWord(cpustate->gdtr.base+(cpustate->tr.sel&~7));
+ cpustate->tr.base=ReadWord(cpustate->gdtr.base+(cpustate->tr.sel&~7)+2)
+ |(ReadWord(cpustate->gdtr.base+(cpustate->tr.sel&~7)+4)<<16);
+ cpustate->tr.rights=cpustate->tr.base>>24;
+ cpustate->tr.base&=0xffffff;
break;
case 0x20: /* verr */
- if (!PM) i80286_trap2(ILLEGAL_INSTRUCTION);
+ if (!PM) i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
tmp=GetRMWord(ModRM);
if (tmp&4) {
- I.ZeroVal=( ((tmp&~7)<I.ldtr.limit)
- && READABLE( ReadByte(I.ldtr.base+(tmp&~7)+5)) );
+ cpustate->ZeroVal=( ((tmp&~7)<cpustate->ldtr.limit)
+ && READABLE( ReadByte(cpustate->ldtr.base+(tmp&~7)+5)) );
} else {
- I.ZeroVal=( ((tmp&~7)<I.gdtr.limit)
- && READABLE( ReadByte(I.gdtr.base+(tmp&~7)+5)) );
+ cpustate->ZeroVal=( ((tmp&~7)<cpustate->gdtr.limit)
+ && READABLE( ReadByte(cpustate->gdtr.base+(tmp&~7)+5)) );
}
break;
case 0x28: /* verw */
- if (!PM) i80286_trap2(ILLEGAL_INSTRUCTION);
+ if (!PM) i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
tmp=GetRMWord(ModRM);
if (tmp&4) {
- I.ZeroVal=( ((tmp&~7)<I.ldtr.limit)
- && WRITEABLE( ReadByte(I.ldtr.base+(tmp&~7)+5)) );
+ cpustate->ZeroVal=( ((tmp&~7)<cpustate->ldtr.limit)
+ && WRITEABLE( ReadByte(cpustate->ldtr.base+(tmp&~7)+5)) );
} else {
- I.ZeroVal=( ((tmp&~7)<I.gdtr.limit)
- && WRITEABLE( ReadByte(I.gdtr.base+(tmp&~7)+5)) );
+ cpustate->ZeroVal=( ((tmp&~7)<cpustate->gdtr.limit)
+ && WRITEABLE( ReadByte(cpustate->gdtr.base+(tmp&~7)+5)) );
}
break;
default:
- i80286_trap2(ILLEGAL_INSTRUCTION);
+ i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
break;
}
break;
@@ -234,75 +234,75 @@ static void PREFIX286(_0fpre)(void)
ModRM = FETCHOP;
switch (ModRM&0x38) {
case 0: /* sgdt */
- PutRMWord(ModRM,I.gdtr.limit);
- PutRMWordOffset(2,I.gdtr.base&0xffff);
- PutRMByteOffset(4,I.gdtr.base>>16);
+ PutRMWord(ModRM,cpustate->gdtr.limit);
+ PutRMWordOffset(2,cpustate->gdtr.base&0xffff);
+ PutRMByteOffset(4,cpustate->gdtr.base>>16);
break;
case 8: /* sidt */
- PutRMWord(ModRM,I.idtr.limit);
- PutRMWordOffset(2,I.idtr.base&0xffff);
- PutRMByteOffset(4,I.idtr.base>>16);
+ PutRMWord(ModRM,cpustate->idtr.limit);
+ PutRMWordOffset(2,cpustate->idtr.base&0xffff);
+ PutRMByteOffset(4,cpustate->idtr.base>>16);
break;
case 0x10: /* lgdt */
- if (PM&&(CPL!=0)) i80286_trap2(GENERAL_PROTECTION_FAULT);
- I.gdtr.limit=GetRMWord(ModRM);
- I.gdtr.base=GetRMWordOffset(2)|(GetRMByteOffset(4)<<16);
+ if (PM&&(CPL!=0)) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
+ cpustate->gdtr.limit=GetRMWord(ModRM);
+ cpustate->gdtr.base=GetRMWordOffset(2)|(GetRMByteOffset(4)<<16);
break;
case 0x18: /* lidt */
- if (PM&&(CPL!=0)) i80286_trap2(GENERAL_PROTECTION_FAULT);
- I.idtr.limit=GetRMWord(ModRM);
- I.idtr.base=GetRMWordOffset(2)|(GetRMByteOffset(4)<<16);
+ if (PM&&(CPL!=0)) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
+ cpustate->idtr.limit=GetRMWord(ModRM);
+ cpustate->idtr.base=GetRMWordOffset(2)|(GetRMByteOffset(4)<<16);
break;
case 0x20: /* smsw */
- PutRMWord(ModRM, I.msw);
+ PutRMWord(ModRM, cpustate->msw);
break;
case 0x30: /* lmsw */
- if (PM&&(CPL!=0)) i80286_trap2(GENERAL_PROTECTION_FAULT);
- I.msw=(I.msw&1)|GetRMWord(ModRM);
+ if (PM&&(CPL!=0)) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
+ cpustate->msw=(cpustate->msw&1)|GetRMWord(ModRM);
break;
default:
- i80286_trap2(ILLEGAL_INSTRUCTION);
+ i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
break;
}
break;
case 2: /* LAR */
ModRM = FETCHOP;
tmp=GetRMWord(ModRM);
- I.ZeroVal=i80286_selector_okay(tmp);
- if (I.ZeroVal) {
+ cpustate->ZeroVal=i80286_selector_okay(cpustate,tmp);
+ if (cpustate->ZeroVal) {
RegWord(ModRM)=tmp;
}
break;
case 3: /* LSL */
- if (!PM) i80286_trap2(ILLEGAL_INSTRUCTION);
+ if (!PM) i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
ModRM = FETCHOP;
tmp=GetRMWord(ModRM);
- I.ZeroVal=i80286_selector_okay(tmp);
- if (I.ZeroVal) {
- addr=i80286_selector_to_address(tmp);
+ cpustate->ZeroVal=i80286_selector_okay(cpustate,tmp);
+ if (cpustate->ZeroVal) {
+ addr=i80286_selector_to_address(cpustate,tmp);
RegWord(ModRM)=ReadWord(addr);
}
break;
case 6: /* clts */
- if (PM&&(CPL!=0)) i80286_trap2(GENERAL_PROTECTION_FAULT);
- I.msw=~8;
+ if (PM&&(CPL!=0)) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
+ cpustate->msw=~8;
break;
default:
- i80286_trap2(ILLEGAL_INSTRUCTION);
+ i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
break;
}
}
-static void PREFIX286(_arpl)(void) /* 0x63 */
+static void PREFIX286(_arpl)(i8086_state *cpustate) /* 0x63 */
{
if (PM) {
UINT16 ModRM=FETCHOP, tmp=GetRMWord(ModRM);
- I.ZeroVal=i80286_selector_okay(RegWord(ModRM))
- &&i80286_selector_okay(RegWord(ModRM))
+ cpustate->ZeroVal=i80286_selector_okay(cpustate,RegWord(ModRM))
+ &&i80286_selector_okay(cpustate,RegWord(ModRM))
&&((tmp&3)<(RegWord(ModRM)&3));
- if (I.ZeroVal) PutbackRMWord(ModRM, (tmp&~3)|(RegWord(ModRM)&3));
+ if (cpustate->ZeroVal) PutbackRMWord(ModRM, (tmp&~3)|(RegWord(ModRM)&3));
} else {
- i80286_trap2(ILLEGAL_INSTRUCTION);
+ i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
}
}
diff --git a/src/emu/cpu/i86/instr286.h b/src/emu/cpu/i86/instr286.h
index 53431ada3be..f4539b323ca 100644
--- a/src/emu/cpu/i86/instr286.h
+++ b/src/emu/cpu/i86/instr286.h
@@ -1,13 +1,13 @@
#define ILLEGAL_INSTRUCTION 6
#define GENERAL_PROTECTION_FAULT 0xd
-#define PM (I.msw&1)
-#define CPL (I.sregs[CS]&3)
-#define IOPL ((I.flags&0x3000)>>12)
+#define PM (cpustate->msw&1)
+#define CPL (cpustate->sregs[CS]&3)
+#define IOPL ((cpustate->flags&0x3000)>>12)
-static void i80286_trap2(int number);
-static void i80286_interrupt_descriptor(UINT16 number);
-static void i80286_code_descriptor(UINT16 selector, UINT16 offset);
-static void i80286_data_descriptor(int reg, UINT16 selector);
-static void PREFIX286(_0fpre)(void);
-static void PREFIX286(_arpl)(void);
+static void i80286_trap2(i80286_state *cpustate,int number);
+static void i80286_interrupt_descriptor(i80286_state *cpustate,UINT16 number);
+static void i80286_code_descriptor(i80286_state *cpustate,UINT16 selector, UINT16 offset);
+static void i80286_data_descriptor(i80286_state *cpustate,int reg, UINT16 selector);
+static void PREFIX286(_0fpre)(i80286_state *cpustate);
+static void PREFIX286(_arpl)(i80286_state *cpustate);
diff --git a/src/emu/cpu/i86/instr86.c b/src/emu/cpu/i86/instr86.c
index 2da447af900..87df4b45d88 100644
--- a/src/emu/cpu/i86/instr86.c
+++ b/src/emu/cpu/i86/instr86.c
@@ -12,50 +12,50 @@
#undef ICOUNT
-#define ICOUNT i8086_ICount
+#define ICOUNT cpustate->icount
#if !defined(I80186)
-static void PREFIX86(_interrupt)(unsigned int_num)
+static void PREFIX86(_interrupt)(i8086_state *cpustate, unsigned int_num)
{
unsigned dest_seg, dest_off;
- WORD ip = I.pc - I.base[CS];
+ WORD ip = cpustate->pc - cpustate->base[CS];
if (int_num == -1)
- int_num = (*I.irq_callback)(I.device, 0);
+ int_num = (*cpustate->irq_callback)(cpustate->device, 0);
#ifdef I80286
if (PM) {
- i80286_interrupt_descriptor(int_num);
+ i80286_interrupt_descriptor(cpustate, int_num);
} else {
#endif
dest_off = ReadWord(int_num*4);
dest_seg = ReadWord(int_num*4+2);
- PREFIX(_pushf());
- I.TF = I.IF = 0;
- PUSH(I.sregs[CS]);
+ PREFIX(_pushf(cpustate));
+ cpustate->TF = cpustate->IF = 0;
+ PUSH(cpustate->sregs[CS]);
PUSH(ip);
- I.sregs[CS] = (WORD)dest_seg;
- I.base[CS] = SegBase(CS);
- I.pc = (I.base[CS] + dest_off) & AMASK;
+ cpustate->sregs[CS] = (WORD)dest_seg;
+ cpustate->base[CS] = SegBase(CS);
+ cpustate->pc = (cpustate->base[CS] + dest_off) & AMASK;
#ifdef I80286
}
#endif
- CHANGE_PC(I.pc);
+ CHANGE_PC(cpustate->pc);
- I.extra_cycles += timing.exception;
+ cpustate->extra_cycles += timing.exception;
}
-static void PREFIX86(_trap)(void)
+static void PREFIX86(_trap)(i8086_state *cpustate)
{
- PREFIX(_instruction)[FETCHOP]();
- PREFIX(_interrupt)(1);
+ PREFIX(_instruction)[FETCHOP](cpustate);
+ PREFIX(_interrupt)(cpustate, 1);
}
#endif
#ifndef I80186
-static void PREFIX86(_rotate_shift_Byte)(unsigned ModRM, unsigned count)
+static void PREFIX86(_rotate_shift_Byte)(i8086_state *cpustate, unsigned ModRM, unsigned count)
{
unsigned src = (unsigned)GetRMByte(ModRM);
unsigned dst=src;
@@ -71,52 +71,52 @@ static void PREFIX86(_rotate_shift_Byte)(unsigned ModRM, unsigned count)
switch (ModRM & 0x38)
{
case 0x00: /* ROL eb,1 */
- I.CarryVal = src & 0x80;
+ cpustate->CarryVal = src & 0x80;
dst=(src<<1)+CF;
PutbackRMByte(ModRM,dst);
- I.OverVal = (src^dst)&0x80;
+ cpustate->OverVal = (src^dst)&0x80;
break;
case 0x08: /* ROR eb,1 */
- I.CarryVal = src & 0x01;
+ cpustate->CarryVal = src & 0x01;
dst = ((CF<<8)+src) >> 1;
PutbackRMByte(ModRM,dst);
- I.OverVal = (src^dst)&0x80;
+ cpustate->OverVal = (src^dst)&0x80;
break;
case 0x10: /* RCL eb,1 */
dst=(src<<1)+CF;
PutbackRMByte(ModRM,dst);
SetCFB(dst);
- I.OverVal = (src^dst)&0x80;
+ cpustate->OverVal = (src^dst)&0x80;
break;
case 0x18: /* RCR eb,1 */
dst = ((CF<<8)+src) >> 1;
PutbackRMByte(ModRM,dst);
- I.CarryVal = src & 0x01;
- I.OverVal = (src^dst)&0x80;
+ cpustate->CarryVal = src & 0x01;
+ cpustate->OverVal = (src^dst)&0x80;
break;
case 0x20: /* SHL eb,1 */
case 0x30:
dst = src << 1;
PutbackRMByte(ModRM,dst);
SetCFB(dst);
- I.OverVal = (src^dst)&0x80;
- I.AuxVal = 1;
+ cpustate->OverVal = (src^dst)&0x80;
+ cpustate->AuxVal = 1;
SetSZPF_Byte(dst);
break;
case 0x28: /* SHR eb,1 */
dst = src >> 1;
PutbackRMByte(ModRM,dst);
- I.CarryVal = src & 0x01;
- I.OverVal = src & 0x80;
- I.AuxVal = 1;
+ cpustate->CarryVal = src & 0x01;
+ cpustate->OverVal = src & 0x80;
+ cpustate->AuxVal = 1;
SetSZPF_Byte(dst);
break;
case 0x38: /* SAR eb,1 */
dst = ((INT8)src) >> 1;
PutbackRMByte(ModRM,dst);
- I.CarryVal = src & 0x01;
- I.OverVal = 0;
- I.AuxVal = 1;
+ cpustate->CarryVal = src & 0x01;
+ cpustate->OverVal = 0;
+ cpustate->AuxVal = 1;
SetSZPF_Byte(dst);
break;
}
@@ -130,7 +130,7 @@ static void PREFIX86(_rotate_shift_Byte)(unsigned ModRM, unsigned count)
case 0x00: /* ROL eb,count */
for (; count > 0; count--)
{
- I.CarryVal = dst & 0x80;
+ cpustate->CarryVal = dst & 0x80;
dst = (dst << 1) + CF;
}
PutbackRMByte(ModRM,(BYTE)dst);
@@ -138,7 +138,7 @@ static void PREFIX86(_rotate_shift_Byte)(unsigned ModRM, unsigned count)
case 0x08: /* ROR eb,count */
for (; count > 0; count--)
{
- I.CarryVal = dst & 0x01;
+ cpustate->CarryVal = dst & 0x01;
dst = (dst >> 1) + (CF << 7);
}
PutbackRMByte(ModRM,(BYTE)dst);
@@ -155,7 +155,7 @@ static void PREFIX86(_rotate_shift_Byte)(unsigned ModRM, unsigned count)
for (; count > 0; count--)
{
dst = (CF<<8)+dst;
- I.CarryVal = dst & 0x01;
+ cpustate->CarryVal = dst & 0x01;
dst >>= 1;
}
PutbackRMByte(ModRM,(BYTE)dst);
@@ -164,31 +164,31 @@ static void PREFIX86(_rotate_shift_Byte)(unsigned ModRM, unsigned count)
case 0x30: /* SHL eb,count */
dst <<= count;
SetCFB(dst);
- I.AuxVal = 1;
+ cpustate->AuxVal = 1;
SetSZPF_Byte(dst);
PutbackRMByte(ModRM,(BYTE)dst);
break;
case 0x28: /* SHR eb,count */
dst >>= count-1;
- I.CarryVal = dst & 0x1;
+ cpustate->CarryVal = dst & 0x1;
dst >>= 1;
SetSZPF_Byte(dst);
- I.AuxVal = 1;
+ cpustate->AuxVal = 1;
PutbackRMByte(ModRM,(BYTE)dst);
break;
case 0x38: /* SAR eb,count */
dst = ((INT8)dst) >> (count-1);
- I.CarryVal = dst & 0x1;
+ cpustate->CarryVal = dst & 0x1;
dst = ((INT8)((BYTE)dst)) >> 1;
SetSZPF_Byte(dst);
- I.AuxVal = 1;
+ cpustate->AuxVal = 1;
PutbackRMByte(ModRM,(BYTE)dst);
break;
}
}
}
-static void PREFIX86(_rotate_shift_Word)(unsigned ModRM, unsigned count)
+static void PREFIX86(_rotate_shift_Word)(i8086_state *cpustate, unsigned ModRM, unsigned count)
{
unsigned src = GetRMWord(ModRM);
unsigned dst=src;
@@ -207,25 +207,25 @@ static void PREFIX86(_rotate_shift_Word)(unsigned ModRM, unsigned count)
case 0x00: /* ROL ew,1 */
tmp2 = (tmp << 1) + CF;
SetCFW(tmp2);
- I.OverVal = !(!(tmp & 0x4000)) != CF;
+ cpustate->OverVal = !(!(tmp & 0x4000)) != CF;
PutbackRMWord(ModRM,tmp2);
break;
case 0x08: /* ROR ew,1 */
- I.CarryVal = tmp & 0x01;
+ cpustate->CarryVal = tmp & 0x01;
tmp2 = (tmp >> 1) + ((unsigned)CF << 15);
- I.OverVal = !(!(tmp & 0x8000)) != CF;
+ cpustate->OverVal = !(!(tmp & 0x8000)) != CF;
PutbackRMWord(ModRM,tmp2);
break;
case 0x10: /* RCL ew,1 */
tmp2 = (tmp << 1) + CF;
SetCFW(tmp2);
- I.OverVal = (tmp ^ (tmp << 1)) & 0x8000;
+ cpustate->OverVal = (tmp ^ (tmp << 1)) & 0x8000;
PutbackRMWord(ModRM,tmp2);
break;
case 0x18: /* RCR ew,1 */
tmp2 = (tmp >> 1) + ((unsigned)CF << 15);
- I.OverVal = !(!(tmp & 0x8000)) != CF;
- I.CarryVal = tmp & 0x01;
+ cpustate->OverVal = !(!(tmp & 0x8000)) != CF;
+ cpustate->CarryVal = tmp & 0x01;
PutbackRMWord(ModRM,tmp2);
break;
case 0x20: /* SHL ew,1 */
@@ -234,79 +234,79 @@ static void PREFIX86(_rotate_shift_Word)(unsigned ModRM, unsigned count)
SetCFW(tmp);
SetOFW_Add(tmp,tmp2,tmp2);
- I.AuxVal = 1;
+ cpustate->AuxVal = 1;
SetSZPF_Word(tmp);
PutbackRMWord(ModRM,tmp);
break;
case 0x28: /* SHR ew,1 */
- I.CarryVal = tmp & 0x01;
- I.OverVal = tmp & 0x8000;
+ cpustate->CarryVal = tmp & 0x01;
+ cpustate->OverVal = tmp & 0x8000;
tmp2 = tmp >> 1;
SetSZPF_Word(tmp2);
- I.AuxVal = 1;
+ cpustate->AuxVal = 1;
PutbackRMWord(ModRM,tmp2);
break;
case 0x38: /* SAR ew,1 */
- I.CarryVal = tmp & 0x01;
- I.OverVal = 0;
+ cpustate->CarryVal = tmp & 0x01;
+ cpustate->OverVal = 0;
tmp2 = (tmp >> 1) | (tmp & 0x8000);
SetSZPF_Word(tmp2);
- I.AuxVal = 1;
+ cpustate->AuxVal = 1;
PutbackRMWord(ModRM,tmp2);
break;
#else
case 0x00: /* ROL ew,1 */
- I.CarryVal = src & 0x8000;
+ cpustate->CarryVal = src & 0x8000;
dst=(src<<1)+CF;
PutbackRMWord(ModRM,dst);
- I.OverVal = (src^dst)&0x8000;
+ cpustate->OverVal = (src^dst)&0x8000;
break;
case 0x08: /* ROR ew,1 */
- I.CarryVal = src & 0x01;
+ cpustate->CarryVal = src & 0x01;
dst = ((CF<<16)+src) >> 1;
PutbackRMWord(ModRM,dst);
- I.OverVal = (src^dst)&0x8000;
+ cpustate->OverVal = (src^dst)&0x8000;
break;
case 0x10: /* RCL ew,1 */
dst=(src<<1)+CF;
PutbackRMWord(ModRM,dst);
SetCFW(dst);
- I.OverVal = (src^dst)&0x8000;
+ cpustate->OverVal = (src^dst)&0x8000;
break;
case 0x18: /* RCR ew,1 */
dst = ((CF<<16)+src) >> 1;
PutbackRMWord(ModRM,dst);
- I.CarryVal = src & 0x01;
- I.OverVal = (src^dst)&0x8000;
+ cpustate->CarryVal = src & 0x01;
+ cpustate->OverVal = (src^dst)&0x8000;
break;
case 0x20: /* SHL ew,1 */
case 0x30:
dst = src << 1;
PutbackRMWord(ModRM,dst);
SetCFW(dst);
- I.OverVal = (src^dst)&0x8000;
- I.AuxVal = 1;
+ cpustate->OverVal = (src^dst)&0x8000;
+ cpustate->AuxVal = 1;
SetSZPF_Word(dst);
break;
case 0x28: /* SHR ew,1 */
dst = src >> 1;
PutbackRMWord(ModRM,dst);
- I.CarryVal = src & 0x01;
- I.OverVal = src & 0x8000;
- I.AuxVal = 1;
+ cpustate->CarryVal = src & 0x01;
+ cpustate->OverVal = src & 0x8000;
+ cpustate->AuxVal = 1;
SetSZPF_Word(dst);
break;
case 0x38: /* SAR ew,1 */
dst = ((INT16)src) >> 1;
PutbackRMWord(ModRM,dst);
- I.CarryVal = src & 0x01;
- I.OverVal = 0;
- I.AuxVal = 1;
+ cpustate->CarryVal = src & 0x01;
+ cpustate->OverVal = 0;
+ cpustate->AuxVal = 1;
SetSZPF_Word(dst);
break;
#endif
@@ -321,7 +321,7 @@ static void PREFIX86(_rotate_shift_Word)(unsigned ModRM, unsigned count)
case 0x00: /* ROL ew,count */
for (; count > 0; count--)
{
- I.CarryVal = dst & 0x8000;
+ cpustate->CarryVal = dst & 0x8000;
dst = (dst << 1) + CF;
}
PutbackRMWord(ModRM,dst);
@@ -329,7 +329,7 @@ static void PREFIX86(_rotate_shift_Word)(unsigned ModRM, unsigned count)
case 0x08: /* ROR ew,count */
for (; count > 0; count--)
{
- I.CarryVal = dst & 0x01;
+ cpustate->CarryVal = dst & 0x01;
dst = (dst >> 1) + (CF << 15);
}
PutbackRMWord(ModRM,dst);
@@ -346,7 +346,7 @@ static void PREFIX86(_rotate_shift_Word)(unsigned ModRM, unsigned count)
for (; count > 0; count--)
{
dst = dst + (CF << 16);
- I.CarryVal = dst & 0x01;
+ cpustate->CarryVal = dst & 0x01;
dst >>= 1;
}
PutbackRMWord(ModRM,dst);
@@ -355,24 +355,24 @@ static void PREFIX86(_rotate_shift_Word)(unsigned ModRM, unsigned count)
case 0x30: /* SHL ew,count */
dst <<= count;
SetCFW(dst);
- I.AuxVal = 1;
+ cpustate->AuxVal = 1;
SetSZPF_Word(dst);
PutbackRMWord(ModRM,dst);
break;
case 0x28: /* SHR ew,count */
dst >>= count-1;
- I.CarryVal = dst & 0x1;
+ cpustate->CarryVal = dst & 0x1;
dst >>= 1;
SetSZPF_Word(dst);
- I.AuxVal = 1;
+ cpustate->AuxVal = 1;
PutbackRMWord(ModRM,dst);
break;
case 0x38: /* SAR ew,count */
dst = ((INT16)dst) >> (count-1);
- I.CarryVal = dst & 0x01;
+ cpustate->CarryVal = dst & 0x01;
dst = ((INT16)((WORD)dst)) >> 1;
SetSZPF_Word(dst);
- I.AuxVal = 1;
+ cpustate->AuxVal = 1;
PutbackRMWord(ModRM,dst);
break;
}
@@ -380,84 +380,84 @@ static void PREFIX86(_rotate_shift_Word)(unsigned ModRM, unsigned count)
}
#endif
-static void PREFIX(rep)(int flagval)
+static void PREFIX(rep)(i8086_state *cpustate,int flagval)
{
/* Handles rep- and repnz- prefixes. flagval is the value of ZF for the
loop to continue for CMPS and SCAS instructions. */
unsigned next = FETCHOP;
- unsigned count = I.regs.w[CX];
+ unsigned count = cpustate->regs.w[CX];
switch(next)
{
case 0x26: /* ES: */
- seg_prefix=TRUE;
- prefix_base=I.base[ES];
+ cpustate->seg_prefix=TRUE;
+ cpustate->prefix_base=cpustate->base[ES];
ICOUNT -= timing.override;
- PREFIX(rep)(flagval);
+ PREFIX(rep)(cpustate, flagval);
break;
case 0x2e: /* CS: */
- seg_prefix=TRUE;
- prefix_base=I.base[CS];
+ cpustate->seg_prefix=TRUE;
+ cpustate->prefix_base=cpustate->base[CS];
ICOUNT -= timing.override;
- PREFIX(rep)(flagval);
+ PREFIX(rep)(cpustate, flagval);
break;
case 0x36: /* SS: */
- seg_prefix=TRUE;
- prefix_base=I.base[SS];
+ cpustate->seg_prefix=TRUE;
+ cpustate->prefix_base=cpustate->base[SS];
ICOUNT -= timing.override;
- PREFIX(rep)(flagval);
+ PREFIX(rep)(cpustate, flagval);
break;
case 0x3e: /* DS: */
- seg_prefix=TRUE;
- prefix_base=I.base[DS];
+ cpustate->seg_prefix=TRUE;
+ cpustate->prefix_base=cpustate->base[DS];
ICOUNT -= timing.override;
- PREFIX(rep)(flagval);
+ PREFIX(rep)(cpustate, flagval);
break;
#ifndef I8086
case 0x6c: /* REP INSB */
ICOUNT -= timing.rep_ins8_base;
for (; count > 0; count--)
{
- if (ICOUNT <= 0) { I.pc = I.prevpc; break; }
- PutMemB(ES,I.regs.w[DI],read_port_byte(I.regs.w[DX]));
- I.regs.w[DI] += I.DirVal;
+ if (ICOUNT <= 0) { cpustate->pc = cpustate->prevpc; break; }
+ PutMemB(ES,cpustate->regs.w[DI],read_port_byte(cpustate->regs.w[DX]));
+ cpustate->regs.w[DI] += cpustate->DirVal;
ICOUNT -= timing.rep_ins8_count;
}
- I.regs.w[CX]=count;
+ cpustate->regs.w[CX]=count;
break;
case 0x6d: /* REP INSW */
ICOUNT -= timing.rep_ins16_base;
for (; count > 0; count--)
{
- if (ICOUNT <= 0) { I.pc = I.prevpc; break; }
- PutMemW(ES,I.regs.w[DI],read_port_word(I.regs.w[DX]));
- I.regs.w[DI] += 2 * I.DirVal;
+ if (ICOUNT <= 0) { cpustate->pc = cpustate->prevpc; break; }
+ PutMemW(ES,cpustate->regs.w[DI],read_port_word(cpustate->regs.w[DX]));
+ cpustate->regs.w[DI] += 2 * cpustate->DirVal;
ICOUNT -= timing.rep_ins16_count;
}
- I.regs.w[CX]=count;
+ cpustate->regs.w[CX]=count;
break;
case 0x6e: /* REP OUTSB */
ICOUNT -= timing.rep_outs8_base;
for (; count > 0; count--)
{
- if (ICOUNT <= 0) { I.pc = I.prevpc; break; }
- write_port_byte(I.regs.w[DX],GetMemB(DS,I.regs.w[SI]));
- I.regs.w[SI] += I.DirVal; /* GOL 11/27/01 */
+ if (ICOUNT <= 0) { cpustate->pc = cpustate->prevpc; break; }
+ write_port_byte(cpustate->regs.w[DX],GetMemB(DS,cpustate->regs.w[SI]));
+ cpustate->regs.w[SI] += cpustate->DirVal; /* GOL 11/27/01 */
ICOUNT -= timing.rep_outs8_count;
}
- I.regs.w[CX]=count;
+ cpustate->regs.w[CX]=count;
break;
case 0x6f: /* REP OUTSW */
ICOUNT -= timing.rep_outs16_base;
for (; count > 0; count--)
{
- if (ICOUNT <= 0) { I.pc = I.prevpc; break; }
- write_port_word(I.regs.w[DX],GetMemW(DS,I.regs.w[SI]));
- I.regs.w[SI] += 2 * I.DirVal; /* GOL 11/27/01 */
+ if (ICOUNT <= 0) { cpustate->pc = cpustate->prevpc; break; }
+ write_port_word(cpustate->regs.w[DX],GetMemW(DS,cpustate->regs.w[SI]));
+ cpustate->regs.w[SI] += 2 * cpustate->DirVal; /* GOL 11/27/01 */
ICOUNT -= timing.rep_outs16_count;
}
- I.regs.w[CX]=count;
+ cpustate->regs.w[CX]=count;
break;
#endif
case 0xa4: /* REP MOVSB */
@@ -466,14 +466,14 @@ static void PREFIX(rep)(int flagval)
{
BYTE tmp;
- if (ICOUNT <= 0) { I.pc = I.prevpc; break; }
- tmp = GetMemB(DS,I.regs.w[SI]);
- PutMemB(ES,I.regs.w[DI], tmp);
- I.regs.w[DI] += I.DirVal;
- I.regs.w[SI] += I.DirVal;
+ if (ICOUNT <= 0) { cpustate->pc = cpustate->prevpc; break; }
+ tmp = GetMemB(DS,cpustate->regs.w[SI]);
+ PutMemB(ES,cpustate->regs.w[DI], tmp);
+ cpustate->regs.w[DI] += cpustate->DirVal;
+ cpustate->regs.w[SI] += cpustate->DirVal;
ICOUNT -= timing.rep_movs8_count;
}
- I.regs.w[CX]=count;
+ cpustate->regs.w[CX]=count;
break;
case 0xa5: /* REP MOVSW */
ICOUNT -= timing.rep_movs16_base;
@@ -481,128 +481,128 @@ static void PREFIX(rep)(int flagval)
{
WORD tmp;
- if (ICOUNT <= 0) { I.pc = I.prevpc; break; }
- tmp = GetMemW(DS,I.regs.w[SI]);
- PutMemW(ES,I.regs.w[DI], tmp);
- I.regs.w[DI] += 2 * I.DirVal;
- I.regs.w[SI] += 2 * I.DirVal;
+ if (ICOUNT <= 0) { cpustate->pc = cpustate->prevpc; break; }
+ tmp = GetMemW(DS,cpustate->regs.w[SI]);
+ PutMemW(ES,cpustate->regs.w[DI], tmp);
+ cpustate->regs.w[DI] += 2 * cpustate->DirVal;
+ cpustate->regs.w[SI] += 2 * cpustate->DirVal;
ICOUNT -= timing.rep_movs16_count;
}
- I.regs.w[CX]=count;
+ cpustate->regs.w[CX]=count;
break;
case 0xa6: /* REP(N)E CMPSB */
ICOUNT -= timing.rep_cmps8_base;
- for (I.ZeroVal = !flagval; (ZF == flagval) && (count > 0); count--)
+ for (cpustate->ZeroVal = !flagval; (ZF == flagval) && (count > 0); count--)
{
unsigned dst, src;
- if (ICOUNT <= 0) { I.pc = I.prevpc; break; }
- dst = GetMemB(ES, I.regs.w[DI]);
- src = GetMemB(DS, I.regs.w[SI]);
+ if (ICOUNT <= 0) { cpustate->pc = cpustate->prevpc; break; }
+ dst = GetMemB(ES, cpustate->regs.w[DI]);
+ src = GetMemB(DS, cpustate->regs.w[SI]);
SUBB(src,dst); /* opposite of the usual convention */
- I.regs.w[DI] += I.DirVal;
- I.regs.w[SI] += I.DirVal;
+ cpustate->regs.w[DI] += cpustate->DirVal;
+ cpustate->regs.w[SI] += cpustate->DirVal;
ICOUNT -= timing.rep_cmps8_count;
}
- I.regs.w[CX]=count;
+ cpustate->regs.w[CX]=count;
break;
case 0xa7: /* REP(N)E CMPSW */
ICOUNT -= timing.rep_cmps16_base;
- for (I.ZeroVal = !flagval; (ZF == flagval) && (count > 0); count--)
+ for (cpustate->ZeroVal = !flagval; (ZF == flagval) && (count > 0); count--)
{
unsigned dst, src;
- if (ICOUNT <= 0) { I.pc = I.prevpc; break; }
- dst = GetMemW(ES, I.regs.w[DI]);
- src = GetMemW(DS, I.regs.w[SI]);
+ if (ICOUNT <= 0) { cpustate->pc = cpustate->prevpc; break; }
+ dst = GetMemW(ES, cpustate->regs.w[DI]);
+ src = GetMemW(DS, cpustate->regs.w[SI]);
SUBW(src,dst); /* opposite of the usual convention */
- I.regs.w[DI] += 2 * I.DirVal;
- I.regs.w[SI] += 2 * I.DirVal;
+ cpustate->regs.w[DI] += 2 * cpustate->DirVal;
+ cpustate->regs.w[SI] += 2 * cpustate->DirVal;
ICOUNT -= timing.rep_cmps16_count;
}
- I.regs.w[CX]=count;
+ cpustate->regs.w[CX]=count;
break;
case 0xaa: /* REP STOSB */
ICOUNT -= timing.rep_stos8_base;
for (; count > 0; count--)
{
- if (ICOUNT <= 0) { I.pc = I.prevpc; break; }
- PutMemB(ES,I.regs.w[DI],I.regs.b[AL]);
- I.regs.w[DI] += I.DirVal;
+ if (ICOUNT <= 0) { cpustate->pc = cpustate->prevpc; break; }
+ PutMemB(ES,cpustate->regs.w[DI],cpustate->regs.b[AL]);
+ cpustate->regs.w[DI] += cpustate->DirVal;
ICOUNT -= timing.rep_stos8_count;
}
- I.regs.w[CX]=count;
+ cpustate->regs.w[CX]=count;
break;
case 0xab: /* REP STOSW */
ICOUNT -= timing.rep_stos16_base;
for (; count > 0; count--)
{
- if (ICOUNT <= 0) { I.pc = I.prevpc; break; }
- PutMemW(ES,I.regs.w[DI],I.regs.w[AX]);
- I.regs.w[DI] += 2 * I.DirVal;
+ if (ICOUNT <= 0) { cpustate->pc = cpustate->prevpc; break; }
+ PutMemW(ES,cpustate->regs.w[DI],cpustate->regs.w[AX]);
+ cpustate->regs.w[DI] += 2 * cpustate->DirVal;
ICOUNT -= timing.rep_stos16_count;
}
- I.regs.w[CX]=count;
+ cpustate->regs.w[CX]=count;
break;
case 0xac: /* REP LODSB */
ICOUNT -= timing.rep_lods8_base;
for (; count > 0; count--)
{
- if (ICOUNT <= 0) { I.pc = I.prevpc; break; }
- I.regs.b[AL] = GetMemB(DS,I.regs.w[SI]);
- I.regs.w[SI] += I.DirVal;
+ if (ICOUNT <= 0) { cpustate->pc = cpustate->prevpc; break; }
+ cpustate->regs.b[AL] = GetMemB(DS,cpustate->regs.w[SI]);
+ cpustate->regs.w[SI] += cpustate->DirVal;
ICOUNT -= timing.rep_lods8_count;
}
- I.regs.w[CX]=count;
+ cpustate->regs.w[CX]=count;
break;
case 0xad: /* REP LODSW */
ICOUNT -= timing.rep_lods16_base;
for (; count > 0; count--)
{
- if (ICOUNT <= 0) { I.pc = I.prevpc; break; }
- I.regs.w[AX] = GetMemW(DS,I.regs.w[SI]);
- I.regs.w[SI] += 2 * I.DirVal;
+ if (ICOUNT <= 0) { cpustate->pc = cpustate->prevpc; break; }
+ cpustate->regs.w[AX] = GetMemW(DS,cpustate->regs.w[SI]);
+ cpustate->regs.w[SI] += 2 * cpustate->DirVal;
ICOUNT -= timing.rep_lods16_count;
}
- I.regs.w[CX]=count;
+ cpustate->regs.w[CX]=count;
break;
case 0xae: /* REP(N)E SCASB */
ICOUNT -= timing.rep_scas8_base;
- for (I.ZeroVal = !flagval; (ZF == flagval) && (count > 0); count--)
+ for (cpustate->ZeroVal = !flagval; (ZF == flagval) && (count > 0); count--)
{
unsigned src, dst;
- if (ICOUNT <= 0) { I.pc = I.prevpc; break; }
- src = GetMemB(ES, I.regs.w[DI]);
- dst = I.regs.b[AL];
+ if (ICOUNT <= 0) { cpustate->pc = cpustate->prevpc; break; }
+ src = GetMemB(ES, cpustate->regs.w[DI]);
+ dst = cpustate->regs.b[AL];
SUBB(dst,src);
- I.regs.w[DI] += I.DirVal;
+ cpustate->regs.w[DI] += cpustate->DirVal;
ICOUNT -= timing.rep_scas8_count;
}
- I.regs.w[CX]=count;
+ cpustate->regs.w[CX]=count;
break;
case 0xaf: /* REP(N)E SCASW */
ICOUNT -= timing.rep_scas16_base;
- for (I.ZeroVal = !flagval; (ZF == flagval) && (count > 0); count--)
+ for (cpustate->ZeroVal = !flagval; (ZF == flagval) && (count > 0); count--)
{
unsigned src, dst;
- if (ICOUNT <= 0) { I.pc = I.prevpc; break; }
- src = GetMemW(ES, I.regs.w[DI]);
- dst = I.regs.w[AX];
+ if (ICOUNT <= 0) { cpustate->pc = cpustate->prevpc; break; }
+ src = GetMemW(ES, cpustate->regs.w[DI]);
+ dst = cpustate->regs.w[AX];
SUBW(dst,src);
- I.regs.w[DI] += 2 * I.DirVal;
+ cpustate->regs.w[DI] += 2 * cpustate->DirVal;
ICOUNT -= timing.rep_scas16_count;
}
- I.regs.w[CX]=count;
+ cpustate->regs.w[CX]=count;
break;
default:
- PREFIX(_instruction)[next]();
+ PREFIX(_instruction)[next](cpustate);
}
}
#ifndef I80186
-static void PREFIX86(_add_br8)(void) /* Opcode 0x00 */
+static void PREFIX86(_add_br8)(i8086_state *cpustate) /* Opcode 0x00 */
{
DEF_br8(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr8 : timing.alu_mr8;
@@ -610,7 +610,7 @@ static void PREFIX86(_add_br8)(void) /* Opcode 0x00 */
PutbackRMByte(ModRM,dst);
}
-static void PREFIX86(_add_wr16)(void) /* Opcode 0x01 */
+static void PREFIX86(_add_wr16)(i8086_state *cpustate) /* Opcode 0x01 */
{
DEF_wr16(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr16 : timing.alu_mr16;
@@ -618,7 +618,7 @@ static void PREFIX86(_add_wr16)(void) /* Opcode 0x01 */
PutbackRMWord(ModRM,dst);
}
-static void PREFIX86(_add_r8b)(void) /* Opcode 0x02 */
+static void PREFIX86(_add_r8b)(i8086_state *cpustate) /* Opcode 0x02 */
{
DEF_r8b(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr8 : timing.alu_rm8;
@@ -626,7 +626,7 @@ static void PREFIX86(_add_r8b)(void) /* Opcode 0x02 */
RegByte(ModRM)=dst;
}
-static void PREFIX86(_add_r16w)(void) /* Opcode 0x03 */
+static void PREFIX86(_add_r16w)(i8086_state *cpustate) /* Opcode 0x03 */
{
DEF_r16w(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr16 : timing.alu_rm16;
@@ -635,45 +635,45 @@ static void PREFIX86(_add_r16w)(void) /* Opcode 0x03 */
}
-static void PREFIX86(_add_ald8)(void) /* Opcode 0x04 */
+static void PREFIX86(_add_ald8)(i8086_state *cpustate) /* Opcode 0x04 */
{
DEF_ald8(dst,src);
ICOUNT -= timing.alu_ri8;
ADDB(dst,src);
- I.regs.b[AL]=dst;
+ cpustate->regs.b[AL]=dst;
}
-static void PREFIX86(_add_axd16)(void) /* Opcode 0x05 */
+static void PREFIX86(_add_axd16)(i8086_state *cpustate) /* Opcode 0x05 */
{
DEF_axd16(dst,src);
ICOUNT -= timing.alu_ri16;
ADDW(dst,src);
- I.regs.w[AX]=dst;
+ cpustate->regs.w[AX]=dst;
}
-static void PREFIX86(_push_es)(void) /* Opcode 0x06 */
+static void PREFIX86(_push_es)(i8086_state *cpustate) /* Opcode 0x06 */
{
ICOUNT -= timing.push_seg;
- PUSH(I.sregs[ES]);
+ PUSH(cpustate->sregs[ES]);
}
-static void PREFIX86(_pop_es)(void) /* Opcode 0x07 */
+static void PREFIX86(_pop_es)(i8086_state *cpustate) /* Opcode 0x07 */
{
#ifdef I80286
UINT16 tmp;
POP(tmp);
- i80286_data_descriptor(ES,tmp);
+ i80286_data_descriptor(cpustate,ES,tmp);
#else
- POP(I.sregs[ES]);
- I.base[ES] = SegBase(ES);
+ POP(cpustate->sregs[ES]);
+ cpustate->base[ES] = SegBase(ES);
#endif
ICOUNT -= timing.pop_seg;
}
-static void PREFIX86(_or_br8)(void) /* Opcode 0x08 */
+static void PREFIX86(_or_br8)(i8086_state *cpustate) /* Opcode 0x08 */
{
DEF_br8(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr8 : timing.alu_mr8;
@@ -681,7 +681,7 @@ static void PREFIX86(_or_br8)(void) /* Opcode 0x08 */
PutbackRMByte(ModRM,dst);
}
-static void PREFIX86(_or_wr16)(void) /* Opcode 0x09 */
+static void PREFIX86(_or_wr16)(i8086_state *cpustate) /* Opcode 0x09 */
{
DEF_wr16(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr16 : timing.alu_mr16;
@@ -689,7 +689,7 @@ static void PREFIX86(_or_wr16)(void) /* Opcode 0x09 */
PutbackRMWord(ModRM,dst);
}
-static void PREFIX86(_or_r8b)(void) /* Opcode 0x0a */
+static void PREFIX86(_or_r8b)(i8086_state *cpustate) /* Opcode 0x0a */
{
DEF_r8b(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr8 : timing.alu_rm8;
@@ -697,7 +697,7 @@ static void PREFIX86(_or_r8b)(void) /* Opcode 0x0a */
RegByte(ModRM)=dst;
}
-static void PREFIX86(_or_r16w)(void) /* Opcode 0x0b */
+static void PREFIX86(_or_r16w)(i8086_state *cpustate) /* Opcode 0x0b */
{
DEF_r16w(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr16 : timing.alu_rm16;
@@ -705,31 +705,31 @@ static void PREFIX86(_or_r16w)(void) /* Opcode 0x0b */
RegWord(ModRM)=dst;
}
-static void PREFIX86(_or_ald8)(void) /* Opcode 0x0c */
+static void PREFIX86(_or_ald8)(i8086_state *cpustate) /* Opcode 0x0c */
{
DEF_ald8(dst,src);
ICOUNT -= timing.alu_ri8;
ORB(dst,src);
- I.regs.b[AL]=dst;
+ cpustate->regs.b[AL]=dst;
}
-static void PREFIX86(_or_axd16)(void) /* Opcode 0x0d */
+static void PREFIX86(_or_axd16)(i8086_state *cpustate) /* Opcode 0x0d */
{
DEF_axd16(dst,src);
ICOUNT -= timing.alu_ri16;
ORW(dst,src);
- I.regs.w[AX]=dst;
+ cpustate->regs.w[AX]=dst;
}
-static void PREFIX86(_push_cs)(void) /* Opcode 0x0e */
+static void PREFIX86(_push_cs)(i8086_state *cpustate) /* Opcode 0x0e */
{
ICOUNT -= timing.push_seg;
- PUSH(I.sregs[CS]);
+ PUSH(cpustate->sregs[CS]);
}
/* Opcode 0x0f invalid */
-static void PREFIX86(_adc_br8)(void) /* Opcode 0x10 */
+static void PREFIX86(_adc_br8)(i8086_state *cpustate) /* Opcode 0x10 */
{
DEF_br8(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr8 : timing.alu_mr8;
@@ -738,7 +738,7 @@ static void PREFIX86(_adc_br8)(void) /* Opcode 0x10 */
PutbackRMByte(ModRM,dst);
}
-static void PREFIX86(_adc_wr16)(void) /* Opcode 0x11 */
+static void PREFIX86(_adc_wr16)(i8086_state *cpustate) /* Opcode 0x11 */
{
DEF_wr16(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr16 : timing.alu_mr16;
@@ -747,7 +747,7 @@ static void PREFIX86(_adc_wr16)(void) /* Opcode 0x11 */
PutbackRMWord(ModRM,dst);
}
-static void PREFIX86(_adc_r8b)(void) /* Opcode 0x12 */
+static void PREFIX86(_adc_r8b)(i8086_state *cpustate) /* Opcode 0x12 */
{
DEF_r8b(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr8 : timing.alu_rm8;
@@ -756,7 +756,7 @@ static void PREFIX86(_adc_r8b)(void) /* Opcode 0x12 */
RegByte(ModRM)=dst;
}
-static void PREFIX86(_adc_r16w)(void) /* Opcode 0x13 */
+static void PREFIX86(_adc_r16w)(i8086_state *cpustate) /* Opcode 0x13 */
{
DEF_r16w(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr16 : timing.alu_rm16;
@@ -765,45 +765,45 @@ static void PREFIX86(_adc_r16w)(void) /* Opcode 0x13 */
RegWord(ModRM)=dst;
}
-static void PREFIX86(_adc_ald8)(void) /* Opcode 0x14 */
+static void PREFIX86(_adc_ald8)(i8086_state *cpustate) /* Opcode 0x14 */
{
DEF_ald8(dst,src);
ICOUNT -= timing.alu_ri8;
src+=CF;
ADDB(dst,src);
- I.regs.b[AL] = dst;
+ cpustate->regs.b[AL] = dst;
}
-static void PREFIX86(_adc_axd16)(void) /* Opcode 0x15 */
+static void PREFIX86(_adc_axd16)(i8086_state *cpustate) /* Opcode 0x15 */
{
DEF_axd16(dst,src);
ICOUNT -= timing.alu_ri16;
src+=CF;
ADDW(dst,src);
- I.regs.w[AX]=dst;
+ cpustate->regs.w[AX]=dst;
}
-static void PREFIX86(_push_ss)(void) /* Opcode 0x16 */
+static void PREFIX86(_push_ss)(i8086_state *cpustate) /* Opcode 0x16 */
{
- PUSH(I.sregs[SS]);
+ PUSH(cpustate->sregs[SS]);
ICOUNT -= timing.push_seg;
}
-static void PREFIX86(_pop_ss)(void) /* Opcode 0x17 */
+static void PREFIX86(_pop_ss)(i8086_state *cpustate) /* Opcode 0x17 */
{
#ifdef I80286
UINT16 tmp;
POP(tmp);
- i80286_data_descriptor(SS, tmp);
+ i80286_data_descriptor(cpustate, SS, tmp);
#else
- POP(I.sregs[SS]);
- I.base[SS] = SegBase(SS);
+ POP(cpustate->sregs[SS]);
+ cpustate->base[SS] = SegBase(SS);
#endif
ICOUNT -= timing.pop_seg;
- PREFIX(_instruction)[FETCHOP](); /* no interrupt before next instruction */
+ PREFIX(_instruction)[FETCHOP](cpustate); /* no interrupt before next instruction */
}
-static void PREFIX86(_sbb_br8)(void) /* Opcode 0x18 */
+static void PREFIX86(_sbb_br8)(i8086_state *cpustate) /* Opcode 0x18 */
{
DEF_br8(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr8 : timing.alu_mr8;
@@ -812,7 +812,7 @@ static void PREFIX86(_sbb_br8)(void) /* Opcode 0x18 */
PutbackRMByte(ModRM,dst);
}
-static void PREFIX86(_sbb_wr16)(void) /* Opcode 0x19 */
+static void PREFIX86(_sbb_wr16)(i8086_state *cpustate) /* Opcode 0x19 */
{
DEF_wr16(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr16 : timing.alu_mr16;
@@ -821,7 +821,7 @@ static void PREFIX86(_sbb_wr16)(void) /* Opcode 0x19 */
PutbackRMWord(ModRM,dst);
}
-static void PREFIX86(_sbb_r8b)(void) /* Opcode 0x1a */
+static void PREFIX86(_sbb_r8b)(i8086_state *cpustate) /* Opcode 0x1a */
{
DEF_r8b(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr8 : timing.alu_rm8;
@@ -830,7 +830,7 @@ static void PREFIX86(_sbb_r8b)(void) /* Opcode 0x1a */
RegByte(ModRM)=dst;
}
-static void PREFIX86(_sbb_r16w)(void) /* Opcode 0x1b */
+static void PREFIX86(_sbb_r16w)(i8086_state *cpustate) /* Opcode 0x1b */
{
DEF_r16w(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr16 : timing.alu_rm16;
@@ -839,44 +839,44 @@ static void PREFIX86(_sbb_r16w)(void) /* Opcode 0x1b */
RegWord(ModRM)= dst;
}
-static void PREFIX86(_sbb_ald8)(void) /* Opcode 0x1c */
+static void PREFIX86(_sbb_ald8)(i8086_state *cpustate) /* Opcode 0x1c */
{
DEF_ald8(dst,src);
ICOUNT -= timing.alu_ri8;
src+=CF;
SUBB(dst,src);
- I.regs.b[AL] = dst;
+ cpustate->regs.b[AL] = dst;
}
-static void PREFIX86(_sbb_axd16)(void) /* Opcode 0x1d */
+static void PREFIX86(_sbb_axd16)(i8086_state *cpustate) /* Opcode 0x1d */
{
DEF_axd16(dst,src);
ICOUNT -= timing.alu_ri16;
src+=CF;
SUBW(dst,src);
- I.regs.w[AX]=dst;
+ cpustate->regs.w[AX]=dst;
}
-static void PREFIX86(_push_ds)(void) /* Opcode 0x1e */
+static void PREFIX86(_push_ds)(i8086_state *cpustate) /* Opcode 0x1e */
{
- PUSH(I.sregs[DS]);
+ PUSH(cpustate->sregs[DS]);
ICOUNT -= timing.push_seg;
}
-static void PREFIX86(_pop_ds)(void) /* Opcode 0x1f */
+static void PREFIX86(_pop_ds)(i8086_state *cpustate) /* Opcode 0x1f */
{
#ifdef I80286
UINT16 tmp;
POP(tmp);
- i80286_data_descriptor(DS,tmp);
+ i80286_data_descriptor(cpustate,DS,tmp);
#else
- POP(I.sregs[DS]);
- I.base[DS] = SegBase(DS);
+ POP(cpustate->sregs[DS]);
+ cpustate->base[DS] = SegBase(DS);
#endif
ICOUNT -= timing.push_seg;
}
-static void PREFIX86(_and_br8)(void) /* Opcode 0x20 */
+static void PREFIX86(_and_br8)(i8086_state *cpustate) /* Opcode 0x20 */
{
DEF_br8(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr8 : timing.alu_mr8;
@@ -884,7 +884,7 @@ static void PREFIX86(_and_br8)(void) /* Opcode 0x20 */
PutbackRMByte(ModRM,dst);
}
-static void PREFIX86(_and_wr16)(void) /* Opcode 0x21 */
+static void PREFIX86(_and_wr16)(i8086_state *cpustate) /* Opcode 0x21 */
{
DEF_wr16(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr16 : timing.alu_mr16;
@@ -892,7 +892,7 @@ static void PREFIX86(_and_wr16)(void) /* Opcode 0x21 */
PutbackRMWord(ModRM,dst);
}
-static void PREFIX86(_and_r8b)(void) /* Opcode 0x22 */
+static void PREFIX86(_and_r8b)(i8086_state *cpustate) /* Opcode 0x22 */
{
DEF_r8b(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr8 : timing.alu_rm8;
@@ -900,7 +900,7 @@ static void PREFIX86(_and_r8b)(void) /* Opcode 0x22 */
RegByte(ModRM)=dst;
}
-static void PREFIX86(_and_r16w)(void) /* Opcode 0x23 */
+static void PREFIX86(_and_r16w)(i8086_state *cpustate) /* Opcode 0x23 */
{
DEF_r16w(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr16 : timing.alu_rm16;
@@ -908,51 +908,51 @@ static void PREFIX86(_and_r16w)(void) /* Opcode 0x23 */
RegWord(ModRM)=dst;
}
-static void PREFIX86(_and_ald8)(void) /* Opcode 0x24 */
+static void PREFIX86(_and_ald8)(i8086_state *cpustate) /* Opcode 0x24 */
{
DEF_ald8(dst,src);
ICOUNT -= timing.alu_ri8;
ANDB(dst,src);
- I.regs.b[AL] = dst;
+ cpustate->regs.b[AL] = dst;
}
-static void PREFIX86(_and_axd16)(void) /* Opcode 0x25 */
+static void PREFIX86(_and_axd16)(i8086_state *cpustate) /* Opcode 0x25 */
{
DEF_axd16(dst,src);
ICOUNT -= timing.alu_ri16;
ANDW(dst,src);
- I.regs.w[AX]=dst;
+ cpustate->regs.w[AX]=dst;
}
-static void PREFIX86(_es)(void) /* Opcode 0x26 */
+static void PREFIX86(_es)(i8086_state *cpustate) /* Opcode 0x26 */
{
- seg_prefix=TRUE;
- prefix_base=I.base[ES];
+ cpustate->seg_prefix=TRUE;
+ cpustate->prefix_base=cpustate->base[ES];
ICOUNT -= timing.override;
- PREFIX(_instruction)[FETCHOP]();
+ PREFIX(_instruction)[FETCHOP](cpustate);
}
-static void PREFIX86(_daa)(void) /* Opcode 0x27 */
+static void PREFIX86(_daa)(i8086_state *cpustate) /* Opcode 0x27 */
{
- if (AF || ((I.regs.b[AL] & 0xf) > 9))
+ if (AF || ((cpustate->regs.b[AL] & 0xf) > 9))
{
int tmp;
- I.regs.b[AL] = tmp = I.regs.b[AL] + 6;
- I.AuxVal = 1;
- I.CarryVal |= tmp & 0x100;
+ cpustate->regs.b[AL] = tmp = cpustate->regs.b[AL] + 6;
+ cpustate->AuxVal = 1;
+ cpustate->CarryVal |= tmp & 0x100;
}
- if (CF || (I.regs.b[AL] > 0x9f))
+ if (CF || (cpustate->regs.b[AL] > 0x9f))
{
- I.regs.b[AL] += 0x60;
- I.CarryVal = 1;
+ cpustate->regs.b[AL] += 0x60;
+ cpustate->CarryVal = 1;
}
- SetSZPF_Byte(I.regs.b[AL]);
+ SetSZPF_Byte(cpustate->regs.b[AL]);
ICOUNT -= timing.daa;
}
-static void PREFIX86(_sub_br8)(void) /* Opcode 0x28 */
+static void PREFIX86(_sub_br8)(i8086_state *cpustate) /* Opcode 0x28 */
{
DEF_br8(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr8 : timing.alu_mr8;
@@ -960,7 +960,7 @@ static void PREFIX86(_sub_br8)(void) /* Opcode 0x28 */
PutbackRMByte(ModRM,dst);
}
-static void PREFIX86(_sub_wr16)(void) /* Opcode 0x29 */
+static void PREFIX86(_sub_wr16)(i8086_state *cpustate) /* Opcode 0x29 */
{
DEF_wr16(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr16 : timing.alu_mr16;
@@ -968,7 +968,7 @@ static void PREFIX86(_sub_wr16)(void) /* Opcode 0x29 */
PutbackRMWord(ModRM,dst);
}
-static void PREFIX86(_sub_r8b)(void) /* Opcode 0x2a */
+static void PREFIX86(_sub_r8b)(i8086_state *cpustate) /* Opcode 0x2a */
{
DEF_r8b(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr8 : timing.alu_rm8;
@@ -976,7 +976,7 @@ static void PREFIX86(_sub_r8b)(void) /* Opcode 0x2a */
RegByte(ModRM)=dst;
}
-static void PREFIX86(_sub_r16w)(void) /* Opcode 0x2b */
+static void PREFIX86(_sub_r16w)(i8086_state *cpustate) /* Opcode 0x2b */
{
DEF_r16w(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr16 : timing.alu_rm16;
@@ -984,52 +984,52 @@ static void PREFIX86(_sub_r16w)(void) /* Opcode 0x2b */
RegWord(ModRM)=dst;
}
-static void PREFIX86(_sub_ald8)(void) /* Opcode 0x2c */
+static void PREFIX86(_sub_ald8)(i8086_state *cpustate) /* Opcode 0x2c */
{
DEF_ald8(dst,src);
ICOUNT -= timing.alu_ri8;
SUBB(dst,src);
- I.regs.b[AL] = dst;
+ cpustate->regs.b[AL] = dst;
}
-static void PREFIX86(_sub_axd16)(void) /* Opcode 0x2d */
+static void PREFIX86(_sub_axd16)(i8086_state *cpustate) /* Opcode 0x2d */
{
DEF_axd16(dst,src);
ICOUNT -= timing.alu_ri16;
SUBW(dst,src);
- I.regs.w[AX]=dst;
+ cpustate->regs.w[AX]=dst;
}
-static void PREFIX86(_cs)(void) /* Opcode 0x2e */
+static void PREFIX86(_cs)(i8086_state *cpustate) /* Opcode 0x2e */
{
- seg_prefix=TRUE;
- prefix_base=I.base[CS];
+ cpustate->seg_prefix=TRUE;
+ cpustate->prefix_base=cpustate->base[CS];
ICOUNT -= timing.override;
- PREFIX(_instruction)[FETCHOP]();
+ PREFIX(_instruction)[FETCHOP](cpustate);
}
-static void PREFIX86(_das)(void) /* Opcode 0x2f */
+static void PREFIX86(_das)(i8086_state *cpustate) /* Opcode 0x2f */
{
- UINT8 tmpAL=I.regs.b[AL];
- if (AF || ((I.regs.b[AL] & 0xf) > 9))
+ UINT8 tmpAL=cpustate->regs.b[AL];
+ if (AF || ((cpustate->regs.b[AL] & 0xf) > 9))
{
int tmp;
- I.regs.b[AL] = tmp = I.regs.b[AL] - 6;
- I.AuxVal = 1;
- I.CarryVal |= tmp & 0x100;
+ cpustate->regs.b[AL] = tmp = cpustate->regs.b[AL] - 6;
+ cpustate->AuxVal = 1;
+ cpustate->CarryVal |= tmp & 0x100;
}
if (CF || (tmpAL > 0x9f))
{
- I.regs.b[AL] -= 0x60;
- I.CarryVal = 1;
+ cpustate->regs.b[AL] -= 0x60;
+ cpustate->CarryVal = 1;
}
- SetSZPF_Byte(I.regs.b[AL]);
+ SetSZPF_Byte(cpustate->regs.b[AL]);
ICOUNT -= timing.das;
}
-static void PREFIX86(_xor_br8)(void) /* Opcode 0x30 */
+static void PREFIX86(_xor_br8)(i8086_state *cpustate) /* Opcode 0x30 */
{
DEF_br8(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr8 : timing.alu_mr8;
@@ -1037,7 +1037,7 @@ static void PREFIX86(_xor_br8)(void) /* Opcode 0x30 */
PutbackRMByte(ModRM,dst);
}
-static void PREFIX86(_xor_wr16)(void) /* Opcode 0x31 */
+static void PREFIX86(_xor_wr16)(i8086_state *cpustate) /* Opcode 0x31 */
{
DEF_wr16(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr16 : timing.alu_mr16;
@@ -1045,7 +1045,7 @@ static void PREFIX86(_xor_wr16)(void) /* Opcode 0x31 */
PutbackRMWord(ModRM,dst);
}
-static void PREFIX86(_xor_r8b)(void) /* Opcode 0x32 */
+static void PREFIX86(_xor_r8b)(i8086_state *cpustate) /* Opcode 0x32 */
{
DEF_r8b(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr8 : timing.alu_rm8;
@@ -1053,7 +1053,7 @@ static void PREFIX86(_xor_r8b)(void) /* Opcode 0x32 */
RegByte(ModRM)=dst;
}
-static void PREFIX86(_xor_r16w)(void) /* Opcode 0x33 */
+static void PREFIX86(_xor_r16w)(i8086_state *cpustate) /* Opcode 0x33 */
{
DEF_r16w(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr16 : timing.alu_rm16;
@@ -1061,499 +1061,499 @@ static void PREFIX86(_xor_r16w)(void) /* Opcode 0x33 */
RegWord(ModRM)=dst;
}
-static void PREFIX86(_xor_ald8)(void) /* Opcode 0x34 */
+static void PREFIX86(_xor_ald8)(i8086_state *cpustate) /* Opcode 0x34 */
{
DEF_ald8(dst,src);
ICOUNT -= timing.alu_ri8;
XORB(dst,src);
- I.regs.b[AL] = dst;
+ cpustate->regs.b[AL] = dst;
}
-static void PREFIX86(_xor_axd16)(void) /* Opcode 0x35 */
+static void PREFIX86(_xor_axd16)(i8086_state *cpustate) /* Opcode 0x35 */
{
DEF_axd16(dst,src);
ICOUNT -= timing.alu_ri16;
XORW(dst,src);
- I.regs.w[AX]=dst;
+ cpustate->regs.w[AX]=dst;
}
-static void PREFIX86(_ss)(void) /* Opcode 0x36 */
+static void PREFIX86(_ss)(i8086_state *cpustate) /* Opcode 0x36 */
{
- seg_prefix=TRUE;
- prefix_base=I.base[SS];
+ cpustate->seg_prefix=TRUE;
+ cpustate->prefix_base=cpustate->base[SS];
ICOUNT -= timing.override;
- PREFIX(_instruction)[FETCHOP]();
+ PREFIX(_instruction)[FETCHOP](cpustate);
}
-static void PREFIX86(_aaa)(void) /* Opcode 0x37 */
+static void PREFIX86(_aaa)(i8086_state *cpustate) /* Opcode 0x37 */
{
UINT8 ALcarry=1;
- if (I.regs.b[AL]>0xf9) ALcarry=2;
+ if (cpustate->regs.b[AL]>0xf9) ALcarry=2;
- if (AF || ((I.regs.b[AL] & 0xf) > 9))
+ if (AF || ((cpustate->regs.b[AL] & 0xf) > 9))
{
- I.regs.b[AL] += 6;
- I.regs.b[AH] += ALcarry;
- I.AuxVal = 1;
- I.CarryVal = 1;
+ cpustate->regs.b[AL] += 6;
+ cpustate->regs.b[AH] += ALcarry;
+ cpustate->AuxVal = 1;
+ cpustate->CarryVal = 1;
}
else
{
- I.AuxVal = 0;
- I.CarryVal = 0;
+ cpustate->AuxVal = 0;
+ cpustate->CarryVal = 0;
}
- I.regs.b[AL] &= 0x0F;
+ cpustate->regs.b[AL] &= 0x0F;
ICOUNT -= timing.aaa;
}
-static void PREFIX86(_cmp_br8)(void) /* Opcode 0x38 */
+static void PREFIX86(_cmp_br8)(i8086_state *cpustate) /* Opcode 0x38 */
{
DEF_br8(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr8 : timing.alu_rm8;
SUBB(dst,src);
}
-static void PREFIX86(_cmp_wr16)(void) /* Opcode 0x39 */
+static void PREFIX86(_cmp_wr16)(i8086_state *cpustate) /* Opcode 0x39 */
{
DEF_wr16(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr16 : timing.alu_rm16;
SUBW(dst,src);
}
-static void PREFIX86(_cmp_r8b)(void) /* Opcode 0x3a */
+static void PREFIX86(_cmp_r8b)(i8086_state *cpustate) /* Opcode 0x3a */
{
DEF_r8b(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr8 : timing.alu_rm8;
SUBB(dst,src);
}
-static void PREFIX86(_cmp_r16w)(void) /* Opcode 0x3b */
+static void PREFIX86(_cmp_r16w)(i8086_state *cpustate) /* Opcode 0x3b */
{
DEF_r16w(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr16 : timing.alu_rm16;
SUBW(dst,src);
}
-static void PREFIX86(_cmp_ald8)(void) /* Opcode 0x3c */
+static void PREFIX86(_cmp_ald8)(i8086_state *cpustate) /* Opcode 0x3c */
{
DEF_ald8(dst,src);
ICOUNT -= timing.alu_ri8;
SUBB(dst,src);
}
-static void PREFIX86(_cmp_axd16)(void) /* Opcode 0x3d */
+static void PREFIX86(_cmp_axd16)(i8086_state *cpustate) /* Opcode 0x3d */
{
DEF_axd16(dst,src);
ICOUNT -= timing.alu_ri16;
SUBW(dst,src);
}
-static void PREFIX86(_ds)(void) /* Opcode 0x3e */
+static void PREFIX86(_ds)(i8086_state *cpustate) /* Opcode 0x3e */
{
- seg_prefix=TRUE;
- prefix_base=I.base[DS];
+ cpustate->seg_prefix=TRUE;
+ cpustate->prefix_base=cpustate->base[DS];
ICOUNT -= timing.override;
- PREFIX(_instruction)[FETCHOP]();
+ PREFIX(_instruction)[FETCHOP](cpustate);
}
-static void PREFIX86(_aas)(void) /* Opcode 0x3f */
+static void PREFIX86(_aas)(i8086_state *cpustate) /* Opcode 0x3f */
{
UINT8 ALcarry=1;
- if (I.regs.b[AL]>0xf9) ALcarry=2;
+ if (cpustate->regs.b[AL]>0xf9) ALcarry=2;
- if (AF || ((I.regs.b[AL] & 0xf) > 9))
+ if (AF || ((cpustate->regs.b[AL] & 0xf) > 9))
{
- I.regs.b[AL] -= 6;
- I.regs.b[AH] -= 1;
- I.AuxVal = 1;
- I.CarryVal = 1;
+ cpustate->regs.b[AL] -= 6;
+ cpustate->regs.b[AH] -= 1;
+ cpustate->AuxVal = 1;
+ cpustate->CarryVal = 1;
}
else
{
- I.AuxVal = 0;
- I.CarryVal = 0;
+ cpustate->AuxVal = 0;
+ cpustate->CarryVal = 0;
}
- I.regs.b[AL] &= 0x0F;
+ cpustate->regs.b[AL] &= 0x0F;
ICOUNT -= timing.aas;
}
#define IncWordReg(Reg) \
{ \
- unsigned tmp = (unsigned)I.regs.w[Reg]; \
+ unsigned tmp = (unsigned)cpustate->regs.w[Reg]; \
unsigned tmp1 = tmp+1; \
SetOFW_Add(tmp1,tmp,1); \
SetAF(tmp1,tmp,1); \
SetSZPF_Word(tmp1); \
- I.regs.w[Reg]=tmp1; \
+ cpustate->regs.w[Reg]=tmp1; \
ICOUNT -= timing.incdec_r16; \
}
-static void PREFIX86(_inc_ax)(void) /* Opcode 0x40 */
+static void PREFIX86(_inc_ax)(i8086_state *cpustate) /* Opcode 0x40 */
{
IncWordReg(AX);
}
-static void PREFIX86(_inc_cx)(void) /* Opcode 0x41 */
+static void PREFIX86(_inc_cx)(i8086_state *cpustate) /* Opcode 0x41 */
{
IncWordReg(CX);
}
-static void PREFIX86(_inc_dx)(void) /* Opcode 0x42 */
+static void PREFIX86(_inc_dx)(i8086_state *cpustate) /* Opcode 0x42 */
{
IncWordReg(DX);
}
-static void PREFIX(_inc_bx)(void) /* Opcode 0x43 */
+static void PREFIX(_inc_bx)(i8086_state *cpustate) /* Opcode 0x43 */
{
IncWordReg(BX);
}
-static void PREFIX86(_inc_sp)(void) /* Opcode 0x44 */
+static void PREFIX86(_inc_sp)(i8086_state *cpustate) /* Opcode 0x44 */
{
IncWordReg(SP);
}
-static void PREFIX86(_inc_bp)(void) /* Opcode 0x45 */
+static void PREFIX86(_inc_bp)(i8086_state *cpustate) /* Opcode 0x45 */
{
IncWordReg(BP);
}
-static void PREFIX86(_inc_si)(void) /* Opcode 0x46 */
+static void PREFIX86(_inc_si)(i8086_state *cpustate) /* Opcode 0x46 */
{
IncWordReg(SI);
}
-static void PREFIX86(_inc_di)(void) /* Opcode 0x47 */
+static void PREFIX86(_inc_di)(i8086_state *cpustate) /* Opcode 0x47 */
{
IncWordReg(DI);
}
#define DecWordReg(Reg) \
{ \
- unsigned tmp = (unsigned)I.regs.w[Reg]; \
+ unsigned tmp = (unsigned)cpustate->regs.w[Reg]; \
unsigned tmp1 = tmp-1; \
SetOFW_Sub(tmp1,1,tmp); \
SetAF(tmp1,tmp,1); \
SetSZPF_Word(tmp1); \
- I.regs.w[Reg]=tmp1; \
+ cpustate->regs.w[Reg]=tmp1; \
ICOUNT -= timing.incdec_r16; \
}
-static void PREFIX86(_dec_ax)(void) /* Opcode 0x48 */
+static void PREFIX86(_dec_ax)(i8086_state *cpustate) /* Opcode 0x48 */
{
DecWordReg(AX);
}
-static void PREFIX86(_dec_cx)(void) /* Opcode 0x49 */
+static void PREFIX86(_dec_cx)(i8086_state *cpustate) /* Opcode 0x49 */
{
DecWordReg(CX);
}
-static void PREFIX86(_dec_dx)(void) /* Opcode 0x4a */
+static void PREFIX86(_dec_dx)(i8086_state *cpustate) /* Opcode 0x4a */
{
DecWordReg(DX);
}
-static void PREFIX86(_dec_bx)(void) /* Opcode 0x4b */
+static void PREFIX86(_dec_bx)(i8086_state *cpustate) /* Opcode 0x4b */
{
DecWordReg(BX);
}
-static void PREFIX86(_dec_sp)(void) /* Opcode 0x4c */
+static void PREFIX86(_dec_sp)(i8086_state *cpustate) /* Opcode 0x4c */
{
DecWordReg(SP);
}
-static void PREFIX86(_dec_bp)(void) /* Opcode 0x4d */
+static void PREFIX86(_dec_bp)(i8086_state *cpustate) /* Opcode 0x4d */
{
DecWordReg(BP);
}
-static void PREFIX86(_dec_si)(void) /* Opcode 0x4e */
+static void PREFIX86(_dec_si)(i8086_state *cpustate) /* Opcode 0x4e */
{
DecWordReg(SI);
}
-static void PREFIX86(_dec_di)(void) /* Opcode 0x4f */
+static void PREFIX86(_dec_di)(i8086_state *cpustate) /* Opcode 0x4f */
{
DecWordReg(DI);
}
-static void PREFIX86(_push_ax)(void) /* Opcode 0x50 */
+static void PREFIX86(_push_ax)(i8086_state *cpustate) /* Opcode 0x50 */
{
ICOUNT -= timing.push_r16;
- PUSH(I.regs.w[AX]);
+ PUSH(cpustate->regs.w[AX]);
}
-static void PREFIX86(_push_cx)(void) /* Opcode 0x51 */
+static void PREFIX86(_push_cx)(i8086_state *cpustate) /* Opcode 0x51 */
{
ICOUNT -= timing.push_r16;
- PUSH(I.regs.w[CX]);
+ PUSH(cpustate->regs.w[CX]);
}
-static void PREFIX86(_push_dx)(void) /* Opcode 0x52 */
+static void PREFIX86(_push_dx)(i8086_state *cpustate) /* Opcode 0x52 */
{
ICOUNT -= timing.push_r16;
- PUSH(I.regs.w[DX]);
+ PUSH(cpustate->regs.w[DX]);
}
-static void PREFIX86(_push_bx)(void) /* Opcode 0x53 */
+static void PREFIX86(_push_bx)(i8086_state *cpustate) /* Opcode 0x53 */
{
ICOUNT -= timing.push_r16;
- PUSH(I.regs.w[BX]);
+ PUSH(cpustate->regs.w[BX]);
}
-static void PREFIX86(_push_sp)(void) /* Opcode 0x54 */
+static void PREFIX86(_push_sp)(i8086_state *cpustate) /* Opcode 0x54 */
{
ICOUNT -= timing.push_r16;
- PUSH(I.regs.w[SP]);
+ PUSH(cpustate->regs.w[SP]);
}
-static void PREFIX86(_push_bp)(void) /* Opcode 0x55 */
+static void PREFIX86(_push_bp)(i8086_state *cpustate) /* Opcode 0x55 */
{
ICOUNT -= timing.push_r16;
- PUSH(I.regs.w[BP]);
+ PUSH(cpustate->regs.w[BP]);
}
-static void PREFIX86(_push_si)(void) /* Opcode 0x56 */
+static void PREFIX86(_push_si)(i8086_state *cpustate) /* Opcode 0x56 */
{
ICOUNT -= timing.push_r16;
- PUSH(I.regs.w[SI]);
+ PUSH(cpustate->regs.w[SI]);
}
-static void PREFIX86(_push_di)(void) /* Opcode 0x57 */
+static void PREFIX86(_push_di)(i8086_state *cpustate) /* Opcode 0x57 */
{
ICOUNT -= timing.push_r16;
- PUSH(I.regs.w[DI]);
+ PUSH(cpustate->regs.w[DI]);
}
-static void PREFIX86(_pop_ax)(void) /* Opcode 0x58 */
+static void PREFIX86(_pop_ax)(i8086_state *cpustate) /* Opcode 0x58 */
{
ICOUNT -= timing.pop_r16;
- POP(I.regs.w[AX]);
+ POP(cpustate->regs.w[AX]);
}
-static void PREFIX86(_pop_cx)(void) /* Opcode 0x59 */
+static void PREFIX86(_pop_cx)(i8086_state *cpustate) /* Opcode 0x59 */
{
ICOUNT -= timing.pop_r16;
- POP(I.regs.w[CX]);
+ POP(cpustate->regs.w[CX]);
}
-static void PREFIX86(_pop_dx)(void) /* Opcode 0x5a */
+static void PREFIX86(_pop_dx)(i8086_state *cpustate) /* Opcode 0x5a */
{
ICOUNT -= timing.pop_r16;
- POP(I.regs.w[DX]);
+ POP(cpustate->regs.w[DX]);
}
-static void PREFIX86(_pop_bx)(void) /* Opcode 0x5b */
+static void PREFIX86(_pop_bx)(i8086_state *cpustate) /* Opcode 0x5b */
{
ICOUNT -= timing.pop_r16;
- POP(I.regs.w[BX]);
+ POP(cpustate->regs.w[BX]);
}
-static void PREFIX86(_pop_sp)(void) /* Opcode 0x5c */
+static void PREFIX86(_pop_sp)(i8086_state *cpustate) /* Opcode 0x5c */
{
ICOUNT -= timing.pop_r16;
- POP(I.regs.w[SP]);
+ POP(cpustate->regs.w[SP]);
}
-static void PREFIX86(_pop_bp)(void) /* Opcode 0x5d */
+static void PREFIX86(_pop_bp)(i8086_state *cpustate) /* Opcode 0x5d */
{
ICOUNT -= timing.pop_r16;
- POP(I.regs.w[BP]);
+ POP(cpustate->regs.w[BP]);
}
-static void PREFIX86(_pop_si)(void) /* Opcode 0x5e */
+static void PREFIX86(_pop_si)(i8086_state *cpustate) /* Opcode 0x5e */
{
ICOUNT -= timing.pop_r16;
- POP(I.regs.w[SI]);
+ POP(cpustate->regs.w[SI]);
}
-static void PREFIX86(_pop_di)(void) /* Opcode 0x5f */
+static void PREFIX86(_pop_di)(i8086_state *cpustate) /* Opcode 0x5f */
{
ICOUNT -= timing.pop_r16;
- POP(I.regs.w[DI]);
+ POP(cpustate->regs.w[DI]);
}
-static void PREFIX86(_jo)(void) /* Opcode 0x70 */
+static void PREFIX86(_jo)(i8086_state *cpustate) /* Opcode 0x70 */
{
int tmp = (int)((INT8)FETCH);
if (OF)
{
- I.pc += tmp;
+ cpustate->pc += tmp;
ICOUNT -= timing.jcc_t;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.jcc_nt;
}
-static void PREFIX86(_jno)(void) /* Opcode 0x71 */
+static void PREFIX86(_jno)(i8086_state *cpustate) /* Opcode 0x71 */
{
int tmp = (int)((INT8)FETCH);
if (!OF) {
- I.pc += tmp;
+ cpustate->pc += tmp;
ICOUNT -= timing.jcc_t;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.jcc_nt;
}
-static void PREFIX86(_jb)(void) /* Opcode 0x72 */
+static void PREFIX86(_jb)(i8086_state *cpustate) /* Opcode 0x72 */
{
int tmp = (int)((INT8)FETCH);
if (CF) {
- I.pc += tmp;
+ cpustate->pc += tmp;
ICOUNT -= timing.jcc_t;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.jcc_nt;
}
-static void PREFIX86(_jnb)(void) /* Opcode 0x73 */
+static void PREFIX86(_jnb)(i8086_state *cpustate) /* Opcode 0x73 */
{
int tmp = (int)((INT8)FETCH);
if (!CF) {
- I.pc += tmp;
+ cpustate->pc += tmp;
ICOUNT -= timing.jcc_t;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.jcc_nt;
}
-static void PREFIX86(_jz)(void) /* Opcode 0x74 */
+static void PREFIX86(_jz)(i8086_state *cpustate) /* Opcode 0x74 */
{
int tmp = (int)((INT8)FETCH);
if (ZF) {
- I.pc += tmp;
+ cpustate->pc += tmp;
ICOUNT -= timing.jcc_t;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.jcc_nt;
}
-static void PREFIX86(_jnz)(void) /* Opcode 0x75 */
+static void PREFIX86(_jnz)(i8086_state *cpustate) /* Opcode 0x75 */
{
int tmp = (int)((INT8)FETCH);
if (!ZF) {
- I.pc += tmp;
+ cpustate->pc += tmp;
ICOUNT -= timing.jcc_t;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.jcc_nt;
}
-static void PREFIX86(_jbe)(void) /* Opcode 0x76 */
+static void PREFIX86(_jbe)(i8086_state *cpustate) /* Opcode 0x76 */
{
int tmp = (int)((INT8)FETCH);
if (CF || ZF) {
- I.pc += tmp;
+ cpustate->pc += tmp;
ICOUNT -= timing.jcc_t;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.jcc_nt;
}
-static void PREFIX86(_jnbe)(void) /* Opcode 0x77 */
+static void PREFIX86(_jnbe)(i8086_state *cpustate) /* Opcode 0x77 */
{
int tmp = (int)((INT8)FETCH);
if (!(CF || ZF)) {
- I.pc += tmp;
+ cpustate->pc += tmp;
ICOUNT -= timing.jcc_t;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.jcc_nt;
}
-static void PREFIX86(_js)(void) /* Opcode 0x78 */
+static void PREFIX86(_js)(i8086_state *cpustate) /* Opcode 0x78 */
{
int tmp = (int)((INT8)FETCH);
if (SF) {
- I.pc += tmp;
+ cpustate->pc += tmp;
ICOUNT -= timing.jcc_t;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.jcc_nt;
}
-static void PREFIX86(_jns)(void) /* Opcode 0x79 */
+static void PREFIX86(_jns)(i8086_state *cpustate) /* Opcode 0x79 */
{
int tmp = (int)((INT8)FETCH);
if (!SF) {
- I.pc += tmp;
+ cpustate->pc += tmp;
ICOUNT -= timing.jcc_t;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.jcc_nt;
}
-static void PREFIX86(_jp)(void) /* Opcode 0x7a */
+static void PREFIX86(_jp)(i8086_state *cpustate) /* Opcode 0x7a */
{
int tmp = (int)((INT8)FETCH);
if (PF) {
- I.pc += tmp;
+ cpustate->pc += tmp;
ICOUNT -= timing.jcc_t;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.jcc_nt;
}
-static void PREFIX86(_jnp)(void) /* Opcode 0x7b */
+static void PREFIX86(_jnp)(i8086_state *cpustate) /* Opcode 0x7b */
{
int tmp = (int)((INT8)FETCH);
if (!PF) {
- I.pc += tmp;
+ cpustate->pc += tmp;
ICOUNT -= timing.jcc_t;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.jcc_nt;
}
-static void PREFIX86(_jl)(void) /* Opcode 0x7c */
+static void PREFIX86(_jl)(i8086_state *cpustate) /* Opcode 0x7c */
{
int tmp = (int)((INT8)FETCH);
if ((SF!=OF)&&!ZF) {
- I.pc += tmp;
+ cpustate->pc += tmp;
ICOUNT -= timing.jcc_t;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.jcc_nt;
}
-static void PREFIX86(_jnl)(void) /* Opcode 0x7d */
+static void PREFIX86(_jnl)(i8086_state *cpustate) /* Opcode 0x7d */
{
int tmp = (int)((INT8)FETCH);
if (ZF||(SF==OF)) {
- I.pc += tmp;
+ cpustate->pc += tmp;
ICOUNT -= timing.jcc_t;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.jcc_nt;
}
-static void PREFIX86(_jle)(void) /* Opcode 0x7e */
+static void PREFIX86(_jle)(i8086_state *cpustate) /* Opcode 0x7e */
{
int tmp = (int)((INT8)FETCH);
if (ZF||(SF!=OF)) {
- I.pc += tmp;
+ cpustate->pc += tmp;
ICOUNT -= timing.jcc_t;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.jcc_nt;
}
-static void PREFIX86(_jnle)(void) /* Opcode 0x7f */
+static void PREFIX86(_jnle)(i8086_state *cpustate) /* Opcode 0x7f */
{
int tmp = (int)((INT8)FETCH);
if ((SF==OF)&&!ZF) {
- I.pc += tmp;
+ cpustate->pc += tmp;
ICOUNT -= timing.jcc_t;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.jcc_nt;
}
-static void PREFIX86(_80pre)(void) /* Opcode 0x80 */
+static void PREFIX86(_80pre)(i8086_state *cpustate) /* Opcode 0x80 */
{
unsigned ModRM = FETCHOP;
unsigned dst = GetRMByte(ModRM);
@@ -1606,7 +1606,7 @@ static void PREFIX86(_80pre)(void) /* Opcode 0x80 */
}
-static void PREFIX86(_81pre)(void) /* Opcode 0x81 */
+static void PREFIX86(_81pre)(i8086_state *cpustate) /* Opcode 0x81 */
{
unsigned ModRM = FETCH;
unsigned dst = GetRMWord(ModRM);
@@ -1659,7 +1659,7 @@ static void PREFIX86(_81pre)(void) /* Opcode 0x81 */
}
}
-static void PREFIX86(_82pre)(void) /* Opcode 0x82 */
+static void PREFIX86(_82pre)(i8086_state *cpustate) /* Opcode 0x82 */
{
unsigned ModRM = FETCH;
unsigned dst = GetRMByte(ModRM);
@@ -1711,7 +1711,7 @@ static void PREFIX86(_82pre)(void) /* Opcode 0x82 */
}
}
-static void PREFIX86(_83pre)(void) /* Opcode 0x83 */
+static void PREFIX86(_83pre)(i8086_state *cpustate) /* Opcode 0x83 */
{
unsigned ModRM = FETCH;
unsigned dst = GetRMWord(ModRM);
@@ -1763,21 +1763,21 @@ static void PREFIX86(_83pre)(void) /* Opcode 0x83 */
}
}
-static void PREFIX86(_test_br8)(void) /* Opcode 0x84 */
+static void PREFIX86(_test_br8)(i8086_state *cpustate) /* Opcode 0x84 */
{
DEF_br8(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr8 : timing.alu_rm8;
ANDB(dst,src);
}
-static void PREFIX86(_test_wr16)(void) /* Opcode 0x85 */
+static void PREFIX86(_test_wr16)(i8086_state *cpustate) /* Opcode 0x85 */
{
DEF_wr16(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_rr16 : timing.alu_rm16;
ANDW(dst,src);
}
-static void PREFIX86(_xchg_br8)(void) /* Opcode 0x86 */
+static void PREFIX86(_xchg_br8)(i8086_state *cpustate) /* Opcode 0x86 */
{
DEF_br8(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.xchg_rr8 : timing.xchg_rm8;
@@ -1785,7 +1785,7 @@ static void PREFIX86(_xchg_br8)(void) /* Opcode 0x86 */
PutbackRMByte(ModRM,src);
}
-static void PREFIX86(_xchg_wr16)(void) /* Opcode 0x87 */
+static void PREFIX86(_xchg_wr16)(i8086_state *cpustate) /* Opcode 0x87 */
{
DEF_wr16(dst,src);
ICOUNT -= (ModRM >= 0xc0) ? timing.xchg_rr16 : timing.xchg_rm16;
@@ -1793,7 +1793,7 @@ static void PREFIX86(_xchg_wr16)(void) /* Opcode 0x87 */
PutbackRMWord(ModRM,src);
}
-static void PREFIX86(_mov_br8)(void) /* Opcode 0x88 */
+static void PREFIX86(_mov_br8)(i8086_state *cpustate) /* Opcode 0x88 */
{
unsigned ModRM = FETCH;
BYTE src = RegByte(ModRM);
@@ -1801,7 +1801,7 @@ static void PREFIX86(_mov_br8)(void) /* Opcode 0x88 */
PutRMByte(ModRM,src);
}
-static void PREFIX86(_mov_wr16)(void) /* Opcode 0x89 */
+static void PREFIX86(_mov_wr16)(i8086_state *cpustate) /* Opcode 0x89 */
{
unsigned ModRM = FETCH;
WORD src = RegWord(ModRM);
@@ -1809,7 +1809,7 @@ static void PREFIX86(_mov_wr16)(void) /* Opcode 0x89 */
PutRMWord(ModRM,src);
}
-static void PREFIX86(_mov_r8b)(void) /* Opcode 0x8a */
+static void PREFIX86(_mov_r8b)(i8086_state *cpustate) /* Opcode 0x8a */
{
unsigned ModRM = FETCH;
BYTE src = GetRMByte(ModRM);
@@ -1817,7 +1817,7 @@ static void PREFIX86(_mov_r8b)(void) /* Opcode 0x8a */
RegByte(ModRM)=src;
}
-static void PREFIX86(_mov_r16w)(void) /* Opcode 0x8b */
+static void PREFIX86(_mov_r16w)(i8086_state *cpustate) /* Opcode 0x8b */
{
unsigned ModRM = FETCH;
WORD src = GetRMWord(ModRM);
@@ -1825,30 +1825,30 @@ static void PREFIX86(_mov_r16w)(void) /* Opcode 0x8b */
RegWord(ModRM)=src;
}
-static void PREFIX86(_mov_wsreg)(void) /* Opcode 0x8c */
+static void PREFIX86(_mov_wsreg)(i8086_state *cpustate) /* Opcode 0x8c */
{
unsigned ModRM = FETCH;
ICOUNT -= (ModRM >= 0xc0) ? timing.mov_rs : timing.mov_ms;
#ifdef I80286
if (ModRM & 0x20) { /* HJB 12/13/98 1xx is invalid */
- i80286_trap2(ILLEGAL_INSTRUCTION);
+ i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
return;
}
#else
if (ModRM & 0x20) return; /* HJB 12/13/98 1xx is invalid */
#endif
- PutRMWord(ModRM,I.sregs[(ModRM & 0x38) >> 3]);
+ PutRMWord(ModRM,cpustate->sregs[(ModRM & 0x38) >> 3]);
}
-static void PREFIX86(_lea)(void) /* Opcode 0x8d */
+static void PREFIX86(_lea)(i8086_state *cpustate) /* Opcode 0x8d */
{
unsigned ModRM = FETCH;
ICOUNT -= timing.lea;
- (void)(*GetEA[ModRM])();
- RegWord(ModRM)=EO; /* HJB 12/13/98 effective offset (no segment part) */
+ (void)(*GetEA[ModRM])(cpustate);
+ RegWord(ModRM)=cpustate->eo; /* HJB 12/13/98 effective offset (no segment part) */
}
-static void PREFIX86(_mov_sregw)(void) /* Opcode 0x8e */
+static void PREFIX86(_mov_sregw)(i8086_state *cpustate) /* Opcode 0x8e */
{
unsigned ModRM = FETCH;
WORD src = GetRMWord(ModRM);
@@ -1858,14 +1858,14 @@ static void PREFIX86(_mov_sregw)(void) /* Opcode 0x8e */
switch (ModRM & 0x38)
{
case 0x00: /* mov es,ew */
- i80286_data_descriptor(ES,src);
+ i80286_data_descriptor(cpustate,ES,src);
break;
case 0x18: /* mov ds,ew */
- i80286_data_descriptor(DS,src);
+ i80286_data_descriptor(cpustate,DS,src);
break;
case 0x10: /* mov ss,ew */
- i80286_data_descriptor(SS,src);
- PREFIX(_instruction)[FETCHOP]();
+ i80286_data_descriptor(cpustate,SS,src);
+ PREFIX(_instruction)[FETCHOP](cpustate);
break;
case 0x08: /* mov cs,ew */
break; /* doesn't do a jump far */
@@ -1874,17 +1874,17 @@ static void PREFIX86(_mov_sregw)(void) /* Opcode 0x8e */
switch (ModRM & 0x38)
{
case 0x00: /* mov es,ew */
- I.sregs[ES] = src;
- I.base[ES] = SegBase(ES);
+ cpustate->sregs[ES] = src;
+ cpustate->base[ES] = SegBase(ES);
break;
case 0x18: /* mov ds,ew */
- I.sregs[DS] = src;
- I.base[DS] = SegBase(DS);
+ cpustate->sregs[DS] = src;
+ cpustate->base[DS] = SegBase(DS);
break;
case 0x10: /* mov ss,ew */
- I.sregs[SS] = src;
- I.base[SS] = SegBase(SS); /* no interrupt allowed before next instr */
- PREFIX(_instruction)[FETCHOP]();
+ cpustate->sregs[SS] = src;
+ cpustate->base[SS] = SegBase(SS); /* no interrupt allowed before next instr */
+ PREFIX(_instruction)[FETCHOP](cpustate);
break;
case 0x08: /* mov cs,ew */
break; /* doesn't do a jump far */
@@ -1892,7 +1892,7 @@ static void PREFIX86(_mov_sregw)(void) /* Opcode 0x8e */
#endif
}
-static void PREFIX86(_popw)(void) /* Opcode 0x8f */
+static void PREFIX86(_popw)(i8086_state *cpustate) /* Opcode 0x8f */
{
unsigned ModRM = FETCH;
WORD tmp;
@@ -1905,67 +1905,67 @@ static void PREFIX86(_popw)(void) /* Opcode 0x8f */
#define XchgAXReg(Reg) \
{ \
WORD tmp; \
- tmp = I.regs.w[Reg]; \
- I.regs.w[Reg] = I.regs.w[AX]; \
- I.regs.w[AX] = tmp; \
+ tmp = cpustate->regs.w[Reg]; \
+ cpustate->regs.w[Reg] = cpustate->regs.w[AX]; \
+ cpustate->regs.w[AX] = tmp; \
ICOUNT -= timing.xchg_ar16; \
}
-static void PREFIX86(_nop)(void) /* Opcode 0x90 */
+static void PREFIX86(_nop)(i8086_state *cpustate) /* Opcode 0x90 */
{
/* this is XchgAXReg(AX); */
ICOUNT -= timing.nop;
}
-static void PREFIX86(_xchg_axcx)(void) /* Opcode 0x91 */
+static void PREFIX86(_xchg_axcx)(i8086_state *cpustate) /* Opcode 0x91 */
{
XchgAXReg(CX);
}
-static void PREFIX86(_xchg_axdx)(void) /* Opcode 0x92 */
+static void PREFIX86(_xchg_axdx)(i8086_state *cpustate) /* Opcode 0x92 */
{
XchgAXReg(DX);
}
-static void PREFIX86(_xchg_axbx)(void) /* Opcode 0x93 */
+static void PREFIX86(_xchg_axbx)(i8086_state *cpustate) /* Opcode 0x93 */
{
XchgAXReg(BX);
}
-static void PREFIX86(_xchg_axsp)(void) /* Opcode 0x94 */
+static void PREFIX86(_xchg_axsp)(i8086_state *cpustate) /* Opcode 0x94 */
{
XchgAXReg(SP);
}
-static void PREFIX86(_xchg_axbp)(void) /* Opcode 0x95 */
+static void PREFIX86(_xchg_axbp)(i8086_state *cpustate) /* Opcode 0x95 */
{
XchgAXReg(BP);
}
-static void PREFIX86(_xchg_axsi)(void) /* Opcode 0x96 */
+static void PREFIX86(_xchg_axsi)(i8086_state *cpustate) /* Opcode 0x96 */
{
XchgAXReg(SI);
}
-static void PREFIX86(_xchg_axdi)(void) /* Opcode 0x97 */
+static void PREFIX86(_xchg_axdi)(i8086_state *cpustate) /* Opcode 0x97 */
{
XchgAXReg(DI);
}
-static void PREFIX86(_cbw)(void) /* Opcode 0x98 */
+static void PREFIX86(_cbw)(i8086_state *cpustate) /* Opcode 0x98 */
{
ICOUNT -= timing.cbw;
- I.regs.b[AH] = (I.regs.b[AL] & 0x80) ? 0xff : 0;
+ cpustate->regs.b[AH] = (cpustate->regs.b[AL] & 0x80) ? 0xff : 0;
}
-static void PREFIX86(_cwd)(void) /* Opcode 0x99 */
+static void PREFIX86(_cwd)(i8086_state *cpustate) /* Opcode 0x99 */
{
ICOUNT -= timing.cwd;
- I.regs.w[DX] = (I.regs.b[AH] & 0x80) ? 0xffff : 0;
+ cpustate->regs.w[DX] = (cpustate->regs.b[AH] & 0x80) ? 0xffff : 0;
}
-static void PREFIX86(_call_far)(void)
+static void PREFIX86(_call_far)(i8086_state *cpustate)
{
unsigned tmp, tmp2;
WORD ip;
@@ -1976,33 +1976,33 @@ static void PREFIX86(_call_far)(void)
tmp2 = FETCH;
tmp2 += FETCH << 8;
- ip = I.pc - I.base[CS];
- PUSH(I.sregs[CS]);
+ ip = cpustate->pc - cpustate->base[CS];
+ PUSH(cpustate->sregs[CS]);
PUSH(ip);
#ifdef I80286
- i80286_code_descriptor(tmp2, tmp);
+ i80286_code_descriptor(cpustate, tmp2, tmp);
#else
- I.sregs[CS] = (WORD)tmp2;
- I.base[CS] = SegBase(CS);
- I.pc = (I.base[CS] + (WORD)tmp) & AMASK;
+ cpustate->sregs[CS] = (WORD)tmp2;
+ cpustate->base[CS] = SegBase(CS);
+ cpustate->pc = (cpustate->base[CS] + (WORD)tmp) & AMASK;
#endif
ICOUNT -= timing.call_far;
- CHANGE_PC(I.pc);
+ CHANGE_PC(cpustate->pc);
}
-static void PREFIX86(_wait)(void) /* Opcode 0x9b */
+static void PREFIX86(_wait)(i8086_state *cpustate) /* Opcode 0x9b */
{
- if (I.test_state)
+ if (cpustate->test_state)
{
ICOUNT = 0;
- I.pc--;
+ cpustate->pc--;
}
else
ICOUNT -= timing.wait;
}
-static void PREFIX86(_pushf)(void) /* Opcode 0x9c */
+static void PREFIX86(_pushf)(i8086_state *cpustate) /* Opcode 0x9c */
{
unsigned tmp;
ICOUNT -= timing.pushf;
@@ -2015,35 +2015,35 @@ static void PREFIX86(_pushf)(void) /* Opcode 0x9c */
#endif
}
-static void PREFIX86(_popf)(void) /* Opcode 0x9d */
+static void PREFIX86(_popf)(i8086_state *cpustate) /* Opcode 0x9d */
{
unsigned tmp;
POP(tmp);
ICOUNT -= timing.popf;
ExpandFlags(tmp);
- if (I.TF) PREFIX(_trap)();
+ if (cpustate->TF) PREFIX(_trap)(cpustate);
/* if the IF is set, and an interrupt is pending, signal an interrupt */
- if (I.IF && I.irq_state)
- PREFIX(_interrupt)(-1);
+ if (cpustate->IF && cpustate->irq_state)
+ PREFIX(_interrupt)(cpustate, -1);
}
-static void PREFIX86(_sahf)(void) /* Opcode 0x9e */
+static void PREFIX86(_sahf)(i8086_state *cpustate) /* Opcode 0x9e */
{
- unsigned tmp = (CompressFlags() & 0xff00) | (I.regs.b[AH] & 0xd5);
+ unsigned tmp = (CompressFlags() & 0xff00) | (cpustate->regs.b[AH] & 0xd5);
ICOUNT -= timing.sahf;
ExpandFlags(tmp);
}
-static void PREFIX86(_lahf)(void) /* Opcode 0x9f */
+static void PREFIX86(_lahf)(i8086_state *cpustate) /* Opcode 0x9f */
{
- I.regs.b[AH] = CompressFlags() & 0xff;
+ cpustate->regs.b[AH] = CompressFlags() & 0xff;
ICOUNT -= timing.lahf;
}
-static void PREFIX86(_mov_aldisp)(void) /* Opcode 0xa0 */
+static void PREFIX86(_mov_aldisp)(i8086_state *cpustate) /* Opcode 0xa0 */
{
unsigned addr;
@@ -2051,10 +2051,10 @@ static void PREFIX86(_mov_aldisp)(void) /* Opcode 0xa0 */
addr += FETCH << 8;
ICOUNT -= timing.mov_am8;
- I.regs.b[AL] = GetMemB(DS, addr);
+ cpustate->regs.b[AL] = GetMemB(DS, addr);
}
-static void PREFIX86(_mov_axdisp)(void) /* Opcode 0xa1 */
+static void PREFIX86(_mov_axdisp)(i8086_state *cpustate) /* Opcode 0xa1 */
{
unsigned addr;
@@ -2062,10 +2062,10 @@ static void PREFIX86(_mov_axdisp)(void) /* Opcode 0xa1 */
addr += FETCH << 8;
ICOUNT -= timing.mov_am16;
- I.regs.w[AX] = GetMemW(DS, addr);
+ cpustate->regs.w[AX] = GetMemW(DS, addr);
}
-static void PREFIX86(_mov_dispal)(void) /* Opcode 0xa2 */
+static void PREFIX86(_mov_dispal)(i8086_state *cpustate) /* Opcode 0xa2 */
{
unsigned addr;
@@ -2073,10 +2073,10 @@ static void PREFIX86(_mov_dispal)(void) /* Opcode 0xa2 */
addr += FETCH << 8;
ICOUNT -= timing.mov_ma8;
- PutMemB(DS, addr, I.regs.b[AL]);
+ PutMemB(DS, addr, cpustate->regs.b[AL]);
}
-static void PREFIX86(_mov_dispax)(void) /* Opcode 0xa3 */
+static void PREFIX86(_mov_dispax)(i8086_state *cpustate) /* Opcode 0xa3 */
{
unsigned addr;
@@ -2084,275 +2084,275 @@ static void PREFIX86(_mov_dispax)(void) /* Opcode 0xa3 */
addr += FETCH << 8;
ICOUNT -= timing.mov_ma16;
- PutMemW(DS, addr, I.regs.w[AX]);
+ PutMemW(DS, addr, cpustate->regs.w[AX]);
}
-static void PREFIX86(_movsb)(void) /* Opcode 0xa4 */
+static void PREFIX86(_movsb)(i8086_state *cpustate) /* Opcode 0xa4 */
{
- BYTE tmp = GetMemB(DS,I.regs.w[SI]);
- PutMemB(ES,I.regs.w[DI], tmp);
- I.regs.w[DI] += I.DirVal;
- I.regs.w[SI] += I.DirVal;
+ BYTE tmp = GetMemB(DS,cpustate->regs.w[SI]);
+ PutMemB(ES,cpustate->regs.w[DI], tmp);
+ cpustate->regs.w[DI] += cpustate->DirVal;
+ cpustate->regs.w[SI] += cpustate->DirVal;
ICOUNT -= timing.movs8;
}
-static void PREFIX86(_movsw)(void) /* Opcode 0xa5 */
+static void PREFIX86(_movsw)(i8086_state *cpustate) /* Opcode 0xa5 */
{
- WORD tmp = GetMemW(DS,I.regs.w[SI]);
- PutMemW(ES,I.regs.w[DI], tmp);
- I.regs.w[DI] += 2 * I.DirVal;
- I.regs.w[SI] += 2 * I.DirVal;
+ WORD tmp = GetMemW(DS,cpustate->regs.w[SI]);
+ PutMemW(ES,cpustate->regs.w[DI], tmp);
+ cpustate->regs.w[DI] += 2 * cpustate->DirVal;
+ cpustate->regs.w[SI] += 2 * cpustate->DirVal;
ICOUNT -= timing.movs16;
}
-static void PREFIX86(_cmpsb)(void) /* Opcode 0xa6 */
+static void PREFIX86(_cmpsb)(i8086_state *cpustate) /* Opcode 0xa6 */
{
- unsigned dst = GetMemB(ES, I.regs.w[DI]);
- unsigned src = GetMemB(DS, I.regs.w[SI]);
+ unsigned dst = GetMemB(ES, cpustate->regs.w[DI]);
+ unsigned src = GetMemB(DS, cpustate->regs.w[SI]);
SUBB(src,dst); /* opposite of the usual convention */
- I.regs.w[DI] += I.DirVal;
- I.regs.w[SI] += I.DirVal;
+ cpustate->regs.w[DI] += cpustate->DirVal;
+ cpustate->regs.w[SI] += cpustate->DirVal;
ICOUNT -= timing.cmps8;
}
-static void PREFIX86(_cmpsw)(void) /* Opcode 0xa7 */
+static void PREFIX86(_cmpsw)(i8086_state *cpustate) /* Opcode 0xa7 */
{
- unsigned dst = GetMemW(ES, I.regs.w[DI]);
- unsigned src = GetMemW(DS, I.regs.w[SI]);
+ unsigned dst = GetMemW(ES, cpustate->regs.w[DI]);
+ unsigned src = GetMemW(DS, cpustate->regs.w[SI]);
SUBW(src,dst); /* opposite of the usual convention */
- I.regs.w[DI] += 2 * I.DirVal;
- I.regs.w[SI] += 2 * I.DirVal;
+ cpustate->regs.w[DI] += 2 * cpustate->DirVal;
+ cpustate->regs.w[SI] += 2 * cpustate->DirVal;
ICOUNT -= timing.cmps16;
}
-static void PREFIX86(_test_ald8)(void) /* Opcode 0xa8 */
+static void PREFIX86(_test_ald8)(i8086_state *cpustate) /* Opcode 0xa8 */
{
DEF_ald8(dst,src);
ICOUNT -= timing.alu_ri8;
ANDB(dst,src);
}
-static void PREFIX86(_test_axd16)(void) /* Opcode 0xa9 */
+static void PREFIX86(_test_axd16)(i8086_state *cpustate) /* Opcode 0xa9 */
{
DEF_axd16(dst,src);
ICOUNT -= timing.alu_ri16;
ANDW(dst,src);
}
-static void PREFIX86(_stosb)(void) /* Opcode 0xaa */
+static void PREFIX86(_stosb)(i8086_state *cpustate) /* Opcode 0xaa */
{
- PutMemB(ES,I.regs.w[DI],I.regs.b[AL]);
- I.regs.w[DI] += I.DirVal;
+ PutMemB(ES,cpustate->regs.w[DI],cpustate->regs.b[AL]);
+ cpustate->regs.w[DI] += cpustate->DirVal;
ICOUNT -= timing.stos8;
}
-static void PREFIX86(_stosw)(void) /* Opcode 0xab */
+static void PREFIX86(_stosw)(i8086_state *cpustate) /* Opcode 0xab */
{
- PutMemW(ES,I.regs.w[DI],I.regs.w[AX]);
- I.regs.w[DI] += 2 * I.DirVal;
+ PutMemW(ES,cpustate->regs.w[DI],cpustate->regs.w[AX]);
+ cpustate->regs.w[DI] += 2 * cpustate->DirVal;
ICOUNT -= timing.stos16;
}
-static void PREFIX86(_lodsb)(void) /* Opcode 0xac */
+static void PREFIX86(_lodsb)(i8086_state *cpustate) /* Opcode 0xac */
{
- I.regs.b[AL] = GetMemB(DS,I.regs.w[SI]);
- I.regs.w[SI] += I.DirVal;
+ cpustate->regs.b[AL] = GetMemB(DS,cpustate->regs.w[SI]);
+ cpustate->regs.w[SI] += cpustate->DirVal;
ICOUNT -= timing.lods8;
}
-static void PREFIX86(_lodsw)(void) /* Opcode 0xad */
+static void PREFIX86(_lodsw)(i8086_state *cpustate) /* Opcode 0xad */
{
- I.regs.w[AX] = GetMemW(DS,I.regs.w[SI]);
- I.regs.w[SI] += 2 * I.DirVal;
+ cpustate->regs.w[AX] = GetMemW(DS,cpustate->regs.w[SI]);
+ cpustate->regs.w[SI] += 2 * cpustate->DirVal;
ICOUNT -= timing.lods16;
}
-static void PREFIX86(_scasb)(void) /* Opcode 0xae */
+static void PREFIX86(_scasb)(i8086_state *cpustate) /* Opcode 0xae */
{
- unsigned src = GetMemB(ES, I.regs.w[DI]);
- unsigned dst = I.regs.b[AL];
+ unsigned src = GetMemB(ES, cpustate->regs.w[DI]);
+ unsigned dst = cpustate->regs.b[AL];
SUBB(dst,src);
- I.regs.w[DI] += I.DirVal;
+ cpustate->regs.w[DI] += cpustate->DirVal;
ICOUNT -= timing.scas8;
}
-static void PREFIX86(_scasw)(void) /* Opcode 0xaf */
+static void PREFIX86(_scasw)(i8086_state *cpustate) /* Opcode 0xaf */
{
- unsigned src = GetMemW(ES, I.regs.w[DI]);
- unsigned dst = I.regs.w[AX];
+ unsigned src = GetMemW(ES, cpustate->regs.w[DI]);
+ unsigned dst = cpustate->regs.w[AX];
SUBW(dst,src);
- I.regs.w[DI] += 2 * I.DirVal;
+ cpustate->regs.w[DI] += 2 * cpustate->DirVal;
ICOUNT -= timing.scas16;
}
-static void PREFIX86(_mov_ald8)(void) /* Opcode 0xb0 */
+static void PREFIX86(_mov_ald8)(i8086_state *cpustate) /* Opcode 0xb0 */
{
- I.regs.b[AL] = FETCH;
+ cpustate->regs.b[AL] = FETCH;
ICOUNT -= timing.mov_ri8;
}
-static void PREFIX86(_mov_cld8)(void) /* Opcode 0xb1 */
+static void PREFIX86(_mov_cld8)(i8086_state *cpustate) /* Opcode 0xb1 */
{
- I.regs.b[CL] = FETCH;
+ cpustate->regs.b[CL] = FETCH;
ICOUNT -= timing.mov_ri8;
}
-static void PREFIX86(_mov_dld8)(void) /* Opcode 0xb2 */
+static void PREFIX86(_mov_dld8)(i8086_state *cpustate) /* Opcode 0xb2 */
{
- I.regs.b[DL] = FETCH;
+ cpustate->regs.b[DL] = FETCH;
ICOUNT -= timing.mov_ri8;
}
-static void PREFIX86(_mov_bld8)(void) /* Opcode 0xb3 */
+static void PREFIX86(_mov_bld8)(i8086_state *cpustate) /* Opcode 0xb3 */
{
- I.regs.b[BL] = FETCH;
+ cpustate->regs.b[BL] = FETCH;
ICOUNT -= timing.mov_ri8;
}
-static void PREFIX86(_mov_ahd8)(void) /* Opcode 0xb4 */
+static void PREFIX86(_mov_ahd8)(i8086_state *cpustate) /* Opcode 0xb4 */
{
- I.regs.b[AH] = FETCH;
+ cpustate->regs.b[AH] = FETCH;
ICOUNT -= timing.mov_ri8;
}
-static void PREFIX86(_mov_chd8)(void) /* Opcode 0xb5 */
+static void PREFIX86(_mov_chd8)(i8086_state *cpustate) /* Opcode 0xb5 */
{
- I.regs.b[CH] = FETCH;
+ cpustate->regs.b[CH] = FETCH;
ICOUNT -= timing.mov_ri8;
}
-static void PREFIX86(_mov_dhd8)(void) /* Opcode 0xb6 */
+static void PREFIX86(_mov_dhd8)(i8086_state *cpustate) /* Opcode 0xb6 */
{
- I.regs.b[DH] = FETCH;
+ cpustate->regs.b[DH] = FETCH;
ICOUNT -= timing.mov_ri8;
}
-static void PREFIX86(_mov_bhd8)(void) /* Opcode 0xb7 */
+static void PREFIX86(_mov_bhd8)(i8086_state *cpustate) /* Opcode 0xb7 */
{
- I.regs.b[BH] = FETCH;
+ cpustate->regs.b[BH] = FETCH;
ICOUNT -= timing.mov_ri8;
}
-static void PREFIX86(_mov_axd16)(void) /* Opcode 0xb8 */
+static void PREFIX86(_mov_axd16)(i8086_state *cpustate) /* Opcode 0xb8 */
{
- I.regs.b[AL] = FETCH;
- I.regs.b[AH] = FETCH;
+ cpustate->regs.b[AL] = FETCH;
+ cpustate->regs.b[AH] = FETCH;
ICOUNT -= timing.mov_ri16;
}
-static void PREFIX86(_mov_cxd16)(void) /* Opcode 0xb9 */
+static void PREFIX86(_mov_cxd16)(i8086_state *cpustate) /* Opcode 0xb9 */
{
- I.regs.b[CL] = FETCH;
- I.regs.b[CH] = FETCH;
+ cpustate->regs.b[CL] = FETCH;
+ cpustate->regs.b[CH] = FETCH;
ICOUNT -= timing.mov_ri16;
}
-static void PREFIX86(_mov_dxd16)(void) /* Opcode 0xba */
+static void PREFIX86(_mov_dxd16)(i8086_state *cpustate) /* Opcode 0xba */
{
- I.regs.b[DL] = FETCH;
- I.regs.b[DH] = FETCH;
+ cpustate->regs.b[DL] = FETCH;
+ cpustate->regs.b[DH] = FETCH;
ICOUNT -= timing.mov_ri16;
}
-static void PREFIX86(_mov_bxd16)(void) /* Opcode 0xbb */
+static void PREFIX86(_mov_bxd16)(i8086_state *cpustate) /* Opcode 0xbb */
{
- I.regs.b[BL] = FETCH;
- I.regs.b[BH] = FETCH;
+ cpustate->regs.b[BL] = FETCH;
+ cpustate->regs.b[BH] = FETCH;
ICOUNT -= timing.mov_ri16;
}
-static void PREFIX86(_mov_spd16)(void) /* Opcode 0xbc */
+static void PREFIX86(_mov_spd16)(i8086_state *cpustate) /* Opcode 0xbc */
{
- I.regs.b[SPL] = FETCH;
- I.regs.b[SPH] = FETCH;
+ cpustate->regs.b[SPL] = FETCH;
+ cpustate->regs.b[SPH] = FETCH;
ICOUNT -= timing.mov_ri16;
}
-static void PREFIX86(_mov_bpd16)(void) /* Opcode 0xbd */
+static void PREFIX86(_mov_bpd16)(i8086_state *cpustate) /* Opcode 0xbd */
{
- I.regs.b[BPL] = FETCH;
- I.regs.b[BPH] = FETCH;
+ cpustate->regs.b[BPL] = FETCH;
+ cpustate->regs.b[BPH] = FETCH;
ICOUNT -= timing.mov_ri16;
}
-static void PREFIX86(_mov_sid16)(void) /* Opcode 0xbe */
+static void PREFIX86(_mov_sid16)(i8086_state *cpustate) /* Opcode 0xbe */
{
- I.regs.b[SIL] = FETCH;
- I.regs.b[SIH] = FETCH;
+ cpustate->regs.b[SIL] = FETCH;
+ cpustate->regs.b[SIH] = FETCH;
ICOUNT -= timing.mov_ri16;
}
-static void PREFIX86(_mov_did16)(void) /* Opcode 0xbf */
+static void PREFIX86(_mov_did16)(i8086_state *cpustate) /* Opcode 0xbf */
{
- I.regs.b[DIL] = FETCH;
- I.regs.b[DIH] = FETCH;
+ cpustate->regs.b[DIL] = FETCH;
+ cpustate->regs.b[DIH] = FETCH;
ICOUNT -= timing.mov_ri16;
}
-static void PREFIX86(_ret_d16)(void) /* Opcode 0xc2 */
+static void PREFIX86(_ret_d16)(i8086_state *cpustate) /* Opcode 0xc2 */
{
unsigned count = FETCH;
count += FETCH << 8;
- POP(I.pc);
- I.pc = (I.pc + I.base[CS]) & AMASK;
- I.regs.w[SP]+=count;
+ POP(cpustate->pc);
+ cpustate->pc = (cpustate->pc + cpustate->base[CS]) & AMASK;
+ cpustate->regs.w[SP]+=count;
ICOUNT -= timing.ret_near_imm;
- CHANGE_PC(I.pc);
+ CHANGE_PC(cpustate->pc);
}
-static void PREFIX86(_ret)(void) /* Opcode 0xc3 */
+static void PREFIX86(_ret)(i8086_state *cpustate) /* Opcode 0xc3 */
{
- POP(I.pc);
- I.pc = (I.pc + I.base[CS]) & AMASK;
+ POP(cpustate->pc);
+ cpustate->pc = (cpustate->pc + cpustate->base[CS]) & AMASK;
ICOUNT -= timing.ret_near;
- CHANGE_PC(I.pc);
+ CHANGE_PC(cpustate->pc);
}
-static void PREFIX86(_les_dw)(void) /* Opcode 0xc4 */
+static void PREFIX86(_les_dw)(i8086_state *cpustate) /* Opcode 0xc4 */
{
unsigned ModRM = FETCH;
WORD tmp = GetRMWord(ModRM);
RegWord(ModRM)= tmp;
#ifdef I80286
- i80286_data_descriptor(ES,GetnextRMWord);
+ i80286_data_descriptor(cpustate,ES,GetnextRMWord);
#else
- I.sregs[ES] = GetnextRMWord;
- I.base[ES] = SegBase(ES);
+ cpustate->sregs[ES] = GetnextRMWord;
+ cpustate->base[ES] = SegBase(ES);
#endif
ICOUNT -= timing.load_ptr;
}
-static void PREFIX86(_lds_dw)(void) /* Opcode 0xc5 */
+static void PREFIX86(_lds_dw)(i8086_state *cpustate) /* Opcode 0xc5 */
{
unsigned ModRM = FETCH;
WORD tmp = GetRMWord(ModRM);
RegWord(ModRM)=tmp;
#ifdef I80286
- i80286_data_descriptor(DS,GetnextRMWord);
+ i80286_data_descriptor(cpustate,DS,GetnextRMWord);
#else
- I.sregs[DS] = GetnextRMWord;
- I.base[DS] = SegBase(DS);
+ cpustate->sregs[DS] = GetnextRMWord;
+ cpustate->base[DS] = SegBase(DS);
#endif
ICOUNT -= timing.load_ptr;
}
-static void PREFIX86(_mov_bd8)(void) /* Opcode 0xc6 */
+static void PREFIX86(_mov_bd8)(i8086_state *cpustate) /* Opcode 0xc6 */
{
unsigned ModRM = FETCH;
ICOUNT -= (ModRM >= 0xc0) ? timing.mov_ri8 : timing.mov_mi8;
PutImmRMByte(ModRM);
}
-static void PREFIX86(_mov_wd16)(void) /* Opcode 0xc7 */
+static void PREFIX86(_mov_wd16)(i8086_state *cpustate) /* Opcode 0xc7 */
{
unsigned ModRM = FETCH;
ICOUNT -= (ModRM >= 0xc0) ? timing.mov_ri16 : timing.mov_mi16;
PutImmRMWord(ModRM);
}
-static void PREFIX86(_retf_d16)(void) /* Opcode 0xca */
+static void PREFIX86(_retf_d16)(i8086_state *cpustate) /* Opcode 0xca */
{
unsigned count = FETCH;
count += FETCH << 8;
@@ -2362,60 +2362,60 @@ static void PREFIX86(_retf_d16)(void) /* Opcode 0xca */
int tmp, tmp2;
POP(tmp2);
POP(tmp);
- i80286_code_descriptor(tmp, tmp2);
+ i80286_code_descriptor(cpustate, tmp, tmp2);
}
#else
- POP(I.pc);
- POP(I.sregs[CS]);
- I.base[CS] = SegBase(CS);
- I.pc = (I.pc + I.base[CS]) & AMASK;
+ POP(cpustate->pc);
+ POP(cpustate->sregs[CS]);
+ cpustate->base[CS] = SegBase(CS);
+ cpustate->pc = (cpustate->pc + cpustate->base[CS]) & AMASK;
#endif
- I.regs.w[SP]+=count;
+ cpustate->regs.w[SP]+=count;
ICOUNT -= timing.ret_far_imm;
- CHANGE_PC(I.pc);
+ CHANGE_PC(cpustate->pc);
}
-static void PREFIX86(_retf)(void) /* Opcode 0xcb */
+static void PREFIX86(_retf)(i8086_state *cpustate) /* Opcode 0xcb */
{
#ifdef I80286
{
int tmp, tmp2;
POP(tmp2);
POP(tmp);
- i80286_code_descriptor(tmp, tmp2);
+ i80286_code_descriptor(cpustate, tmp, tmp2);
}
#else
- POP(I.pc);
- POP(I.sregs[CS]);
- I.base[CS] = SegBase(CS);
- I.pc = (I.pc + I.base[CS]) & AMASK;
+ POP(cpustate->pc);
+ POP(cpustate->sregs[CS]);
+ cpustate->base[CS] = SegBase(CS);
+ cpustate->pc = (cpustate->pc + cpustate->base[CS]) & AMASK;
#endif
ICOUNT -= timing.ret_far;
- CHANGE_PC(I.pc);
+ CHANGE_PC(cpustate->pc);
}
-static void PREFIX86(_int3)(void) /* Opcode 0xcc */
+static void PREFIX86(_int3)(i8086_state *cpustate) /* Opcode 0xcc */
{
ICOUNT -= timing.int3;
- PREFIX(_interrupt)(3);
+ PREFIX(_interrupt)(cpustate, 3);
}
-static void PREFIX86(_int)(void) /* Opcode 0xcd */
+static void PREFIX86(_int)(i8086_state *cpustate) /* Opcode 0xcd */
{
unsigned int_num = FETCH;
ICOUNT -= timing.int_imm;
- PREFIX(_interrupt)(int_num);
+ PREFIX(_interrupt)(cpustate, int_num);
}
-static void PREFIX86(_into)(void) /* Opcode 0xce */
+static void PREFIX86(_into)(i8086_state *cpustate) /* Opcode 0xce */
{
if (OF) {
ICOUNT -= timing.into_t;
- PREFIX(_interrupt)(4);
+ PREFIX(_interrupt)(cpustate, 4);
} else ICOUNT -= timing.into_nt;
}
-static void PREFIX86(_iret)(void) /* Opcode 0xcf */
+static void PREFIX86(_iret)(i8086_state *cpustate) /* Opcode 0xcf */
{
ICOUNT -= timing.iret;
#ifdef I80286
@@ -2423,208 +2423,208 @@ static void PREFIX86(_iret)(void) /* Opcode 0xcf */
int tmp, tmp2;
POP(tmp2);
POP(tmp);
- i80286_code_descriptor(tmp, tmp2);
+ i80286_code_descriptor(cpustate, tmp, tmp2);
}
#else
- POP(I.pc);
- POP(I.sregs[CS]);
- I.base[CS] = SegBase(CS);
- I.pc = (I.pc + I.base[CS]) & AMASK;
+ POP(cpustate->pc);
+ POP(cpustate->sregs[CS]);
+ cpustate->base[CS] = SegBase(CS);
+ cpustate->pc = (cpustate->pc + cpustate->base[CS]) & AMASK;
#endif
- PREFIX(_popf)();
- CHANGE_PC(I.pc);
+ PREFIX(_popf)(cpustate);
+ CHANGE_PC(cpustate->pc);
/* if the IF is set, and an interrupt is pending, signal an interrupt */
- if (I.IF && I.irq_state)
- PREFIX(_interrupt)(-1);
+ if (cpustate->IF && cpustate->irq_state)
+ PREFIX(_interrupt)(cpustate, -1);
}
-static void PREFIX86(_rotshft_b)(void) /* Opcode 0xd0 */
+static void PREFIX86(_rotshft_b)(i8086_state *cpustate) /* Opcode 0xd0 */
{
- PREFIX(_rotate_shift_Byte)(FETCHOP,1);
+ PREFIX(_rotate_shift_Byte)(cpustate,FETCHOP,1);
}
-static void PREFIX86(_rotshft_w)(void) /* Opcode 0xd1 */
+static void PREFIX86(_rotshft_w)(i8086_state *cpustate) /* Opcode 0xd1 */
{
- PREFIX(_rotate_shift_Word)(FETCHOP,1);
+ PREFIX(_rotate_shift_Word)(cpustate,FETCHOP,1);
}
-static void PREFIX86(_rotshft_bcl)(void) /* Opcode 0xd2 */
+static void PREFIX86(_rotshft_bcl)(i8086_state *cpustate) /* Opcode 0xd2 */
{
- PREFIX(_rotate_shift_Byte)(FETCHOP,I.regs.b[CL]);
+ PREFIX(_rotate_shift_Byte)(cpustate,FETCHOP,cpustate->regs.b[CL]);
}
-static void PREFIX86(_rotshft_wcl)(void) /* Opcode 0xd3 */
+static void PREFIX86(_rotshft_wcl)(i8086_state *cpustate) /* Opcode 0xd3 */
{
- PREFIX(_rotate_shift_Word)(FETCHOP,I.regs.b[CL]);
+ PREFIX(_rotate_shift_Word)(cpustate,FETCHOP,cpustate->regs.b[CL]);
}
/* OB: Opcode works on NEC V-Series but not the Variants */
/* one could specify any byte value as operand but the NECs */
/* always substitute 0x0a. */
-static void PREFIX86(_aam)(void) /* Opcode 0xd4 */
+static void PREFIX86(_aam)(i8086_state *cpustate) /* Opcode 0xd4 */
{
unsigned mult = FETCH;
ICOUNT -= timing.aam;
if (mult == 0)
- PREFIX(_interrupt)(0);
+ PREFIX(_interrupt)(cpustate, 0);
else
{
- I.regs.b[AH] = I.regs.b[AL] / mult;
- I.regs.b[AL] %= mult;
+ cpustate->regs.b[AH] = cpustate->regs.b[AL] / mult;
+ cpustate->regs.b[AL] %= mult;
- SetSZPF_Word(I.regs.w[AX]);
+ SetSZPF_Word(cpustate->regs.w[AX]);
}
}
-static void PREFIX86(_aad)(void) /* Opcode 0xd5 */
+static void PREFIX86(_aad)(i8086_state *cpustate) /* Opcode 0xd5 */
{
unsigned mult = FETCH;
ICOUNT -= timing.aad;
- I.regs.b[AL] = I.regs.b[AH] * mult + I.regs.b[AL];
- I.regs.b[AH] = 0;
+ cpustate->regs.b[AL] = cpustate->regs.b[AH] * mult + cpustate->regs.b[AL];
+ cpustate->regs.b[AH] = 0;
- SetZF(I.regs.b[AL]);
- SetPF(I.regs.b[AL]);
- I.SignVal = 0;
+ SetZF(cpustate->regs.b[AL]);
+ SetPF(cpustate->regs.b[AL]);
+ cpustate->SignVal = 0;
}
-static void PREFIX86(_xlat)(void) /* Opcode 0xd7 */
+static void PREFIX86(_xlat)(i8086_state *cpustate) /* Opcode 0xd7 */
{
- unsigned dest = I.regs.w[BX]+I.regs.b[AL];
+ unsigned dest = cpustate->regs.w[BX]+cpustate->regs.b[AL];
ICOUNT -= timing.xlat;
- I.regs.b[AL] = GetMemB(DS, dest);
+ cpustate->regs.b[AL] = GetMemB(DS, dest);
}
-static void PREFIX86(_escape)(void) /* Opcodes 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde and 0xdf */
+static void PREFIX86(_escape)(i8086_state *cpustate) /* Opcodes 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde and 0xdf */
{
unsigned ModRM = FETCH;
ICOUNT -= timing.nop;
GetRMByte(ModRM);
}
-static void PREFIX86(_loopne)(void) /* Opcode 0xe0 */
+static void PREFIX86(_loopne)(i8086_state *cpustate) /* Opcode 0xe0 */
{
int disp = (int)((INT8)FETCH);
- unsigned tmp = I.regs.w[CX]-1;
+ unsigned tmp = cpustate->regs.w[CX]-1;
- I.regs.w[CX]=tmp;
+ cpustate->regs.w[CX]=tmp;
if (!ZF && tmp) {
ICOUNT -= timing.loop_t;
- I.pc += disp;
+ cpustate->pc += disp;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.loop_nt;
}
-static void PREFIX86(_loope)(void) /* Opcode 0xe1 */
+static void PREFIX86(_loope)(i8086_state *cpustate) /* Opcode 0xe1 */
{
int disp = (int)((INT8)FETCH);
- unsigned tmp = I.regs.w[CX]-1;
+ unsigned tmp = cpustate->regs.w[CX]-1;
- I.regs.w[CX]=tmp;
+ cpustate->regs.w[CX]=tmp;
if (ZF && tmp) {
ICOUNT -= timing.loope_t;
- I.pc += disp;
+ cpustate->pc += disp;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.loope_nt;
}
-static void PREFIX86(_loop)(void) /* Opcode 0xe2 */
+static void PREFIX86(_loop)(i8086_state *cpustate) /* Opcode 0xe2 */
{
int disp = (int)((INT8)FETCH);
- unsigned tmp = I.regs.w[CX]-1;
+ unsigned tmp = cpustate->regs.w[CX]-1;
- I.regs.w[CX]=tmp;
+ cpustate->regs.w[CX]=tmp;
if (tmp) {
ICOUNT -= timing.loop_t;
- I.pc += disp;
+ cpustate->pc += disp;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else ICOUNT -= timing.loop_nt;
}
-static void PREFIX86(_jcxz)(void) /* Opcode 0xe3 */
+static void PREFIX86(_jcxz)(i8086_state *cpustate) /* Opcode 0xe3 */
{
int disp = (int)((INT8)FETCH);
- if (I.regs.w[CX] == 0) {
+ if (cpustate->regs.w[CX] == 0) {
ICOUNT -= timing.jcxz_t;
- I.pc += disp;
+ cpustate->pc += disp;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
} else
ICOUNT -= timing.jcxz_nt;
}
-static void PREFIX86(_inal)(void) /* Opcode 0xe4 */
+static void PREFIX86(_inal)(i8086_state *cpustate) /* Opcode 0xe4 */
{
unsigned port = FETCH;
ICOUNT -= timing.in_imm8;
- I.regs.b[AL] = read_port_byte(port);
+ cpustate->regs.b[AL] = read_port_byte(port);
}
-static void PREFIX86(_inax)(void) /* Opcode 0xe5 */
+static void PREFIX86(_inax)(i8086_state *cpustate) /* Opcode 0xe5 */
{
unsigned port = FETCH;
ICOUNT -= timing.in_imm16;
- I.regs.w[AX] = read_port_word(port);
+ cpustate->regs.w[AX] = read_port_word(port);
}
-static void PREFIX86(_outal)(void) /* Opcode 0xe6 */
+static void PREFIX86(_outal)(i8086_state *cpustate) /* Opcode 0xe6 */
{
unsigned port = FETCH;
ICOUNT -= timing.out_imm8;
- write_port_byte(port, I.regs.b[AL]);
+ write_port_byte(port, cpustate->regs.b[AL]);
}
-static void PREFIX86(_outax)(void) /* Opcode 0xe7 */
+static void PREFIX86(_outax)(i8086_state *cpustate) /* Opcode 0xe7 */
{
unsigned port = FETCH;
ICOUNT -= timing.out_imm16;
- write_port_word(port, I.regs.w[AX]);
+ write_port_word(port, cpustate->regs.w[AX]);
}
-static void PREFIX86(_call_d16)(void) /* Opcode 0xe8 */
+static void PREFIX86(_call_d16)(i8086_state *cpustate) /* Opcode 0xe8 */
{
WORD ip, tmp;
FETCHWORD(tmp);
- ip = I.pc - I.base[CS];
+ ip = cpustate->pc - cpustate->base[CS];
PUSH(ip);
ip += tmp;
- I.pc = (ip + I.base[CS]) & AMASK;
+ cpustate->pc = (ip + cpustate->base[CS]) & AMASK;
ICOUNT -= timing.call_near;
- CHANGE_PC(I.pc);
+ CHANGE_PC(cpustate->pc);
}
-static void PREFIX86(_jmp_d16)(void) /* Opcode 0xe9 */
+static void PREFIX86(_jmp_d16)(i8086_state *cpustate) /* Opcode 0xe9 */
{
WORD ip, tmp;
FETCHWORD(tmp);
- ip = I.pc - I.base[CS] + tmp;
- I.pc = (ip + I.base[CS]) & AMASK;
+ ip = cpustate->pc - cpustate->base[CS] + tmp;
+ cpustate->pc = (ip + cpustate->base[CS]) & AMASK;
ICOUNT -= timing.jmp_near;
- CHANGE_PC(I.pc);
+ CHANGE_PC(cpustate->pc);
}
-static void PREFIX86(_jmp_far)(void) /* Opcode 0xea */
+static void PREFIX86(_jmp_far)(i8086_state *cpustate) /* Opcode 0xea */
{
unsigned tmp,tmp1;
@@ -2635,85 +2635,85 @@ static void PREFIX86(_jmp_far)(void) /* Opcode 0xea */
tmp1 += FETCH << 8;
#ifdef I80286
- i80286_code_descriptor(tmp1,tmp);
+ i80286_code_descriptor(cpustate, tmp1,tmp);
#else
- I.sregs[CS] = (WORD)tmp1;
- I.base[CS] = SegBase(CS);
- I.pc = (I.base[CS] + tmp) & AMASK;
+ cpustate->sregs[CS] = (WORD)tmp1;
+ cpustate->base[CS] = SegBase(CS);
+ cpustate->pc = (cpustate->base[CS] + tmp) & AMASK;
#endif
ICOUNT -= timing.jmp_far;
- CHANGE_PC(I.pc);
+ CHANGE_PC(cpustate->pc);
}
-static void PREFIX86(_jmp_d8)(void) /* Opcode 0xeb */
+static void PREFIX86(_jmp_d8)(i8086_state *cpustate) /* Opcode 0xeb */
{
int tmp = (int)((INT8)FETCH);
- I.pc += tmp;
+ cpustate->pc += tmp;
/* ASG - can probably assume this is safe
- CHANGE_PC(I.pc);*/
+ CHANGE_PC(cpustate->pc);*/
ICOUNT -= timing.jmp_short;
}
-static void PREFIX86(_inaldx)(void) /* Opcode 0xec */
+static void PREFIX86(_inaldx)(i8086_state *cpustate) /* Opcode 0xec */
{
ICOUNT -= timing.in_dx8;
- I.regs.b[AL] = read_port_byte(I.regs.w[DX]);
+ cpustate->regs.b[AL] = read_port_byte(cpustate->regs.w[DX]);
}
-static void PREFIX86(_inaxdx)(void) /* Opcode 0xed */
+static void PREFIX86(_inaxdx)(i8086_state *cpustate) /* Opcode 0xed */
{
- unsigned port = I.regs.w[DX];
+ unsigned port = cpustate->regs.w[DX];
ICOUNT -= timing.in_dx16;
- I.regs.w[AX] = read_port_word(port);
+ cpustate->regs.w[AX] = read_port_word(port);
}
-static void PREFIX86(_outdxal)(void) /* Opcode 0xee */
+static void PREFIX86(_outdxal)(i8086_state *cpustate) /* Opcode 0xee */
{
ICOUNT -= timing.out_dx8;
- write_port_byte(I.regs.w[DX], I.regs.b[AL]);
+ write_port_byte(cpustate->regs.w[DX], cpustate->regs.b[AL]);
}
-static void PREFIX86(_outdxax)(void) /* Opcode 0xef */
+static void PREFIX86(_outdxax)(i8086_state *cpustate) /* Opcode 0xef */
{
- unsigned port = I.regs.w[DX];
+ unsigned port = cpustate->regs.w[DX];
ICOUNT -= timing.out_dx16;
- write_port_word(port, I.regs.w[AX]);
+ write_port_word(port, cpustate->regs.w[AX]);
}
/* I think thats not a V20 instruction...*/
-static void PREFIX86(_lock)(void) /* Opcode 0xf0 */
+static void PREFIX86(_lock)(i8086_state *cpustate) /* Opcode 0xf0 */
{
ICOUNT -= timing.nop;
- PREFIX(_instruction)[FETCHOP](); /* un-interruptible */
+ PREFIX(_instruction)[FETCHOP](cpustate); /* un-interruptible */
}
#endif
-static void PREFIX(_repne)(void) /* Opcode 0xf2 */
+static void PREFIX(_repne)(i8086_state *cpustate) /* Opcode 0xf2 */
{
- PREFIX(rep)(0);
+ PREFIX(rep)(cpustate, 0);
}
-static void PREFIX(_repe)(void) /* Opcode 0xf3 */
+static void PREFIX(_repe)(i8086_state *cpustate) /* Opcode 0xf3 */
{
- PREFIX(rep)(1);
+ PREFIX(rep)(cpustate, 1);
}
#ifndef I80186
-static void PREFIX86(_hlt)(void) /* Opcode 0xf4 */
+static void PREFIX86(_hlt)(i8086_state *cpustate) /* Opcode 0xf4 */
{
- I.pc--;
+ cpustate->pc--;
ICOUNT = 0;
}
-static void PREFIX86(_cmc)(void) /* Opcode 0xf5 */
+static void PREFIX86(_cmc)(i8086_state *cpustate) /* Opcode 0xf5 */
{
ICOUNT -= timing.flag_ops;
- I.CarryVal = !CF;
+ cpustate->CarryVal = !CF;
}
-static void PREFIX86(_f6pre)(void)
+static void PREFIX86(_f6pre)(i8086_state *cpustate)
{
/* Opcode 0xf6 */
unsigned ModRM = FETCH;
@@ -2728,7 +2728,7 @@ static void PREFIX86(_f6pre)(void)
ICOUNT -= (ModRM >= 0xc0) ? timing.alu_ri8 : timing.alu_mi8_ro;
tmp &= FETCH;
- I.CarryVal = I.OverVal = I.AuxVal = 0;
+ cpustate->CarryVal = cpustate->OverVal = cpustate->AuxVal = 0;
SetSZPF_Byte(tmp);
break;
@@ -2747,16 +2747,16 @@ static void PREFIX86(_f6pre)(void)
ICOUNT -= (ModRM >= 0xc0) ? timing.mul_r8 : timing.mul_m8;
{
UINT16 result;
- tmp2 = I.regs.b[AL];
+ tmp2 = cpustate->regs.b[AL];
SetSF((INT8)tmp2);
SetPF(tmp2);
result = (UINT16)tmp2*tmp;
- I.regs.w[AX]=(WORD)result;
+ cpustate->regs.w[AX]=(WORD)result;
- SetZF(I.regs.w[AX]);
- I.CarryVal = I.OverVal = (I.regs.b[AH] != 0);
+ SetZF(cpustate->regs.w[AX]);
+ cpustate->CarryVal = cpustate->OverVal = (cpustate->regs.b[AH] != 0);
}
break;
case 0x28: /* IMUL AL, Eb */
@@ -2764,17 +2764,17 @@ static void PREFIX86(_f6pre)(void)
{
INT16 result;
- tmp2 = (unsigned)I.regs.b[AL];
+ tmp2 = (unsigned)cpustate->regs.b[AL];
SetSF((INT8)tmp2);
SetPF(tmp2);
result = (INT16)((INT8)tmp2)*(INT16)((INT8)tmp);
- I.regs.w[AX]=(WORD)result;
+ cpustate->regs.w[AX]=(WORD)result;
- SetZF(I.regs.w[AX]);
+ SetZF(cpustate->regs.w[AX]);
- I.CarryVal = I.OverVal = (result >> 7 != 0) && (result >> 7 != -1);
+ cpustate->CarryVal = cpustate->OverVal = (result >> 7 != 0) && (result >> 7 != -1);
}
break;
case 0x30: /* DIV AL, Ew */
@@ -2782,24 +2782,24 @@ static void PREFIX86(_f6pre)(void)
{
UINT16 result;
- result = I.regs.w[AX];
+ result = cpustate->regs.w[AX];
if (tmp)
{
if ((result / tmp) > 0xff)
{
- PREFIX(_interrupt)(0);
+ PREFIX(_interrupt)(cpustate, 0);
break;
}
else
{
- I.regs.b[AH] = result % tmp;
- I.regs.b[AL] = result / tmp;
+ cpustate->regs.b[AH] = result % tmp;
+ cpustate->regs.b[AL] = result / tmp;
}
}
else
{
- PREFIX(_interrupt)(0);
+ PREFIX(_interrupt)(cpustate, 0);
break;
}
}
@@ -2810,7 +2810,7 @@ static void PREFIX86(_f6pre)(void)
INT16 result;
- result = I.regs.w[AX];
+ result = cpustate->regs.w[AX];
if (tmp)
{
@@ -2818,18 +2818,18 @@ static void PREFIX86(_f6pre)(void)
if ((result /= (INT16)((INT8)tmp)) > 0xff)
{
- PREFIX(_interrupt)(0);
+ PREFIX(_interrupt)(cpustate, 0);
break;
}
else
{
- I.regs.b[AL] = result;
- I.regs.b[AH] = tmp2;
+ cpustate->regs.b[AL] = result;
+ cpustate->regs.b[AH] = tmp2;
}
}
else
{
- PREFIX(_interrupt)(0);
+ PREFIX(_interrupt)(cpustate, 0);
break;
}
}
@@ -2838,7 +2838,7 @@ static void PREFIX86(_f6pre)(void)
}
-static void PREFIX86(_f7pre)(void)
+static void PREFIX86(_f7pre)(i8086_state *cpustate)
{
/* Opcode 0xf7 */
unsigned ModRM = FETCH;
@@ -2856,7 +2856,7 @@ static void PREFIX86(_f7pre)(void)
tmp &= tmp2;
- I.CarryVal = I.OverVal = I.AuxVal = 0;
+ cpustate->CarryVal = cpustate->OverVal = cpustate->AuxVal = 0;
SetSZPF_Word(tmp);
break;
@@ -2876,18 +2876,18 @@ static void PREFIX86(_f7pre)(void)
ICOUNT -= (ModRM >= 0xc0) ? timing.mul_r16 : timing.mul_m16;
{
UINT32 result;
- tmp2 = I.regs.w[AX];
+ tmp2 = cpustate->regs.w[AX];
SetSF((INT16)tmp2);
SetPF(tmp2);
result = (UINT32)tmp2*tmp;
- I.regs.w[AX]=(WORD)result;
+ cpustate->regs.w[AX]=(WORD)result;
result >>= 16;
- I.regs.w[DX]=result;
+ cpustate->regs.w[DX]=result;
- SetZF(I.regs.w[AX] | I.regs.w[DX]);
- I.CarryVal = I.OverVal = (I.regs.w[DX] != 0);
+ SetZF(cpustate->regs.w[AX] | cpustate->regs.w[DX]);
+ cpustate->CarryVal = cpustate->OverVal = (cpustate->regs.w[DX] != 0);
}
break;
@@ -2896,19 +2896,19 @@ static void PREFIX86(_f7pre)(void)
{
INT32 result;
- tmp2 = I.regs.w[AX];
+ tmp2 = cpustate->regs.w[AX];
SetSF((INT16)tmp2);
SetPF(tmp2);
result = (INT32)((INT16)tmp2)*(INT32)((INT16)tmp);
- I.CarryVal = I.OverVal = (result >> 15 != 0) && (result >> 15 != -1);
+ cpustate->CarryVal = cpustate->OverVal = (result >> 15 != 0) && (result >> 15 != -1);
- I.regs.w[AX]=(WORD)result;
+ cpustate->regs.w[AX]=(WORD)result;
result = (WORD)(result >> 16);
- I.regs.w[DX]=result;
+ cpustate->regs.w[DX]=result;
- SetZF(I.regs.w[AX] | I.regs.w[DX]);
+ SetZF(cpustate->regs.w[AX] | cpustate->regs.w[DX]);
}
break;
case 0x30: /* DIV AX, Ew */
@@ -2916,26 +2916,26 @@ static void PREFIX86(_f7pre)(void)
{
UINT32 result;
- result = (I.regs.w[DX] << 16) + I.regs.w[AX];
+ result = (cpustate->regs.w[DX] << 16) + cpustate->regs.w[AX];
if (tmp)
{
tmp2 = result % tmp;
if ((result / tmp) > 0xffff)
{
- PREFIX(_interrupt)(0);
+ PREFIX(_interrupt)(cpustate, 0);
break;
}
else
{
- I.regs.w[DX]=tmp2;
+ cpustate->regs.w[DX]=tmp2;
result /= tmp;
- I.regs.w[AX]=result;
+ cpustate->regs.w[AX]=result;
}
}
else
{
- PREFIX(_interrupt)(0);
+ PREFIX(_interrupt)(cpustate, 0);
break;
}
}
@@ -2945,25 +2945,25 @@ static void PREFIX86(_f7pre)(void)
{
INT32 result;
- result = (I.regs.w[DX] << 16) + I.regs.w[AX];
+ result = (cpustate->regs.w[DX] << 16) + cpustate->regs.w[AX];
if (tmp)
{
tmp2 = result % (INT32)((INT16)tmp);
if ((result /= (INT32)((INT16)tmp)) > 0xffff)
{
- PREFIX(_interrupt)(0);
+ PREFIX(_interrupt)(cpustate, 0);
break;
}
else
{
- I.regs.w[AX]=result;
- I.regs.w[DX]=tmp2;
+ cpustate->regs.w[AX]=result;
+ cpustate->regs.w[DX]=tmp2;
}
}
else
{
- PREFIX(_interrupt)(0);
+ PREFIX(_interrupt)(cpustate, 0);
break;
}
}
@@ -2972,48 +2972,48 @@ static void PREFIX86(_f7pre)(void)
}
-static void PREFIX86(_clc)(void) /* Opcode 0xf8 */
+static void PREFIX86(_clc)(i8086_state *cpustate) /* Opcode 0xf8 */
{
ICOUNT -= timing.flag_ops;
- I.CarryVal = 0;
+ cpustate->CarryVal = 0;
}
-static void PREFIX86(_stc)(void) /* Opcode 0xf9 */
+static void PREFIX86(_stc)(i8086_state *cpustate) /* Opcode 0xf9 */
{
ICOUNT -= timing.flag_ops;
- I.CarryVal = 1;
+ cpustate->CarryVal = 1;
}
-static void PREFIX86(_cli)(void) /* Opcode 0xfa */
+static void PREFIX86(_cli)(i8086_state *cpustate) /* Opcode 0xfa */
{
ICOUNT -= timing.flag_ops;
SetIF(0);
}
-static void PREFIX86(_sti)(void) /* Opcode 0xfb */
+static void PREFIX86(_sti)(i8086_state *cpustate) /* Opcode 0xfb */
{
ICOUNT -= timing.flag_ops;
SetIF(1);
- PREFIX(_instruction)[FETCHOP](); /* no interrupt before next instruction */
+ PREFIX(_instruction)[FETCHOP](cpustate); /* no interrupt before next instruction */
/* if an interrupt is pending, signal an interrupt */
- if (I.irq_state)
- PREFIX(_interrupt)(-1);
+ if (cpustate->irq_state)
+ PREFIX(_interrupt)(cpustate, -1);
}
-static void PREFIX86(_cld)(void) /* Opcode 0xfc */
+static void PREFIX86(_cld)(i8086_state *cpustate) /* Opcode 0xfc */
{
ICOUNT -= timing.flag_ops;
SetDF(0);
}
-static void PREFIX86(_std)(void) /* Opcode 0xfd */
+static void PREFIX86(_std)(i8086_state *cpustate) /* Opcode 0xfd */
{
ICOUNT -= timing.flag_ops;
SetDF(1);
}
-static void PREFIX86(_fepre)(void) /* Opcode 0xfe */
+static void PREFIX86(_fepre)(i8086_state *cpustate) /* Opcode 0xfe */
{
unsigned ModRM = FETCH;
unsigned tmp = GetRMByte(ModRM);
@@ -3038,7 +3038,7 @@ static void PREFIX86(_fepre)(void) /* Opcode 0xfe */
}
-static void PREFIX86(_ffpre)(void) /* Opcode 0xff */
+static void PREFIX86(_ffpre)(i8086_state *cpustate) /* Opcode 0xff */
{
unsigned ModRM = FETCHOP;
unsigned tmp;
@@ -3074,34 +3074,34 @@ static void PREFIX86(_ffpre)(void) /* Opcode 0xff */
case 0x10: /* CALL ew */
ICOUNT -= (ModRM >= 0xc0) ? timing.call_r16 : timing.call_m16;
tmp = GetRMWord(ModRM);
- ip = I.pc - I.base[CS];
+ ip = cpustate->pc - cpustate->base[CS];
PUSH(ip);
- I.pc = (I.base[CS] + (WORD)tmp) & AMASK;
- CHANGE_PC(I.pc);
+ cpustate->pc = (cpustate->base[CS] + (WORD)tmp) & AMASK;
+ CHANGE_PC(cpustate->pc);
break;
case 0x18: /* CALL FAR ea */
ICOUNT -= timing.call_m32;
- tmp = I.sregs[CS]; /* HJB 12/13/98 need to skip displacements of EA */
+ tmp = cpustate->sregs[CS]; /* HJB 12/13/98 need to skip displacements of cpustate->ea */
tmp1 = GetRMWord(ModRM);
- ip = I.pc - I.base[CS];
+ ip = cpustate->pc - cpustate->base[CS];
PUSH(tmp);
PUSH(ip);
#ifdef I80286
- i80286_code_descriptor(GetnextRMWord, tmp1);
+ i80286_code_descriptor(cpustate, GetnextRMWord, tmp1);
#else
- I.sregs[CS] = GetnextRMWord;
- I.base[CS] = SegBase(CS);
- I.pc = (I.base[CS] + tmp1) & AMASK;
+ cpustate->sregs[CS] = GetnextRMWord;
+ cpustate->base[CS] = SegBase(CS);
+ cpustate->pc = (cpustate->base[CS] + tmp1) & AMASK;
#endif
- CHANGE_PC(I.pc);
+ CHANGE_PC(cpustate->pc);
break;
case 0x20: /* JMP ea */
ICOUNT -= (ModRM >= 0xc0) ? timing.jmp_r16 : timing.jmp_m16;
ip = GetRMWord(ModRM);
- I.pc = (I.base[CS] + ip) & AMASK;
- CHANGE_PC(I.pc);
+ cpustate->pc = (cpustate->base[CS] + ip) & AMASK;
+ CHANGE_PC(cpustate->pc);
break;
case 0x28: /* JMP FAR ea */
@@ -3109,14 +3109,14 @@ static void PREFIX86(_ffpre)(void) /* Opcode 0xff */
#ifdef I80286
tmp = GetRMWord(ModRM);
- i80286_code_descriptor(GetnextRMWord, tmp);
+ i80286_code_descriptor(cpustate, GetnextRMWord, tmp);
#else
- I.pc = GetRMWord(ModRM);
- I.sregs[CS] = GetnextRMWord;
- I.base[CS] = SegBase(CS);
- I.pc = (I.pc + I.base[CS]) & AMASK;
+ cpustate->pc = GetRMWord(ModRM);
+ cpustate->sregs[CS] = GetnextRMWord;
+ cpustate->base[CS] = SegBase(CS);
+ cpustate->pc = (cpustate->pc + cpustate->base[CS]) & AMASK;
#endif
- CHANGE_PC(I.pc);
+ CHANGE_PC(cpustate->pc);
break;
case 0x30: /* PUSH ea */
@@ -3128,15 +3128,15 @@ static void PREFIX86(_ffpre)(void) /* Opcode 0xff */
}
-static void PREFIX86(_invalid)(void)
+static void PREFIX86(_invalid)(i8086_state *cpustate)
{
#ifdef I80286
- i80286_trap2(ILLEGAL_INSTRUCTION);
+ i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
#else
/* makes the cpu loops forever until user resets it */
/*{ debugger_break(Machine); } */
- logerror("illegal instruction %.2x at %.5x\n",PEEKBYTE(I.pc), I.pc);
- I.pc--;
+ logerror("illegal instruction %.2x at %.5x\n",PEEKBYTE(cpustate->pc), cpustate->pc);
+ cpustate->pc--;
ICOUNT -= 10;
#endif
}
diff --git a/src/emu/cpu/i86/instr86.h b/src/emu/cpu/i86/instr86.h
index 08583948678..fafc18d412f 100644
--- a/src/emu/cpu/i86/instr86.h
+++ b/src/emu/cpu/i86/instr86.h
@@ -13,232 +13,232 @@
// function renaming will be added when neccessary
// timing value should move to separate array
-static void PREFIX86(_add_br8)(void);
-static void PREFIX86(_add_wr16)(void);
-static void PREFIX86(_add_r8b)(void);
-static void PREFIX86(_add_r16w)(void);
-static void PREFIX86(_add_ald8)(void);
-static void PREFIX86(_add_axd16)(void);
-static void PREFIX86(_push_es)(void);
-static void PREFIX86(_pop_es)(void);
-static void PREFIX86(_or_br8)(void);
-static void PREFIX86(_or_r8b)(void);
-static void PREFIX86(_or_wr16)(void);
-static void PREFIX86(_or_r16w)(void);
-static void PREFIX86(_or_ald8)(void);
-static void PREFIX86(_or_axd16)(void);
-static void PREFIX86(_push_cs)(void);
-static void PREFIX86(_adc_br8)(void);
-static void PREFIX86(_adc_wr16)(void);
-static void PREFIX86(_adc_r8b)(void);
-static void PREFIX86(_adc_r16w)(void);
-static void PREFIX86(_adc_ald8)(void);
-static void PREFIX86(_adc_axd16)(void);
-static void PREFIX86(_push_ss)(void);
-static void PREFIX86(_pop_ss)(void);
-static void PREFIX86(_sbb_br8)(void);
-static void PREFIX86(_sbb_wr16)(void);
-static void PREFIX86(_sbb_r8b)(void);
-static void PREFIX86(_sbb_r16w)(void);
-static void PREFIX86(_sbb_ald8)(void);
-static void PREFIX86(_sbb_axd16)(void);
-static void PREFIX86(_push_ds)(void);
-static void PREFIX86(_pop_ds)(void);
-static void PREFIX86(_and_br8)(void);
-static void PREFIX86(_and_r8b)(void);
-static void PREFIX86(_and_wr16)(void);
-static void PREFIX86(_and_r16w)(void);
-static void PREFIX86(_and_ald8)(void);
-static void PREFIX86(_and_axd16)(void);
-static void PREFIX86(_es)(void);
-static void PREFIX86(_daa)(void);
-static void PREFIX86(_sub_br8)(void);
-static void PREFIX86(_sub_wr16)(void);
-static void PREFIX86(_sub_r8b)(void);
-static void PREFIX86(_sub_r16w)(void);
-static void PREFIX86(_sub_ald8)(void);
-static void PREFIX86(_sub_axd16)(void);
-static void PREFIX86(_cs)(void);
-static void PREFIX86(_das)(void);
-static void PREFIX86(_xor_br8)(void);
-static void PREFIX86(_xor_r8b)(void);
-static void PREFIX86(_xor_wr16)(void);
-static void PREFIX86(_xor_r16w)(void);
-static void PREFIX86(_xor_ald8)(void);
-static void PREFIX86(_xor_axd16)(void);
-static void PREFIX86(_ss)(void);
-static void PREFIX86(_aaa)(void);
-static void PREFIX86(_cmp_br8)(void);
-static void PREFIX86(_cmp_wr16)(void);
-static void PREFIX86(_cmp_r8b)(void);
-static void PREFIX86(_cmp_r16w)(void);
-static void PREFIX86(_cmp_ald8)(void);
-static void PREFIX86(_cmp_axd16)(void);
-static void PREFIX86(_ds)(void);
-static void PREFIX86(_aas)(void);
-static void PREFIX86(_inc_ax)(void);
-static void PREFIX86(_inc_cx)(void);
-static void PREFIX86(_inc_dx)(void);
-static void PREFIX86(_inc_bx)(void);
-static void PREFIX86(_inc_sp)(void);
-static void PREFIX86(_inc_bp)(void);
-static void PREFIX86(_inc_si)(void);
-static void PREFIX86(_inc_di)(void);
-static void PREFIX86(_dec_ax)(void);
-static void PREFIX86(_dec_cx)(void);
-static void PREFIX86(_dec_dx)(void);
-static void PREFIX86(_dec_bx)(void);
-static void PREFIX86(_dec_sp)(void);
-static void PREFIX86(_dec_bp)(void);
-static void PREFIX86(_dec_si)(void);
-static void PREFIX86(_dec_di)(void);
-static void PREFIX86(_push_ax)(void);
-static void PREFIX86(_push_cx)(void);
-static void PREFIX86(_push_dx)(void);
-static void PREFIX86(_push_bx)(void);
-static void PREFIX86(_push_sp)(void);
-static void PREFIX86(_push_bp)(void);
-static void PREFIX86(_push_si)(void);
-static void PREFIX86(_push_di)(void);
-static void PREFIX86(_pop_ax)(void);
-static void PREFIX86(_pop_cx)(void);
-static void PREFIX86(_pop_dx)(void);
-static void PREFIX86(_pop_bx)(void);
-static void PREFIX86(_pop_sp)(void);
-static void PREFIX86(_pop_bp)(void);
-static void PREFIX86(_pop_si)(void);
-static void PREFIX86(_pop_di)(void);
-static void PREFIX86(_jo)(void);
-static void PREFIX86(_jno)(void);
-static void PREFIX86(_jb)(void);
-static void PREFIX86(_jnb)(void);
-static void PREFIX86(_jz)(void);
-static void PREFIX86(_jnz)(void);
-static void PREFIX86(_jbe)(void);
-static void PREFIX86(_jnbe)(void);
-static void PREFIX86(_js)(void);
-static void PREFIX86(_jns)(void);
-static void PREFIX86(_jp)(void);
-static void PREFIX86(_jnp)(void);
-static void PREFIX86(_jl)(void);
-static void PREFIX86(_jnl)(void);
-static void PREFIX86(_jle)(void);
-static void PREFIX86(_jnle)(void);
-static void PREFIX86(_80pre)(void);
-static void PREFIX86(_82pre)(void);
-static void PREFIX86(_81pre)(void);
-static void PREFIX86(_83pre)(void);
-static void PREFIX86(_test_br8)(void);
-static void PREFIX86(_test_wr16)(void);
-static void PREFIX86(_xchg_br8)(void);
-static void PREFIX86(_xchg_wr16)(void);
-static void PREFIX86(_mov_br8)(void);
-static void PREFIX86(_mov_r8b)(void);
-static void PREFIX86(_mov_wr16)(void);
-static void PREFIX86(_mov_r16w)(void);
-static void PREFIX86(_mov_wsreg)(void);
-static void PREFIX86(_lea)(void);
-static void PREFIX86(_mov_sregw)(void);
-static void PREFIX86(_invalid)(void);
-static void PREFIX86(_popw)(void);
-static void PREFIX86(_nop)(void);
-static void PREFIX86(_xchg_axcx)(void);
-static void PREFIX86(_xchg_axdx)(void);
-static void PREFIX86(_xchg_axbx)(void);
-static void PREFIX86(_xchg_axsp)(void);
-static void PREFIX86(_xchg_axbp)(void);
-static void PREFIX86(_xchg_axsi)(void);
-static void PREFIX86(_xchg_axdi)(void);
-static void PREFIX86(_cbw)(void);
-static void PREFIX86(_cwd)(void);
-static void PREFIX86(_call_far)(void);
-static void PREFIX86(_pushf)(void);
-static void PREFIX86(_popf)(void);
-static void PREFIX86(_sahf)(void);
-static void PREFIX86(_lahf)(void);
-static void PREFIX86(_mov_aldisp)(void);
-static void PREFIX86(_mov_axdisp)(void);
-static void PREFIX86(_mov_dispal)(void);
-static void PREFIX86(_mov_dispax)(void);
-static void PREFIX86(_movsb)(void);
-static void PREFIX86(_movsw)(void);
-static void PREFIX86(_cmpsb)(void);
-static void PREFIX86(_cmpsw)(void);
-static void PREFIX86(_test_ald8)(void);
-static void PREFIX86(_test_axd16)(void);
-static void PREFIX86(_stosb)(void);
-static void PREFIX86(_stosw)(void);
-static void PREFIX86(_lodsb)(void);
-static void PREFIX86(_lodsw)(void);
-static void PREFIX86(_scasb)(void);
-static void PREFIX86(_scasw)(void);
-static void PREFIX86(_mov_ald8)(void);
-static void PREFIX86(_mov_cld8)(void);
-static void PREFIX86(_mov_dld8)(void);
-static void PREFIX86(_mov_bld8)(void);
-static void PREFIX86(_mov_ahd8)(void);
-static void PREFIX86(_mov_chd8)(void);
-static void PREFIX86(_mov_dhd8)(void);
-static void PREFIX86(_mov_bhd8)(void);
-static void PREFIX86(_mov_axd16)(void);
-static void PREFIX86(_mov_cxd16)(void);
-static void PREFIX86(_mov_dxd16)(void);
-static void PREFIX86(_mov_bxd16)(void);
-static void PREFIX86(_mov_spd16)(void);
-static void PREFIX86(_mov_bpd16)(void);
-static void PREFIX86(_mov_sid16)(void);
-static void PREFIX86(_mov_did16)(void);
-static void PREFIX86(_ret_d16)(void);
-static void PREFIX86(_ret)(void);
-static void PREFIX86(_les_dw)(void);
-static void PREFIX86(_lds_dw)(void);
-static void PREFIX86(_mov_bd8)(void);
-static void PREFIX86(_mov_wd16)(void);
-static void PREFIX86(_retf_d16)(void);
-static void PREFIX86(_retf)(void);
-static void PREFIX86(_int3)(void);
-static void PREFIX86(_int)(void);
-static void PREFIX86(_into)(void);
-static void PREFIX86(_iret)(void);
-static void PREFIX86(_rotshft_b)(void);
-static void PREFIX86(_rotshft_w)(void);
-static void PREFIX86(_rotshft_bcl)(void);
-static void PREFIX86(_rotshft_wcl)(void);
-static void PREFIX86(_aam)(void);
-static void PREFIX86(_aad)(void);
-static void PREFIX86(_xlat)(void);
-static void PREFIX86(_escape)(void);
-static void PREFIX86(_loopne)(void);
-static void PREFIX86(_loope)(void);
-static void PREFIX86(_loop)(void);
-static void PREFIX86(_jcxz)(void);
-static void PREFIX86(_inal)(void);
-static void PREFIX86(_inax)(void);
-static void PREFIX86(_outal)(void);
-static void PREFIX86(_outax)(void);
-static void PREFIX86(_call_d16)(void);
-static void PREFIX86(_jmp_d16)(void);
-static void PREFIX86(_jmp_far)(void);
-static void PREFIX86(_jmp_d8)(void);
-static void PREFIX86(_inaldx)(void);
-static void PREFIX86(_inaxdx)(void);
-static void PREFIX86(_outdxal)(void);
-static void PREFIX86(_outdxax)(void);
-static void PREFIX86(_lock)(void);
-static void PREFIX86(_repne)(void);
-static void PREFIX86(_repe)(void);
-static void PREFIX86(_hlt)(void);
-static void PREFIX86(_cmc)(void);
-static void PREFIX86(_f6pre)(void);
-static void PREFIX86(_f7pre)(void);
-static void PREFIX86(_clc)(void);
-static void PREFIX86(_stc)(void);
-static void PREFIX86(_cli)(void);
-static void PREFIX86(_sti)(void);
-static void PREFIX86(_cld)(void);
-static void PREFIX86(_std)(void);
-static void PREFIX86(_fepre)(void);
-static void PREFIX86(_ffpre)(void);
-static void PREFIX86(_wait)(void);
+static void PREFIX86(_add_br8)(i8086_state *cpustate);
+static void PREFIX86(_add_wr16)(i8086_state *cpustate);
+static void PREFIX86(_add_r8b)(i8086_state *cpustate);
+static void PREFIX86(_add_r16w)(i8086_state *cpustate);
+static void PREFIX86(_add_ald8)(i8086_state *cpustate);
+static void PREFIX86(_add_axd16)(i8086_state *cpustate);
+static void PREFIX86(_push_es)(i8086_state *cpustate);
+static void PREFIX86(_pop_es)(i8086_state *cpustate);
+static void PREFIX86(_or_br8)(i8086_state *cpustate);
+static void PREFIX86(_or_r8b)(i8086_state *cpustate);
+static void PREFIX86(_or_wr16)(i8086_state *cpustate);
+static void PREFIX86(_or_r16w)(i8086_state *cpustate);
+static void PREFIX86(_or_ald8)(i8086_state *cpustate);
+static void PREFIX86(_or_axd16)(i8086_state *cpustate);
+static void PREFIX86(_push_cs)(i8086_state *cpustate);
+static void PREFIX86(_adc_br8)(i8086_state *cpustate);
+static void PREFIX86(_adc_wr16)(i8086_state *cpustate);
+static void PREFIX86(_adc_r8b)(i8086_state *cpustate);
+static void PREFIX86(_adc_r16w)(i8086_state *cpustate);
+static void PREFIX86(_adc_ald8)(i8086_state *cpustate);
+static void PREFIX86(_adc_axd16)(i8086_state *cpustate);
+static void PREFIX86(_push_ss)(i8086_state *cpustate);
+static void PREFIX86(_pop_ss)(i8086_state *cpustate);
+static void PREFIX86(_sbb_br8)(i8086_state *cpustate);
+static void PREFIX86(_sbb_wr16)(i8086_state *cpustate);
+static void PREFIX86(_sbb_r8b)(i8086_state *cpustate);
+static void PREFIX86(_sbb_r16w)(i8086_state *cpustate);
+static void PREFIX86(_sbb_ald8)(i8086_state *cpustate);
+static void PREFIX86(_sbb_axd16)(i8086_state *cpustate);
+static void PREFIX86(_push_ds)(i8086_state *cpustate);
+static void PREFIX86(_pop_ds)(i8086_state *cpustate);
+static void PREFIX86(_and_br8)(i8086_state *cpustate);
+static void PREFIX86(_and_r8b)(i8086_state *cpustate);
+static void PREFIX86(_and_wr16)(i8086_state *cpustate);
+static void PREFIX86(_and_r16w)(i8086_state *cpustate);
+static void PREFIX86(_and_ald8)(i8086_state *cpustate);
+static void PREFIX86(_and_axd16)(i8086_state *cpustate);
+static void PREFIX86(_es)(i8086_state *cpustate);
+static void PREFIX86(_daa)(i8086_state *cpustate);
+static void PREFIX86(_sub_br8)(i8086_state *cpustate);
+static void PREFIX86(_sub_wr16)(i8086_state *cpustate);
+static void PREFIX86(_sub_r8b)(i8086_state *cpustate);
+static void PREFIX86(_sub_r16w)(i8086_state *cpustate);
+static void PREFIX86(_sub_ald8)(i8086_state *cpustate);
+static void PREFIX86(_sub_axd16)(i8086_state *cpustate);
+static void PREFIX86(_cs)(i8086_state *cpustate);
+static void PREFIX86(_das)(i8086_state *cpustate);
+static void PREFIX86(_xor_br8)(i8086_state *cpustate);
+static void PREFIX86(_xor_r8b)(i8086_state *cpustate);
+static void PREFIX86(_xor_wr16)(i8086_state *cpustate);
+static void PREFIX86(_xor_r16w)(i8086_state *cpustate);
+static void PREFIX86(_xor_ald8)(i8086_state *cpustate);
+static void PREFIX86(_xor_axd16)(i8086_state *cpustate);
+static void PREFIX86(_ss)(i8086_state *cpustate);
+static void PREFIX86(_aaa)(i8086_state *cpustate);
+static void PREFIX86(_cmp_br8)(i8086_state *cpustate);
+static void PREFIX86(_cmp_wr16)(i8086_state *cpustate);
+static void PREFIX86(_cmp_r8b)(i8086_state *cpustate);
+static void PREFIX86(_cmp_r16w)(i8086_state *cpustate);
+static void PREFIX86(_cmp_ald8)(i8086_state *cpustate);
+static void PREFIX86(_cmp_axd16)(i8086_state *cpustate);
+static void PREFIX86(_ds)(i8086_state *cpustate);
+static void PREFIX86(_aas)(i8086_state *cpustate);
+static void PREFIX86(_inc_ax)(i8086_state *cpustate);
+static void PREFIX86(_inc_cx)(i8086_state *cpustate);
+static void PREFIX86(_inc_dx)(i8086_state *cpustate);
+static void PREFIX86(_inc_bx)(i8086_state *cpustate);
+static void PREFIX86(_inc_sp)(i8086_state *cpustate);
+static void PREFIX86(_inc_bp)(i8086_state *cpustate);
+static void PREFIX86(_inc_si)(i8086_state *cpustate);
+static void PREFIX86(_inc_di)(i8086_state *cpustate);
+static void PREFIX86(_dec_ax)(i8086_state *cpustate);
+static void PREFIX86(_dec_cx)(i8086_state *cpustate);
+static void PREFIX86(_dec_dx)(i8086_state *cpustate);
+static void PREFIX86(_dec_bx)(i8086_state *cpustate);
+static void PREFIX86(_dec_sp)(i8086_state *cpustate);
+static void PREFIX86(_dec_bp)(i8086_state *cpustate);
+static void PREFIX86(_dec_si)(i8086_state *cpustate);
+static void PREFIX86(_dec_di)(i8086_state *cpustate);
+static void PREFIX86(_push_ax)(i8086_state *cpustate);
+static void PREFIX86(_push_cx)(i8086_state *cpustate);
+static void PREFIX86(_push_dx)(i8086_state *cpustate);
+static void PREFIX86(_push_bx)(i8086_state *cpustate);
+static void PREFIX86(_push_sp)(i8086_state *cpustate);
+static void PREFIX86(_push_bp)(i8086_state *cpustate);
+static void PREFIX86(_push_si)(i8086_state *cpustate);
+static void PREFIX86(_push_di)(i8086_state *cpustate);
+static void PREFIX86(_pop_ax)(i8086_state *cpustate);
+static void PREFIX86(_pop_cx)(i8086_state *cpustate);
+static void PREFIX86(_pop_dx)(i8086_state *cpustate);
+static void PREFIX86(_pop_bx)(i8086_state *cpustate);
+static void PREFIX86(_pop_sp)(i8086_state *cpustate);
+static void PREFIX86(_pop_bp)(i8086_state *cpustate);
+static void PREFIX86(_pop_si)(i8086_state *cpustate);
+static void PREFIX86(_pop_di)(i8086_state *cpustate);
+static void PREFIX86(_jo)(i8086_state *cpustate);
+static void PREFIX86(_jno)(i8086_state *cpustate);
+static void PREFIX86(_jb)(i8086_state *cpustate);
+static void PREFIX86(_jnb)(i8086_state *cpustate);
+static void PREFIX86(_jz)(i8086_state *cpustate);
+static void PREFIX86(_jnz)(i8086_state *cpustate);
+static void PREFIX86(_jbe)(i8086_state *cpustate);
+static void PREFIX86(_jnbe)(i8086_state *cpustate);
+static void PREFIX86(_js)(i8086_state *cpustate);
+static void PREFIX86(_jns)(i8086_state *cpustate);
+static void PREFIX86(_jp)(i8086_state *cpustate);
+static void PREFIX86(_jnp)(i8086_state *cpustate);
+static void PREFIX86(_jl)(i8086_state *cpustate);
+static void PREFIX86(_jnl)(i8086_state *cpustate);
+static void PREFIX86(_jle)(i8086_state *cpustate);
+static void PREFIX86(_jnle)(i8086_state *cpustate);
+static void PREFIX86(_80pre)(i8086_state *cpustate);
+static void PREFIX86(_82pre)(i8086_state *cpustate);
+static void PREFIX86(_81pre)(i8086_state *cpustate);
+static void PREFIX86(_83pre)(i8086_state *cpustate);
+static void PREFIX86(_test_br8)(i8086_state *cpustate);
+static void PREFIX86(_test_wr16)(i8086_state *cpustate);
+static void PREFIX86(_xchg_br8)(i8086_state *cpustate);
+static void PREFIX86(_xchg_wr16)(i8086_state *cpustate);
+static void PREFIX86(_mov_br8)(i8086_state *cpustate);
+static void PREFIX86(_mov_r8b)(i8086_state *cpustate);
+static void PREFIX86(_mov_wr16)(i8086_state *cpustate);
+static void PREFIX86(_mov_r16w)(i8086_state *cpustate);
+static void PREFIX86(_mov_wsreg)(i8086_state *cpustate);
+static void PREFIX86(_lea)(i8086_state *cpustate);
+static void PREFIX86(_mov_sregw)(i8086_state *cpustate);
+static void PREFIX86(_invalid)(i8086_state *cpustate);
+static void PREFIX86(_popw)(i8086_state *cpustate);
+static void PREFIX86(_nop)(i8086_state *cpustate);
+static void PREFIX86(_xchg_axcx)(i8086_state *cpustate);
+static void PREFIX86(_xchg_axdx)(i8086_state *cpustate);
+static void PREFIX86(_xchg_axbx)(i8086_state *cpustate);
+static void PREFIX86(_xchg_axsp)(i8086_state *cpustate);
+static void PREFIX86(_xchg_axbp)(i8086_state *cpustate);
+static void PREFIX86(_xchg_axsi)(i8086_state *cpustate);
+static void PREFIX86(_xchg_axdi)(i8086_state *cpustate);
+static void PREFIX86(_cbw)(i8086_state *cpustate);
+static void PREFIX86(_cwd)(i8086_state *cpustate);
+static void PREFIX86(_call_far)(i8086_state *cpustate);
+static void PREFIX86(_pushf)(i8086_state *cpustate);
+static void PREFIX86(_popf)(i8086_state *cpustate);
+static void PREFIX86(_sahf)(i8086_state *cpustate);
+static void PREFIX86(_lahf)(i8086_state *cpustate);
+static void PREFIX86(_mov_aldisp)(i8086_state *cpustate);
+static void PREFIX86(_mov_axdisp)(i8086_state *cpustate);
+static void PREFIX86(_mov_dispal)(i8086_state *cpustate);
+static void PREFIX86(_mov_dispax)(i8086_state *cpustate);
+static void PREFIX86(_movsb)(i8086_state *cpustate);
+static void PREFIX86(_movsw)(i8086_state *cpustate);
+static void PREFIX86(_cmpsb)(i8086_state *cpustate);
+static void PREFIX86(_cmpsw)(i8086_state *cpustate);
+static void PREFIX86(_test_ald8)(i8086_state *cpustate);
+static void PREFIX86(_test_axd16)(i8086_state *cpustate);
+static void PREFIX86(_stosb)(i8086_state *cpustate);
+static void PREFIX86(_stosw)(i8086_state *cpustate);
+static void PREFIX86(_lodsb)(i8086_state *cpustate);
+static void PREFIX86(_lodsw)(i8086_state *cpustate);
+static void PREFIX86(_scasb)(i8086_state *cpustate);
+static void PREFIX86(_scasw)(i8086_state *cpustate);
+static void PREFIX86(_mov_ald8)(i8086_state *cpustate);
+static void PREFIX86(_mov_cld8)(i8086_state *cpustate);
+static void PREFIX86(_mov_dld8)(i8086_state *cpustate);
+static void PREFIX86(_mov_bld8)(i8086_state *cpustate);
+static void PREFIX86(_mov_ahd8)(i8086_state *cpustate);
+static void PREFIX86(_mov_chd8)(i8086_state *cpustate);
+static void PREFIX86(_mov_dhd8)(i8086_state *cpustate);
+static void PREFIX86(_mov_bhd8)(i8086_state *cpustate);
+static void PREFIX86(_mov_axd16)(i8086_state *cpustate);
+static void PREFIX86(_mov_cxd16)(i8086_state *cpustate);
+static void PREFIX86(_mov_dxd16)(i8086_state *cpustate);
+static void PREFIX86(_mov_bxd16)(i8086_state *cpustate);
+static void PREFIX86(_mov_spd16)(i8086_state *cpustate);
+static void PREFIX86(_mov_bpd16)(i8086_state *cpustate);
+static void PREFIX86(_mov_sid16)(i8086_state *cpustate);
+static void PREFIX86(_mov_did16)(i8086_state *cpustate);
+static void PREFIX86(_ret_d16)(i8086_state *cpustate);
+static void PREFIX86(_ret)(i8086_state *cpustate);
+static void PREFIX86(_les_dw)(i8086_state *cpustate);
+static void PREFIX86(_lds_dw)(i8086_state *cpustate);
+static void PREFIX86(_mov_bd8)(i8086_state *cpustate);
+static void PREFIX86(_mov_wd16)(i8086_state *cpustate);
+static void PREFIX86(_retf_d16)(i8086_state *cpustate);
+static void PREFIX86(_retf)(i8086_state *cpustate);
+static void PREFIX86(_int3)(i8086_state *cpustate);
+static void PREFIX86(_int)(i8086_state *cpustate);
+static void PREFIX86(_into)(i8086_state *cpustate);
+static void PREFIX86(_iret)(i8086_state *cpustate);
+static void PREFIX86(_rotshft_b)(i8086_state *cpustate);
+static void PREFIX86(_rotshft_w)(i8086_state *cpustate);
+static void PREFIX86(_rotshft_bcl)(i8086_state *cpustate);
+static void PREFIX86(_rotshft_wcl)(i8086_state *cpustate);
+static void PREFIX86(_aam)(i8086_state *cpustate);
+static void PREFIX86(_aad)(i8086_state *cpustate);
+static void PREFIX86(_xlat)(i8086_state *cpustate);
+static void PREFIX86(_escape)(i8086_state *cpustate);
+static void PREFIX86(_loopne)(i8086_state *cpustate);
+static void PREFIX86(_loope)(i8086_state *cpustate);
+static void PREFIX86(_loop)(i8086_state *cpustate);
+static void PREFIX86(_jcxz)(i8086_state *cpustate);
+static void PREFIX86(_inal)(i8086_state *cpustate);
+static void PREFIX86(_inax)(i8086_state *cpustate);
+static void PREFIX86(_outal)(i8086_state *cpustate);
+static void PREFIX86(_outax)(i8086_state *cpustate);
+static void PREFIX86(_call_d16)(i8086_state *cpustate);
+static void PREFIX86(_jmp_d16)(i8086_state *cpustate);
+static void PREFIX86(_jmp_far)(i8086_state *cpustate);
+static void PREFIX86(_jmp_d8)(i8086_state *cpustate);
+static void PREFIX86(_inaldx)(i8086_state *cpustate);
+static void PREFIX86(_inaxdx)(i8086_state *cpustate);
+static void PREFIX86(_outdxal)(i8086_state *cpustate);
+static void PREFIX86(_outdxax)(i8086_state *cpustate);
+static void PREFIX86(_lock)(i8086_state *cpustate);
+static void PREFIX86(_repne)(i8086_state *cpustate);
+static void PREFIX86(_repe)(i8086_state *cpustate);
+static void PREFIX86(_hlt)(i8086_state *cpustate);
+static void PREFIX86(_cmc)(i8086_state *cpustate);
+static void PREFIX86(_f6pre)(i8086_state *cpustate);
+static void PREFIX86(_f7pre)(i8086_state *cpustate);
+static void PREFIX86(_clc)(i8086_state *cpustate);
+static void PREFIX86(_stc)(i8086_state *cpustate);
+static void PREFIX86(_cli)(i8086_state *cpustate);
+static void PREFIX86(_sti)(i8086_state *cpustate);
+static void PREFIX86(_cld)(i8086_state *cpustate);
+static void PREFIX86(_std)(i8086_state *cpustate);
+static void PREFIX86(_fepre)(i8086_state *cpustate);
+static void PREFIX86(_ffpre)(i8086_state *cpustate);
+static void PREFIX86(_wait)(i8086_state *cpustate);
#endif /* __INSTR86_H__ */
diff --git a/src/emu/cpu/i86/instrv30.c b/src/emu/cpu/i86/instrv30.c
deleted file mode 100644
index bb167d1b4b7..00000000000
--- a/src/emu/cpu/i86/instrv30.c
+++ /dev/null
@@ -1,1311 +0,0 @@
-static void PREFIXV30(_0fpre) (void) /* Opcode 0x0f */
-{
- unsigned Opcode = FETCH;
- unsigned ModRM;
- unsigned tmp;
- unsigned tmp2;
-
- switch (Opcode)
- {
- case 0x10: /* 0F 10 47 30 - TEST1 [bx+30h],cl */
- ModRM = FETCH;
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.b[Mod_RM.RM.b[ModRM]];
- nec_ICount -= 3;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadByte(EA);
- nec_ICount = old - 12; /* my source says 14 cycles everytime and not
- * ModRM-dependent like GetEA[] does..hmmm */
- }
- tmp2 = I.regs.b[CL] & 0x7;
- I.ZeroVal = tmp & bytes[tmp2] ? 1 : 0;
-/* SetZF(tmp & (1<<tmp2)); */
- break;
-
- case 0x11: /* 0F 11 47 30 - TEST1 [bx+30h],cl */
- ModRM = FETCH;
- /* tmp = GetRMWord(ModRM); */
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.w[Mod_RM.RM.w[ModRM]];
- nec_ICount -= 3;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadWord(EA);
- nec_ICount = old - 12; /* my source says 14 cycles everytime and not
- * ModRM-dependent like GetEA[] does..hmmm */
- }
- tmp2 = I.regs.b[CL] & 0xF;
- I.ZeroVal = tmp & bytes[tmp2] ? 1 : 0;
-/* SetZF(tmp & (1<<tmp2)); */
- break;
-
- case 0x12: /* 0F 12 [mod:000:r/m] - CLR1 reg/m8,cl */
- ModRM = FETCH;
- /* need the long if due to correct cycles OB[19.07.99] */
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.b[Mod_RM.RM.b[ModRM]];
- nec_ICount -= 5;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadByte(EA);
- nec_ICount = old - 14; /* my source says 14 cycles everytime and not
- * ModRM-dependent like GetEA[] does..hmmm */
- }
- tmp2 = I.regs.b[CL] & 0x7; /* hey its a Byte so &07 NOT &0f */
- tmp &= ~(bytes[tmp2]);
- PutbackRMByte(ModRM, tmp);
- break;
-
- case 0x13: /* 0F 13 [mod:000:r/m] - CLR1 reg/m16,cl */
- ModRM = FETCH;
- /* tmp = GetRMWord(ModRM); */
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.w[Mod_RM.RM.w[ModRM]];
- nec_ICount -= 5;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadWord(EA);
- nec_ICount = old - 14; /* my source says 14 cycles everytime and not
- * ModRM-dependent like GetEA[] does..hmmm */
- }
- tmp2 = I.regs.b[CL] & 0xF; /* this time its a word */
- tmp &= ~(bytes[tmp2]);
- PutbackRMWord(ModRM, tmp);
- break;
-
- case 0x14: /* 0F 14 47 30 - SET1 [bx+30h],cl */
- ModRM = FETCH;
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.b[Mod_RM.RM.b[ModRM]];
- nec_ICount -= 4;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadByte(EA);
- nec_ICount = old - 13;
- }
- tmp2 = I.regs.b[CL] & 0x7;
- tmp |= (bytes[tmp2]);
- PutbackRMByte(ModRM, tmp);
- break;
-
- case 0x15: /* 0F 15 C6 - SET1 si,cl */
- ModRM = FETCH;
- /* tmp = GetRMWord(ModRM); */
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.w[Mod_RM.RM.w[ModRM]];
- nec_ICount -= 4;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadWord(EA);
- nec_ICount = old - 13;
- }
- tmp2 = I.regs.b[CL] & 0xF;
- tmp |= (bytes[tmp2]);
- PutbackRMWord(ModRM, tmp);
- break;
-
- case 0x16: /* 0F 16 C6 - NOT1 si,cl */
- ModRM = FETCH;
- /* need the long if due to correct cycles OB[19.07.99] */
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.b[Mod_RM.RM.b[ModRM]];
- nec_ICount -= 4;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadByte(EA);
- nec_ICount = old - 18; /* my source says 18 cycles everytime and not
- * ModRM-dependent like GetEA[] does..hmmm */
- }
- tmp2 = I.regs.b[CL] & 0x7; /* hey its a Byte so &07 NOT &0f */
- if (tmp & bytes[tmp2])
- tmp &= ~(bytes[tmp2]);
- else
- tmp |= (bytes[tmp2]);
- PutbackRMByte(ModRM, tmp);
- break;
-
- case 0x17: /* 0F 17 C6 - NOT1 si,cl */
- ModRM = FETCH;
- /* tmp = GetRMWord(ModRM); */
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.w[Mod_RM.RM.w[ModRM]];
- nec_ICount -= 4;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadWord(EA);
- nec_ICount = old - 18; /* my source says 14 cycles everytime and not
- * ModRM-dependent like GetEA[] does..hmmm */
- }
- tmp2 = I.regs.b[CL] & 0xF; /* this time its a word */
- if (tmp & bytes[tmp2])
- tmp &= ~(bytes[tmp2]);
- else
- tmp |= (bytes[tmp2]);
- PutbackRMWord(ModRM, tmp);
- break;
-
- case 0x18: /* 0F 18 XX - TEST1 [bx+30h],07 */
- ModRM = FETCH;
- /* tmp = GetRMByte(ModRM); */
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.b[Mod_RM.RM.b[ModRM]];
- nec_ICount -= 4;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadByte(EA);
- nec_ICount = old - 13; /* my source says 15 cycles everytime and not
- * ModRM-dependent like GetEA[] does..hmmm */
- }
- tmp2 = FETCH;
- tmp2 &= 0xF;
- I.ZeroVal = tmp & (bytes[tmp2]) ? 1 : 0;
-/* SetZF(tmp & (1<<tmp2)); */
- break;
-
- case 0x19: /* 0F 19 XX - TEST1 [bx+30h],07 */
- ModRM = FETCH;
- /* tmp = GetRMWord(ModRM); */
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.w[Mod_RM.RM.w[ModRM]];
- nec_ICount -= 4;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadWord(EA);
- nec_ICount = old - 13; /* my source says 14 cycles everytime and not
- * ModRM-dependent like GetEA[] does..hmmm */
- }
- tmp2 = FETCH;
- tmp2 &= 0xf;
- I.ZeroVal = tmp & (bytes[tmp2]) ? 1 : 0;
-/* SetZF(tmp & (1<<tmp2)); */
- break;
-
- case 0x1a: /* 0F 1A 06 - CLR1 si,cl */
- ModRM = FETCH;
- /* tmp = GetRMByte(ModRM); */
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.b[Mod_RM.RM.b[ModRM]];
- nec_ICount -= 6;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadByte(EA);
- nec_ICount = old - 15; /* my source says 15 cycles everytime and not
- * ModRM-dependent like GetEA[] does..hmmm */
- }
- tmp2 = FETCH;
- tmp2 &= 0x7;
- tmp &= ~(bytes[tmp2]);
- PutbackRMByte(ModRM, tmp);
- break;
-
- case 0x1B: /* 0F 1B 06 - CLR1 si,cl */
- ModRM = FETCH;
- /* tmp = GetRMWord(ModRM); */
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.w[Mod_RM.RM.w[ModRM]];
- nec_ICount -= 6;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadWord(EA);
- nec_ICount = old - 15; /* my source says 15 cycles everytime and not
- * ModRM-dependent like GetEA[] does..hmmm */
- }
- tmp2 = FETCH;
- tmp2 &= 0xF;
- tmp &= ~(bytes[tmp2]);
- PutbackRMWord(ModRM, tmp);
- break;
-
- case 0x1C: /* 0F 1C 47 30 - SET1 [bx+30h],cl */
- ModRM = FETCH;
- /* tmp = GetRMByte(ModRM); */
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.b[Mod_RM.RM.b[ModRM]];
- nec_ICount -= 5;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadByte(EA);
- nec_ICount = old - 14; /* my source says 15 cycles everytime and not
- * ModRM-dependent like GetEA[] does..hmmm */
- }
- tmp2 = FETCH;
- tmp2 &= 0x7;
- tmp |= (bytes[tmp2]);
- PutbackRMByte(ModRM, tmp);
- break;
-
- case 0x1D: /* 0F 1D C6 - SET1 si,cl */
- /* logerror("PC=%06x : Set1 ",I.pc-2); */
- ModRM = FETCH;
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.w[Mod_RM.RM.w[ModRM]];
- nec_ICount -= 5;
- /* logerror("reg=%04x ->",tmp); */
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) (); /* calculate EA */
- tmp = ReadWord(EA); /* read from EA */
- nec_ICount = old - 14;
- /* logerror("[%04x]=%04x ->",EA,tmp); */
- }
- tmp2 = FETCH;
- tmp2 &= 0xF;
- tmp |= (bytes[tmp2]);
- /* logerror("%04x",tmp); */
- PutbackRMWord(ModRM, tmp);
- break;
-
- case 0x1e: /* 0F 1e C6 - NOT1 si,07 */
- ModRM = FETCH;
- /* tmp = GetRMByte(ModRM); */
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.b[Mod_RM.RM.b[ModRM]];
- nec_ICount -= 5;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadByte(EA);
- nec_ICount = old - 19;
- }
- tmp2 = FETCH;
- tmp2 &= 0x7;
- if (tmp & bytes[tmp2])
- tmp &= ~(bytes[tmp2]);
- else
- tmp |= (bytes[tmp2]);
- PutbackRMByte(ModRM, tmp);
- break;
-
- case 0x1f: /* 0F 1f C6 - NOT1 si,07 */
- ModRM = FETCH;
- //tmp = GetRMWord(ModRM);
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.w[Mod_RM.RM.w[ModRM]];
- nec_ICount -= 5;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadWord(EA);
- nec_ICount = old - 19; /* my source says 15 cycles everytime and not
- * ModRM-dependent like GetEA[] does..hmmm */
- }
- tmp2 = FETCH;
- tmp2 &= 0xF;
- if (tmp & bytes[tmp2])
- tmp &= ~(bytes[tmp2]);
- else
- tmp |= (bytes[tmp2]);
- PutbackRMWord(ModRM, tmp);
- break;
-
- case 0x20: /* 0F 20 59 - add4s */
- {
- /* length in words ! */
- int count = (I.regs.b[CL] + 1) / 2;
- int i;
- unsigned di = I.regs.w[DI];
- unsigned si = I.regs.w[SI];
-
- I.ZeroVal = 1;
- I.CarryVal = 0; /* NOT ADC */
- for (i = 0; i < count; i++)
- {
- int v1, v2;
- int result;
-
- tmp = GetMemB(DS, si);
- tmp2 = GetMemB(ES, di);
-
- v1 = (tmp >> 4) * 10 + (tmp & 0xf);
- v2 = (tmp2 >> 4) * 10 + (tmp2 & 0xf);
- result = v1 + v2 + I.CarryVal;
- I.CarryVal = result > 99 ? 1 : 0;
- result = result % 100;
- v1 = ((result / 10) << 4) | (result % 10);
- PutMemB(ES, di, v1);
- if (v1)
- I.ZeroVal = 0;
- si++;
- di++;
- }
- I.OverVal = I.CarryVal;
- nec_ICount -= 7 + 19 * count; /* 7+19n, n #operand words */
- }
- break;
-
- case 0x22: /* 0F 22 59 - sub4s */
- {
- int count = (I.regs.b[CL] + 1) / 2;
- int i;
- unsigned di = I.regs.w[DI];
- unsigned si = I.regs.w[SI];
-
- I.ZeroVal = 1;
- I.CarryVal = 0; /* NOT ADC */
- for (i = 0; i < count; i++)
- {
- int v1, v2;
- int result;
-
- tmp = GetMemB(ES, di);
- tmp2 = GetMemB(DS, si);
-
- v1 = (tmp >> 4) * 10 + (tmp & 0xf);
- v2 = (tmp2 >> 4) * 10 + (tmp2 & 0xf);
- if (v1 < (v2 + I.CarryVal))
- {
- v1 += 100;
- result = v1 - (v2 + I.CarryVal);
- I.CarryVal = 1;
- }
- else
- {
- result = v1 - (v2 + I.CarryVal);
- I.CarryVal = 0;
- }
- v1 = ((result / 10) << 4) | (result % 10);
- PutMemB(ES, di, v1);
- if (v1)
- I.ZeroVal = 0;
- si++;
- di++;
- }
- I.OverVal = I.CarryVal;
- nec_ICount -= 7 + 19 * count;
- }
- break;
-
- case 0x25:
- /*
- * ----------O-MOVSPA---------------------------------
- * OPCODE MOVSPA - Move Stack Pointer After Bank Switched
- *
- * CPU: NEC V25,V35,V25 Plus,V35 Plus,V25 Software Guard
- * Type of Instruction: System
- *
- * Instruction: MOVSPA
- *
- * Description: This instruction transfer both SS and SP of the old register
- * bank to new register bank after the bank has been switched by
- * interrupt or BRKCS instruction.
- *
- * Flags Affected: None
- *
- * CPU mode: RM
- *
- * +++++++++++++++++++++++
- * Physical Form: MOVSPA
- * COP (Code of Operation) : 0Fh 25h
- *
- * Clocks: 16
- */
- logerror("PC=%06x : MOVSPA\n", I.pc - 2);
- nec_ICount -= 16;
- break;
- case 0x26: /* 0F 22 59 - cmp4s */
- {
- int count = (I.regs.b[CL] + 1) / 2;
- int i;
- unsigned di = I.regs.w[DI];
- unsigned si = I.regs.w[SI];
-
- I.ZeroVal = 1;
- I.CarryVal = 0; /* NOT ADC */
- for (i = 0; i < count; i++)
- {
- int v1, v2;
- int result;
-
- tmp = GetMemB(ES, di);
- tmp2 = GetMemB(DS, si);
-
- v1 = (tmp >> 4) * 10 + (tmp & 0xf);
- v2 = (tmp2 >> 4) * 10 + (tmp2 & 0xf);
- if (v1 < (v2 + I.CarryVal))
- {
- v1 += 100;
- result = v1 - (v2 + I.CarryVal);
- I.CarryVal = 1;
- }
- else
- {
- result = v1 - (v2 + I.CarryVal);
- I.CarryVal = 0;
- }
- v1 = ((result / 10) << 4) | (result % 10);
-/* PutMemB(ES, di,v1); */ /* no store, only compare */
- if (v1)
- I.ZeroVal = 0;
- si++;
- di++;
- }
- I.OverVal = I.CarryVal;
- nec_ICount -= 7 + 19 * (I.regs.b[CL] + 1); // 7+19n, n #operand bytes
- }
- break;
- case 0x28: /* 0F 28 C7 - ROL4 bh */
- ModRM = FETCH;
- /* tmp = GetRMByte(ModRM); */
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.b[Mod_RM.RM.b[ModRM]];
- nec_ICount -= 25;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadByte(EA);
- nec_ICount = old - 28;
- }
- tmp <<= 4;
- tmp |= I.regs.b[AL] & 0xF;
- I.regs.b[AL] = (I.regs.b[AL] & 0xF0) | ((tmp >> 8) & 0xF);
- tmp &= 0xff;
- PutbackRMByte(ModRM, tmp);
- break;
-
- /* Is this a REAL instruction?? */
- case 0x29: /* 0F 29 C7 - ROL4 bx */
-
- ModRM = FETCH;
- /*
- * if (ModRM >= 0xc0)
- * {
- * tmp=I.regs.w[Mod_RM.RM.w[ModRM]];
- * nec_ICount-=29;
- * }
- * else
- * {
- * int old=nec_ICount;
- * (*GetEA[ModRM])();
- * tmp=ReadWord(EA);
- * nec_ICount=old-33;
- * }
- * tmp <<= 4;
- * tmp |= I.regs.b[AL] & 0xF;
- * I.regs.b[AL] = (I.regs.b[AL] & 0xF0) | ((tmp>>8)&0xF);
- * tmp &= 0xffff;
- * PutbackRMWord(ModRM,tmp);
- */
- logerror("PC=%06x : ROL4 %02x\n", I.pc - 3, ModRM);
- break;
-
- case 0x2A: /* 0F 2a c2 - ROR4 bh */
- ModRM = FETCH;
- /* tmp = GetRMByte(ModRM); */
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.b[Mod_RM.RM.b[ModRM]];
- nec_ICount -= 29;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadByte(EA);
- nec_ICount = old - 33;
- }
- tmp2 = (I.regs.b[AL] & 0xF) << 4;
- I.regs.b[AL] = (I.regs.b[AL] & 0xF0) | (tmp & 0xF);
- tmp = tmp2 | (tmp >> 4);
- PutbackRMByte(ModRM, tmp);
- break;
-
- case 0x2B: // 0F 2b c2 - ROR4 bx
- ModRM = FETCH;
- /*
- * /* tmp = GetRMWord(ModRM);
- * if (ModRM >= 0xc0)
- * {
- * tmp=I.regs.w[Mod_RM.RM.w[ModRM]];
- * nec_ICount-=29;
- * }
- * else {
- * int old=nec_ICount;
- * (*GetEA[ModRM])();
- * tmp=ReadWord(EA);
- * nec_ICount=old-33;
- * }
- * tmp2 = (I.regs.b[AL] & 0xF)<<4;
- * I.regs.b[AL] = (I.regs.b[AL] & 0xF0) | (tmp&0xF);
- * tmp = tmp2 | (tmp>>4);
- * PutbackRMWord(ModRM,tmp);
- */
- logerror("PC=%06x : ROR4 %02x\n", I.pc - 3, ModRM);
- break;
-
- case 0x2D: /* 0Fh 2Dh <1111 1RRR> */
- /* OPCODE BRKCS - Break with Contex Switch
- * CPU: NEC V25,V35,V25 Plus,V35 Plus,V25 Software Guard
- * Description:
- *
- * Perform a High-Speed Software Interrupt with contex-switch to
- * register bank indicated by the lower 3-bits of 'bank'.
- *
- * Info: NEC V25/V35/V25 Plus/V35 Plus Bank System
- *
- * This Chips have 8 32bytes register banks, which placed in
- * Internal chip RAM by addresses:
- * xxE00h..xxE1Fh Bank 0
- * xxE20h..xxE3Fh Bank 1
- * .........
- * xxEC0h..xxEDFh Bank 6
- * xxEE0h..xxEFFh Bank 7
- * xxF00h..xxFFFh Special Functions Register
- * Where xx is Value of IDB register.
- * IBD is Byte Register contained Internal data area base
- * IBD addresses is FFFFFh and xxFFFh where xx is data in IBD.
- *
- * Format of Bank:
- * +0 Reserved
- * +2 Vector PC
- * +4 Save PSW
- * +6 Save PC
- * +8 DS0 ;DS
- * +A SS ;SS
- * +C PS ;CS
- * +E DS1 ;ES
- * +10 IY ;DI
- * +11 IX ;SI
- * +14 BP ;BP
- * +16 SP ;SP
- * +18 BW ;BX
- * +1A DW ;DX
- * +1C CW ;CX
- * +1E AW ;AX
- *
- * Format of V25 etc. PSW (FLAGS):
- * Bit Description
- * 15 1
- * 14 RB2 \
- * 13 RB1 > Current Bank Number
- * 12 RB0 /
- * 11 V ;OF
- * 10 IYR ;DF
- * 9 IE ;IF
- * 8 BRK ;TF
- * 7 S ;SF
- * 6 Z ;ZF
- * 5 F1 General Purpose user flag #1 (accessed by Flag Special Function Register)
- * 4 AC ;AF
- * 3 F0 General purpose user flag #0 (accessed by Flag Special Function Register)
- * 2 P ;PF
- * 1 BRKI I/O Trap Enable Flag
- * 0 CY ;CF
- *
- * Flags Affected: None
- */
- ModRM = FETCH;
- logerror("PC=%06x : BRKCS %02x\n", I.pc - 3, ModRM);
- nec_ICount -= 15; /* checked ! */
- break;
-
- case 0x31: /* 0F 31 [mod:reg:r/m] - INS reg8,reg8 or INS reg8,imm4 */
- ModRM = FETCH;
- logerror("PC=%06x : INS ", I.pc - 2);
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.b[Mod_RM.RM.b[ModRM]];
- logerror("ModRM=%04x \n", ModRM);
- nec_ICount -= 29;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadByte(EA);
- logerror("ModRM=%04x Byte=%04x\n", EA, tmp);
- nec_ICount = old - 33;
- }
-
- /* more to come
- * bfl=tmp2 & 0xf; /* bit field length
- * bfs=tmp & 0xf; /* bit field start (bit offset in DS:SI)
- * I.regs.b[AH] =0; /* AH =0
- */
-
- /* 2do: the rest is silence....yet
- * ----------O-INS------------------------------------
- * OPCODE INS - Insert Bit String
- *
- * CPU: NEC/Sony all V-series
- * Type of Instruction: User
- *
- * Instruction: INS start,len
- *
- * Description:
- *
- * BitField [ BASE = ES:DI
- * START BIT OFFSET = start
- * LENGTH = len
- * ] <- AX [ bits= (len-1)..0]
- *
- * Note: di and start automatically UPDATE
- * Note: Alternative Name of this instruction is NECINS
- *
- * Flags Affected: None
- *
- * CPU mode: RM
- *
- * +++++++++++++++++++++++
- * Physical Form : INS reg8,reg8
- * COP (Code of Operation) : 0FH 31H PostByte
- */
-
- /* nec_ICount-=31; */ /* 31 -117 clocks ....*/
- break;
-
- case 0x33: /* 0F 33 [mod:reg:r/m] - EXT reg8,reg8 or EXT reg8,imm4 */
- ModRM = FETCH;
- logerror("PC=%06x : EXT ", I.pc - 2);
- if (ModRM >= 0xc0)
- {
- tmp = I.regs.b[Mod_RM.RM.b[ModRM]];
- logerror("ModRM=%04x \n", ModRM);
- nec_ICount -= 29;
- }
- else
- {
- int old = nec_ICount;
-
- (*GetEA[ModRM]) ();
- tmp = ReadByte(EA);
- logerror("ModRM=%04x Byte=%04x\n", EA, tmp);
- nec_ICount = old - 33;
- }
- /* 2do: the rest is silence....yet
- /*
- * bfl=tmp2 & 0xf; /* bit field length
- * bfs=tmp & 0xf; /* bit field start (bit offset in DS:SI)
- * I.regs.b[AH] =0; /* AH =0
- */
-
- /*
- *
- * ----------O-EXT------------------------------------
- * OPCODE EXT - Extract Bit Field
- *
- * CPU: NEC/Sony all V-series
- * Type of Instruction: User
- *
- * Instruction: EXT start,len
- *
- * Description:
- *
- * AX <- BitField [
- * BASE = DS:SI
- * START BIT OFFSET = start
- * LENGTH = len
- * ];
- *
- * Note: si and start automatically UPDATE
- *
- * Flags Affected: None
- *
- * CPU mode: RM
- *
- * +++++++++++++++++++++++
- * Physical Form : EXT reg8,reg8
- * COP (Code of Operation) : 0FH 33H PostByte
- *
- * Clocks: EXT reg8,reg8
- * NEC V20: 26-55
- */
-
- /* NEC_ICount-=26; */ /* 26 -55 clocks ....*/
- break;
-
- case 0x91:
- /*
- * ----------O-RETRBI---------------------------------
- * OPCODE RETRBI - Return from Register Bank Context
- * Switch Interrupt.
- *
- * CPU: NEC V25,V35,V25 Plus,V35 Plus,V25 Software Guard
- * Type of Instruction: System
- *
- * Instruction: RETRBI
- *
- * Description:
- *
- * PC <- Save PC;
- * PSW <- Save PSW;
- *
- * Flags Affected: All
- *
- * CPU mode: RM
- *
- * +++++++++++++++++++++++
- * Physical Form: RETRBI
- * COP (Code of Operation) : 0Fh 91h
- *
- * Clocks: 12
- */
- logerror("PC=%06x : RETRBI\n", I.pc - 2);
- nec_ICount -= 12;
- break;
-
- case 0x94:
- /*
- * ----------O-TSKSW----------------------------------
- * OPCODE TSKSW - Task Switch
- *
- * CPU: NEC V25,V35,V25 Plus,V35 Plus,V25 Software Guard
- * Type of Instruction: System
- *
- * Instruction: TSKSW reg16
- *
- * Description: Perform a High-Speed task switch to the register bank indicated
- * by lower 3 bits of reg16. The PC and PSW are saved in the old
- * banks. PC and PSW save Registers and the new PC and PSW values
- * are retrived from the new register bank's save area.
- *
- * Note: See BRKCS instruction for more Info about banks.
- *
- * Flags Affected: All
- *
- * CPU mode: RM
- *
- * +++++++++++++++++++++++
- * Physical Form: TSCSW reg16
- * COP (Code of Operation) : 0Fh 94h <1111 1RRR>
- *
- * Clocks: 11
- */
- ModRM = FETCH;
-
- logerror("PC=%06x : TSCSW %02x\n", I.pc - 3, ModRM);
- nec_ICount -= 11;
- break;
-
- case 0x95:
- /*
- * ----------O-MOVSPB---------------------------------
- * OPCODE MOVSPB - Move Stack Pointer Before Bamk Switching
- *
- * CPU: NEC V25,V35,V25 Plus,V35 Plus,V25 Software Guard
- * Type of Instruction: System
- *
- * Instruction: MOVSPB Number_of_bank
- *
- * Description: The MOVSPB instruction transfers the current SP and SS before
- * the bank switching to new register bank.
- *
- * Note: New Register Bank Number indicated by lower 3bit of Number_of_
- * _bank.
- *
- * Note: See BRKCS instruction for more info about banks.
- *
- * Flags Affected: None
- *
- * CPU mode: RM
- *
- * +++++++++++++++++++++++
- * Physical Form: MOVSPB reg16
- * COP (Code of Operation) : 0Fh 95h <1111 1RRR>
- *
- * Clocks: 11
- */
- ModRM = FETCH;
- logerror("PC=%06x : MOVSPB %02x\n", I.pc - 3, ModRM);
- nec_ICount -= 11;
- break;
-
- case 0xbe:
- /*
- * ----------O-STOP-----------------------------------
- * OPCODE STOP - Stop CPU
- *
- * CPU: NEC V25,V35,V25 Plus,V35 Plus,V25 Software Guard
- * Type of Instruction: System
- *
- * Instruction: STOP
- *
- * Description:
- * PowerDown instruction, Stop Oscillator,
- * Halt CPU.
- *
- * Flags Affected: None
- *
- * CPU mode: RM
- *
- * +++++++++++++++++++++++
- * Physical Form: STOP
- * COP (Code of Operation) : 0Fh BEh
- *
- * Clocks: N/A
- */
- logerror("PC=%06x : STOP\n", I.pc - 2);
- nec_ICount -= 2; /* of course this is crap */
- break;
-
- case 0xe0:
- /*
- * ----------O-BRKXA----------------------------------
- * OPCODE BRKXA - Break to Expansion Address
- *
- * CPU: NEC V33/V53 only
- * Type of Instruction: System
- *
- * Instruction: BRKXA int_vector
- *
- * Description:
- * [sp-1,sp-2] <- PSW ; PSW EQU FLAGS
- * [sp-3,sp-4] <- PS ; PS EQU CS
- * [sp-5,sp-6] <- PC ; PC EQU IP
- * SP <- SP -6
- * IE <- 0
- * BRK <- 0
- * MD <- 0
- * PC <- [int_vector*4 +0,+1]
- * PS <- [int_vector*4 +2,+3]
- * Enter Expansion Address Mode.
- *
- * Note: In NEC V53 Memory Space dividing into 1024 16K pages.
- * The programming model is Same as in Normal mode.
- *
- * Mechanism is:
- * 20 bit Logical Address: 19..14 Page Num 13..0 Offset
- *
- * page Num convertin by internal table to 23..14 Page Base
- * tHE pHYIXCAL ADDRESS is both Base and Offset.
- *
- * Address Expansion Registers:
- * logical Address A19..A14 I/O Address
- * 0 FF00h
- * 1 FF02h
- * ... ...
- * 63 FF7Eh
- *
- * Register XAM aliased with port # FF80h indicated current mode
- * of operation.
- * Format of XAM register (READ ONLY):
- * 15..1 reserved
- * 0 XA Flag, if=1 then in XA mode.
- *
- * Format of V53 PSW:
- * 15..12 1
- * 11 V
- * 10 IYR
- * 9 IE
- * 8 BRK
- * 7 S
- * 6 Z
- * 5 0
- * 4 AC
- * 3 0
- * 2 P
- * 1 1
- * 0 CY
- *
- * Flags Affected: None
- *
- * CPU mode: RM
- *
- * +++++++++++++++++++++++
- * Physical Form: BRKXA imm8
- * COP (Code of Operation) : 0Fh E0h imm8
- */
-
- ModRM = FETCH;
- logerror("PC=%06x : BRKXA %02x\n", I.pc - 3, ModRM);
- nec_ICount -= 12;
- break;
-
- case 0xf0:
- /*
- * ----------O-RETXA----------------------------------
- * OPCODE RETXA - Return from Expansion Address
- *
- * CPU: NEC V33/V53 only
- * Type of Instruction: System
- *
- * Instruction: RETXA int_vector
- *
- * Description:
- * [sp-1,sp-2] <- PSW ; PSW EQU FLAGS
- * [sp-3,sp-4] <- PS ; PS EQU CS
- * [sp-5,sp-6] <- PC ; PC EQU IP
- * SP <- SP -6
- * IE <- 0
- * BRK <- 0
- * MD <- 0
- * PC <- [int_vector*4 +0,+1]
- * PS <- [int_vector*4 +2,+3]
- * Disable EA mode.
- *
- * Flags Affected: None
- *
- * CPU mode: RM
- *
- * +++++++++++++++++++++++
- * Physical Form: RETXA imm8
- * COP (Code of Operation) : 0Fh F0h imm8
- *
- * Clocks: 12
- */
- ModRM = FETCH;
- logerror("PC=%06x : RETXA %02x\n", I.pc - 3, ModRM);
- nec_ICount -= 12;
- break;
-
- case 0xff: /* 0F ff imm8 - BRKEM */
- /*
- * OPCODE BRKEM - Break for Emulation
- *
- * CPU: NEC/Sony V20/V30/V40/V50
- * Description:
- *
- * PUSH FLAGS
- * PUSH CS
- * PUSH IP
- * MOV CS,0:[intnum*4+2]
- * MOV IP,0:[intnum*4]
- * MD <- 0; // Enable 8080 emulation
- *
- * Note:
- * BRKEM instruction do software interrupt and then New CS,IP loaded
- * it switch to 8080 mode i.e. CPU will execute 8080 code.
- * Mapping Table of Registers in 8080 Mode
- * 8080 Md. A B C D E H L SP PC F
- * native. AL CH CL DH DL BH BL BP IP FLAGS(low)
- * For Return of 8080 mode use CALLN instruction.
- * Note: I.e. 8080 addressing only 64KB then "Real Address" is CS*16+PC
- *
- * Flags Affected: MD
- */
- ModRM = FETCH;
- nec_ICount -= 38;
- logerror("PC=%06x : BRKEM %02x\n", I.pc - 3, ModRM);
- PREFIXV30(_interrupt) (ModRM, 1);
- break;
- }
-}
-
-static void PREFIXV30(_brkn) (void) /* Opcode 0x63 BRKN - Break to Native Mode */
-{
- /*
- * CPU: NEC (V25/V35) Software Guard only
- * Instruction: BRKN int_vector
- *
- * Description:
- * [sp-1,sp-2] <- PSW ; PSW EQU FLAGS
- * [sp-3,sp-4] <- PS ; PS EQU CS
- * [sp-5,sp-6] <- PC ; PC EQU IP
- * SP <- SP -6
- * IE <- 0
- * BRK <- 0
- * MD <- 1
- * PC <- [int_vector*4 +0,+1]
- * PS <- [int_vector*4 +2,+3]
- *
- * Note: The BRKN instruction switches operations in Native Mode
- * from Security Mode via Interrupt call. In Normal Mode
- * Instruction executed as mPD70320/70322 (V25) operation mode.
- *
- * Flags Affected: None
- *
- * CPU mode: RM
- *
- * +++++++++++++++++++++++
- * Physical Form: BRKN imm8
- * COP (Code of Operation) : 63h imm8
- *
- * Clocks: 56+10T [44+10T]
- */
- /* nec_ICount-=56; */
- unsigned int_vector;
-
- int_vector = FETCH;
- logerror("PC=%06x : BRKN %02x\n", I.pc - 2, int_vector);
-}
-
-static void PREFIXV30(repc) (int flagval)
-{
- /* Handles repc- and repnc- prefixes. flagval is the value of ZF
- * for the loop to continue for CMPS and SCAS instructions.
- */
-
- unsigned next = FETCHOP;
- unsigned count = I.regs.w[CX];
-
- switch (next)
- {
- case 0x26: /* ES: */
- seg_prefix = TRUE;
- prefix_base = I.base[ES];
- nec_ICount -= 2;
- PREFIXV30(repc) (flagval);
- break;
- case 0x2e: /* CS: */
- seg_prefix = TRUE;
- prefix_base = I.base[CS];
- nec_ICount -= 2;
- PREFIXV30(repc) (flagval);
- break;
- case 0x36: /* SS: */
- seg_prefix = TRUE;
- prefix_base = I.base[SS];
- nec_ICount -= 2;
- PREFIXV30(repc) (flagval);
- break;
- case 0x3e: /* DS: */
- seg_prefix = TRUE;
- prefix_base = I.base[DS];
- nec_ICount -= 2;
- PREFIXV30(repc) (flagval);
- break;
- case 0x6c: /* REP INSB */
- nec_ICount -= 9 - count;
- for (; (CF == flagval) && (count > 0); count--)
- PREFIX186(_insb) ();
- I.regs.w[CX] = count;
- break;
- case 0x6d: /* REP INSW */
- nec_ICount -= 9 - count;
- for (; (CF == flagval) && (count > 0); count--)
- PREFIX186(_insw) ();
- I.regs.w[CX] = count;
- break;
- case 0x6e: /* REP OUTSB */
- nec_ICount -= 9 - count;
- for (; (CF == flagval) && (count > 0); count--)
- PREFIX186(_outsb) ();
- I.regs.w[CX] = count;
- break;
- case 0x6f: /* REP OUTSW */
- nec_ICount -= 9 - count;
- for (; (CF == flagval) && (count > 0); count--)
- PREFIX186(_outsw) ();
- I.regs.w[CX] = count;
- break;
- case 0xa4: /* REP MOVSB */
- nec_ICount -= 9 - count;
- for (; (CF == flagval) && (count > 0); count--)
- PREFIX86(_movsb) ();
- I.regs.w[CX] = count;
- break;
- case 0xa5: /* REP MOVSW */
- nec_ICount -= 9 - count;
- for (; (CF == flagval) && (count > 0); count--)
- PREFIX86(_movsw) ();
- I.regs.w[CX] = count;
- break;
- case 0xa6: /* REP(N)E CMPSB */
- nec_ICount -= 9;
- for (I.ZeroVal = !flagval; (ZF == flagval) && (CF == flagval) && (count > 0); count--)
- PREFIX86(_cmpsb) ();
- I.regs.w[CX] = count;
- break;
- case 0xa7: /* REP(N)E CMPSW */
- nec_ICount -= 9;
- for (I.ZeroVal = !flagval; (ZF == flagval) && (CF == flagval) && (count > 0); count--)
- PREFIX86(_cmpsw) ();
- I.regs.w[CX] = count;
- break;
- case 0xaa: /* REP STOSB */
- nec_ICount -= 9 - count;
- for (; (CF == flagval) && (count > 0); count--)
- PREFIX86(_stosb) ();
- I.regs.w[CX] = count;
- break;
- case 0xab: /* REP STOSW */
- nec_ICount -= 9 - count;
- for (; (CF == flagval) && (count > 0); count--)
- PREFIX86(_stosw) ();
- I.regs.w[CX] = count;
- break;
- case 0xac: /* REP LODSB */
- nec_ICount -= 9;
- for (; (CF == flagval) && (count > 0); count--)
- PREFIX86(_lodsb) ();
- I.regs.w[CX] = count;
- break;
- case 0xad: /* REP LODSW */
- nec_ICount -= 9;
- for (; (CF == flagval) && (count > 0); count--)
- PREFIX86(_lodsw) ();
- I.regs.w[CX] = count;
- break;
- case 0xae: /* REP(N)E SCASB */
- nec_ICount -= 9;
- for (I.ZeroVal = !flagval; (ZF == flagval) && (CF == flagval) && (count > 0); count--)
- PREFIX86(_scasb) ();
- I.regs.w[CX] = count;
- break;
- case 0xaf: /* REP(N)E SCASW */
- nec_ICount -= 9;
- for (I.ZeroVal = !flagval; (ZF == flagval) && (CF == flagval) && (count > 0); count--)
- PREFIX86(_scasw) ();
- I.regs.w[CX] = count;
- break;
- default:
- PREFIXV30(_instruction)[next] ();
- }
-}
-
-static void PREFIXV30(_repnc) (void) /* Opcode 0x64 */
-{
- PREFIXV30(repc) (0);
-}
-
-static void PREFIXV30(_repc) (void) /* Opcode 0x65 */
-{
- PREFIXV30(repc) (1);
-}
-
-static void PREFIXV30(_setalc) (void) /* Opcode 0xd6 */
-{
- /*
- * ----------O-SETALC---------------------------------
- * OPCODE SETALC - Set AL to Carry Flag
- *
- * CPU: Intel 8086 and all its clones and upward
- * compatibility chips.
- * Type of Instruction: User
- *
- * Instruction: SETALC
- *
- * Description:
- *
- * IF (CF=0) THEN AL:=0 ELSE AL:=FFH;
- *
- * Flags Affected: None
- *
- * CPU mode: RM,PM,VM,SMM
- *
- * Physical Form: SETALC
- * COP (Code of Operation): D6H
- * Clocks: 80286 : n/a [3]
- * 80386 : n/a [3]
- * Cx486SLC : n/a [2]
- * i486 : n/a [3]
- * Pentium : n/a [3]
- * Note: n/a is Time that Intel etc not say.
- * [3] is real time it executed.
- *
- */
- I.regs.b[AL] = (CF) ? 0xff : 0x00;
- nec_ICount -= 3; // V30
- logerror("PC=%06x : SETALC\n", I.pc - 1);
-}
-
-#if 0
-static void PREFIXV30(_brks) (void) /* Opcode 0xf1 - Break to Security Mode */
-{
- /*
- * CPU: NEC (V25/V35) Software Guard only
- * Instruction: BRKS int_vector
- *
- * Description:
- * [sp-1,sp-2] <- PSW ; PSW EQU FLAGS
- * [sp-3,sp-4] <- PS ; PS EQU CS
- * [sp-5,sp-6] <- PC ; PC EQU IP
- * SP <- SP -6
- * IE <- 0
- * BRK <- 0
- * MD <- 0
- * PC <- [int_vector*4 +0,+1]
- * PS <- [int_vector*4 +2,+3]
- *
- * Note: The BRKS instruction switches operations in Security Mode
- * via Interrupt call. In Security Mode the fetched operation
- * code is executed after conversion in accordance with build-in
- * translation table
- *
- * Flags Affected: None
- *
- * CPU mode: RM
- *
- * +++++++++++++++++++++++
- * Physical Form: BRKS imm8
- * Clocks: 56+10T [44+10T]
- */
- unsigned int_vector;
-
- int_vector = FETCH;
- logerror("PC=%06x : BRKS %02x\n", I.pc - 2, int_vector);
-}
-#endif
diff --git a/src/emu/cpu/i86/instrv30.h b/src/emu/cpu/i86/instrv30.h
deleted file mode 100644
index 0647ae8d841..00000000000
--- a/src/emu/cpu/i86/instrv30.h
+++ /dev/null
@@ -1,7 +0,0 @@
-static void PREFIXV30(_0fpre)(void);
-static void PREFIXV30(_repnc)(void);
-static void PREFIXV30(_repc)(void);
-static void PREFIXV30(_setalc)(void);
-#if 0
-static void PREFIXV30(_brks)(void);
-#endif
diff --git a/src/emu/cpu/i86/modrm.h b/src/emu/cpu/i86/modrm.h
index 2f83dbfe1e9..5919ebf230a 100644
--- a/src/emu/cpu/i86/modrm.h
+++ b/src/emu/cpu/i86/modrm.h
@@ -12,81 +12,81 @@ static struct
} RM;
} Mod_RM;
-#define RegWord(ModRM) I.regs.w[Mod_RM.reg.w[ModRM]]
-#define RegByte(ModRM) I.regs.b[Mod_RM.reg.b[ModRM]]
+#define RegWord(ModRM) cpustate->regs.w[Mod_RM.reg.w[ModRM]]
+#define RegByte(ModRM) cpustate->regs.b[Mod_RM.reg.b[ModRM]]
#define GetRMWord(ModRM) \
- ((ModRM) >= 0xc0 ? I.regs.w[Mod_RM.RM.w[ModRM]] : ( (*GetEA[ModRM])(), ReadWord( EA ) ))
+ ((ModRM) >= 0xc0 ? cpustate->regs.w[Mod_RM.RM.w[ModRM]] : ( (*GetEA[ModRM])(cpustate), ReadWord( cpustate->ea ) ))
#define PutbackRMWord(ModRM,val) \
{ \
- if (ModRM >= 0xc0) I.regs.w[Mod_RM.RM.w[ModRM]]=val; \
- else WriteWord(EA,val); \
+ if (ModRM >= 0xc0) cpustate->regs.w[Mod_RM.RM.w[ModRM]]=val; \
+ else WriteWord(cpustate->ea,val); \
}
-#define GetnextRMWord ReadWord(EA+2)
+#define GetnextRMWord ReadWord(cpustate->ea+2)
#define GetRMWordOffset(offs) \
- ReadWord(EA-EO+(UINT16)(EO+offs))
+ ReadWord(cpustate->ea-cpustate->eo+(UINT16)(cpustate->eo+offs))
#define GetRMByteOffset(offs) \
- ReadByte(EA-EO+(UINT16)(EO+offs))
+ ReadByte(cpustate->ea-cpustate->eo+(UINT16)(cpustate->eo+offs))
#define PutRMWord(ModRM,val) \
{ \
if (ModRM >= 0xc0) \
- I.regs.w[Mod_RM.RM.w[ModRM]]=val; \
+ cpustate->regs.w[Mod_RM.RM.w[ModRM]]=val; \
else { \
- (*GetEA[ModRM])(); \
- WriteWord( EA ,val); \
+ (*GetEA[ModRM])(cpustate); \
+ WriteWord( cpustate->ea ,val); \
} \
}
#define PutRMWordOffset(offs, val) \
- WriteWord( EA-EO+(UINT16)(EO+offs), val)
+ WriteWord( cpustate->ea-cpustate->eo+(UINT16)(cpustate->eo+offs), val)
#define PutRMByteOffset(offs, val) \
- WriteByte( EA-EO+(UINT16)(EO+offs), val)
+ WriteByte( cpustate->ea-cpustate->eo+(UINT16)(cpustate->eo+offs), val)
#define PutImmRMWord(ModRM) \
{ \
WORD val; \
if (ModRM >= 0xc0) \
- FETCHWORD(I.regs.w[Mod_RM.RM.w[ModRM]]) \
+ FETCHWORD(cpustate->regs.w[Mod_RM.RM.w[ModRM]]) \
else { \
- (*GetEA[ModRM])(); \
+ (*GetEA[ModRM])(cpustate); \
FETCHWORD(val) \
- WriteWord( EA , val); \
+ WriteWord( cpustate->ea , val); \
} \
}
#define GetRMByte(ModRM) \
- ((ModRM) >= 0xc0 ? I.regs.b[Mod_RM.RM.b[ModRM]] : ReadByte( (*GetEA[ModRM])() ))
+ ((ModRM) >= 0xc0 ? cpustate->regs.b[Mod_RM.RM.b[ModRM]] : ReadByte( (*GetEA[ModRM])(cpustate) ))
#define PutRMByte(ModRM,val) \
{ \
if (ModRM >= 0xc0) \
- I.regs.b[Mod_RM.RM.b[ModRM]]=val; \
+ cpustate->regs.b[Mod_RM.RM.b[ModRM]]=val; \
else \
- WriteByte( (*GetEA[ModRM])() ,val); \
+ WriteByte( (*GetEA[ModRM])(cpustate) ,val); \
}
#define PutImmRMByte(ModRM) \
{ \
if (ModRM >= 0xc0) \
- I.regs.b[Mod_RM.RM.b[ModRM]]=FETCH; \
+ cpustate->regs.b[Mod_RM.RM.b[ModRM]]=FETCH; \
else { \
- (*GetEA[ModRM])(); \
- WriteByte( EA , FETCH ); \
+ (*GetEA[ModRM])(cpustate); \
+ WriteByte( cpustate->ea , FETCH ); \
} \
}
#define PutbackRMByte(ModRM,val) \
{ \
if (ModRM >= 0xc0) \
- I.regs.b[Mod_RM.RM.b[ModRM]]=val; \
+ cpustate->regs.b[Mod_RM.RM.b[ModRM]]=val; \
else \
- WriteByte(EA,val); \
+ WriteByte(cpustate->ea,val); \
}
#define DEF_br8(dst,src) \
@@ -111,9 +111,9 @@ static struct
#define DEF_ald8(dst,src) \
unsigned src = FETCHOP; \
- unsigned dst = I.regs.b[AL]
+ unsigned dst = cpustate->regs.b[AL]
#define DEF_axd16(dst,src) \
unsigned src = FETCHOP; \
- unsigned dst = I.regs.w[AX]; \
+ unsigned dst = cpustate->regs.w[AX]; \
src += (FETCH << 8)
diff --git a/src/emu/cpu/i86/table186.h b/src/emu/cpu/i86/table186.h
index 9a415558f0f..d7fd9e4198e 100644
--- a/src/emu/cpu/i86/table186.h
+++ b/src/emu/cpu/i86/table186.h
@@ -1,4 +1,4 @@
-static void (*const PREFIX186(_instruction)[256])(void) =
+static void (*const PREFIX186(_instruction)[256])(i8086_state *cpustate) =
{
PREFIX86(_add_br8), /* 0x00 */
PREFIX86(_add_wr16), /* 0x01 */
@@ -263,263 +263,263 @@ static void (*const PREFIX186(_instruction)[256])(void) =
#define TABLE186 \
switch(FETCHOP)\
{\
- case 0x00: PREFIX86(_add_br8)(); break;\
- case 0x01: PREFIX86(_add_wr16)(); break;\
- case 0x02: PREFIX86(_add_r8b)(); break;\
- case 0x03: PREFIX86(_add_r16w)(); break;\
- case 0x04: PREFIX86(_add_ald8)(); break;\
- case 0x05: PREFIX86(_add_axd16)(); break;\
- case 0x06: PREFIX86(_push_es)(); break;\
- case 0x07: PREFIX86(_pop_es)(); break;\
- case 0x08: PREFIX86(_or_br8)(); break;\
- case 0x09: PREFIX86(_or_wr16)(); break;\
- case 0x0a: PREFIX86(_or_r8b)(); break;\
- case 0x0b: PREFIX86(_or_r16w)(); break;\
- case 0x0c: PREFIX86(_or_ald8)(); break;\
- case 0x0d: PREFIX86(_or_axd16)(); break;\
- case 0x0e: PREFIX86(_push_cs)(); break;\
- case 0x0f: PREFIX86(_invalid)(); break;\
- case 0x10: PREFIX86(_adc_br8)(); break;\
- case 0x11: PREFIX86(_adc_wr16)(); break;\
- case 0x12: PREFIX86(_adc_r8b)(); break;\
- case 0x13: PREFIX86(_adc_r16w)(); break;\
- case 0x14: PREFIX86(_adc_ald8)(); break;\
- case 0x15: PREFIX86(_adc_axd16)(); break;\
- case 0x16: PREFIX86(_push_ss)(); break;\
- case 0x17: PREFIX86(_pop_ss)(); break;\
- case 0x18: PREFIX86(_sbb_br8)(); break;\
- case 0x19: PREFIX86(_sbb_wr16)(); break;\
- case 0x1a: PREFIX86(_sbb_r8b)(); break;\
- case 0x1b: PREFIX86(_sbb_r16w)(); break;\
- case 0x1c: PREFIX86(_sbb_ald8)(); break;\
- case 0x1d: PREFIX86(_sbb_axd16)(); break;\
- case 0x1e: PREFIX86(_push_ds)(); break;\
- case 0x1f: PREFIX86(_pop_ds)(); break;\
- case 0x20: PREFIX86(_and_br8)(); break;\
- case 0x21: PREFIX86(_and_wr16)(); break;\
- case 0x22: PREFIX86(_and_r8b)(); break;\
- case 0x23: PREFIX86(_and_r16w)(); break;\
- case 0x24: PREFIX86(_and_ald8)(); break;\
- case 0x25: PREFIX86(_and_axd16)(); break;\
- case 0x26: PREFIX86(_es)(); break;\
- case 0x27: PREFIX86(_daa)(); break;\
- case 0x28: PREFIX86(_sub_br8)(); break;\
- case 0x29: PREFIX86(_sub_wr16)(); break;\
- case 0x2a: PREFIX86(_sub_r8b)(); break;\
- case 0x2b: PREFIX86(_sub_r16w)(); break;\
- case 0x2c: PREFIX86(_sub_ald8)(); break;\
- case 0x2d: PREFIX86(_sub_axd16)(); break;\
- case 0x2e: PREFIX86(_cs)(); break;\
- case 0x2f: PREFIX86(_das)(); break;\
- case 0x30: PREFIX86(_xor_br8)(); break;\
- case 0x31: PREFIX86(_xor_wr16)(); break;\
- case 0x32: PREFIX86(_xor_r8b)(); break;\
- case 0x33: PREFIX86(_xor_r16w)(); break;\
- case 0x34: PREFIX86(_xor_ald8)(); break;\
- case 0x35: PREFIX86(_xor_axd16)(); break;\
- case 0x36: PREFIX86(_ss)(); break;\
- case 0x37: PREFIX86(_aaa)(); break;\
- case 0x38: PREFIX86(_cmp_br8)(); break;\
- case 0x39: PREFIX86(_cmp_wr16)(); break;\
- case 0x3a: PREFIX86(_cmp_r8b)(); break;\
- case 0x3b: PREFIX86(_cmp_r16w)(); break;\
- case 0x3c: PREFIX86(_cmp_ald8)(); break;\
- case 0x3d: PREFIX86(_cmp_axd16)(); break;\
- case 0x3e: PREFIX86(_ds)(); break;\
- case 0x3f: PREFIX86(_aas)(); break;\
- case 0x40: PREFIX86(_inc_ax)(); break;\
- case 0x41: PREFIX86(_inc_cx)(); break;\
- case 0x42: PREFIX86(_inc_dx)(); break;\
- case 0x43: PREFIX86(_inc_bx)(); break;\
- case 0x44: PREFIX86(_inc_sp)(); break;\
- case 0x45: PREFIX86(_inc_bp)(); break;\
- case 0x46: PREFIX86(_inc_si)(); break;\
- case 0x47: PREFIX86(_inc_di)(); break;\
- case 0x48: PREFIX86(_dec_ax)(); break;\
- case 0x49: PREFIX86(_dec_cx)(); break;\
- case 0x4a: PREFIX86(_dec_dx)(); break;\
- case 0x4b: PREFIX86(_dec_bx)(); break;\
- case 0x4c: PREFIX86(_dec_sp)(); break;\
- case 0x4d: PREFIX86(_dec_bp)(); break;\
- case 0x4e: PREFIX86(_dec_si)(); break;\
- case 0x4f: PREFIX86(_dec_di)(); break;\
- case 0x50: PREFIX86(_push_ax)(); break;\
- case 0x51: PREFIX86(_push_cx)(); break;\
- case 0x52: PREFIX86(_push_dx)(); break;\
- case 0x53: PREFIX86(_push_bx)(); break;\
- case 0x54: PREFIX86(_push_sp)(); break;\
- case 0x55: PREFIX86(_push_bp)(); break;\
- case 0x56: PREFIX86(_push_si)(); break;\
- case 0x57: PREFIX86(_push_di)(); break;\
- case 0x58: PREFIX86(_pop_ax)(); break;\
- case 0x59: PREFIX86(_pop_cx)(); break;\
- case 0x5a: PREFIX86(_pop_dx)(); break;\
- case 0x5b: PREFIX86(_pop_bx)(); break;\
- case 0x5c: PREFIX86(_pop_sp)(); break;\
- case 0x5d: PREFIX86(_pop_bp)(); break;\
- case 0x5e: PREFIX86(_pop_si)(); break;\
- case 0x5f: PREFIX86(_pop_di)(); break;\
- case 0x60: PREFIX186(_pusha)(); break;\
- case 0x61: PREFIX186(_popa)(); break;\
- case 0x62: PREFIX186(_bound)(); break;\
- case 0x63: PREFIX86(_invalid)(); break;\
- case 0x64: PREFIX86(_invalid)(); break;\
- case 0x65: PREFIX86(_invalid)(); break;\
- case 0x66: PREFIX86(_invalid)(); break;\
- case 0x67: PREFIX86(_invalid)(); break;\
- case 0x68: PREFIX186(_push_d16)(); break;\
- case 0x69: PREFIX186(_imul_d16)(); break;\
- case 0x6a: PREFIX186(_push_d8)(); break;\
- case 0x6b: PREFIX186(_imul_d8)(); break;\
- case 0x6c: PREFIX186(_insb)(); break;\
- case 0x6d: PREFIX186(_insw)(); break;\
- case 0x6e: PREFIX186(_outsb)(); break;\
- case 0x6f: PREFIX186(_outsw)(); break;\
- case 0x70: PREFIX86(_jo)(); break;\
- case 0x71: PREFIX86(_jno)(); break;\
- case 0x72: PREFIX86(_jb)(); break;\
- case 0x73: PREFIX86(_jnb)(); break;\
- case 0x74: PREFIX86(_jz)(); break;\
- case 0x75: PREFIX86(_jnz)(); break;\
- case 0x76: PREFIX86(_jbe)(); break;\
- case 0x77: PREFIX86(_jnbe)(); break;\
- case 0x78: PREFIX86(_js)(); break;\
- case 0x79: PREFIX86(_jns)(); break;\
- case 0x7a: PREFIX86(_jp)(); break;\
- case 0x7b: PREFIX86(_jnp)(); break;\
- case 0x7c: PREFIX86(_jl)(); break;\
- case 0x7d: PREFIX86(_jnl)(); break;\
- case 0x7e: PREFIX86(_jle)(); break;\
- case 0x7f: PREFIX86(_jnle)(); break;\
- case 0x80: PREFIX86(_80pre)(); break;\
- case 0x81: PREFIX86(_81pre)(); break;\
- case 0x82: PREFIX86(_82pre)(); break;\
- case 0x83: PREFIX86(_83pre)(); break;\
- case 0x84: PREFIX86(_test_br8)(); break;\
- case 0x85: PREFIX86(_test_wr16)(); break;\
- case 0x86: PREFIX86(_xchg_br8)(); break;\
- case 0x87: PREFIX86(_xchg_wr16)(); break;\
- case 0x88: PREFIX86(_mov_br8)(); break;\
- case 0x89: PREFIX86(_mov_wr16)(); break;\
- case 0x8a: PREFIX86(_mov_r8b)(); break;\
- case 0x8b: PREFIX86(_mov_r16w)(); break;\
- case 0x8c: PREFIX86(_mov_wsreg)(); break;\
- case 0x8d: PREFIX86(_lea)(); break;\
- case 0x8e: PREFIX86(_mov_sregw)(); break;\
- case 0x8f: PREFIX86(_popw)(); break;\
- case 0x90: PREFIX86(_nop)(); break;\
- case 0x91: PREFIX86(_xchg_axcx)(); break;\
- case 0x92: PREFIX86(_xchg_axdx)(); break;\
- case 0x93: PREFIX86(_xchg_axbx)(); break;\
- case 0x94: PREFIX86(_xchg_axsp)(); break;\
- case 0x95: PREFIX86(_xchg_axbp)(); break;\
- case 0x96: PREFIX86(_xchg_axsi)(); break;\
- case 0x97: PREFIX86(_xchg_axdi)(); break;\
- case 0x98: PREFIX86(_cbw)(); break;\
- case 0x99: PREFIX86(_cwd)(); break;\
- case 0x9a: PREFIX86(_call_far)(); break;\
- case 0x9b: PREFIX86(_wait)(); break;\
- case 0x9c: PREFIX86(_pushf)(); break;\
- case 0x9d: PREFIX86(_popf)(); break;\
- case 0x9e: PREFIX86(_sahf)(); break;\
- case 0x9f: PREFIX86(_lahf)(); break;\
- case 0xa0: PREFIX86(_mov_aldisp)(); break;\
- case 0xa1: PREFIX86(_mov_axdisp)(); break;\
- case 0xa2: PREFIX86(_mov_dispal)(); break;\
- case 0xa3: PREFIX86(_mov_dispax)(); break;\
- case 0xa4: PREFIX86(_movsb)(); break;\
- case 0xa5: PREFIX86(_movsw)(); break;\
- case 0xa6: PREFIX86(_cmpsb)(); break;\
- case 0xa7: PREFIX86(_cmpsw)(); break;\
- case 0xa8: PREFIX86(_test_ald8)(); break;\
- case 0xa9: PREFIX86(_test_axd16)(); break;\
- case 0xaa: PREFIX86(_stosb)(); break;\
- case 0xab: PREFIX86(_stosw)(); break;\
- case 0xac: PREFIX86(_lodsb)(); break;\
- case 0xad: PREFIX86(_lodsw)(); break;\
- case 0xae: PREFIX86(_scasb)(); break;\
- case 0xaf: PREFIX86(_scasw)(); break;\
- case 0xb0: PREFIX86(_mov_ald8)(); break;\
- case 0xb1: PREFIX86(_mov_cld8)(); break;\
- case 0xb2: PREFIX86(_mov_dld8)(); break;\
- case 0xb3: PREFIX86(_mov_bld8)(); break;\
- case 0xb4: PREFIX86(_mov_ahd8)(); break;\
- case 0xb5: PREFIX86(_mov_chd8)(); break;\
- case 0xb6: PREFIX86(_mov_dhd8)(); break;\
- case 0xb7: PREFIX86(_mov_bhd8)(); break;\
- case 0xb8: PREFIX86(_mov_axd16)(); break;\
- case 0xb9: PREFIX86(_mov_cxd16)(); break;\
- case 0xba: PREFIX86(_mov_dxd16)(); break;\
- case 0xbb: PREFIX86(_mov_bxd16)(); break;\
- case 0xbc: PREFIX86(_mov_spd16)(); break;\
- case 0xbd: PREFIX86(_mov_bpd16)(); break;\
- case 0xbe: PREFIX86(_mov_sid16)(); break;\
- case 0xbf: PREFIX86(_mov_did16)(); break;\
- case 0xc0: PREFIX186(_rotshft_bd8)(); break;\
- case 0xc1: PREFIX186(_rotshft_wd8)(); break;\
- case 0xc2: PREFIX86(_ret_d16)(); break;\
- case 0xc3: PREFIX86(_ret)(); break;\
- case 0xc4: PREFIX86(_les_dw)(); break;\
- case 0xc5: PREFIX86(_lds_dw)(); break;\
- case 0xc6: PREFIX86(_mov_bd8)(); break;\
- case 0xc7: PREFIX86(_mov_wd16)(); break;\
- case 0xc8: PREFIX186(_enter)(); break;\
- case 0xc9: PREFIX186(_leave)(); break;\
- case 0xca: PREFIX86(_retf_d16)(); break;\
- case 0xcb: PREFIX86(_retf)(); break;\
- case 0xcc: PREFIX86(_int3)(); break;\
- case 0xcd: PREFIX86(_int)(); break;\
- case 0xce: PREFIX86(_into)(); break;\
- case 0xcf: PREFIX86(_iret)(); break;\
- case 0xd0: PREFIX86(_rotshft_b)(); break;\
- case 0xd1: PREFIX86(_rotshft_w)(); break;\
- case 0xd2: PREFIX86(_rotshft_bcl)(); break;\
- case 0xd3: PREFIX86(_rotshft_wcl)(); break;\
- case 0xd4: PREFIX86(_aam)(); break;\
- case 0xd5: PREFIX86(_aad)(); break;\
- case 0xd6: PREFIX86(_invalid)(); break;\
- case 0xd7: PREFIX86(_xlat)(); break;\
- case 0xd8: PREFIX86(_escape)(); break;\
- case 0xd9: PREFIX86(_escape)(); break;\
- case 0xda: PREFIX86(_escape)(); break;\
- case 0xdb: PREFIX86(_escape)(); break;\
- case 0xdc: PREFIX86(_escape)(); break;\
- case 0xdd: PREFIX86(_escape)(); break;\
- case 0xde: PREFIX86(_escape)(); break;\
- case 0xdf: PREFIX86(_escape)(); break;\
- case 0xe0: PREFIX86(_loopne)(); break;\
- case 0xe1: PREFIX86(_loope)(); break;\
- case 0xe2: PREFIX86(_loop)(); break;\
- case 0xe3: PREFIX86(_jcxz)(); break;\
- case 0xe4: PREFIX86(_inal)(); break;\
- case 0xe5: PREFIX86(_inax)(); break;\
- case 0xe6: PREFIX86(_outal)(); break;\
- case 0xe7: PREFIX86(_outax)(); break;\
- case 0xe8: PREFIX86(_call_d16)(); break;\
- case 0xe9: PREFIX86(_jmp_d16)(); break;\
- case 0xea: PREFIX86(_jmp_far)(); break;\
- case 0xeb: PREFIX86(_jmp_d8)(); break;\
- case 0xec: PREFIX86(_inaldx)(); break;\
- case 0xed: PREFIX86(_inaxdx)(); break;\
- case 0xee: PREFIX86(_outdxal)(); break;\
- case 0xef: PREFIX86(_outdxax)(); break;\
- case 0xf0: PREFIX86(_lock)(); break;\
- case 0xf1: PREFIX86(_invalid)(); break;\
- case 0xf2: PREFIX186(_repne)(); break;\
- case 0xf3: PREFIX186(_repe)(); break;\
- case 0xf4: PREFIX86(_hlt)(); break;\
- case 0xf5: PREFIX86(_cmc)(); break;\
- case 0xf6: PREFIX86(_f6pre)(); break;\
- case 0xf7: PREFIX86(_f7pre)(); break;\
- case 0xf8: PREFIX86(_clc)(); break;\
- case 0xf9: PREFIX86(_stc)(); break;\
- case 0xfa: PREFIX86(_cli)(); break;\
- case 0xfb: PREFIX86(_sti)(); break;\
- case 0xfc: PREFIX86(_cld)(); break;\
- case 0xfd: PREFIX86(_std)(); break;\
- case 0xfe: PREFIX86(_fepre)(); break;\
- case 0xff: PREFIX86(_ffpre)(); break;\
+ case 0x00: PREFIX86(_add_br8)(cpustate); break;\
+ case 0x01: PREFIX86(_add_wr16)(cpustate); break;\
+ case 0x02: PREFIX86(_add_r8b)(cpustate); break;\
+ case 0x03: PREFIX86(_add_r16w)(cpustate); break;\
+ case 0x04: PREFIX86(_add_ald8)(cpustate); break;\
+ case 0x05: PREFIX86(_add_axd16)(cpustate); break;\
+ case 0x06: PREFIX86(_push_es)(cpustate); break;\
+ case 0x07: PREFIX86(_pop_es)(cpustate); break;\
+ case 0x08: PREFIX86(_or_br8)(cpustate); break;\
+ case 0x09: PREFIX86(_or_wr16)(cpustate); break;\
+ case 0x0a: PREFIX86(_or_r8b)(cpustate); break;\
+ case 0x0b: PREFIX86(_or_r16w)(cpustate); break;\
+ case 0x0c: PREFIX86(_or_ald8)(cpustate); break;\
+ case 0x0d: PREFIX86(_or_axd16)(cpustate); break;\
+ case 0x0e: PREFIX86(_push_cs)(cpustate); break;\
+ case 0x0f: PREFIX86(_invalid)(cpustate); break;\
+ case 0x10: PREFIX86(_adc_br8)(cpustate); break;\
+ case 0x11: PREFIX86(_adc_wr16)(cpustate); break;\
+ case 0x12: PREFIX86(_adc_r8b)(cpustate); break;\
+ case 0x13: PREFIX86(_adc_r16w)(cpustate); break;\
+ case 0x14: PREFIX86(_adc_ald8)(cpustate); break;\
+ case 0x15: PREFIX86(_adc_axd16)(cpustate); break;\
+ case 0x16: PREFIX86(_push_ss)(cpustate); break;\
+ case 0x17: PREFIX86(_pop_ss)(cpustate); break;\
+ case 0x18: PREFIX86(_sbb_br8)(cpustate); break;\
+ case 0x19: PREFIX86(_sbb_wr16)(cpustate); break;\
+ case 0x1a: PREFIX86(_sbb_r8b)(cpustate); break;\
+ case 0x1b: PREFIX86(_sbb_r16w)(cpustate); break;\
+ case 0x1c: PREFIX86(_sbb_ald8)(cpustate); break;\
+ case 0x1d: PREFIX86(_sbb_axd16)(cpustate); break;\
+ case 0x1e: PREFIX86(_push_ds)(cpustate); break;\
+ case 0x1f: PREFIX86(_pop_ds)(cpustate); break;\
+ case 0x20: PREFIX86(_and_br8)(cpustate); break;\
+ case 0x21: PREFIX86(_and_wr16)(cpustate); break;\
+ case 0x22: PREFIX86(_and_r8b)(cpustate); break;\
+ case 0x23: PREFIX86(_and_r16w)(cpustate); break;\
+ case 0x24: PREFIX86(_and_ald8)(cpustate); break;\
+ case 0x25: PREFIX86(_and_axd16)(cpustate); break;\
+ case 0x26: PREFIX86(_es)(cpustate); break;\
+ case 0x27: PREFIX86(_daa)(cpustate); break;\
+ case 0x28: PREFIX86(_sub_br8)(cpustate); break;\
+ case 0x29: PREFIX86(_sub_wr16)(cpustate); break;\
+ case 0x2a: PREFIX86(_sub_r8b)(cpustate); break;\
+ case 0x2b: PREFIX86(_sub_r16w)(cpustate); break;\
+ case 0x2c: PREFIX86(_sub_ald8)(cpustate); break;\
+ case 0x2d: PREFIX86(_sub_axd16)(cpustate); break;\
+ case 0x2e: PREFIX86(_cs)(cpustate); break;\
+ case 0x2f: PREFIX86(_das)(cpustate); break;\
+ case 0x30: PREFIX86(_xor_br8)(cpustate); break;\
+ case 0x31: PREFIX86(_xor_wr16)(cpustate); break;\
+ case 0x32: PREFIX86(_xor_r8b)(cpustate); break;\
+ case 0x33: PREFIX86(_xor_r16w)(cpustate); break;\
+ case 0x34: PREFIX86(_xor_ald8)(cpustate); break;\
+ case 0x35: PREFIX86(_xor_axd16)(cpustate); break;\
+ case 0x36: PREFIX86(_ss)(cpustate); break;\
+ case 0x37: PREFIX86(_aaa)(cpustate); break;\
+ case 0x38: PREFIX86(_cmp_br8)(cpustate); break;\
+ case 0x39: PREFIX86(_cmp_wr16)(cpustate); break;\
+ case 0x3a: PREFIX86(_cmp_r8b)(cpustate); break;\
+ case 0x3b: PREFIX86(_cmp_r16w)(cpustate); break;\
+ case 0x3c: PREFIX86(_cmp_ald8)(cpustate); break;\
+ case 0x3d: PREFIX86(_cmp_axd16)(cpustate); break;\
+ case 0x3e: PREFIX86(_ds)(cpustate); break;\
+ case 0x3f: PREFIX86(_aas)(cpustate); break;\
+ case 0x40: PREFIX86(_inc_ax)(cpustate); break;\
+ case 0x41: PREFIX86(_inc_cx)(cpustate); break;\
+ case 0x42: PREFIX86(_inc_dx)(cpustate); break;\
+ case 0x43: PREFIX86(_inc_bx)(cpustate); break;\
+ case 0x44: PREFIX86(_inc_sp)(cpustate); break;\
+ case 0x45: PREFIX86(_inc_bp)(cpustate); break;\
+ case 0x46: PREFIX86(_inc_si)(cpustate); break;\
+ case 0x47: PREFIX86(_inc_di)(cpustate); break;\
+ case 0x48: PREFIX86(_dec_ax)(cpustate); break;\
+ case 0x49: PREFIX86(_dec_cx)(cpustate); break;\
+ case 0x4a: PREFIX86(_dec_dx)(cpustate); break;\
+ case 0x4b: PREFIX86(_dec_bx)(cpustate); break;\
+ case 0x4c: PREFIX86(_dec_sp)(cpustate); break;\
+ case 0x4d: PREFIX86(_dec_bp)(cpustate); break;\
+ case 0x4e: PREFIX86(_dec_si)(cpustate); break;\
+ case 0x4f: PREFIX86(_dec_di)(cpustate); break;\
+ case 0x50: PREFIX86(_push_ax)(cpustate); break;\
+ case 0x51: PREFIX86(_push_cx)(cpustate); break;\
+ case 0x52: PREFIX86(_push_dx)(cpustate); break;\
+ case 0x53: PREFIX86(_push_bx)(cpustate); break;\
+ case 0x54: PREFIX86(_push_sp)(cpustate); break;\
+ case 0x55: PREFIX86(_push_bp)(cpustate); break;\
+ case 0x56: PREFIX86(_push_si)(cpustate); break;\
+ case 0x57: PREFIX86(_push_di)(cpustate); break;\
+ case 0x58: PREFIX86(_pop_ax)(cpustate); break;\
+ case 0x59: PREFIX86(_pop_cx)(cpustate); break;\
+ case 0x5a: PREFIX86(_pop_dx)(cpustate); break;\
+ case 0x5b: PREFIX86(_pop_bx)(cpustate); break;\
+ case 0x5c: PREFIX86(_pop_sp)(cpustate); break;\
+ case 0x5d: PREFIX86(_pop_bp)(cpustate); break;\
+ case 0x5e: PREFIX86(_pop_si)(cpustate); break;\
+ case 0x5f: PREFIX86(_pop_di)(cpustate); break;\
+ case 0x60: PREFIX186(_pusha)(cpustate); break;\
+ case 0x61: PREFIX186(_popa)(cpustate); break;\
+ case 0x62: PREFIX186(_bound)(cpustate); break;\
+ case 0x63: PREFIX86(_invalid)(cpustate); break;\
+ case 0x64: PREFIX86(_invalid)(cpustate); break;\
+ case 0x65: PREFIX86(_invalid)(cpustate); break;\
+ case 0x66: PREFIX86(_invalid)(cpustate); break;\
+ case 0x67: PREFIX86(_invalid)(cpustate); break;\
+ case 0x68: PREFIX186(_push_d16)(cpustate); break;\
+ case 0x69: PREFIX186(_imul_d16)(cpustate); break;\
+ case 0x6a: PREFIX186(_push_d8)(cpustate); break;\
+ case 0x6b: PREFIX186(_imul_d8)(cpustate); break;\
+ case 0x6c: PREFIX186(_insb)(cpustate); break;\
+ case 0x6d: PREFIX186(_insw)(cpustate); break;\
+ case 0x6e: PREFIX186(_outsb)(cpustate); break;\
+ case 0x6f: PREFIX186(_outsw)(cpustate); break;\
+ case 0x70: PREFIX86(_jo)(cpustate); break;\
+ case 0x71: PREFIX86(_jno)(cpustate); break;\
+ case 0x72: PREFIX86(_jb)(cpustate); break;\
+ case 0x73: PREFIX86(_jnb)(cpustate); break;\
+ case 0x74: PREFIX86(_jz)(cpustate); break;\
+ case 0x75: PREFIX86(_jnz)(cpustate); break;\
+ case 0x76: PREFIX86(_jbe)(cpustate); break;\
+ case 0x77: PREFIX86(_jnbe)(cpustate); break;\
+ case 0x78: PREFIX86(_js)(cpustate); break;\
+ case 0x79: PREFIX86(_jns)(cpustate); break;\
+ case 0x7a: PREFIX86(_jp)(cpustate); break;\
+ case 0x7b: PREFIX86(_jnp)(cpustate); break;\
+ case 0x7c: PREFIX86(_jl)(cpustate); break;\
+ case 0x7d: PREFIX86(_jnl)(cpustate); break;\
+ case 0x7e: PREFIX86(_jle)(cpustate); break;\
+ case 0x7f: PREFIX86(_jnle)(cpustate); break;\
+ case 0x80: PREFIX86(_80pre)(cpustate); break;\
+ case 0x81: PREFIX86(_81pre)(cpustate); break;\
+ case 0x82: PREFIX86(_82pre)(cpustate); break;\
+ case 0x83: PREFIX86(_83pre)(cpustate); break;\
+ case 0x84: PREFIX86(_test_br8)(cpustate); break;\
+ case 0x85: PREFIX86(_test_wr16)(cpustate); break;\
+ case 0x86: PREFIX86(_xchg_br8)(cpustate); break;\
+ case 0x87: PREFIX86(_xchg_wr16)(cpustate); break;\
+ case 0x88: PREFIX86(_mov_br8)(cpustate); break;\
+ case 0x89: PREFIX86(_mov_wr16)(cpustate); break;\
+ case 0x8a: PREFIX86(_mov_r8b)(cpustate); break;\
+ case 0x8b: PREFIX86(_mov_r16w)(cpustate); break;\
+ case 0x8c: PREFIX86(_mov_wsreg)(cpustate); break;\
+ case 0x8d: PREFIX86(_lea)(cpustate); break;\
+ case 0x8e: PREFIX86(_mov_sregw)(cpustate); break;\
+ case 0x8f: PREFIX86(_popw)(cpustate); break;\
+ case 0x90: PREFIX86(_nop)(cpustate); break;\
+ case 0x91: PREFIX86(_xchg_axcx)(cpustate); break;\
+ case 0x92: PREFIX86(_xchg_axdx)(cpustate); break;\
+ case 0x93: PREFIX86(_xchg_axbx)(cpustate); break;\
+ case 0x94: PREFIX86(_xchg_axsp)(cpustate); break;\
+ case 0x95: PREFIX86(_xchg_axbp)(cpustate); break;\
+ case 0x96: PREFIX86(_xchg_axsi)(cpustate); break;\
+ case 0x97: PREFIX86(_xchg_axdi)(cpustate); break;\
+ case 0x98: PREFIX86(_cbw)(cpustate); break;\
+ case 0x99: PREFIX86(_cwd)(cpustate); break;\
+ case 0x9a: PREFIX86(_call_far)(cpustate); break;\
+ case 0x9b: PREFIX86(_wait)(cpustate); break;\
+ case 0x9c: PREFIX86(_pushf)(cpustate); break;\
+ case 0x9d: PREFIX86(_popf)(cpustate); break;\
+ case 0x9e: PREFIX86(_sahf)(cpustate); break;\
+ case 0x9f: PREFIX86(_lahf)(cpustate); break;\
+ case 0xa0: PREFIX86(_mov_aldisp)(cpustate); break;\
+ case 0xa1: PREFIX86(_mov_axdisp)(cpustate); break;\
+ case 0xa2: PREFIX86(_mov_dispal)(cpustate); break;\
+ case 0xa3: PREFIX86(_mov_dispax)(cpustate); break;\
+ case 0xa4: PREFIX86(_movsb)(cpustate); break;\
+ case 0xa5: PREFIX86(_movsw)(cpustate); break;\
+ case 0xa6: PREFIX86(_cmpsb)(cpustate); break;\
+ case 0xa7: PREFIX86(_cmpsw)(cpustate); break;\
+ case 0xa8: PREFIX86(_test_ald8)(cpustate); break;\
+ case 0xa9: PREFIX86(_test_axd16)(cpustate); break;\
+ case 0xaa: PREFIX86(_stosb)(cpustate); break;\
+ case 0xab: PREFIX86(_stosw)(cpustate); break;\
+ case 0xac: PREFIX86(_lodsb)(cpustate); break;\
+ case 0xad: PREFIX86(_lodsw)(cpustate); break;\
+ case 0xae: PREFIX86(_scasb)(cpustate); break;\
+ case 0xaf: PREFIX86(_scasw)(cpustate); break;\
+ case 0xb0: PREFIX86(_mov_ald8)(cpustate); break;\
+ case 0xb1: PREFIX86(_mov_cld8)(cpustate); break;\
+ case 0xb2: PREFIX86(_mov_dld8)(cpustate); break;\
+ case 0xb3: PREFIX86(_mov_bld8)(cpustate); break;\
+ case 0xb4: PREFIX86(_mov_ahd8)(cpustate); break;\
+ case 0xb5: PREFIX86(_mov_chd8)(cpustate); break;\
+ case 0xb6: PREFIX86(_mov_dhd8)(cpustate); break;\
+ case 0xb7: PREFIX86(_mov_bhd8)(cpustate); break;\
+ case 0xb8: PREFIX86(_mov_axd16)(cpustate); break;\
+ case 0xb9: PREFIX86(_mov_cxd16)(cpustate); break;\
+ case 0xba: PREFIX86(_mov_dxd16)(cpustate); break;\
+ case 0xbb: PREFIX86(_mov_bxd16)(cpustate); break;\
+ case 0xbc: PREFIX86(_mov_spd16)(cpustate); break;\
+ case 0xbd: PREFIX86(_mov_bpd16)(cpustate); break;\
+ case 0xbe: PREFIX86(_mov_sid16)(cpustate); break;\
+ case 0xbf: PREFIX86(_mov_did16)(cpustate); break;\
+ case 0xc0: PREFIX186(_rotshft_bd8)(cpustate); break;\
+ case 0xc1: PREFIX186(_rotshft_wd8)(cpustate); break;\
+ case 0xc2: PREFIX86(_ret_d16)(cpustate); break;\
+ case 0xc3: PREFIX86(_ret)(cpustate); break;\
+ case 0xc4: PREFIX86(_les_dw)(cpustate); break;\
+ case 0xc5: PREFIX86(_lds_dw)(cpustate); break;\
+ case 0xc6: PREFIX86(_mov_bd8)(cpustate); break;\
+ case 0xc7: PREFIX86(_mov_wd16)(cpustate); break;\
+ case 0xc8: PREFIX186(_enter)(cpustate); break;\
+ case 0xc9: PREFIX186(_leave)(cpustate); break;\
+ case 0xca: PREFIX86(_retf_d16)(cpustate); break;\
+ case 0xcb: PREFIX86(_retf)(cpustate); break;\
+ case 0xcc: PREFIX86(_int3)(cpustate); break;\
+ case 0xcd: PREFIX86(_int)(cpustate); break;\
+ case 0xce: PREFIX86(_into)(cpustate); break;\
+ case 0xcf: PREFIX86(_iret)(cpustate); break;\
+ case 0xd0: PREFIX86(_rotshft_b)(cpustate); break;\
+ case 0xd1: PREFIX86(_rotshft_w)(cpustate); break;\
+ case 0xd2: PREFIX86(_rotshft_bcl)(cpustate); break;\
+ case 0xd3: PREFIX86(_rotshft_wcl)(cpustate); break;\
+ case 0xd4: PREFIX86(_aam)(cpustate); break;\
+ case 0xd5: PREFIX86(_aad)(cpustate); break;\
+ case 0xd6: PREFIX86(_invalid)(cpustate); break;\
+ case 0xd7: PREFIX86(_xlat)(cpustate); break;\
+ case 0xd8: PREFIX86(_escape)(cpustate); break;\
+ case 0xd9: PREFIX86(_escape)(cpustate); break;\
+ case 0xda: PREFIX86(_escape)(cpustate); break;\
+ case 0xdb: PREFIX86(_escape)(cpustate); break;\
+ case 0xdc: PREFIX86(_escape)(cpustate); break;\
+ case 0xdd: PREFIX86(_escape)(cpustate); break;\
+ case 0xde: PREFIX86(_escape)(cpustate); break;\
+ case 0xdf: PREFIX86(_escape)(cpustate); break;\
+ case 0xe0: PREFIX86(_loopne)(cpustate); break;\
+ case 0xe1: PREFIX86(_loope)(cpustate); break;\
+ case 0xe2: PREFIX86(_loop)(cpustate); break;\
+ case 0xe3: PREFIX86(_jcxz)(cpustate); break;\
+ case 0xe4: PREFIX86(_inal)(cpustate); break;\
+ case 0xe5: PREFIX86(_inax)(cpustate); break;\
+ case 0xe6: PREFIX86(_outal)(cpustate); break;\
+ case 0xe7: PREFIX86(_outax)(cpustate); break;\
+ case 0xe8: PREFIX86(_call_d16)(cpustate); break;\
+ case 0xe9: PREFIX86(_jmp_d16)(cpustate); break;\
+ case 0xea: PREFIX86(_jmp_far)(cpustate); break;\
+ case 0xeb: PREFIX86(_jmp_d8)(cpustate); break;\
+ case 0xec: PREFIX86(_inaldx)(cpustate); break;\
+ case 0xed: PREFIX86(_inaxdx)(cpustate); break;\
+ case 0xee: PREFIX86(_outdxal)(cpustate); break;\
+ case 0xef: PREFIX86(_outdxax)(cpustate); break;\
+ case 0xf0: PREFIX86(_lock)(cpustate); break;\
+ case 0xf1: PREFIX86(_invalid)(cpustate); break;\
+ case 0xf2: PREFIX186(_repne)(cpustate); break;\
+ case 0xf3: PREFIX186(_repe)(cpustate); break;\
+ case 0xf4: PREFIX86(_hlt)(cpustate); break;\
+ case 0xf5: PREFIX86(_cmc)(cpustate); break;\
+ case 0xf6: PREFIX86(_f6pre)(cpustate); break;\
+ case 0xf7: PREFIX86(_f7pre)(cpustate); break;\
+ case 0xf8: PREFIX86(_clc)(cpustate); break;\
+ case 0xf9: PREFIX86(_stc)(cpustate); break;\
+ case 0xfa: PREFIX86(_cli)(cpustate); break;\
+ case 0xfb: PREFIX86(_sti)(cpustate); break;\
+ case 0xfc: PREFIX86(_cld)(cpustate); break;\
+ case 0xfd: PREFIX86(_std)(cpustate); break;\
+ case 0xfe: PREFIX86(_fepre)(cpustate); break;\
+ case 0xff: PREFIX86(_ffpre)(cpustate); break;\
};
#else
-#define TABLE186 PREFIX186(_instruction)[FETCHOP]();
+#define TABLE186 PREFIX186(_instruction)[FETCHOP](cpustate);
#endif
diff --git a/src/emu/cpu/i86/table286.h b/src/emu/cpu/i86/table286.h
index b3dfac80eda..1b09b4ac191 100644
--- a/src/emu/cpu/i86/table286.h
+++ b/src/emu/cpu/i86/table286.h
@@ -3,7 +3,7 @@
* at the time the same like table186.h
*/
-static void (*const PREFIX286(_instruction)[256])(void) =
+static void (*const PREFIX286(_instruction)[256])(i8086_state *cpustate) =
{
PREFIX86(_add_br8), /* 0x00 */
PREFIX86(_add_wr16), /* 0x01 */
@@ -268,263 +268,263 @@ static void (*const PREFIX286(_instruction)[256])(void) =
#define TABLE286 \
switch(FETCHOP)\
{\
- case 0x00: PREFIX86(_add_br8)(); break;\
- case 0x01: PREFIX86(_add_wr16)(); break;\
- case 0x02: PREFIX86(_add_r8b)(); break;\
- case 0x03: PREFIX86(_add_r16w)(); break;\
- case 0x04: PREFIX86(_add_ald8)(); break;\
- case 0x05: PREFIX86(_add_axd16)(); break;\
- case 0x06: PREFIX86(_push_es)(); break;\
- case 0x07: PREFIX86(_pop_es)(); break;\
- case 0x08: PREFIX86(_or_br8)(); break;\
- case 0x09: PREFIX86(_or_wr16)(); break;\
- case 0x0a: PREFIX86(_or_r8b)(); break;\
- case 0x0b: PREFIX86(_or_r16w)(); break;\
- case 0x0c: PREFIX86(_or_ald8)(); break;\
- case 0x0d: PREFIX86(_or_axd16)(); break;\
- case 0x0e: PREFIX86(_push_cs)(); break;\
- case 0x0f: PREFIX286(_0fpre)(); break;\
- case 0x10: PREFIX86(_adc_br8)(); break;\
- case 0x11: PREFIX86(_adc_wr16)(); break;\
- case 0x12: PREFIX86(_adc_r8b)(); break;\
- case 0x13: PREFIX86(_adc_r16w)(); break;\
- case 0x14: PREFIX86(_adc_ald8)(); break;\
- case 0x15: PREFIX86(_adc_axd16)(); break;\
- case 0x16: PREFIX86(_push_ss)(); break;\
- case 0x17: PREFIX86(_pop_ss)(); break;\
- case 0x18: PREFIX86(_sbb_br8)(); break;\
- case 0x19: PREFIX86(_sbb_wr16)(); break;\
- case 0x1a: PREFIX86(_sbb_r8b)(); break;\
- case 0x1b: PREFIX86(_sbb_r16w)(); break;\
- case 0x1c: PREFIX86(_sbb_ald8)(); break;\
- case 0x1d: PREFIX86(_sbb_axd16)(); break;\
- case 0x1e: PREFIX86(_push_ds)(); break;\
- case 0x1f: PREFIX86(_pop_ds)(); break;\
- case 0x20: PREFIX86(_and_br8)(); break;\
- case 0x21: PREFIX86(_and_wr16)(); break;\
- case 0x22: PREFIX86(_and_r8b)(); break;\
- case 0x23: PREFIX86(_and_r16w)(); break;\
- case 0x24: PREFIX86(_and_ald8)(); break;\
- case 0x25: PREFIX86(_and_axd16)(); break;\
- case 0x26: PREFIX86(_es)(); break;\
- case 0x27: PREFIX86(_daa)(); break;\
- case 0x28: PREFIX86(_sub_br8)(); break;\
- case 0x29: PREFIX86(_sub_wr16)(); break;\
- case 0x2a: PREFIX86(_sub_r8b)(); break;\
- case 0x2b: PREFIX86(_sub_r16w)(); break;\
- case 0x2c: PREFIX86(_sub_ald8)(); break;\
- case 0x2d: PREFIX86(_sub_axd16)(); break;\
- case 0x2e: PREFIX86(_cs)(); break;\
- case 0x2f: PREFIX86(_das)(); break;\
- case 0x30: PREFIX86(_xor_br8)(); break;\
- case 0x31: PREFIX86(_xor_wr16)(); break;\
- case 0x32: PREFIX86(_xor_r8b)(); break;\
- case 0x33: PREFIX86(_xor_r16w)(); break;\
- case 0x34: PREFIX86(_xor_ald8)(); break;\
- case 0x35: PREFIX86(_xor_axd16)(); break;\
- case 0x36: PREFIX86(_ss)(); break;\
- case 0x37: PREFIX86(_aaa)(); break;\
- case 0x38: PREFIX86(_cmp_br8)(); break;\
- case 0x39: PREFIX86(_cmp_wr16)(); break;\
- case 0x3a: PREFIX86(_cmp_r8b)(); break;\
- case 0x3b: PREFIX86(_cmp_r16w)(); break;\
- case 0x3c: PREFIX86(_cmp_ald8)(); break;\
- case 0x3d: PREFIX86(_cmp_axd16)(); break;\
- case 0x3e: PREFIX86(_ds)(); break;\
- case 0x3f: PREFIX86(_aas)(); break;\
- case 0x40: PREFIX86(_inc_ax)(); break;\
- case 0x41: PREFIX86(_inc_cx)(); break;\
- case 0x42: PREFIX86(_inc_dx)(); break;\
- case 0x43: PREFIX86(_inc_bx)(); break;\
- case 0x44: PREFIX86(_inc_sp)(); break;\
- case 0x45: PREFIX86(_inc_bp)(); break;\
- case 0x46: PREFIX86(_inc_si)(); break;\
- case 0x47: PREFIX86(_inc_di)(); break;\
- case 0x48: PREFIX86(_dec_ax)(); break;\
- case 0x49: PREFIX86(_dec_cx)(); break;\
- case 0x4a: PREFIX86(_dec_dx)(); break;\
- case 0x4b: PREFIX86(_dec_bx)(); break;\
- case 0x4c: PREFIX86(_dec_sp)(); break;\
- case 0x4d: PREFIX86(_dec_bp)(); break;\
- case 0x4e: PREFIX86(_dec_si)(); break;\
- case 0x4f: PREFIX86(_dec_di)(); break;\
- case 0x50: PREFIX86(_push_ax)(); break;\
- case 0x51: PREFIX86(_push_cx)(); break;\
- case 0x52: PREFIX86(_push_dx)(); break;\
- case 0x53: PREFIX86(_push_bx)(); break;\
- case 0x54: PREFIX86(_push_sp)(); break;\
- case 0x55: PREFIX86(_push_bp)(); break;\
- case 0x56: PREFIX86(_push_si)(); break;\
- case 0x57: PREFIX86(_push_di)(); break;\
- case 0x58: PREFIX86(_pop_ax)(); break;\
- case 0x59: PREFIX86(_pop_cx)(); break;\
- case 0x5a: PREFIX86(_pop_dx)(); break;\
- case 0x5b: PREFIX86(_pop_bx)(); break;\
- case 0x5c: PREFIX86(_pop_sp)(); break;\
- case 0x5d: PREFIX86(_pop_bp)(); break;\
- case 0x5e: PREFIX86(_pop_si)(); break;\
- case 0x5f: PREFIX86(_pop_di)(); break;\
- case 0x60: PREFIX186(_pusha)(); break;\
- case 0x61: PREFIX186(_popa)(); break;\
- case 0x62: PREFIX186(_bound)(); break;\
- case 0x63: PREFIX286(_arpl)(); break;\
- case 0x64: PREFIX286(_invalid)(); break;\
- case 0x65: PREFIX286(_invalid)(); break;\
- case 0x66: PREFIX286(_invalid)(); break;\
- case 0x67: PREFIX286(_invalid)(); break;\
- case 0x68: PREFIX186(_push_d16)(); break;\
- case 0x69: PREFIX186(_imul_d16)(); break;\
- case 0x6a: PREFIX186(_push_d8)(); break;\
- case 0x6b: PREFIX186(_imul_d8)(); break;\
- case 0x6c: PREFIX186(_insb)(); break;\
- case 0x6d: PREFIX186(_insw)(); break;\
- case 0x6e: PREFIX186(_outsb)(); break;\
- case 0x6f: PREFIX186(_outsw)(); break;\
- case 0x70: PREFIX86(_jo)(); break;\
- case 0x71: PREFIX86(_jno)(); break;\
- case 0x72: PREFIX86(_jb)(); break;\
- case 0x73: PREFIX86(_jnb)(); break;\
- case 0x74: PREFIX86(_jz)(); break;\
- case 0x75: PREFIX86(_jnz)(); break;\
- case 0x76: PREFIX86(_jbe)(); break;\
- case 0x77: PREFIX86(_jnbe)(); break;\
- case 0x78: PREFIX86(_js)(); break;\
- case 0x79: PREFIX86(_jns)(); break;\
- case 0x7a: PREFIX86(_jp)(); break;\
- case 0x7b: PREFIX86(_jnp)(); break;\
- case 0x7c: PREFIX86(_jl)(); break;\
- case 0x7d: PREFIX86(_jnl)(); break;\
- case 0x7e: PREFIX86(_jle)(); break;\
- case 0x7f: PREFIX86(_jnle)(); break;\
- case 0x80: PREFIX86(_80pre)(); break;\
- case 0x81: PREFIX86(_81pre)(); break;\
- case 0x82: PREFIX86(_82pre)(); break;\
- case 0x83: PREFIX86(_83pre)(); break;\
- case 0x84: PREFIX86(_test_br8)(); break;\
- case 0x85: PREFIX86(_test_wr16)(); break;\
- case 0x86: PREFIX86(_xchg_br8)(); break;\
- case 0x87: PREFIX86(_xchg_wr16)(); break;\
- case 0x88: PREFIX86(_mov_br8)(); break;\
- case 0x89: PREFIX86(_mov_wr16)(); break;\
- case 0x8a: PREFIX86(_mov_r8b)(); break;\
- case 0x8b: PREFIX86(_mov_r16w)(); break;\
- case 0x8c: PREFIX86(_mov_wsreg)(); break;\
- case 0x8d: PREFIX86(_lea)(); break;\
- case 0x8e: PREFIX86(_mov_sregw)(); break;\
- case 0x8f: PREFIX86(_popw)(); break;\
- case 0x90: PREFIX86(_nop)(); break;\
- case 0x91: PREFIX86(_xchg_axcx)(); break;\
- case 0x92: PREFIX86(_xchg_axdx)(); break;\
- case 0x93: PREFIX86(_xchg_axbx)(); break;\
- case 0x94: PREFIX86(_xchg_axsp)(); break;\
- case 0x95: PREFIX86(_xchg_axbp)(); break;\
- case 0x96: PREFIX86(_xchg_axsi)(); break;\
- case 0x97: PREFIX86(_xchg_axdi)(); break;\
- case 0x98: PREFIX86(_cbw)(); break;\
- case 0x99: PREFIX86(_cwd)(); break;\
- case 0x9a: PREFIX86(_call_far)(); break;\
- case 0x9b: PREFIX86(_wait)(); break;\
- case 0x9c: PREFIX86(_pushf)(); break;\
- case 0x9d: PREFIX86(_popf)(); break;\
- case 0x9e: PREFIX86(_sahf)(); break;\
- case 0x9f: PREFIX86(_lahf)(); break;\
- case 0xa0: PREFIX86(_mov_aldisp)(); break;\
- case 0xa1: PREFIX86(_mov_axdisp)(); break;\
- case 0xa2: PREFIX86(_mov_dispal)(); break;\
- case 0xa3: PREFIX86(_mov_dispax)(); break;\
- case 0xa4: PREFIX86(_movsb)(); break;\
- case 0xa5: PREFIX86(_movsw)(); break;\
- case 0xa6: PREFIX86(_cmpsb)(); break;\
- case 0xa7: PREFIX86(_cmpsw)(); break;\
- case 0xa8: PREFIX86(_test_ald8)(); break;\
- case 0xa9: PREFIX86(_test_axd16)(); break;\
- case 0xaa: PREFIX86(_stosb)(); break;\
- case 0xab: PREFIX86(_stosw)(); break;\
- case 0xac: PREFIX86(_lodsb)(); break;\
- case 0xad: PREFIX86(_lodsw)(); break;\
- case 0xae: PREFIX86(_scasb)(); break;\
- case 0xaf: PREFIX86(_scasw)(); break;\
- case 0xb0: PREFIX86(_mov_ald8)(); break;\
- case 0xb1: PREFIX86(_mov_cld8)(); break;\
- case 0xb2: PREFIX86(_mov_dld8)(); break;\
- case 0xb3: PREFIX86(_mov_bld8)(); break;\
- case 0xb4: PREFIX86(_mov_ahd8)(); break;\
- case 0xb5: PREFIX86(_mov_chd8)(); break;\
- case 0xb6: PREFIX86(_mov_dhd8)(); break;\
- case 0xb7: PREFIX86(_mov_bhd8)(); break;\
- case 0xb8: PREFIX86(_mov_axd16)(); break;\
- case 0xb9: PREFIX86(_mov_cxd16)(); break;\
- case 0xba: PREFIX86(_mov_dxd16)(); break;\
- case 0xbb: PREFIX86(_mov_bxd16)(); break;\
- case 0xbc: PREFIX86(_mov_spd16)(); break;\
- case 0xbd: PREFIX86(_mov_bpd16)(); break;\
- case 0xbe: PREFIX86(_mov_sid16)(); break;\
- case 0xbf: PREFIX86(_mov_did16)(); break;\
- case 0xc0: PREFIX186(_rotshft_bd8)(); break;\
- case 0xc1: PREFIX186(_rotshft_wd8)(); break;\
- case 0xc2: PREFIX86(_ret_d16)(); break;\
- case 0xc3: PREFIX86(_ret)(); break;\
- case 0xc4: PREFIX86(_les_dw)(); break;\
- case 0xc5: PREFIX86(_lds_dw)(); break;\
- case 0xc6: PREFIX86(_mov_bd8)(); break;\
- case 0xc7: PREFIX86(_mov_wd16)(); break;\
- case 0xc8: PREFIX186(_enter)(); break;\
- case 0xc9: PREFIX186(_leave)(); break;\
- case 0xca: PREFIX86(_retf_d16)(); break;\
- case 0xcb: PREFIX86(_retf)(); break;\
- case 0xcc: PREFIX86(_int3)(); break;\
- case 0xcd: PREFIX86(_int)(); break;\
- case 0xce: PREFIX86(_into)(); break;\
- case 0xcf: PREFIX86(_iret)(); break;\
- case 0xd0: PREFIX86(_rotshft_b)(); break;\
- case 0xd1: PREFIX86(_rotshft_w)(); break;\
- case 0xd2: PREFIX86(_rotshft_bcl)(); break;\
- case 0xd3: PREFIX86(_rotshft_wcl)(); break;\
- case 0xd4: PREFIX86(_aam)(); break;\
- case 0xd5: PREFIX86(_aad)(); break;\
- case 0xd6: PREFIX286(_invalid)(); break;\
- case 0xd7: PREFIX86(_xlat)(); break;\
- case 0xd8: PREFIX86(_escape)(); break;\
- case 0xd9: PREFIX86(_escape)(); break;\
- case 0xda: PREFIX86(_escape)(); break;\
- case 0xdb: PREFIX86(_escape)(); break;\
- case 0xdc: PREFIX86(_escape)(); break;\
- case 0xdd: PREFIX86(_escape)(); break;\
- case 0xde: PREFIX86(_escape)(); break;\
- case 0xdf: PREFIX86(_escape)(); break;\
- case 0xe0: PREFIX86(_loopne)(); break;\
- case 0xe1: PREFIX86(_loope)(); break;\
- case 0xe2: PREFIX86(_loop)(); break;\
- case 0xe3: PREFIX86(_jcxz)(); break;\
- case 0xe4: PREFIX86(_inal)(); break;\
- case 0xe5: PREFIX86(_inax)(); break;\
- case 0xe6: PREFIX86(_outal)(); break;\
- case 0xe7: PREFIX86(_outax)(); break;\
- case 0xe8: PREFIX86(_call_d16)(); break;\
- case 0xe9: PREFIX86(_jmp_d16)(); break;\
- case 0xea: PREFIX86(_jmp_far)(); break;\
- case 0xeb: PREFIX86(_jmp_d8)(); break;\
- case 0xec: PREFIX86(_inaldx)(); break;\
- case 0xed: PREFIX86(_inaxdx)(); break;\
- case 0xee: PREFIX86(_outdxal)(); break;\
- case 0xef: PREFIX86(_outdxax)(); break;\
- case 0xf0: PREFIX86(_lock)(); break;\
- case 0xf1: PREFIX286(_invalid)(); break;\
- case 0xf2: PREFIX186(_repne)(); break;\
- case 0xf3: PREFIX186(_repe)(); break;\
- case 0xf4: PREFIX86(_hlt)(); break;\
- case 0xf5: PREFIX86(_cmc)(); break;\
- case 0xf6: PREFIX86(_f6pre)(); break;\
- case 0xf7: PREFIX86(_f7pre)(); break;\
- case 0xf8: PREFIX86(_clc)(); break;\
- case 0xf9: PREFIX86(_stc)(); break;\
- case 0xfa: PREFIX86(_cli)(); break;\
- case 0xfb: PREFIX86(_sti)(); break;\
- case 0xfc: PREFIX86(_cld)(); break;\
- case 0xfd: PREFIX86(_std)(); break;\
- case 0xfe: PREFIX86(_fepre)(); break;\
- case 0xff: PREFIX86(_ffpre)(); break;\
+ case 0x00: PREFIX86(_add_br8)(cpustate); break;\
+ case 0x01: PREFIX86(_add_wr16)(cpustate); break;\
+ case 0x02: PREFIX86(_add_r8b)(cpustate); break;\
+ case 0x03: PREFIX86(_add_r16w)(cpustate); break;\
+ case 0x04: PREFIX86(_add_ald8)(cpustate); break;\
+ case 0x05: PREFIX86(_add_axd16)(cpustate); break;\
+ case 0x06: PREFIX86(_push_es)(cpustate); break;\
+ case 0x07: PREFIX86(_pop_es)(cpustate); break;\
+ case 0x08: PREFIX86(_or_br8)(cpustate); break;\
+ case 0x09: PREFIX86(_or_wr16)(cpustate); break;\
+ case 0x0a: PREFIX86(_or_r8b)(cpustate); break;\
+ case 0x0b: PREFIX86(_or_r16w)(cpustate); break;\
+ case 0x0c: PREFIX86(_or_ald8)(cpustate); break;\
+ case 0x0d: PREFIX86(_or_axd16)(cpustate); break;\
+ case 0x0e: PREFIX86(_push_cs)(cpustate); break;\
+ case 0x0f: PREFIX286(_0fpre)(cpustate); break;\
+ case 0x10: PREFIX86(_adc_br8)(cpustate); break;\
+ case 0x11: PREFIX86(_adc_wr16)(cpustate); break;\
+ case 0x12: PREFIX86(_adc_r8b)(cpustate); break;\
+ case 0x13: PREFIX86(_adc_r16w)(cpustate); break;\
+ case 0x14: PREFIX86(_adc_ald8)(cpustate); break;\
+ case 0x15: PREFIX86(_adc_axd16)(cpustate); break;\
+ case 0x16: PREFIX86(_push_ss)(cpustate); break;\
+ case 0x17: PREFIX86(_pop_ss)(cpustate); break;\
+ case 0x18: PREFIX86(_sbb_br8)(cpustate); break;\
+ case 0x19: PREFIX86(_sbb_wr16)(cpustate); break;\
+ case 0x1a: PREFIX86(_sbb_r8b)(cpustate); break;\
+ case 0x1b: PREFIX86(_sbb_r16w)(cpustate); break;\
+ case 0x1c: PREFIX86(_sbb_ald8)(cpustate); break;\
+ case 0x1d: PREFIX86(_sbb_axd16)(cpustate); break;\
+ case 0x1e: PREFIX86(_push_ds)(cpustate); break;\
+ case 0x1f: PREFIX86(_pop_ds)(cpustate); break;\
+ case 0x20: PREFIX86(_and_br8)(cpustate); break;\
+ case 0x21: PREFIX86(_and_wr16)(cpustate); break;\
+ case 0x22: PREFIX86(_and_r8b)(cpustate); break;\
+ case 0x23: PREFIX86(_and_r16w)(cpustate); break;\
+ case 0x24: PREFIX86(_and_ald8)(cpustate); break;\
+ case 0x25: PREFIX86(_and_axd16)(cpustate); break;\
+ case 0x26: PREFIX86(_es)(cpustate); break;\
+ case 0x27: PREFIX86(_daa)(cpustate); break;\
+ case 0x28: PREFIX86(_sub_br8)(cpustate); break;\
+ case 0x29: PREFIX86(_sub_wr16)(cpustate); break;\
+ case 0x2a: PREFIX86(_sub_r8b)(cpustate); break;\
+ case 0x2b: PREFIX86(_sub_r16w)(cpustate); break;\
+ case 0x2c: PREFIX86(_sub_ald8)(cpustate); break;\
+ case 0x2d: PREFIX86(_sub_axd16)(cpustate); break;\
+ case 0x2e: PREFIX86(_cs)(cpustate); break;\
+ case 0x2f: PREFIX86(_das)(cpustate); break;\
+ case 0x30: PREFIX86(_xor_br8)(cpustate); break;\
+ case 0x31: PREFIX86(_xor_wr16)(cpustate); break;\
+ case 0x32: PREFIX86(_xor_r8b)(cpustate); break;\
+ case 0x33: PREFIX86(_xor_r16w)(cpustate); break;\
+ case 0x34: PREFIX86(_xor_ald8)(cpustate); break;\
+ case 0x35: PREFIX86(_xor_axd16)(cpustate); break;\
+ case 0x36: PREFIX86(_ss)(cpustate); break;\
+ case 0x37: PREFIX86(_aaa)(cpustate); break;\
+ case 0x38: PREFIX86(_cmp_br8)(cpustate); break;\
+ case 0x39: PREFIX86(_cmp_wr16)(cpustate); break;\
+ case 0x3a: PREFIX86(_cmp_r8b)(cpustate); break;\
+ case 0x3b: PREFIX86(_cmp_r16w)(cpustate); break;\
+ case 0x3c: PREFIX86(_cmp_ald8)(cpustate); break;\
+ case 0x3d: PREFIX86(_cmp_axd16)(cpustate); break;\
+ case 0x3e: PREFIX86(_ds)(cpustate); break;\
+ case 0x3f: PREFIX86(_aas)(cpustate); break;\
+ case 0x40: PREFIX86(_inc_ax)(cpustate); break;\
+ case 0x41: PREFIX86(_inc_cx)(cpustate); break;\
+ case 0x42: PREFIX86(_inc_dx)(cpustate); break;\
+ case 0x43: PREFIX86(_inc_bx)(cpustate); break;\
+ case 0x44: PREFIX86(_inc_sp)(cpustate); break;\
+ case 0x45: PREFIX86(_inc_bp)(cpustate); break;\
+ case 0x46: PREFIX86(_inc_si)(cpustate); break;\
+ case 0x47: PREFIX86(_inc_di)(cpustate); break;\
+ case 0x48: PREFIX86(_dec_ax)(cpustate); break;\
+ case 0x49: PREFIX86(_dec_cx)(cpustate); break;\
+ case 0x4a: PREFIX86(_dec_dx)(cpustate); break;\
+ case 0x4b: PREFIX86(_dec_bx)(cpustate); break;\
+ case 0x4c: PREFIX86(_dec_sp)(cpustate); break;\
+ case 0x4d: PREFIX86(_dec_bp)(cpustate); break;\
+ case 0x4e: PREFIX86(_dec_si)(cpustate); break;\
+ case 0x4f: PREFIX86(_dec_di)(cpustate); break;\
+ case 0x50: PREFIX86(_push_ax)(cpustate); break;\
+ case 0x51: PREFIX86(_push_cx)(cpustate); break;\
+ case 0x52: PREFIX86(_push_dx)(cpustate); break;\
+ case 0x53: PREFIX86(_push_bx)(cpustate); break;\
+ case 0x54: PREFIX86(_push_sp)(cpustate); break;\
+ case 0x55: PREFIX86(_push_bp)(cpustate); break;\
+ case 0x56: PREFIX86(_push_si)(cpustate); break;\
+ case 0x57: PREFIX86(_push_di)(cpustate); break;\
+ case 0x58: PREFIX86(_pop_ax)(cpustate); break;\
+ case 0x59: PREFIX86(_pop_cx)(cpustate); break;\
+ case 0x5a: PREFIX86(_pop_dx)(cpustate); break;\
+ case 0x5b: PREFIX86(_pop_bx)(cpustate); break;\
+ case 0x5c: PREFIX86(_pop_sp)(cpustate); break;\
+ case 0x5d: PREFIX86(_pop_bp)(cpustate); break;\
+ case 0x5e: PREFIX86(_pop_si)(cpustate); break;\
+ case 0x5f: PREFIX86(_pop_di)(cpustate); break;\
+ case 0x60: PREFIX186(_pusha)(cpustate); break;\
+ case 0x61: PREFIX186(_popa)(cpustate); break;\
+ case 0x62: PREFIX186(_bound)(cpustate); break;\
+ case 0x63: PREFIX286(_arpl)(cpustate); break;\
+ case 0x64: PREFIX286(_invalid)(cpustate); break;\
+ case 0x65: PREFIX286(_invalid)(cpustate); break;\
+ case 0x66: PREFIX286(_invalid)(cpustate); break;\
+ case 0x67: PREFIX286(_invalid)(cpustate); break;\
+ case 0x68: PREFIX186(_push_d16)(cpustate); break;\
+ case 0x69: PREFIX186(_imul_d16)(cpustate); break;\
+ case 0x6a: PREFIX186(_push_d8)(cpustate); break;\
+ case 0x6b: PREFIX186(_imul_d8)(cpustate); break;\
+ case 0x6c: PREFIX186(_insb)(cpustate); break;\
+ case 0x6d: PREFIX186(_insw)(cpustate); break;\
+ case 0x6e: PREFIX186(_outsb)(cpustate); break;\
+ case 0x6f: PREFIX186(_outsw)(cpustate); break;\
+ case 0x70: PREFIX86(_jo)(cpustate); break;\
+ case 0x71: PREFIX86(_jno)(cpustate); break;\
+ case 0x72: PREFIX86(_jb)(cpustate); break;\
+ case 0x73: PREFIX86(_jnb)(cpustate); break;\
+ case 0x74: PREFIX86(_jz)(cpustate); break;\
+ case 0x75: PREFIX86(_jnz)(cpustate); break;\
+ case 0x76: PREFIX86(_jbe)(cpustate); break;\
+ case 0x77: PREFIX86(_jnbe)(cpustate); break;\
+ case 0x78: PREFIX86(_js)(cpustate); break;\
+ case 0x79: PREFIX86(_jns)(cpustate); break;\
+ case 0x7a: PREFIX86(_jp)(cpustate); break;\
+ case 0x7b: PREFIX86(_jnp)(cpustate); break;\
+ case 0x7c: PREFIX86(_jl)(cpustate); break;\
+ case 0x7d: PREFIX86(_jnl)(cpustate); break;\
+ case 0x7e: PREFIX86(_jle)(cpustate); break;\
+ case 0x7f: PREFIX86(_jnle)(cpustate); break;\
+ case 0x80: PREFIX86(_80pre)(cpustate); break;\
+ case 0x81: PREFIX86(_81pre)(cpustate); break;\
+ case 0x82: PREFIX86(_82pre)(cpustate); break;\
+ case 0x83: PREFIX86(_83pre)(cpustate); break;\
+ case 0x84: PREFIX86(_test_br8)(cpustate); break;\
+ case 0x85: PREFIX86(_test_wr16)(cpustate); break;\
+ case 0x86: PREFIX86(_xchg_br8)(cpustate); break;\
+ case 0x87: PREFIX86(_xchg_wr16)(cpustate); break;\
+ case 0x88: PREFIX86(_mov_br8)(cpustate); break;\
+ case 0x89: PREFIX86(_mov_wr16)(cpustate); break;\
+ case 0x8a: PREFIX86(_mov_r8b)(cpustate); break;\
+ case 0x8b: PREFIX86(_mov_r16w)(cpustate); break;\
+ case 0x8c: PREFIX86(_mov_wsreg)(cpustate); break;\
+ case 0x8d: PREFIX86(_lea)(cpustate); break;\
+ case 0x8e: PREFIX86(_mov_sregw)(cpustate); break;\
+ case 0x8f: PREFIX86(_popw)(cpustate); break;\
+ case 0x90: PREFIX86(_nop)(cpustate); break;\
+ case 0x91: PREFIX86(_xchg_axcx)(cpustate); break;\
+ case 0x92: PREFIX86(_xchg_axdx)(cpustate); break;\
+ case 0x93: PREFIX86(_xchg_axbx)(cpustate); break;\
+ case 0x94: PREFIX86(_xchg_axsp)(cpustate); break;\
+ case 0x95: PREFIX86(_xchg_axbp)(cpustate); break;\
+ case 0x96: PREFIX86(_xchg_axsi)(cpustate); break;\
+ case 0x97: PREFIX86(_xchg_axdi)(cpustate); break;\
+ case 0x98: PREFIX86(_cbw)(cpustate); break;\
+ case 0x99: PREFIX86(_cwd)(cpustate); break;\
+ case 0x9a: PREFIX86(_call_far)(cpustate); break;\
+ case 0x9b: PREFIX86(_wait)(cpustate); break;\
+ case 0x9c: PREFIX86(_pushf)(cpustate); break;\
+ case 0x9d: PREFIX86(_popf)(cpustate); break;\
+ case 0x9e: PREFIX86(_sahf)(cpustate); break;\
+ case 0x9f: PREFIX86(_lahf)(cpustate); break;\
+ case 0xa0: PREFIX86(_mov_aldisp)(cpustate); break;\
+ case 0xa1: PREFIX86(_mov_axdisp)(cpustate); break;\
+ case 0xa2: PREFIX86(_mov_dispal)(cpustate); break;\
+ case 0xa3: PREFIX86(_mov_dispax)(cpustate); break;\
+ case 0xa4: PREFIX86(_movsb)(cpustate); break;\
+ case 0xa5: PREFIX86(_movsw)(cpustate); break;\
+ case 0xa6: PREFIX86(_cmpsb)(cpustate); break;\
+ case 0xa7: PREFIX86(_cmpsw)(cpustate); break;\
+ case 0xa8: PREFIX86(_test_ald8)(cpustate); break;\
+ case 0xa9: PREFIX86(_test_axd16)(cpustate); break;\
+ case 0xaa: PREFIX86(_stosb)(cpustate); break;\
+ case 0xab: PREFIX86(_stosw)(cpustate); break;\
+ case 0xac: PREFIX86(_lodsb)(cpustate); break;\
+ case 0xad: PREFIX86(_lodsw)(cpustate); break;\
+ case 0xae: PREFIX86(_scasb)(cpustate); break;\
+ case 0xaf: PREFIX86(_scasw)(cpustate); break;\
+ case 0xb0: PREFIX86(_mov_ald8)(cpustate); break;\
+ case 0xb1: PREFIX86(_mov_cld8)(cpustate); break;\
+ case 0xb2: PREFIX86(_mov_dld8)(cpustate); break;\
+ case 0xb3: PREFIX86(_mov_bld8)(cpustate); break;\
+ case 0xb4: PREFIX86(_mov_ahd8)(cpustate); break;\
+ case 0xb5: PREFIX86(_mov_chd8)(cpustate); break;\
+ case 0xb6: PREFIX86(_mov_dhd8)(cpustate); break;\
+ case 0xb7: PREFIX86(_mov_bhd8)(cpustate); break;\
+ case 0xb8: PREFIX86(_mov_axd16)(cpustate); break;\
+ case 0xb9: PREFIX86(_mov_cxd16)(cpustate); break;\
+ case 0xba: PREFIX86(_mov_dxd16)(cpustate); break;\
+ case 0xbb: PREFIX86(_mov_bxd16)(cpustate); break;\
+ case 0xbc: PREFIX86(_mov_spd16)(cpustate); break;\
+ case 0xbd: PREFIX86(_mov_bpd16)(cpustate); break;\
+ case 0xbe: PREFIX86(_mov_sid16)(cpustate); break;\
+ case 0xbf: PREFIX86(_mov_did16)(cpustate); break;\
+ case 0xc0: PREFIX186(_rotshft_bd8)(cpustate); break;\
+ case 0xc1: PREFIX186(_rotshft_wd8)(cpustate); break;\
+ case 0xc2: PREFIX86(_ret_d16)(cpustate); break;\
+ case 0xc3: PREFIX86(_ret)(cpustate); break;\
+ case 0xc4: PREFIX86(_les_dw)(cpustate); break;\
+ case 0xc5: PREFIX86(_lds_dw)(cpustate); break;\
+ case 0xc6: PREFIX86(_mov_bd8)(cpustate); break;\
+ case 0xc7: PREFIX86(_mov_wd16)(cpustate); break;\
+ case 0xc8: PREFIX186(_enter)(cpustate); break;\
+ case 0xc9: PREFIX186(_leave)(cpustate); break;\
+ case 0xca: PREFIX86(_retf_d16)(cpustate); break;\
+ case 0xcb: PREFIX86(_retf)(cpustate); break;\
+ case 0xcc: PREFIX86(_int3)(cpustate); break;\
+ case 0xcd: PREFIX86(_int)(cpustate); break;\
+ case 0xce: PREFIX86(_into)(cpustate); break;\
+ case 0xcf: PREFIX86(_iret)(cpustate); break;\
+ case 0xd0: PREFIX86(_rotshft_b)(cpustate); break;\
+ case 0xd1: PREFIX86(_rotshft_w)(cpustate); break;\
+ case 0xd2: PREFIX86(_rotshft_bcl)(cpustate); break;\
+ case 0xd3: PREFIX86(_rotshft_wcl)(cpustate); break;\
+ case 0xd4: PREFIX86(_aam)(cpustate); break;\
+ case 0xd5: PREFIX86(_aad)(cpustate); break;\
+ case 0xd6: PREFIX286(_invalid)(cpustate); break;\
+ case 0xd7: PREFIX86(_xlat)(cpustate); break;\
+ case 0xd8: PREFIX86(_escape)(cpustate); break;\
+ case 0xd9: PREFIX86(_escape)(cpustate); break;\
+ case 0xda: PREFIX86(_escape)(cpustate); break;\
+ case 0xdb: PREFIX86(_escape)(cpustate); break;\
+ case 0xdc: PREFIX86(_escape)(cpustate); break;\
+ case 0xdd: PREFIX86(_escape)(cpustate); break;\
+ case 0xde: PREFIX86(_escape)(cpustate); break;\
+ case 0xdf: PREFIX86(_escape)(cpustate); break;\
+ case 0xe0: PREFIX86(_loopne)(cpustate); break;\
+ case 0xe1: PREFIX86(_loope)(cpustate); break;\
+ case 0xe2: PREFIX86(_loop)(cpustate); break;\
+ case 0xe3: PREFIX86(_jcxz)(cpustate); break;\
+ case 0xe4: PREFIX86(_inal)(cpustate); break;\
+ case 0xe5: PREFIX86(_inax)(cpustate); break;\
+ case 0xe6: PREFIX86(_outal)(cpustate); break;\
+ case 0xe7: PREFIX86(_outax)(cpustate); break;\
+ case 0xe8: PREFIX86(_call_d16)(cpustate); break;\
+ case 0xe9: PREFIX86(_jmp_d16)(cpustate); break;\
+ case 0xea: PREFIX86(_jmp_far)(cpustate); break;\
+ case 0xeb: PREFIX86(_jmp_d8)(cpustate); break;\
+ case 0xec: PREFIX86(_inaldx)(cpustate); break;\
+ case 0xed: PREFIX86(_inaxdx)(cpustate); break;\
+ case 0xee: PREFIX86(_outdxal)(cpustate); break;\
+ case 0xef: PREFIX86(_outdxax)(cpustate); break;\
+ case 0xf0: PREFIX86(_lock)(cpustate); break;\
+ case 0xf1: PREFIX286(_invalid)(cpustate); break;\
+ case 0xf2: PREFIX186(_repne)(cpustate); break;\
+ case 0xf3: PREFIX186(_repe)(cpustate); break;\
+ case 0xf4: PREFIX86(_hlt)(cpustate); break;\
+ case 0xf5: PREFIX86(_cmc)(cpustate); break;\
+ case 0xf6: PREFIX86(_f6pre)(cpustate); break;\
+ case 0xf7: PREFIX86(_f7pre)(cpustate); break;\
+ case 0xf8: PREFIX86(_clc)(cpustate); break;\
+ case 0xf9: PREFIX86(_stc)(cpustate); break;\
+ case 0xfa: PREFIX86(_cli)(cpustate); break;\
+ case 0xfb: PREFIX86(_sti)(cpustate); break;\
+ case 0xfc: PREFIX86(_cld)(cpustate); break;\
+ case 0xfd: PREFIX86(_std)(cpustate); break;\
+ case 0xfe: PREFIX86(_fepre)(cpustate); break;\
+ case 0xff: PREFIX86(_ffpre)(cpustate); break;\
};
#else
-#define TABLE286 PREFIX286(_instruction)[FETCHOP]();
+#define TABLE286 PREFIX286(_instruction)[FETCHOP](cpustate);
#endif
diff --git a/src/emu/cpu/i86/table86.h b/src/emu/cpu/i86/table86.h
index 1038501bd03..21619b54a55 100644
--- a/src/emu/cpu/i86/table86.h
+++ b/src/emu/cpu/i86/table86.h
@@ -1,4 +1,4 @@
-static void (*const PREFIX86(_instruction)[256])(void) =
+static void (*const PREFIX86(_instruction)[256])(i8086_state *cpustate) =
{
PREFIX86(_add_br8), /* 0x00 */
PREFIX86(_add_wr16), /* 0x01 */
@@ -263,263 +263,263 @@ static void (*const PREFIX86(_instruction)[256])(void) =
#define TABLE86 \
switch(FETCHOP)\
{\
- case 0x00: PREFIX86(_add_br8)(); break;\
- case 0x01: PREFIX86(_add_wr16)(); break;\
- case 0x02: PREFIX86(_add_r8b)(); break;\
- case 0x03: PREFIX86(_add_r16w)(); break;\
- case 0x04: PREFIX86(_add_ald8)(); break;\
- case 0x05: PREFIX86(_add_axd16)(); break;\
- case 0x06: PREFIX86(_push_es)(); break;\
- case 0x07: PREFIX86(_pop_es)(); break;\
- case 0x08: PREFIX86(_or_br8)(); break;\
- case 0x09: PREFIX86(_or_wr16)(); break;\
- case 0x0a: PREFIX86(_or_r8b)(); break;\
- case 0x0b: PREFIX86(_or_r16w)(); break;\
- case 0x0c: PREFIX86(_or_ald8)(); break;\
- case 0x0d: PREFIX86(_or_axd16)(); break;\
- case 0x0e: PREFIX86(_push_cs)(); break;\
- case 0x0f: PREFIX86(_invalid)(); break;\
- case 0x10: PREFIX86(_adc_br8)(); break;\
- case 0x11: PREFIX86(_adc_wr16)(); break;\
- case 0x12: PREFIX86(_adc_r8b)(); break;\
- case 0x13: PREFIX86(_adc_r16w)(); break;\
- case 0x14: PREFIX86(_adc_ald8)(); break;\
- case 0x15: PREFIX86(_adc_axd16)(); break;\
- case 0x16: PREFIX86(_push_ss)(); break;\
- case 0x17: PREFIX86(_pop_ss)(); break;\
- case 0x18: PREFIX86(_sbb_br8)(); break;\
- case 0x19: PREFIX86(_sbb_wr16)(); break;\
- case 0x1a: PREFIX86(_sbb_r8b)(); break;\
- case 0x1b: PREFIX86(_sbb_r16w)(); break;\
- case 0x1c: PREFIX86(_sbb_ald8)(); break;\
- case 0x1d: PREFIX86(_sbb_axd16)(); break;\
- case 0x1e: PREFIX86(_push_ds)(); break;\
- case 0x1f: PREFIX86(_pop_ds)(); break;\
- case 0x20: PREFIX86(_and_br8)(); break;\
- case 0x21: PREFIX86(_and_wr16)(); break;\
- case 0x22: PREFIX86(_and_r8b)(); break;\
- case 0x23: PREFIX86(_and_r16w)(); break;\
- case 0x24: PREFIX86(_and_ald8)(); break;\
- case 0x25: PREFIX86(_and_axd16)(); break;\
- case 0x26: PREFIX86(_es)(); break;\
- case 0x27: PREFIX86(_daa)(); break;\
- case 0x28: PREFIX86(_sub_br8)(); break;\
- case 0x29: PREFIX86(_sub_wr16)(); break;\
- case 0x2a: PREFIX86(_sub_r8b)(); break;\
- case 0x2b: PREFIX86(_sub_r16w)(); break;\
- case 0x2c: PREFIX86(_sub_ald8)(); break;\
- case 0x2d: PREFIX86(_sub_axd16)(); break;\
- case 0x2e: PREFIX86(_cs)(); break;\
- case 0x2f: PREFIX86(_das)(); break;\
- case 0x30: PREFIX86(_xor_br8)(); break;\
- case 0x31: PREFIX86(_xor_wr16)(); break;\
- case 0x32: PREFIX86(_xor_r8b)(); break;\
- case 0x33: PREFIX86(_xor_r16w)(); break;\
- case 0x34: PREFIX86(_xor_ald8)(); break;\
- case 0x35: PREFIX86(_xor_axd16)(); break;\
- case 0x36: PREFIX86(_ss)(); break;\
- case 0x37: PREFIX86(_aaa)(); break;\
- case 0x38: PREFIX86(_cmp_br8)(); break;\
- case 0x39: PREFIX86(_cmp_wr16)(); break;\
- case 0x3a: PREFIX86(_cmp_r8b)(); break;\
- case 0x3b: PREFIX86(_cmp_r16w)(); break;\
- case 0x3c: PREFIX86(_cmp_ald8)(); break;\
- case 0x3d: PREFIX86(_cmp_axd16)(); break;\
- case 0x3e: PREFIX86(_ds)(); break;\
- case 0x3f: PREFIX86(_aas)(); break;\
- case 0x40: PREFIX86(_inc_ax)(); break;\
- case 0x41: PREFIX86(_inc_cx)(); break;\
- case 0x42: PREFIX86(_inc_dx)(); break;\
- case 0x43: PREFIX86(_inc_bx)(); break;\
- case 0x44: PREFIX86(_inc_sp)(); break;\
- case 0x45: PREFIX86(_inc_bp)(); break;\
- case 0x46: PREFIX86(_inc_si)(); break;\
- case 0x47: PREFIX86(_inc_di)(); break;\
- case 0x48: PREFIX86(_dec_ax)(); break;\
- case 0x49: PREFIX86(_dec_cx)(); break;\
- case 0x4a: PREFIX86(_dec_dx)(); break;\
- case 0x4b: PREFIX86(_dec_bx)(); break;\
- case 0x4c: PREFIX86(_dec_sp)(); break;\
- case 0x4d: PREFIX86(_dec_bp)(); break;\
- case 0x4e: PREFIX86(_dec_si)(); break;\
- case 0x4f: PREFIX86(_dec_di)(); break;\
- case 0x50: PREFIX86(_push_ax)(); break;\
- case 0x51: PREFIX86(_push_cx)(); break;\
- case 0x52: PREFIX86(_push_dx)(); break;\
- case 0x53: PREFIX86(_push_bx)(); break;\
- case 0x54: PREFIX86(_push_sp)(); break;\
- case 0x55: PREFIX86(_push_bp)(); break;\
- case 0x56: PREFIX86(_push_si)(); break;\
- case 0x57: PREFIX86(_push_di)(); break;\
- case 0x58: PREFIX86(_pop_ax)(); break;\
- case 0x59: PREFIX86(_pop_cx)(); break;\
- case 0x5a: PREFIX86(_pop_dx)(); break;\
- case 0x5b: PREFIX86(_pop_bx)(); break;\
- case 0x5c: PREFIX86(_pop_sp)(); break;\
- case 0x5d: PREFIX86(_pop_bp)(); break;\
- case 0x5e: PREFIX86(_pop_si)(); break;\
- case 0x5f: PREFIX86(_pop_di)(); break;\
- case 0x60: PREFIX86(_invalid)(); break;\
- case 0x61: PREFIX86(_invalid)(); break;\
- case 0x62: PREFIX86(_invalid)(); break;\
- case 0x63: PREFIX86(_invalid)(); break;\
- case 0x64: PREFIX86(_invalid)(); break;\
- case 0x65: PREFIX86(_invalid)(); break;\
- case 0x66: PREFIX86(_invalid)(); break;\
- case 0x67: PREFIX86(_invalid)(); break;\
- case 0x68: PREFIX86(_invalid)(); break;\
- case 0x69: PREFIX86(_invalid)(); break;\
- case 0x6a: PREFIX86(_invalid)(); break;\
- case 0x6b: PREFIX86(_invalid)(); break;\
- case 0x6c: PREFIX86(_invalid)(); break;\
- case 0x6d: PREFIX86(_invalid)(); break;\
- case 0x6e: PREFIX86(_invalid)(); break;\
- case 0x6f: PREFIX86(_invalid)(); break;\
- case 0x70: PREFIX86(_jo)(); break;\
- case 0x71: PREFIX86(_jno)(); break;\
- case 0x72: PREFIX86(_jb)(); break;\
- case 0x73: PREFIX86(_jnb)(); break;\
- case 0x74: PREFIX86(_jz)(); break;\
- case 0x75: PREFIX86(_jnz)(); break;\
- case 0x76: PREFIX86(_jbe)(); break;\
- case 0x77: PREFIX86(_jnbe)(); break;\
- case 0x78: PREFIX86(_js)(); break;\
- case 0x79: PREFIX86(_jns)(); break;\
- case 0x7a: PREFIX86(_jp)(); break;\
- case 0x7b: PREFIX86(_jnp)(); break;\
- case 0x7c: PREFIX86(_jl)(); break;\
- case 0x7d: PREFIX86(_jnl)(); break;\
- case 0x7e: PREFIX86(_jle)(); break;\
- case 0x7f: PREFIX86(_jnle)(); break;\
- case 0x80: PREFIX86(_80pre)(); break;\
- case 0x81: PREFIX86(_81pre)(); break;\
- case 0x82: PREFIX86(_82pre)(); break;\
- case 0x83: PREFIX86(_83pre)(); break;\
- case 0x84: PREFIX86(_test_br8)(); break;\
- case 0x85: PREFIX86(_test_wr16)(); break;\
- case 0x86: PREFIX86(_xchg_br8)(); break;\
- case 0x87: PREFIX86(_xchg_wr16)(); break;\
- case 0x88: PREFIX86(_mov_br8)(); break;\
- case 0x89: PREFIX86(_mov_wr16)(); break;\
- case 0x8a: PREFIX86(_mov_r8b)(); break;\
- case 0x8b: PREFIX86(_mov_r16w)(); break;\
- case 0x8c: PREFIX86(_mov_wsreg)(); break;\
- case 0x8d: PREFIX86(_lea)(); break;\
- case 0x8e: PREFIX86(_mov_sregw)(); break;\
- case 0x8f: PREFIX86(_popw)(); break;\
- case 0x90: PREFIX86(_nop)(); break;\
- case 0x91: PREFIX86(_xchg_axcx)(); break;\
- case 0x92: PREFIX86(_xchg_axdx)(); break;\
- case 0x93: PREFIX86(_xchg_axbx)(); break;\
- case 0x94: PREFIX86(_xchg_axsp)(); break;\
- case 0x95: PREFIX86(_xchg_axbp)(); break;\
- case 0x96: PREFIX86(_xchg_axsi)(); break;\
- case 0x97: PREFIX86(_xchg_axdi)(); break;\
- case 0x98: PREFIX86(_cbw)(); break;\
- case 0x99: PREFIX86(_cwd)(); break;\
- case 0x9a: PREFIX86(_call_far)(); break;\
- case 0x9b: PREFIX86(_wait)(); break;\
- case 0x9c: PREFIX86(_pushf)(); break;\
- case 0x9d: PREFIX86(_popf)(); break;\
- case 0x9e: PREFIX86(_sahf)(); break;\
- case 0x9f: PREFIX86(_lahf)(); break;\
- case 0xa0: PREFIX86(_mov_aldisp)(); break;\
- case 0xa1: PREFIX86(_mov_axdisp)(); break;\
- case 0xa2: PREFIX86(_mov_dispal)(); break;\
- case 0xa3: PREFIX86(_mov_dispax)(); break;\
- case 0xa4: PREFIX86(_movsb)(); break;\
- case 0xa5: PREFIX86(_movsw)(); break;\
- case 0xa6: PREFIX86(_cmpsb)(); break;\
- case 0xa7: PREFIX86(_cmpsw)(); break;\
- case 0xa8: PREFIX86(_test_ald8)(); break;\
- case 0xa9: PREFIX86(_test_axd16)(); break;\
- case 0xaa: PREFIX86(_stosb)(); break;\
- case 0xab: PREFIX86(_stosw)(); break;\
- case 0xac: PREFIX86(_lodsb)(); break;\
- case 0xad: PREFIX86(_lodsw)(); break;\
- case 0xae: PREFIX86(_scasb)(); break;\
- case 0xaf: PREFIX86(_scasw)(); break;\
- case 0xb0: PREFIX86(_mov_ald8)(); break;\
- case 0xb1: PREFIX86(_mov_cld8)(); break;\
- case 0xb2: PREFIX86(_mov_dld8)(); break;\
- case 0xb3: PREFIX86(_mov_bld8)(); break;\
- case 0xb4: PREFIX86(_mov_ahd8)(); break;\
- case 0xb5: PREFIX86(_mov_chd8)(); break;\
- case 0xb6: PREFIX86(_mov_dhd8)(); break;\
- case 0xb7: PREFIX86(_mov_bhd8)(); break;\
- case 0xb8: PREFIX86(_mov_axd16)(); break;\
- case 0xb9: PREFIX86(_mov_cxd16)(); break;\
- case 0xba: PREFIX86(_mov_dxd16)(); break;\
- case 0xbb: PREFIX86(_mov_bxd16)(); break;\
- case 0xbc: PREFIX86(_mov_spd16)(); break;\
- case 0xbd: PREFIX86(_mov_bpd16)(); break;\
- case 0xbe: PREFIX86(_mov_sid16)(); break;\
- case 0xbf: PREFIX86(_mov_did16)(); break;\
- case 0xc0: PREFIX86(_invalid)(); break;\
- case 0xc1: PREFIX86(_invalid)(); break;\
- case 0xc2: PREFIX86(_ret_d16)(); break;\
- case 0xc3: PREFIX86(_ret)(); break;\
- case 0xc4: PREFIX86(_les_dw)(); break;\
- case 0xc5: PREFIX86(_lds_dw)(); break;\
- case 0xc6: PREFIX86(_mov_bd8)(); break;\
- case 0xc7: PREFIX86(_mov_wd16)(); break;\
- case 0xc8: PREFIX86(_invalid)(); break;\
- case 0xc9: PREFIX86(_invalid)(); break;\
- case 0xca: PREFIX86(_retf_d16)(); break;\
- case 0xcb: PREFIX86(_retf)(); break;\
- case 0xcc: PREFIX86(_int3)(); break;\
- case 0xcd: PREFIX86(_int)(); break;\
- case 0xce: PREFIX86(_into)(); break;\
- case 0xcf: PREFIX86(_iret)(); break;\
- case 0xd0: PREFIX86(_rotshft_b)(); break;\
- case 0xd1: PREFIX86(_rotshft_w)(); break;\
- case 0xd2: PREFIX86(_rotshft_bcl)(); break;\
- case 0xd3: PREFIX86(_rotshft_wcl)(); break;\
- case 0xd4: PREFIX86(_aam)(); break;\
- case 0xd5: PREFIX86(_aad)(); break;\
- case 0xd6: PREFIX86(_invalid)(); break;\
- case 0xd7: PREFIX86(_xlat)(); break;\
- case 0xd8: PREFIX86(_escape)(); break;\
- case 0xd9: PREFIX86(_escape)(); break;\
- case 0xda: PREFIX86(_escape)(); break;\
- case 0xdb: PREFIX86(_escape)(); break;\
- case 0xdc: PREFIX86(_escape)(); break;\
- case 0xdd: PREFIX86(_escape)(); break;\
- case 0xde: PREFIX86(_escape)(); break;\
- case 0xdf: PREFIX86(_escape)(); break;\
- case 0xe0: PREFIX86(_loopne)(); break;\
- case 0xe1: PREFIX86(_loope)(); break;\
- case 0xe2: PREFIX86(_loop)(); break;\
- case 0xe3: PREFIX86(_jcxz)(); break;\
- case 0xe4: PREFIX86(_inal)(); break;\
- case 0xe5: PREFIX86(_inax)(); break;\
- case 0xe6: PREFIX86(_outal)(); break;\
- case 0xe7: PREFIX86(_outax)(); break;\
- case 0xe8: PREFIX86(_call_d16)(); break;\
- case 0xe9: PREFIX86(_jmp_d16)(); break;\
- case 0xea: PREFIX86(_jmp_far)(); break;\
- case 0xeb: PREFIX86(_jmp_d8)(); break;\
- case 0xec: PREFIX86(_inaldx)(); break;\
- case 0xed: PREFIX86(_inaxdx)(); break;\
- case 0xee: PREFIX86(_outdxal)(); break;\
- case 0xef: PREFIX86(_outdxax)(); break;\
- case 0xf0: PREFIX86(_lock)(); break;\
- case 0xf1: PREFIX86(_invalid)(); break;\
- case 0xf2: PREFIX86(_repne)(); break;\
- case 0xf3: PREFIX86(_repe)(); break;\
- case 0xf4: PREFIX86(_hlt)(); break;\
- case 0xf5: PREFIX86(_cmc)(); break;\
- case 0xf6: PREFIX86(_f6pre)(); break;\
- case 0xf7: PREFIX86(_f7pre)(); break;\
- case 0xf8: PREFIX86(_clc)(); break;\
- case 0xf9: PREFIX86(_stc)(); break;\
- case 0xfa: PREFIX86(_cli)(); break;\
- case 0xfb: PREFIX86(_sti)(); break;\
- case 0xfc: PREFIX86(_cld)(); break;\
- case 0xfd: PREFIX86(_std)(); break;\
- case 0xfe: PREFIX86(_fepre)(); break;\
- case 0xff: PREFIX86(_ffpre)(); break;\
+ case 0x00: PREFIX86(_add_br8)(cpustate); break;\
+ case 0x01: PREFIX86(_add_wr16)(cpustate); break;\
+ case 0x02: PREFIX86(_add_r8b)(cpustate); break;\
+ case 0x03: PREFIX86(_add_r16w)(cpustate); break;\
+ case 0x04: PREFIX86(_add_ald8)(cpustate); break;\
+ case 0x05: PREFIX86(_add_axd16)(cpustate); break;\
+ case 0x06: PREFIX86(_push_es)(cpustate); break;\
+ case 0x07: PREFIX86(_pop_es)(cpustate); break;\
+ case 0x08: PREFIX86(_or_br8)(cpustate); break;\
+ case 0x09: PREFIX86(_or_wr16)(cpustate); break;\
+ case 0x0a: PREFIX86(_or_r8b)(cpustate); break;\
+ case 0x0b: PREFIX86(_or_r16w)(cpustate); break;\
+ case 0x0c: PREFIX86(_or_ald8)(cpustate); break;\
+ case 0x0d: PREFIX86(_or_axd16)(cpustate); break;\
+ case 0x0e: PREFIX86(_push_cs)(cpustate); break;\
+ case 0x0f: PREFIX86(_invalid)(cpustate); break;\
+ case 0x10: PREFIX86(_adc_br8)(cpustate); break;\
+ case 0x11: PREFIX86(_adc_wr16)(cpustate); break;\
+ case 0x12: PREFIX86(_adc_r8b)(cpustate); break;\
+ case 0x13: PREFIX86(_adc_r16w)(cpustate); break;\
+ case 0x14: PREFIX86(_adc_ald8)(cpustate); break;\
+ case 0x15: PREFIX86(_adc_axd16)(cpustate); break;\
+ case 0x16: PREFIX86(_push_ss)(cpustate); break;\
+ case 0x17: PREFIX86(_pop_ss)(cpustate); break;\
+ case 0x18: PREFIX86(_sbb_br8)(cpustate); break;\
+ case 0x19: PREFIX86(_sbb_wr16)(cpustate); break;\
+ case 0x1a: PREFIX86(_sbb_r8b)(cpustate); break;\
+ case 0x1b: PREFIX86(_sbb_r16w)(cpustate); break;\
+ case 0x1c: PREFIX86(_sbb_ald8)(cpustate); break;\
+ case 0x1d: PREFIX86(_sbb_axd16)(cpustate); break;\
+ case 0x1e: PREFIX86(_push_ds)(cpustate); break;\
+ case 0x1f: PREFIX86(_pop_ds)(cpustate); break;\
+ case 0x20: PREFIX86(_and_br8)(cpustate); break;\
+ case 0x21: PREFIX86(_and_wr16)(cpustate); break;\
+ case 0x22: PREFIX86(_and_r8b)(cpustate); break;\
+ case 0x23: PREFIX86(_and_r16w)(cpustate); break;\
+ case 0x24: PREFIX86(_and_ald8)(cpustate); break;\
+ case 0x25: PREFIX86(_and_axd16)(cpustate); break;\
+ case 0x26: PREFIX86(_es)(cpustate); break;\
+ case 0x27: PREFIX86(_daa)(cpustate); break;\
+ case 0x28: PREFIX86(_sub_br8)(cpustate); break;\
+ case 0x29: PREFIX86(_sub_wr16)(cpustate); break;\
+ case 0x2a: PREFIX86(_sub_r8b)(cpustate); break;\
+ case 0x2b: PREFIX86(_sub_r16w)(cpustate); break;\
+ case 0x2c: PREFIX86(_sub_ald8)(cpustate); break;\
+ case 0x2d: PREFIX86(_sub_axd16)(cpustate); break;\
+ case 0x2e: PREFIX86(_cs)(cpustate); break;\
+ case 0x2f: PREFIX86(_das)(cpustate); break;\
+ case 0x30: PREFIX86(_xor_br8)(cpustate); break;\
+ case 0x31: PREFIX86(_xor_wr16)(cpustate); break;\
+ case 0x32: PREFIX86(_xor_r8b)(cpustate); break;\
+ case 0x33: PREFIX86(_xor_r16w)(cpustate); break;\
+ case 0x34: PREFIX86(_xor_ald8)(cpustate); break;\
+ case 0x35: PREFIX86(_xor_axd16)(cpustate); break;\
+ case 0x36: PREFIX86(_ss)(cpustate); break;\
+ case 0x37: PREFIX86(_aaa)(cpustate); break;\
+ case 0x38: PREFIX86(_cmp_br8)(cpustate); break;\
+ case 0x39: PREFIX86(_cmp_wr16)(cpustate); break;\
+ case 0x3a: PREFIX86(_cmp_r8b)(cpustate); break;\
+ case 0x3b: PREFIX86(_cmp_r16w)(cpustate); break;\
+ case 0x3c: PREFIX86(_cmp_ald8)(cpustate); break;\
+ case 0x3d: PREFIX86(_cmp_axd16)(cpustate); break;\
+ case 0x3e: PREFIX86(_ds)(cpustate); break;\
+ case 0x3f: PREFIX86(_aas)(cpustate); break;\
+ case 0x40: PREFIX86(_inc_ax)(cpustate); break;\
+ case 0x41: PREFIX86(_inc_cx)(cpustate); break;\
+ case 0x42: PREFIX86(_inc_dx)(cpustate); break;\
+ case 0x43: PREFIX86(_inc_bx)(cpustate); break;\
+ case 0x44: PREFIX86(_inc_sp)(cpustate); break;\
+ case 0x45: PREFIX86(_inc_bp)(cpustate); break;\
+ case 0x46: PREFIX86(_inc_si)(cpustate); break;\
+ case 0x47: PREFIX86(_inc_di)(cpustate); break;\
+ case 0x48: PREFIX86(_dec_ax)(cpustate); break;\
+ case 0x49: PREFIX86(_dec_cx)(cpustate); break;\
+ case 0x4a: PREFIX86(_dec_dx)(cpustate); break;\
+ case 0x4b: PREFIX86(_dec_bx)(cpustate); break;\
+ case 0x4c: PREFIX86(_dec_sp)(cpustate); break;\
+ case 0x4d: PREFIX86(_dec_bp)(cpustate); break;\
+ case 0x4e: PREFIX86(_dec_si)(cpustate); break;\
+ case 0x4f: PREFIX86(_dec_di)(cpustate); break;\
+ case 0x50: PREFIX86(_push_ax)(cpustate); break;\
+ case 0x51: PREFIX86(_push_cx)(cpustate); break;\
+ case 0x52: PREFIX86(_push_dx)(cpustate); break;\
+ case 0x53: PREFIX86(_push_bx)(cpustate); break;\
+ case 0x54: PREFIX86(_push_sp)(cpustate); break;\
+ case 0x55: PREFIX86(_push_bp)(cpustate); break;\
+ case 0x56: PREFIX86(_push_si)(cpustate); break;\
+ case 0x57: PREFIX86(_push_di)(cpustate); break;\
+ case 0x58: PREFIX86(_pop_ax)(cpustate); break;\
+ case 0x59: PREFIX86(_pop_cx)(cpustate); break;\
+ case 0x5a: PREFIX86(_pop_dx)(cpustate); break;\
+ case 0x5b: PREFIX86(_pop_bx)(cpustate); break;\
+ case 0x5c: PREFIX86(_pop_sp)(cpustate); break;\
+ case 0x5d: PREFIX86(_pop_bp)(cpustate); break;\
+ case 0x5e: PREFIX86(_pop_si)(cpustate); break;\
+ case 0x5f: PREFIX86(_pop_di)(cpustate); break;\
+ case 0x60: PREFIX86(_invalid)(cpustate); break;\
+ case 0x61: PREFIX86(_invalid)(cpustate); break;\
+ case 0x62: PREFIX86(_invalid)(cpustate); break;\
+ case 0x63: PREFIX86(_invalid)(cpustate); break;\
+ case 0x64: PREFIX86(_invalid)(cpustate); break;\
+ case 0x65: PREFIX86(_invalid)(cpustate); break;\
+ case 0x66: PREFIX86(_invalid)(cpustate); break;\
+ case 0x67: PREFIX86(_invalid)(cpustate); break;\
+ case 0x68: PREFIX86(_invalid)(cpustate); break;\
+ case 0x69: PREFIX86(_invalid)(cpustate); break;\
+ case 0x6a: PREFIX86(_invalid)(cpustate); break;\
+ case 0x6b: PREFIX86(_invalid)(cpustate); break;\
+ case 0x6c: PREFIX86(_invalid)(cpustate); break;\
+ case 0x6d: PREFIX86(_invalid)(cpustate); break;\
+ case 0x6e: PREFIX86(_invalid)(cpustate); break;\
+ case 0x6f: PREFIX86(_invalid)(cpustate); break;\
+ case 0x70: PREFIX86(_jo)(cpustate); break;\
+ case 0x71: PREFIX86(_jno)(cpustate); break;\
+ case 0x72: PREFIX86(_jb)(cpustate); break;\
+ case 0x73: PREFIX86(_jnb)(cpustate); break;\
+ case 0x74: PREFIX86(_jz)(cpustate); break;\
+ case 0x75: PREFIX86(_jnz)(cpustate); break;\
+ case 0x76: PREFIX86(_jbe)(cpustate); break;\
+ case 0x77: PREFIX86(_jnbe)(cpustate); break;\
+ case 0x78: PREFIX86(_js)(cpustate); break;\
+ case 0x79: PREFIX86(_jns)(cpustate); break;\
+ case 0x7a: PREFIX86(_jp)(cpustate); break;\
+ case 0x7b: PREFIX86(_jnp)(cpustate); break;\
+ case 0x7c: PREFIX86(_jl)(cpustate); break;\
+ case 0x7d: PREFIX86(_jnl)(cpustate); break;\
+ case 0x7e: PREFIX86(_jle)(cpustate); break;\
+ case 0x7f: PREFIX86(_jnle)(cpustate); break;\
+ case 0x80: PREFIX86(_80pre)(cpustate); break;\
+ case 0x81: PREFIX86(_81pre)(cpustate); break;\
+ case 0x82: PREFIX86(_82pre)(cpustate); break;\
+ case 0x83: PREFIX86(_83pre)(cpustate); break;\
+ case 0x84: PREFIX86(_test_br8)(cpustate); break;\
+ case 0x85: PREFIX86(_test_wr16)(cpustate); break;\
+ case 0x86: PREFIX86(_xchg_br8)(cpustate); break;\
+ case 0x87: PREFIX86(_xchg_wr16)(cpustate); break;\
+ case 0x88: PREFIX86(_mov_br8)(cpustate); break;\
+ case 0x89: PREFIX86(_mov_wr16)(cpustate); break;\
+ case 0x8a: PREFIX86(_mov_r8b)(cpustate); break;\
+ case 0x8b: PREFIX86(_mov_r16w)(cpustate); break;\
+ case 0x8c: PREFIX86(_mov_wsreg)(cpustate); break;\
+ case 0x8d: PREFIX86(_lea)(cpustate); break;\
+ case 0x8e: PREFIX86(_mov_sregw)(cpustate); break;\
+ case 0x8f: PREFIX86(_popw)(cpustate); break;\
+ case 0x90: PREFIX86(_nop)(cpustate); break;\
+ case 0x91: PREFIX86(_xchg_axcx)(cpustate); break;\
+ case 0x92: PREFIX86(_xchg_axdx)(cpustate); break;\
+ case 0x93: PREFIX86(_xchg_axbx)(cpustate); break;\
+ case 0x94: PREFIX86(_xchg_axsp)(cpustate); break;\
+ case 0x95: PREFIX86(_xchg_axbp)(cpustate); break;\
+ case 0x96: PREFIX86(_xchg_axsi)(cpustate); break;\
+ case 0x97: PREFIX86(_xchg_axdi)(cpustate); break;\
+ case 0x98: PREFIX86(_cbw)(cpustate); break;\
+ case 0x99: PREFIX86(_cwd)(cpustate); break;\
+ case 0x9a: PREFIX86(_call_far)(cpustate); break;\
+ case 0x9b: PREFIX86(_wait)(cpustate); break;\
+ case 0x9c: PREFIX86(_pushf)(cpustate); break;\
+ case 0x9d: PREFIX86(_popf)(cpustate); break;\
+ case 0x9e: PREFIX86(_sahf)(cpustate); break;\
+ case 0x9f: PREFIX86(_lahf)(cpustate); break;\
+ case 0xa0: PREFIX86(_mov_aldisp)(cpustate); break;\
+ case 0xa1: PREFIX86(_mov_axdisp)(cpustate); break;\
+ case 0xa2: PREFIX86(_mov_dispal)(cpustate); break;\
+ case 0xa3: PREFIX86(_mov_dispax)(cpustate); break;\
+ case 0xa4: PREFIX86(_movsb)(cpustate); break;\
+ case 0xa5: PREFIX86(_movsw)(cpustate); break;\
+ case 0xa6: PREFIX86(_cmpsb)(cpustate); break;\
+ case 0xa7: PREFIX86(_cmpsw)(cpustate); break;\
+ case 0xa8: PREFIX86(_test_ald8)(cpustate); break;\
+ case 0xa9: PREFIX86(_test_axd16)(cpustate); break;\
+ case 0xaa: PREFIX86(_stosb)(cpustate); break;\
+ case 0xab: PREFIX86(_stosw)(cpustate); break;\
+ case 0xac: PREFIX86(_lodsb)(cpustate); break;\
+ case 0xad: PREFIX86(_lodsw)(cpustate); break;\
+ case 0xae: PREFIX86(_scasb)(cpustate); break;\
+ case 0xaf: PREFIX86(_scasw)(cpustate); break;\
+ case 0xb0: PREFIX86(_mov_ald8)(cpustate); break;\
+ case 0xb1: PREFIX86(_mov_cld8)(cpustate); break;\
+ case 0xb2: PREFIX86(_mov_dld8)(cpustate); break;\
+ case 0xb3: PREFIX86(_mov_bld8)(cpustate); break;\
+ case 0xb4: PREFIX86(_mov_ahd8)(cpustate); break;\
+ case 0xb5: PREFIX86(_mov_chd8)(cpustate); break;\
+ case 0xb6: PREFIX86(_mov_dhd8)(cpustate); break;\
+ case 0xb7: PREFIX86(_mov_bhd8)(cpustate); break;\
+ case 0xb8: PREFIX86(_mov_axd16)(cpustate); break;\
+ case 0xb9: PREFIX86(_mov_cxd16)(cpustate); break;\
+ case 0xba: PREFIX86(_mov_dxd16)(cpustate); break;\
+ case 0xbb: PREFIX86(_mov_bxd16)(cpustate); break;\
+ case 0xbc: PREFIX86(_mov_spd16)(cpustate); break;\
+ case 0xbd: PREFIX86(_mov_bpd16)(cpustate); break;\
+ case 0xbe: PREFIX86(_mov_sid16)(cpustate); break;\
+ case 0xbf: PREFIX86(_mov_did16)(cpustate); break;\
+ case 0xc0: PREFIX86(_invalid)(cpustate); break;\
+ case 0xc1: PREFIX86(_invalid)(cpustate); break;\
+ case 0xc2: PREFIX86(_ret_d16)(cpustate); break;\
+ case 0xc3: PREFIX86(_ret)(cpustate); break;\
+ case 0xc4: PREFIX86(_les_dw)(cpustate); break;\
+ case 0xc5: PREFIX86(_lds_dw)(cpustate); break;\
+ case 0xc6: PREFIX86(_mov_bd8)(cpustate); break;\
+ case 0xc7: PREFIX86(_mov_wd16)(cpustate); break;\
+ case 0xc8: PREFIX86(_invalid)(cpustate); break;\
+ case 0xc9: PREFIX86(_invalid)(cpustate); break;\
+ case 0xca: PREFIX86(_retf_d16)(cpustate); break;\
+ case 0xcb: PREFIX86(_retf)(cpustate); break;\
+ case 0xcc: PREFIX86(_int3)(cpustate); break;\
+ case 0xcd: PREFIX86(_int)(cpustate); break;\
+ case 0xce: PREFIX86(_into)(cpustate); break;\
+ case 0xcf: PREFIX86(_iret)(cpustate); break;\
+ case 0xd0: PREFIX86(_rotshft_b)(cpustate); break;\
+ case 0xd1: PREFIX86(_rotshft_w)(cpustate); break;\
+ case 0xd2: PREFIX86(_rotshft_bcl)(cpustate); break;\
+ case 0xd3: PREFIX86(_rotshft_wcl)(cpustate); break;\
+ case 0xd4: PREFIX86(_aam)(cpustate); break;\
+ case 0xd5: PREFIX86(_aad)(cpustate); break;\
+ case 0xd6: PREFIX86(_invalid)(cpustate); break;\
+ case 0xd7: PREFIX86(_xlat)(cpustate); break;\
+ case 0xd8: PREFIX86(_escape)(cpustate); break;\
+ case 0xd9: PREFIX86(_escape)(cpustate); break;\
+ case 0xda: PREFIX86(_escape)(cpustate); break;\
+ case 0xdb: PREFIX86(_escape)(cpustate); break;\
+ case 0xdc: PREFIX86(_escape)(cpustate); break;\
+ case 0xdd: PREFIX86(_escape)(cpustate); break;\
+ case 0xde: PREFIX86(_escape)(cpustate); break;\
+ case 0xdf: PREFIX86(_escape)(cpustate); break;\
+ case 0xe0: PREFIX86(_loopne)(cpustate); break;\
+ case 0xe1: PREFIX86(_loope)(cpustate); break;\
+ case 0xe2: PREFIX86(_loop)(cpustate); break;\
+ case 0xe3: PREFIX86(_jcxz)(cpustate); break;\
+ case 0xe4: PREFIX86(_inal)(cpustate); break;\
+ case 0xe5: PREFIX86(_inax)(cpustate); break;\
+ case 0xe6: PREFIX86(_outal)(cpustate); break;\
+ case 0xe7: PREFIX86(_outax)(cpustate); break;\
+ case 0xe8: PREFIX86(_call_d16)(cpustate); break;\
+ case 0xe9: PREFIX86(_jmp_d16)(cpustate); break;\
+ case 0xea: PREFIX86(_jmp_far)(cpustate); break;\
+ case 0xeb: PREFIX86(_jmp_d8)(cpustate); break;\
+ case 0xec: PREFIX86(_inaldx)(cpustate); break;\
+ case 0xed: PREFIX86(_inaxdx)(cpustate); break;\
+ case 0xee: PREFIX86(_outdxal)(cpustate); break;\
+ case 0xef: PREFIX86(_outdxax)(cpustate); break;\
+ case 0xf0: PREFIX86(_lock)(cpustate); break;\
+ case 0xf1: PREFIX86(_invalid)(cpustate); break;\
+ case 0xf2: PREFIX86(_repne)(cpustate); break;\
+ case 0xf3: PREFIX86(_repe)(cpustate); break;\
+ case 0xf4: PREFIX86(_hlt)(cpustate); break;\
+ case 0xf5: PREFIX86(_cmc)(cpustate); break;\
+ case 0xf6: PREFIX86(_f6pre)(cpustate); break;\
+ case 0xf7: PREFIX86(_f7pre)(cpustate); break;\
+ case 0xf8: PREFIX86(_clc)(cpustate); break;\
+ case 0xf9: PREFIX86(_stc)(cpustate); break;\
+ case 0xfa: PREFIX86(_cli)(cpustate); break;\
+ case 0xfb: PREFIX86(_sti)(cpustate); break;\
+ case 0xfc: PREFIX86(_cld)(cpustate); break;\
+ case 0xfd: PREFIX86(_std)(cpustate); break;\
+ case 0xfe: PREFIX86(_fepre)(cpustate); break;\
+ case 0xff: PREFIX86(_ffpre)(cpustate); break;\
};
#else
-#define TABLE86 PREFIX86(_instruction)[FETCHOP]();
+#define TABLE86 PREFIX86(_instruction)[FETCHOP](cpustate);
#endif
diff --git a/src/emu/cpu/i86/tablev30.h b/src/emu/cpu/i86/tablev30.h
deleted file mode 100644
index 3c29bf85678..00000000000
--- a/src/emu/cpu/i86/tablev30.h
+++ /dev/null
@@ -1,528 +0,0 @@
-// special nec instructions missing
-// at the time the same like table186.h
-
-static void (*const PREFIXV30(_instruction)[256])(void) =
-{
- PREFIX86(_add_br8), /* 0x00 */
- PREFIX86(_add_wr16), /* 0x01 */
- PREFIX86(_add_r8b), /* 0x02 */
- PREFIX86(_add_r16w), /* 0x03 */
- PREFIX86(_add_ald8), /* 0x04 */
- PREFIX86(_add_axd16), /* 0x05 */
- PREFIX86(_push_es), /* 0x06 */
- PREFIX86(_pop_es), /* 0x07 */
- PREFIX86(_or_br8), /* 0x08 */
- PREFIX86(_or_wr16), /* 0x09 */
- PREFIX86(_or_r8b), /* 0x0a */
- PREFIX86(_or_r16w), /* 0x0b */
- PREFIX86(_or_ald8), /* 0x0c */
- PREFIX86(_or_axd16), /* 0x0d */
- PREFIX86(_push_cs), /* 0x0e */
- PREFIXV30(_0fpre),
- PREFIX86(_adc_br8), /* 0x10 */
- PREFIX86(_adc_wr16), /* 0x11 */
- PREFIX86(_adc_r8b), /* 0x12 */
- PREFIX86(_adc_r16w), /* 0x13 */
- PREFIX86(_adc_ald8), /* 0x14 */
- PREFIX86(_adc_axd16), /* 0x15 */
- PREFIX86(_push_ss), /* 0x16 */
- PREFIX86(_pop_ss), /* 0x17 */
- PREFIX86(_sbb_br8), /* 0x18 */
- PREFIX86(_sbb_wr16), /* 0x19 */
- PREFIX86(_sbb_r8b), /* 0x1a */
- PREFIX86(_sbb_r16w), /* 0x1b */
- PREFIX86(_sbb_ald8), /* 0x1c */
- PREFIX86(_sbb_axd16), /* 0x1d */
- PREFIX86(_push_ds), /* 0x1e */
- PREFIX86(_pop_ds), /* 0x1f */
- PREFIX86(_and_br8), /* 0x20 */
- PREFIX86(_and_wr16), /* 0x21 */
- PREFIX86(_and_r8b), /* 0x22 */
- PREFIX86(_and_r16w), /* 0x23 */
- PREFIX86(_and_ald8), /* 0x24 */
- PREFIX86(_and_axd16), /* 0x25 */
- PREFIX86(_es), /* 0x26 */
- PREFIX86(_daa), /* 0x27 */
- PREFIX86(_sub_br8), /* 0x28 */
- PREFIX86(_sub_wr16), /* 0x29 */
- PREFIX86(_sub_r8b), /* 0x2a */
- PREFIX86(_sub_r16w), /* 0x2b */
- PREFIX86(_sub_ald8), /* 0x2c */
- PREFIX86(_sub_axd16), /* 0x2d */
- PREFIX86(_cs), /* 0x2e */
- PREFIX86(_das), /* 0x2f */
- PREFIX86(_xor_br8), /* 0x30 */
- PREFIX86(_xor_wr16), /* 0x31 */
- PREFIX86(_xor_r8b), /* 0x32 */
- PREFIX86(_xor_r16w), /* 0x33 */
- PREFIX86(_xor_ald8), /* 0x34 */
- PREFIX86(_xor_axd16), /* 0x35 */
- PREFIX86(_ss), /* 0x36 */
- PREFIX86(_aaa), /* 0x37 */
- PREFIX86(_cmp_br8), /* 0x38 */
- PREFIX86(_cmp_wr16), /* 0x39 */
- PREFIX86(_cmp_r8b), /* 0x3a */
- PREFIX86(_cmp_r16w), /* 0x3b */
- PREFIX86(_cmp_ald8), /* 0x3c */
- PREFIX86(_cmp_axd16), /* 0x3d */
- PREFIX86(_ds), /* 0x3e */
- PREFIX86(_aas), /* 0x3f */
- PREFIX86(_inc_ax), /* 0x40 */
- PREFIX86(_inc_cx), /* 0x41 */
- PREFIX86(_inc_dx), /* 0x42 */
- PREFIX86(_inc_bx), /* 0x43 */
- PREFIX86(_inc_sp), /* 0x44 */
- PREFIX86(_inc_bp), /* 0x45 */
- PREFIX86(_inc_si), /* 0x46 */
- PREFIX86(_inc_di), /* 0x47 */
- PREFIX86(_dec_ax), /* 0x48 */
- PREFIX86(_dec_cx), /* 0x49 */
- PREFIX86(_dec_dx), /* 0x4a */
- PREFIX86(_dec_bx), /* 0x4b */
- PREFIX86(_dec_sp), /* 0x4c */
- PREFIX86(_dec_bp), /* 0x4d */
- PREFIX86(_dec_si), /* 0x4e */
- PREFIX86(_dec_di), /* 0x4f */
- PREFIX86(_push_ax), /* 0x50 */
- PREFIX86(_push_cx), /* 0x51 */
- PREFIX86(_push_dx), /* 0x52 */
- PREFIX86(_push_bx), /* 0x53 */
- PREFIX86(_push_sp), /* 0x54 */
- PREFIX86(_push_bp), /* 0x55 */
- PREFIX86(_push_si), /* 0x56 */
- PREFIX86(_push_di), /* 0x57 */
- PREFIX86(_pop_ax), /* 0x58 */
- PREFIX86(_pop_cx), /* 0x59 */
- PREFIX86(_pop_dx), /* 0x5a */
- PREFIX86(_pop_bx), /* 0x5b */
- PREFIX86(_pop_sp), /* 0x5c */
- PREFIX86(_pop_bp), /* 0x5d */
- PREFIX86(_pop_si), /* 0x5e */
- PREFIX86(_pop_di), /* 0x5f */
- PREFIX186(_pusha), /* 0x60 */
- PREFIX186(_popa), /* 0x61 */
- PREFIX186(_bound), /* 0x62 */
- PREFIX86(_invalid),
- PREFIXV30(_repnc),
- PREFIXV30(_repc),
- PREFIX86(_invalid),
- PREFIX86(_invalid),
- PREFIX186(_push_d16), /* 0x68 */
- PREFIX186(_imul_d16), /* 0x69 */
- PREFIX186(_push_d8), /* 0x6a */
- PREFIX186(_imul_d8), /* 0x6b */
- PREFIX186(_insb), /* 0x6c */
- PREFIX186(_insw), /* 0x6d */
- PREFIX186(_outsb), /* 0x6e */
- PREFIX186(_outsw), /* 0x6f */
- PREFIX86(_jo), /* 0x70 */
- PREFIX86(_jno), /* 0x71 */
- PREFIX86(_jb), /* 0x72 */
- PREFIX86(_jnb), /* 0x73 */
- PREFIX86(_jz), /* 0x74 */
- PREFIX86(_jnz), /* 0x75 */
- PREFIX86(_jbe), /* 0x76 */
- PREFIX86(_jnbe), /* 0x77 */
- PREFIX86(_js), /* 0x78 */
- PREFIX86(_jns), /* 0x79 */
- PREFIX86(_jp), /* 0x7a */
- PREFIX86(_jnp), /* 0x7b */
- PREFIX86(_jl), /* 0x7c */
- PREFIX86(_jnl), /* 0x7d */
- PREFIX86(_jle), /* 0x7e */
- PREFIX86(_jnle), /* 0x7f */
- PREFIX86(_80pre), /* 0x80 */
- PREFIX86(_81pre), /* 0x81 */
- PREFIX86(_82pre), /* 0x82 */
- PREFIX86(_83pre), /* 0x83 */
- PREFIX86(_test_br8), /* 0x84 */
- PREFIX86(_test_wr16), /* 0x85 */
- PREFIX86(_xchg_br8), /* 0x86 */
- PREFIX86(_xchg_wr16), /* 0x87 */
- PREFIX86(_mov_br8), /* 0x88 */
- PREFIX86(_mov_wr16), /* 0x89 */
- PREFIX86(_mov_r8b), /* 0x8a */
- PREFIX86(_mov_r16w), /* 0x8b */
- PREFIX86(_mov_wsreg), /* 0x8c */
- PREFIX86(_lea), /* 0x8d */
- PREFIX86(_mov_sregw), /* 0x8e */
- PREFIX86(_popw), /* 0x8f */
- PREFIX86(_nop), /* 0x90 */
- PREFIX86(_xchg_axcx), /* 0x91 */
- PREFIX86(_xchg_axdx), /* 0x92 */
- PREFIX86(_xchg_axbx), /* 0x93 */
- PREFIX86(_xchg_axsp), /* 0x94 */
- PREFIX86(_xchg_axbp), /* 0x95 */
- PREFIX86(_xchg_axsi), /* 0x97 */
- PREFIX86(_xchg_axdi), /* 0x97 */
- PREFIX86(_cbw), /* 0x98 */
- PREFIX86(_cwd), /* 0x99 */
- PREFIX86(_call_far), /* 0x9a */
- PREFIX86(_wait), /* 0x9b */
- PREFIXV30(_pushf), /* 0x9c */
- PREFIX86(_popf), /* 0x9d */
- PREFIX86(_sahf), /* 0x9e */
- PREFIX86(_lahf), /* 0x9f */
- PREFIX86(_mov_aldisp), /* 0xa0 */
- PREFIX86(_mov_axdisp), /* 0xa1 */
- PREFIX86(_mov_dispal), /* 0xa2 */
- PREFIX86(_mov_dispax), /* 0xa3 */
- PREFIX86(_movsb), /* 0xa4 */
- PREFIX86(_movsw), /* 0xa5 */
- PREFIX86(_cmpsb), /* 0xa6 */
- PREFIX86(_cmpsw), /* 0xa7 */
- PREFIX86(_test_ald8), /* 0xa8 */
- PREFIX86(_test_axd16), /* 0xa9 */
- PREFIX86(_stosb), /* 0xaa */
- PREFIX86(_stosw), /* 0xab */
- PREFIX86(_lodsb), /* 0xac */
- PREFIX86(_lodsw), /* 0xad */
- PREFIX86(_scasb), /* 0xae */
- PREFIX86(_scasw), /* 0xaf */
- PREFIX86(_mov_ald8), /* 0xb0 */
- PREFIX86(_mov_cld8), /* 0xb1 */
- PREFIX86(_mov_dld8), /* 0xb2 */
- PREFIX86(_mov_bld8), /* 0xb3 */
- PREFIX86(_mov_ahd8), /* 0xb4 */
- PREFIX86(_mov_chd8), /* 0xb5 */
- PREFIX86(_mov_dhd8), /* 0xb6 */
- PREFIX86(_mov_bhd8), /* 0xb7 */
- PREFIX86(_mov_axd16), /* 0xb8 */
- PREFIX86(_mov_cxd16), /* 0xb9 */
- PREFIX86(_mov_dxd16), /* 0xba */
- PREFIX86(_mov_bxd16), /* 0xbb */
- PREFIX86(_mov_spd16), /* 0xbc */
- PREFIX86(_mov_bpd16), /* 0xbd */
- PREFIX86(_mov_sid16), /* 0xbe */
- PREFIX86(_mov_did16), /* 0xbf */
- PREFIX186(_rotshft_bd8), /* 0xc0 */
- PREFIX186(_rotshft_wd8), /* 0xc1 */
- PREFIX86(_ret_d16), /* 0xc2 */
- PREFIX86(_ret), /* 0xc3 */
- PREFIX86(_les_dw), /* 0xc4 */
- PREFIX86(_lds_dw), /* 0xc5 */
- PREFIX86(_mov_bd8), /* 0xc6 */
- PREFIX86(_mov_wd16), /* 0xc7 */
- PREFIX186(_enter), /* 0xc8 */
- PREFIX186(_leave), /* 0xc9 */
- PREFIX86(_retf_d16), /* 0xca */
- PREFIX86(_retf), /* 0xcb */
- PREFIX86(_int3), /* 0xcc */
- PREFIX86(_int), /* 0xcd */
- PREFIX86(_into), /* 0xce */
- PREFIX86(_iret), /* 0xcf */
- PREFIX86(_rotshft_b), /* 0xd0 */
- PREFIX86(_rotshft_w), /* 0xd1 */
- PREFIX86(_rotshft_bcl), /* 0xd2 */
- PREFIX86(_rotshft_wcl), /* 0xd3 */
- PREFIX86(_aam), /* 0xd4 */
- PREFIX86(_aad), /* 0xd5 */
- PREFIXV30(_setalc),
- PREFIX86(_xlat), /* 0xd7 */
- PREFIX86(_escape), /* 0xd8 */
- PREFIX86(_escape), /* 0xd9 */
- PREFIX86(_escape), /* 0xda */
- PREFIX86(_escape), /* 0xdb */
- PREFIX86(_escape), /* 0xdc */
- PREFIX86(_escape), /* 0xdd */
- PREFIX86(_escape), /* 0xde */
- PREFIX86(_escape), /* 0xdf */
- PREFIX86(_loopne), /* 0xe0 */
- PREFIX86(_loope), /* 0xe1 */
- PREFIX86(_loop), /* 0xe2 */
- PREFIX86(_jcxz), /* 0xe3 */
- PREFIX86(_inal), /* 0xe4 */
- PREFIX86(_inax), /* 0xe5 */
- PREFIX86(_outal), /* 0xe6 */
- PREFIX86(_outax), /* 0xe7 */
- PREFIX86(_call_d16), /* 0xe8 */
- PREFIX86(_jmp_d16), /* 0xe9 */
- PREFIX86(_jmp_far), /* 0xea */
- PREFIX86(_jmp_d8), /* 0xeb */
- PREFIX86(_inaldx), /* 0xec */
- PREFIX86(_inaxdx), /* 0xed */
- PREFIX86(_outdxal), /* 0xee */
- PREFIX86(_outdxax), /* 0xef */
- PREFIX86(_lock), /* 0xf0 */
- PREFIX86(_invalid), /* 0xf1 */
- PREFIX186(_repne), /* 0xf2 */
- PREFIX186(_repe), /* 0xf3 */
- PREFIX86(_hlt), /* 0xf4 */
- PREFIX86(_cmc), /* 0xf5 */
- PREFIX86(_f6pre), /* 0xf6 */
- PREFIX86(_f7pre), /* 0xf7 */
- PREFIX86(_clc), /* 0xf8 */
- PREFIX86(_stc), /* 0xf9 */
- PREFIX86(_cli), /* 0xfa */
- PREFIX86(_sti), /* 0xfb */
- PREFIX86(_cld), /* 0xfc */
- PREFIX86(_std), /* 0xfd */
- PREFIX86(_fepre), /* 0xfe */
- PREFIX86(_ffpre) /* 0xff */
-};
-
-#if defined(BIGCASE) && !defined(RS6000)
- /* Some compilers cannot handle large case statements */
-#define TABLEV30 \
- switch(FETCHOP)\
- {\
- case 0x00: PREFIX86(_add_br8)(); break;\
- case 0x01: PREFIX86(_add_wr16)(); break;\
- case 0x02: PREFIX86(_add_r8b)(); break;\
- case 0x03: PREFIX86(_add_r16w)(); break;\
- case 0x04: PREFIX86(_add_ald8)(); break;\
- case 0x05: PREFIX86(_add_axd16)(); break;\
- case 0x06: PREFIX86(_push_es)(); break;\
- case 0x07: PREFIX86(_pop_es)(); break;\
- case 0x08: PREFIX86(_or_br8)(); break;\
- case 0x09: PREFIX86(_or_wr16)(); break;\
- case 0x0a: PREFIX86(_or_r8b)(); break;\
- case 0x0b: PREFIX86(_or_r16w)(); break;\
- case 0x0c: PREFIX86(_or_ald8)(); break;\
- case 0x0d: PREFIX86(_or_axd16)(); break;\
- case 0x0e: PREFIX86(_push_cs)(); break;\
- case 0x0f: PREFIXV30(_0fpre)(); break;\
- case 0x10: PREFIX86(_adc_br8)(); break;\
- case 0x11: PREFIX86(_adc_wr16)(); break;\
- case 0x12: PREFIX86(_adc_r8b)(); break;\
- case 0x13: PREFIX86(_adc_r16w)(); break;\
- case 0x14: PREFIX86(_adc_ald8)(); break;\
- case 0x15: PREFIX86(_adc_axd16)(); break;\
- case 0x16: PREFIX86(_push_ss)(); break;\
- case 0x17: PREFIX86(_pop_ss)(); break;\
- case 0x18: PREFIX86(_sbb_br8)(); break;\
- case 0x19: PREFIX86(_sbb_wr16)(); break;\
- case 0x1a: PREFIX86(_sbb_r8b)(); break;\
- case 0x1b: PREFIX86(_sbb_r16w)(); break;\
- case 0x1c: PREFIX86(_sbb_ald8)(); break;\
- case 0x1d: PREFIX86(_sbb_axd16)(); break;\
- case 0x1e: PREFIX86(_push_ds)(); break;\
- case 0x1f: PREFIX86(_pop_ds)(); break;\
- case 0x20: PREFIX86(_and_br8)(); break;\
- case 0x21: PREFIX86(_and_wr16)(); break;\
- case 0x22: PREFIX86(_and_r8b)(); break;\
- case 0x23: PREFIX86(_and_r16w)(); break;\
- case 0x24: PREFIX86(_and_ald8)(); break;\
- case 0x25: PREFIX86(_and_axd16)(); break;\
- case 0x26: PREFIX86(_es)(); break;\
- case 0x27: PREFIX86(_daa)(); break;\
- case 0x28: PREFIX86(_sub_br8)(); break;\
- case 0x29: PREFIX86(_sub_wr16)(); break;\
- case 0x2a: PREFIX86(_sub_r8b)(); break;\
- case 0x2b: PREFIX86(_sub_r16w)(); break;\
- case 0x2c: PREFIX86(_sub_ald8)(); break;\
- case 0x2d: PREFIX86(_sub_axd16)(); break;\
- case 0x2e: PREFIX86(_cs)(); break;\
- case 0x2f: PREFIX86(_das)(); break;\
- case 0x30: PREFIX86(_xor_br8)(); break;\
- case 0x31: PREFIX86(_xor_wr16)(); break;\
- case 0x32: PREFIX86(_xor_r8b)(); break;\
- case 0x33: PREFIX86(_xor_r16w)(); break;\
- case 0x34: PREFIX86(_xor_ald8)(); break;\
- case 0x35: PREFIX86(_xor_axd16)(); break;\
- case 0x36: PREFIX86(_ss)(); break;\
- case 0x37: PREFIX86(_aaa)(); break;\
- case 0x38: PREFIX86(_cmp_br8)(); break;\
- case 0x39: PREFIX86(_cmp_wr16)(); break;\
- case 0x3a: PREFIX86(_cmp_r8b)(); break;\
- case 0x3b: PREFIX86(_cmp_r16w)(); break;\
- case 0x3c: PREFIX86(_cmp_ald8)(); break;\
- case 0x3d: PREFIX86(_cmp_axd16)(); break;\
- case 0x3e: PREFIX86(_ds)(); break;\
- case 0x3f: PREFIX86(_aas)(); break;\
- case 0x40: PREFIX86(_inc_ax)(); break;\
- case 0x41: PREFIX86(_inc_cx)(); break;\
- case 0x42: PREFIX86(_inc_dx)(); break;\
- case 0x43: PREFIX86(_inc_bx)(); break;\
- case 0x44: PREFIX86(_inc_sp)(); break;\
- case 0x45: PREFIX86(_inc_bp)(); break;\
- case 0x46: PREFIX86(_inc_si)(); break;\
- case 0x47: PREFIX86(_inc_di)(); break;\
- case 0x48: PREFIX86(_dec_ax)(); break;\
- case 0x49: PREFIX86(_dec_cx)(); break;\
- case 0x4a: PREFIX86(_dec_dx)(); break;\
- case 0x4b: PREFIX86(_dec_bx)(); break;\
- case 0x4c: PREFIX86(_dec_sp)(); break;\
- case 0x4d: PREFIX86(_dec_bp)(); break;\
- case 0x4e: PREFIX86(_dec_si)(); break;\
- case 0x4f: PREFIX86(_dec_di)(); break;\
- case 0x50: PREFIX86(_push_ax)(); break;\
- case 0x51: PREFIX86(_push_cx)(); break;\
- case 0x52: PREFIX86(_push_dx)(); break;\
- case 0x53: PREFIX86(_push_bx)(); break;\
- case 0x54: PREFIX86(_push_sp)(); break;\
- case 0x55: PREFIX86(_push_bp)(); break;\
- case 0x56: PREFIX86(_push_si)(); break;\
- case 0x57: PREFIX86(_push_di)(); break;\
- case 0x58: PREFIX86(_pop_ax)(); break;\
- case 0x59: PREFIX86(_pop_cx)(); break;\
- case 0x5a: PREFIX86(_pop_dx)(); break;\
- case 0x5b: PREFIX86(_pop_bx)(); break;\
- case 0x5c: PREFIX86(_pop_sp)(); break;\
- case 0x5d: PREFIX86(_pop_bp)(); break;\
- case 0x5e: PREFIX86(_pop_si)(); break;\
- case 0x5f: PREFIX86(_pop_di)(); break;\
- case 0x60: PREFIX186(_pusha)(); break;\
- case 0x61: PREFIX186(_popa)(); break;\
- case 0x62: PREFIX186(_bound)(); break;\
- case 0x63: PREFIX86(_invalid)(); break;\
- case 0x64: PREFIXV30(_repnc)(); break;\
- case 0x65: PREFIXV30(_repc)(); break;\
- case 0x66: PREFIX86(_invalid)(); break;\
- case 0x67: PREFIX86(_invalid)(); break;\
- case 0x68: PREFIX186(_push_d16)(); break;\
- case 0x69: PREFIX186(_imul_d16)(); break;\
- case 0x6a: PREFIX186(_push_d8)(); break;\
- case 0x6b: PREFIX186(_imul_d8)(); break;\
- case 0x6c: PREFIX186(_insb)(); break;\
- case 0x6d: PREFIX186(_insw)(); break;\
- case 0x6e: PREFIX186(_outsb)(); break;\
- case 0x6f: PREFIX186(_outsw)(); break;\
- case 0x70: PREFIX86(_jo)(); break;\
- case 0x71: PREFIX86(_jno)(); break;\
- case 0x72: PREFIX86(_jb)(); break;\
- case 0x73: PREFIX86(_jnb)(); break;\
- case 0x74: PREFIX86(_jz)(); break;\
- case 0x75: PREFIX86(_jnz)(); break;\
- case 0x76: PREFIX86(_jbe)(); break;\
- case 0x77: PREFIX86(_jnbe)(); break;\
- case 0x78: PREFIX86(_js)(); break;\
- case 0x79: PREFIX86(_jns)(); break;\
- case 0x7a: PREFIX86(_jp)(); break;\
- case 0x7b: PREFIX86(_jnp)(); break;\
- case 0x7c: PREFIX86(_jl)(); break;\
- case 0x7d: PREFIX86(_jnl)(); break;\
- case 0x7e: PREFIX86(_jle)(); break;\
- case 0x7f: PREFIX86(_jnle)(); break;\
- case 0x80: PREFIX86(_80pre)(); break;\
- case 0x81: PREFIX86(_81pre)(); break;\
- case 0x82: PREFIX86(_82pre)(); break;\
- case 0x83: PREFIX86(_83pre)(); break;\
- case 0x84: PREFIX86(_test_br8)(); break;\
- case 0x85: PREFIX86(_test_wr16)(); break;\
- case 0x86: PREFIX86(_xchg_br8)(); break;\
- case 0x87: PREFIX86(_xchg_wr16)(); break;\
- case 0x88: PREFIX86(_mov_br8)(); break;\
- case 0x89: PREFIX86(_mov_wr16)(); break;\
- case 0x8a: PREFIX86(_mov_r8b)(); break;\
- case 0x8b: PREFIX86(_mov_r16w)(); break;\
- case 0x8c: PREFIX86(_mov_wsreg)(); break;\
- case 0x8d: PREFIX86(_lea)(); break;\
- case 0x8e: PREFIX86(_mov_sregw)(); break;\
- case 0x8f: PREFIX86(_popw)(); break;\
- case 0x90: PREFIX86(_nop)(); break;\
- case 0x91: PREFIX86(_xchg_axcx)(); break;\
- case 0x92: PREFIX86(_xchg_axdx)(); break;\
- case 0x93: PREFIX86(_xchg_axbx)(); break;\
- case 0x94: PREFIX86(_xchg_axsp)(); break;\
- case 0x95: PREFIX86(_xchg_axbp)(); break;\
- case 0x96: PREFIX86(_xchg_axsi)(); break;\
- case 0x97: PREFIX86(_xchg_axdi)(); break;\
- case 0x98: PREFIX86(_cbw)(); break;\
- case 0x99: PREFIX86(_cwd)(); break;\
- case 0x9a: PREFIX86(_call_far)(); break;\
- case 0x9b: PREFIX86(_wait)(); break;\
- case 0x9c: PREFIXV30(_pushf)(); break;\
- case 0x9d: PREFIX86(_popf)(); break;\
- case 0x9e: PREFIX86(_sahf)(); break;\
- case 0x9f: PREFIX86(_lahf)(); break;\
- case 0xa0: PREFIX86(_mov_aldisp)(); break;\
- case 0xa1: PREFIX86(_mov_axdisp)(); break;\
- case 0xa2: PREFIX86(_mov_dispal)(); break;\
- case 0xa3: PREFIX86(_mov_dispax)(); break;\
- case 0xa4: PREFIX86(_movsb)(); break;\
- case 0xa5: PREFIX86(_movsw)(); break;\
- case 0xa6: PREFIX86(_cmpsb)(); break;\
- case 0xa7: PREFIX86(_cmpsw)(); break;\
- case 0xa8: PREFIX86(_test_ald8)(); break;\
- case 0xa9: PREFIX86(_test_axd16)(); break;\
- case 0xaa: PREFIX86(_stosb)(); break;\
- case 0xab: PREFIX86(_stosw)(); break;\
- case 0xac: PREFIX86(_lodsb)(); break;\
- case 0xad: PREFIX86(_lodsw)(); break;\
- case 0xae: PREFIX86(_scasb)(); break;\
- case 0xaf: PREFIX86(_scasw)(); break;\
- case 0xb0: PREFIX86(_mov_ald8)(); break;\
- case 0xb1: PREFIX86(_mov_cld8)(); break;\
- case 0xb2: PREFIX86(_mov_dld8)(); break;\
- case 0xb3: PREFIX86(_mov_bld8)(); break;\
- case 0xb4: PREFIX86(_mov_ahd8)(); break;\
- case 0xb5: PREFIX86(_mov_chd8)(); break;\
- case 0xb6: PREFIX86(_mov_dhd8)(); break;\
- case 0xb7: PREFIX86(_mov_bhd8)(); break;\
- case 0xb8: PREFIX86(_mov_axd16)(); break;\
- case 0xb9: PREFIX86(_mov_cxd16)(); break;\
- case 0xba: PREFIX86(_mov_dxd16)(); break;\
- case 0xbb: PREFIX86(_mov_bxd16)(); break;\
- case 0xbc: PREFIX86(_mov_spd16)(); break;\
- case 0xbd: PREFIX86(_mov_bpd16)(); break;\
- case 0xbe: PREFIX86(_mov_sid16)(); break;\
- case 0xbf: PREFIX86(_mov_did16)(); break;\
- case 0xc0: PREFIX186(_rotshft_bd8)(); break;\
- case 0xc1: PREFIX186(_rotshft_wd8)(); break;\
- case 0xc2: PREFIX86(_ret_d16)(); break;\
- case 0xc3: PREFIX86(_ret)(); break;\
- case 0xc4: PREFIX86(_les_dw)(); break;\
- case 0xc5: PREFIX86(_lds_dw)(); break;\
- case 0xc6: PREFIX86(_mov_bd8)(); break;\
- case 0xc7: PREFIX86(_mov_wd16)(); break;\
- case 0xc8: PREFIX186(_enter)(); break;\
- case 0xc9: PREFIX186(_leave)(); break;\
- case 0xca: PREFIX86(_retf_d16)(); break;\
- case 0xcb: PREFIX86(_retf)(); break;\
- case 0xcc: PREFIX86(_int3)(); break;\
- case 0xcd: PREFIX86(_int)(); break;\
- case 0xce: PREFIX86(_into)(); break;\
- case 0xcf: PREFIX86(_iret)(); break;\
- case 0xd0: PREFIX86(_rotshft_b)(); break;\
- case 0xd1: PREFIX86(_rotshft_w)(); break;\
- case 0xd2: PREFIX86(_rotshft_bcl)(); break;\
- case 0xd3: PREFIX86(_rotshft_wcl)(); break;\
- case 0xd4: PREFIX86(_aam)(); break;\
- case 0xd5: PREFIX86(_aad)(); break;\
- case 0xd6: PREFIXV30(_setalc)(); break;\
- case 0xd7: PREFIX86(_xlat)(); break;\
- case 0xd8: PREFIX86(_escape)(); break;\
- case 0xd9: PREFIX86(_escape)(); break;\
- case 0xda: PREFIX86(_escape)(); break;\
- case 0xdb: PREFIX86(_escape)(); break;\
- case 0xdc: PREFIX86(_escape)(); break;\
- case 0xdd: PREFIX86(_escape)(); break;\
- case 0xde: PREFIX86(_escape)(); break;\
- case 0xdf: PREFIX86(_escape)(); break;\
- case 0xe0: PREFIX86(_loopne)(); break;\
- case 0xe1: PREFIX86(_loope)(); break;\
- case 0xe2: PREFIX86(_loop)(); break;\
- case 0xe3: PREFIX86(_jcxz)(); break;\
- case 0xe4: PREFIX86(_inal)(); break;\
- case 0xe5: PREFIX86(_inax)(); break;\
- case 0xe6: PREFIX86(_outal)(); break;\
- case 0xe7: PREFIX86(_outax)(); break;\
- case 0xe8: PREFIX86(_call_d16)(); break;\
- case 0xe9: PREFIX86(_jmp_d16)(); break;\
- case 0xea: PREFIX86(_jmp_far)(); break;\
- case 0xeb: PREFIX86(_jmp_d8)(); break;\
- case 0xec: PREFIX86(_inaldx)(); break;\
- case 0xed: PREFIX86(_inaxdx)(); break;\
- case 0xee: PREFIX86(_outdxal)(); break;\
- case 0xef: PREFIX86(_outdxax)(); break;\
- case 0xf0: PREFIX86(_lock)(); break;\
- case 0xf1: PREFIX86(_invalid)(); break;\
- case 0xf2: PREFIX186(_repne)(); break;\
- case 0xf3: PREFIX186(_repe)(); break;\
- case 0xf4: PREFIX86(_hlt)(); break;\
- case 0xf5: PREFIX86(_cmc)(); break;\
- case 0xf6: PREFIX86(_f6pre)(); break;\
- case 0xf7: PREFIX86(_f7pre)(); break;\
- case 0xf8: PREFIX86(_clc)(); break;\
- case 0xf9: PREFIX86(_stc)(); break;\
- case 0xfa: PREFIX86(_cli)(); break;\
- case 0xfb: PREFIX86(_sti)(); break;\
- case 0xfc: PREFIX86(_cld)(); break;\
- case 0xfd: PREFIX86(_std)(); break;\
- case 0xfe: PREFIX86(_fepre)(); break;\
- case 0xff: PREFIX86(_ffpre)(); break;\
- };
-#else
-#define TABLEV30 PREFIXV30(_instruction)[FETCHOP]();
-#endif
diff --git a/src/emu/cpu/i86/v20intf.h b/src/emu/cpu/i86/v20intf.h
deleted file mode 100644
index 6c8a8714859..00000000000
--- a/src/emu/cpu/i86/v20intf.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* ASG 971222 -- rewrote this interface */
-#pragma once
-
-#ifndef __V20INTF_H__
-#define __V20INTF_H__
-
-#include "i86intrf.h"
-#include "v30intrf.h"
-
-/* Public functions */
-CPU_GET_INFO( v20 );
-
-#endif /* __V20INTF_H__ */
diff --git a/src/emu/cpu/i86/v30.h b/src/emu/cpu/i86/v30.h
deleted file mode 100644
index 33513beb7c3..00000000000
--- a/src/emu/cpu/i86/v30.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#pragma once
-
-#ifndef __V30_H__
-#define __V30_H__
-
-#define SetMD(x) (I.MF = (x)) /* OB [19.07.99] Mode Flag V30 */
-
-#define MD (I.MF!=0)
-
-#undef CompressFlags
-#define CompressFlags() (WORD)(CF | (PF << 2) | (AF << 4) | (ZF << 6) \
- | (SF << 7) | (I.TF << 8) | (I.IF << 9) \
- | (I.DF << 10) | (OF << 11)| (MD << 15))
-
-#undef ExpandFlags
-#define ExpandFlags(f) \
-{ \
- I.CarryVal = (f) & 1; \
- I.ParityVal = !((f) & 4); \
- I.AuxVal = (f) & 16; \
- I.ZeroVal = !((f) & 64); \
- I.SignVal = (f) & 128 ? -1 : 0; \
- I.TF = ((f) & 256) == 256; \
- I.IF = ((f) & 512) == 512; \
- I.DF = ((f) & 1024) == 1024; \
- I.OverVal = (f) & 2048; \
- I.MF = ((f) & 0x8000) == 0x8000; \
-}
-
-#endif /* __V30_H__ */
diff --git a/src/emu/cpu/i86/v30intf.h b/src/emu/cpu/i86/v30intf.h
deleted file mode 100644
index 9b8310966f6..00000000000
--- a/src/emu/cpu/i86/v30intf.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#pragma once
-
-#ifndef __V30INTF_H__
-#define __V30INTF_H__
-
-#include "i86intf.h"
-
-/* Public functions */
-CPU_GET_INFO( v30 );
-
-#endif /* __V30INTF_H__ */
diff --git a/src/emu/cpu/i86/v33intf.h b/src/emu/cpu/i86/v33intf.h
deleted file mode 100644
index 8a0a66fb9c6..00000000000
--- a/src/emu/cpu/i86/v33intf.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __V33INTF_H__
-#define __V33INTF_H__
-
-#include "i86intrf.h"
-#include "v30intrf.h"
-
-/* Public functions */
-CPU_GET_INFO( v33 );
-
-#endif /* __V33INTF_H__ */