diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/emu/cpu/i386/i386.c | 1037 | ||||
-rw-r--r-- | src/emu/cpu/i386/i386.h | 445 | ||||
-rw-r--r-- | src/emu/cpu/i386/i386op16.c | 2670 | ||||
-rw-r--r-- | src/emu/cpu/i386/i386op32.c | 2568 | ||||
-rw-r--r-- | src/emu/cpu/i386/i386ops.c | 1912 | ||||
-rw-r--r-- | src/emu/cpu/i386/i386ops.h | 4 | ||||
-rw-r--r-- | src/emu/cpu/i386/i486ops.c | 258 | ||||
-rw-r--r-- | src/emu/cpu/i386/pentops.c | 36 | ||||
-rw-r--r-- | src/emu/cpu/i386/x87ops.c | 166 |
9 files changed, 4552 insertions, 4544 deletions
diff --git a/src/emu/cpu/i386/i386.c b/src/emu/cpu/i386/i386.c index b3bfcfef55e..17672f5948d 100644 --- a/src/emu/cpu/i386/i386.c +++ b/src/emu/cpu/i386/i386.c @@ -26,7 +26,7 @@ MODRM_TABLE i386_MODRM_table[256]; #define INT_DEBUG 1 -static void i386_load_protected_mode_segment( I386_SREG *seg ) +static void i386_load_protected_mode_segment(i386_state *cpustate, I386_SREG *seg ) { UINT32 v1,v2; UINT32 base, limit; @@ -34,19 +34,19 @@ static void i386_load_protected_mode_segment( I386_SREG *seg ) if ( seg->selector & 0x4 ) { - base = I.ldtr.base; - limit = I.ldtr.limit; + base = cpustate->ldtr.base; + limit = cpustate->ldtr.limit; } else { - base = I.gdtr.base; - limit = I.gdtr.limit; + base = cpustate->gdtr.base; + limit = cpustate->gdtr.limit; } if (limit == 0 || seg->selector + 7 > limit) return; entry = seg->selector & ~0x7; - v1 = READ32( base + entry ); - v2 = READ32( base + entry + 4 ); + v1 = READ32(cpustate, base + entry ); + v2 = READ32(cpustate, base + entry + 4 ); seg->flags = (v2 >> 8) & 0xf0ff; seg->base = (v2 & 0xff000000) | ((v2 & 0xff) << 16) | ((v1 >> 16) & 0xffff); @@ -56,62 +56,62 @@ static void i386_load_protected_mode_segment( I386_SREG *seg ) seg->d = (seg->flags & 0x4000) ? 1 : 0; } -static void i386_load_segment_descriptor( int segment ) +static void i386_load_segment_descriptor(i386_state *cpustate, int segment ) { if (PROTECTED_MODE) { if (!V8086_MODE) - i386_load_protected_mode_segment( &I.sreg[segment] ); + i386_load_protected_mode_segment(cpustate, &cpustate->sreg[segment] ); else { - I.sreg[segment].base = I.sreg[segment].selector << 4; - I.sreg[segment].limit = 0xffff; - I.sreg[segment].flags = (segment == CS) ? 0x009a : 0x0092; + cpustate->sreg[segment].base = cpustate->sreg[segment].selector << 4; + cpustate->sreg[segment].limit = 0xffff; + cpustate->sreg[segment].flags = (segment == CS) ? 0x009a : 0x0092; } } else { - I.sreg[segment].base = I.sreg[segment].selector << 4; + cpustate->sreg[segment].base = cpustate->sreg[segment].selector << 4; - if( segment == CS && !I.performed_intersegment_jump ) - I.sreg[segment].base |= 0xfff00000; + if( segment == CS && !cpustate->performed_intersegment_jump ) + cpustate->sreg[segment].base |= 0xfff00000; } } -static UINT32 get_flags(void) +static UINT32 get_flags(i386_state *cpustate) { UINT32 f = 0x2; - f |= I.CF; - f |= I.PF << 2; - f |= I.AF << 4; - f |= I.ZF << 6; - f |= I.SF << 7; - f |= I.TF << 8; - f |= I.IF << 9; - f |= I.DF << 10; - f |= I.OF << 11; - return (I.eflags & 0xFFFF0000) | (f & 0xFFFF); + f |= cpustate->CF; + f |= cpustate->PF << 2; + f |= cpustate->AF << 4; + f |= cpustate->ZF << 6; + f |= cpustate->SF << 7; + f |= cpustate->TF << 8; + f |= cpustate->IF << 9; + f |= cpustate->DF << 10; + f |= cpustate->OF << 11; + return (cpustate->eflags & 0xFFFF0000) | (f & 0xFFFF); } -static void set_flags( UINT32 f ) +static void set_flags(i386_state *cpustate, UINT32 f ) { - I.CF = (f & 0x1) ? 1 : 0; - I.PF = (f & 0x4) ? 1 : 0; - I.AF = (f & 0x10) ? 1 : 0; - I.ZF = (f & 0x40) ? 1 : 0; - I.SF = (f & 0x80) ? 1 : 0; - I.TF = (f & 0x100) ? 1 : 0; - I.IF = (f & 0x200) ? 1 : 0; - I.DF = (f & 0x400) ? 1 : 0; - I.OF = (f & 0x800) ? 1 : 0; + cpustate->CF = (f & 0x1) ? 1 : 0; + cpustate->PF = (f & 0x4) ? 1 : 0; + cpustate->AF = (f & 0x10) ? 1 : 0; + cpustate->ZF = (f & 0x40) ? 1 : 0; + cpustate->SF = (f & 0x80) ? 1 : 0; + cpustate->TF = (f & 0x100) ? 1 : 0; + cpustate->IF = (f & 0x200) ? 1 : 0; + cpustate->DF = (f & 0x400) ? 1 : 0; + cpustate->OF = (f & 0x800) ? 1 : 0; } -static void sib_byte(UINT8 mod, UINT32* out_ea, UINT8* out_segment) +static void sib_byte(i386_state *cpustate,UINT8 mod, UINT32* out_ea, UINT8* out_segment) { UINT32 ea = 0; UINT8 segment = 0; UINT8 scale, i, base; - UINT8 sib = FETCH(); + UINT8 sib = FETCH(cpustate); scale = (sib >> 6) & 0x3; i = (sib >> 3) & 0x7; base = sib & 0x7; @@ -125,7 +125,7 @@ static void sib_byte(UINT8 mod, UINT32* out_ea, UINT8* out_segment) case 4: ea = REG32(ESP); segment = SS; break; case 5: if( mod == 0 ) { - ea = FETCH32(); + ea = FETCH32(cpustate); segment = DS; } else if( mod == 1 ) { ea = REG32(EBP); @@ -153,7 +153,7 @@ static void sib_byte(UINT8 mod, UINT32* out_ea, UINT8* out_segment) *out_segment = segment; } -static void modrm_to_EA(UINT8 mod_rm, UINT32* out_ea, UINT8* out_segment) +static void modrm_to_EA(i386_state *cpustate,UINT8 mod_rm, UINT32* out_ea, UINT8* out_segment) { INT8 disp8; INT16 disp16; @@ -166,7 +166,7 @@ static void modrm_to_EA(UINT8 mod_rm, UINT32* out_ea, UINT8* out_segment) if( mod_rm >= 0xc0 ) fatalerror("i386: Called modrm_to_EA with modrm value %02X !",mod_rm); - if( I.address_size ) { + if( cpustate->address_size ) { switch( rm ) { default: @@ -174,10 +174,10 @@ static void modrm_to_EA(UINT8 mod_rm, UINT32* out_ea, UINT8* out_segment) case 1: ea = REG32(ECX); segment = DS; break; case 2: ea = REG32(EDX); segment = DS; break; case 3: ea = REG32(EBX); segment = DS; break; - case 4: sib_byte( mod, &ea, &segment ); break; + case 4: sib_byte(cpustate, mod, &ea, &segment ); break; case 5: if( mod == 0 ) { - ea = FETCH32(); segment = DS; + ea = FETCH32(cpustate); segment = DS; } else { ea = REG32(EBP); segment = SS; } @@ -186,15 +186,15 @@ static void modrm_to_EA(UINT8 mod_rm, UINT32* out_ea, UINT8* out_segment) case 7: ea = REG32(EDI); segment = DS; break; } if( mod == 1 ) { - disp8 = FETCH(); + disp8 = FETCH(cpustate); ea += (INT32)disp8; } else if( mod == 2 ) { - disp32 = FETCH32(); + disp32 = FETCH32(cpustate); ea += disp32; } - if( I.segment_prefix ) - segment = I.segment_override; + if( cpustate->segment_prefix ) + segment = cpustate->segment_override; *out_ea = ea; *out_segment = segment; @@ -211,7 +211,7 @@ static void modrm_to_EA(UINT8 mod_rm, UINT32* out_ea, UINT8* out_segment) case 5: ea = REG16(DI); segment = DS; break; case 6: if( mod == 0 ) { - ea = FETCH16(); segment = DS; + ea = FETCH16(cpustate); segment = DS; } else { ea = REG16(BP); segment = SS; } @@ -219,38 +219,38 @@ static void modrm_to_EA(UINT8 mod_rm, UINT32* out_ea, UINT8* out_segment) case 7: ea = REG16(BX); segment = DS; break; } if( mod == 1 ) { - disp8 = FETCH(); + disp8 = FETCH(cpustate); ea += (INT32)disp8; } else if( mod == 2 ) { - disp16 = FETCH16(); + disp16 = FETCH16(cpustate); ea += (INT32)disp16; } - if( I.segment_prefix ) - segment = I.segment_override; + if( cpustate->segment_prefix ) + segment = cpustate->segment_override; *out_ea = ea & 0xffff; *out_segment = segment; } } -static UINT32 GetNonTranslatedEA(UINT8 modrm) +static UINT32 GetNonTranslatedEA(i386_state *cpustate,UINT8 modrm) { UINT8 segment; UINT32 ea; - modrm_to_EA( modrm, &ea, &segment ); + modrm_to_EA(cpustate, modrm, &ea, &segment ); return ea; } -static UINT32 GetEA(UINT8 modrm) +static UINT32 GetEA(i386_state *cpustate,UINT8 modrm) { UINT8 segment; UINT32 ea; - modrm_to_EA( modrm, &ea, &segment ); - return i386_translate( segment, ea ); + modrm_to_EA(cpustate, modrm, &ea, &segment ); + return i386_translate(cpustate, segment, ea ); } -static void i386_trap(int irq, int irq_gate) +static void i386_trap(i386_state *cpustate,int irq, int irq_gate) { /* I386 Interrupts/Traps/Faults: * @@ -275,30 +275,30 @@ static void i386_trap(int irq, int irq_gate) UINT32 v1, v2; UINT32 offset; UINT16 segment; - int entry = irq * (I.sreg[CS].d ? 8 : 4); + int entry = irq * (cpustate->sreg[CS].d ? 8 : 4); /* Check if IRQ is out of IDTR's bounds */ - if( entry > I.idtr.limit ) { - fatalerror("I386 Interrupt: IRQ out of IDTR bounds (IRQ: %d, IDTR Limit: %d)", irq, I.idtr.limit); + if( entry > cpustate->idtr.limit ) { + fatalerror("I386 Interrupt: IRQ out of IDTR bounds (IRQ: %d, IDTR Limit: %d)", irq, cpustate->idtr.limit); } - if( !I.sreg[CS].d ) + if( !cpustate->sreg[CS].d ) { /* 16-bit */ - PUSH16( get_flags() & 0xffff ); - PUSH16( I.sreg[CS].selector ); - PUSH16( I.eip ); + PUSH16(cpustate, get_flags(cpustate) & 0xffff ); + PUSH16(cpustate, cpustate->sreg[CS].selector ); + PUSH16(cpustate, cpustate->eip ); - I.sreg[CS].selector = READ16( I.idtr.base + entry + 2 ); - I.eip = READ16( I.idtr.base + entry ); + cpustate->sreg[CS].selector = READ16(cpustate, cpustate->idtr.base + entry + 2 ); + cpustate->eip = READ16(cpustate, cpustate->idtr.base + entry ); /* Interrupts that vector through either interrupt gates or trap gates cause TF */ /* (the trap flag) to be reset after the current value of TF is saved on the stack as part of EFLAGS. */ - I.TF = 0; + cpustate->TF = 0; if (irq_gate) { - I.IF = 0; + cpustate->IF = 0; } } @@ -306,43 +306,43 @@ static void i386_trap(int irq, int irq_gate) { int type; /* 32-bit */ - PUSH32( get_flags() & 0x00fcffff ); - PUSH32( I.sreg[CS].selector ); - PUSH32( I.eip ); + PUSH32(cpustate, get_flags(cpustate) & 0x00fcffff ); + PUSH32(cpustate, cpustate->sreg[CS].selector ); + PUSH32(cpustate, cpustate->eip ); - v1 = READ32( I.idtr.base + entry ); - v2 = READ32( I.idtr.base + entry + 4 ); + v1 = READ32(cpustate, cpustate->idtr.base + entry ); + v2 = READ32(cpustate, cpustate->idtr.base + entry + 4 ); offset = (v2 & 0xffff0000) | (v1 & 0xffff); segment = (v1 >> 16) & 0xffff; type = (v2>>8) & 0x1F; - I.sreg[CS].selector = segment; - I.eip = offset; + cpustate->sreg[CS].selector = segment; + cpustate->eip = offset; /* Interrupts that vector through either interrupt gates or trap gates cause TF */ /* (the trap flag) to be reset after the current value of TF is saved on the stack as part of EFLAGS. */ if ((type == 14) || (type==15)) - I.TF = 0; + cpustate->TF = 0; if (type == 14) { - I.IF = 0; + cpustate->IF = 0; } } - i386_load_segment_descriptor(CS); - CHANGE_PC(I.eip); + i386_load_segment_descriptor(cpustate,CS); + CHANGE_PC(cpustate,cpustate->eip); } -static void i386_check_irq_line(void) +static void i386_check_irq_line(i386_state *cpustate) { /* Check if the interrupts are enabled */ - if ( (I.irq_state) && I.IF ) + if ( (cpustate->irq_state) && cpustate->IF ) { - I.cycles -= 2; - i386_trap(I.irq_callback(I.device, 0), 1); + cpustate->cycles -= 2; + i386_trap(cpustate,cpustate->irq_callback(cpustate->device, 0), 1); } } @@ -351,42 +351,42 @@ static void i386_check_irq_line(void) static UINT8 *cycle_table_rm[X86_NUM_CPUS]; static UINT8 *cycle_table_pm[X86_NUM_CPUS]; -#define CYCLES_NUM(x) (I.cycles -= (x)) +#define CYCLES_NUM(x) (cpustate->cycles -= (x)) -INLINE void CYCLES(int x) +INLINE void CYCLES(i386_state *cpustate,int x) { if (PROTECTED_MODE) { - I.cycles -= I.cycle_table_pm[x]; + cpustate->cycles -= cpustate->cycle_table_pm[x]; } else { - I.cycles -= I.cycle_table_rm[x]; + cpustate->cycles -= cpustate->cycle_table_rm[x]; } } -INLINE void CYCLES_RM(int modrm, int r, int m) +INLINE void CYCLES_RM(i386_state *cpustate,int modrm, int r, int m) { if (modrm >= 0xc0) { if (PROTECTED_MODE) { - I.cycles -= I.cycle_table_pm[r]; + cpustate->cycles -= cpustate->cycle_table_pm[r]; } else { - I.cycles -= I.cycle_table_rm[r]; + cpustate->cycles -= cpustate->cycle_table_rm[r]; } } else { if (PROTECTED_MODE) { - I.cycles -= I.cycle_table_pm[m]; + cpustate->cycles -= cpustate->cycle_table_pm[m]; } else { - I.cycles -= I.cycle_table_rm[m]; + cpustate->cycles -= cpustate->cycle_table_rm[m]; } } } @@ -409,8 +409,8 @@ static void build_cycle_table(void) } /* Forward declarations */ -static void I386OP(decode_opcode)(void); -static void I386OP(decode_two_byte)(void); +static void I386OP(decode_opcode)(i386_state *cpustate); +static void I386OP(decode_two_byte)(i386_state *cpustate); @@ -422,29 +422,31 @@ static void I386OP(decode_two_byte)(void); #include "x87ops.c" #include "i386ops.h" -static void I386OP(decode_opcode)(void) +static void I386OP(decode_opcode)(i386_state *cpustate) { - I.opcode = FETCH(); - if( I.operand_size ) - I.opcode_table1_32[I.opcode](); + cpustate->opcode = FETCH(cpustate); + if( cpustate->operand_size ) + cpustate->opcode_table1_32[cpustate->opcode](cpustate); else - I.opcode_table1_16[I.opcode](); + cpustate->opcode_table1_16[cpustate->opcode](cpustate); } /* Two-byte opcode prefix */ -static void I386OP(decode_two_byte)(void) +static void I386OP(decode_two_byte)(i386_state *cpustate) { - I.opcode = FETCH(); - if( I.operand_size ) - I.opcode_table2_32[I.opcode](); + cpustate->opcode = FETCH(cpustate); + if( cpustate->operand_size ) + cpustate->opcode_table2_32[cpustate->opcode](cpustate); else - I.opcode_table2_16[I.opcode](); + cpustate->opcode_table2_16[cpustate->opcode](cpustate); } /*************************************************************************/ static UINT64 i386_debug_segbase(void *globalref, void *ref, UINT32 params, const UINT64 *param) { + const device_config *device = ref; + i386_state *cpustate = device->token; UINT32 result; I386_SREG seg; @@ -452,7 +454,7 @@ static UINT64 i386_debug_segbase(void *globalref, void *ref, UINT32 params, cons { memset(&seg, 0, sizeof(seg)); seg.selector = (UINT16) param[0]; - i386_load_protected_mode_segment(&seg); + i386_load_protected_mode_segment(cpustate,&seg); result = seg.base; } else @@ -464,6 +466,8 @@ static UINT64 i386_debug_segbase(void *globalref, void *ref, UINT32 params, cons static UINT64 i386_debug_seglimit(void *globalref, void *ref, UINT32 params, const UINT64 *param) { + const device_config *device = ref; + i386_state *cpustate = device->token; UINT32 result = 0; I386_SREG seg; @@ -471,7 +475,7 @@ static UINT64 i386_debug_seglimit(void *globalref, void *ref, UINT32 params, con { memset(&seg, 0, sizeof(seg)); seg.selector = (UINT16) param[0]; - i386_load_protected_mode_segment(&seg); + i386_load_protected_mode_segment(cpustate,&seg); result = seg.limit; } return result; @@ -479,18 +483,20 @@ static UINT64 i386_debug_seglimit(void *globalref, void *ref, UINT32 params, con static CPU_DEBUG_INIT( i386 ) { - symtable_add_function(debug_cpu_get_symtable(device), "segbase", NULL, 1, 1, i386_debug_segbase); - symtable_add_function(debug_cpu_get_symtable(device), "seglimit", NULL, 1, 1, i386_debug_seglimit); + symtable_add_function(debug_cpu_get_symtable(device), "segbase", (void *)device, 1, 1, i386_debug_segbase); + symtable_add_function(debug_cpu_get_symtable(device), "seglimit", (void *)device, 1, 1, i386_debug_seglimit); } /*************************************************************************/ static STATE_POSTLOAD( i386_postload ) { + const device_config *device = param; + i386_state *cpustate = device->token; int i; for (i = 0; i < 6; i++) - i386_load_segment_descriptor(i); - CHANGE_PC(I.eip); + i386_load_segment_descriptor(cpustate,i); + CHANGE_PC(cpustate,cpustate->eip); } static CPU_INIT( i386 ) @@ -499,6 +505,7 @@ static CPU_INIT( i386 ) static const int regs8[8] = {AL,CL,DL,BL,AH,CH,DH,BH}; static const int regs16[8] = {AX,CX,DX,BX,SP,BP,SI,DI}; static const int regs32[8] = {EAX,ECX,EDX,EBX,ESP,EBP,ESI,EDI}; + i386_state *cpustate = device->token; build_cycle_table(); @@ -521,76 +528,76 @@ static CPU_INIT( i386 ) i386_MODRM_table[i].rm.d = regs32[i & 0x7]; } - I.irq_callback = irqcallback; - I.device = device; - I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); - I.io = memory_find_address_space(device, ADDRESS_SPACE_IO); - - state_save_register_device_item_array(device, 0, I.reg.d); - state_save_register_device_item(device, 0, I.sreg[ES].selector); - state_save_register_device_item(device, 0, I.sreg[ES].base); - state_save_register_device_item(device, 0, I.sreg[ES].limit); - state_save_register_device_item(device, 0, I.sreg[ES].flags); - state_save_register_device_item(device, 0, I.sreg[CS].selector); - state_save_register_device_item(device, 0, I.sreg[CS].base); - state_save_register_device_item(device, 0, I.sreg[CS].limit); - state_save_register_device_item(device, 0, I.sreg[CS].flags); - state_save_register_device_item(device, 0, I.sreg[SS].selector); - state_save_register_device_item(device, 0, I.sreg[SS].base); - state_save_register_device_item(device, 0, I.sreg[SS].limit); - state_save_register_device_item(device, 0, I.sreg[SS].flags); - state_save_register_device_item(device, 0, I.sreg[DS].selector); - state_save_register_device_item(device, 0, I.sreg[DS].base); - state_save_register_device_item(device, 0, I.sreg[DS].limit); - state_save_register_device_item(device, 0, I.sreg[DS].flags); - state_save_register_device_item(device, 0, I.sreg[FS].selector); - state_save_register_device_item(device, 0, I.sreg[FS].base); - state_save_register_device_item(device, 0, I.sreg[FS].limit); - state_save_register_device_item(device, 0, I.sreg[FS].flags); - state_save_register_device_item(device, 0, I.sreg[GS].selector); - state_save_register_device_item(device, 0, I.sreg[GS].base); - state_save_register_device_item(device, 0, I.sreg[GS].limit); - state_save_register_device_item(device, 0, I.sreg[GS].flags); - state_save_register_device_item(device, 0, I.eip); - state_save_register_device_item(device, 0, I.prev_eip); - state_save_register_device_item(device, 0, I.CF); - state_save_register_device_item(device, 0, I.DF); - state_save_register_device_item(device, 0, I.SF); - state_save_register_device_item(device, 0, I.OF); - state_save_register_device_item(device, 0, I.ZF); - state_save_register_device_item(device, 0, I.PF); - state_save_register_device_item(device, 0, I.AF); - state_save_register_device_item(device, 0, I.IF); - state_save_register_device_item(device, 0, I.TF); - state_save_register_device_item_array(device, 0, I.cr); - state_save_register_device_item_array(device, 0, I.dr); - state_save_register_device_item_array(device, 0, I.tr); - state_save_register_device_item(device, 0, I.idtr.base); - state_save_register_device_item(device, 0, I.idtr.limit); - state_save_register_device_item(device, 0, I.gdtr.base); - state_save_register_device_item(device, 0, I.gdtr.limit); - state_save_register_device_item(device, 0, I.task.base); - state_save_register_device_item(device, 0, I.task.segment); - state_save_register_device_item(device, 0, I.task.limit); - state_save_register_device_item(device, 0, I.task.flags); - state_save_register_device_item(device, 0, I.ldtr.base); - state_save_register_device_item(device, 0, I.ldtr.segment); - state_save_register_device_item(device, 0, I.ldtr.limit); - state_save_register_device_item(device, 0, I.ldtr.flags); - state_save_register_device_item(device, 0, I.irq_state); - state_save_register_device_item(device, 0, I.performed_intersegment_jump); - state_save_register_postload(device->machine, i386_postload, NULL); + cpustate->irq_callback = irqcallback; + cpustate->device = device; + cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); + cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO); + + state_save_register_device_item_array(device, 0, cpustate->reg.d); + state_save_register_device_item(device, 0, cpustate->sreg[ES].selector); + state_save_register_device_item(device, 0, cpustate->sreg[ES].base); + state_save_register_device_item(device, 0, cpustate->sreg[ES].limit); + state_save_register_device_item(device, 0, cpustate->sreg[ES].flags); + state_save_register_device_item(device, 0, cpustate->sreg[CS].selector); + state_save_register_device_item(device, 0, cpustate->sreg[CS].base); + state_save_register_device_item(device, 0, cpustate->sreg[CS].limit); + state_save_register_device_item(device, 0, cpustate->sreg[CS].flags); + state_save_register_device_item(device, 0, cpustate->sreg[SS].selector); + state_save_register_device_item(device, 0, cpustate->sreg[SS].base); + state_save_register_device_item(device, 0, cpustate->sreg[SS].limit); + state_save_register_device_item(device, 0, cpustate->sreg[SS].flags); + state_save_register_device_item(device, 0, cpustate->sreg[DS].selector); + state_save_register_device_item(device, 0, cpustate->sreg[DS].base); + state_save_register_device_item(device, 0, cpustate->sreg[DS].limit); + state_save_register_device_item(device, 0, cpustate->sreg[DS].flags); + state_save_register_device_item(device, 0, cpustate->sreg[FS].selector); + state_save_register_device_item(device, 0, cpustate->sreg[FS].base); + state_save_register_device_item(device, 0, cpustate->sreg[FS].limit); + state_save_register_device_item(device, 0, cpustate->sreg[FS].flags); + state_save_register_device_item(device, 0, cpustate->sreg[GS].selector); + state_save_register_device_item(device, 0, cpustate->sreg[GS].base); + state_save_register_device_item(device, 0, cpustate->sreg[GS].limit); + state_save_register_device_item(device, 0, cpustate->sreg[GS].flags); + state_save_register_device_item(device, 0, cpustate->eip); + state_save_register_device_item(device, 0, cpustate->prev_eip); + state_save_register_device_item(device, 0, cpustate->CF); + state_save_register_device_item(device, 0, cpustate->DF); + state_save_register_device_item(device, 0, cpustate->SF); + state_save_register_device_item(device, 0, cpustate->OF); + state_save_register_device_item(device, 0, cpustate->ZF); + state_save_register_device_item(device, 0, cpustate->PF); + state_save_register_device_item(device, 0, cpustate->AF); + state_save_register_device_item(device, 0, cpustate->IF); + state_save_register_device_item(device, 0, cpustate->TF); + state_save_register_device_item_array(device, 0, cpustate->cr); + state_save_register_device_item_array(device, 0, cpustate->dr); + state_save_register_device_item_array(device, 0, cpustate->tr); + state_save_register_device_item(device, 0, cpustate->idtr.base); + state_save_register_device_item(device, 0, cpustate->idtr.limit); + state_save_register_device_item(device, 0, cpustate->gdtr.base); + state_save_register_device_item(device, 0, cpustate->gdtr.limit); + state_save_register_device_item(device, 0, cpustate->task.base); + state_save_register_device_item(device, 0, cpustate->task.segment); + state_save_register_device_item(device, 0, cpustate->task.limit); + state_save_register_device_item(device, 0, cpustate->task.flags); + state_save_register_device_item(device, 0, cpustate->ldtr.base); + state_save_register_device_item(device, 0, cpustate->ldtr.segment); + state_save_register_device_item(device, 0, cpustate->ldtr.limit); + state_save_register_device_item(device, 0, cpustate->ldtr.flags); + state_save_register_device_item(device, 0, cpustate->irq_state); + state_save_register_device_item(device, 0, cpustate->performed_intersegment_jump); + state_save_register_postload(device->machine, i386_postload, (void *)device); } -static void build_opcode_table(UINT32 features) +static void build_opcode_table(i386_state *cpustate, UINT32 features) { int i; for (i=0; i < 256; i++) { - I.opcode_table1_16[i] = I386OP(invalid); - I.opcode_table1_32[i] = I386OP(invalid); - I.opcode_table2_16[i] = I386OP(invalid); - I.opcode_table2_32[i] = I386OP(invalid); + cpustate->opcode_table1_16[i] = I386OP(invalid); + cpustate->opcode_table1_32[i] = I386OP(invalid); + cpustate->opcode_table2_16[i] = I386OP(invalid); + cpustate->opcode_table2_32[i] = I386OP(invalid); } for (i=0; i < sizeof(x86_opcode_table)/sizeof(X86_OPCODE); i++) @@ -601,13 +608,13 @@ static void build_opcode_table(UINT32 features) { if (op->flags & OP_2BYTE) { - I.opcode_table2_32[op->opcode] = op->handler32; - I.opcode_table2_16[op->opcode] = op->handler16; + cpustate->opcode_table2_32[op->opcode] = op->handler32; + cpustate->opcode_table2_16[op->opcode] = op->handler16; } else { - I.opcode_table1_32[op->opcode] = op->handler32; - I.opcode_table1_16[op->opcode] = op->handler16; + cpustate->opcode_table1_32[op->opcode] = op->handler32; + cpustate->opcode_table1_16[op->opcode] = op->handler16; } } } @@ -615,148 +622,139 @@ static void build_opcode_table(UINT32 features) static CPU_RESET( i386 ) { + i386_state *cpustate = device->token; cpu_irq_callback save_irqcallback; - save_irqcallback = I.irq_callback; - memset( &I, 0, sizeof(I386_REGS) ); - I.irq_callback = save_irqcallback; - I.device = device; - I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); - I.io = memory_find_address_space(device, ADDRESS_SPACE_IO); + save_irqcallback = cpustate->irq_callback; + memset( cpustate, 0, sizeof(*cpustate) ); + cpustate->irq_callback = save_irqcallback; + cpustate->device = device; + cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); + cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO); - I.sreg[CS].selector = 0xf000; - I.sreg[CS].base = 0xffff0000; - I.sreg[CS].limit = 0xffff; + cpustate->sreg[CS].selector = 0xf000; + cpustate->sreg[CS].base = 0xffff0000; + cpustate->sreg[CS].limit = 0xffff; - I.sreg[DS].base = I.sreg[ES].base = I.sreg[FS].base = I.sreg[GS].base = I.sreg[SS].base = 0x00000000; - I.sreg[DS].limit = I.sreg[ES].limit = I.sreg[FS].limit = I.sreg[GS].limit = I.sreg[SS].limit = 0xffff; - I.sreg[DS].flags = I.sreg[ES].flags = I.sreg[FS].flags = I.sreg[GS].flags = I.sreg[SS].flags = 0x0092; + cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000; + cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff; + cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092; - I.idtr.base = 0; - I.idtr.limit = 0x3ff; + cpustate->idtr.base = 0; + cpustate->idtr.limit = 0x3ff; - I.a20_mask = ~0; + cpustate->a20_mask = ~0; - I.cr[0] = 0; - I.eflags = 0; - I.eip = 0xfff0; + cpustate->cr[0] = 0; + cpustate->eflags = 0; + cpustate->eip = 0xfff0; REG32(EAX) = 0x0308; // Intel 386, stepping D1 REG32(EDX) = 0; - build_opcode_table(OP_I386); - I.cycle_table_rm = cycle_table_rm[CPU_CYCLES_I386]; - I.cycle_table_pm = cycle_table_pm[CPU_CYCLES_I386]; + build_opcode_table(cpustate, OP_I386); + cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_I386]; + cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_I386]; - CHANGE_PC(I.eip); + CHANGE_PC(cpustate,cpustate->eip); } -static CPU_GET_CONTEXT( i386 ) +static void i386_set_irq_line(i386_state *cpustate,int irqline, int state) { - if(dst) { - *(I386_REGS *)dst = I; - } -} - -static CPU_SET_CONTEXT( i386 ) -{ - if(src) { - I = *(I386_REGS *)src; - } - - CHANGE_PC(I.eip); -} - -static void i386_set_irq_line(int irqline, int state) -{ - if (state != CLEAR_LINE && I.halted) + if (state != CLEAR_LINE && cpustate->halted) { - I.halted = 0; + cpustate->halted = 0; } if ( irqline == INPUT_LINE_NMI ) { /* NMI (I do not think that this is 100% right) */ if ( state ) - i386_trap(2, 1); + i386_trap(cpustate,2, 1); } else { - I.irq_state = state; + cpustate->irq_state = state; } } -static void i386_set_a20_line(int state) +static void i386_set_a20_line(i386_state *cpustate,int state) { if (state) { - I.a20_mask = ~0; + cpustate->a20_mask = ~0; } else { - I.a20_mask = ~(1 << 20); + cpustate->a20_mask = ~(1 << 20); } } static CPU_EXECUTE( i386 ) { - I.cycles = cycles; - I.base_cycles = cycles; - CHANGE_PC(I.eip); + i386_state *cpustate = device->token; - if (I.halted) + cpustate->cycles = cycles; + cpustate->base_cycles = cycles; + CHANGE_PC(cpustate,cpustate->eip); + + if (cpustate->halted) { - I.tsc += cycles; + cpustate->tsc += cycles; return cycles; } - while( I.cycles > 0 ) + while( cpustate->cycles > 0 ) { - I.operand_size = I.sreg[CS].d; - I.address_size = I.sreg[CS].d; + cpustate->operand_size = cpustate->sreg[CS].d; + cpustate->address_size = cpustate->sreg[CS].d; - I.segment_prefix = 0; - I.prev_eip = I.eip; + cpustate->segment_prefix = 0; + cpustate->prev_eip = cpustate->eip; - debugger_instruction_hook(device, I.pc); + debugger_instruction_hook(device, cpustate->pc); - i386_check_irq_line(); - I386OP(decode_opcode)(); + i386_check_irq_line(cpustate); + I386OP(decode_opcode)(cpustate); } - I.tsc += (cycles - I.cycles); + cpustate->tsc += (cycles - cpustate->cycles); - return cycles - I.cycles; + return cycles - cpustate->cycles; } /*************************************************************************/ static CPU_TRANSLATE( i386 ) { + i386_state *cpustate = device->token; int result = 1; if (space == ADDRESS_SPACE_PROGRAM) { - if (I.cr[0] & 0x80000000) - result = translate_address(address); - *address &= I.a20_mask; + if (cpustate->cr[0] & 0x80000000) + result = translate_address(cpustate,address); + *address &= cpustate->a20_mask; } return result; } static CPU_DISASSEMBLE( i386 ) { - return i386_dasm_one(buffer, pc, oprom, I.sreg[CS].d ? 32 : 16); + i386_state *cpustate = device->token; + return i386_dasm_one(buffer, pc, oprom, cpustate->sreg[CS].d ? 32 : 16); } static CPU_SET_INFO( i386 ) { + i386_state *cpustate = device->token; + if (state == CPUINFO_INT_INPUT_STATE+INPUT_LINE_A20) { - i386_set_a20_line(info->i); + i386_set_a20_line(cpustate,info->i); return; } if (state >= CPUINFO_INT_INPUT_STATE && state <= CPUINFO_INT_INPUT_STATE + MAX_INPUT_LINES) { - i386_set_irq_line(state-CPUINFO_INT_INPUT_STATE, info->i); + i386_set_irq_line(cpustate,state-CPUINFO_INT_INPUT_STATE, info->i); return; } @@ -764,8 +762,8 @@ static CPU_SET_INFO( i386 ) { /* --- the following bits of info are set as 64-bit signed integers --- */ case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + I386_PC: I.pc = info->i; break; - case CPUINFO_INT_REGISTER + I386_EIP: I.eip = info->i; CHANGE_PC(I.eip); break; + case CPUINFO_INT_REGISTER + I386_PC: cpustate->pc = info->i; break; + case CPUINFO_INT_REGISTER + I386_EIP: cpustate->eip = info->i; CHANGE_PC(cpustate,cpustate->eip); break; case CPUINFO_INT_REGISTER + I386_AL: REG8(AL) = info->i; break; case CPUINFO_INT_REGISTER + I386_AH: REG8(AH) = info->i; break; case CPUINFO_INT_REGISTER + I386_BL: REG8(BL) = info->i; break; @@ -782,7 +780,7 @@ static CPU_SET_INFO( i386 ) case CPUINFO_INT_REGISTER + I386_DI: REG16(DI) = info->i; break; case CPUINFO_INT_REGISTER + I386_BP: REG16(BP) = info->i; break; case CPUINFO_INT_REGISTER + I386_SP: REG16(SP) = info->i; break; - case CPUINFO_INT_REGISTER + I386_IP: I.eip = (I.eip & ~0xFFFF) | (info->i & 0xFFFF); CHANGE_PC(I.eip); break; + case CPUINFO_INT_REGISTER + I386_IP: cpustate->eip = (cpustate->eip & ~0xFFFF) | (info->i & 0xFFFF); CHANGE_PC(cpustate,cpustate->eip); break; case CPUINFO_INT_REGISTER + I386_EAX: REG32(EAX) = info->i; break; case CPUINFO_INT_REGISTER + I386_EBX: REG32(EBX) = info->i; break; case CPUINFO_INT_REGISTER + I386_ECX: REG32(ECX) = info->i; break; @@ -792,66 +790,68 @@ static CPU_SET_INFO( i386 ) case CPUINFO_INT_REGISTER + I386_ESP: REG32(ESP) = info->i; break; case CPUINFO_INT_REGISTER + I386_ESI: REG32(ESI) = info->i; break; case CPUINFO_INT_REGISTER + I386_EDI: REG32(EDI) = info->i; break; - case CPUINFO_INT_REGISTER + I386_EFLAGS: I.eflags = info->i; break; - case CPUINFO_INT_REGISTER + I386_CS: I.sreg[CS].selector = info->i & 0xffff; i386_load_segment_descriptor(CS); break; - case CPUINFO_INT_REGISTER + I386_CS_BASE: I.sreg[CS].base = info->i; break; - case CPUINFO_INT_REGISTER + I386_CS_LIMIT: I.sreg[CS].limit = info->i; break; - case CPUINFO_INT_REGISTER + I386_CS_FLAGS: I.sreg[CS].flags = info->i & 0xf0ff; break; - case CPUINFO_INT_REGISTER + I386_SS: I.sreg[SS].selector = info->i & 0xffff; i386_load_segment_descriptor(SS); break; - case CPUINFO_INT_REGISTER + I386_SS_BASE: I.sreg[SS].base = info->i; break; - case CPUINFO_INT_REGISTER + I386_SS_LIMIT: I.sreg[SS].limit = info->i; break; - case CPUINFO_INT_REGISTER + I386_SS_FLAGS: I.sreg[SS].flags = info->i & 0xf0ff; break; - case CPUINFO_INT_REGISTER + I386_DS: I.sreg[DS].selector = info->i & 0xffff; i386_load_segment_descriptor(DS); break; - case CPUINFO_INT_REGISTER + I386_DS_BASE: I.sreg[DS].base = info->i; break; - case CPUINFO_INT_REGISTER + I386_DS_LIMIT: I.sreg[DS].limit = info->i; break; - case CPUINFO_INT_REGISTER + I386_DS_FLAGS: I.sreg[DS].flags = info->i & 0xf0ff; break; - case CPUINFO_INT_REGISTER + I386_ES: I.sreg[ES].selector = info->i & 0xffff; i386_load_segment_descriptor(ES); break; - case CPUINFO_INT_REGISTER + I386_ES_BASE: I.sreg[ES].base = info->i; break; - case CPUINFO_INT_REGISTER + I386_ES_LIMIT: I.sreg[ES].limit = info->i; break; - case CPUINFO_INT_REGISTER + I386_ES_FLAGS: I.sreg[ES].flags = info->i & 0xf0ff; break; - case CPUINFO_INT_REGISTER + I386_FS: I.sreg[FS].selector = info->i & 0xffff; i386_load_segment_descriptor(FS); break; - case CPUINFO_INT_REGISTER + I386_FS_BASE: I.sreg[FS].base = info->i; break; - case CPUINFO_INT_REGISTER + I386_FS_LIMIT: I.sreg[FS].limit = info->i; break; - case CPUINFO_INT_REGISTER + I386_FS_FLAGS: I.sreg[FS].flags = info->i & 0xf0ff; break; - case CPUINFO_INT_REGISTER + I386_GS: I.sreg[GS].selector = info->i & 0xffff; i386_load_segment_descriptor(GS); break; - case CPUINFO_INT_REGISTER + I386_GS_BASE: I.sreg[GS].base = info->i; break; - case CPUINFO_INT_REGISTER + I386_GS_LIMIT: I.sreg[GS].limit = info->i; break; - case CPUINFO_INT_REGISTER + I386_GS_FLAGS: I.sreg[GS].flags = info->i & 0xf0ff; break; - case CPUINFO_INT_REGISTER + I386_CR0: I.cr[0] = info->i; break; - case CPUINFO_INT_REGISTER + I386_CR1: I.cr[1] = info->i; break; - case CPUINFO_INT_REGISTER + I386_CR2: I.cr[2] = info->i; break; - case CPUINFO_INT_REGISTER + I386_CR3: I.cr[3] = info->i; break; - case CPUINFO_INT_REGISTER + I386_DR0: I.dr[0] = info->i; break; - case CPUINFO_INT_REGISTER + I386_DR1: I.dr[1] = info->i; break; - case CPUINFO_INT_REGISTER + I386_DR2: I.dr[2] = info->i; break; - case CPUINFO_INT_REGISTER + I386_DR3: I.dr[3] = info->i; break; - case CPUINFO_INT_REGISTER + I386_DR4: I.dr[4] = info->i; break; - case CPUINFO_INT_REGISTER + I386_DR5: I.dr[5] = info->i; break; - case CPUINFO_INT_REGISTER + I386_DR6: I.dr[6] = info->i; break; - case CPUINFO_INT_REGISTER + I386_DR7: I.dr[7] = info->i; break; - case CPUINFO_INT_REGISTER + I386_TR6: I.tr[6] = info->i; break; - case CPUINFO_INT_REGISTER + I386_TR7: I.tr[7] = info->i; break; - case CPUINFO_INT_REGISTER + I386_GDTR_BASE: I.gdtr.base = info->i; break; - case CPUINFO_INT_REGISTER + I386_GDTR_LIMIT: I.gdtr.limit = info->i & 0xffff; break; - case CPUINFO_INT_REGISTER + I386_IDTR_BASE: I.idtr.base = info->i; break; - case CPUINFO_INT_REGISTER + I386_IDTR_LIMIT: I.idtr.limit = info->i & 0xffff; break; - case CPUINFO_INT_REGISTER + I386_TR: I.task.segment = info->i & 0xffff; break; - case CPUINFO_INT_REGISTER + I386_TR_BASE: I.task.base = info->i; break; - case CPUINFO_INT_REGISTER + I386_TR_LIMIT: I.task.limit = info->i; break; - case CPUINFO_INT_REGISTER + I386_TR_FLAGS: I.task.flags = info->i & 0xf0ff; break; - case CPUINFO_INT_REGISTER + I386_LDTR: I.ldtr.segment = info->i & 0xffff; break; - case CPUINFO_INT_REGISTER + I386_LDTR_BASE: I.ldtr.base = info->i; break; - case CPUINFO_INT_REGISTER + I386_LDTR_LIMIT: I.ldtr.limit = info->i; break; - case CPUINFO_INT_REGISTER + I386_LDTR_FLAGS: I.ldtr.flags = info->i & 0xf0ff; break; + case CPUINFO_INT_REGISTER + I386_EFLAGS: cpustate->eflags = info->i; break; + case CPUINFO_INT_REGISTER + I386_CS: cpustate->sreg[CS].selector = info->i & 0xffff; i386_load_segment_descriptor(cpustate,CS); break; + case CPUINFO_INT_REGISTER + I386_CS_BASE: cpustate->sreg[CS].base = info->i; break; + case CPUINFO_INT_REGISTER + I386_CS_LIMIT: cpustate->sreg[CS].limit = info->i; break; + case CPUINFO_INT_REGISTER + I386_CS_FLAGS: cpustate->sreg[CS].flags = info->i & 0xf0ff; break; + case CPUINFO_INT_REGISTER + I386_SS: cpustate->sreg[SS].selector = info->i & 0xffff; i386_load_segment_descriptor(cpustate,SS); break; + case CPUINFO_INT_REGISTER + I386_SS_BASE: cpustate->sreg[SS].base = info->i; break; + case CPUINFO_INT_REGISTER + I386_SS_LIMIT: cpustate->sreg[SS].limit = info->i; break; + case CPUINFO_INT_REGISTER + I386_SS_FLAGS: cpustate->sreg[SS].flags = info->i & 0xf0ff; break; + case CPUINFO_INT_REGISTER + I386_DS: cpustate->sreg[DS].selector = info->i & 0xffff; i386_load_segment_descriptor(cpustate,DS); break; + case CPUINFO_INT_REGISTER + I386_DS_BASE: cpustate->sreg[DS].base = info->i; break; + case CPUINFO_INT_REGISTER + I386_DS_LIMIT: cpustate->sreg[DS].limit = info->i; break; + case CPUINFO_INT_REGISTER + I386_DS_FLAGS: cpustate->sreg[DS].flags = info->i & 0xf0ff; break; + case CPUINFO_INT_REGISTER + I386_ES: cpustate->sreg[ES].selector = info->i & 0xffff; i386_load_segment_descriptor(cpustate,ES); break; + case CPUINFO_INT_REGISTER + I386_ES_BASE: cpustate->sreg[ES].base = info->i; break; + case CPUINFO_INT_REGISTER + I386_ES_LIMIT: cpustate->sreg[ES].limit = info->i; break; + case CPUINFO_INT_REGISTER + I386_ES_FLAGS: cpustate->sreg[ES].flags = info->i & 0xf0ff; break; + case CPUINFO_INT_REGISTER + I386_FS: cpustate->sreg[FS].selector = info->i & 0xffff; i386_load_segment_descriptor(cpustate,FS); break; + case CPUINFO_INT_REGISTER + I386_FS_BASE: cpustate->sreg[FS].base = info->i; break; + case CPUINFO_INT_REGISTER + I386_FS_LIMIT: cpustate->sreg[FS].limit = info->i; break; + case CPUINFO_INT_REGISTER + I386_FS_FLAGS: cpustate->sreg[FS].flags = info->i & 0xf0ff; break; + case CPUINFO_INT_REGISTER + I386_GS: cpustate->sreg[GS].selector = info->i & 0xffff; i386_load_segment_descriptor(cpustate,GS); break; + case CPUINFO_INT_REGISTER + I386_GS_BASE: cpustate->sreg[GS].base = info->i; break; + case CPUINFO_INT_REGISTER + I386_GS_LIMIT: cpustate->sreg[GS].limit = info->i; break; + case CPUINFO_INT_REGISTER + I386_GS_FLAGS: cpustate->sreg[GS].flags = info->i & 0xf0ff; break; + case CPUINFO_INT_REGISTER + I386_CR0: cpustate->cr[0] = info->i; break; + case CPUINFO_INT_REGISTER + I386_CR1: cpustate->cr[1] = info->i; break; + case CPUINFO_INT_REGISTER + I386_CR2: cpustate->cr[2] = info->i; break; + case CPUINFO_INT_REGISTER + I386_CR3: cpustate->cr[3] = info->i; break; + case CPUINFO_INT_REGISTER + I386_DR0: cpustate->dr[0] = info->i; break; + case CPUINFO_INT_REGISTER + I386_DR1: cpustate->dr[1] = info->i; break; + case CPUINFO_INT_REGISTER + I386_DR2: cpustate->dr[2] = info->i; break; + case CPUINFO_INT_REGISTER + I386_DR3: cpustate->dr[3] = info->i; break; + case CPUINFO_INT_REGISTER + I386_DR4: cpustate->dr[4] = info->i; break; + case CPUINFO_INT_REGISTER + I386_DR5: cpustate->dr[5] = info->i; break; + case CPUINFO_INT_REGISTER + I386_DR6: cpustate->dr[6] = info->i; break; + case CPUINFO_INT_REGISTER + I386_DR7: cpustate->dr[7] = info->i; break; + case CPUINFO_INT_REGISTER + I386_TR6: cpustate->tr[6] = info->i; break; + case CPUINFO_INT_REGISTER + I386_TR7: cpustate->tr[7] = info->i; break; + case CPUINFO_INT_REGISTER + I386_GDTR_BASE: cpustate->gdtr.base = info->i; break; + case CPUINFO_INT_REGISTER + I386_GDTR_LIMIT: cpustate->gdtr.limit = info->i & 0xffff; break; + case CPUINFO_INT_REGISTER + I386_IDTR_BASE: cpustate->idtr.base = info->i; break; + case CPUINFO_INT_REGISTER + I386_IDTR_LIMIT: cpustate->idtr.limit = info->i & 0xffff; break; + case CPUINFO_INT_REGISTER + I386_TR: cpustate->task.segment = info->i & 0xffff; break; + case CPUINFO_INT_REGISTER + I386_TR_BASE: cpustate->task.base = info->i; break; + case CPUINFO_INT_REGISTER + I386_TR_LIMIT: cpustate->task.limit = info->i; break; + case CPUINFO_INT_REGISTER + I386_TR_FLAGS: cpustate->task.flags = info->i & 0xf0ff; break; + case CPUINFO_INT_REGISTER + I386_LDTR: cpustate->ldtr.segment = info->i & 0xffff; break; + case CPUINFO_INT_REGISTER + I386_LDTR_BASE: cpustate->ldtr.base = info->i; break; + case CPUINFO_INT_REGISTER + I386_LDTR_LIMIT: cpustate->ldtr.limit = info->i; break; + case CPUINFO_INT_REGISTER + I386_LDTR_FLAGS: cpustate->ldtr.flags = info->i & 0xf0ff; break; } } CPU_GET_INFO( i386 ) { + i386_state *cpustate = (device != NULL) ? device->token : NULL; + switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(I386_REGS); break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(i386_state); break; case CPUINFO_INT_INPUT_LINES: info->i = 32; break; case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; @@ -879,8 +879,8 @@ CPU_GET_INFO( i386 ) case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break; case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + I386_PC: info->i = I.pc; break; - case CPUINFO_INT_REGISTER + I386_EIP: info->i = I.eip; break; + case CPUINFO_INT_REGISTER + I386_PC: info->i = cpustate->pc; break; + case CPUINFO_INT_REGISTER + I386_EIP: info->i = cpustate->eip; break; case CPUINFO_INT_REGISTER + I386_AL: info->i = REG8(AL); break; case CPUINFO_INT_REGISTER + I386_AH: info->i = REG8(AH); break; case CPUINFO_INT_REGISTER + I386_BL: info->i = REG8(BL); break; @@ -897,7 +897,7 @@ CPU_GET_INFO( i386 ) case CPUINFO_INT_REGISTER + I386_DI: info->i = REG16(DI); break; case CPUINFO_INT_REGISTER + I386_BP: info->i = REG16(BP); break; case CPUINFO_INT_REGISTER + I386_SP: info->i = REG16(SP); break; - case CPUINFO_INT_REGISTER + I386_IP: info->i = I.eip & 0xFFFF; break; + case CPUINFO_INT_REGISTER + I386_IP: info->i = cpustate->eip & 0xFFFF; break; case CPUINFO_INT_REGISTER + I386_EAX: info->i = REG32(EAX); break; case CPUINFO_INT_REGISTER + I386_EBX: info->i = REG32(EBX); break; case CPUINFO_INT_REGISTER + I386_ECX: info->i = REG32(ECX); break; @@ -906,67 +906,67 @@ CPU_GET_INFO( i386 ) case CPUINFO_INT_REGISTER + I386_ESP: info->i = REG32(ESP); break; case CPUINFO_INT_REGISTER + I386_ESI: info->i = REG32(ESI); break; case CPUINFO_INT_REGISTER + I386_EDI: info->i = REG32(EDI); break; - case CPUINFO_INT_REGISTER + I386_EFLAGS: info->i = I.eflags; break; - case CPUINFO_INT_REGISTER + I386_CS: info->i = I.sreg[CS].selector; break; - case CPUINFO_INT_REGISTER + I386_CS_BASE: info->i = I.sreg[CS].base; break; - case CPUINFO_INT_REGISTER + I386_CS_LIMIT: info->i = I.sreg[CS].limit; break; - case CPUINFO_INT_REGISTER + I386_CS_FLAGS: info->i = I.sreg[CS].flags; break; - case CPUINFO_INT_REGISTER + I386_SS: info->i = I.sreg[SS].selector; break; - case CPUINFO_INT_REGISTER + I386_SS_BASE: info->i = I.sreg[SS].base; break; - case CPUINFO_INT_REGISTER + I386_SS_LIMIT: info->i = I.sreg[SS].limit; break; - case CPUINFO_INT_REGISTER + I386_SS_FLAGS: info->i = I.sreg[SS].flags; break; - case CPUINFO_INT_REGISTER + I386_DS: info->i = I.sreg[DS].selector; break; - case CPUINFO_INT_REGISTER + I386_DS_BASE: info->i = I.sreg[DS].base; break; - case CPUINFO_INT_REGISTER + I386_DS_LIMIT: info->i = I.sreg[DS].limit; break; - case CPUINFO_INT_REGISTER + I386_DS_FLAGS: info->i = I.sreg[DS].flags; break; - case CPUINFO_INT_REGISTER + I386_ES: info->i = I.sreg[ES].selector; break; - case CPUINFO_INT_REGISTER + I386_ES_BASE: info->i = I.sreg[ES].base; break; - case CPUINFO_INT_REGISTER + I386_ES_LIMIT: info->i = I.sreg[ES].limit; break; - case CPUINFO_INT_REGISTER + I386_ES_FLAGS: info->i = I.sreg[ES].flags; break; - case CPUINFO_INT_REGISTER + I386_FS: info->i = I.sreg[FS].selector; break; - case CPUINFO_INT_REGISTER + I386_FS_BASE: info->i = I.sreg[FS].base; break; - case CPUINFO_INT_REGISTER + I386_FS_LIMIT: info->i = I.sreg[FS].limit; break; - case CPUINFO_INT_REGISTER + I386_FS_FLAGS: info->i = I.sreg[FS].flags; break; - case CPUINFO_INT_REGISTER + I386_GS: info->i = I.sreg[GS].selector; break; - case CPUINFO_INT_REGISTER + I386_GS_BASE: info->i = I.sreg[GS].base; break; - case CPUINFO_INT_REGISTER + I386_GS_LIMIT: info->i = I.sreg[GS].limit; break; - case CPUINFO_INT_REGISTER + I386_GS_FLAGS: info->i = I.sreg[GS].flags; break; - case CPUINFO_INT_REGISTER + I386_CR0: info->i = I.cr[0]; break; - case CPUINFO_INT_REGISTER + I386_CR1: info->i = I.cr[1]; break; - case CPUINFO_INT_REGISTER + I386_CR2: info->i = I.cr[2]; break; - case CPUINFO_INT_REGISTER + I386_CR3: info->i = I.cr[3]; break; - case CPUINFO_INT_REGISTER + I386_DR0: info->i = I.dr[0]; break; - case CPUINFO_INT_REGISTER + I386_DR1: info->i = I.dr[1]; break; - case CPUINFO_INT_REGISTER + I386_DR2: info->i = I.dr[2]; break; - case CPUINFO_INT_REGISTER + I386_DR3: info->i = I.dr[3]; break; - case CPUINFO_INT_REGISTER + I386_DR4: info->i = I.dr[4]; break; - case CPUINFO_INT_REGISTER + I386_DR5: info->i = I.dr[5]; break; - case CPUINFO_INT_REGISTER + I386_DR6: info->i = I.dr[6]; break; - case CPUINFO_INT_REGISTER + I386_DR7: info->i = I.dr[7]; break; - case CPUINFO_INT_REGISTER + I386_TR6: info->i = I.tr[6]; break; - case CPUINFO_INT_REGISTER + I386_TR7: info->i = I.tr[7]; break; - case CPUINFO_INT_REGISTER + I386_GDTR_BASE: info->i = I.gdtr.base; break; - case CPUINFO_INT_REGISTER + I386_GDTR_LIMIT: info->i = I.gdtr.limit; break; - case CPUINFO_INT_REGISTER + I386_IDTR_BASE: info->i = I.idtr.base; break; - case CPUINFO_INT_REGISTER + I386_IDTR_LIMIT: info->i = I.idtr.limit; break; - case CPUINFO_INT_REGISTER + I386_TR: info->i = I.task.segment; break; - case CPUINFO_INT_REGISTER + I386_TR_BASE: info->i = I.task.base; break; - case CPUINFO_INT_REGISTER + I386_TR_LIMIT: info->i = I.task.limit; break; - case CPUINFO_INT_REGISTER + I386_TR_FLAGS: info->i = I.task.flags; break; - case CPUINFO_INT_REGISTER + I386_LDTR: info->i = I.ldtr.segment; break; - case CPUINFO_INT_REGISTER + I386_LDTR_BASE: info->i = I.ldtr.base; break; - case CPUINFO_INT_REGISTER + I386_LDTR_LIMIT: info->i = I.ldtr.limit; break; - case CPUINFO_INT_REGISTER + I386_LDTR_FLAGS: info->i = I.ldtr.flags; break; + case CPUINFO_INT_REGISTER + I386_EFLAGS: info->i = cpustate->eflags; break; + case CPUINFO_INT_REGISTER + I386_CS: info->i = cpustate->sreg[CS].selector; break; + case CPUINFO_INT_REGISTER + I386_CS_BASE: info->i = cpustate->sreg[CS].base; break; + case CPUINFO_INT_REGISTER + I386_CS_LIMIT: info->i = cpustate->sreg[CS].limit; break; + case CPUINFO_INT_REGISTER + I386_CS_FLAGS: info->i = cpustate->sreg[CS].flags; break; + case CPUINFO_INT_REGISTER + I386_SS: info->i = cpustate->sreg[SS].selector; break; + case CPUINFO_INT_REGISTER + I386_SS_BASE: info->i = cpustate->sreg[SS].base; break; + case CPUINFO_INT_REGISTER + I386_SS_LIMIT: info->i = cpustate->sreg[SS].limit; break; + case CPUINFO_INT_REGISTER + I386_SS_FLAGS: info->i = cpustate->sreg[SS].flags; break; + case CPUINFO_INT_REGISTER + I386_DS: info->i = cpustate->sreg[DS].selector; break; + case CPUINFO_INT_REGISTER + I386_DS_BASE: info->i = cpustate->sreg[DS].base; break; + case CPUINFO_INT_REGISTER + I386_DS_LIMIT: info->i = cpustate->sreg[DS].limit; break; + case CPUINFO_INT_REGISTER + I386_DS_FLAGS: info->i = cpustate->sreg[DS].flags; break; + case CPUINFO_INT_REGISTER + I386_ES: info->i = cpustate->sreg[ES].selector; break; + case CPUINFO_INT_REGISTER + I386_ES_BASE: info->i = cpustate->sreg[ES].base; break; + case CPUINFO_INT_REGISTER + I386_ES_LIMIT: info->i = cpustate->sreg[ES].limit; break; + case CPUINFO_INT_REGISTER + I386_ES_FLAGS: info->i = cpustate->sreg[ES].flags; break; + case CPUINFO_INT_REGISTER + I386_FS: info->i = cpustate->sreg[FS].selector; break; + case CPUINFO_INT_REGISTER + I386_FS_BASE: info->i = cpustate->sreg[FS].base; break; + case CPUINFO_INT_REGISTER + I386_FS_LIMIT: info->i = cpustate->sreg[FS].limit; break; + case CPUINFO_INT_REGISTER + I386_FS_FLAGS: info->i = cpustate->sreg[FS].flags; break; + case CPUINFO_INT_REGISTER + I386_GS: info->i = cpustate->sreg[GS].selector; break; + case CPUINFO_INT_REGISTER + I386_GS_BASE: info->i = cpustate->sreg[GS].base; break; + case CPUINFO_INT_REGISTER + I386_GS_LIMIT: info->i = cpustate->sreg[GS].limit; break; + case CPUINFO_INT_REGISTER + I386_GS_FLAGS: info->i = cpustate->sreg[GS].flags; break; + case CPUINFO_INT_REGISTER + I386_CR0: info->i = cpustate->cr[0]; break; + case CPUINFO_INT_REGISTER + I386_CR1: info->i = cpustate->cr[1]; break; + case CPUINFO_INT_REGISTER + I386_CR2: info->i = cpustate->cr[2]; break; + case CPUINFO_INT_REGISTER + I386_CR3: info->i = cpustate->cr[3]; break; + case CPUINFO_INT_REGISTER + I386_DR0: info->i = cpustate->dr[0]; break; + case CPUINFO_INT_REGISTER + I386_DR1: info->i = cpustate->dr[1]; break; + case CPUINFO_INT_REGISTER + I386_DR2: info->i = cpustate->dr[2]; break; + case CPUINFO_INT_REGISTER + I386_DR3: info->i = cpustate->dr[3]; break; + case CPUINFO_INT_REGISTER + I386_DR4: info->i = cpustate->dr[4]; break; + case CPUINFO_INT_REGISTER + I386_DR5: info->i = cpustate->dr[5]; break; + case CPUINFO_INT_REGISTER + I386_DR6: info->i = cpustate->dr[6]; break; + case CPUINFO_INT_REGISTER + I386_DR7: info->i = cpustate->dr[7]; break; + case CPUINFO_INT_REGISTER + I386_TR6: info->i = cpustate->tr[6]; break; + case CPUINFO_INT_REGISTER + I386_TR7: info->i = cpustate->tr[7]; break; + case CPUINFO_INT_REGISTER + I386_GDTR_BASE: info->i = cpustate->gdtr.base; break; + case CPUINFO_INT_REGISTER + I386_GDTR_LIMIT: info->i = cpustate->gdtr.limit; break; + case CPUINFO_INT_REGISTER + I386_IDTR_BASE: info->i = cpustate->idtr.base; break; + case CPUINFO_INT_REGISTER + I386_IDTR_LIMIT: info->i = cpustate->idtr.limit; break; + case CPUINFO_INT_REGISTER + I386_TR: info->i = cpustate->task.segment; break; + case CPUINFO_INT_REGISTER + I386_TR_BASE: info->i = cpustate->task.base; break; + case CPUINFO_INT_REGISTER + I386_TR_LIMIT: info->i = cpustate->task.limit; break; + case CPUINFO_INT_REGISTER + I386_TR_FLAGS: info->i = cpustate->task.flags; break; + case CPUINFO_INT_REGISTER + I386_LDTR: info->i = cpustate->ldtr.segment; break; + case CPUINFO_INT_REGISTER + I386_LDTR_BASE: info->i = cpustate->ldtr.base; break; + case CPUINFO_INT_REGISTER + I386_LDTR_LIMIT: info->i = cpustate->ldtr.limit; break; + case CPUINFO_INT_REGISTER + I386_LDTR_FLAGS: info->i = cpustate->ldtr.flags; break; /* --- the following bits of info are returned as pointers to data or functions --- */ case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(i386); break; - case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(i386); break; - case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(i386); break; + case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(dummy); break; + case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(dummy); break; case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i386); break; case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(i386); break; case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(i386); break; case CPUINFO_PTR_BURN: info->burn = NULL; break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &I.cycles; break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->cycles; break; case CPUINFO_PTR_TRANSLATE: info->translate = CPU_TRANSLATE_NAME(i386); break; case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i386); break; case CPUINFO_PTR_DEBUG_INIT: info->debug_init = CPU_DEBUG_INIT_NAME(i386); break; @@ -978,10 +978,10 @@ CPU_GET_INFO( i386 ) case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break; case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Copyright Ville Linde"); break; - case CPUINFO_STR_FLAGS: sprintf(info->s, "%08X", get_flags()); break; + case CPUINFO_STR_FLAGS: sprintf(info->s, "%08X", get_flags(cpustate)); break; - case CPUINFO_STR_REGISTER + I386_PC: sprintf(info->s, "PC: %08X", I.pc); break; - case CPUINFO_STR_REGISTER + I386_EIP: sprintf(info->s, "EIP: %08X", I.eip); break; + case CPUINFO_STR_REGISTER + I386_PC: sprintf(info->s, "PC: %08X", cpustate->pc); break; + case CPUINFO_STR_REGISTER + I386_EIP: sprintf(info->s, "EIP: %08X", cpustate->eip); break; case CPUINFO_STR_REGISTER + I386_AL: sprintf(info->s, "~AL: %02X", REG8(AL)); break; case CPUINFO_STR_REGISTER + I386_AH: sprintf(info->s, "~AH: %02X", REG8(AH)); break; case CPUINFO_STR_REGISTER + I386_BL: sprintf(info->s, "~BL: %02X", REG8(BL)); break; @@ -998,66 +998,66 @@ CPU_GET_INFO( i386 ) case CPUINFO_STR_REGISTER + I386_DI: sprintf(info->s, "~DI: %04X", REG16(DI)); break; case CPUINFO_STR_REGISTER + I386_BP: sprintf(info->s, "~BP: %04X", REG16(BP)); break; case CPUINFO_STR_REGISTER + I386_SP: sprintf(info->s, "~SP: %04X", REG16(SP)); break; - case CPUINFO_STR_REGISTER + I386_IP: sprintf(info->s, "~IP: %04X", I.eip & 0xFFFF); break; - case CPUINFO_STR_REGISTER + I386_EAX: sprintf(info->s, "EAX: %08X", I.reg.d[EAX]); break; - case CPUINFO_STR_REGISTER + I386_EBX: sprintf(info->s, "EBX: %08X", I.reg.d[EBX]); break; - case CPUINFO_STR_REGISTER + I386_ECX: sprintf(info->s, "ECX: %08X", I.reg.d[ECX]); break; - case CPUINFO_STR_REGISTER + I386_EDX: sprintf(info->s, "EDX: %08X", I.reg.d[EDX]); break; - case CPUINFO_STR_REGISTER + I386_EBP: sprintf(info->s, "EBP: %08X", I.reg.d[EBP]); break; - case CPUINFO_STR_REGISTER + I386_ESP: sprintf(info->s, "ESP: %08X", I.reg.d[ESP]); break; - case CPUINFO_STR_REGISTER + I386_ESI: sprintf(info->s, "ESI: %08X", I.reg.d[ESI]); break; - case CPUINFO_STR_REGISTER + I386_EDI: sprintf(info->s, "EDI: %08X", I.reg.d[EDI]); break; - case CPUINFO_STR_REGISTER + I386_EFLAGS: sprintf(info->s, "EFLAGS: %08X", I.eflags); break; - case CPUINFO_STR_REGISTER + I386_CS: sprintf(info->s, "CS: %04X", I.sreg[CS].selector); break; - case CPUINFO_STR_REGISTER + I386_CS_BASE: sprintf(info->s, "CSBASE: %08X", I.sreg[CS].base); break; - case CPUINFO_STR_REGISTER + I386_CS_LIMIT: sprintf(info->s, "CSLIMIT: %08X", I.sreg[CS].limit); break; - case CPUINFO_STR_REGISTER + I386_CS_FLAGS: sprintf(info->s, "CSFLAGS: %04X", I.sreg[CS].flags); break; - case CPUINFO_STR_REGISTER + I386_SS: sprintf(info->s, "SS: %04X", I.sreg[SS].selector); break; - case CPUINFO_STR_REGISTER + I386_SS_BASE: sprintf(info->s, "SSBASE: %08X", I.sreg[SS].base); break; - case CPUINFO_STR_REGISTER + I386_SS_LIMIT: sprintf(info->s, "SSLIMIT: %08X", I.sreg[SS].limit); break; - case CPUINFO_STR_REGISTER + I386_SS_FLAGS: sprintf(info->s, "SSFLAGS: %04X", I.sreg[SS].flags); break; - case CPUINFO_STR_REGISTER + I386_DS: sprintf(info->s, "DS: %04X", I.sreg[DS].selector); break; - case CPUINFO_STR_REGISTER + I386_DS_BASE: sprintf(info->s, "DSBASE: %08X", I.sreg[DS].base); break; - case CPUINFO_STR_REGISTER + I386_DS_LIMIT: sprintf(info->s, "DSLIMIT: %08X", I.sreg[DS].limit); break; - case CPUINFO_STR_REGISTER + I386_DS_FLAGS: sprintf(info->s, "DSFLAGS: %04X", I.sreg[DS].flags); break; - case CPUINFO_STR_REGISTER + I386_ES: sprintf(info->s, "ES: %04X", I.sreg[ES].selector); break; - case CPUINFO_STR_REGISTER + I386_ES_BASE: sprintf(info->s, "ESBASE: %08X", I.sreg[ES].base); break; - case CPUINFO_STR_REGISTER + I386_ES_LIMIT: sprintf(info->s, "ESLIMIT: %08X", I.sreg[ES].limit); break; - case CPUINFO_STR_REGISTER + I386_ES_FLAGS: sprintf(info->s, "ESFLAGS: %04X", I.sreg[ES].flags); break; - case CPUINFO_STR_REGISTER + I386_FS: sprintf(info->s, "FS: %04X", I.sreg[FS].selector); break; - case CPUINFO_STR_REGISTER + I386_FS_BASE: sprintf(info->s, "FSBASE: %08X", I.sreg[FS].base); break; - case CPUINFO_STR_REGISTER + I386_FS_LIMIT: sprintf(info->s, "FSLIMIT: %08X", I.sreg[FS].limit); break; - case CPUINFO_STR_REGISTER + I386_FS_FLAGS: sprintf(info->s, "FSFLAGS: %04X", I.sreg[FS].flags); break; - case CPUINFO_STR_REGISTER + I386_GS: sprintf(info->s, "GS: %04X", I.sreg[GS].selector); break; - case CPUINFO_STR_REGISTER + I386_GS_BASE: sprintf(info->s, "GSBASE: %08X", I.sreg[GS].base); break; - case CPUINFO_STR_REGISTER + I386_GS_LIMIT: sprintf(info->s, "GSLIMIT: %08X", I.sreg[GS].limit); break; - case CPUINFO_STR_REGISTER + I386_GS_FLAGS: sprintf(info->s, "GSFLAGS: %04X", I.sreg[GS].flags); break; - case CPUINFO_STR_REGISTER + I386_CR0: sprintf(info->s, "CR0: %08X", I.cr[0]); break; - case CPUINFO_STR_REGISTER + I386_CR1: sprintf(info->s, "CR1: %08X", I.cr[1]); break; - case CPUINFO_STR_REGISTER + I386_CR2: sprintf(info->s, "CR2: %08X", I.cr[2]); break; - case CPUINFO_STR_REGISTER + I386_CR3: sprintf(info->s, "CR3: %08X", I.cr[3]); break; - case CPUINFO_STR_REGISTER + I386_DR0: sprintf(info->s, "DR0: %08X", I.dr[0]); break; - case CPUINFO_STR_REGISTER + I386_DR1: sprintf(info->s, "DR1: %08X", I.dr[1]); break; - case CPUINFO_STR_REGISTER + I386_DR2: sprintf(info->s, "DR2: %08X", I.dr[2]); break; - case CPUINFO_STR_REGISTER + I386_DR3: sprintf(info->s, "DR3: %08X", I.dr[3]); break; - case CPUINFO_STR_REGISTER + I386_DR4: sprintf(info->s, "DR4: %08X", I.dr[4]); break; - case CPUINFO_STR_REGISTER + I386_DR5: sprintf(info->s, "DR5: %08X", I.dr[5]); break; - case CPUINFO_STR_REGISTER + I386_DR6: sprintf(info->s, "DR6: %08X", I.dr[6]); break; - case CPUINFO_STR_REGISTER + I386_DR7: sprintf(info->s, "DR7: %08X", I.dr[7]); break; - case CPUINFO_STR_REGISTER + I386_TR6: sprintf(info->s, "TR6: %08X", I.tr[6]); break; - case CPUINFO_STR_REGISTER + I386_TR7: sprintf(info->s, "TR7: %08X", I.tr[7]); break; - case CPUINFO_STR_REGISTER + I386_GDTR_BASE: sprintf(info->s, "GDTRBASE: %08X", I.gdtr.base); break; - case CPUINFO_STR_REGISTER + I386_GDTR_LIMIT: sprintf(info->s, "GDTRLIMIT: %04X", I.gdtr.limit); break; - case CPUINFO_STR_REGISTER + I386_IDTR_BASE: sprintf(info->s, "IDTRBASE: %08X", I.idtr.base); break; - case CPUINFO_STR_REGISTER + I386_IDTR_LIMIT: sprintf(info->s, "IDTRLIMIT: %04X", I.idtr.limit); break; - case CPUINFO_STR_REGISTER + I386_LDTR: sprintf(info->s, "LDTR: %04X", I.ldtr.segment); break; - case CPUINFO_STR_REGISTER + I386_LDTR_BASE: sprintf(info->s, "LDTRBASE: %08X", I.ldtr.base); break; - case CPUINFO_STR_REGISTER + I386_LDTR_LIMIT: sprintf(info->s, "LDTRLIMIT: %08X", I.ldtr.limit); break; - case CPUINFO_STR_REGISTER + I386_LDTR_FLAGS: sprintf(info->s, "LDTRFLAGS: %04X", I.ldtr.flags); break; - case CPUINFO_STR_REGISTER + I386_TR: sprintf(info->s, "TR: %04X", I.task.segment); break; - case CPUINFO_STR_REGISTER + I386_TR_BASE: sprintf(info->s, "TRBASE: %08X", I.task.base); break; - case CPUINFO_STR_REGISTER + I386_TR_LIMIT: sprintf(info->s, "TRLIMIT: %08X", I.task.limit); break; - case CPUINFO_STR_REGISTER + I386_TR_FLAGS: sprintf(info->s, "TRFLAGS: %04X", I.task.flags); break; + case CPUINFO_STR_REGISTER + I386_IP: sprintf(info->s, "~IP: %04X", cpustate->eip & 0xFFFF); break; + case CPUINFO_STR_REGISTER + I386_EAX: sprintf(info->s, "EAX: %08X", cpustate->reg.d[EAX]); break; + case CPUINFO_STR_REGISTER + I386_EBX: sprintf(info->s, "EBX: %08X", cpustate->reg.d[EBX]); break; + case CPUINFO_STR_REGISTER + I386_ECX: sprintf(info->s, "ECX: %08X", cpustate->reg.d[ECX]); break; + case CPUINFO_STR_REGISTER + I386_EDX: sprintf(info->s, "EDX: %08X", cpustate->reg.d[EDX]); break; + case CPUINFO_STR_REGISTER + I386_EBP: sprintf(info->s, "EBP: %08X", cpustate->reg.d[EBP]); break; + case CPUINFO_STR_REGISTER + I386_ESP: sprintf(info->s, "ESP: %08X", cpustate->reg.d[ESP]); break; + case CPUINFO_STR_REGISTER + I386_ESI: sprintf(info->s, "ESI: %08X", cpustate->reg.d[ESI]); break; + case CPUINFO_STR_REGISTER + I386_EDI: sprintf(info->s, "EDI: %08X", cpustate->reg.d[EDI]); break; + case CPUINFO_STR_REGISTER + I386_EFLAGS: sprintf(info->s, "EFLAGS: %08X", cpustate->eflags); break; + case CPUINFO_STR_REGISTER + I386_CS: sprintf(info->s, "CS: %04X", cpustate->sreg[CS].selector); break; + case CPUINFO_STR_REGISTER + I386_CS_BASE: sprintf(info->s, "CSBASE: %08X", cpustate->sreg[CS].base); break; + case CPUINFO_STR_REGISTER + I386_CS_LIMIT: sprintf(info->s, "CSLIMIT: %08X", cpustate->sreg[CS].limit); break; + case CPUINFO_STR_REGISTER + I386_CS_FLAGS: sprintf(info->s, "CSFLAGS: %04X", cpustate->sreg[CS].flags); break; + case CPUINFO_STR_REGISTER + I386_SS: sprintf(info->s, "SS: %04X", cpustate->sreg[SS].selector); break; + case CPUINFO_STR_REGISTER + I386_SS_BASE: sprintf(info->s, "SSBASE: %08X", cpustate->sreg[SS].base); break; + case CPUINFO_STR_REGISTER + I386_SS_LIMIT: sprintf(info->s, "SSLIMIT: %08X", cpustate->sreg[SS].limit); break; + case CPUINFO_STR_REGISTER + I386_SS_FLAGS: sprintf(info->s, "SSFLAGS: %04X", cpustate->sreg[SS].flags); break; + case CPUINFO_STR_REGISTER + I386_DS: sprintf(info->s, "DS: %04X", cpustate->sreg[DS].selector); break; + case CPUINFO_STR_REGISTER + I386_DS_BASE: sprintf(info->s, "DSBASE: %08X", cpustate->sreg[DS].base); break; + case CPUINFO_STR_REGISTER + I386_DS_LIMIT: sprintf(info->s, "DSLIMIT: %08X", cpustate->sreg[DS].limit); break; + case CPUINFO_STR_REGISTER + I386_DS_FLAGS: sprintf(info->s, "DSFLAGS: %04X", cpustate->sreg[DS].flags); break; + case CPUINFO_STR_REGISTER + I386_ES: sprintf(info->s, "ES: %04X", cpustate->sreg[ES].selector); break; + case CPUINFO_STR_REGISTER + I386_ES_BASE: sprintf(info->s, "ESBASE: %08X", cpustate->sreg[ES].base); break; + case CPUINFO_STR_REGISTER + I386_ES_LIMIT: sprintf(info->s, "ESLIMIT: %08X", cpustate->sreg[ES].limit); break; + case CPUINFO_STR_REGISTER + I386_ES_FLAGS: sprintf(info->s, "ESFLAGS: %04X", cpustate->sreg[ES].flags); break; + case CPUINFO_STR_REGISTER + I386_FS: sprintf(info->s, "FS: %04X", cpustate->sreg[FS].selector); break; + case CPUINFO_STR_REGISTER + I386_FS_BASE: sprintf(info->s, "FSBASE: %08X", cpustate->sreg[FS].base); break; + case CPUINFO_STR_REGISTER + I386_FS_LIMIT: sprintf(info->s, "FSLIMIT: %08X", cpustate->sreg[FS].limit); break; + case CPUINFO_STR_REGISTER + I386_FS_FLAGS: sprintf(info->s, "FSFLAGS: %04X", cpustate->sreg[FS].flags); break; + case CPUINFO_STR_REGISTER + I386_GS: sprintf(info->s, "GS: %04X", cpustate->sreg[GS].selector); break; + case CPUINFO_STR_REGISTER + I386_GS_BASE: sprintf(info->s, "GSBASE: %08X", cpustate->sreg[GS].base); break; + case CPUINFO_STR_REGISTER + I386_GS_LIMIT: sprintf(info->s, "GSLIMIT: %08X", cpustate->sreg[GS].limit); break; + case CPUINFO_STR_REGISTER + I386_GS_FLAGS: sprintf(info->s, "GSFLAGS: %04X", cpustate->sreg[GS].flags); break; + case CPUINFO_STR_REGISTER + I386_CR0: sprintf(info->s, "CR0: %08X", cpustate->cr[0]); break; + case CPUINFO_STR_REGISTER + I386_CR1: sprintf(info->s, "CR1: %08X", cpustate->cr[1]); break; + case CPUINFO_STR_REGISTER + I386_CR2: sprintf(info->s, "CR2: %08X", cpustate->cr[2]); break; + case CPUINFO_STR_REGISTER + I386_CR3: sprintf(info->s, "CR3: %08X", cpustate->cr[3]); break; + case CPUINFO_STR_REGISTER + I386_DR0: sprintf(info->s, "DR0: %08X", cpustate->dr[0]); break; + case CPUINFO_STR_REGISTER + I386_DR1: sprintf(info->s, "DR1: %08X", cpustate->dr[1]); break; + case CPUINFO_STR_REGISTER + I386_DR2: sprintf(info->s, "DR2: %08X", cpustate->dr[2]); break; + case CPUINFO_STR_REGISTER + I386_DR3: sprintf(info->s, "DR3: %08X", cpustate->dr[3]); break; + case CPUINFO_STR_REGISTER + I386_DR4: sprintf(info->s, "DR4: %08X", cpustate->dr[4]); break; + case CPUINFO_STR_REGISTER + I386_DR5: sprintf(info->s, "DR5: %08X", cpustate->dr[5]); break; + case CPUINFO_STR_REGISTER + I386_DR6: sprintf(info->s, "DR6: %08X", cpustate->dr[6]); break; + case CPUINFO_STR_REGISTER + I386_DR7: sprintf(info->s, "DR7: %08X", cpustate->dr[7]); break; + case CPUINFO_STR_REGISTER + I386_TR6: sprintf(info->s, "TR6: %08X", cpustate->tr[6]); break; + case CPUINFO_STR_REGISTER + I386_TR7: sprintf(info->s, "TR7: %08X", cpustate->tr[7]); break; + case CPUINFO_STR_REGISTER + I386_GDTR_BASE: sprintf(info->s, "GDTRBASE: %08X", cpustate->gdtr.base); break; + case CPUINFO_STR_REGISTER + I386_GDTR_LIMIT: sprintf(info->s, "GDTRLIMIT: %04X", cpustate->gdtr.limit); break; + case CPUINFO_STR_REGISTER + I386_IDTR_BASE: sprintf(info->s, "IDTRBASE: %08X", cpustate->idtr.base); break; + case CPUINFO_STR_REGISTER + I386_IDTR_LIMIT: sprintf(info->s, "IDTRLIMIT: %04X", cpustate->idtr.limit); break; + case CPUINFO_STR_REGISTER + I386_LDTR: sprintf(info->s, "LDTR: %04X", cpustate->ldtr.segment); break; + case CPUINFO_STR_REGISTER + I386_LDTR_BASE: sprintf(info->s, "LDTRBASE: %08X", cpustate->ldtr.base); break; + case CPUINFO_STR_REGISTER + I386_LDTR_LIMIT: sprintf(info->s, "LDTRLIMIT: %08X", cpustate->ldtr.limit); break; + case CPUINFO_STR_REGISTER + I386_LDTR_FLAGS: sprintf(info->s, "LDTRFLAGS: %04X", cpustate->ldtr.flags); break; + case CPUINFO_STR_REGISTER + I386_TR: sprintf(info->s, "TR: %04X", cpustate->task.segment); break; + case CPUINFO_STR_REGISTER + I386_TR_BASE: sprintf(info->s, "TRBASE: %08X", cpustate->task.base); break; + case CPUINFO_STR_REGISTER + I386_TR_LIMIT: sprintf(info->s, "TRLIMIT: %08X", cpustate->task.limit); break; + case CPUINFO_STR_REGISTER + I386_TR_FLAGS: sprintf(info->s, "TRFLAGS: %04X", cpustate->task.flags); break; } } @@ -1073,39 +1073,40 @@ static CPU_INIT( i486 ) static CPU_RESET( i486 ) { + i386_state *cpustate = device->token; cpu_irq_callback save_irqcallback; - save_irqcallback = I.irq_callback; - memset( &I, 0, sizeof(I386_REGS) ); - I.irq_callback = save_irqcallback; - I.device = device; + save_irqcallback = cpustate->irq_callback; + memset( cpustate, 0, sizeof(*cpustate) ); + cpustate->irq_callback = save_irqcallback; + cpustate->device = device; - I.sreg[CS].selector = 0xf000; - I.sreg[CS].base = 0xffff0000; - I.sreg[CS].limit = 0xffff; - I.sreg[CS].flags = 0x009b; + cpustate->sreg[CS].selector = 0xf000; + cpustate->sreg[CS].base = 0xffff0000; + cpustate->sreg[CS].limit = 0xffff; + cpustate->sreg[CS].flags = 0x009b; - I.sreg[DS].base = I.sreg[ES].base = I.sreg[FS].base = I.sreg[GS].base = I.sreg[SS].base = 0x00000000; - I.sreg[DS].limit = I.sreg[ES].limit = I.sreg[FS].limit = I.sreg[GS].limit = I.sreg[SS].limit = 0xffff; - I.sreg[DS].flags = I.sreg[ES].flags = I.sreg[FS].flags = I.sreg[GS].flags = I.sreg[SS].flags = 0x0092; + cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000; + cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff; + cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092; - I.idtr.base = 0; - I.idtr.limit = 0x3ff; + cpustate->idtr.base = 0; + cpustate->idtr.limit = 0x3ff; - I.a20_mask = ~0; + cpustate->a20_mask = ~0; - I.cr[0] = 0; - I.eflags = 0; - I.eip = 0xfff0; + cpustate->cr[0] = 0; + cpustate->eflags = 0; + cpustate->eip = 0xfff0; REG32(EAX) = 0x0308; // Intel 386, stepping D1 REG32(EDX) = 0; - build_opcode_table(OP_I386 | OP_FPU | OP_I486); - I.cycle_table_rm = cycle_table_rm[CPU_CYCLES_I486]; - I.cycle_table_pm = cycle_table_pm[CPU_CYCLES_I486]; + build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486); + cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_I486]; + cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_I486]; - CHANGE_PC(I.eip); + CHANGE_PC(cpustate,cpustate->eip); } static CPU_EXIT( i486 ) @@ -1114,10 +1115,11 @@ static CPU_EXIT( i486 ) static CPU_SET_INFO( i486 ) { + i386_state *cpustate = device->token; switch (state) { - case CPUINFO_INT_REGISTER + X87_CTRL: I.fpu_control_word = info->i; break; - case CPUINFO_INT_REGISTER + X87_STATUS: I.fpu_status_word = info->i; break; + case CPUINFO_INT_REGISTER + X87_CTRL: cpustate->fpu_control_word = info->i; break; + case CPUINFO_INT_REGISTER + X87_STATUS: cpustate->fpu_status_word = info->i; break; case CPUINFO_INT_REGISTER + X87_ST0: ST(0).f = info->i; break; case CPUINFO_INT_REGISTER + X87_ST1: ST(1).f = info->i; break; case CPUINFO_INT_REGISTER + X87_ST2: ST(2).f = info->i; break; @@ -1133,6 +1135,7 @@ static CPU_SET_INFO( i486 ) CPU_GET_INFO( i486 ) { + i386_state *cpustate = (device != NULL) ? device->token : NULL; switch (state) { case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(i486);break; @@ -1140,8 +1143,8 @@ CPU_GET_INFO( i486 ) case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(i486); break; case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(i486); break; - case CPUINFO_INT_REGISTER + X87_CTRL: info->i = I.fpu_control_word; break; - case CPUINFO_INT_REGISTER + X87_STATUS: info->i = I.fpu_status_word; break; + case CPUINFO_INT_REGISTER + X87_CTRL: info->i = cpustate->fpu_control_word; break; + case CPUINFO_INT_REGISTER + X87_STATUS: info->i = cpustate->fpu_status_word; break; case CPUINFO_INT_REGISTER + X87_ST0: info->i = ST(0).f; break; case CPUINFO_INT_REGISTER + X87_ST1: info->i = ST(1).f; break; case CPUINFO_INT_REGISTER + X87_ST2: info->i = ST(2).f; break; @@ -1153,8 +1156,8 @@ CPU_GET_INFO( i486 ) case CPUINFO_STR_NAME: strcpy(info->s, "I486"); break; case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "Intel 486"); break; - case CPUINFO_STR_REGISTER + X87_CTRL: sprintf(info->s, "FPU_CW: %04X", I.fpu_control_word); break; - case CPUINFO_STR_REGISTER + X87_STATUS: sprintf(info->s, "FPU_SW: %04X", I.fpu_status_word); break; + case CPUINFO_STR_REGISTER + X87_CTRL: sprintf(info->s, "FPU_CW: %04X", cpustate->fpu_control_word); break; + case CPUINFO_STR_REGISTER + X87_STATUS: sprintf(info->s, "FPU_SW: %04X", cpustate->fpu_status_word); break; case CPUINFO_STR_REGISTER + X87_ST0: sprintf(info->s, "ST0: %f", ST(0).f); break; case CPUINFO_STR_REGISTER + X87_ST1: sprintf(info->s, "ST1: %f", ST(1).f); break; case CPUINFO_STR_REGISTER + X87_ST2: sprintf(info->s, "ST2: %f", ST(2).f); break; @@ -1181,49 +1184,50 @@ static CPU_INIT( pentium ) static CPU_RESET( pentium ) { + i386_state *cpustate = device->token; cpu_irq_callback save_irqcallback; - save_irqcallback = I.irq_callback; - memset( &I, 0, sizeof(I386_REGS) ); - I.irq_callback = save_irqcallback; - I.device = device; + save_irqcallback = cpustate->irq_callback; + memset( cpustate, 0, sizeof(*cpustate) ); + cpustate->irq_callback = save_irqcallback; + cpustate->device = device; - I.sreg[CS].selector = 0xf000; - I.sreg[CS].base = 0xffff0000; - I.sreg[CS].limit = 0xffff; - I.sreg[CS].flags = 0x009b; + cpustate->sreg[CS].selector = 0xf000; + cpustate->sreg[CS].base = 0xffff0000; + cpustate->sreg[CS].limit = 0xffff; + cpustate->sreg[CS].flags = 0x009b; - I.sreg[DS].base = I.sreg[ES].base = I.sreg[FS].base = I.sreg[GS].base = I.sreg[SS].base = 0x00000000; - I.sreg[DS].limit = I.sreg[ES].limit = I.sreg[FS].limit = I.sreg[GS].limit = I.sreg[SS].limit = 0xffff; - I.sreg[DS].flags = I.sreg[ES].flags = I.sreg[FS].flags = I.sreg[GS].flags = I.sreg[SS].flags = 0x0092; + cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000; + cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff; + cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092; - I.idtr.base = 0; - I.idtr.limit = 0x3ff; + cpustate->idtr.base = 0; + cpustate->idtr.limit = 0x3ff; - I.a20_mask = ~0; + cpustate->a20_mask = ~0; - I.cr[0] = 0; - I.eflags = 0; - I.eip = 0xfff0; + cpustate->cr[0] = 0; + cpustate->eflags = 0; + cpustate->eip = 0xfff0; REG32(EAX) = 0x0308; // Intel 386, stepping D1 REG32(EDX) = 0; - build_opcode_table(OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM); - I.cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; - I.cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; + build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM); + cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; + cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; - I.cpuid_id0 = 0x756e6547; // Genu - I.cpuid_id1 = 0x49656e69; // ineI - I.cpuid_id2 = 0x6c65746e; // ntel + cpustate->cpuid_id0 = 0x756e6547; // Genu + cpustate->cpuid_id1 = 0x49656e69; // ineI + cpustate->cpuid_id2 = 0x6c65746e; // ntel - I.cpuid_max_input_value_eax = 0x01; + cpustate->cpuid_max_input_value_eax = 0x01; // [11:8] Family // [ 7:4] Model // [ 3:0] Stepping ID // Family 5 (Pentium), Model 2 (75 - 200MHz), Stepping 1 - I.cpu_version = (5 << 8) | (2 << 4) | (1); + cpustate->cpu_version = (5 << 8) | (2 << 4) | (1); // [ 0:0] FPU on chip // [ 2:2] I/O breakpoints @@ -1231,9 +1235,9 @@ static CPU_RESET( pentium ) // [ 5:5] Pentium CPU style model specific registers // [ 7:7] Machine Check Exception // [ 8:8] CMPXCHG8B instruction - I.feature_flags = 0x00000000; + cpustate->feature_flags = 0x00000000; - CHANGE_PC(I.eip); + CHANGE_PC(cpustate,cpustate->eip); } static CPU_EXIT( pentium ) @@ -1242,10 +1246,11 @@ static CPU_EXIT( pentium ) static CPU_SET_INFO( pentium ) { + i386_state *cpustate = device->token; switch (state) { - case CPUINFO_INT_REGISTER + X87_CTRL: I.fpu_control_word = info->i; break; - case CPUINFO_INT_REGISTER + X87_STATUS: I.fpu_status_word = info->i; break; + case CPUINFO_INT_REGISTER + X87_CTRL: cpustate->fpu_control_word = info->i; break; + case CPUINFO_INT_REGISTER + X87_STATUS: cpustate->fpu_status_word = info->i; break; case CPUINFO_INT_REGISTER + X87_ST0: ST(0).f = info->i; break; case CPUINFO_INT_REGISTER + X87_ST1: ST(1).f = info->i; break; case CPUINFO_INT_REGISTER + X87_ST2: ST(2).f = info->i; break; @@ -1261,6 +1266,7 @@ static CPU_SET_INFO( pentium ) CPU_GET_INFO( pentium ) { + i386_state *cpustate = (device != NULL) ? device->token : NULL; switch (state) { case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(pentium); break; @@ -1268,8 +1274,8 @@ CPU_GET_INFO( pentium ) case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(pentium); break; case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(pentium); break; - case CPUINFO_INT_REGISTER + X87_CTRL: info->i = I.fpu_control_word; break; - case CPUINFO_INT_REGISTER + X87_STATUS: info->i = I.fpu_status_word; break; + case CPUINFO_INT_REGISTER + X87_CTRL: info->i = cpustate->fpu_control_word; break; + case CPUINFO_INT_REGISTER + X87_STATUS: info->i = cpustate->fpu_status_word; break; case CPUINFO_INT_REGISTER + X87_ST0: info->i = ST(0).f; break; case CPUINFO_INT_REGISTER + X87_ST1: info->i = ST(1).f; break; case CPUINFO_INT_REGISTER + X87_ST2: info->i = ST(2).f; break; @@ -1281,8 +1287,8 @@ CPU_GET_INFO( pentium ) case CPUINFO_STR_NAME: strcpy(info->s, "PENTIUM"); break; case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "Intel Pentium"); break; - case CPUINFO_STR_REGISTER + X87_CTRL: sprintf(info->s, "FPU_CW: %04X", I.fpu_control_word); break; - case CPUINFO_STR_REGISTER + X87_STATUS: sprintf(info->s, "FPU_SW: %04X", I.fpu_status_word); break; + case CPUINFO_STR_REGISTER + X87_CTRL: sprintf(info->s, "FPU_CW: %04X", cpustate->fpu_control_word); break; + case CPUINFO_STR_REGISTER + X87_STATUS: sprintf(info->s, "FPU_SW: %04X", cpustate->fpu_status_word); break; case CPUINFO_STR_REGISTER + X87_ST0: sprintf(info->s, "ST0: %f", ST(0).f); break; case CPUINFO_STR_REGISTER + X87_ST1: sprintf(info->s, "ST1: %f", ST(1).f); break; case CPUINFO_STR_REGISTER + X87_ST2: sprintf(info->s, "ST2: %f", ST(2).f); break; @@ -1309,49 +1315,50 @@ static CPU_INIT( mediagx ) static CPU_RESET( mediagx ) { + i386_state *cpustate = device->token; cpu_irq_callback save_irqcallback; - save_irqcallback = I.irq_callback; - memset( &I, 0, sizeof(I386_REGS) ); - I.irq_callback = save_irqcallback; - I.device = device; + save_irqcallback = cpustate->irq_callback; + memset( cpustate, 0, sizeof(*cpustate) ); + cpustate->irq_callback = save_irqcallback; + cpustate->device = device; - I.sreg[CS].selector = 0xf000; - I.sreg[CS].base = 0xffff0000; - I.sreg[CS].limit = 0xffff; - I.sreg[CS].flags = 0x009b; + cpustate->sreg[CS].selector = 0xf000; + cpustate->sreg[CS].base = 0xffff0000; + cpustate->sreg[CS].limit = 0xffff; + cpustate->sreg[CS].flags = 0x009b; - I.sreg[DS].base = I.sreg[ES].base = I.sreg[FS].base = I.sreg[GS].base = I.sreg[SS].base = 0x00000000; - I.sreg[DS].limit = I.sreg[ES].limit = I.sreg[FS].limit = I.sreg[GS].limit = I.sreg[SS].limit = 0xffff; - I.sreg[DS].flags = I.sreg[ES].flags = I.sreg[FS].flags = I.sreg[GS].flags = I.sreg[SS].flags = 0x0092; + cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000; + cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff; + cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092; - I.idtr.base = 0; - I.idtr.limit = 0x3ff; + cpustate->idtr.base = 0; + cpustate->idtr.limit = 0x3ff; - I.a20_mask = ~0; + cpustate->a20_mask = ~0; - I.cr[0] = 0; - I.eflags = 0; - I.eip = 0xfff0; + cpustate->cr[0] = 0; + cpustate->eflags = 0; + cpustate->eip = 0xfff0; REG32(EAX) = 0x0308; // Intel 386, stepping D1 REG32(EDX) = 0; - build_opcode_table(OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_CYRIX); - I.cycle_table_rm = cycle_table_rm[CPU_CYCLES_MEDIAGX]; - I.cycle_table_pm = cycle_table_pm[CPU_CYCLES_MEDIAGX]; + build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_CYRIX); + cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_MEDIAGX]; + cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_MEDIAGX]; - I.cpuid_id0 = 0x69727943; // Cyri - I.cpuid_id1 = 0x736e4978; // xIns - I.cpuid_id2 = 0x6d616574; // tead + cpustate->cpuid_id0 = 0x69727943; // Cyri + cpustate->cpuid_id1 = 0x736e4978; // xIns + cpustate->cpuid_id2 = 0x6d616574; // tead - I.cpuid_max_input_value_eax = 0x01; + cpustate->cpuid_max_input_value_eax = 0x01; // [11:8] Family // [ 7:4] Model // [ 3:0] Stepping ID // Family 4, Model 4 (MediaGX) - I.cpu_version = (4 << 8) | (4 << 4) | (1); + cpustate->cpu_version = (4 << 8) | (4 << 4) | (1); // [ 0:0] FPU on chip // [ 2:2] I/O breakpoints @@ -1359,9 +1366,9 @@ static CPU_RESET( mediagx ) // [ 5:5] Pentium CPU style model specific registers // [ 7:7] Machine Check Exception // [ 8:8] CMPXCHG8B instruction - I.feature_flags = 0x00000001; + cpustate->feature_flags = 0x00000001; - CHANGE_PC(I.eip); + CHANGE_PC(cpustate,cpustate->eip); } static CPU_EXIT( mediagx ) @@ -1370,10 +1377,11 @@ static CPU_EXIT( mediagx ) static CPU_SET_INFO( mediagx ) { + i386_state *cpustate = device->token; switch (state) { - case CPUINFO_INT_REGISTER + X87_CTRL: I.fpu_control_word = info->i; break; - case CPUINFO_INT_REGISTER + X87_STATUS: I.fpu_status_word = info->i; break; + case CPUINFO_INT_REGISTER + X87_CTRL: cpustate->fpu_control_word = info->i; break; + case CPUINFO_INT_REGISTER + X87_STATUS: cpustate->fpu_status_word = info->i; break; case CPUINFO_INT_REGISTER + X87_ST0: ST(0).f = info->i; break; case CPUINFO_INT_REGISTER + X87_ST1: ST(1).f = info->i; break; case CPUINFO_INT_REGISTER + X87_ST2: ST(2).f = info->i; break; @@ -1389,6 +1397,7 @@ static CPU_SET_INFO( mediagx ) CPU_GET_INFO( mediagx ) { + i386_state *cpustate = (device != NULL) ? device->token : NULL; switch (state) { case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(mediagx); break; @@ -1396,8 +1405,8 @@ CPU_GET_INFO( mediagx ) case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(mediagx); break; case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(mediagx); break; - case CPUINFO_INT_REGISTER + X87_CTRL: info->i = I.fpu_control_word; break; - case CPUINFO_INT_REGISTER + X87_STATUS: info->i = I.fpu_status_word; break; + case CPUINFO_INT_REGISTER + X87_CTRL: info->i = cpustate->fpu_control_word; break; + case CPUINFO_INT_REGISTER + X87_STATUS: info->i = cpustate->fpu_status_word; break; case CPUINFO_INT_REGISTER + X87_ST0: info->i = ST(0).f; break; case CPUINFO_INT_REGISTER + X87_ST1: info->i = ST(1).f; break; case CPUINFO_INT_REGISTER + X87_ST2: info->i = ST(2).f; break; @@ -1409,8 +1418,8 @@ CPU_GET_INFO( mediagx ) case CPUINFO_STR_NAME: strcpy(info->s, "MEDIAGX"); break; case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "Cyrix MediaGX"); break; - case CPUINFO_STR_REGISTER + X87_CTRL: sprintf(info->s, "FPU_CW: %04X", I.fpu_control_word); break; - case CPUINFO_STR_REGISTER + X87_STATUS: sprintf(info->s, "FPU_SW: %04X", I.fpu_status_word); break; + case CPUINFO_STR_REGISTER + X87_CTRL: sprintf(info->s, "FPU_CW: %04X", cpustate->fpu_control_word); break; + case CPUINFO_STR_REGISTER + X87_STATUS: sprintf(info->s, "FPU_SW: %04X", cpustate->fpu_status_word); break; case CPUINFO_STR_REGISTER + X87_ST0: sprintf(info->s, "ST0: %f", ST(0).f); break; case CPUINFO_STR_REGISTER + X87_ST1: sprintf(info->s, "ST1: %f", ST(1).f); break; case CPUINFO_STR_REGISTER + X87_ST2: sprintf(info->s, "ST2: %f", ST(2).f); break; diff --git a/src/emu/cpu/i386/i386.h b/src/emu/cpu/i386/i386.h index c8fecfbc835..4f4300c3d6d 100644 --- a/src/emu/cpu/i386/i386.h +++ b/src/emu/cpu/i386/i386.h @@ -208,7 +208,9 @@ typedef union { double f; } X87_REG; -typedef struct { +typedef struct _i386_state i386_state; +struct _i386_state +{ I386_GPR reg; I386_SREG sreg[6]; UINT32 eip; @@ -271,45 +273,42 @@ typedef struct { UINT16 fpu_opcode; int fpu_top; - void (*opcode_table1_16[256])(void); - void (*opcode_table1_32[256])(void); - void (*opcode_table2_16[256])(void); - void (*opcode_table2_32[256])(void); + void (*opcode_table1_16[256])(i386_state *cpustate); + void (*opcode_table1_32[256])(i386_state *cpustate); + void (*opcode_table2_16[256])(i386_state *cpustate); + void (*opcode_table2_32[256])(i386_state *cpustate); UINT8 *cycle_table_pm; UINT8 *cycle_table_rm; -} I386_REGS; - - -static I386_REGS I; +}; extern int i386_parity_table[256]; -#define PROTECTED_MODE (I.cr[0] & 0x1) -#define STACK_32BIT (I.sreg[SS].d) -#define V8086_MODE (I.eflags & 0x00020000) +#define PROTECTED_MODE (cpustate->cr[0] & 0x1) +#define STACK_32BIT (cpustate->sreg[SS].d) +#define V8086_MODE (cpustate->eflags & 0x00020000) -#define SetOF_Add32(r,s,d) (I.OF = (((r) ^ (s)) & ((r) ^ (d)) & 0x80000000) ? 1: 0) -#define SetOF_Add16(r,s,d) (I.OF = (((r) ^ (s)) & ((r) ^ (d)) & 0x8000) ? 1 : 0) -#define SetOF_Add8(r,s,d) (I.OF = (((r) ^ (s)) & ((r) ^ (d)) & 0x80) ? 1 : 0) +#define SetOF_Add32(r,s,d) (cpustate->OF = (((r) ^ (s)) & ((r) ^ (d)) & 0x80000000) ? 1: 0) +#define SetOF_Add16(r,s,d) (cpustate->OF = (((r) ^ (s)) & ((r) ^ (d)) & 0x8000) ? 1 : 0) +#define SetOF_Add8(r,s,d) (cpustate->OF = (((r) ^ (s)) & ((r) ^ (d)) & 0x80) ? 1 : 0) -#define SetOF_Sub32(r,s,d) (I.OF = (((d) ^ (s)) & ((d) ^ (r)) & 0x80000000) ? 1 : 0) -#define SetOF_Sub16(r,s,d) (I.OF = (((d) ^ (s)) & ((d) ^ (r)) & 0x8000) ? 1 : 0) -#define SetOF_Sub8(r,s,d) (I.OF = (((d) ^ (s)) & ((d) ^ (r)) & 0x80) ? 1 : 0) +#define SetOF_Sub32(r,s,d) (cpustate->OF = (((d) ^ (s)) & ((d) ^ (r)) & 0x80000000) ? 1 : 0) +#define SetOF_Sub16(r,s,d) (cpustate->OF = (((d) ^ (s)) & ((d) ^ (r)) & 0x8000) ? 1 : 0) +#define SetOF_Sub8(r,s,d) (cpustate->OF = (((d) ^ (s)) & ((d) ^ (r)) & 0x80) ? 1 : 0) -#define SetCF8(x) {I.CF = ((x) & 0x100) ? 1 : 0; } -#define SetCF16(x) {I.CF = ((x) & 0x10000) ? 1 : 0; } -#define SetCF32(x) {I.CF = ((x) & (((UINT64)1) << 32)) ? 1 : 0; } +#define SetCF8(x) {cpustate->CF = ((x) & 0x100) ? 1 : 0; } +#define SetCF16(x) {cpustate->CF = ((x) & 0x10000) ? 1 : 0; } +#define SetCF32(x) {cpustate->CF = ((x) & (((UINT64)1) << 32)) ? 1 : 0; } -#define SetSF(x) (I.SF = (x)) -#define SetZF(x) (I.ZF = (x)) -#define SetAF(x,y,z) (I.AF = (((x) ^ ((y) ^ (z))) & 0x10) ? 1 : 0) -#define SetPF(x) (I.PF = i386_parity_table[(x) & 0xFF]) +#define SetSF(x) (cpustate->SF = (x)) +#define SetZF(x) (cpustate->ZF = (x)) +#define SetAF(x,y,z) (cpustate->AF = (((x) ^ ((y) ^ (z))) & 0x10) ? 1 : 0) +#define SetPF(x) (cpustate->PF = i386_parity_table[(x) & 0xFF]) -#define SetSZPF8(x) {I.ZF = ((UINT8)(x)==0); I.SF = ((x)&0x80) ? 1 : 0; I.PF = i386_parity_table[x & 0xFF]; } -#define SetSZPF16(x) {I.ZF = ((UINT16)(x)==0); I.SF = ((x)&0x8000) ? 1 : 0; I.PF = i386_parity_table[x & 0xFF]; } -#define SetSZPF32(x) {I.ZF = ((UINT32)(x)==0); I.SF = ((x)&0x80000000) ? 1 : 0; I.PF = i386_parity_table[x & 0xFF]; } +#define SetSZPF8(x) {cpustate->ZF = ((UINT8)(x)==0); cpustate->SF = ((x)&0x80) ? 1 : 0; cpustate->PF = i386_parity_table[x & 0xFF]; } +#define SetSZPF16(x) {cpustate->ZF = ((UINT16)(x)==0); cpustate->SF = ((x)&0x8000) ? 1 : 0; cpustate->PF = i386_parity_table[x & 0xFF]; } +#define SetSZPF32(x) {cpustate->ZF = ((UINT32)(x)==0); cpustate->SF = ((x)&0x80000000) ? 1 : 0; cpustate->PF = i386_parity_table[x & 0xFF]; } /***********************************************************************************/ @@ -328,9 +327,9 @@ typedef struct { extern MODRM_TABLE i386_MODRM_table[256]; -#define REG8(x) (I.reg.b[x]) -#define REG16(x) (I.reg.w[x]) -#define REG32(x) (I.reg.d[x]) +#define REG8(x) (cpustate->reg.b[x]) +#define REG16(x) (cpustate->reg.w[x]) +#define REG32(x) (cpustate->reg.d[x]) #define LOAD_REG8(x) (REG8(i386_MODRM_table[x].reg.b)) #define LOAD_REG16(x) (REG16(i386_MODRM_table[x].reg.w)) @@ -348,341 +347,341 @@ extern MODRM_TABLE i386_MODRM_table[256]; /***********************************************************************************/ -INLINE UINT32 i386_translate(int segment, UINT32 ip) +INLINE UINT32 i386_translate(i386_state *cpustate, int segment, UINT32 ip) { // TODO: segment limit - return I.sreg[segment].base + ip; + return cpustate->sreg[segment].base + ip; } -INLINE int translate_address(UINT32 *address) +INLINE int translate_address(i386_state *cpustate, UINT32 *address) { UINT32 a = *address; - UINT32 pdbr = I.cr[3] & 0xfffff000; + UINT32 pdbr = cpustate->cr[3] & 0xfffff000; UINT32 directory = (a >> 22) & 0x3ff; UINT32 table = (a >> 12) & 0x3ff; UINT32 offset = a & 0xfff; // TODO: 4MB pages - UINT32 page_dir = memory_read_dword_32le(I.program, pdbr + directory * 4); - UINT32 page_entry = memory_read_dword_32le(I.program, (page_dir & 0xfffff000) + (table * 4)); + UINT32 page_dir = memory_read_dword_32le(cpustate->program, pdbr + directory * 4); + UINT32 page_entry = memory_read_dword_32le(cpustate->program, (page_dir & 0xfffff000) + (table * 4)); *address = (page_entry & 0xfffff000) | offset; return 1; } -INLINE void CHANGE_PC(UINT32 pc) +INLINE void CHANGE_PC(i386_state *cpustate, UINT32 pc) { UINT32 address; - I.pc = i386_translate( CS, pc ); + cpustate->pc = i386_translate(cpustate, CS, pc ); - address = I.pc; + address = cpustate->pc; - if (I.cr[0] & 0x80000000) // page translation enabled + if (cpustate->cr[0] & 0x80000000) // page translation enabled { - translate_address(&address); + translate_address(cpustate,&address); } } -INLINE void NEAR_BRANCH(INT32 offs) +INLINE void NEAR_BRANCH(i386_state *cpustate, INT32 offs) { UINT32 address; /* TODO: limit */ - I.eip += offs; - I.pc += offs; + cpustate->eip += offs; + cpustate->pc += offs; - address = I.pc; + address = cpustate->pc; - if (I.cr[0] & 0x80000000) // page translation enabled + if (cpustate->cr[0] & 0x80000000) // page translation enabled { - translate_address(&address); + translate_address(cpustate,&address); } } -INLINE UINT8 FETCH(void) +INLINE UINT8 FETCH(i386_state *cpustate) { UINT8 value; - UINT32 address = I.pc; + UINT32 address = cpustate->pc; - if (I.cr[0] & 0x80000000) // page translation enabled + if (cpustate->cr[0] & 0x80000000) // page translation enabled { - translate_address(&address); + translate_address(cpustate,&address); } - value = memory_decrypted_read_byte(I.program, address & I.a20_mask); - I.eip++; - I.pc++; + value = memory_decrypted_read_byte(cpustate->program, address & cpustate->a20_mask); + cpustate->eip++; + cpustate->pc++; return value; } -INLINE UINT16 FETCH16(void) +INLINE UINT16 FETCH16(i386_state *cpustate) { UINT16 value; - UINT32 address = I.pc; + UINT32 address = cpustate->pc; - if (I.cr[0] & 0x80000000) // page translation enabled + if (cpustate->cr[0] & 0x80000000) // page translation enabled { - translate_address(&address); + translate_address(cpustate,&address); } if( address & 0x1 ) { /* Unaligned read */ - address &= I.a20_mask; - value = (memory_decrypted_read_byte(I.program, address+0) << 0) | - (memory_decrypted_read_byte(I.program, address+1) << 8); + address &= cpustate->a20_mask; + value = (memory_decrypted_read_byte(cpustate->program, address+0) << 0) | + (memory_decrypted_read_byte(cpustate->program, address+1) << 8); } else { - address &= I.a20_mask; - value = memory_decrypted_read_word(I.program, address); + address &= cpustate->a20_mask; + value = memory_decrypted_read_word(cpustate->program, address); } - I.eip += 2; - I.pc += 2; + cpustate->eip += 2; + cpustate->pc += 2; return value; } -INLINE UINT32 FETCH32(void) +INLINE UINT32 FETCH32(i386_state *cpustate) { UINT32 value; - UINT32 address = I.pc; + UINT32 address = cpustate->pc; - if (I.cr[0] & 0x80000000) // page translation enabled + if (cpustate->cr[0] & 0x80000000) // page translation enabled { - translate_address(&address); + translate_address(cpustate,&address); } - if( I.pc & 0x3 ) { /* Unaligned read */ - address &= I.a20_mask; - value = (memory_decrypted_read_byte(I.program, address+0) << 0) | - (memory_decrypted_read_byte(I.program, address+1) << 8) | - (memory_decrypted_read_byte(I.program, address+2) << 16) | - (memory_decrypted_read_byte(I.program, address+3) << 24); + if( cpustate->pc & 0x3 ) { /* Unaligned read */ + address &= cpustate->a20_mask; + value = (memory_decrypted_read_byte(cpustate->program, address+0) << 0) | + (memory_decrypted_read_byte(cpustate->program, address+1) << 8) | + (memory_decrypted_read_byte(cpustate->program, address+2) << 16) | + (memory_decrypted_read_byte(cpustate->program, address+3) << 24); } else { - address &= I.a20_mask; - value = memory_decrypted_read_dword(I.program, address); + address &= cpustate->a20_mask; + value = memory_decrypted_read_dword(cpustate->program, address); } - I.eip += 4; - I.pc += 4; + cpustate->eip += 4; + cpustate->pc += 4; return value; } -INLINE UINT8 READ8(UINT32 ea) +INLINE UINT8 READ8(i386_state *cpustate,UINT32 ea) { UINT32 address = ea; - if (I.cr[0] & 0x80000000) // page translation enabled + if (cpustate->cr[0] & 0x80000000) // page translation enabled { - translate_address(&address); + translate_address(cpustate,&address); } - address &= I.a20_mask; - return memory_read_byte_32le(I.program, address); + address &= cpustate->a20_mask; + return memory_read_byte_32le(cpustate->program, address); } -INLINE UINT16 READ16(UINT32 ea) +INLINE UINT16 READ16(i386_state *cpustate,UINT32 ea) { UINT16 value; UINT32 address = ea; - if (I.cr[0] & 0x80000000) // page translation enabled + if (cpustate->cr[0] & 0x80000000) // page translation enabled { - translate_address(&address); + translate_address(cpustate,&address); } - address &= I.a20_mask; + address &= cpustate->a20_mask; if( ea & 0x1 ) { /* Unaligned read */ - value = (memory_read_byte_32le( I.program, address+0 ) << 0) | - (memory_read_byte_32le( I.program, address+1 ) << 8); + value = (memory_read_byte_32le( cpustate->program, address+0 ) << 0) | + (memory_read_byte_32le( cpustate->program, address+1 ) << 8); } else { - value = memory_read_word_32le( I.program, address ); + value = memory_read_word_32le( cpustate->program, address ); } return value; } -INLINE UINT32 READ32(UINT32 ea) +INLINE UINT32 READ32(i386_state *cpustate,UINT32 ea) { UINT32 value; UINT32 address = ea; - if (I.cr[0] & 0x80000000) // page translation enabled + if (cpustate->cr[0] & 0x80000000) // page translation enabled { - translate_address(&address); + translate_address(cpustate,&address); } - address &= I.a20_mask; + address &= cpustate->a20_mask; if( ea & 0x3 ) { /* Unaligned read */ - value = (memory_read_byte_32le( I.program, address+0 ) << 0) | - (memory_read_byte_32le( I.program, address+1 ) << 8) | - (memory_read_byte_32le( I.program, address+2 ) << 16) | - (memory_read_byte_32le( I.program, address+3 ) << 24); + value = (memory_read_byte_32le( cpustate->program, address+0 ) << 0) | + (memory_read_byte_32le( cpustate->program, address+1 ) << 8) | + (memory_read_byte_32le( cpustate->program, address+2 ) << 16) | + (memory_read_byte_32le( cpustate->program, address+3 ) << 24); } else { - value = memory_read_dword_32le( I.program, address ); + value = memory_read_dword_32le( cpustate->program, address ); } return value; } -INLINE UINT64 READ64(UINT32 ea) +INLINE UINT64 READ64(i386_state *cpustate,UINT32 ea) { UINT64 value; UINT32 address = ea; - if (I.cr[0] & 0x80000000) // page translation enabled + if (cpustate->cr[0] & 0x80000000) // page translation enabled { - translate_address(&address); + translate_address(cpustate,&address); } - address &= I.a20_mask; + address &= cpustate->a20_mask; if( ea & 0x7 ) { /* Unaligned read */ - value = (((UINT64) memory_read_byte_32le( I.program, address+0 )) << 0) | - (((UINT64) memory_read_byte_32le( I.program, address+1 )) << 8) | - (((UINT64) memory_read_byte_32le( I.program, address+2 )) << 16) | - (((UINT64) memory_read_byte_32le( I.program, address+3 )) << 24) | - (((UINT64) memory_read_byte_32le( I.program, address+4 )) << 32) | - (((UINT64) memory_read_byte_32le( I.program, address+5 )) << 40) | - (((UINT64) memory_read_byte_32le( I.program, address+6 )) << 48) | - (((UINT64) memory_read_byte_32le( I.program, address+7 )) << 56); + value = (((UINT64) memory_read_byte_32le( cpustate->program, address+0 )) << 0) | + (((UINT64) memory_read_byte_32le( cpustate->program, address+1 )) << 8) | + (((UINT64) memory_read_byte_32le( cpustate->program, address+2 )) << 16) | + (((UINT64) memory_read_byte_32le( cpustate->program, address+3 )) << 24) | + (((UINT64) memory_read_byte_32le( cpustate->program, address+4 )) << 32) | + (((UINT64) memory_read_byte_32le( cpustate->program, address+5 )) << 40) | + (((UINT64) memory_read_byte_32le( cpustate->program, address+6 )) << 48) | + (((UINT64) memory_read_byte_32le( cpustate->program, address+7 )) << 56); } else { - value = (((UINT64) memory_read_dword_32le( I.program, address+0 )) << 0) | - (((UINT64) memory_read_dword_32le( I.program, address+4 )) << 32); + value = (((UINT64) memory_read_dword_32le( cpustate->program, address+0 )) << 0) | + (((UINT64) memory_read_dword_32le( cpustate->program, address+4 )) << 32); } return value; } -INLINE void WRITE8(UINT32 ea, UINT8 value) +INLINE void WRITE8(i386_state *cpustate,UINT32 ea, UINT8 value) { UINT32 address = ea; - if (I.cr[0] & 0x80000000) // page translation enabled + if (cpustate->cr[0] & 0x80000000) // page translation enabled { - translate_address(&address); + translate_address(cpustate,&address); } - address &= I.a20_mask; - memory_write_byte_32le(I.program, address, value); + address &= cpustate->a20_mask; + memory_write_byte_32le(cpustate->program, address, value); } -INLINE void WRITE16(UINT32 ea, UINT16 value) +INLINE void WRITE16(i386_state *cpustate,UINT32 ea, UINT16 value) { UINT32 address = ea; - if (I.cr[0] & 0x80000000) // page translation enabled + if (cpustate->cr[0] & 0x80000000) // page translation enabled { - translate_address(&address); + translate_address(cpustate,&address); } - address &= I.a20_mask; + address &= cpustate->a20_mask; if( ea & 0x1 ) { /* Unaligned write */ - memory_write_byte_32le( I.program, address+0, value & 0xff ); - memory_write_byte_32le( I.program, address+1, (value >> 8) & 0xff ); + memory_write_byte_32le( cpustate->program, address+0, value & 0xff ); + memory_write_byte_32le( cpustate->program, address+1, (value >> 8) & 0xff ); } else { - memory_write_word_32le(I.program, address, value); + memory_write_word_32le(cpustate->program, address, value); } } -INLINE void WRITE32(UINT32 ea, UINT32 value) +INLINE void WRITE32(i386_state *cpustate,UINT32 ea, UINT32 value) { UINT32 address = ea; - if (I.cr[0] & 0x80000000) // page translation enabled + if (cpustate->cr[0] & 0x80000000) // page translation enabled { - translate_address(&address); + translate_address(cpustate,&address); } - ea &= I.a20_mask; + ea &= cpustate->a20_mask; if( ea & 0x3 ) { /* Unaligned write */ - memory_write_byte_32le( I.program, address+0, value & 0xff ); - memory_write_byte_32le( I.program, address+1, (value >> 8) & 0xff ); - memory_write_byte_32le( I.program, address+2, (value >> 16) & 0xff ); - memory_write_byte_32le( I.program, address+3, (value >> 24) & 0xff ); + memory_write_byte_32le( cpustate->program, address+0, value & 0xff ); + memory_write_byte_32le( cpustate->program, address+1, (value >> 8) & 0xff ); + memory_write_byte_32le( cpustate->program, address+2, (value >> 16) & 0xff ); + memory_write_byte_32le( cpustate->program, address+3, (value >> 24) & 0xff ); } else { - memory_write_dword_32le(I.program, address, value); + memory_write_dword_32le(cpustate->program, address, value); } } -INLINE void WRITE64(UINT32 ea, UINT64 value) +INLINE void WRITE64(i386_state *cpustate,UINT32 ea, UINT64 value) { UINT32 address = ea; - if (I.cr[0] & 0x80000000) // page translation enabled + if (cpustate->cr[0] & 0x80000000) // page translation enabled { - translate_address(&address); + translate_address(cpustate,&address); } - ea &= I.a20_mask; + ea &= cpustate->a20_mask; if( ea & 0x7 ) { /* Unaligned write */ - memory_write_byte_32le( I.program, address+0, value & 0xff ); - memory_write_byte_32le( I.program, address+1, (value >> 8) & 0xff ); - memory_write_byte_32le( I.program, address+2, (value >> 16) & 0xff ); - memory_write_byte_32le( I.program, address+3, (value >> 24) & 0xff ); - memory_write_byte_32le( I.program, address+4, (value >> 32) & 0xff ); - memory_write_byte_32le( I.program, address+5, (value >> 40) & 0xff ); - memory_write_byte_32le( I.program, address+6, (value >> 48) & 0xff ); - memory_write_byte_32le( I.program, address+7, (value >> 56) & 0xff ); + memory_write_byte_32le( cpustate->program, address+0, value & 0xff ); + memory_write_byte_32le( cpustate->program, address+1, (value >> 8) & 0xff ); + memory_write_byte_32le( cpustate->program, address+2, (value >> 16) & 0xff ); + memory_write_byte_32le( cpustate->program, address+3, (value >> 24) & 0xff ); + memory_write_byte_32le( cpustate->program, address+4, (value >> 32) & 0xff ); + memory_write_byte_32le( cpustate->program, address+5, (value >> 40) & 0xff ); + memory_write_byte_32le( cpustate->program, address+6, (value >> 48) & 0xff ); + memory_write_byte_32le( cpustate->program, address+7, (value >> 56) & 0xff ); } else { - memory_write_dword_32le(I.program, address+0, value & 0xffffffff); - memory_write_dword_32le(I.program, address+4, (value >> 32) & 0xffffffff); + memory_write_dword_32le(cpustate->program, address+0, value & 0xffffffff); + memory_write_dword_32le(cpustate->program, address+4, (value >> 32) & 0xffffffff); } } /***********************************************************************************/ -INLINE UINT8 OR8(UINT8 dst, UINT8 src) +INLINE UINT8 OR8(i386_state *cpustate,UINT8 dst, UINT8 src) { UINT8 res = dst | src; - I.CF = I.OF = 0; + cpustate->CF = cpustate->OF = 0; SetSZPF8(res); return res; } -INLINE UINT16 OR16(UINT16 dst, UINT16 src) +INLINE UINT16 OR16(i386_state *cpustate,UINT16 dst, UINT16 src) { UINT16 res = dst | src; - I.CF = I.OF = 0; + cpustate->CF = cpustate->OF = 0; SetSZPF16(res); return res; } -INLINE UINT32 OR32(UINT32 dst, UINT32 src) +INLINE UINT32 OR32(i386_state *cpustate,UINT32 dst, UINT32 src) { UINT32 res = dst | src; - I.CF = I.OF = 0; + cpustate->CF = cpustate->OF = 0; SetSZPF32(res); return res; } -INLINE UINT8 AND8(UINT8 dst, UINT8 src) +INLINE UINT8 AND8(i386_state *cpustate,UINT8 dst, UINT8 src) { UINT8 res = dst & src; - I.CF = I.OF = 0; + cpustate->CF = cpustate->OF = 0; SetSZPF8(res); return res; } -INLINE UINT16 AND16(UINT16 dst, UINT16 src) +INLINE UINT16 AND16(i386_state *cpustate,UINT16 dst, UINT16 src) { UINT16 res = dst & src; - I.CF = I.OF = 0; + cpustate->CF = cpustate->OF = 0; SetSZPF16(res); return res; } -INLINE UINT32 AND32(UINT32 dst, UINT32 src) +INLINE UINT32 AND32(i386_state *cpustate,UINT32 dst, UINT32 src) { UINT32 res = dst & src; - I.CF = I.OF = 0; + cpustate->CF = cpustate->OF = 0; SetSZPF32(res); return res; } -INLINE UINT8 XOR8(UINT8 dst, UINT8 src) +INLINE UINT8 XOR8(i386_state *cpustate,UINT8 dst, UINT8 src) { UINT8 res = dst ^ src; - I.CF = I.OF = 0; + cpustate->CF = cpustate->OF = 0; SetSZPF8(res); return res; } -INLINE UINT16 XOR16(UINT16 dst, UINT16 src) +INLINE UINT16 XOR16(i386_state *cpustate,UINT16 dst, UINT16 src) { UINT16 res = dst ^ src; - I.CF = I.OF = 0; + cpustate->CF = cpustate->OF = 0; SetSZPF16(res); return res; } -INLINE UINT32 XOR32(UINT32 dst, UINT32 src) +INLINE UINT32 XOR32(i386_state *cpustate,UINT32 dst, UINT32 src) { UINT32 res = dst ^ src; - I.CF = I.OF = 0; + cpustate->CF = cpustate->OF = 0; SetSZPF32(res); return res; } -INLINE UINT8 SUB8(UINT8 dst, UINT8 src) +INLINE UINT8 SUB8(i386_state *cpustate,UINT8 dst, UINT8 src) { UINT16 res = (UINT16)dst - (UINT16)src; SetCF8(res); @@ -691,7 +690,7 @@ INLINE UINT8 SUB8(UINT8 dst, UINT8 src) SetSZPF8(res); return (UINT8)res; } -INLINE UINT16 SUB16(UINT16 dst, UINT16 src) +INLINE UINT16 SUB16(i386_state *cpustate,UINT16 dst, UINT16 src) { UINT32 res = (UINT32)dst - (UINT32)src; SetCF16(res); @@ -700,7 +699,7 @@ INLINE UINT16 SUB16(UINT16 dst, UINT16 src) SetSZPF16(res); return (UINT16)res; } -INLINE UINT32 SUB32(UINT32 dst, UINT32 src) +INLINE UINT32 SUB32(i386_state *cpustate,UINT32 dst, UINT32 src) { UINT64 res = (UINT64)dst - (UINT64)src; SetCF32(res); @@ -710,7 +709,7 @@ INLINE UINT32 SUB32(UINT32 dst, UINT32 src) return (UINT32)res; } -INLINE UINT8 ADD8(UINT8 dst, UINT8 src) +INLINE UINT8 ADD8(i386_state *cpustate,UINT8 dst, UINT8 src) { UINT16 res = (UINT16)dst + (UINT16)src; SetCF8(res); @@ -719,7 +718,7 @@ INLINE UINT8 ADD8(UINT8 dst, UINT8 src) SetSZPF8(res); return (UINT8)res; } -INLINE UINT16 ADD16(UINT16 dst, UINT16 src) +INLINE UINT16 ADD16(i386_state *cpustate,UINT16 dst, UINT16 src) { UINT32 res = (UINT32)dst + (UINT32)src; SetCF16(res); @@ -728,7 +727,7 @@ INLINE UINT16 ADD16(UINT16 dst, UINT16 src) SetSZPF16(res); return (UINT16)res; } -INLINE UINT32 ADD32(UINT32 dst, UINT32 src) +INLINE UINT32 ADD32(i386_state *cpustate,UINT32 dst, UINT32 src) { UINT64 res = (UINT64)dst + (UINT64)src; SetCF32(res); @@ -738,7 +737,7 @@ INLINE UINT32 ADD32(UINT32 dst, UINT32 src) return (UINT32)res; } -INLINE UINT8 INC8(UINT8 dst) +INLINE UINT8 INC8(i386_state *cpustate,UINT8 dst) { UINT16 res = (UINT16)dst + 1; SetOF_Add8(res,1,dst); @@ -746,7 +745,7 @@ INLINE UINT8 INC8(UINT8 dst) SetSZPF8(res); return (UINT8)res; } -INLINE UINT16 INC16(UINT16 dst) +INLINE UINT16 INC16(i386_state *cpustate,UINT16 dst) { UINT32 res = (UINT32)dst + 1; SetOF_Add16(res,1,dst); @@ -754,7 +753,7 @@ INLINE UINT16 INC16(UINT16 dst) SetSZPF16(res); return (UINT16)res; } -INLINE UINT32 INC32(UINT32 dst) +INLINE UINT32 INC32(i386_state *cpustate,UINT32 dst) { UINT64 res = (UINT64)dst + 1; SetOF_Add32(res,1,dst); @@ -763,7 +762,7 @@ INLINE UINT32 INC32(UINT32 dst) return (UINT32)res; } -INLINE UINT8 DEC8(UINT8 dst) +INLINE UINT8 DEC8(i386_state *cpustate,UINT8 dst) { UINT16 res = (UINT16)dst - 1; SetOF_Sub8(res,1,dst); @@ -771,7 +770,7 @@ INLINE UINT8 DEC8(UINT8 dst) SetSZPF8(res); return (UINT8)res; } -INLINE UINT16 DEC16(UINT16 dst) +INLINE UINT16 DEC16(i386_state *cpustate,UINT16 dst) { UINT32 res = (UINT32)dst - 1; SetOF_Sub16(res,1,dst); @@ -779,7 +778,7 @@ INLINE UINT16 DEC16(UINT16 dst) SetSZPF16(res); return (UINT16)res; } -INLINE UINT32 DEC32(UINT32 dst) +INLINE UINT32 DEC32(i386_state *cpustate,UINT32 dst) { UINT64 res = (UINT64)dst - 1; SetOF_Sub32(res,1,dst); @@ -790,112 +789,112 @@ INLINE UINT32 DEC32(UINT32 dst) -INLINE void PUSH16(UINT16 value) +INLINE void PUSH16(i386_state *cpustate,UINT16 value) { UINT32 ea; if( STACK_32BIT ) { REG32(ESP) -= 2; - ea = i386_translate( SS, REG32(ESP) ); - WRITE16( ea, value ); + ea = i386_translate(cpustate, SS, REG32(ESP) ); + WRITE16(cpustate, ea, value ); } else { REG16(SP) -= 2; - ea = i386_translate( SS, REG16(SP) ); - WRITE16( ea, value ); + ea = i386_translate(cpustate, SS, REG16(SP) ); + WRITE16(cpustate, ea, value ); } } -INLINE void PUSH32(UINT32 value) +INLINE void PUSH32(i386_state *cpustate,UINT32 value) { UINT32 ea; if( STACK_32BIT ) { REG32(ESP) -= 4; - ea = i386_translate( SS, REG32(ESP) ); - WRITE32( ea, value ); + ea = i386_translate(cpustate, SS, REG32(ESP) ); + WRITE32(cpustate, ea, value ); } else { REG16(SP) -= 4; - ea = i386_translate( SS, REG16(SP) ); - WRITE32( ea, value ); + ea = i386_translate(cpustate, SS, REG16(SP) ); + WRITE32(cpustate, ea, value ); } } -INLINE void PUSH8(UINT8 value) +INLINE void PUSH8(i386_state *cpustate,UINT8 value) { - if( I.operand_size ) { - PUSH32((INT32)(INT8)value); + if( cpustate->operand_size ) { + PUSH32(cpustate,(INT32)(INT8)value); } else { - PUSH16((INT16)(INT8)value); + PUSH16(cpustate,(INT16)(INT8)value); } } -INLINE UINT8 POP8(void) +INLINE UINT8 POP8(i386_state *cpustate) { UINT8 value; UINT32 ea; if( STACK_32BIT ) { - ea = i386_translate( SS, REG32(ESP) ); - value = READ8( ea ); + ea = i386_translate(cpustate, SS, REG32(ESP) ); + value = READ8(cpustate, ea ); REG32(ESP) += 1; } else { - ea = i386_translate( SS, REG16(SP) ); - value = READ8( ea ); + ea = i386_translate(cpustate, SS, REG16(SP) ); + value = READ8(cpustate, ea ); REG16(SP) += 1; } return value; } -INLINE UINT16 POP16(void) +INLINE UINT16 POP16(i386_state *cpustate) { UINT16 value; UINT32 ea; if( STACK_32BIT ) { - ea = i386_translate( SS, REG32(ESP) ); - value = READ16( ea ); + ea = i386_translate(cpustate, SS, REG32(ESP) ); + value = READ16(cpustate, ea ); REG32(ESP) += 2; } else { - ea = i386_translate( SS, REG16(SP) ); - value = READ16( ea ); + ea = i386_translate(cpustate, SS, REG16(SP) ); + value = READ16(cpustate, ea ); REG16(SP) += 2; } return value; } -INLINE UINT32 POP32(void) +INLINE UINT32 POP32(i386_state *cpustate) { UINT32 value; UINT32 ea; if( STACK_32BIT ) { - ea = i386_translate( SS, REG32(ESP) ); - value = READ32( ea ); + ea = i386_translate(cpustate, SS, REG32(ESP) ); + value = READ32(cpustate, ea ); REG32(ESP) += 4; } else { - ea = i386_translate( SS, REG16(SP) ); - value = READ32( ea ); + ea = i386_translate(cpustate, SS, REG16(SP) ); + value = READ32(cpustate, ea ); REG16(SP) += 4; } return value; } -INLINE void BUMP_SI(int adjustment) +INLINE void BUMP_SI(i386_state *cpustate,int adjustment) { - if ( I.address_size ) - REG32(ESI) += ((I.DF) ? -adjustment : +adjustment); + if ( cpustate->address_size ) + REG32(ESI) += ((cpustate->DF) ? -adjustment : +adjustment); else - REG16(SI) += ((I.DF) ? -adjustment : +adjustment); + REG16(SI) += ((cpustate->DF) ? -adjustment : +adjustment); } -INLINE void BUMP_DI(int adjustment) +INLINE void BUMP_DI(i386_state *cpustate,int adjustment) { - if ( I.address_size ) - REG32(EDI) += ((I.DF) ? -adjustment : +adjustment); + if ( cpustate->address_size ) + REG32(EDI) += ((cpustate->DF) ? -adjustment : +adjustment); else - REG16(DI) += ((I.DF) ? -adjustment : +adjustment); + REG16(DI) += ((cpustate->DF) ? -adjustment : +adjustment); } /***********************************************************************************/ -#define READPORT8(port) (memory_read_byte_32le(I.io, port)) -#define READPORT16(port) (memory_read_word_32le(I.io, port)) -#define READPORT32(port) (memory_read_dword_32le(I.io, port)) -#define WRITEPORT8(port, value) (memory_write_byte_32le(I.io, port, value)) -#define WRITEPORT16(port, value) (memory_write_word_32le(I.io, port, value)) -#define WRITEPORT32(port, value) (memory_write_dword_32le(I.io, port, value)) +#define READPORT8(port) (memory_read_byte_32le(cpustate->io, port)) +#define READPORT16(port) (memory_read_word_32le(cpustate->io, port)) +#define READPORT32(port) (memory_read_dword_32le(cpustate->io, port)) +#define WRITEPORT8(port, value) (memory_write_byte_32le(cpustate->io, port, value)) +#define WRITEPORT16(port, value) (memory_write_word_32le(cpustate->io, port, value)) +#define WRITEPORT32(port, value) (memory_write_dword_32le(cpustate->io, port, value)) #endif /* __I386_H__ */ diff --git a/src/emu/cpu/i386/i386op16.c b/src/emu/cpu/i386/i386op16.c index ecccddf5050..cdddf91cdf1 100644 --- a/src/emu/cpu/i386/i386op16.c +++ b/src/emu/cpu/i386/i386op16.c @@ -1,59 +1,59 @@ -static UINT16 I386OP(shift_rotate16)(UINT8 modrm, UINT32 value, UINT8 shift) +static UINT16 I386OP(shift_rotate16)(i386_state *cpustate, UINT8 modrm, UINT32 value, UINT8 shift) { UINT16 src = value; UINT16 dst = value; if( shift == 0 ) { - CYCLES_RM(modrm, 3, 7); + CYCLES_RM(cpustate,modrm, 3, 7); } else if( shift == 1 ) { switch( (modrm >> 3) & 0x7 ) { case 0: /* ROL rm16, 1 */ - I.CF = (src & 0x8000) ? 1 : 0; - dst = (src << 1) + I.CF; - I.OF = ((src ^ dst) & 0x8000) ? 1 : 0; - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + cpustate->CF = (src & 0x8000) ? 1 : 0; + dst = (src << 1) + cpustate->CF; + cpustate->OF = ((src ^ dst) & 0x8000) ? 1 : 0; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 1: /* ROR rm16, 1 */ - I.CF = (src & 0x1) ? 1 : 0; - dst = (I.CF << 15) | (src >> 1); - I.OF = ((src ^ dst) & 0x8000) ? 1 : 0; - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + cpustate->CF = (src & 0x1) ? 1 : 0; + dst = (cpustate->CF << 15) | (src >> 1); + cpustate->OF = ((src ^ dst) & 0x8000) ? 1 : 0; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 2: /* RCL rm16, 1 */ - dst = (src << 1) + I.CF; - I.CF = (src & 0x8000) ? 1 : 0; - I.OF = ((src ^ dst) & 0x8000) ? 1 : 0; - CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); + dst = (src << 1) + cpustate->CF; + cpustate->CF = (src & 0x8000) ? 1 : 0; + cpustate->OF = ((src ^ dst) & 0x8000) ? 1 : 0; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); break; case 3: /* RCR rm16, 1 */ - dst = (I.CF << 15) | (src >> 1); - I.CF = src & 0x1; - I.OF = ((src ^ dst) & 0x8000) ? 1 : 0; - CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); + dst = (cpustate->CF << 15) | (src >> 1); + cpustate->CF = src & 0x1; + cpustate->OF = ((src ^ dst) & 0x8000) ? 1 : 0; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); break; case 4: /* SHL/SAL rm16, 1 */ case 6: dst = src << 1; - I.CF = (src & 0x8000) ? 1 : 0; - I.OF = (((I.CF << 15) ^ dst) & 0x8000) ? 1 : 0; + cpustate->CF = (src & 0x8000) ? 1 : 0; + cpustate->OF = (((cpustate->CF << 15) ^ dst) & 0x8000) ? 1 : 0; SetSZPF16(dst); - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 5: /* SHR rm16, 1 */ dst = src >> 1; - I.CF = src & 0x1; - I.OF = (dst & 0x8000) ? 1 : 0; + cpustate->CF = src & 0x1; + cpustate->OF = (dst & 0x8000) ? 1 : 0; SetSZPF16(dst); - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 7: /* SAR rm16, 1 */ dst = (INT16)(src) >> 1; - I.CF = src & 0x1; - I.OF = 0; + cpustate->CF = src & 0x1; + cpustate->OF = 0; SetSZPF16(dst); - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; } } else { @@ -63,47 +63,47 @@ static UINT16 I386OP(shift_rotate16)(UINT8 modrm, UINT32 value, UINT8 shift) case 0: /* ROL rm16, i8 */ dst = ((src & ((UINT16)0xffff >> shift)) << shift) | ((src & ((UINT16)0xffff << (16-shift))) >> (16-shift)); - I.CF = (src >> (16-shift)) & 0x1; - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + cpustate->CF = (src >> (16-shift)) & 0x1; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 1: /* ROR rm16, i8 */ dst = ((src & ((UINT16)0xffff << shift)) >> shift) | ((src & ((UINT16)0xffff >> (16-shift))) << (16-shift)); - I.CF = (src >> (shift-1)) & 0x1; - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + cpustate->CF = (src >> (shift-1)) & 0x1; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 2: /* RCL rm16, i8 */ dst = ((src & ((UINT16)0xffff >> shift)) << shift) | ((src & ((UINT16)0xffff << (17-shift))) >> (17-shift)) | - (I.CF << (shift-1)); - I.CF = (src >> (16-shift)) & 0x1; - CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); + (cpustate->CF << (shift-1)); + cpustate->CF = (src >> (16-shift)) & 0x1; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); break; case 3: /* RCR rm16, i8 */ dst = ((src & ((UINT16)0xffff << shift)) >> shift) | ((src & ((UINT16)0xffff >> (16-shift))) << (17-shift)) | - (I.CF << (16-shift)); - I.CF = (src >> (shift-1)) & 0x1; - CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); + (cpustate->CF << (16-shift)); + cpustate->CF = (src >> (shift-1)) & 0x1; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); break; case 4: /* SHL/SAL rm16, i8 */ case 6: dst = src << shift; - I.CF = (src & (1 << (16-shift))) ? 1 : 0; + cpustate->CF = (src & (1 << (16-shift))) ? 1 : 0; SetSZPF16(dst); - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 5: /* SHR rm16, i8 */ dst = src >> shift; - I.CF = (src & (1 << (shift-1))) ? 1 : 0; + cpustate->CF = (src & (1 << (shift-1))) ? 1 : 0; SetSZPF16(dst); - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 7: /* SAR rm16, i8 */ dst = (INT16)src >> shift; - I.CF = (src & (1 << (shift-1))) ? 1 : 0; + cpustate->CF = (src & (1 << (shift-1))) ? 1 : 0; SetSZPF16(dst); - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; } @@ -113,523 +113,523 @@ static UINT16 I386OP(shift_rotate16)(UINT8 modrm, UINT32 value, UINT8 shift) -static void I386OP(adc_rm16_r16)(void) // Opcode 0x11 +static void I386OP(adc_rm16_r16)(i386_state *cpustate) // Opcode 0x11 { UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG16(modrm); dst = LOAD_RM16(modrm); - src = ADD16(src, I.CF); - dst = ADD16(dst, src); + src = ADD16(cpustate,src, cpustate->CF); + dst = ADD16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG16(modrm); - dst = READ16(ea); - src = ADD16(src, I.CF); - dst = ADD16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + dst = READ16(cpustate,ea); + src = ADD16(cpustate,src, cpustate->CF); + dst = ADD16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(adc_r16_rm16)(void) // Opcode 0x13 +static void I386OP(adc_r16_rm16)(i386_state *cpustate) // Opcode 0x13 { UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM16(modrm); dst = LOAD_REG16(modrm); - src = ADD16(src, I.CF); - dst = ADD16(dst, src); + src = ADD16(cpustate,src, cpustate->CF); + dst = ADD16(cpustate,dst, src); STORE_REG16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ16(cpustate,ea); dst = LOAD_REG16(modrm); - src = ADD16(src, I.CF); - dst = ADD16(dst, src); + src = ADD16(cpustate,src, cpustate->CF); + dst = ADD16(cpustate,dst, src); STORE_REG16(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(adc_ax_i16)(void) // Opcode 0x15 +static void I386OP(adc_ax_i16)(i386_state *cpustate) // Opcode 0x15 { UINT16 src, dst; - src = FETCH16(); + src = FETCH16(cpustate); dst = REG16(AX); - src = ADD16(src, I.CF); - dst = ADD16(dst, src); + src = ADD16(cpustate,src, cpustate->CF); + dst = ADD16(cpustate,dst, src); REG16(AX) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(add_rm16_r16)(void) // Opcode 0x01 +static void I386OP(add_rm16_r16)(i386_state *cpustate) // Opcode 0x01 { UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG16(modrm); dst = LOAD_RM16(modrm); - dst = ADD16(dst, src); + dst = ADD16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG16(modrm); - dst = READ16(ea); - dst = ADD16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + dst = READ16(cpustate,ea); + dst = ADD16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(add_r16_rm16)(void) // Opcode 0x03 +static void I386OP(add_r16_rm16)(i386_state *cpustate) // Opcode 0x03 { UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM16(modrm); dst = LOAD_REG16(modrm); - dst = ADD16(dst, src); + dst = ADD16(cpustate,dst, src); STORE_REG16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ16(cpustate,ea); dst = LOAD_REG16(modrm); - dst = ADD16(dst, src); + dst = ADD16(cpustate,dst, src); STORE_REG16(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(add_ax_i16)(void) // Opcode 0x05 +static void I386OP(add_ax_i16)(i386_state *cpustate) // Opcode 0x05 { UINT16 src, dst; - src = FETCH16(); + src = FETCH16(cpustate); dst = REG16(AX); - dst = ADD16(dst, src); + dst = ADD16(cpustate,dst, src); REG16(AX) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(and_rm16_r16)(void) // Opcode 0x21 +static void I386OP(and_rm16_r16)(i386_state *cpustate) // Opcode 0x21 { UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG16(modrm); dst = LOAD_RM16(modrm); - dst = AND16(dst, src); + dst = AND16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG16(modrm); - dst = READ16(ea); - dst = AND16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + dst = READ16(cpustate,ea); + dst = AND16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(and_r16_rm16)(void) // Opcode 0x23 +static void I386OP(and_r16_rm16)(i386_state *cpustate) // Opcode 0x23 { UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM16(modrm); dst = LOAD_REG16(modrm); - dst = AND16(dst, src); + dst = AND16(cpustate,dst, src); STORE_REG16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ16(cpustate,ea); dst = LOAD_REG16(modrm); - dst = AND16(dst, src); + dst = AND16(cpustate,dst, src); STORE_REG16(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(and_ax_i16)(void) // Opcode 0x25 +static void I386OP(and_ax_i16)(i386_state *cpustate) // Opcode 0x25 { UINT16 src, dst; - src = FETCH16(); + src = FETCH16(cpustate); dst = REG16(AX); - dst = AND16(dst, src); + dst = AND16(cpustate,dst, src); REG16(AX) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(bsf_r16_rm16)(void) // Opcode 0x0f bc +static void I386OP(bsf_r16_rm16)(i386_state *cpustate) // Opcode 0x0f bc { UINT16 src, dst, temp; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM16(modrm); } else { - UINT32 ea = GetEA(modrm); - src = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ16(cpustate,ea); } dst = 0; if( src == 0 ) { - I.ZF = 1; + cpustate->ZF = 1; } else { - I.ZF = 0; + cpustate->ZF = 0; temp = 0; while( (src & (1 << temp)) == 0 ) { temp++; dst = temp; - CYCLES(CYCLES_BSF); + CYCLES(cpustate,CYCLES_BSF); } } - CYCLES(CYCLES_BSF_BASE); + CYCLES(cpustate,CYCLES_BSF_BASE); STORE_REG16(modrm, dst); } -static void I386OP(bsr_r16_rm16)(void) // Opcode 0x0f bd +static void I386OP(bsr_r16_rm16)(i386_state *cpustate) // Opcode 0x0f bd { UINT16 src, dst, temp; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM16(modrm); } else { - UINT32 ea = GetEA(modrm); - src = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ16(cpustate,ea); } dst = 0; if( src == 0 ) { - I.ZF = 1; + cpustate->ZF = 1; } else { - I.ZF = 0; + cpustate->ZF = 0; dst = temp = 15; while( (src & (1 << temp)) == 0 ) { temp--; dst = temp; - CYCLES(CYCLES_BSR); + CYCLES(cpustate,CYCLES_BSR); } } - CYCLES(CYCLES_BSR_BASE); + CYCLES(cpustate,CYCLES_BSR_BASE); STORE_REG16(modrm, dst); } -static void I386OP(bt_rm16_r16)(void) // Opcode 0x0f a3 +static void I386OP(bt_rm16_r16)(i386_state *cpustate) // Opcode 0x0f a3 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT16 dst = LOAD_RM16(modrm); UINT16 bit = LOAD_REG16(modrm); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; - CYCLES(CYCLES_BT_REG_REG); + CYCLES(cpustate,CYCLES_BT_REG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); UINT16 bit = LOAD_REG16(modrm); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; - CYCLES(CYCLES_BT_REG_MEM); + CYCLES(cpustate,CYCLES_BT_REG_MEM); } } -static void I386OP(btc_rm16_r16)(void) // Opcode 0x0f bb +static void I386OP(btc_rm16_r16)(i386_state *cpustate) // Opcode 0x0f bb { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT16 dst = LOAD_RM16(modrm); UINT16 bit = LOAD_REG16(modrm); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst ^= (1 << bit); STORE_RM16(modrm, dst); - CYCLES(CYCLES_BTC_REG_REG); + CYCLES(cpustate,CYCLES_BTC_REG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); UINT16 bit = LOAD_REG16(modrm); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst ^= (1 << bit); - WRITE16(ea, dst); - CYCLES(CYCLES_BTC_REG_MEM); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_BTC_REG_MEM); } } -static void I386OP(btr_rm16_r16)(void) // Opcode 0x0f b3 +static void I386OP(btr_rm16_r16)(i386_state *cpustate) // Opcode 0x0f b3 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT16 dst = LOAD_RM16(modrm); UINT16 bit = LOAD_REG16(modrm); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst &= ~(1 << bit); STORE_RM16(modrm, dst); - CYCLES(CYCLES_BTR_REG_REG); + CYCLES(cpustate,CYCLES_BTR_REG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); UINT16 bit = LOAD_REG16(modrm); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst &= ~(1 << bit); - WRITE16(ea, dst); - CYCLES(CYCLES_BTR_REG_MEM); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_BTR_REG_MEM); } } -static void I386OP(bts_rm16_r16)(void) // Opcode 0x0f ab +static void I386OP(bts_rm16_r16)(i386_state *cpustate) // Opcode 0x0f ab { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT16 dst = LOAD_RM16(modrm); UINT16 bit = LOAD_REG16(modrm); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst |= (1 << bit); STORE_RM16(modrm, dst); - CYCLES(CYCLES_BTS_REG_REG); + CYCLES(cpustate,CYCLES_BTS_REG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); UINT16 bit = LOAD_REG16(modrm); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst |= (1 << bit); - WRITE16(ea, dst); - CYCLES(CYCLES_BTS_REG_MEM); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_BTS_REG_MEM); } } -static void I386OP(call_abs16)(void) // Opcode 0x9a +static void I386OP(call_abs16)(i386_state *cpustate) // Opcode 0x9a { - UINT16 offset = FETCH16(); - UINT16 ptr = FETCH16(); + UINT16 offset = FETCH16(cpustate); + UINT16 ptr = FETCH16(cpustate); if( PROTECTED_MODE ) { /* TODO */ fatalerror("i386: call_abs16 in protected mode unimplemented"); } else { - if (I.sreg[CS].d) + if (cpustate->sreg[CS].d) { - PUSH32( I.sreg[CS].selector ); - PUSH32( I.eip ); + PUSH32(cpustate, cpustate->sreg[CS].selector ); + PUSH32(cpustate, cpustate->eip ); } else { - PUSH16( I.sreg[CS].selector ); - PUSH16( I.eip ); + PUSH16(cpustate, cpustate->sreg[CS].selector ); + PUSH16(cpustate, cpustate->eip ); } - I.sreg[CS].selector = ptr; - I.eip = offset; - i386_load_segment_descriptor(CS); + cpustate->sreg[CS].selector = ptr; + cpustate->eip = offset; + i386_load_segment_descriptor(cpustate,CS); } - CYCLES(CYCLES_CALL_INTERSEG); /* TODO: Timing = 17 + m */ - CHANGE_PC(I.eip); + CYCLES(cpustate,CYCLES_CALL_INTERSEG); /* TODO: Timing = 17 + m */ + CHANGE_PC(cpustate,cpustate->eip); } -static void I386OP(call_rel16)(void) // Opcode 0xe8 +static void I386OP(call_rel16)(i386_state *cpustate) // Opcode 0xe8 { - INT16 disp = FETCH16(); + INT16 disp = FETCH16(cpustate); - PUSH16( I.eip ); - if (I.sreg[CS].d) + PUSH16(cpustate, cpustate->eip ); + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_CALL); /* TODO: Timing = 7 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_CALL); /* TODO: Timing = 7 + m */ } -static void I386OP(cbw)(void) // Opcode 0x98 +static void I386OP(cbw)(i386_state *cpustate) // Opcode 0x98 { REG16(AX) = (INT16)((INT8)REG8(AL)); - CYCLES(CYCLES_CBW); + CYCLES(cpustate,CYCLES_CBW); } -static void I386OP(cmp_rm16_r16)(void) // Opcode 0x39 +static void I386OP(cmp_rm16_r16)(i386_state *cpustate) // Opcode 0x39 { UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG16(modrm); dst = LOAD_RM16(modrm); - SUB16(dst, src); - CYCLES(CYCLES_CMP_REG_REG); + SUB16(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG16(modrm); - dst = READ16(ea); - SUB16(dst, src); - CYCLES(CYCLES_CMP_REG_MEM); + dst = READ16(cpustate,ea); + SUB16(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_MEM); } } -static void I386OP(cmp_r16_rm16)(void) // Opcode 0x3b +static void I386OP(cmp_r16_rm16)(i386_state *cpustate) // Opcode 0x3b { UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM16(modrm); dst = LOAD_REG16(modrm); - SUB16(dst, src); - CYCLES(CYCLES_CMP_REG_REG); + SUB16(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ16(cpustate,ea); dst = LOAD_REG16(modrm); - SUB16(dst, src); - CYCLES(CYCLES_CMP_MEM_REG); + SUB16(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_MEM_REG); } } -static void I386OP(cmp_ax_i16)(void) // Opcode 0x3d +static void I386OP(cmp_ax_i16)(i386_state *cpustate) // Opcode 0x3d { UINT16 src, dst; - src = FETCH16(); + src = FETCH16(cpustate); dst = REG16(AX); - SUB16(dst, src); - CYCLES(CYCLES_CMP_IMM_ACC); + SUB16(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_IMM_ACC); } -static void I386OP(cmpsw)(void) // Opcode 0xa7 +static void I386OP(cmpsw)(i386_state *cpustate) // Opcode 0xa7 { UINT32 eas, ead; UINT16 src, dst; - if( I.segment_prefix ) { - eas = i386_translate( I.segment_override, I.address_size ? REG32(ESI) : REG16(SI) ); + if( cpustate->segment_prefix ) { + eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } else { - eas = i386_translate( DS, I.address_size ? REG32(ESI) : REG16(SI) ); + eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } - ead = i386_translate( ES, I.address_size ? REG32(EDI) : REG16(DI) ); - src = READ16(eas); - dst = READ16(ead); - SUB16(dst, src); - BUMP_SI(2); - BUMP_DI(2); - CYCLES(CYCLES_CMPS); + ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI) ); + src = READ16(cpustate,eas); + dst = READ16(cpustate,ead); + SUB16(cpustate,dst, src); + BUMP_SI(cpustate,2); + BUMP_DI(cpustate,2); + CYCLES(cpustate,CYCLES_CMPS); } -static void I386OP(cwd)(void) // Opcode 0x99 +static void I386OP(cwd)(i386_state *cpustate) // Opcode 0x99 { if( REG16(AX) & 0x8000 ) { REG16(DX) = 0xffff; } else { REG16(DX) = 0x0000; } - CYCLES(CYCLES_CWD); + CYCLES(cpustate,CYCLES_CWD); } -static void I386OP(dec_ax)(void) // Opcode 0x48 +static void I386OP(dec_ax)(i386_state *cpustate) // Opcode 0x48 { - REG16(AX) = DEC16( REG16(AX) ); - CYCLES(CYCLES_DEC_REG); + REG16(AX) = DEC16(cpustate, REG16(AX) ); + CYCLES(cpustate,CYCLES_DEC_REG); } -static void I386OP(dec_cx)(void) // Opcode 0x49 +static void I386OP(dec_cx)(i386_state *cpustate) // Opcode 0x49 { - REG16(CX) = DEC16( REG16(CX) ); - CYCLES(CYCLES_DEC_REG); + REG16(CX) = DEC16(cpustate, REG16(CX) ); + CYCLES(cpustate,CYCLES_DEC_REG); } -static void I386OP(dec_dx)(void) // Opcode 0x4a +static void I386OP(dec_dx)(i386_state *cpustate) // Opcode 0x4a { - REG16(DX) = DEC16( REG16(DX) ); - CYCLES(CYCLES_DEC_REG); + REG16(DX) = DEC16(cpustate, REG16(DX) ); + CYCLES(cpustate,CYCLES_DEC_REG); } -static void I386OP(dec_bx)(void) // Opcode 0x4b +static void I386OP(dec_bx)(i386_state *cpustate) // Opcode 0x4b { - REG16(BX) = DEC16( REG16(BX) ); - CYCLES(CYCLES_DEC_REG); + REG16(BX) = DEC16(cpustate, REG16(BX) ); + CYCLES(cpustate,CYCLES_DEC_REG); } -static void I386OP(dec_sp)(void) // Opcode 0x4c +static void I386OP(dec_sp)(i386_state *cpustate) // Opcode 0x4c { - REG16(SP) = DEC16( REG16(SP) ); - CYCLES(CYCLES_DEC_REG); + REG16(SP) = DEC16(cpustate, REG16(SP) ); + CYCLES(cpustate,CYCLES_DEC_REG); } -static void I386OP(dec_bp)(void) // Opcode 0x4d +static void I386OP(dec_bp)(i386_state *cpustate) // Opcode 0x4d { - REG16(BP) = DEC16( REG16(BP) ); - CYCLES(CYCLES_DEC_REG); + REG16(BP) = DEC16(cpustate, REG16(BP) ); + CYCLES(cpustate,CYCLES_DEC_REG); } -static void I386OP(dec_si)(void) // Opcode 0x4e +static void I386OP(dec_si)(i386_state *cpustate) // Opcode 0x4e { - REG16(SI) = DEC16( REG16(SI) ); - CYCLES(CYCLES_DEC_REG); + REG16(SI) = DEC16(cpustate, REG16(SI) ); + CYCLES(cpustate,CYCLES_DEC_REG); } -static void I386OP(dec_di)(void) // Opcode 0x4f +static void I386OP(dec_di)(i386_state *cpustate) // Opcode 0x4f { - REG16(DI) = DEC16( REG16(DI) ); - CYCLES(CYCLES_DEC_REG); + REG16(DI) = DEC16(cpustate, REG16(DI) ); + CYCLES(cpustate,CYCLES_DEC_REG); } -static void I386OP(imul_r16_rm16)(void) // Opcode 0x0f af +static void I386OP(imul_r16_rm16)(i386_state *cpustate) // Opcode 0x0f af { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); INT32 result; INT32 src, dst; if( modrm >= 0xc0 ) { src = (INT32)(INT16)LOAD_RM16(modrm); - CYCLES(CYCLES_IMUL16_REG_REG); /* TODO: Correct multiply timing */ + CYCLES(cpustate,CYCLES_IMUL16_REG_REG); /* TODO: Correct multiply timing */ } else { - UINT32 ea = GetEA(modrm); - src = (INT32)(INT16)READ16(ea); - CYCLES(CYCLES_IMUL16_REG_MEM); /* TODO: Correct multiply timing */ + UINT32 ea = GetEA(cpustate,modrm); + src = (INT32)(INT16)READ16(cpustate,ea); + CYCLES(cpustate,CYCLES_IMUL16_REG_MEM); /* TODO: Correct multiply timing */ } dst = (INT32)(INT16)LOAD_REG16(modrm); @@ -637,1201 +637,1201 @@ static void I386OP(imul_r16_rm16)(void) // Opcode 0x0f af STORE_REG16(modrm, (UINT16)result); - I.CF = I.OF = !(result == (INT32)(INT16)result); + cpustate->CF = cpustate->OF = !(result == (INT32)(INT16)result); } -static void I386OP(imul_r16_rm16_i16)(void) // Opcode 0x69 +static void I386OP(imul_r16_rm16_i16)(i386_state *cpustate) // Opcode 0x69 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); INT32 result; INT32 src, dst; if( modrm >= 0xc0 ) { dst = (INT32)(INT16)LOAD_RM16(modrm); - CYCLES(CYCLES_IMUL16_REG_IMM_REG); /* TODO: Correct multiply timing */ + CYCLES(cpustate,CYCLES_IMUL16_REG_IMM_REG); /* TODO: Correct multiply timing */ } else { - UINT32 ea = GetEA(modrm); - dst = (INT32)(INT16)READ16(ea); - CYCLES(CYCLES_IMUL16_MEM_IMM_REG); /* TODO: Correct multiply timing */ + UINT32 ea = GetEA(cpustate,modrm); + dst = (INT32)(INT16)READ16(cpustate,ea); + CYCLES(cpustate,CYCLES_IMUL16_MEM_IMM_REG); /* TODO: Correct multiply timing */ } - src = (INT32)(INT16)FETCH16(); + src = (INT32)(INT16)FETCH16(cpustate); result = src * dst; STORE_REG16(modrm, (UINT16)result); - I.CF = I.OF = !(result == (INT32)(INT16)result); + cpustate->CF = cpustate->OF = !(result == (INT32)(INT16)result); } -static void I386OP(imul_r16_rm16_i8)(void) // Opcode 0x6b +static void I386OP(imul_r16_rm16_i8)(i386_state *cpustate) // Opcode 0x6b { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); INT32 result; INT32 src, dst; if( modrm >= 0xc0 ) { dst = (INT32)(INT16)LOAD_RM16(modrm); - CYCLES(CYCLES_IMUL16_REG_IMM_REG); /* TODO: Correct multiply timing */ + CYCLES(cpustate,CYCLES_IMUL16_REG_IMM_REG); /* TODO: Correct multiply timing */ } else { - UINT32 ea = GetEA(modrm); - dst = (INT32)(INT16)READ16(ea); - CYCLES(CYCLES_IMUL16_MEM_IMM_REG); /* TODO: Correct multiply timing */ + UINT32 ea = GetEA(cpustate,modrm); + dst = (INT32)(INT16)READ16(cpustate,ea); + CYCLES(cpustate,CYCLES_IMUL16_MEM_IMM_REG); /* TODO: Correct multiply timing */ } - src = (INT32)(INT8)FETCH(); + src = (INT32)(INT8)FETCH(cpustate); result = src * dst; STORE_REG16(modrm, (UINT16)result); - I.CF = I.OF = !(result == (INT32)(INT16)result); + cpustate->CF = cpustate->OF = !(result == (INT32)(INT16)result); } -static void I386OP(in_ax_i8)(void) // Opcode 0xe5 +static void I386OP(in_ax_i8)(i386_state *cpustate) // Opcode 0xe5 { - UINT16 port = FETCH(); + UINT16 port = FETCH(cpustate); UINT16 data = READPORT16(port); REG16(AX) = data; - CYCLES(CYCLES_IN_VAR); + CYCLES(cpustate,CYCLES_IN_VAR); } -static void I386OP(in_ax_dx)(void) // Opcode 0xed +static void I386OP(in_ax_dx)(i386_state *cpustate) // Opcode 0xed { UINT16 port = REG16(DX); UINT16 data = READPORT16(port); REG16(AX) = data; - CYCLES(CYCLES_IN); + CYCLES(cpustate,CYCLES_IN); } -static void I386OP(inc_ax)(void) // Opcode 0x40 +static void I386OP(inc_ax)(i386_state *cpustate) // Opcode 0x40 { - REG16(AX) = INC16( REG16(AX) ); - CYCLES(CYCLES_INC_REG); + REG16(AX) = INC16(cpustate, REG16(AX) ); + CYCLES(cpustate,CYCLES_INC_REG); } -static void I386OP(inc_cx)(void) // Opcode 0x41 +static void I386OP(inc_cx)(i386_state *cpustate) // Opcode 0x41 { - REG16(CX) = INC16( REG16(CX) ); - CYCLES(CYCLES_INC_REG); + REG16(CX) = INC16(cpustate, REG16(CX) ); + CYCLES(cpustate,CYCLES_INC_REG); } -static void I386OP(inc_dx)(void) // Opcode 0x42 +static void I386OP(inc_dx)(i386_state *cpustate) // Opcode 0x42 { - REG16(DX) = INC16( REG16(DX) ); - CYCLES(CYCLES_INC_REG); + REG16(DX) = INC16(cpustate, REG16(DX) ); + CYCLES(cpustate,CYCLES_INC_REG); } -static void I386OP(inc_bx)(void) // Opcode 0x43 +static void I386OP(inc_bx)(i386_state *cpustate) // Opcode 0x43 { - REG16(BX) = INC16( REG16(BX) ); - CYCLES(CYCLES_INC_REG); + REG16(BX) = INC16(cpustate, REG16(BX) ); + CYCLES(cpustate,CYCLES_INC_REG); } -static void I386OP(inc_sp)(void) // Opcode 0x44 +static void I386OP(inc_sp)(i386_state *cpustate) // Opcode 0x44 { - REG16(SP) = INC16( REG16(SP) ); - CYCLES(CYCLES_INC_REG); + REG16(SP) = INC16(cpustate, REG16(SP) ); + CYCLES(cpustate,CYCLES_INC_REG); } -static void I386OP(inc_bp)(void) // Opcode 0x45 +static void I386OP(inc_bp)(i386_state *cpustate) // Opcode 0x45 { - REG16(BP) = INC16( REG16(BP) ); - CYCLES(CYCLES_INC_REG); + REG16(BP) = INC16(cpustate, REG16(BP) ); + CYCLES(cpustate,CYCLES_INC_REG); } -static void I386OP(inc_si)(void) // Opcode 0x46 +static void I386OP(inc_si)(i386_state *cpustate) // Opcode 0x46 { - REG16(SI) = INC16( REG16(SI) ); - CYCLES(CYCLES_INC_REG); + REG16(SI) = INC16(cpustate, REG16(SI) ); + CYCLES(cpustate,CYCLES_INC_REG); } -static void I386OP(inc_di)(void) // Opcode 0x47 +static void I386OP(inc_di)(i386_state *cpustate) // Opcode 0x47 { - REG16(DI) = INC16( REG16(DI) ); - CYCLES(CYCLES_INC_REG); + REG16(DI) = INC16(cpustate, REG16(DI) ); + CYCLES(cpustate,CYCLES_INC_REG); } -static void I386OP(iret16)(void) // Opcode 0xcf +static void I386OP(iret16)(i386_state *cpustate) // Opcode 0xcf { if( PROTECTED_MODE ) { /* TODO: Virtual 8086-mode */ /* TODO: Nested task */ /* TODO: #SS(0) exception */ /* TODO: All the protection-related stuff... */ - I.eip = POP16(); - I.sreg[CS].selector = POP16(); - set_flags( POP16() ); - i386_load_segment_descriptor(CS); - CHANGE_PC(I.eip); + cpustate->eip = POP16(cpustate); + cpustate->sreg[CS].selector = POP16(cpustate); + set_flags(cpustate, POP16(cpustate) ); + i386_load_segment_descriptor(cpustate,CS); + CHANGE_PC(cpustate,cpustate->eip); } else { /* TODO: #SS(0) exception */ /* TODO: #GP(0) exception */ - I.eip = POP16(); - I.sreg[CS].selector = POP16(); - set_flags( POP16() ); - i386_load_segment_descriptor(CS); - CHANGE_PC(I.eip); + cpustate->eip = POP16(cpustate); + cpustate->sreg[CS].selector = POP16(cpustate); + set_flags(cpustate, POP16(cpustate) ); + i386_load_segment_descriptor(cpustate,CS); + CHANGE_PC(cpustate,cpustate->eip); } - CYCLES(CYCLES_IRET); + CYCLES(cpustate,CYCLES_IRET); } -static void I386OP(ja_rel16)(void) // Opcode 0x0f 87 +static void I386OP(ja_rel16)(i386_state *cpustate) // Opcode 0x0f 87 { - INT16 disp = FETCH16(); - if( I.CF == 0 && I.ZF == 0 ) { - if (I.sreg[CS].d) + INT16 disp = FETCH16(cpustate); + if( cpustate->CF == 0 && cpustate->ZF == 0 ) { + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jbe_rel16)(void) // Opcode 0x0f 86 +static void I386OP(jbe_rel16)(i386_state *cpustate) // Opcode 0x0f 86 { - INT16 disp = FETCH16(); - if( I.CF != 0 || I.ZF != 0 ) { - if (I.sreg[CS].d) + INT16 disp = FETCH16(cpustate); + if( cpustate->CF != 0 || cpustate->ZF != 0 ) { + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jc_rel16)(void) // Opcode 0x0f 82 +static void I386OP(jc_rel16)(i386_state *cpustate) // Opcode 0x0f 82 { - INT16 disp = FETCH16(); - if( I.CF != 0 ) { - if (I.sreg[CS].d) + INT16 disp = FETCH16(cpustate); + if( cpustate->CF != 0 ) { + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jg_rel16)(void) // Opcode 0x0f 8f +static void I386OP(jg_rel16)(i386_state *cpustate) // Opcode 0x0f 8f { - INT16 disp = FETCH16(); - if( I.ZF == 0 && (I.SF == I.OF) ) { - if (I.sreg[CS].d) + INT16 disp = FETCH16(cpustate); + if( cpustate->ZF == 0 && (cpustate->SF == cpustate->OF) ) { + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jge_rel16)(void) // Opcode 0x0f 8d +static void I386OP(jge_rel16)(i386_state *cpustate) // Opcode 0x0f 8d { - INT16 disp = FETCH16(); - if( (I.SF == I.OF) ) { - if (I.sreg[CS].d) + INT16 disp = FETCH16(cpustate); + if( (cpustate->SF == cpustate->OF) ) { + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jl_rel16)(void) // Opcode 0x0f 8c +static void I386OP(jl_rel16)(i386_state *cpustate) // Opcode 0x0f 8c { - INT16 disp = FETCH16(); - if( (I.SF != I.OF) ) { - if (I.sreg[CS].d) + INT16 disp = FETCH16(cpustate); + if( (cpustate->SF != cpustate->OF) ) { + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jle_rel16)(void) // Opcode 0x0f 8e +static void I386OP(jle_rel16)(i386_state *cpustate) // Opcode 0x0f 8e { - INT16 disp = FETCH16(); - if( I.ZF != 0 || (I.SF != I.OF) ) { - if (I.sreg[CS].d) + INT16 disp = FETCH16(cpustate); + if( cpustate->ZF != 0 || (cpustate->SF != cpustate->OF) ) { + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jnc_rel16)(void) // Opcode 0x0f 83 +static void I386OP(jnc_rel16)(i386_state *cpustate) // Opcode 0x0f 83 { - INT16 disp = FETCH16(); - if( I.CF == 0 ) { - if (I.sreg[CS].d) + INT16 disp = FETCH16(cpustate); + if( cpustate->CF == 0 ) { + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jno_rel16)(void) // Opcode 0x0f 81 +static void I386OP(jno_rel16)(i386_state *cpustate) // Opcode 0x0f 81 { - INT16 disp = FETCH16(); - if( I.OF == 0 ) { - if (I.sreg[CS].d) + INT16 disp = FETCH16(cpustate); + if( cpustate->OF == 0 ) { + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jnp_rel16)(void) // Opcode 0x0f 8b +static void I386OP(jnp_rel16)(i386_state *cpustate) // Opcode 0x0f 8b { - INT16 disp = FETCH16(); - if( I.PF == 0 ) { - if (I.sreg[CS].d) + INT16 disp = FETCH16(cpustate); + if( cpustate->PF == 0 ) { + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jns_rel16)(void) // Opcode 0x0f 89 +static void I386OP(jns_rel16)(i386_state *cpustate) // Opcode 0x0f 89 { - INT16 disp = FETCH16(); - if( I.SF == 0 ) { - if (I.sreg[CS].d) + INT16 disp = FETCH16(cpustate); + if( cpustate->SF == 0 ) { + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jnz_rel16)(void) // Opcode 0x0f 85 +static void I386OP(jnz_rel16)(i386_state *cpustate) // Opcode 0x0f 85 { - INT16 disp = FETCH16(); - if( I.ZF == 0 ) { - if (I.sreg[CS].d) + INT16 disp = FETCH16(cpustate); + if( cpustate->ZF == 0 ) { + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jo_rel16)(void) // Opcode 0x0f 80 +static void I386OP(jo_rel16)(i386_state *cpustate) // Opcode 0x0f 80 { - INT16 disp = FETCH16(); - if( I.OF != 0 ) { - if (I.sreg[CS].d) + INT16 disp = FETCH16(cpustate); + if( cpustate->OF != 0 ) { + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jp_rel16)(void) // Opcode 0x0f 8a +static void I386OP(jp_rel16)(i386_state *cpustate) // Opcode 0x0f 8a { - INT16 disp = FETCH16(); - if( I.PF != 0 ) { - if (I.sreg[CS].d) + INT16 disp = FETCH16(cpustate); + if( cpustate->PF != 0 ) { + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(js_rel16)(void) // Opcode 0x0f 88 +static void I386OP(js_rel16)(i386_state *cpustate) // Opcode 0x0f 88 { - INT16 disp = FETCH16(); - if( I.SF != 0 ) { - if (I.sreg[CS].d) + INT16 disp = FETCH16(cpustate); + if( cpustate->SF != 0 ) { + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jz_rel16)(void) // Opcode 0x0f 84 +static void I386OP(jz_rel16)(i386_state *cpustate) // Opcode 0x0f 84 { - INT16 disp = FETCH16(); - if( I.ZF != 0 ) { - if (I.sreg[CS].d) + INT16 disp = FETCH16(cpustate); + if( cpustate->ZF != 0 ) { + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jcxz16)(void) // Opcode 0xe3 +static void I386OP(jcxz16)(i386_state *cpustate) // Opcode 0xe3 { - INT8 disp = FETCH(); + INT8 disp = FETCH(cpustate); if( REG16(CX) == 0 ) { - if (I.sreg[CS].d) + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCXZ); /* TODO: Timing = 9 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCXZ); /* TODO: Timing = 9 + m */ } else { - CYCLES(CYCLES_JCXZ_NOBRANCH); + CYCLES(cpustate,CYCLES_JCXZ_NOBRANCH); } } -static void I386OP(jmp_rel16)(void) // Opcode 0xe9 +static void I386OP(jmp_rel16)(i386_state *cpustate) // Opcode 0xe9 { - INT16 disp = FETCH16(); + INT16 disp = FETCH16(cpustate); - if (I.sreg[CS].d) + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); - CYCLES(CYCLES_JMP); /* TODO: Timing = 7 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JMP); /* TODO: Timing = 7 + m */ } -static void I386OP(jmp_abs16)(void) // Opcode 0xea +static void I386OP(jmp_abs16)(i386_state *cpustate) // Opcode 0xea { - UINT16 address = FETCH16(); - UINT16 segment = FETCH16(); + UINT16 address = FETCH16(cpustate); + UINT16 segment = FETCH16(cpustate); if( PROTECTED_MODE ) { /* TODO: #GP */ /* TODO: access rights, etc. */ - I.eip = address; - I.sreg[CS].selector = segment; - I.performed_intersegment_jump = 1; - i386_load_segment_descriptor(CS); - CHANGE_PC(I.eip); + cpustate->eip = address; + cpustate->sreg[CS].selector = segment; + cpustate->performed_intersegment_jump = 1; + i386_load_segment_descriptor(cpustate,CS); + CHANGE_PC(cpustate,cpustate->eip); } else { - I.eip = address; - I.sreg[CS].selector = segment; - I.performed_intersegment_jump = 1; - i386_load_segment_descriptor(CS); - CHANGE_PC(I.eip); + cpustate->eip = address; + cpustate->sreg[CS].selector = segment; + cpustate->performed_intersegment_jump = 1; + i386_load_segment_descriptor(cpustate,CS); + CHANGE_PC(cpustate,cpustate->eip); } - CYCLES(CYCLES_JMP_INTERSEG); + CYCLES(cpustate,CYCLES_JMP_INTERSEG); } -static void I386OP(lea16)(void) // Opcode 0x8d +static void I386OP(lea16)(i386_state *cpustate) // Opcode 0x8d { - UINT8 modrm = FETCH(); - UINT32 ea = GetNonTranslatedEA(modrm); + UINT8 modrm = FETCH(cpustate); + UINT32 ea = GetNonTranslatedEA(cpustate,modrm); STORE_REG16(modrm, ea); - CYCLES(CYCLES_LEA); + CYCLES(cpustate,CYCLES_LEA); } -static void I386OP(leave16)(void) // Opcode 0xc9 +static void I386OP(leave16)(i386_state *cpustate) // Opcode 0xc9 { REG16(SP) = REG16(BP); - REG16(BP) = POP16(); - CYCLES(CYCLES_LEAVE); + REG16(BP) = POP16(cpustate); + CYCLES(cpustate,CYCLES_LEAVE); } -static void I386OP(lodsw)(void) // Opcode 0xad +static void I386OP(lodsw)(i386_state *cpustate) // Opcode 0xad { UINT32 eas; - if( I.segment_prefix ) { - eas = i386_translate( I.segment_override, I.address_size ? REG32(ESI) : REG16(SI) ); + if( cpustate->segment_prefix ) { + eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } else { - eas = i386_translate( DS, I.address_size ? REG32(ESI) : REG16(SI) ); + eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } - REG16(AX) = READ16(eas); - BUMP_SI(2); - CYCLES(CYCLES_LODS); + REG16(AX) = READ16(cpustate,eas); + BUMP_SI(cpustate,2); + CYCLES(cpustate,CYCLES_LODS); } -static void I386OP(loop16)(void) // Opcode 0xe2 +static void I386OP(loop16)(i386_state *cpustate) // Opcode 0xe2 { - INT8 disp = FETCH(); + INT8 disp = FETCH(cpustate); REG16(CX)--; if( REG16(CX) != 0 ) { - if (I.sreg[CS].d) + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); + CHANGE_PC(cpustate,cpustate->eip); } - CYCLES(CYCLES_LOOP); /* TODO: Timing = 11 + m */ + CYCLES(cpustate,CYCLES_LOOP); /* TODO: Timing = 11 + m */ } -static void I386OP(loopne16)(void) // Opcode 0xe0 +static void I386OP(loopne16)(i386_state *cpustate) // Opcode 0xe0 { - INT8 disp = FETCH(); + INT8 disp = FETCH(cpustate); REG16(CX)--; - if( REG16(CX) != 0 && I.ZF == 0 ) { - if (I.sreg[CS].d) + if( REG16(CX) != 0 && cpustate->ZF == 0 ) { + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); + CHANGE_PC(cpustate,cpustate->eip); } - CYCLES(CYCLES_LOOPNZ); /* TODO: Timing = 11 + m */ + CYCLES(cpustate,CYCLES_LOOPNZ); /* TODO: Timing = 11 + m */ } -static void I386OP(loopz16)(void) // Opcode 0xe1 +static void I386OP(loopz16)(i386_state *cpustate) // Opcode 0xe1 { - INT8 disp = FETCH(); + INT8 disp = FETCH(cpustate); REG16(CX)--; - if( REG16(CX) != 0 && I.ZF != 0 ) { - if (I.sreg[CS].d) + if( REG16(CX) != 0 && cpustate->ZF != 0 ) { + if (cpustate->sreg[CS].d) { - I.eip += disp; + cpustate->eip += disp; } else { - I.eip = (I.eip + disp) & 0xffff; + cpustate->eip = (cpustate->eip + disp) & 0xffff; } - CHANGE_PC(I.eip); + CHANGE_PC(cpustate,cpustate->eip); } - CYCLES(CYCLES_LOOPZ); /* TODO: Timing = 11 + m */ + CYCLES(cpustate,CYCLES_LOOPZ); /* TODO: Timing = 11 + m */ } -static void I386OP(mov_rm16_r16)(void) // Opcode 0x89 +static void I386OP(mov_rm16_r16)(i386_state *cpustate) // Opcode 0x89 { UINT16 src; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG16(modrm); STORE_RM16(modrm, src); - CYCLES(CYCLES_MOV_REG_REG); + CYCLES(cpustate,CYCLES_MOV_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG16(modrm); - WRITE16(ea, src); - CYCLES(CYCLES_MOV_REG_MEM); + WRITE16(cpustate,ea, src); + CYCLES(cpustate,CYCLES_MOV_REG_MEM); } } -static void I386OP(mov_r16_rm16)(void) // Opcode 0x8b +static void I386OP(mov_r16_rm16)(i386_state *cpustate) // Opcode 0x8b { UINT16 src; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM16(modrm); STORE_REG16(modrm, src); - CYCLES(CYCLES_MOV_REG_REG); + CYCLES(cpustate,CYCLES_MOV_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ16(cpustate,ea); STORE_REG16(modrm, src); - CYCLES(CYCLES_MOV_MEM_REG); + CYCLES(cpustate,CYCLES_MOV_MEM_REG); } } -static void I386OP(mov_rm16_i16)(void) // Opcode 0xc7 +static void I386OP(mov_rm16_i16)(i386_state *cpustate) // Opcode 0xc7 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { - UINT16 value = FETCH16(); + UINT16 value = FETCH16(cpustate); STORE_RM16(modrm, value); - CYCLES(CYCLES_MOV_IMM_REG); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 value = FETCH16(); - WRITE16(ea, value); - CYCLES(CYCLES_MOV_IMM_MEM); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 value = FETCH16(cpustate); + WRITE16(cpustate,ea, value); + CYCLES(cpustate,CYCLES_MOV_IMM_MEM); } } -static void I386OP(mov_ax_m16)(void) // Opcode 0xa1 +static void I386OP(mov_ax_m16)(i386_state *cpustate) // Opcode 0xa1 { UINT32 offset, ea; - if( I.address_size ) { - offset = FETCH32(); + if( cpustate->address_size ) { + offset = FETCH32(cpustate); } else { - offset = FETCH16(); + offset = FETCH16(cpustate); } /* TODO: Not sure if this is correct... */ - if( I.segment_prefix ) { - ea = i386_translate( I.segment_override, offset ); + if( cpustate->segment_prefix ) { + ea = i386_translate(cpustate, cpustate->segment_override, offset ); } else { - ea = i386_translate( DS, offset ); + ea = i386_translate(cpustate, DS, offset ); } - REG16(AX) = READ16(ea); - CYCLES(CYCLES_MOV_MEM_ACC); + REG16(AX) = READ16(cpustate,ea); + CYCLES(cpustate,CYCLES_MOV_MEM_ACC); } -static void I386OP(mov_m16_ax)(void) // Opcode 0xa3 +static void I386OP(mov_m16_ax)(i386_state *cpustate) // Opcode 0xa3 { UINT32 offset, ea; - if( I.address_size ) { - offset = FETCH32(); + if( cpustate->address_size ) { + offset = FETCH32(cpustate); } else { - offset = FETCH16(); + offset = FETCH16(cpustate); } /* TODO: Not sure if this is correct... */ - if( I.segment_prefix ) { - ea = i386_translate( I.segment_override, offset ); + if( cpustate->segment_prefix ) { + ea = i386_translate(cpustate, cpustate->segment_override, offset ); } else { - ea = i386_translate( DS, offset ); + ea = i386_translate(cpustate, DS, offset ); } - WRITE16( ea, REG16(AX) ); - CYCLES(CYCLES_MOV_ACC_MEM); + WRITE16(cpustate, ea, REG16(AX) ); + CYCLES(cpustate,CYCLES_MOV_ACC_MEM); } -static void I386OP(mov_ax_i16)(void) // Opcode 0xb8 +static void I386OP(mov_ax_i16)(i386_state *cpustate) // Opcode 0xb8 { - REG16(AX) = FETCH16(); - CYCLES(CYCLES_MOV_IMM_REG); + REG16(AX) = FETCH16(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_cx_i16)(void) // Opcode 0xb9 +static void I386OP(mov_cx_i16)(i386_state *cpustate) // Opcode 0xb9 { - REG16(CX) = FETCH16(); - CYCLES(CYCLES_MOV_IMM_REG); + REG16(CX) = FETCH16(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_dx_i16)(void) // Opcode 0xba +static void I386OP(mov_dx_i16)(i386_state *cpustate) // Opcode 0xba { - REG16(DX) = FETCH16(); - CYCLES(CYCLES_MOV_IMM_REG); + REG16(DX) = FETCH16(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_bx_i16)(void) // Opcode 0xbb +static void I386OP(mov_bx_i16)(i386_state *cpustate) // Opcode 0xbb { - REG16(BX) = FETCH16(); - CYCLES(CYCLES_MOV_IMM_REG); + REG16(BX) = FETCH16(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_sp_i16)(void) // Opcode 0xbc +static void I386OP(mov_sp_i16)(i386_state *cpustate) // Opcode 0xbc { - REG16(SP) = FETCH16(); - CYCLES(CYCLES_MOV_IMM_REG); + REG16(SP) = FETCH16(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_bp_i16)(void) // Opcode 0xbd +static void I386OP(mov_bp_i16)(i386_state *cpustate) // Opcode 0xbd { - REG16(BP) = FETCH16(); - CYCLES(CYCLES_MOV_IMM_REG); + REG16(BP) = FETCH16(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_si_i16)(void) // Opcode 0xbe +static void I386OP(mov_si_i16)(i386_state *cpustate) // Opcode 0xbe { - REG16(SI) = FETCH16(); - CYCLES(CYCLES_MOV_IMM_REG); + REG16(SI) = FETCH16(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_di_i16)(void) // Opcode 0xbf +static void I386OP(mov_di_i16)(i386_state *cpustate) // Opcode 0xbf { - REG16(DI) = FETCH16(); - CYCLES(CYCLES_MOV_IMM_REG); + REG16(DI) = FETCH16(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(movsw)(void) // Opcode 0xa5 +static void I386OP(movsw)(i386_state *cpustate) // Opcode 0xa5 { UINT32 eas, ead; UINT16 v; - if( I.segment_prefix ) { - eas = i386_translate( I.segment_override, I.address_size ? REG32(ESI) : REG16(SI) ); + if( cpustate->segment_prefix ) { + eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } else { - eas = i386_translate( DS, I.address_size ? REG32(ESI) : REG16(SI) ); + eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } - ead = i386_translate( ES, I.address_size ? REG32(EDI) : REG16(DI) ); - v = READ16(eas); - WRITE16(ead, v); - BUMP_SI(2); - BUMP_DI(2); - CYCLES(CYCLES_MOVS); + ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI) ); + v = READ16(cpustate,eas); + WRITE16(cpustate,ead, v); + BUMP_SI(cpustate,2); + BUMP_DI(cpustate,2); + CYCLES(cpustate,CYCLES_MOVS); } -static void I386OP(movsx_r16_rm8)(void) // Opcode 0x0f be +static void I386OP(movsx_r16_rm8)(i386_state *cpustate) // Opcode 0x0f be { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { INT16 src = (INT8)LOAD_RM8(modrm); STORE_REG16(modrm, src); - CYCLES(CYCLES_MOVSX_REG_REG); + CYCLES(cpustate,CYCLES_MOVSX_REG_REG); } else { - UINT32 ea = GetEA(modrm); - INT16 src = (INT8)READ8(ea); + UINT32 ea = GetEA(cpustate,modrm); + INT16 src = (INT8)READ8(cpustate,ea); STORE_REG16(modrm, src); - CYCLES(CYCLES_MOVSX_MEM_REG); + CYCLES(cpustate,CYCLES_MOVSX_MEM_REG); } } -static void I386OP(movzx_r16_rm8)(void) // Opcode 0x0f b6 +static void I386OP(movzx_r16_rm8)(i386_state *cpustate) // Opcode 0x0f b6 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT16 src = (UINT8)LOAD_RM8(modrm); STORE_REG16(modrm, src); - CYCLES(CYCLES_MOVZX_REG_REG); + CYCLES(cpustate,CYCLES_MOVZX_REG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 src = (UINT8)READ8(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 src = (UINT8)READ8(cpustate,ea); STORE_REG16(modrm, src); - CYCLES(CYCLES_MOVZX_MEM_REG); + CYCLES(cpustate,CYCLES_MOVZX_MEM_REG); } } -static void I386OP(or_rm16_r16)(void) // Opcode 0x09 +static void I386OP(or_rm16_r16)(i386_state *cpustate) // Opcode 0x09 { UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG16(modrm); dst = LOAD_RM16(modrm); - dst = OR16(dst, src); + dst = OR16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG16(modrm); - dst = READ16(ea); - dst = OR16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + dst = READ16(cpustate,ea); + dst = OR16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(or_r16_rm16)(void) // Opcode 0x0b +static void I386OP(or_r16_rm16)(i386_state *cpustate) // Opcode 0x0b { UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM16(modrm); dst = LOAD_REG16(modrm); - dst = OR16(dst, src); + dst = OR16(cpustate,dst, src); STORE_REG16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ16(cpustate,ea); dst = LOAD_REG16(modrm); - dst = OR16(dst, src); + dst = OR16(cpustate,dst, src); STORE_REG16(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(or_ax_i16)(void) // Opcode 0x0d +static void I386OP(or_ax_i16)(i386_state *cpustate) // Opcode 0x0d { UINT16 src, dst; - src = FETCH16(); + src = FETCH16(cpustate); dst = REG16(AX); - dst = OR16(dst, src); + dst = OR16(cpustate,dst, src); REG16(AX) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(out_ax_i8)(void) // Opcode 0xe7 +static void I386OP(out_ax_i8)(i386_state *cpustate) // Opcode 0xe7 { - UINT16 port = FETCH(); + UINT16 port = FETCH(cpustate); UINT16 data = REG16(AX); WRITEPORT16(port, data); - CYCLES(CYCLES_OUT_VAR); + CYCLES(cpustate,CYCLES_OUT_VAR); } -static void I386OP(out_ax_dx)(void) // Opcode 0xef +static void I386OP(out_ax_dx)(i386_state *cpustate) // Opcode 0xef { UINT16 port = REG16(DX); UINT16 data = REG16(AX); WRITEPORT16(port, data); - CYCLES(CYCLES_OUT); + CYCLES(cpustate,CYCLES_OUT); } -static void I386OP(pop_ax)(void) // Opcode 0x58 +static void I386OP(pop_ax)(i386_state *cpustate) // Opcode 0x58 { - REG16(AX) = POP16(); - CYCLES(CYCLES_POP_REG_SHORT); + REG16(AX) = POP16(cpustate); + CYCLES(cpustate,CYCLES_POP_REG_SHORT); } -static void I386OP(pop_cx)(void) // Opcode 0x59 +static void I386OP(pop_cx)(i386_state *cpustate) // Opcode 0x59 { - REG16(CX) = POP16(); - CYCLES(CYCLES_POP_REG_SHORT); + REG16(CX) = POP16(cpustate); + CYCLES(cpustate,CYCLES_POP_REG_SHORT); } -static void I386OP(pop_dx)(void) // Opcode 0x5a +static void I386OP(pop_dx)(i386_state *cpustate) // Opcode 0x5a { - REG16(DX) = POP16(); - CYCLES(CYCLES_POP_REG_SHORT); + REG16(DX) = POP16(cpustate); + CYCLES(cpustate,CYCLES_POP_REG_SHORT); } -static void I386OP(pop_bx)(void) // Opcode 0x5b +static void I386OP(pop_bx)(i386_state *cpustate) // Opcode 0x5b { - REG16(BX) = POP16(); - CYCLES(CYCLES_POP_REG_SHORT); + REG16(BX) = POP16(cpustate); + CYCLES(cpustate,CYCLES_POP_REG_SHORT); } -static void I386OP(pop_sp)(void) // Opcode 0x5c +static void I386OP(pop_sp)(i386_state *cpustate) // Opcode 0x5c { - REG16(SP) = POP16(); - CYCLES(CYCLES_POP_REG_SHORT); + REG16(SP) = POP16(cpustate); + CYCLES(cpustate,CYCLES_POP_REG_SHORT); } -static void I386OP(pop_bp)(void) // Opcode 0x5d +static void I386OP(pop_bp)(i386_state *cpustate) // Opcode 0x5d { - REG16(BP) = POP16(); - CYCLES(CYCLES_POP_REG_SHORT); + REG16(BP) = POP16(cpustate); + CYCLES(cpustate,CYCLES_POP_REG_SHORT); } -static void I386OP(pop_si)(void) // Opcode 0x5e +static void I386OP(pop_si)(i386_state *cpustate) // Opcode 0x5e { - REG16(SI) = POP16(); - CYCLES(CYCLES_POP_REG_SHORT); + REG16(SI) = POP16(cpustate); + CYCLES(cpustate,CYCLES_POP_REG_SHORT); } -static void I386OP(pop_di)(void) // Opcode 0x5f +static void I386OP(pop_di)(i386_state *cpustate) // Opcode 0x5f { - REG16(DI) = POP16(); - CYCLES(CYCLES_POP_REG_SHORT); + REG16(DI) = POP16(cpustate); + CYCLES(cpustate,CYCLES_POP_REG_SHORT); } -static void I386OP(pop_ds16)(void) // Opcode 0x1f +static void I386OP(pop_ds16)(i386_state *cpustate) // Opcode 0x1f { - I.sreg[DS].selector = POP16(); + cpustate->sreg[DS].selector = POP16(cpustate); if( PROTECTED_MODE ) { - i386_load_segment_descriptor(DS); + i386_load_segment_descriptor(cpustate,DS); } else { - i386_load_segment_descriptor(DS); + i386_load_segment_descriptor(cpustate,DS); } - CYCLES(CYCLES_POP_SREG); + CYCLES(cpustate,CYCLES_POP_SREG); } -static void I386OP(pop_es16)(void) // Opcode 0x07 +static void I386OP(pop_es16)(i386_state *cpustate) // Opcode 0x07 { - I.sreg[ES].selector = POP16(); + cpustate->sreg[ES].selector = POP16(cpustate); if( PROTECTED_MODE ) { - i386_load_segment_descriptor(ES); + i386_load_segment_descriptor(cpustate,ES); } else { - i386_load_segment_descriptor(ES); + i386_load_segment_descriptor(cpustate,ES); } - CYCLES(CYCLES_POP_SREG); + CYCLES(cpustate,CYCLES_POP_SREG); } -static void I386OP(pop_fs16)(void) // Opcode 0x0f a1 +static void I386OP(pop_fs16)(i386_state *cpustate) // Opcode 0x0f a1 { - I.sreg[FS].selector = POP16(); + cpustate->sreg[FS].selector = POP16(cpustate); if( PROTECTED_MODE ) { - i386_load_segment_descriptor(FS); + i386_load_segment_descriptor(cpustate,FS); } else { - i386_load_segment_descriptor(FS); + i386_load_segment_descriptor(cpustate,FS); } - CYCLES(CYCLES_POP_SREG); + CYCLES(cpustate,CYCLES_POP_SREG); } -static void I386OP(pop_gs16)(void) // Opcode 0x0f a9 +static void I386OP(pop_gs16)(i386_state *cpustate) // Opcode 0x0f a9 { - I.sreg[GS].selector = POP16(); + cpustate->sreg[GS].selector = POP16(cpustate); if( PROTECTED_MODE ) { - i386_load_segment_descriptor(GS); + i386_load_segment_descriptor(cpustate,GS); } else { - i386_load_segment_descriptor(GS); + i386_load_segment_descriptor(cpustate,GS); } - CYCLES(CYCLES_POP_SREG); + CYCLES(cpustate,CYCLES_POP_SREG); } -static void I386OP(pop_ss16)(void) // Opcode 0x17 +static void I386OP(pop_ss16)(i386_state *cpustate) // Opcode 0x17 { - I.sreg[SS].selector = POP16(); + cpustate->sreg[SS].selector = POP16(cpustate); if( PROTECTED_MODE ) { - i386_load_segment_descriptor(SS); + i386_load_segment_descriptor(cpustate,SS); } else { - i386_load_segment_descriptor(SS); + i386_load_segment_descriptor(cpustate,SS); } - CYCLES(CYCLES_POP_SREG); + CYCLES(cpustate,CYCLES_POP_SREG); } -static void I386OP(pop_rm16)(void) // Opcode 0x8f +static void I386OP(pop_rm16)(i386_state *cpustate) // Opcode 0x8f { - UINT8 modrm = FETCH(); - UINT16 value = POP16(); + UINT8 modrm = FETCH(cpustate); + UINT16 value = POP16(cpustate); if( modrm >= 0xc0 ) { STORE_RM16(modrm, value); } else { - UINT32 ea = GetEA(modrm); - WRITE16(ea, value); + UINT32 ea = GetEA(cpustate,modrm); + WRITE16(cpustate,ea, value); } - CYCLES(CYCLES_POP_RM); + CYCLES(cpustate,CYCLES_POP_RM); } -static void I386OP(popa)(void) // Opcode 0x61 +static void I386OP(popa)(i386_state *cpustate) // Opcode 0x61 { - REG16(DI) = POP16(); - REG16(SI) = POP16(); - REG16(BP) = POP16(); + REG16(DI) = POP16(cpustate); + REG16(SI) = POP16(cpustate); + REG16(BP) = POP16(cpustate); REG16(SP) += 2; - REG16(BX) = POP16(); - REG16(DX) = POP16(); - REG16(CX) = POP16(); - REG16(AX) = POP16(); - CYCLES(CYCLES_POPA); + REG16(BX) = POP16(cpustate); + REG16(DX) = POP16(cpustate); + REG16(CX) = POP16(cpustate); + REG16(AX) = POP16(cpustate); + CYCLES(cpustate,CYCLES_POPA); } -static void I386OP(popf)(void) // Opcode 0x9d +static void I386OP(popf)(i386_state *cpustate) // Opcode 0x9d { - UINT16 value = POP16(); - set_flags(value); - CYCLES(CYCLES_POPF); + UINT16 value = POP16(cpustate); + set_flags(cpustate,value); + CYCLES(cpustate,CYCLES_POPF); } -static void I386OP(push_ax)(void) // Opcode 0x50 +static void I386OP(push_ax)(i386_state *cpustate) // Opcode 0x50 { - PUSH16( REG16(AX) ); - CYCLES(CYCLES_PUSH_REG_SHORT); + PUSH16(cpustate, REG16(AX) ); + CYCLES(cpustate,CYCLES_PUSH_REG_SHORT); } -static void I386OP(push_cx)(void) // Opcode 0x51 +static void I386OP(push_cx)(i386_state *cpustate) // Opcode 0x51 { - PUSH16( REG16(CX) ); - CYCLES(CYCLES_PUSH_REG_SHORT); + PUSH16(cpustate, REG16(CX) ); + CYCLES(cpustate,CYCLES_PUSH_REG_SHORT); } -static void I386OP(push_dx)(void) // Opcode 0x52 +static void I386OP(push_dx)(i386_state *cpustate) // Opcode 0x52 { - PUSH16( REG16(DX) ); - CYCLES(CYCLES_PUSH_REG_SHORT); + PUSH16(cpustate, REG16(DX) ); + CYCLES(cpustate,CYCLES_PUSH_REG_SHORT); } -static void I386OP(push_bx)(void) // Opcode 0x53 +static void I386OP(push_bx)(i386_state *cpustate) // Opcode 0x53 { - PUSH16( REG16(BX) ); - CYCLES(CYCLES_PUSH_REG_SHORT); + PUSH16(cpustate, REG16(BX) ); + CYCLES(cpustate,CYCLES_PUSH_REG_SHORT); } -static void I386OP(push_sp)(void) // Opcode 0x54 +static void I386OP(push_sp)(i386_state *cpustate) // Opcode 0x54 { - PUSH16( REG16(SP) ); - CYCLES(CYCLES_PUSH_REG_SHORT); + PUSH16(cpustate, REG16(SP) ); + CYCLES(cpustate,CYCLES_PUSH_REG_SHORT); } -static void I386OP(push_bp)(void) // Opcode 0x55 +static void I386OP(push_bp)(i386_state *cpustate) // Opcode 0x55 { - PUSH16( REG16(BP) ); - CYCLES(CYCLES_PUSH_REG_SHORT); + PUSH16(cpustate, REG16(BP) ); + CYCLES(cpustate,CYCLES_PUSH_REG_SHORT); } -static void I386OP(push_si)(void) // Opcode 0x56 +static void I386OP(push_si)(i386_state *cpustate) // Opcode 0x56 { - PUSH16( REG16(SI) ); - CYCLES(CYCLES_PUSH_REG_SHORT); + PUSH16(cpustate, REG16(SI) ); + CYCLES(cpustate,CYCLES_PUSH_REG_SHORT); } -static void I386OP(push_di)(void) // Opcode 0x57 +static void I386OP(push_di)(i386_state *cpustate) // Opcode 0x57 { - PUSH16( REG16(DI) ); - CYCLES(CYCLES_PUSH_REG_SHORT); + PUSH16(cpustate, REG16(DI) ); + CYCLES(cpustate,CYCLES_PUSH_REG_SHORT); } -static void I386OP(push_cs16)(void) // Opcode 0x0e +static void I386OP(push_cs16)(i386_state *cpustate) // Opcode 0x0e { - PUSH16( I.sreg[CS].selector ); - CYCLES(CYCLES_PUSH_SREG); + PUSH16(cpustate, cpustate->sreg[CS].selector ); + CYCLES(cpustate,CYCLES_PUSH_SREG); } -static void I386OP(push_ds16)(void) // Opcode 0x1e +static void I386OP(push_ds16)(i386_state *cpustate) // Opcode 0x1e { - PUSH16( I.sreg[DS].selector ); - CYCLES(CYCLES_PUSH_SREG); + PUSH16(cpustate, cpustate->sreg[DS].selector ); + CYCLES(cpustate,CYCLES_PUSH_SREG); } -static void I386OP(push_es16)(void) // Opcode 0x06 +static void I386OP(push_es16)(i386_state *cpustate) // Opcode 0x06 { - PUSH16( I.sreg[ES].selector ); - CYCLES(CYCLES_PUSH_SREG); + PUSH16(cpustate, cpustate->sreg[ES].selector ); + CYCLES(cpustate,CYCLES_PUSH_SREG); } -static void I386OP(push_fs16)(void) // Opcode 0x0f a0 +static void I386OP(push_fs16)(i386_state *cpustate) // Opcode 0x0f a0 { - PUSH16( I.sreg[FS].selector ); - CYCLES(CYCLES_PUSH_SREG); + PUSH16(cpustate, cpustate->sreg[FS].selector ); + CYCLES(cpustate,CYCLES_PUSH_SREG); } -static void I386OP(push_gs16)(void) // Opcode 0x0f a8 +static void I386OP(push_gs16)(i386_state *cpustate) // Opcode 0x0f a8 { - PUSH16( I.sreg[GS].selector ); - CYCLES(CYCLES_PUSH_SREG); + PUSH16(cpustate, cpustate->sreg[GS].selector ); + CYCLES(cpustate,CYCLES_PUSH_SREG); } -static void I386OP(push_ss16)(void) // Opcode 0x16 +static void I386OP(push_ss16)(i386_state *cpustate) // Opcode 0x16 { - PUSH16( I.sreg[SS].selector ); - CYCLES(CYCLES_PUSH_SREG); + PUSH16(cpustate, cpustate->sreg[SS].selector ); + CYCLES(cpustate,CYCLES_PUSH_SREG); } -static void I386OP(push_i16)(void) // Opcode 0x68 +static void I386OP(push_i16)(i386_state *cpustate) // Opcode 0x68 { - UINT16 value = FETCH16(); - PUSH16(value); - CYCLES(CYCLES_PUSH_IMM); + UINT16 value = FETCH16(cpustate); + PUSH16(cpustate,value); + CYCLES(cpustate,CYCLES_PUSH_IMM); } -static void I386OP(pusha)(void) // Opcode 0x60 +static void I386OP(pusha)(i386_state *cpustate) // Opcode 0x60 { UINT16 temp = REG16(SP); - PUSH16( REG16(AX) ); - PUSH16( REG16(CX) ); - PUSH16( REG16(DX) ); - PUSH16( REG16(BX) ); - PUSH16( temp ); - PUSH16( REG16(BP) ); - PUSH16( REG16(SI) ); - PUSH16( REG16(DI) ); - CYCLES(CYCLES_PUSHA); + PUSH16(cpustate, REG16(AX) ); + PUSH16(cpustate, REG16(CX) ); + PUSH16(cpustate, REG16(DX) ); + PUSH16(cpustate, REG16(BX) ); + PUSH16(cpustate, temp ); + PUSH16(cpustate, REG16(BP) ); + PUSH16(cpustate, REG16(SI) ); + PUSH16(cpustate, REG16(DI) ); + CYCLES(cpustate,CYCLES_PUSHA); } -static void I386OP(pushf)(void) // Opcode 0x9c +static void I386OP(pushf)(i386_state *cpustate) // Opcode 0x9c { - PUSH16( get_flags() & 0xffff ); - CYCLES(CYCLES_PUSHF); + PUSH16(cpustate, get_flags(cpustate) & 0xffff ); + CYCLES(cpustate,CYCLES_PUSHF); } -static void I386OP(ret_near16_i16)(void) // Opcode 0xc2 +static void I386OP(ret_near16_i16)(i386_state *cpustate) // Opcode 0xc2 { - INT16 disp = FETCH16(); - I.eip = POP16(); + INT16 disp = FETCH16(cpustate); + cpustate->eip = POP16(cpustate); REG16(SP) += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_RET_IMM); /* TODO: Timing = 10 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_RET_IMM); /* TODO: Timing = 10 + m */ } -static void I386OP(ret_near16)(void) // Opcode 0xc3 +static void I386OP(ret_near16)(i386_state *cpustate) // Opcode 0xc3 { - I.eip = POP16(); - CHANGE_PC(I.eip); - CYCLES(CYCLES_RET); /* TODO: Timing = 10 + m */ + cpustate->eip = POP16(cpustate); + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_RET); /* TODO: Timing = 10 + m */ } -static void I386OP(sbb_rm16_r16)(void) // Opcode 0x19 +static void I386OP(sbb_rm16_r16)(i386_state *cpustate) // Opcode 0x19 { UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { - src = LOAD_REG16(modrm) + I.CF; + src = LOAD_REG16(modrm) + cpustate->CF; dst = LOAD_RM16(modrm); - dst = SUB16(dst, src); + dst = SUB16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = LOAD_REG16(modrm) + I.CF; - dst = READ16(ea); - dst = SUB16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + UINT32 ea = GetEA(cpustate,modrm); + src = LOAD_REG16(modrm) + cpustate->CF; + dst = READ16(cpustate,ea); + dst = SUB16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(sbb_r16_rm16)(void) // Opcode 0x1b +static void I386OP(sbb_r16_rm16)(i386_state *cpustate) // Opcode 0x1b { UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { - src = LOAD_RM16(modrm) + I.CF; + src = LOAD_RM16(modrm) + cpustate->CF; dst = LOAD_REG16(modrm); - dst = SUB16(dst, src); + dst = SUB16(cpustate,dst, src); STORE_REG16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ16(ea) + I.CF; + UINT32 ea = GetEA(cpustate,modrm); + src = READ16(cpustate,ea) + cpustate->CF; dst = LOAD_REG16(modrm); - dst = SUB16(dst, src); + dst = SUB16(cpustate,dst, src); STORE_REG16(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(sbb_ax_i16)(void) // Opcode 0x1d +static void I386OP(sbb_ax_i16)(i386_state *cpustate) // Opcode 0x1d { UINT16 src, dst; - src = FETCH16() + I.CF; + src = FETCH16(cpustate) + cpustate->CF; dst = REG16(AX); - dst = SUB16(dst, src); + dst = SUB16(cpustate,dst, src); REG16(AX) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(scasw)(void) // Opcode 0xaf +static void I386OP(scasw)(i386_state *cpustate) // Opcode 0xaf { UINT32 eas; UINT16 src, dst; - eas = i386_translate( ES, I.address_size ? REG32(EDI) : REG16(DI) ); - src = READ16(eas); + eas = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI) ); + src = READ16(cpustate,eas); dst = REG16(AX); - SUB16(dst, src); - BUMP_DI(2); - CYCLES(CYCLES_SCAS); + SUB16(cpustate,dst, src); + BUMP_DI(cpustate,2); + CYCLES(cpustate,CYCLES_SCAS); } -static void I386OP(shld16_i8)(void) // Opcode 0x0f a4 +static void I386OP(shld16_i8)(i386_state *cpustate) // Opcode 0x0f a4 { /* TODO: Correct flags */ - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT16 dst = LOAD_RM16(modrm); UINT16 upper = LOAD_REG16(modrm); - UINT8 shift = FETCH(); + UINT8 shift = FETCH(cpustate); if( shift > 31 || shift == 0 ) { } else if( shift > 15 ) { - I.CF = (dst & (1 << (16-shift))) ? 1 : 0; + cpustate->CF = (dst & (1 << (16-shift))) ? 1 : 0; dst = (upper << (shift-16)) | (upper >> (32-shift)); SetSZPF16(dst); } else { - I.CF = (dst & (1 << (16-shift))) ? 1 : 0; + cpustate->CF = (dst & (1 << (16-shift))) ? 1 : 0; dst = (dst << shift) | (upper >> (16-shift)); SetSZPF16(dst); } STORE_RM16(modrm, dst); - CYCLES(CYCLES_SHLD_REG); + CYCLES(cpustate,CYCLES_SHLD_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); UINT16 upper = LOAD_REG16(modrm); - UINT8 shift = FETCH(); + UINT8 shift = FETCH(cpustate); if( shift > 31 || shift == 0 ) { } else if( shift > 15 ) { - I.CF = (dst & (1 << (16-shift))) ? 1 : 0; + cpustate->CF = (dst & (1 << (16-shift))) ? 1 : 0; dst = (upper << (shift-16)) | (upper >> (32-shift)); SetSZPF16(dst); } else { - I.CF = (dst & (1 << (16-shift))) ? 1 : 0; + cpustate->CF = (dst & (1 << (16-shift))) ? 1 : 0; dst = (dst << shift) | (upper >> (16-shift)); SetSZPF16(dst); } - WRITE16(ea, dst); - CYCLES(CYCLES_SHLD_MEM); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_SHLD_MEM); } } -static void I386OP(shld16_cl)(void) // Opcode 0x0f a5 +static void I386OP(shld16_cl)(i386_state *cpustate) // Opcode 0x0f a5 { /* TODO: Correct flags */ - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT16 dst = LOAD_RM16(modrm); UINT16 upper = LOAD_REG16(modrm); @@ -1839,75 +1839,75 @@ static void I386OP(shld16_cl)(void) // Opcode 0x0f a5 if( shift > 31 || shift == 0 ) { } else if( shift > 15 ) { - I.CF = (dst & (1 << (16-shift))) ? 1 : 0; + cpustate->CF = (dst & (1 << (16-shift))) ? 1 : 0; dst = (upper << (shift-16)) | (upper >> (32-shift)); SetSZPF16(dst); } else { - I.CF = (dst & (1 << (16-shift))) ? 1 : 0; + cpustate->CF = (dst & (1 << (16-shift))) ? 1 : 0; dst = (dst << shift) | (upper >> (16-shift)); SetSZPF16(dst); } STORE_RM16(modrm, dst); - CYCLES(CYCLES_SHLD_REG); + CYCLES(cpustate,CYCLES_SHLD_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); UINT16 upper = LOAD_REG16(modrm); UINT8 shift = REG8(CL); if( shift > 31 || shift == 0 ) { } else if( shift > 15 ) { - I.CF = (dst & (1 << (16-shift))) ? 1 : 0; + cpustate->CF = (dst & (1 << (16-shift))) ? 1 : 0; dst = (upper << (shift-16)) | (upper >> (32-shift)); SetSZPF16(dst); } else { - I.CF = (dst & (1 << (16-shift))) ? 1 : 0; + cpustate->CF = (dst & (1 << (16-shift))) ? 1 : 0; dst = (dst << shift) | (upper >> (16-shift)); SetSZPF16(dst); } - WRITE16(ea, dst); - CYCLES(CYCLES_SHLD_MEM); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_SHLD_MEM); } } -static void I386OP(shrd16_i8)(void) // Opcode 0x0f ac +static void I386OP(shrd16_i8)(i386_state *cpustate) // Opcode 0x0f ac { /* TODO: Correct flags */ - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT16 dst = LOAD_RM16(modrm); UINT16 upper = LOAD_REG16(modrm); - UINT8 shift = FETCH(); + UINT8 shift = FETCH(cpustate); if( shift > 15 || shift == 0) { } else { - I.CF = (dst & (1 << (shift-1))) ? 1 : 0; + cpustate->CF = (dst & (1 << (shift-1))) ? 1 : 0; dst = (dst >> shift) | (upper << (16-shift)); SetSZPF16(dst); } STORE_RM16(modrm, dst); - CYCLES(CYCLES_SHRD_REG); + CYCLES(cpustate,CYCLES_SHRD_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); UINT16 upper = LOAD_REG16(modrm); - UINT8 shift = FETCH(); + UINT8 shift = FETCH(cpustate); if( shift > 15 || shift == 0) { } else { - I.CF = (dst & (1 << (shift-1))) ? 1 : 0; + cpustate->CF = (dst & (1 << (shift-1))) ? 1 : 0; dst = (dst >> shift) | (upper << (16-shift)); SetSZPF16(dst); } - WRITE16(ea, dst); - CYCLES(CYCLES_SHRD_MEM); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_SHRD_MEM); } } -static void I386OP(shrd16_cl)(void) // Opcode 0x0f ad +static void I386OP(shrd16_cl)(i386_state *cpustate) // Opcode 0x0f ad { /* TODO: Correct flags */ - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT16 dst = LOAD_RM16(modrm); UINT16 upper = LOAD_REG16(modrm); @@ -1915,611 +1915,611 @@ static void I386OP(shrd16_cl)(void) // Opcode 0x0f ad if( shift > 15 || shift == 0) { } else { - I.CF = (dst & (1 << (shift-1))) ? 1 : 0; + cpustate->CF = (dst & (1 << (shift-1))) ? 1 : 0; dst = (dst >> shift) | (upper << (16-shift)); SetSZPF16(dst); } STORE_RM16(modrm, dst); - CYCLES(CYCLES_SHRD_REG); + CYCLES(cpustate,CYCLES_SHRD_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); UINT16 upper = LOAD_REG16(modrm); UINT8 shift = REG8(CL); if( shift > 15 || shift == 0) { } else { - I.CF = (dst & (1 << (shift-1))) ? 1 : 0; + cpustate->CF = (dst & (1 << (shift-1))) ? 1 : 0; dst = (dst >> shift) | (upper << (16-shift)); SetSZPF16(dst); } - WRITE16(ea, dst); - CYCLES(CYCLES_SHRD_MEM); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_SHRD_MEM); } } -static void I386OP(stosw)(void) // Opcode 0xab +static void I386OP(stosw)(i386_state *cpustate) // Opcode 0xab { UINT32 ead; - ead = i386_translate( ES, I.address_size ? REG32(EDI) : REG16(DI) ); - WRITE16(ead, REG16(AX)); - BUMP_DI(2); - CYCLES(CYCLES_STOS); + ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI) ); + WRITE16(cpustate,ead, REG16(AX)); + BUMP_DI(cpustate,2); + CYCLES(cpustate,CYCLES_STOS); } -static void I386OP(sub_rm16_r16)(void) // Opcode 0x29 +static void I386OP(sub_rm16_r16)(i386_state *cpustate) // Opcode 0x29 { UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG16(modrm); dst = LOAD_RM16(modrm); - dst = SUB16(dst, src); + dst = SUB16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG16(modrm); - dst = READ16(ea); - dst = SUB16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + dst = READ16(cpustate,ea); + dst = SUB16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(sub_r16_rm16)(void) // Opcode 0x2b +static void I386OP(sub_r16_rm16)(i386_state *cpustate) // Opcode 0x2b { UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM16(modrm); dst = LOAD_REG16(modrm); - dst = SUB16(dst, src); + dst = SUB16(cpustate,dst, src); STORE_REG16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ16(cpustate,ea); dst = LOAD_REG16(modrm); - dst = SUB16(dst, src); + dst = SUB16(cpustate,dst, src); STORE_REG16(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(sub_ax_i16)(void) // Opcode 0x2d +static void I386OP(sub_ax_i16)(i386_state *cpustate) // Opcode 0x2d { UINT16 src, dst; - src = FETCH16(); + src = FETCH16(cpustate); dst = REG16(AX); - dst = SUB16(dst, src); + dst = SUB16(cpustate,dst, src); REG16(AX) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(test_ax_i16)(void) // Opcode 0xa9 +static void I386OP(test_ax_i16)(i386_state *cpustate) // Opcode 0xa9 { - UINT16 src = FETCH16(); + UINT16 src = FETCH16(cpustate); UINT16 dst = REG16(AX); dst = src & dst; SetSZPF16(dst); - I.CF = 0; - I.OF = 0; - CYCLES(CYCLES_TEST_IMM_ACC); + cpustate->CF = 0; + cpustate->OF = 0; + CYCLES(cpustate,CYCLES_TEST_IMM_ACC); } -static void I386OP(test_rm16_r16)(void) // Opcode 0x85 +static void I386OP(test_rm16_r16)(i386_state *cpustate) // Opcode 0x85 { UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG16(modrm); dst = LOAD_RM16(modrm); dst = src & dst; SetSZPF16(dst); - I.CF = 0; - I.OF = 0; - CYCLES(CYCLES_TEST_REG_REG); + cpustate->CF = 0; + cpustate->OF = 0; + CYCLES(cpustate,CYCLES_TEST_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG16(modrm); - dst = READ16(ea); + dst = READ16(cpustate,ea); dst = src & dst; SetSZPF16(dst); - I.CF = 0; - I.OF = 0; - CYCLES(CYCLES_TEST_REG_MEM); + cpustate->CF = 0; + cpustate->OF = 0; + CYCLES(cpustate,CYCLES_TEST_REG_MEM); } } -static void I386OP(xchg_ax_cx)(void) // Opcode 0x91 +static void I386OP(xchg_ax_cx)(i386_state *cpustate) // Opcode 0x91 { UINT16 temp; temp = REG16(AX); REG16(AX) = REG16(CX); REG16(CX) = temp; - CYCLES(CYCLES_XCHG_REG_REG); + CYCLES(cpustate,CYCLES_XCHG_REG_REG); } -static void I386OP(xchg_ax_dx)(void) // Opcode 0x92 +static void I386OP(xchg_ax_dx)(i386_state *cpustate) // Opcode 0x92 { UINT16 temp; temp = REG16(AX); REG16(AX) = REG16(DX); REG16(DX) = temp; - CYCLES(CYCLES_XCHG_REG_REG); + CYCLES(cpustate,CYCLES_XCHG_REG_REG); } -static void I386OP(xchg_ax_bx)(void) // Opcode 0x93 +static void I386OP(xchg_ax_bx)(i386_state *cpustate) // Opcode 0x93 { UINT16 temp; temp = REG16(AX); REG16(AX) = REG16(BX); REG16(BX) = temp; - CYCLES(CYCLES_XCHG_REG_REG); + CYCLES(cpustate,CYCLES_XCHG_REG_REG); } -static void I386OP(xchg_ax_sp)(void) // Opcode 0x94 +static void I386OP(xchg_ax_sp)(i386_state *cpustate) // Opcode 0x94 { UINT16 temp; temp = REG16(AX); REG16(AX) = REG16(SP); REG16(SP) = temp; - CYCLES(CYCLES_XCHG_REG_REG); + CYCLES(cpustate,CYCLES_XCHG_REG_REG); } -static void I386OP(xchg_ax_bp)(void) // Opcode 0x95 +static void I386OP(xchg_ax_bp)(i386_state *cpustate) // Opcode 0x95 { UINT16 temp; temp = REG16(AX); REG16(AX) = REG16(BP); REG16(BP) = temp; - CYCLES(CYCLES_XCHG_REG_REG); + CYCLES(cpustate,CYCLES_XCHG_REG_REG); } -static void I386OP(xchg_ax_si)(void) // Opcode 0x96 +static void I386OP(xchg_ax_si)(i386_state *cpustate) // Opcode 0x96 { UINT16 temp; temp = REG16(AX); REG16(AX) = REG16(SI); REG16(SI) = temp; - CYCLES(CYCLES_XCHG_REG_REG); + CYCLES(cpustate,CYCLES_XCHG_REG_REG); } -static void I386OP(xchg_ax_di)(void) // Opcode 0x97 +static void I386OP(xchg_ax_di)(i386_state *cpustate) // Opcode 0x97 { UINT16 temp; temp = REG16(AX); REG16(AX) = REG16(DI); REG16(DI) = temp; - CYCLES(CYCLES_XCHG_REG_REG); + CYCLES(cpustate,CYCLES_XCHG_REG_REG); } -static void I386OP(xchg_r16_rm16)(void) // Opcode 0x87 +static void I386OP(xchg_r16_rm16)(i386_state *cpustate) // Opcode 0x87 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT16 src = LOAD_RM16(modrm); UINT16 dst = LOAD_REG16(modrm); STORE_REG16(modrm, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_XCHG_REG_REG); + CYCLES(cpustate,CYCLES_XCHG_REG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 src = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 src = READ16(cpustate,ea); UINT16 dst = LOAD_REG16(modrm); STORE_REG16(modrm, src); - WRITE16(ea, dst); - CYCLES(CYCLES_XCHG_REG_MEM); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_XCHG_REG_MEM); } } -static void I386OP(xor_rm16_r16)(void) // Opcode 0x31 +static void I386OP(xor_rm16_r16)(i386_state *cpustate) // Opcode 0x31 { UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG16(modrm); dst = LOAD_RM16(modrm); - dst = XOR16(dst, src); + dst = XOR16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG16(modrm); - dst = READ16(ea); - dst = XOR16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + dst = READ16(cpustate,ea); + dst = XOR16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(xor_r16_rm16)(void) // Opcode 0x33 +static void I386OP(xor_r16_rm16)(i386_state *cpustate) // Opcode 0x33 { UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM16(modrm); dst = LOAD_REG16(modrm); - dst = XOR16(dst, src); + dst = XOR16(cpustate,dst, src); STORE_REG16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ16(cpustate,ea); dst = LOAD_REG16(modrm); - dst = XOR16(dst, src); + dst = XOR16(cpustate,dst, src); STORE_REG16(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(xor_ax_i16)(void) // Opcode 0x35 +static void I386OP(xor_ax_i16)(i386_state *cpustate) // Opcode 0x35 { UINT16 src, dst; - src = FETCH16(); + src = FETCH16(cpustate); dst = REG16(AX); - dst = XOR16(dst, src); + dst = XOR16(cpustate,dst, src); REG16(AX) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(group81_16)(void) // Opcode 0x81 +static void I386OP(group81_16)(i386_state *cpustate) // Opcode 0x81 { UINT32 ea; UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); switch( (modrm >> 3) & 0x7 ) { case 0: // ADD Rm16, i16 if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - src = FETCH16(); - dst = ADD16(dst, src); + src = FETCH16(cpustate); + dst = ADD16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ16(ea); - src = FETCH16(); - dst = ADD16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + src = FETCH16(cpustate); + dst = ADD16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 1: // OR Rm16, i16 if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - src = FETCH16(); - dst = OR16(dst, src); + src = FETCH16(cpustate); + dst = OR16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ16(ea); - src = FETCH16(); - dst = OR16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + src = FETCH16(cpustate); + dst = OR16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 2: // ADC Rm16, i16 if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - src = FETCH16(); - src = ADD16(src, I.CF); - dst = ADD16(dst, src); + src = FETCH16(cpustate); + src = ADD16(cpustate,src, cpustate->CF); + dst = ADD16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ16(ea); - src = FETCH16(); - src = ADD16(src, I.CF); - dst = ADD16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + src = FETCH16(cpustate); + src = ADD16(cpustate,src, cpustate->CF); + dst = ADD16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 3: // SBB Rm16, i16 if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - src = FETCH16() + I.CF; - dst = SUB16(dst, src); + src = FETCH16(cpustate) + cpustate->CF; + dst = SUB16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ16(ea); - src = FETCH16() + I.CF; - dst = SUB16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + src = FETCH16(cpustate) + cpustate->CF; + dst = SUB16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 4: // AND Rm16, i16 if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - src = FETCH16(); - dst = AND16(dst, src); + src = FETCH16(cpustate); + dst = AND16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ16(ea); - src = FETCH16(); - dst = AND16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + src = FETCH16(cpustate); + dst = AND16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 5: // SUB Rm16, i16 if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - src = FETCH16(); - dst = SUB16(dst, src); + src = FETCH16(cpustate); + dst = SUB16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ16(ea); - src = FETCH16(); - dst = SUB16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + src = FETCH16(cpustate); + dst = SUB16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 6: // XOR Rm16, i16 if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - src = FETCH16(); - dst = XOR16(dst, src); + src = FETCH16(cpustate); + dst = XOR16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ16(ea); - src = FETCH16(); - dst = XOR16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + src = FETCH16(cpustate); + dst = XOR16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 7: // CMP Rm16, i16 if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - src = FETCH16(); - SUB16(dst, src); - CYCLES(CYCLES_CMP_REG_REG); + src = FETCH16(cpustate); + SUB16(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_REG); } else { - ea = GetEA(modrm); - dst = READ16(ea); - src = FETCH16(); - SUB16(dst, src); - CYCLES(CYCLES_CMP_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + src = FETCH16(cpustate); + SUB16(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_MEM); } break; } } -static void I386OP(group83_16)(void) // Opcode 0x83 +static void I386OP(group83_16)(i386_state *cpustate) // Opcode 0x83 { UINT32 ea; UINT16 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); switch( (modrm >> 3) & 0x7 ) { case 0: // ADD Rm16, i16 if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - src = (UINT16)(INT16)(INT8)FETCH(); - dst = ADD16(dst, src); + src = (UINT16)(INT16)(INT8)FETCH(cpustate); + dst = ADD16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ16(ea); - src = (UINT16)(INT16)(INT8)FETCH(); - dst = ADD16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + src = (UINT16)(INT16)(INT8)FETCH(cpustate); + dst = ADD16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 1: // OR Rm16, i16 if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - src = (UINT16)(INT16)(INT8)FETCH(); - dst = OR16(dst, src); + src = (UINT16)(INT16)(INT8)FETCH(cpustate); + dst = OR16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ16(ea); - src = (UINT16)(INT16)(INT8)FETCH(); - dst = OR16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + src = (UINT16)(INT16)(INT8)FETCH(cpustate); + dst = OR16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 2: // ADC Rm16, i16 if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - src = (UINT16)(INT16)(INT8)FETCH(); - src = ADD16(src, I.CF); - dst = ADD16(dst, src); + src = (UINT16)(INT16)(INT8)FETCH(cpustate); + src = ADD16(cpustate,src, cpustate->CF); + dst = ADD16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ16(ea); - src = (UINT16)(INT16)(INT8)FETCH(); - src = ADD16(src, I.CF); - dst = ADD16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + src = (UINT16)(INT16)(INT8)FETCH(cpustate); + src = ADD16(cpustate,src, cpustate->CF); + dst = ADD16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 3: // SBB Rm16, i16 if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - src = ((UINT16)(INT16)(INT8)FETCH()) + I.CF; - dst = SUB16(dst, src); + src = ((UINT16)(INT16)(INT8)FETCH(cpustate)) + cpustate->CF; + dst = SUB16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ16(ea); - src = ((UINT16)(INT16)(INT8)FETCH()) + I.CF; - dst = SUB16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + src = ((UINT16)(INT16)(INT8)FETCH(cpustate)) + cpustate->CF; + dst = SUB16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 4: // AND Rm16, i16 if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - src = (UINT16)(INT16)(INT8)FETCH(); - dst = AND16(dst, src); + src = (UINT16)(INT16)(INT8)FETCH(cpustate); + dst = AND16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ16(ea); - src = (UINT16)(INT16)(INT8)FETCH(); - dst = AND16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + src = (UINT16)(INT16)(INT8)FETCH(cpustate); + dst = AND16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 5: // SUB Rm16, i16 if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - src = (UINT16)(INT16)(INT8)FETCH(); - dst = SUB16(dst, src); + src = (UINT16)(INT16)(INT8)FETCH(cpustate); + dst = SUB16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ16(ea); - src = (UINT16)(INT16)(INT8)FETCH(); - dst = SUB16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + src = (UINT16)(INT16)(INT8)FETCH(cpustate); + dst = SUB16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 6: // XOR Rm16, i16 if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - src = (UINT16)(INT16)(INT8)FETCH(); - dst = XOR16(dst, src); + src = (UINT16)(INT16)(INT8)FETCH(cpustate); + dst = XOR16(cpustate,dst, src); STORE_RM16(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ16(ea); - src = (UINT16)(INT16)(INT8)FETCH(); - dst = XOR16(dst, src); - WRITE16(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + src = (UINT16)(INT16)(INT8)FETCH(cpustate); + dst = XOR16(cpustate,dst, src); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 7: // CMP Rm16, i16 if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - src = (UINT16)(INT16)(INT8)FETCH(); - SUB16(dst, src); - CYCLES(CYCLES_CMP_REG_REG); + src = (UINT16)(INT16)(INT8)FETCH(cpustate); + SUB16(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_REG); } else { - ea = GetEA(modrm); - dst = READ16(ea); - src = (UINT16)(INT16)(INT8)FETCH(); - SUB16(dst, src); - CYCLES(CYCLES_CMP_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + src = (UINT16)(INT16)(INT8)FETCH(cpustate); + SUB16(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_MEM); } break; } } -static void I386OP(groupC1_16)(void) // Opcode 0xc1 +static void I386OP(groupC1_16)(i386_state *cpustate) // Opcode 0xc1 { UINT16 dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 shift; if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - shift = FETCH() & 0x1f; - dst = i386_shift_rotate16(modrm, dst, shift); + shift = FETCH(cpustate) & 0x1f; + dst = i386_shift_rotate16(cpustate, modrm, dst, shift); STORE_RM16(modrm, dst); } else { - UINT32 ea = GetEA(modrm); - dst = READ16(ea); - shift = FETCH() & 0x1f; - dst = i386_shift_rotate16(modrm, dst, shift); - WRITE16(ea, dst); + UINT32 ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + shift = FETCH(cpustate) & 0x1f; + dst = i386_shift_rotate16(cpustate, modrm, dst, shift); + WRITE16(cpustate,ea, dst); } } -static void I386OP(groupD1_16)(void) // Opcode 0xd1 +static void I386OP(groupD1_16)(i386_state *cpustate) // Opcode 0xd1 { UINT16 dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - dst = i386_shift_rotate16(modrm, dst, 1); + dst = i386_shift_rotate16(cpustate, modrm, dst, 1); STORE_RM16(modrm, dst); } else { - UINT32 ea = GetEA(modrm); - dst = READ16(ea); - dst = i386_shift_rotate16(modrm, dst, 1); - WRITE16(ea, dst); + UINT32 ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + dst = i386_shift_rotate16(cpustate, modrm, dst, 1); + WRITE16(cpustate,ea, dst); } } -static void I386OP(groupD3_16)(void) // Opcode 0xd3 +static void I386OP(groupD3_16)(i386_state *cpustate) // Opcode 0xd3 { UINT16 dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { dst = LOAD_RM16(modrm); - dst = i386_shift_rotate16(modrm, dst, REG8(CL)); + dst = i386_shift_rotate16(cpustate, modrm, dst, REG8(CL)); STORE_RM16(modrm, dst); } else { - UINT32 ea = GetEA(modrm); - dst = READ16(ea); - dst = i386_shift_rotate16(modrm, dst, REG8(CL)); - WRITE16(ea, dst); + UINT32 ea = GetEA(cpustate,modrm); + dst = READ16(cpustate,ea); + dst = i386_shift_rotate16(cpustate, modrm, dst, REG8(CL)); + WRITE16(cpustate,ea, dst); } } -static void I386OP(groupF7_16)(void) // Opcode 0xf7 +static void I386OP(groupF7_16)(i386_state *cpustate) // Opcode 0xf7 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); switch( (modrm >> 3) & 0x7 ) { case 0: /* TEST Rm16, i16 */ if( modrm >= 0xc0 ) { UINT16 dst = LOAD_RM16(modrm); - UINT16 src = FETCH16(); + UINT16 src = FETCH16(cpustate); dst &= src; - I.CF = I.OF = I.AF = 0; + cpustate->CF = cpustate->OF = cpustate->AF = 0; SetSZPF16(dst); - CYCLES(CYCLES_TEST_IMM_REG); + CYCLES(cpustate,CYCLES_TEST_IMM_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); - UINT16 src = FETCH16(); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); + UINT16 src = FETCH16(cpustate); dst &= src; - I.CF = I.OF = I.AF = 0; + cpustate->CF = cpustate->OF = cpustate->AF = 0; SetSZPF16(dst); - CYCLES(CYCLES_TEST_IMM_MEM); + CYCLES(cpustate,CYCLES_TEST_IMM_MEM); } break; case 2: /* NOT Rm16 */ @@ -2527,27 +2527,27 @@ static void I386OP(groupF7_16)(void) // Opcode 0xf7 UINT16 dst = LOAD_RM16(modrm); dst = ~dst; STORE_RM16(modrm, dst); - CYCLES(CYCLES_NOT_REG); + CYCLES(cpustate,CYCLES_NOT_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); dst = ~dst; - WRITE16(ea, dst); - CYCLES(CYCLES_NOT_MEM); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_NOT_MEM); } break; case 3: /* NEG Rm16 */ if( modrm >= 0xc0 ) { UINT16 dst = LOAD_RM16(modrm); - dst = SUB16( 0, dst ); + dst = SUB16(cpustate, 0, dst ); STORE_RM16(modrm, dst); - CYCLES(CYCLES_NEG_REG); + CYCLES(cpustate,CYCLES_NEG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); - dst = SUB16( 0, dst ); - WRITE16(ea, dst); - CYCLES(CYCLES_NEG_MEM); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); + dst = SUB16(cpustate, 0, dst ); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_NEG_MEM); } break; case 4: /* MUL AX, Rm16 */ @@ -2556,11 +2556,11 @@ static void I386OP(groupF7_16)(void) // Opcode 0xf7 UINT16 src, dst; if( modrm >= 0xc0 ) { src = LOAD_RM16(modrm); - CYCLES(CYCLES_MUL16_ACC_REG); /* TODO: Correct multiply timing */ + CYCLES(cpustate,CYCLES_MUL16_ACC_REG); /* TODO: Correct multiply timing */ } else { - UINT32 ea = GetEA(modrm); - src = READ16(ea); - CYCLES(CYCLES_MUL16_ACC_MEM); /* TODO: Correct multiply timing */ + UINT32 ea = GetEA(cpustate,modrm); + src = READ16(cpustate,ea); + CYCLES(cpustate,CYCLES_MUL16_ACC_MEM); /* TODO: Correct multiply timing */ } dst = REG16(AX); @@ -2568,7 +2568,7 @@ static void I386OP(groupF7_16)(void) // Opcode 0xf7 REG16(DX) = (UINT16)(result >> 16); REG16(AX) = (UINT16)result; - I.CF = I.OF = (REG16(DX) != 0); + cpustate->CF = cpustate->OF = (REG16(DX) != 0); } break; case 5: /* IMUL AX, Rm16 */ @@ -2577,11 +2577,11 @@ static void I386OP(groupF7_16)(void) // Opcode 0xf7 INT32 src, dst; if( modrm >= 0xc0 ) { src = (INT32)(INT16)LOAD_RM16(modrm); - CYCLES(CYCLES_IMUL16_ACC_REG); /* TODO: Correct multiply timing */ + CYCLES(cpustate,CYCLES_IMUL16_ACC_REG); /* TODO: Correct multiply timing */ } else { - UINT32 ea = GetEA(modrm); - src = (INT32)(INT16)READ16(ea); - CYCLES(CYCLES_IMUL16_ACC_MEM); /* TODO: Correct multiply timing */ + UINT32 ea = GetEA(cpustate,modrm); + src = (INT32)(INT16)READ16(cpustate,ea); + CYCLES(cpustate,CYCLES_IMUL16_ACC_MEM); /* TODO: Correct multiply timing */ } dst = (INT32)(INT16)REG16(AX); @@ -2590,7 +2590,7 @@ static void I386OP(groupF7_16)(void) // Opcode 0xf7 REG16(DX) = (UINT16)(result >> 16); REG16(AX) = (UINT16)result; - I.CF = I.OF = !(result == (INT32)(INT16)result); + cpustate->CF = cpustate->OF = !(result == (INT32)(INT16)result); } break; case 6: /* DIV AX, Rm16 */ @@ -2599,11 +2599,11 @@ static void I386OP(groupF7_16)(void) // Opcode 0xf7 UINT16 src; if( modrm >= 0xc0 ) { src = LOAD_RM16(modrm); - CYCLES(CYCLES_DIV16_ACC_REG); + CYCLES(cpustate,CYCLES_DIV16_ACC_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ16(ea); - CYCLES(CYCLES_DIV16_ACC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + src = READ16(cpustate,ea); + CYCLES(cpustate,CYCLES_DIV16_ACC_MEM); } quotient = ((UINT32)(REG16(DX)) << 16) | (UINT32)(REG16(AX)); @@ -2627,11 +2627,11 @@ static void I386OP(groupF7_16)(void) // Opcode 0xf7 UINT16 src; if( modrm >= 0xc0 ) { src = LOAD_RM16(modrm); - CYCLES(CYCLES_IDIV16_ACC_REG); + CYCLES(cpustate,CYCLES_IDIV16_ACC_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ16(ea); - CYCLES(CYCLES_IDIV16_ACC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + src = READ16(cpustate,ea); + CYCLES(cpustate,CYCLES_IDIV16_ACC_MEM); } quotient = (((INT32)REG16(DX)) << 16) | ((UINT32)REG16(AX)); @@ -2652,38 +2652,38 @@ static void I386OP(groupF7_16)(void) // Opcode 0xf7 } } -static void I386OP(groupFF_16)(void) // Opcode 0xff +static void I386OP(groupFF_16)(i386_state *cpustate) // Opcode 0xff { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); switch( (modrm >> 3) & 0x7 ) { case 0: /* INC Rm16 */ if( modrm >= 0xc0 ) { UINT16 dst = LOAD_RM16(modrm); - dst = INC16(dst); + dst = INC16(cpustate,dst); STORE_RM16(modrm, dst); - CYCLES(CYCLES_INC_REG); + CYCLES(cpustate,CYCLES_INC_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); - dst = INC16(dst); - WRITE16(ea, dst); - CYCLES(CYCLES_INC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); + dst = INC16(cpustate,dst); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_INC_MEM); } break; case 1: /* DEC Rm16 */ if( modrm >= 0xc0 ) { UINT16 dst = LOAD_RM16(modrm); - dst = DEC16(dst); + dst = DEC16(cpustate,dst); STORE_RM16(modrm, dst); - CYCLES(CYCLES_DEC_REG); + CYCLES(cpustate,CYCLES_DEC_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); - dst = DEC16(dst); - WRITE16(ea, dst); - CYCLES(CYCLES_DEC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); + dst = DEC16(cpustate,dst); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_DEC_MEM); } break; case 2: /* CALL Rm16 */ @@ -2691,15 +2691,15 @@ static void I386OP(groupFF_16)(void) // Opcode 0xff UINT16 address; if( modrm >= 0xc0 ) { address = LOAD_RM16(modrm); - CYCLES(CYCLES_CALL_REG); /* TODO: Timing = 7 + m */ + CYCLES(cpustate,CYCLES_CALL_REG); /* TODO: Timing = 7 + m */ } else { - UINT32 ea = GetEA(modrm); - address = READ16(ea); - CYCLES(CYCLES_CALL_MEM); /* TODO: Timing = 10 + m */ + UINT32 ea = GetEA(cpustate,modrm); + address = READ16(cpustate,ea); + CYCLES(cpustate,CYCLES_CALL_MEM); /* TODO: Timing = 10 + m */ } - PUSH16( I.eip ); - I.eip = address; - CHANGE_PC(I.eip); + PUSH16(cpustate, cpustate->eip ); + cpustate->eip = address; + CHANGE_PC(cpustate,cpustate->eip); } break; case 3: /* CALL FAR Rm16 */ @@ -2708,18 +2708,18 @@ static void I386OP(groupFF_16)(void) // Opcode 0xff if( modrm >= 0xc0 ) { fatalerror("NYI"); } else { - UINT32 ea = GetEA(modrm); - address = READ16(ea + 0); - selector = READ16(ea + 2); - CYCLES(CYCLES_CALL_MEM_INTERSEG); /* TODO: Timing = 10 + m */ + UINT32 ea = GetEA(cpustate,modrm); + address = READ16(cpustate,ea + 0); + selector = READ16(cpustate,ea + 2); + CYCLES(cpustate,CYCLES_CALL_MEM_INTERSEG); /* TODO: Timing = 10 + m */ } - PUSH16( I.sreg[CS].selector ); - PUSH16( I.eip ); - I.sreg[CS].selector = selector; - I.performed_intersegment_jump = 1; - i386_load_segment_descriptor( CS ); - I.eip = address; - CHANGE_PC(I.eip); + PUSH16(cpustate, cpustate->sreg[CS].selector ); + PUSH16(cpustate, cpustate->eip ); + cpustate->sreg[CS].selector = selector; + cpustate->performed_intersegment_jump = 1; + i386_load_segment_descriptor(cpustate, CS ); + cpustate->eip = address; + CHANGE_PC(cpustate,cpustate->eip); } break; case 4: /* JMP Rm16 */ @@ -2727,14 +2727,14 @@ static void I386OP(groupFF_16)(void) // Opcode 0xff UINT16 address; if( modrm >= 0xc0 ) { address = LOAD_RM16(modrm); - CYCLES(CYCLES_JMP_REG); /* TODO: Timing = 7 + m */ + CYCLES(cpustate,CYCLES_JMP_REG); /* TODO: Timing = 7 + m */ } else { - UINT32 ea = GetEA(modrm); - address = READ16(ea); - CYCLES(CYCLES_JMP_MEM); /* TODO: Timing = 10 + m */ + UINT32 ea = GetEA(cpustate,modrm); + address = READ16(cpustate,ea); + CYCLES(cpustate,CYCLES_JMP_MEM); /* TODO: Timing = 10 + m */ } - I.eip = address; - CHANGE_PC(I.eip); + cpustate->eip = address; + CHANGE_PC(cpustate,cpustate->eip); } break; case 5: /* JMP FAR Rm16 */ @@ -2743,16 +2743,16 @@ static void I386OP(groupFF_16)(void) // Opcode 0xff if( modrm >= 0xc0 ) { fatalerror("NYI"); } else { - UINT32 ea = GetEA(modrm); - address = READ16(ea + 0); - selector = READ16(ea + 2); - CYCLES(CYCLES_JMP_MEM_INTERSEG); /* TODO: Timing = 10 + m */ + UINT32 ea = GetEA(cpustate,modrm); + address = READ16(cpustate,ea + 0); + selector = READ16(cpustate,ea + 2); + CYCLES(cpustate,CYCLES_JMP_MEM_INTERSEG); /* TODO: Timing = 10 + m */ } - I.sreg[CS].selector = selector; - I.performed_intersegment_jump = 1; - i386_load_segment_descriptor( CS ); - I.eip = address; - CHANGE_PC(I.eip); + cpustate->sreg[CS].selector = selector; + cpustate->performed_intersegment_jump = 1; + i386_load_segment_descriptor(cpustate, CS ); + cpustate->eip = address; + CHANGE_PC(cpustate,cpustate->eip); } break; case 6: /* PUSH Rm16 */ @@ -2761,15 +2761,15 @@ static void I386OP(groupFF_16)(void) // Opcode 0xff if( modrm >= 0xc0 ) { value = LOAD_RM16(modrm); } else { - UINT32 ea = GetEA(modrm); - value = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + value = READ16(cpustate,ea); } - PUSH16(value); - CYCLES(CYCLES_PUSH_RM); + PUSH16(cpustate,value); + CYCLES(cpustate,CYCLES_PUSH_RM); } break; case 7: - I386OP(invalid)(); + I386OP(invalid)(cpustate); break; default: fatalerror("i386: groupFF_16 /%d unimplemented", (modrm >> 3) & 0x7); @@ -2777,10 +2777,10 @@ static void I386OP(groupFF_16)(void) // Opcode 0xff } } -static void I386OP(group0F00_16)(void) // Opcode 0x0f 00 +static void I386OP(group0F00_16)(i386_state *cpustate) // Opcode 0x0f 00 { UINT32 address, ea; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); switch( (modrm >> 3) & 0x7 ) { @@ -2789,17 +2789,17 @@ static void I386OP(group0F00_16)(void) // Opcode 0x0f 00 { if( modrm >= 0xc0 ) { address = LOAD_RM16(modrm); - ea = i386_translate( CS, address ); - CYCLES(CYCLES_LLDT_REG); + ea = i386_translate(cpustate, CS, address ); + CYCLES(cpustate,CYCLES_LLDT_REG); } else { - ea = GetEA(modrm); - CYCLES(CYCLES_LLDT_MEM); + ea = GetEA(cpustate,modrm); + CYCLES(cpustate,CYCLES_LLDT_MEM); } - I.ldtr.segment = READ16(ea); + cpustate->ldtr.segment = READ16(cpustate,ea); } else { - i386_trap(6, 0); + i386_trap(cpustate,6, 0); } break; @@ -2808,17 +2808,17 @@ static void I386OP(group0F00_16)(void) // Opcode 0x0f 00 { if( modrm >= 0xc0 ) { address = LOAD_RM16(modrm); - ea = i386_translate( CS, address ); - CYCLES(CYCLES_LTR_REG); + ea = i386_translate(cpustate, CS, address ); + CYCLES(cpustate,CYCLES_LTR_REG); } else { - ea = GetEA(modrm); - CYCLES(CYCLES_LTR_MEM); + ea = GetEA(cpustate,modrm); + CYCLES(cpustate,CYCLES_LTR_MEM); } - I.task.segment = READ16(ea); + cpustate->task.segment = READ16(cpustate,ea); } else { - i386_trap(6, 0); + i386_trap(cpustate,6, 0); } break; @@ -2828,9 +2828,9 @@ static void I386OP(group0F00_16)(void) // Opcode 0x0f 00 } } -static void I386OP(group0F01_16)(void) // Opcode 0x0f 01 +static void I386OP(group0F01_16)(i386_state *cpustate) // Opcode 0x0f 01 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT16 address; UINT32 ea; @@ -2840,13 +2840,13 @@ static void I386OP(group0F01_16)(void) // Opcode 0x0f 01 { if( modrm >= 0xc0 ) { address = LOAD_RM16(modrm); - ea = i386_translate( CS, address ); + ea = i386_translate(cpustate, CS, address ); } else { - ea = GetEA(modrm); + ea = GetEA(cpustate,modrm); } - WRITE16(ea, I.gdtr.limit); - WRITE32(ea + 2, I.gdtr.base & 0xffffff); - CYCLES(CYCLES_SGDT); + WRITE16(cpustate,ea, cpustate->gdtr.limit); + WRITE32(cpustate,ea + 2, cpustate->gdtr.base & 0xffffff); + CYCLES(cpustate,CYCLES_SGDT); break; } case 1: /* SIDT */ @@ -2854,52 +2854,52 @@ static void I386OP(group0F01_16)(void) // Opcode 0x0f 01 if (modrm >= 0xc0) { address = LOAD_RM16(modrm); - ea = i386_translate( CS, address ); + ea = i386_translate(cpustate, CS, address ); } else { - ea = GetEA(modrm); + ea = GetEA(cpustate,modrm); } - WRITE16(ea, I.idtr.limit); - WRITE32(ea + 2, I.idtr.base & 0xffffff); - CYCLES(CYCLES_SIDT); + WRITE16(cpustate,ea, cpustate->idtr.limit); + WRITE32(cpustate,ea + 2, cpustate->idtr.base & 0xffffff); + CYCLES(cpustate,CYCLES_SIDT); break; } case 2: /* LGDT */ { if( modrm >= 0xc0 ) { address = LOAD_RM16(modrm); - ea = i386_translate( CS, address ); + ea = i386_translate(cpustate, CS, address ); } else { - ea = GetEA(modrm); + ea = GetEA(cpustate,modrm); } - I.gdtr.limit = READ16(ea); - I.gdtr.base = READ32(ea + 2) & 0xffffff; - CYCLES(CYCLES_LGDT); + cpustate->gdtr.limit = READ16(cpustate,ea); + cpustate->gdtr.base = READ32(cpustate,ea + 2) & 0xffffff; + CYCLES(cpustate,CYCLES_LGDT); break; } case 3: /* LIDT */ { if( modrm >= 0xc0 ) { address = LOAD_RM16(modrm); - ea = i386_translate( CS, address ); + ea = i386_translate(cpustate, CS, address ); } else { - ea = GetEA(modrm); + ea = GetEA(cpustate,modrm); } - I.idtr.limit = READ16(ea); - I.idtr.base = READ32(ea + 2) & 0xffffff; - CYCLES(CYCLES_LIDT); + cpustate->idtr.limit = READ16(cpustate,ea); + cpustate->idtr.base = READ32(cpustate,ea + 2) & 0xffffff; + CYCLES(cpustate,CYCLES_LIDT); break; } case 4: /* SMSW */ { if( modrm >= 0xc0 ) { - STORE_RM16(modrm, I.cr[0]); - CYCLES(CYCLES_SMSW_REG); + STORE_RM16(modrm, cpustate->cr[0]); + CYCLES(cpustate,CYCLES_SMSW_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE16(ea, I.cr[0]); - CYCLES(CYCLES_SMSW_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE16(cpustate,ea, cpustate->cr[0]); + CYCLES(cpustate,CYCLES_SMSW_MEM); } break; } @@ -2909,134 +2909,134 @@ static void I386OP(group0F01_16)(void) // Opcode 0x0f 01 UINT8 b; if( modrm >= 0xc0 ) { b = LOAD_RM8(modrm); - CYCLES(CYCLES_LMSW_REG); + CYCLES(cpustate,CYCLES_LMSW_REG); } else { - ea = GetEA(modrm); - CYCLES(CYCLES_LMSW_MEM); - b = READ8(ea); + ea = GetEA(cpustate,modrm); + CYCLES(cpustate,CYCLES_LMSW_MEM); + b = READ8(cpustate,ea); } - I.cr[0] &= ~0x03; - I.cr[0] |= b & 0x03; + cpustate->cr[0] &= ~0x03; + cpustate->cr[0] |= b & 0x03; break; } default: - fatalerror("i386: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, I.eip - 2); + fatalerror("i386: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, cpustate->eip - 2); break; } } -static void I386OP(group0FBA_16)(void) // Opcode 0x0f ba +static void I386OP(group0FBA_16)(i386_state *cpustate) // Opcode 0x0f ba { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); switch( (modrm >> 3) & 0x7 ) { case 4: /* BT Rm16, i8 */ if( modrm >= 0xc0 ) { UINT16 dst = LOAD_RM16(modrm); - UINT8 bit = FETCH(); + UINT8 bit = FETCH(cpustate); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; - CYCLES(CYCLES_BT_IMM_REG); + CYCLES(cpustate,CYCLES_BT_IMM_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); - UINT8 bit = FETCH(); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); + UINT8 bit = FETCH(cpustate); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; - CYCLES(CYCLES_BT_IMM_MEM); + CYCLES(cpustate,CYCLES_BT_IMM_MEM); } break; case 5: /* BTS Rm16, i8 */ if( modrm >= 0xc0 ) { UINT16 dst = LOAD_RM16(modrm); - UINT8 bit = FETCH(); + UINT8 bit = FETCH(cpustate); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst |= (1 << bit); STORE_RM16(modrm, dst); - CYCLES(CYCLES_BTS_IMM_REG); + CYCLES(cpustate,CYCLES_BTS_IMM_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); - UINT8 bit = FETCH(); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); + UINT8 bit = FETCH(cpustate); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst |= (1 << bit); - WRITE16(ea, dst); - CYCLES(CYCLES_BTS_IMM_MEM); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_BTS_IMM_MEM); } break; case 6: /* BTR Rm16, i8 */ if( modrm >= 0xc0 ) { UINT16 dst = LOAD_RM16(modrm); - UINT8 bit = FETCH(); + UINT8 bit = FETCH(cpustate); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst &= ~(1 << bit); STORE_RM16(modrm, dst); - CYCLES(CYCLES_BTR_IMM_REG); + CYCLES(cpustate,CYCLES_BTR_IMM_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); - UINT8 bit = FETCH(); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); + UINT8 bit = FETCH(cpustate); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst &= ~(1 << bit); - WRITE16(ea, dst); - CYCLES(CYCLES_BTR_IMM_MEM); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_BTR_IMM_MEM); } break; case 7: /* BTC Rm16, i8 */ if( modrm >= 0xc0 ) { UINT16 dst = LOAD_RM16(modrm); - UINT8 bit = FETCH(); + UINT8 bit = FETCH(cpustate); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst ^= (1 << bit); STORE_RM16(modrm, dst); - CYCLES(CYCLES_BTC_IMM_REG); + CYCLES(cpustate,CYCLES_BTC_IMM_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); - UINT8 bit = FETCH(); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); + UINT8 bit = FETCH(cpustate); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst ^= (1 << bit); - WRITE16(ea, dst); - CYCLES(CYCLES_BTC_IMM_MEM); + WRITE16(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_BTC_IMM_MEM); } break; default: @@ -3045,12 +3045,12 @@ static void I386OP(group0FBA_16)(void) // Opcode 0x0f ba } } -static void I386OP(bound_r16_m16_m16)(void) // Opcode 0x62 +static void I386OP(bound_r16_m16_m16)(i386_state *cpustate) // Opcode 0x62 { UINT8 modrm; INT16 val, low, high; - modrm = FETCH(); + modrm = FETCH(cpustate); if (modrm >= 0xc0) { @@ -3058,99 +3058,99 @@ static void I386OP(bound_r16_m16_m16)(void) // Opcode 0x62 } else { - UINT32 ea = GetEA(modrm); - low = READ16(ea + 0); - high = READ16(ea + 2); + UINT32 ea = GetEA(cpustate,modrm); + low = READ16(cpustate,ea + 0); + high = READ16(cpustate,ea + 2); } val = LOAD_REG16(modrm); if ((val < low) || (val > high)) { - CYCLES(CYCLES_BOUND_OUT_RANGE); - i386_trap(5, 0); + CYCLES(cpustate,CYCLES_BOUND_OUT_RANGE); + i386_trap(cpustate,5, 0); } else { - CYCLES(CYCLES_BOUND_IN_RANGE); + CYCLES(cpustate,CYCLES_BOUND_IN_RANGE); } } -static void I386OP(retf16)(void) // Opcode 0xcb +static void I386OP(retf16)(i386_state *cpustate) // Opcode 0xcb { - I.eip = POP16(); - I.sreg[CS].selector = POP16(); - i386_load_segment_descriptor( CS ); - CHANGE_PC(I.eip); + cpustate->eip = POP16(cpustate); + cpustate->sreg[CS].selector = POP16(cpustate); + i386_load_segment_descriptor(cpustate, CS ); + CHANGE_PC(cpustate,cpustate->eip); - CYCLES(CYCLES_RET_INTERSEG); + CYCLES(cpustate,CYCLES_RET_INTERSEG); } -static void I386OP(retf_i16)(void) // Opcode 0xca +static void I386OP(retf_i16)(i386_state *cpustate) // Opcode 0xca { - UINT16 count = FETCH16(); + UINT16 count = FETCH16(cpustate); - I.eip = POP16(); - I.sreg[CS].selector = POP16(); - i386_load_segment_descriptor( CS ); - CHANGE_PC(I.eip); + cpustate->eip = POP16(cpustate); + cpustate->sreg[CS].selector = POP16(cpustate); + i386_load_segment_descriptor(cpustate, CS ); + CHANGE_PC(cpustate,cpustate->eip); REG16(SP) += count; - CYCLES(CYCLES_RET_IMM_INTERSEG); + CYCLES(cpustate,CYCLES_RET_IMM_INTERSEG); } -static void I386OP(xlat16)(void) // Opcode 0xd7 +static void I386OP(xlat16)(i386_state *cpustate) // Opcode 0xd7 { UINT32 ea; - if( I.segment_prefix ) { - ea = i386_translate( I.segment_override, REG16(BX) + REG8(AL) ); + if( cpustate->segment_prefix ) { + ea = i386_translate(cpustate, cpustate->segment_override, REG16(BX) + REG8(AL) ); } else { - ea = i386_translate( DS, REG16(BX) + REG8(AL) ); + ea = i386_translate(cpustate, DS, REG16(BX) + REG8(AL) ); } - REG8(AL) = READ8(ea); - CYCLES(CYCLES_XLAT); + REG8(AL) = READ8(cpustate,ea); + CYCLES(cpustate,CYCLES_XLAT); } -static void I386OP(load_far_pointer16)(int s) +static void I386OP(load_far_pointer16)(i386_state *cpustate, int s) { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { fatalerror("NYI"); } else { - UINT32 ea = GetEA(modrm); - STORE_REG16(modrm, READ16(ea + 0)); - I.sreg[s].selector = READ16(ea + 2); - i386_load_segment_descriptor( s ); + UINT32 ea = GetEA(cpustate,modrm); + STORE_REG16(modrm, READ16(cpustate,ea + 0)); + cpustate->sreg[s].selector = READ16(cpustate,ea + 2); + i386_load_segment_descriptor(cpustate, s ); } } -static void I386OP(lds16)(void) // Opcode 0xc5 +static void I386OP(lds16)(i386_state *cpustate) // Opcode 0xc5 { - I386OP(load_far_pointer16)(DS); - CYCLES(CYCLES_LDS); + I386OP(load_far_pointer16)(cpustate, DS); + CYCLES(cpustate,CYCLES_LDS); } -static void I386OP(lss16)(void) // Opcode 0x0f 0xb2 +static void I386OP(lss16)(i386_state *cpustate) // Opcode 0x0f 0xb2 { - I386OP(load_far_pointer16)(SS); - CYCLES(CYCLES_LSS); + I386OP(load_far_pointer16)(cpustate, SS); + CYCLES(cpustate,CYCLES_LSS); } -static void I386OP(les16)(void) // Opcode 0xc4 +static void I386OP(les16)(i386_state *cpustate) // Opcode 0xc4 { - I386OP(load_far_pointer16)(ES); - CYCLES(CYCLES_LES); + I386OP(load_far_pointer16)(cpustate, ES); + CYCLES(cpustate,CYCLES_LES); } -static void I386OP(lfs16)(void) // Opcode 0x0f 0xb4 +static void I386OP(lfs16)(i386_state *cpustate) // Opcode 0x0f 0xb4 { - I386OP(load_far_pointer16)(FS); - CYCLES(CYCLES_LFS); + I386OP(load_far_pointer16)(cpustate, FS); + CYCLES(cpustate,CYCLES_LFS); } -static void I386OP(lgs16)(void) // Opcode 0x0f 0xb5 +static void I386OP(lgs16)(i386_state *cpustate) // Opcode 0x0f 0xb5 { - I386OP(load_far_pointer16)(GS); - CYCLES(CYCLES_LGS); + I386OP(load_far_pointer16)(cpustate, GS); + CYCLES(cpustate,CYCLES_LGS); } diff --git a/src/emu/cpu/i386/i386op32.c b/src/emu/cpu/i386/i386op32.c index 821401c1f20..5fe2fee2d14 100644 --- a/src/emu/cpu/i386/i386op32.c +++ b/src/emu/cpu/i386/i386op32.c @@ -1,60 +1,60 @@ -static UINT32 I386OP(shift_rotate32)(UINT8 modrm, UINT32 value, UINT8 shift) +static UINT32 I386OP(shift_rotate32)(i386_state *cpustate, UINT8 modrm, UINT32 value, UINT8 shift) { UINT32 dst, src; dst = value; src = value; if( shift == 0 ) { - CYCLES_RM(modrm, 3, 7); + CYCLES_RM(cpustate,modrm, 3, 7); } else if( shift == 1 ) { switch( (modrm >> 3) & 0x7 ) { case 0: /* ROL rm32, 1 */ - I.CF = (src & 0x80000000) ? 1 : 0; - dst = (src << 1) + I.CF; - I.OF = ((src ^ dst) & 0x80000000) ? 1 : 0; - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + cpustate->CF = (src & 0x80000000) ? 1 : 0; + dst = (src << 1) + cpustate->CF; + cpustate->OF = ((src ^ dst) & 0x80000000) ? 1 : 0; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 1: /* ROR rm32, 1 */ - I.CF = (src & 0x1) ? 1 : 0; - dst = (I.CF << 31) | (src >> 1); - I.OF = ((src ^ dst) & 0x80000000) ? 1 : 0; - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + cpustate->CF = (src & 0x1) ? 1 : 0; + dst = (cpustate->CF << 31) | (src >> 1); + cpustate->OF = ((src ^ dst) & 0x80000000) ? 1 : 0; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 2: /* RCL rm32, 1 */ - dst = (src << 1) + I.CF; - I.CF = (src & 0x80000000) ? 1 : 0; - I.OF = ((src ^ dst) & 0x80000000) ? 1 : 0; - CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); + dst = (src << 1) + cpustate->CF; + cpustate->CF = (src & 0x80000000) ? 1 : 0; + cpustate->OF = ((src ^ dst) & 0x80000000) ? 1 : 0; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); break; case 3: /* RCR rm32, 1 */ - dst = (I.CF << 31) | (src >> 1); - I.CF = src & 0x1; - I.OF = ((src ^ dst) & 0x80000000) ? 1 : 0; - CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); + dst = (cpustate->CF << 31) | (src >> 1); + cpustate->CF = src & 0x1; + cpustate->OF = ((src ^ dst) & 0x80000000) ? 1 : 0; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); break; case 4: /* SHL/SAL rm32, 1 */ case 6: dst = src << 1; - I.CF = (src & 0x80000000) ? 1 : 0; - I.OF = (((I.CF << 31) ^ dst) & 0x80000000) ? 1 : 0; + cpustate->CF = (src & 0x80000000) ? 1 : 0; + cpustate->OF = (((cpustate->CF << 31) ^ dst) & 0x80000000) ? 1 : 0; SetSZPF32(dst); - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 5: /* SHR rm32, 1 */ dst = src >> 1; - I.CF = src & 0x1; - I.OF = (src & 0x80000000) ? 1 : 0; + cpustate->CF = src & 0x1; + cpustate->OF = (src & 0x80000000) ? 1 : 0; SetSZPF32(dst); - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 7: /* SAR rm32, 1 */ dst = (INT32)(src) >> 1; - I.CF = src & 0x1; - I.OF = 0; + cpustate->CF = src & 0x1; + cpustate->OF = 0; SetSZPF32(dst); - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; } @@ -65,47 +65,47 @@ static UINT32 I386OP(shift_rotate32)(UINT8 modrm, UINT32 value, UINT8 shift) case 0: /* ROL rm32, i8 */ dst = ((src & ((UINT32)0xffffffff >> shift)) << shift) | ((src & ((UINT32)0xffffffff << (32-shift))) >> (32-shift)); - I.CF = (src >> (32-shift)) & 0x1; - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + cpustate->CF = (src >> (32-shift)) & 0x1; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 1: /* ROR rm32, i8 */ dst = ((src & ((UINT32)0xffffffff << shift)) >> shift) | ((src & ((UINT32)0xffffffff >> (32-shift))) << (32-shift)); - I.CF = (src >> (shift-1)) & 0x1; - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + cpustate->CF = (src >> (shift-1)) & 0x1; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 2: /* RCL rm32, i8 */ dst = ((src & ((UINT32)0xffffffff >> shift)) << shift) | ((src & ((UINT32)0xffffffff << (33-shift))) >> (33-shift)) | - (I.CF << (shift-1)); - I.CF = (src >> (32-shift)) & 0x1; - CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); + (cpustate->CF << (shift-1)); + cpustate->CF = (src >> (32-shift)) & 0x1; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); break; case 3: /* RCR rm32, i8 */ dst = ((src & ((UINT32)0xffffffff << shift)) >> shift) | ((src & ((UINT32)0xffffffff >> (32-shift))) << (33-shift)) | - (I.CF << (32-shift)); - I.CF = (src >> (shift-1)) & 0x1; - CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); + (cpustate->CF << (32-shift)); + cpustate->CF = (src >> (shift-1)) & 0x1; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); break; case 4: /* SHL/SAL rm32, i8 */ case 6: dst = src << shift; - I.CF = (src & (1 << (32-shift))) ? 1 : 0; + cpustate->CF = (src & (1 << (32-shift))) ? 1 : 0; SetSZPF32(dst); - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 5: /* SHR rm32, i8 */ dst = src >> shift; - I.CF = (src & (1 << (shift-1))) ? 1 : 0; + cpustate->CF = (src & (1 << (shift-1))) ? 1 : 0; SetSZPF32(dst); - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 7: /* SAR rm32, i8 */ dst = (INT32)src >> shift; - I.CF = (src & (1 << (shift-1))) ? 1 : 0; + cpustate->CF = (src & (1 << (shift-1))) ? 1 : 0; SetSZPF32(dst); - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; } @@ -115,506 +115,506 @@ static UINT32 I386OP(shift_rotate32)(UINT8 modrm, UINT32 value, UINT8 shift) -static void I386OP(adc_rm32_r32)(void) // Opcode 0x11 +static void I386OP(adc_rm32_r32)(i386_state *cpustate) // Opcode 0x11 { UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG32(modrm); dst = LOAD_RM32(modrm); - src = ADD32(src, I.CF); - dst = ADD32(dst, src); + src = ADD32(cpustate,src, cpustate->CF); + dst = ADD32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG32(modrm); - dst = READ32(ea); - src = ADD32(src, I.CF); - dst = ADD32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + dst = READ32(cpustate,ea); + src = ADD32(cpustate,src, cpustate->CF); + dst = ADD32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(adc_r32_rm32)(void) // Opcode 0x13 +static void I386OP(adc_r32_rm32)(i386_state *cpustate) // Opcode 0x13 { UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM32(modrm); dst = LOAD_REG32(modrm); - src = ADD32(src, I.CF); - dst = ADD32(dst, src); + src = ADD32(cpustate,src, cpustate->CF); + dst = ADD32(cpustate,dst, src); STORE_REG32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ32(cpustate,ea); dst = LOAD_REG32(modrm); - src = ADD32(src, I.CF); - dst = ADD32(dst, src); + src = ADD32(cpustate,src, cpustate->CF); + dst = ADD32(cpustate,dst, src); STORE_REG32(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(adc_eax_i32)(void) // Opcode 0x15 +static void I386OP(adc_eax_i32)(i386_state *cpustate) // Opcode 0x15 { UINT32 src, dst; - src = FETCH32(); + src = FETCH32(cpustate); dst = REG32(EAX); - src = ADD32(src, I.CF); - dst = ADD32(dst, src); + src = ADD32(cpustate,src, cpustate->CF); + dst = ADD32(cpustate,dst, src); REG32(EAX) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(add_rm32_r32)(void) // Opcode 0x01 +static void I386OP(add_rm32_r32)(i386_state *cpustate) // Opcode 0x01 { UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG32(modrm); dst = LOAD_RM32(modrm); - dst = ADD32(dst, src); + dst = ADD32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG32(modrm); - dst = READ32(ea); - dst = ADD32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + dst = READ32(cpustate,ea); + dst = ADD32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(add_r32_rm32)(void) // Opcode 0x03 +static void I386OP(add_r32_rm32)(i386_state *cpustate) // Opcode 0x03 { UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM32(modrm); dst = LOAD_REG32(modrm); - dst = ADD32(dst, src); + dst = ADD32(cpustate,dst, src); STORE_REG32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ32(cpustate,ea); dst = LOAD_REG32(modrm); - dst = ADD32(dst, src); + dst = ADD32(cpustate,dst, src); STORE_REG32(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(add_eax_i32)(void) // Opcode 0x05 +static void I386OP(add_eax_i32)(i386_state *cpustate) // Opcode 0x05 { UINT32 src, dst; - src = FETCH32(); + src = FETCH32(cpustate); dst = REG32(EAX); - dst = ADD32(dst, src); + dst = ADD32(cpustate,dst, src); REG32(EAX) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(and_rm32_r32)(void) // Opcode 0x21 +static void I386OP(and_rm32_r32)(i386_state *cpustate) // Opcode 0x21 { UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG32(modrm); dst = LOAD_RM32(modrm); - dst = AND32(dst, src); + dst = AND32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG32(modrm); - dst = READ32(ea); - dst = AND32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + dst = READ32(cpustate,ea); + dst = AND32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(and_r32_rm32)(void) // Opcode 0x23 +static void I386OP(and_r32_rm32)(i386_state *cpustate) // Opcode 0x23 { UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM32(modrm); dst = LOAD_REG32(modrm); - dst = AND32(dst, src); + dst = AND32(cpustate,dst, src); STORE_REG32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ32(cpustate,ea); dst = LOAD_REG32(modrm); - dst = AND32(dst, src); + dst = AND32(cpustate,dst, src); STORE_REG32(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(and_eax_i32)(void) // Opcode 0x25 +static void I386OP(and_eax_i32)(i386_state *cpustate) // Opcode 0x25 { UINT32 src, dst; - src = FETCH32(); + src = FETCH32(cpustate); dst = REG32(EAX); - dst = AND32(dst, src); + dst = AND32(cpustate,dst, src); REG32(EAX) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(bsf_r32_rm32)(void) // Opcode 0x0f bc +static void I386OP(bsf_r32_rm32)(i386_state *cpustate) // Opcode 0x0f bc { UINT32 src, dst, temp; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM32(modrm); } else { - UINT32 ea = GetEA(modrm); - src = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ32(cpustate,ea); } dst = 0; if( src == 0 ) { - I.ZF = 1; + cpustate->ZF = 1; } else { - I.ZF = 0; + cpustate->ZF = 0; temp = 0; while( (src & (1 << temp)) == 0 ) { temp++; dst = temp; - CYCLES(CYCLES_BSF); + CYCLES(cpustate,CYCLES_BSF); } } - CYCLES(CYCLES_BSF_BASE); + CYCLES(cpustate,CYCLES_BSF_BASE); STORE_REG32(modrm, dst); } -static void I386OP(bsr_r32_rm32)(void) // Opcode 0x0f bd +static void I386OP(bsr_r32_rm32)(i386_state *cpustate) // Opcode 0x0f bd { UINT32 src, dst, temp; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM32(modrm); } else { - UINT32 ea = GetEA(modrm); - src = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ32(cpustate,ea); } dst = 0; if( src == 0 ) { - I.ZF = 1; + cpustate->ZF = 1; } else { - I.ZF = 0; + cpustate->ZF = 0; dst = temp = 31; while( (src & (1 << temp)) == 0 ) { temp--; dst = temp; - CYCLES(CYCLES_BSR); + CYCLES(cpustate,CYCLES_BSR); } } - CYCLES(CYCLES_BSR_BASE); + CYCLES(cpustate,CYCLES_BSR_BASE); STORE_REG32(modrm, dst); } -static void I386OP(bt_rm32_r32)(void) // Opcode 0x0f a3 +static void I386OP(bt_rm32_r32)(i386_state *cpustate) // Opcode 0x0f a3 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); UINT32 bit = LOAD_REG32(modrm); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; - CYCLES(CYCLES_BT_REG_REG); + CYCLES(cpustate,CYCLES_BT_REG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); UINT32 bit = LOAD_REG32(modrm); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; - CYCLES(CYCLES_BT_REG_MEM); + CYCLES(cpustate,CYCLES_BT_REG_MEM); } } -static void I386OP(btc_rm32_r32)(void) // Opcode 0x0f bb +static void I386OP(btc_rm32_r32)(i386_state *cpustate) // Opcode 0x0f bb { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); UINT32 bit = LOAD_REG32(modrm); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst ^= (1 << bit); STORE_RM32(modrm, dst); - CYCLES(CYCLES_BTC_REG_REG); + CYCLES(cpustate,CYCLES_BTC_REG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); UINT32 bit = LOAD_REG32(modrm); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst ^= (1 << bit); - WRITE32(ea, dst); - CYCLES(CYCLES_BTC_REG_MEM); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_BTC_REG_MEM); } } -static void I386OP(btr_rm32_r32)(void) // Opcode 0x0f b3 +static void I386OP(btr_rm32_r32)(i386_state *cpustate) // Opcode 0x0f b3 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); UINT32 bit = LOAD_REG32(modrm); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst &= ~(1 << bit); STORE_RM32(modrm, dst); - CYCLES(CYCLES_BTR_REG_REG); + CYCLES(cpustate,CYCLES_BTR_REG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); UINT32 bit = LOAD_REG32(modrm); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst &= ~(1 << bit); - WRITE32(ea, dst); - CYCLES(CYCLES_BTR_REG_MEM); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_BTR_REG_MEM); } } -static void I386OP(bts_rm32_r32)(void) // Opcode 0x0f ab +static void I386OP(bts_rm32_r32)(i386_state *cpustate) // Opcode 0x0f ab { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); UINT32 bit = LOAD_REG32(modrm); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst |= (1 << bit); STORE_RM32(modrm, dst); - CYCLES(CYCLES_BTS_REG_REG); + CYCLES(cpustate,CYCLES_BTS_REG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); UINT32 bit = LOAD_REG32(modrm); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst |= (1 << bit); - WRITE32(ea, dst); - CYCLES(CYCLES_BTS_REG_MEM); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_BTS_REG_MEM); } } -static void I386OP(call_abs32)(void) // Opcode 0x9a +static void I386OP(call_abs32)(i386_state *cpustate) // Opcode 0x9a { - UINT32 offset = FETCH32(); - UINT16 ptr = FETCH16(); + UINT32 offset = FETCH32(cpustate); + UINT16 ptr = FETCH16(cpustate); if( PROTECTED_MODE ) { /* TODO */ fatalerror("i386: call_abs32 in protected mode unimplemented"); } else { - PUSH32( I.sreg[CS].selector ); - PUSH32( I.eip ); - I.sreg[CS].selector = ptr; - I.eip = offset; - i386_load_segment_descriptor(CS); + PUSH32(cpustate, cpustate->sreg[CS].selector ); + PUSH32(cpustate, cpustate->eip ); + cpustate->sreg[CS].selector = ptr; + cpustate->eip = offset; + i386_load_segment_descriptor(cpustate,CS); } - CYCLES(CYCLES_CALL_INTERSEG); - CHANGE_PC(I.eip); + CYCLES(cpustate,CYCLES_CALL_INTERSEG); + CHANGE_PC(cpustate,cpustate->eip); } -static void I386OP(call_rel32)(void) // Opcode 0xe8 +static void I386OP(call_rel32)(i386_state *cpustate) // Opcode 0xe8 { - INT32 disp = FETCH32(); + INT32 disp = FETCH32(cpustate); - PUSH32( I.eip ); - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_CALL); /* TODO: Timing = 7 + m */ + PUSH32(cpustate, cpustate->eip ); + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_CALL); /* TODO: Timing = 7 + m */ } -static void I386OP(cdq)(void) // Opcode 0x99 +static void I386OP(cdq)(i386_state *cpustate) // Opcode 0x99 { if( REG32(EAX) & 0x80000000 ) { REG32(EDX) = 0xffffffff; } else { REG32(EDX) = 0x00000000; } - CYCLES(CYCLES_CWD); + CYCLES(cpustate,CYCLES_CWD); } -static void I386OP(cmp_rm32_r32)(void) // Opcode 0x39 +static void I386OP(cmp_rm32_r32)(i386_state *cpustate) // Opcode 0x39 { UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG32(modrm); dst = LOAD_RM32(modrm); - SUB32(dst, src); - CYCLES(CYCLES_CMP_REG_REG); + SUB32(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG32(modrm); - dst = READ32(ea); - SUB32(dst, src); - CYCLES(CYCLES_CMP_REG_MEM); + dst = READ32(cpustate,ea); + SUB32(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_MEM); } } -static void I386OP(cmp_r32_rm32)(void) // Opcode 0x3b +static void I386OP(cmp_r32_rm32)(i386_state *cpustate) // Opcode 0x3b { UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM32(modrm); dst = LOAD_REG32(modrm); - SUB32(dst, src); - CYCLES(CYCLES_CMP_REG_REG); + SUB32(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ32(cpustate,ea); dst = LOAD_REG32(modrm); - SUB32(dst, src); - CYCLES(CYCLES_CMP_MEM_REG); + SUB32(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_MEM_REG); } } -static void I386OP(cmp_eax_i32)(void) // Opcode 0x3d +static void I386OP(cmp_eax_i32)(i386_state *cpustate) // Opcode 0x3d { UINT32 src, dst; - src = FETCH32(); + src = FETCH32(cpustate); dst = REG32(EAX); - SUB32(dst, src); - CYCLES(CYCLES_CMP_IMM_ACC); + SUB32(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_IMM_ACC); } -static void I386OP(cmpsd)(void) // Opcode 0xa7 +static void I386OP(cmpsd)(i386_state *cpustate) // Opcode 0xa7 { UINT32 eas, ead, src, dst; - if( I.segment_prefix ) { - eas = i386_translate( I.segment_override, I.address_size ? REG32(ESI) : REG16(SI) ); + if( cpustate->segment_prefix ) { + eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } else { - eas = i386_translate( DS, I.address_size ? REG32(ESI) : REG16(SI) ); + eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } - ead = i386_translate( ES, I.address_size ? REG32(EDI) : REG16(DI) ); - src = READ32(eas); - dst = READ32(ead); - SUB32(dst, src); - BUMP_SI(4); - BUMP_DI(4); - CYCLES(CYCLES_CMPS); + ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI) ); + src = READ32(cpustate,eas); + dst = READ32(cpustate,ead); + SUB32(cpustate,dst, src); + BUMP_SI(cpustate,4); + BUMP_DI(cpustate,4); + CYCLES(cpustate,CYCLES_CMPS); } -static void I386OP(cwde)(void) // Opcode 0x98 +static void I386OP(cwde)(i386_state *cpustate) // Opcode 0x98 { REG32(EAX) = (INT32)((INT16)REG16(AX)); - CYCLES(CYCLES_CBW); + CYCLES(cpustate,CYCLES_CBW); } -static void I386OP(dec_eax)(void) // Opcode 0x48 +static void I386OP(dec_eax)(i386_state *cpustate) // Opcode 0x48 { - REG32(EAX) = DEC32( REG32(EAX) ); - CYCLES(CYCLES_DEC_REG); + REG32(EAX) = DEC32(cpustate, REG32(EAX) ); + CYCLES(cpustate,CYCLES_DEC_REG); } -static void I386OP(dec_ecx)(void) // Opcode 0x49 +static void I386OP(dec_ecx)(i386_state *cpustate) // Opcode 0x49 { - REG32(ECX) = DEC32( REG32(ECX) ); - CYCLES(CYCLES_DEC_REG); + REG32(ECX) = DEC32(cpustate, REG32(ECX) ); + CYCLES(cpustate,CYCLES_DEC_REG); } -static void I386OP(dec_edx)(void) // Opcode 0x4a +static void I386OP(dec_edx)(i386_state *cpustate) // Opcode 0x4a { - REG32(EDX) = DEC32( REG32(EDX) ); - CYCLES(CYCLES_DEC_REG); + REG32(EDX) = DEC32(cpustate, REG32(EDX) ); + CYCLES(cpustate,CYCLES_DEC_REG); } -static void I386OP(dec_ebx)(void) // Opcode 0x4b +static void I386OP(dec_ebx)(i386_state *cpustate) // Opcode 0x4b { - REG32(EBX) = DEC32( REG32(EBX) ); - CYCLES(CYCLES_DEC_REG); + REG32(EBX) = DEC32(cpustate, REG32(EBX) ); + CYCLES(cpustate,CYCLES_DEC_REG); } -static void I386OP(dec_esp)(void) // Opcode 0x4c +static void I386OP(dec_esp)(i386_state *cpustate) // Opcode 0x4c { - REG32(ESP) = DEC32( REG32(ESP) ); - CYCLES(CYCLES_DEC_REG); + REG32(ESP) = DEC32(cpustate, REG32(ESP) ); + CYCLES(cpustate,CYCLES_DEC_REG); } -static void I386OP(dec_ebp)(void) // Opcode 0x4d +static void I386OP(dec_ebp)(i386_state *cpustate) // Opcode 0x4d { - REG32(EBP) = DEC32( REG32(EBP) ); - CYCLES(CYCLES_DEC_REG); + REG32(EBP) = DEC32(cpustate, REG32(EBP) ); + CYCLES(cpustate,CYCLES_DEC_REG); } -static void I386OP(dec_esi)(void) // Opcode 0x4e +static void I386OP(dec_esi)(i386_state *cpustate) // Opcode 0x4e { - REG32(ESI) = DEC32( REG32(ESI) ); - CYCLES(CYCLES_DEC_REG); + REG32(ESI) = DEC32(cpustate, REG32(ESI) ); + CYCLES(cpustate,CYCLES_DEC_REG); } -static void I386OP(dec_edi)(void) // Opcode 0x4f +static void I386OP(dec_edi)(i386_state *cpustate) // Opcode 0x4f { - REG32(EDI) = DEC32( REG32(EDI) ); - CYCLES(CYCLES_DEC_REG); + REG32(EDI) = DEC32(cpustate, REG32(EDI) ); + CYCLES(cpustate,CYCLES_DEC_REG); } -static void I386OP(imul_r32_rm32)(void) // Opcode 0x0f af +static void I386OP(imul_r32_rm32)(i386_state *cpustate) // Opcode 0x0f af { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); INT64 result; INT64 src, dst; if( modrm >= 0xc0 ) { src = (INT64)(INT32)LOAD_RM32(modrm); - CYCLES(CYCLES_IMUL32_REG_REG); /* TODO: Correct multiply timing */ + CYCLES(cpustate,CYCLES_IMUL32_REG_REG); /* TODO: Correct multiply timing */ } else { - UINT32 ea = GetEA(modrm); - src = (INT64)(INT32)READ32(ea); - CYCLES(CYCLES_IMUL32_REG_REG); /* TODO: Correct multiply timing */ + UINT32 ea = GetEA(cpustate,modrm); + src = (INT64)(INT32)READ32(cpustate,ea); + CYCLES(cpustate,CYCLES_IMUL32_REG_REG); /* TODO: Correct multiply timing */ } dst = (INT64)(INT32)LOAD_REG32(modrm); @@ -622,1074 +622,1074 @@ static void I386OP(imul_r32_rm32)(void) // Opcode 0x0f af STORE_REG32(modrm, (UINT32)result); - I.CF = I.OF = !(result == (INT64)(INT32)result); + cpustate->CF = cpustate->OF = !(result == (INT64)(INT32)result); } -static void I386OP(imul_r32_rm32_i32)(void) // Opcode 0x69 +static void I386OP(imul_r32_rm32_i32)(i386_state *cpustate) // Opcode 0x69 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); INT64 result; INT64 src, dst; if( modrm >= 0xc0 ) { dst = (INT64)(INT32)LOAD_RM32(modrm); - CYCLES(CYCLES_IMUL32_REG_IMM_REG); /* TODO: Correct multiply timing */ + CYCLES(cpustate,CYCLES_IMUL32_REG_IMM_REG); /* TODO: Correct multiply timing */ } else { - UINT32 ea = GetEA(modrm); - dst = (INT64)(INT32)READ32(ea); - CYCLES(CYCLES_IMUL32_MEM_IMM_REG); /* TODO: Correct multiply timing */ + UINT32 ea = GetEA(cpustate,modrm); + dst = (INT64)(INT32)READ32(cpustate,ea); + CYCLES(cpustate,CYCLES_IMUL32_MEM_IMM_REG); /* TODO: Correct multiply timing */ } - src = (INT64)(INT32)FETCH32(); + src = (INT64)(INT32)FETCH32(cpustate); result = src * dst; STORE_REG32(modrm, (UINT32)result); - I.CF = I.OF = !(result == (INT64)(INT32)result); + cpustate->CF = cpustate->OF = !(result == (INT64)(INT32)result); } -static void I386OP(imul_r32_rm32_i8)(void) // Opcode 0x6b +static void I386OP(imul_r32_rm32_i8)(i386_state *cpustate) // Opcode 0x6b { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); INT64 result; INT64 src, dst; if( modrm >= 0xc0 ) { dst = (INT64)(INT32)LOAD_RM32(modrm); - CYCLES(CYCLES_IMUL32_REG_IMM_REG); /* TODO: Correct multiply timing */ + CYCLES(cpustate,CYCLES_IMUL32_REG_IMM_REG); /* TODO: Correct multiply timing */ } else { - UINT32 ea = GetEA(modrm); - dst = (INT64)(INT32)READ32(ea); - CYCLES(CYCLES_IMUL32_MEM_IMM_REG); /* TODO: Correct multiply timing */ + UINT32 ea = GetEA(cpustate,modrm); + dst = (INT64)(INT32)READ32(cpustate,ea); + CYCLES(cpustate,CYCLES_IMUL32_MEM_IMM_REG); /* TODO: Correct multiply timing */ } - src = (INT64)(INT8)FETCH(); + src = (INT64)(INT8)FETCH(cpustate); result = src * dst; STORE_REG32(modrm, (UINT32)result); - I.CF = I.OF = !(result == (INT64)(INT32)result); + cpustate->CF = cpustate->OF = !(result == (INT64)(INT32)result); } -static void I386OP(in_eax_i8)(void) // Opcode 0xe5 +static void I386OP(in_eax_i8)(i386_state *cpustate) // Opcode 0xe5 { - UINT16 port = FETCH(); + UINT16 port = FETCH(cpustate); UINT32 data = READPORT32(port); REG32(EAX) = data; - CYCLES(CYCLES_IN_VAR); + CYCLES(cpustate,CYCLES_IN_VAR); } -static void I386OP(in_eax_dx)(void) // Opcode 0xed +static void I386OP(in_eax_dx)(i386_state *cpustate) // Opcode 0xed { UINT16 port = REG16(DX); UINT32 data = READPORT32(port); REG32(EAX) = data; - CYCLES(CYCLES_IN); + CYCLES(cpustate,CYCLES_IN); } -static void I386OP(inc_eax)(void) // Opcode 0x40 +static void I386OP(inc_eax)(i386_state *cpustate) // Opcode 0x40 { - REG32(EAX) = INC32( REG32(EAX) ); - CYCLES(CYCLES_INC_REG); + REG32(EAX) = INC32(cpustate, REG32(EAX) ); + CYCLES(cpustate,CYCLES_INC_REG); } -static void I386OP(inc_ecx)(void) // Opcode 0x41 +static void I386OP(inc_ecx)(i386_state *cpustate) // Opcode 0x41 { - REG32(ECX) = INC32( REG32(ECX) ); - CYCLES(CYCLES_INC_REG); + REG32(ECX) = INC32(cpustate, REG32(ECX) ); + CYCLES(cpustate,CYCLES_INC_REG); } -static void I386OP(inc_edx)(void) // Opcode 0x42 +static void I386OP(inc_edx)(i386_state *cpustate) // Opcode 0x42 { - REG32(EDX) = INC32( REG32(EDX) ); - CYCLES(CYCLES_INC_REG); + REG32(EDX) = INC32(cpustate, REG32(EDX) ); + CYCLES(cpustate,CYCLES_INC_REG); } -static void I386OP(inc_ebx)(void) // Opcode 0x43 +static void I386OP(inc_ebx)(i386_state *cpustate) // Opcode 0x43 { - REG32(EBX) = INC32( REG32(EBX) ); - CYCLES(CYCLES_INC_REG); + REG32(EBX) = INC32(cpustate, REG32(EBX) ); + CYCLES(cpustate,CYCLES_INC_REG); } -static void I386OP(inc_esp)(void) // Opcode 0x44 +static void I386OP(inc_esp)(i386_state *cpustate) // Opcode 0x44 { - REG32(ESP) = INC32( REG32(ESP) ); - CYCLES(CYCLES_INC_REG); + REG32(ESP) = INC32(cpustate, REG32(ESP) ); + CYCLES(cpustate,CYCLES_INC_REG); } -static void I386OP(inc_ebp)(void) // Opcode 0x45 +static void I386OP(inc_ebp)(i386_state *cpustate) // Opcode 0x45 { - REG32(EBP) = INC32( REG32(EBP) ); - CYCLES(CYCLES_INC_REG); + REG32(EBP) = INC32(cpustate, REG32(EBP) ); + CYCLES(cpustate,CYCLES_INC_REG); } -static void I386OP(inc_esi)(void) // Opcode 0x46 +static void I386OP(inc_esi)(i386_state *cpustate) // Opcode 0x46 { - REG32(ESI) = INC32( REG32(ESI) ); - CYCLES(CYCLES_INC_REG); + REG32(ESI) = INC32(cpustate, REG32(ESI) ); + CYCLES(cpustate,CYCLES_INC_REG); } -static void I386OP(inc_edi)(void) // Opcode 0x47 +static void I386OP(inc_edi)(i386_state *cpustate) // Opcode 0x47 { - REG32(EDI) = INC32( REG32(EDI) ); - CYCLES(CYCLES_INC_REG); + REG32(EDI) = INC32(cpustate, REG32(EDI) ); + CYCLES(cpustate,CYCLES_INC_REG); } -static void I386OP(iret32)(void) // Opcode 0xcf +static void I386OP(iret32)(i386_state *cpustate) // Opcode 0xcf { if( PROTECTED_MODE ) { /* TODO: Virtual 8086-mode */ /* TODO: Nested task */ /* TODO: #SS(0) exception */ /* TODO: All the protection-related stuff... */ - I.eip = POP32(); - I.sreg[CS].selector = POP32() & 0xffff; - set_flags( POP32() ); - i386_load_segment_descriptor(CS); - CHANGE_PC(I.eip); + cpustate->eip = POP32(cpustate); + cpustate->sreg[CS].selector = POP32(cpustate) & 0xffff; + set_flags(cpustate, POP32(cpustate) ); + i386_load_segment_descriptor(cpustate,CS); + CHANGE_PC(cpustate,cpustate->eip); } else { /* TODO: #SS(0) exception */ /* TODO: #GP(0) exception */ - I.eip = POP32(); - I.sreg[CS].selector = POP32() & 0xffff; - set_flags( POP32() ); - i386_load_segment_descriptor(CS); - CHANGE_PC(I.eip); + cpustate->eip = POP32(cpustate); + cpustate->sreg[CS].selector = POP32(cpustate) & 0xffff; + set_flags(cpustate, POP32(cpustate) ); + i386_load_segment_descriptor(cpustate,CS); + CHANGE_PC(cpustate,cpustate->eip); } - CYCLES(CYCLES_IRET); + CYCLES(cpustate,CYCLES_IRET); } -static void I386OP(ja_rel32)(void) // Opcode 0x0f 87 +static void I386OP(ja_rel32)(i386_state *cpustate) // Opcode 0x0f 87 { - INT32 disp = FETCH32(); - if( I.CF == 0 && I.ZF == 0 ) { - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + INT32 disp = FETCH32(cpustate); + if( cpustate->CF == 0 && cpustate->ZF == 0 ) { + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jbe_rel32)(void) // Opcode 0x0f 86 +static void I386OP(jbe_rel32)(i386_state *cpustate) // Opcode 0x0f 86 { - INT32 disp = FETCH32(); - if( I.CF != 0 || I.ZF != 0 ) { - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + INT32 disp = FETCH32(cpustate); + if( cpustate->CF != 0 || cpustate->ZF != 0 ) { + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jc_rel32)(void) // Opcode 0x0f 82 +static void I386OP(jc_rel32)(i386_state *cpustate) // Opcode 0x0f 82 { - INT32 disp = FETCH32(); - if( I.CF != 0 ) { - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + INT32 disp = FETCH32(cpustate); + if( cpustate->CF != 0 ) { + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jg_rel32)(void) // Opcode 0x0f 8f +static void I386OP(jg_rel32)(i386_state *cpustate) // Opcode 0x0f 8f { - INT32 disp = FETCH32(); - if( I.ZF == 0 && (I.SF == I.OF) ) { - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + INT32 disp = FETCH32(cpustate); + if( cpustate->ZF == 0 && (cpustate->SF == cpustate->OF) ) { + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jge_rel32)(void) // Opcode 0x0f 8d +static void I386OP(jge_rel32)(i386_state *cpustate) // Opcode 0x0f 8d { - INT32 disp = FETCH32(); - if( (I.SF == I.OF) ) { - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + INT32 disp = FETCH32(cpustate); + if( (cpustate->SF == cpustate->OF) ) { + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jl_rel32)(void) // Opcode 0x0f 8c +static void I386OP(jl_rel32)(i386_state *cpustate) // Opcode 0x0f 8c { - INT32 disp = FETCH32(); - if( (I.SF != I.OF) ) { - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + INT32 disp = FETCH32(cpustate); + if( (cpustate->SF != cpustate->OF) ) { + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jle_rel32)(void) // Opcode 0x0f 8e +static void I386OP(jle_rel32)(i386_state *cpustate) // Opcode 0x0f 8e { - INT32 disp = FETCH32(); - if( I.ZF != 0 || (I.SF != I.OF) ) { - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + INT32 disp = FETCH32(cpustate); + if( cpustate->ZF != 0 || (cpustate->SF != cpustate->OF) ) { + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jnc_rel32)(void) // Opcode 0x0f 83 +static void I386OP(jnc_rel32)(i386_state *cpustate) // Opcode 0x0f 83 { - INT32 disp = FETCH32(); - if( I.CF == 0 ) { - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + INT32 disp = FETCH32(cpustate); + if( cpustate->CF == 0 ) { + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jno_rel32)(void) // Opcode 0x0f 81 +static void I386OP(jno_rel32)(i386_state *cpustate) // Opcode 0x0f 81 { - INT32 disp = FETCH32(); - if( I.OF == 0 ) { - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + INT32 disp = FETCH32(cpustate); + if( cpustate->OF == 0 ) { + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jnp_rel32)(void) // Opcode 0x0f 8b +static void I386OP(jnp_rel32)(i386_state *cpustate) // Opcode 0x0f 8b { - INT32 disp = FETCH32(); - if( I.PF == 0 ) { - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + INT32 disp = FETCH32(cpustate); + if( cpustate->PF == 0 ) { + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jns_rel32)(void) // Opcode 0x0f 89 +static void I386OP(jns_rel32)(i386_state *cpustate) // Opcode 0x0f 89 { - INT32 disp = FETCH32(); - if( I.SF == 0 ) { - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + INT32 disp = FETCH32(cpustate); + if( cpustate->SF == 0 ) { + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jnz_rel32)(void) // Opcode 0x0f 85 +static void I386OP(jnz_rel32)(i386_state *cpustate) // Opcode 0x0f 85 { - INT32 disp = FETCH32(); - if( I.ZF == 0 ) { - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + INT32 disp = FETCH32(cpustate); + if( cpustate->ZF == 0 ) { + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jo_rel32)(void) // Opcode 0x0f 80 +static void I386OP(jo_rel32)(i386_state *cpustate) // Opcode 0x0f 80 { - INT32 disp = FETCH32(); - if( I.OF != 0 ) { - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + INT32 disp = FETCH32(cpustate); + if( cpustate->OF != 0 ) { + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jp_rel32)(void) // Opcode 0x0f 8a +static void I386OP(jp_rel32)(i386_state *cpustate) // Opcode 0x0f 8a { - INT32 disp = FETCH32(); - if( I.PF != 0 ) { - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + INT32 disp = FETCH32(cpustate); + if( cpustate->PF != 0 ) { + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(js_rel32)(void) // Opcode 0x0f 88 +static void I386OP(js_rel32)(i386_state *cpustate) // Opcode 0x0f 88 { - INT32 disp = FETCH32(); - if( I.SF != 0 ) { - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + INT32 disp = FETCH32(cpustate); + if( cpustate->SF != 0 ) { + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jz_rel32)(void) // Opcode 0x0f 84 +static void I386OP(jz_rel32)(i386_state *cpustate) // Opcode 0x0f 84 { - INT32 disp = FETCH32(); - if( I.ZF != 0 ) { - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ + INT32 disp = FETCH32(cpustate); + if( cpustate->ZF != 0 ) { + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_FULL_DISP_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_FULL_DISP_NOBRANCH); } } -static void I386OP(jcxz32)(void) // Opcode 0xe3 +static void I386OP(jcxz32)(i386_state *cpustate) // Opcode 0xe3 { - INT8 disp = FETCH(); + INT8 disp = FETCH(cpustate); if( REG32(ECX) == 0 ) { - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_JCXZ); /* TODO: Timing = 9 + m */ + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JCXZ); /* TODO: Timing = 9 + m */ } else { - CYCLES(CYCLES_JCXZ_NOBRANCH); + CYCLES(cpustate,CYCLES_JCXZ_NOBRANCH); } } -static void I386OP(jmp_rel32)(void) // Opcode 0xe9 +static void I386OP(jmp_rel32)(i386_state *cpustate) // Opcode 0xe9 { - UINT32 disp = FETCH32(); + UINT32 disp = FETCH32(cpustate); /* TODO: Segment limit */ - I.eip += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_JMP); /* TODO: Timing = 7 + m */ + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_JMP); /* TODO: Timing = 7 + m */ } -static void I386OP(jmp_abs32)(void) // Opcode 0xea +static void I386OP(jmp_abs32)(i386_state *cpustate) // Opcode 0xea { - UINT32 address = FETCH32(); - UINT16 segment = FETCH16(); + UINT32 address = FETCH32(cpustate); + UINT16 segment = FETCH16(cpustate); if( PROTECTED_MODE ) { /* TODO: #GP */ /* TODO: access rights, etc. */ - I.eip = address; - I.sreg[CS].selector = segment; - i386_load_segment_descriptor(CS); - CHANGE_PC(I.eip); + cpustate->eip = address; + cpustate->sreg[CS].selector = segment; + i386_load_segment_descriptor(cpustate,CS); + CHANGE_PC(cpustate,cpustate->eip); } else { - I.eip = address; - I.sreg[CS].selector = segment; - i386_load_segment_descriptor(CS); - CHANGE_PC(I.eip); + cpustate->eip = address; + cpustate->sreg[CS].selector = segment; + i386_load_segment_descriptor(cpustate,CS); + CHANGE_PC(cpustate,cpustate->eip); } - CYCLES(CYCLES_JMP_INTERSEG); + CYCLES(cpustate,CYCLES_JMP_INTERSEG); } -static void I386OP(lea32)(void) // Opcode 0x8d +static void I386OP(lea32)(i386_state *cpustate) // Opcode 0x8d { - UINT8 modrm = FETCH(); - UINT32 ea = GetNonTranslatedEA(modrm); - if (!I.address_size) + UINT8 modrm = FETCH(cpustate); + UINT32 ea = GetNonTranslatedEA(cpustate,modrm); + if (!cpustate->address_size) { ea &= 0xffff; } STORE_REG32(modrm, ea); - CYCLES(CYCLES_LEA); + CYCLES(cpustate,CYCLES_LEA); } -static void I386OP(leave32)(void) // Opcode 0xc9 +static void I386OP(leave32)(i386_state *cpustate) // Opcode 0xc9 { REG32(ESP) = REG32(EBP); - REG32(EBP) = POP32(); - CYCLES(CYCLES_LEAVE); + REG32(EBP) = POP32(cpustate); + CYCLES(cpustate,CYCLES_LEAVE); } -static void I386OP(lodsd)(void) // Opcode 0xad +static void I386OP(lodsd)(i386_state *cpustate) // Opcode 0xad { UINT32 eas; - if( I.segment_prefix ) { - eas = i386_translate( I.segment_override, I.address_size ? REG32(ESI) : REG16(SI) ); + if( cpustate->segment_prefix ) { + eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } else { - eas = i386_translate( DS, I.address_size ? REG32(ESI) : REG16(SI) ); + eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } - REG32(EAX) = READ32(eas); - BUMP_SI(4); - CYCLES(CYCLES_LODS); + REG32(EAX) = READ32(cpustate,eas); + BUMP_SI(cpustate,4); + CYCLES(cpustate,CYCLES_LODS); } -static void I386OP(loop32)(void) // Opcode 0xe2 +static void I386OP(loop32)(i386_state *cpustate) // Opcode 0xe2 { - INT8 disp = FETCH(); + INT8 disp = FETCH(cpustate); REG32(ECX)--; if( REG32(ECX) != 0 ) { - I.eip += disp; - CHANGE_PC(I.eip); + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); } - CYCLES(CYCLES_LOOP); /* TODO: Timing = 11 + m */ + CYCLES(cpustate,CYCLES_LOOP); /* TODO: Timing = 11 + m */ } -static void I386OP(loopne32)(void) // Opcode 0xe0 +static void I386OP(loopne32)(i386_state *cpustate) // Opcode 0xe0 { - INT8 disp = FETCH(); + INT8 disp = FETCH(cpustate); REG32(ECX)--; - if( REG32(ECX) != 0 && I.ZF == 0 ) { - I.eip += disp; - CHANGE_PC(I.eip); + if( REG32(ECX) != 0 && cpustate->ZF == 0 ) { + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); } - CYCLES(CYCLES_LOOPNZ); /* TODO: Timing = 11 + m */ + CYCLES(cpustate,CYCLES_LOOPNZ); /* TODO: Timing = 11 + m */ } -static void I386OP(loopz32)(void) // Opcode 0xe1 +static void I386OP(loopz32)(i386_state *cpustate) // Opcode 0xe1 { - INT8 disp = FETCH(); + INT8 disp = FETCH(cpustate); REG32(ECX)--; - if( REG32(ECX) != 0 && I.ZF != 0 ) { - I.eip += disp; - CHANGE_PC(I.eip); + if( REG32(ECX) != 0 && cpustate->ZF != 0 ) { + cpustate->eip += disp; + CHANGE_PC(cpustate,cpustate->eip); } - CYCLES(CYCLES_LOOPZ); /* TODO: Timing = 11 + m */ + CYCLES(cpustate,CYCLES_LOOPZ); /* TODO: Timing = 11 + m */ } -static void I386OP(mov_rm32_r32)(void) // Opcode 0x89 +static void I386OP(mov_rm32_r32)(i386_state *cpustate) // Opcode 0x89 { UINT32 src; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG32(modrm); STORE_RM32(modrm, src); - CYCLES(CYCLES_MOV_REG_REG); + CYCLES(cpustate,CYCLES_MOV_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG32(modrm); - WRITE32(ea, src); - CYCLES(CYCLES_MOV_REG_MEM); + WRITE32(cpustate,ea, src); + CYCLES(cpustate,CYCLES_MOV_REG_MEM); } } -static void I386OP(mov_r32_rm32)(void) // Opcode 0x8b +static void I386OP(mov_r32_rm32)(i386_state *cpustate) // Opcode 0x8b { UINT32 src; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM32(modrm); STORE_REG32(modrm, src); - CYCLES(CYCLES_MOV_REG_REG); + CYCLES(cpustate,CYCLES_MOV_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ32(cpustate,ea); STORE_REG32(modrm, src); - CYCLES(CYCLES_MOV_MEM_REG); + CYCLES(cpustate,CYCLES_MOV_MEM_REG); } } -static void I386OP(mov_rm32_i32)(void) // Opcode 0xc7 +static void I386OP(mov_rm32_i32)(i386_state *cpustate) // Opcode 0xc7 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { - UINT32 value = FETCH32(); + UINT32 value = FETCH32(cpustate); STORE_RM32(modrm, value); - CYCLES(CYCLES_MOV_IMM_REG); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 value = FETCH32(); - WRITE32(ea, value); - CYCLES(CYCLES_MOV_IMM_MEM); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 value = FETCH32(cpustate); + WRITE32(cpustate,ea, value); + CYCLES(cpustate,CYCLES_MOV_IMM_MEM); } } -static void I386OP(mov_eax_m32)(void) // Opcode 0xa1 +static void I386OP(mov_eax_m32)(i386_state *cpustate) // Opcode 0xa1 { UINT32 offset, ea; - if( I.address_size ) { - offset = FETCH32(); + if( cpustate->address_size ) { + offset = FETCH32(cpustate); } else { - offset = FETCH16(); + offset = FETCH16(cpustate); } - if( I.segment_prefix ) { - ea = i386_translate( I.segment_override, offset ); + if( cpustate->segment_prefix ) { + ea = i386_translate(cpustate, cpustate->segment_override, offset ); } else { - ea = i386_translate( DS, offset ); + ea = i386_translate(cpustate, DS, offset ); } - REG32(EAX) = READ32(ea); - CYCLES(CYCLES_MOV_MEM_ACC); + REG32(EAX) = READ32(cpustate,ea); + CYCLES(cpustate,CYCLES_MOV_MEM_ACC); } -static void I386OP(mov_m32_eax)(void) // Opcode 0xa3 +static void I386OP(mov_m32_eax)(i386_state *cpustate) // Opcode 0xa3 { UINT32 offset, ea; - if( I.address_size ) { - offset = FETCH32(); + if( cpustate->address_size ) { + offset = FETCH32(cpustate); } else { - offset = FETCH16(); + offset = FETCH16(cpustate); } - if( I.segment_prefix ) { - ea = i386_translate( I.segment_override, offset ); + if( cpustate->segment_prefix ) { + ea = i386_translate(cpustate, cpustate->segment_override, offset ); } else { - ea = i386_translate( DS, offset ); + ea = i386_translate(cpustate, DS, offset ); } - WRITE32( ea, REG32(EAX) ); - CYCLES(CYCLES_MOV_ACC_MEM); + WRITE32(cpustate, ea, REG32(EAX) ); + CYCLES(cpustate,CYCLES_MOV_ACC_MEM); } -static void I386OP(mov_eax_i32)(void) // Opcode 0xb8 +static void I386OP(mov_eax_i32)(i386_state *cpustate) // Opcode 0xb8 { - REG32(EAX) = FETCH32(); - CYCLES(CYCLES_MOV_IMM_REG); + REG32(EAX) = FETCH32(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_ecx_i32)(void) // Opcode 0xb9 +static void I386OP(mov_ecx_i32)(i386_state *cpustate) // Opcode 0xb9 { - REG32(ECX) = FETCH32(); - CYCLES(CYCLES_MOV_IMM_REG); + REG32(ECX) = FETCH32(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_edx_i32)(void) // Opcode 0xba +static void I386OP(mov_edx_i32)(i386_state *cpustate) // Opcode 0xba { - REG32(EDX) = FETCH32(); - CYCLES(CYCLES_MOV_IMM_REG); + REG32(EDX) = FETCH32(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_ebx_i32)(void) // Opcode 0xbb +static void I386OP(mov_ebx_i32)(i386_state *cpustate) // Opcode 0xbb { - REG32(EBX) = FETCH32(); - CYCLES(CYCLES_MOV_IMM_REG); + REG32(EBX) = FETCH32(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_esp_i32)(void) // Opcode 0xbc +static void I386OP(mov_esp_i32)(i386_state *cpustate) // Opcode 0xbc { - REG32(ESP) = FETCH32(); - CYCLES(CYCLES_MOV_IMM_REG); + REG32(ESP) = FETCH32(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_ebp_i32)(void) // Opcode 0xbd +static void I386OP(mov_ebp_i32)(i386_state *cpustate) // Opcode 0xbd { - REG32(EBP) = FETCH32(); - CYCLES(CYCLES_MOV_IMM_REG); + REG32(EBP) = FETCH32(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_esi_i32)(void) // Opcode 0xbe +static void I386OP(mov_esi_i32)(i386_state *cpustate) // Opcode 0xbe { - REG32(ESI) = FETCH32(); - CYCLES(CYCLES_MOV_IMM_REG); + REG32(ESI) = FETCH32(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_edi_i32)(void) // Opcode 0xbf +static void I386OP(mov_edi_i32)(i386_state *cpustate) // Opcode 0xbf { - REG32(EDI) = FETCH32(); - CYCLES(CYCLES_MOV_IMM_REG); + REG32(EDI) = FETCH32(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(movsd)(void) // Opcode 0xa5 +static void I386OP(movsd)(i386_state *cpustate) // Opcode 0xa5 { UINT32 eas, ead, v; - if( I.segment_prefix ) { - eas = i386_translate( I.segment_override, I.address_size ? REG32(ESI) : REG16(SI) ); + if( cpustate->segment_prefix ) { + eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } else { - eas = i386_translate( DS, I.address_size ? REG32(ESI) : REG16(SI) ); + eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } - ead = i386_translate( ES, I.address_size ? REG32(EDI) : REG16(DI) ); - v = READ32(eas); - WRITE32(ead, v); - BUMP_SI(4); - BUMP_DI(4); - CYCLES(CYCLES_MOVS); + ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI) ); + v = READ32(cpustate,eas); + WRITE32(cpustate,ead, v); + BUMP_SI(cpustate,4); + BUMP_DI(cpustate,4); + CYCLES(cpustate,CYCLES_MOVS); } -static void I386OP(movsx_r32_rm8)(void) // Opcode 0x0f be +static void I386OP(movsx_r32_rm8)(i386_state *cpustate) // Opcode 0x0f be { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { INT32 src = (INT8)LOAD_RM8(modrm); STORE_REG32(modrm, src); - CYCLES(CYCLES_MOVSX_REG_REG); + CYCLES(cpustate,CYCLES_MOVSX_REG_REG); } else { - UINT32 ea = GetEA(modrm); - INT32 src = (INT8)READ8(ea); + UINT32 ea = GetEA(cpustate,modrm); + INT32 src = (INT8)READ8(cpustate,ea); STORE_REG32(modrm, src); - CYCLES(CYCLES_MOVSX_MEM_REG); + CYCLES(cpustate,CYCLES_MOVSX_MEM_REG); } } -static void I386OP(movsx_r32_rm16)(void) // Opcode 0x0f bf +static void I386OP(movsx_r32_rm16)(i386_state *cpustate) // Opcode 0x0f bf { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { INT32 src = (INT16)LOAD_RM16(modrm); STORE_REG32(modrm, src); - CYCLES(CYCLES_MOVSX_REG_REG); + CYCLES(cpustate,CYCLES_MOVSX_REG_REG); } else { - UINT32 ea = GetEA(modrm); - INT32 src = (INT16)READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + INT32 src = (INT16)READ16(cpustate,ea); STORE_REG32(modrm, src); - CYCLES(CYCLES_MOVSX_MEM_REG); + CYCLES(cpustate,CYCLES_MOVSX_MEM_REG); } } -static void I386OP(movzx_r32_rm8)(void) // Opcode 0x0f b6 +static void I386OP(movzx_r32_rm8)(i386_state *cpustate) // Opcode 0x0f b6 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT32 src = (UINT8)LOAD_RM8(modrm); STORE_REG32(modrm, src); - CYCLES(CYCLES_MOVZX_REG_REG); + CYCLES(cpustate,CYCLES_MOVZX_REG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 src = (UINT8)READ8(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 src = (UINT8)READ8(cpustate,ea); STORE_REG32(modrm, src); - CYCLES(CYCLES_MOVZX_MEM_REG); + CYCLES(cpustate,CYCLES_MOVZX_MEM_REG); } } -static void I386OP(movzx_r32_rm16)(void) // Opcode 0x0f b7 +static void I386OP(movzx_r32_rm16)(i386_state *cpustate) // Opcode 0x0f b7 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT32 src = (UINT16)LOAD_RM16(modrm); STORE_REG32(modrm, src); - CYCLES(CYCLES_MOVZX_REG_REG); + CYCLES(cpustate,CYCLES_MOVZX_REG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 src = (UINT16)READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 src = (UINT16)READ16(cpustate,ea); STORE_REG32(modrm, src); - CYCLES(CYCLES_MOVZX_MEM_REG); + CYCLES(cpustate,CYCLES_MOVZX_MEM_REG); } } -static void I386OP(or_rm32_r32)(void) // Opcode 0x09 +static void I386OP(or_rm32_r32)(i386_state *cpustate) // Opcode 0x09 { UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG32(modrm); dst = LOAD_RM32(modrm); - dst = OR32(dst, src); + dst = OR32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG32(modrm); - dst = READ32(ea); - dst = OR32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + dst = READ32(cpustate,ea); + dst = OR32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(or_r32_rm32)(void) // Opcode 0x0b +static void I386OP(or_r32_rm32)(i386_state *cpustate) // Opcode 0x0b { UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM32(modrm); dst = LOAD_REG32(modrm); - dst = OR32(dst, src); + dst = OR32(cpustate,dst, src); STORE_REG32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ32(cpustate,ea); dst = LOAD_REG32(modrm); - dst = OR32(dst, src); + dst = OR32(cpustate,dst, src); STORE_REG32(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(or_eax_i32)(void) // Opcode 0x0d +static void I386OP(or_eax_i32)(i386_state *cpustate) // Opcode 0x0d { UINT32 src, dst; - src = FETCH32(); + src = FETCH32(cpustate); dst = REG32(EAX); - dst = OR32(dst, src); + dst = OR32(cpustate,dst, src); REG32(EAX) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(out_eax_i8)(void) // Opcode 0xe7 +static void I386OP(out_eax_i8)(i386_state *cpustate) // Opcode 0xe7 { - UINT16 port = FETCH(); + UINT16 port = FETCH(cpustate); UINT32 data = REG32(EAX); WRITEPORT32(port, data); - CYCLES(CYCLES_OUT_VAR); + CYCLES(cpustate,CYCLES_OUT_VAR); } -static void I386OP(out_eax_dx)(void) // Opcode 0xef +static void I386OP(out_eax_dx)(i386_state *cpustate) // Opcode 0xef { UINT16 port = REG16(DX); UINT32 data = REG32(EAX); WRITEPORT32(port, data); - CYCLES(CYCLES_OUT); + CYCLES(cpustate,CYCLES_OUT); } -static void I386OP(pop_eax)(void) // Opcode 0x58 +static void I386OP(pop_eax)(i386_state *cpustate) // Opcode 0x58 { - REG32(EAX) = POP32(); - CYCLES(CYCLES_POP_REG_SHORT); + REG32(EAX) = POP32(cpustate); + CYCLES(cpustate,CYCLES_POP_REG_SHORT); } -static void I386OP(pop_ecx)(void) // Opcode 0x59 +static void I386OP(pop_ecx)(i386_state *cpustate) // Opcode 0x59 { - REG32(ECX) = POP32(); - CYCLES(CYCLES_POP_REG_SHORT); + REG32(ECX) = POP32(cpustate); + CYCLES(cpustate,CYCLES_POP_REG_SHORT); } -static void I386OP(pop_edx)(void) // Opcode 0x5a +static void I386OP(pop_edx)(i386_state *cpustate) // Opcode 0x5a { - REG32(EDX) = POP32(); - CYCLES(CYCLES_POP_REG_SHORT); + REG32(EDX) = POP32(cpustate); + CYCLES(cpustate,CYCLES_POP_REG_SHORT); } -static void I386OP(pop_ebx)(void) // Opcode 0x5b +static void I386OP(pop_ebx)(i386_state *cpustate) // Opcode 0x5b { - REG32(EBX) = POP32(); - CYCLES(CYCLES_POP_REG_SHORT); + REG32(EBX) = POP32(cpustate); + CYCLES(cpustate,CYCLES_POP_REG_SHORT); } -static void I386OP(pop_esp)(void) // Opcode 0x5c +static void I386OP(pop_esp)(i386_state *cpustate) // Opcode 0x5c { - REG32(ESP) = POP32(); - CYCLES(CYCLES_POP_REG_SHORT); + REG32(ESP) = POP32(cpustate); + CYCLES(cpustate,CYCLES_POP_REG_SHORT); } -static void I386OP(pop_ebp)(void) // Opcode 0x5d +static void I386OP(pop_ebp)(i386_state *cpustate) // Opcode 0x5d { - REG32(EBP) = POP32(); - CYCLES(CYCLES_POP_REG_SHORT); + REG32(EBP) = POP32(cpustate); + CYCLES(cpustate,CYCLES_POP_REG_SHORT); } -static void I386OP(pop_esi)(void) // Opcode 0x5e +static void I386OP(pop_esi)(i386_state *cpustate) // Opcode 0x5e { - REG32(ESI) = POP32(); - CYCLES(CYCLES_POP_REG_SHORT); + REG32(ESI) = POP32(cpustate); + CYCLES(cpustate,CYCLES_POP_REG_SHORT); } -static void I386OP(pop_edi)(void) // Opcode 0x5f +static void I386OP(pop_edi)(i386_state *cpustate) // Opcode 0x5f { - REG32(EDI) = POP32(); - CYCLES(CYCLES_POP_REG_SHORT); + REG32(EDI) = POP32(cpustate); + CYCLES(cpustate,CYCLES_POP_REG_SHORT); } -static void I386OP(pop_ds32)(void) // Opcode 0x1f +static void I386OP(pop_ds32)(i386_state *cpustate) // Opcode 0x1f { - I.sreg[DS].selector = POP32(); + cpustate->sreg[DS].selector = POP32(cpustate); if( PROTECTED_MODE ) { - i386_load_segment_descriptor(DS); + i386_load_segment_descriptor(cpustate,DS); } else { - i386_load_segment_descriptor(DS); + i386_load_segment_descriptor(cpustate,DS); } - CYCLES(CYCLES_POP_SREG); + CYCLES(cpustate,CYCLES_POP_SREG); } -static void I386OP(pop_es32)(void) // Opcode 0x07 +static void I386OP(pop_es32)(i386_state *cpustate) // Opcode 0x07 { - I.sreg[ES].selector = POP32(); + cpustate->sreg[ES].selector = POP32(cpustate); if( PROTECTED_MODE ) { - i386_load_segment_descriptor(ES); + i386_load_segment_descriptor(cpustate,ES); } else { - i386_load_segment_descriptor(ES); + i386_load_segment_descriptor(cpustate,ES); } - CYCLES(CYCLES_POP_SREG); + CYCLES(cpustate,CYCLES_POP_SREG); } -static void I386OP(pop_fs32)(void) // Opcode 0x0f a1 +static void I386OP(pop_fs32)(i386_state *cpustate) // Opcode 0x0f a1 { - I.sreg[FS].selector = POP32(); + cpustate->sreg[FS].selector = POP32(cpustate); if( PROTECTED_MODE ) { - i386_load_segment_descriptor(FS); + i386_load_segment_descriptor(cpustate,FS); } else { - i386_load_segment_descriptor(FS); + i386_load_segment_descriptor(cpustate,FS); } - CYCLES(CYCLES_POP_SREG); + CYCLES(cpustate,CYCLES_POP_SREG); } -static void I386OP(pop_gs32)(void) // Opcode 0x0f a9 +static void I386OP(pop_gs32)(i386_state *cpustate) // Opcode 0x0f a9 { - I.sreg[GS].selector = POP32(); + cpustate->sreg[GS].selector = POP32(cpustate); if( PROTECTED_MODE ) { - i386_load_segment_descriptor(GS); + i386_load_segment_descriptor(cpustate,GS); } else { - i386_load_segment_descriptor(GS); + i386_load_segment_descriptor(cpustate,GS); } - CYCLES(CYCLES_POP_SREG); + CYCLES(cpustate,CYCLES_POP_SREG); } -static void I386OP(pop_ss32)(void) // Opcode 0x17 +static void I386OP(pop_ss32)(i386_state *cpustate) // Opcode 0x17 { - I.sreg[SS].selector = POP32(); + cpustate->sreg[SS].selector = POP32(cpustate); if( PROTECTED_MODE ) { - i386_load_segment_descriptor(SS); + i386_load_segment_descriptor(cpustate,SS); } else { - i386_load_segment_descriptor(SS); + i386_load_segment_descriptor(cpustate,SS); } - CYCLES(CYCLES_POP_SREG); + CYCLES(cpustate,CYCLES_POP_SREG); } -static void I386OP(pop_rm32)(void) // Opcode 0x8f +static void I386OP(pop_rm32)(i386_state *cpustate) // Opcode 0x8f { - UINT8 modrm = FETCH(); - UINT32 value = POP32(); + UINT8 modrm = FETCH(cpustate); + UINT32 value = POP32(cpustate); if( modrm >= 0xc0 ) { STORE_RM32(modrm, value); } else { - UINT32 ea = GetEA(modrm); - WRITE32(ea, value); + UINT32 ea = GetEA(cpustate,modrm); + WRITE32(cpustate,ea, value); } - CYCLES(CYCLES_POP_RM); + CYCLES(cpustate,CYCLES_POP_RM); } -static void I386OP(popad)(void) // Opcode 0x61 +static void I386OP(popad)(i386_state *cpustate) // Opcode 0x61 { - REG32(EDI) = POP32(); - REG32(ESI) = POP32(); - REG32(EBP) = POP32(); + REG32(EDI) = POP32(cpustate); + REG32(ESI) = POP32(cpustate); + REG32(EBP) = POP32(cpustate); REG32(ESP) += 4; - REG32(EBX) = POP32(); - REG32(EDX) = POP32(); - REG32(ECX) = POP32(); - REG32(EAX) = POP32(); - CYCLES(CYCLES_POPA); + REG32(EBX) = POP32(cpustate); + REG32(EDX) = POP32(cpustate); + REG32(ECX) = POP32(cpustate); + REG32(EAX) = POP32(cpustate); + CYCLES(cpustate,CYCLES_POPA); } -static void I386OP(popfd)(void) // Opcode 0x9d +static void I386OP(popfd)(i386_state *cpustate) // Opcode 0x9d { - UINT32 value = POP32(); - set_flags(value); - CYCLES(CYCLES_POPF); + UINT32 value = POP32(cpustate); + set_flags(cpustate,value); + CYCLES(cpustate,CYCLES_POPF); } -static void I386OP(push_eax)(void) // Opcode 0x50 +static void I386OP(push_eax)(i386_state *cpustate) // Opcode 0x50 { - PUSH32( REG32(EAX) ); - CYCLES(CYCLES_PUSH_REG_SHORT); + PUSH32(cpustate, REG32(EAX) ); + CYCLES(cpustate,CYCLES_PUSH_REG_SHORT); } -static void I386OP(push_ecx)(void) // Opcode 0x51 +static void I386OP(push_ecx)(i386_state *cpustate) // Opcode 0x51 { - PUSH32( REG32(ECX) ); - CYCLES(CYCLES_PUSH_REG_SHORT); + PUSH32(cpustate, REG32(ECX) ); + CYCLES(cpustate,CYCLES_PUSH_REG_SHORT); } -static void I386OP(push_edx)(void) // Opcode 0x52 +static void I386OP(push_edx)(i386_state *cpustate) // Opcode 0x52 { - PUSH32( REG32(EDX) ); - CYCLES(CYCLES_PUSH_REG_SHORT); + PUSH32(cpustate, REG32(EDX) ); + CYCLES(cpustate,CYCLES_PUSH_REG_SHORT); } -static void I386OP(push_ebx)(void) // Opcode 0x53 +static void I386OP(push_ebx)(i386_state *cpustate) // Opcode 0x53 { - PUSH32( REG32(EBX) ); - CYCLES(CYCLES_PUSH_REG_SHORT); + PUSH32(cpustate, REG32(EBX) ); + CYCLES(cpustate,CYCLES_PUSH_REG_SHORT); } -static void I386OP(push_esp)(void) // Opcode 0x54 +static void I386OP(push_esp)(i386_state *cpustate) // Opcode 0x54 { - PUSH32( REG32(ESP) ); - CYCLES(CYCLES_PUSH_REG_SHORT); + PUSH32(cpustate, REG32(ESP) ); + CYCLES(cpustate,CYCLES_PUSH_REG_SHORT); } -static void I386OP(push_ebp)(void) // Opcode 0x55 +static void I386OP(push_ebp)(i386_state *cpustate) // Opcode 0x55 { - PUSH32( REG32(EBP) ); - CYCLES(CYCLES_PUSH_REG_SHORT); + PUSH32(cpustate, REG32(EBP) ); + CYCLES(cpustate,CYCLES_PUSH_REG_SHORT); } -static void I386OP(push_esi)(void) // Opcode 0x56 +static void I386OP(push_esi)(i386_state *cpustate) // Opcode 0x56 { - PUSH32( REG32(ESI) ); - CYCLES(CYCLES_PUSH_REG_SHORT); + PUSH32(cpustate, REG32(ESI) ); + CYCLES(cpustate,CYCLES_PUSH_REG_SHORT); } -static void I386OP(push_edi)(void) // Opcode 0x57 +static void I386OP(push_edi)(i386_state *cpustate) // Opcode 0x57 { - PUSH32( REG32(EDI) ); - CYCLES(CYCLES_PUSH_REG_SHORT); + PUSH32(cpustate, REG32(EDI) ); + CYCLES(cpustate,CYCLES_PUSH_REG_SHORT); } -static void I386OP(push_cs32)(void) // Opcode 0x0e +static void I386OP(push_cs32)(i386_state *cpustate) // Opcode 0x0e { - PUSH32( I.sreg[CS].selector ); - CYCLES(CYCLES_PUSH_SREG); + PUSH32(cpustate, cpustate->sreg[CS].selector ); + CYCLES(cpustate,CYCLES_PUSH_SREG); } -static void I386OP(push_ds32)(void) // Opcode 0x1e +static void I386OP(push_ds32)(i386_state *cpustate) // Opcode 0x1e { - PUSH32( I.sreg[DS].selector ); - CYCLES(CYCLES_PUSH_SREG); + PUSH32(cpustate, cpustate->sreg[DS].selector ); + CYCLES(cpustate,CYCLES_PUSH_SREG); } -static void I386OP(push_es32)(void) // Opcode 0x06 +static void I386OP(push_es32)(i386_state *cpustate) // Opcode 0x06 { - PUSH32( I.sreg[ES].selector ); - CYCLES(CYCLES_PUSH_SREG); + PUSH32(cpustate, cpustate->sreg[ES].selector ); + CYCLES(cpustate,CYCLES_PUSH_SREG); } -static void I386OP(push_fs32)(void) // Opcode 0x0f a0 +static void I386OP(push_fs32)(i386_state *cpustate) // Opcode 0x0f a0 { - PUSH32( I.sreg[FS].selector ); - CYCLES(CYCLES_PUSH_SREG); + PUSH32(cpustate, cpustate->sreg[FS].selector ); + CYCLES(cpustate,CYCLES_PUSH_SREG); } -static void I386OP(push_gs32)(void) // Opcode 0x0f a8 +static void I386OP(push_gs32)(i386_state *cpustate) // Opcode 0x0f a8 { - PUSH32( I.sreg[GS].selector ); - CYCLES(CYCLES_PUSH_SREG); + PUSH32(cpustate, cpustate->sreg[GS].selector ); + CYCLES(cpustate,CYCLES_PUSH_SREG); } -static void I386OP(push_ss32)(void) // Opcode 0x16 +static void I386OP(push_ss32)(i386_state *cpustate) // Opcode 0x16 { - PUSH32( I.sreg[SS].selector ); - CYCLES(CYCLES_PUSH_SREG); + PUSH32(cpustate, cpustate->sreg[SS].selector ); + CYCLES(cpustate,CYCLES_PUSH_SREG); } -static void I386OP(push_i32)(void) // Opcode 0x68 +static void I386OP(push_i32)(i386_state *cpustate) // Opcode 0x68 { - UINT32 value = FETCH32(); - PUSH32(value); - CYCLES(CYCLES_PUSH_IMM); + UINT32 value = FETCH32(cpustate); + PUSH32(cpustate,value); + CYCLES(cpustate,CYCLES_PUSH_IMM); } -static void I386OP(pushad)(void) // Opcode 0x60 +static void I386OP(pushad)(i386_state *cpustate) // Opcode 0x60 { UINT32 temp = REG32(ESP); - PUSH32( REG32(EAX) ); - PUSH32( REG32(ECX) ); - PUSH32( REG32(EDX) ); - PUSH32( REG32(EBX) ); - PUSH32( temp ); - PUSH32( REG32(EBP) ); - PUSH32( REG32(ESI) ); - PUSH32( REG32(EDI) ); - CYCLES(CYCLES_PUSHA); + PUSH32(cpustate, REG32(EAX) ); + PUSH32(cpustate, REG32(ECX) ); + PUSH32(cpustate, REG32(EDX) ); + PUSH32(cpustate, REG32(EBX) ); + PUSH32(cpustate, temp ); + PUSH32(cpustate, REG32(EBP) ); + PUSH32(cpustate, REG32(ESI) ); + PUSH32(cpustate, REG32(EDI) ); + CYCLES(cpustate,CYCLES_PUSHA); } -static void I386OP(pushfd)(void) // Opcode 0x9c +static void I386OP(pushfd)(i386_state *cpustate) // Opcode 0x9c { - PUSH32( get_flags() & 0x00fcffff ); - CYCLES(CYCLES_PUSHF); + PUSH32(cpustate, get_flags(cpustate) & 0x00fcffff ); + CYCLES(cpustate,CYCLES_PUSHF); } -static void I386OP(ret_near32_i16)(void) // Opcode 0xc2 +static void I386OP(ret_near32_i16)(i386_state *cpustate) // Opcode 0xc2 { - INT16 disp = FETCH16(); - I.eip = POP32(); + INT16 disp = FETCH16(cpustate); + cpustate->eip = POP32(cpustate); REG32(ESP) += disp; - CHANGE_PC(I.eip); - CYCLES(CYCLES_RET_IMM); /* TODO: Timing = 10 + m */ + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_RET_IMM); /* TODO: Timing = 10 + m */ } -static void I386OP(ret_near32)(void) // Opcode 0xc3 +static void I386OP(ret_near32)(i386_state *cpustate) // Opcode 0xc3 { - I.eip = POP32(); - CHANGE_PC(I.eip); - CYCLES(CYCLES_RET); /* TODO: Timing = 10 + m */ + cpustate->eip = POP32(cpustate); + CHANGE_PC(cpustate,cpustate->eip); + CYCLES(cpustate,CYCLES_RET); /* TODO: Timing = 10 + m */ } -static void I386OP(sbb_rm32_r32)(void) // Opcode 0x19 +static void I386OP(sbb_rm32_r32)(i386_state *cpustate) // Opcode 0x19 { UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { - src = LOAD_REG32(modrm) + I.CF; + src = LOAD_REG32(modrm) + cpustate->CF; dst = LOAD_RM32(modrm); - dst = SUB32(dst, src); + dst = SUB32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = LOAD_REG32(modrm) + I.CF; - dst = READ32(ea); - dst = SUB32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + UINT32 ea = GetEA(cpustate,modrm); + src = LOAD_REG32(modrm) + cpustate->CF; + dst = READ32(cpustate,ea); + dst = SUB32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(sbb_r32_rm32)(void) // Opcode 0x1b +static void I386OP(sbb_r32_rm32)(i386_state *cpustate) // Opcode 0x1b { UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { - src = LOAD_RM32(modrm) + I.CF; + src = LOAD_RM32(modrm) + cpustate->CF; dst = LOAD_REG32(modrm); - dst = SUB32(dst, src); + dst = SUB32(cpustate,dst, src); STORE_REG32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ32(ea) + I.CF; + UINT32 ea = GetEA(cpustate,modrm); + src = READ32(cpustate,ea) + cpustate->CF; dst = LOAD_REG32(modrm); - dst = SUB32(dst, src); + dst = SUB32(cpustate,dst, src); STORE_REG32(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(sbb_eax_i32)(void) // Opcode 0x1d +static void I386OP(sbb_eax_i32)(i386_state *cpustate) // Opcode 0x1d { UINT32 src, dst; - src = FETCH32() + I.CF; + src = FETCH32(cpustate) + cpustate->CF; dst = REG32(EAX); - dst = SUB32(dst, src); + dst = SUB32(cpustate,dst, src); REG32(EAX) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(scasd)(void) // Opcode 0xaf +static void I386OP(scasd)(i386_state *cpustate) // Opcode 0xaf { UINT32 eas, src, dst; - eas = i386_translate( ES, I.address_size ? REG32(EDI) : REG16(DI) ); - src = READ32(eas); + eas = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI) ); + src = READ32(cpustate,eas); dst = REG32(EAX); - SUB32(dst, src); - BUMP_DI(4); - CYCLES(CYCLES_SCAS); + SUB32(cpustate,dst, src); + BUMP_DI(cpustate,4); + CYCLES(cpustate,CYCLES_SCAS); } -static void I386OP(shld32_i8)(void) // Opcode 0x0f a4 +static void I386OP(shld32_i8)(i386_state *cpustate) // Opcode 0x0f a4 { /* TODO: Correct flags */ - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); UINT32 upper = LOAD_REG32(modrm); - UINT8 shift = FETCH(); + UINT8 shift = FETCH(cpustate); if( shift > 31 || shift == 0 ) { } else { - I.CF = (dst & (1 << (32-shift))) ? 1 : 0; + cpustate->CF = (dst & (1 << (32-shift))) ? 1 : 0; dst = (dst << shift) | (upper >> (32-shift)); SetSZPF32(dst); } STORE_RM32(modrm, dst); - CYCLES(CYCLES_SHLD_REG); + CYCLES(cpustate,CYCLES_SHLD_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); UINT32 upper = LOAD_REG32(modrm); - UINT8 shift = FETCH(); + UINT8 shift = FETCH(cpustate); if( shift > 31 || shift == 0 ) { } else { - I.CF = (dst & (1 << (32-shift))) ? 1 : 0; + cpustate->CF = (dst & (1 << (32-shift))) ? 1 : 0; dst = (dst << shift) | (upper >> (32-shift)); SetSZPF32(dst); } - WRITE32(ea, dst); - CYCLES(CYCLES_SHLD_MEM); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_SHLD_MEM); } } -static void I386OP(shld32_cl)(void) // Opcode 0x0f a5 +static void I386OP(shld32_cl)(i386_state *cpustate) // Opcode 0x0f a5 { /* TODO: Correct flags */ - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); UINT32 upper = LOAD_REG32(modrm); @@ -1697,67 +1697,67 @@ static void I386OP(shld32_cl)(void) // Opcode 0x0f a5 if( shift > 31 || shift == 0 ) { } else { - I.CF = (dst & (1 << (32-shift))) ? 1 : 0; + cpustate->CF = (dst & (1 << (32-shift))) ? 1 : 0; dst = (dst << shift) | (upper >> (32-shift)); SetSZPF32(dst); } STORE_RM32(modrm, dst); - CYCLES(CYCLES_SHLD_REG); + CYCLES(cpustate,CYCLES_SHLD_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); UINT32 upper = LOAD_REG32(modrm); UINT8 shift = REG8(CL); if( shift > 31 || shift == 0 ) { } else { - I.CF = (dst & (1 << (32-shift))) ? 1 : 0; + cpustate->CF = (dst & (1 << (32-shift))) ? 1 : 0; dst = (dst << shift) | (upper >> (32-shift)); SetSZPF32(dst); } - WRITE32(ea, dst); - CYCLES(CYCLES_SHLD_MEM); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_SHLD_MEM); } } -static void I386OP(shrd32_i8)(void) // Opcode 0x0f ac +static void I386OP(shrd32_i8)(i386_state *cpustate) // Opcode 0x0f ac { /* TODO: Correct flags */ - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); UINT32 upper = LOAD_REG32(modrm); - UINT8 shift = FETCH(); + UINT8 shift = FETCH(cpustate); if( shift > 31 || shift == 0 ) { } else { - I.CF = (dst & (1 << (shift-1))) ? 1 : 0; + cpustate->CF = (dst & (1 << (shift-1))) ? 1 : 0; dst = (dst >> shift) | (upper << (32-shift)); SetSZPF32(dst); } STORE_RM32(modrm, dst); - CYCLES(CYCLES_SHRD_REG); + CYCLES(cpustate,CYCLES_SHRD_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); UINT32 upper = LOAD_REG32(modrm); - UINT8 shift = FETCH(); + UINT8 shift = FETCH(cpustate); if( shift > 31 || shift == 0 ) { } else { - I.CF = (dst & (1 << (shift-1))) ? 1 : 0; + cpustate->CF = (dst & (1 << (shift-1))) ? 1 : 0; dst = (dst >> shift) | (upper << (32-shift)); SetSZPF32(dst); } - WRITE32(ea, dst); - CYCLES(CYCLES_SHRD_MEM); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_SHRD_MEM); } } -static void I386OP(shrd32_cl)(void) // Opcode 0x0f ad +static void I386OP(shrd32_cl)(i386_state *cpustate) // Opcode 0x0f ad { /* TODO: Correct flags */ - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); UINT32 upper = LOAD_REG32(modrm); @@ -1765,610 +1765,610 @@ static void I386OP(shrd32_cl)(void) // Opcode 0x0f ad if( shift > 31 || shift == 0 ) { } else { - I.CF = (dst & (1 << (shift-1))) ? 1 : 0; + cpustate->CF = (dst & (1 << (shift-1))) ? 1 : 0; dst = (dst >> shift) | (upper << (32-shift)); SetSZPF32(dst); } STORE_RM32(modrm, dst); - CYCLES(CYCLES_SHRD_REG); + CYCLES(cpustate,CYCLES_SHRD_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); UINT32 upper = LOAD_REG32(modrm); UINT8 shift = REG8(CL); if( shift > 31 || shift == 0 ) { } else { - I.CF = (dst & (1 << (shift-1))) ? 1 : 0; + cpustate->CF = (dst & (1 << (shift-1))) ? 1 : 0; dst = (dst >> shift) | (upper << (32-shift)); SetSZPF32(dst); } - WRITE32(ea, dst); - CYCLES(CYCLES_SHRD_MEM); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_SHRD_MEM); } } -static void I386OP(stosd)(void) // Opcode 0xab +static void I386OP(stosd)(i386_state *cpustate) // Opcode 0xab { - UINT32 eas = i386_translate( ES, I.address_size ? REG32(EDI) : REG16(DI) ); - WRITE32(eas, REG32(EAX)); - BUMP_DI(4); - CYCLES(CYCLES_STOS); + UINT32 eas = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI) ); + WRITE32(cpustate,eas, REG32(EAX)); + BUMP_DI(cpustate,4); + CYCLES(cpustate,CYCLES_STOS); } -static void I386OP(sub_rm32_r32)(void) // Opcode 0x29 +static void I386OP(sub_rm32_r32)(i386_state *cpustate) // Opcode 0x29 { UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG32(modrm); dst = LOAD_RM32(modrm); - dst = SUB32(dst, src); + dst = SUB32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG32(modrm); - dst = READ32(ea); - dst = SUB32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + dst = READ32(cpustate,ea); + dst = SUB32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(sub_r32_rm32)(void) // Opcode 0x2b +static void I386OP(sub_r32_rm32)(i386_state *cpustate) // Opcode 0x2b { UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM32(modrm); dst = LOAD_REG32(modrm); - dst = SUB32(dst, src); + dst = SUB32(cpustate,dst, src); STORE_REG32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ32(cpustate,ea); dst = LOAD_REG32(modrm); - dst = SUB32(dst, src); + dst = SUB32(cpustate,dst, src); STORE_REG32(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(sub_eax_i32)(void) // Opcode 0x2d +static void I386OP(sub_eax_i32)(i386_state *cpustate) // Opcode 0x2d { UINT32 src, dst; - src = FETCH32(); + src = FETCH32(cpustate); dst = REG32(EAX); - dst = SUB32(dst, src); + dst = SUB32(cpustate,dst, src); REG32(EAX) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(test_eax_i32)(void) // Opcode 0xa9 +static void I386OP(test_eax_i32)(i386_state *cpustate) // Opcode 0xa9 { - UINT32 src = FETCH32(); + UINT32 src = FETCH32(cpustate); UINT32 dst = REG32(EAX); dst = src & dst; SetSZPF32(dst); - I.CF = 0; - I.OF = 0; - CYCLES(CYCLES_TEST_IMM_ACC); + cpustate->CF = 0; + cpustate->OF = 0; + CYCLES(cpustate,CYCLES_TEST_IMM_ACC); } -static void I386OP(test_rm32_r32)(void) // Opcode 0x85 +static void I386OP(test_rm32_r32)(i386_state *cpustate) // Opcode 0x85 { UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG32(modrm); dst = LOAD_RM32(modrm); dst = src & dst; SetSZPF32(dst); - I.CF = 0; - I.OF = 0; - CYCLES(CYCLES_TEST_REG_REG); + cpustate->CF = 0; + cpustate->OF = 0; + CYCLES(cpustate,CYCLES_TEST_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG32(modrm); - dst = READ32(ea); + dst = READ32(cpustate,ea); dst = src & dst; SetSZPF32(dst); - I.CF = 0; - I.OF = 0; - CYCLES(CYCLES_TEST_REG_MEM); + cpustate->CF = 0; + cpustate->OF = 0; + CYCLES(cpustate,CYCLES_TEST_REG_MEM); } } -static void I386OP(xchg_eax_ecx)(void) // Opcode 0x91 +static void I386OP(xchg_eax_ecx)(i386_state *cpustate) // Opcode 0x91 { UINT32 temp; temp = REG32(EAX); REG32(EAX) = REG32(ECX); REG32(ECX) = temp; - CYCLES(CYCLES_XCHG_REG_REG); + CYCLES(cpustate,CYCLES_XCHG_REG_REG); } -static void I386OP(xchg_eax_edx)(void) // Opcode 0x92 +static void I386OP(xchg_eax_edx)(i386_state *cpustate) // Opcode 0x92 { UINT32 temp; temp = REG32(EAX); REG32(EAX) = REG32(EDX); REG32(EDX) = temp; - CYCLES(CYCLES_XCHG_REG_REG); + CYCLES(cpustate,CYCLES_XCHG_REG_REG); } -static void I386OP(xchg_eax_ebx)(void) // Opcode 0x93 +static void I386OP(xchg_eax_ebx)(i386_state *cpustate) // Opcode 0x93 { UINT32 temp; temp = REG32(EAX); REG32(EAX) = REG32(EBX); REG32(EBX) = temp; - CYCLES(CYCLES_XCHG_REG_REG); + CYCLES(cpustate,CYCLES_XCHG_REG_REG); } -static void I386OP(xchg_eax_esp)(void) // Opcode 0x94 +static void I386OP(xchg_eax_esp)(i386_state *cpustate) // Opcode 0x94 { UINT32 temp; temp = REG32(EAX); REG32(EAX) = REG32(ESP); REG32(ESP) = temp; - CYCLES(CYCLES_XCHG_REG_REG); + CYCLES(cpustate,CYCLES_XCHG_REG_REG); } -static void I386OP(xchg_eax_ebp)(void) // Opcode 0x95 +static void I386OP(xchg_eax_ebp)(i386_state *cpustate) // Opcode 0x95 { UINT32 temp; temp = REG32(EAX); REG32(EAX) = REG32(EBP); REG32(EBP) = temp; - CYCLES(CYCLES_XCHG_REG_REG); + CYCLES(cpustate,CYCLES_XCHG_REG_REG); } -static void I386OP(xchg_eax_esi)(void) // Opcode 0x96 +static void I386OP(xchg_eax_esi)(i386_state *cpustate) // Opcode 0x96 { UINT32 temp; temp = REG32(EAX); REG32(EAX) = REG32(ESI); REG32(ESI) = temp; - CYCLES(CYCLES_XCHG_REG_REG); + CYCLES(cpustate,CYCLES_XCHG_REG_REG); } -static void I386OP(xchg_eax_edi)(void) // Opcode 0x97 +static void I386OP(xchg_eax_edi)(i386_state *cpustate) // Opcode 0x97 { UINT32 temp; temp = REG32(EAX); REG32(EAX) = REG32(EDI); REG32(EDI) = temp; - CYCLES(CYCLES_XCHG_REG_REG); + CYCLES(cpustate,CYCLES_XCHG_REG_REG); } -static void I386OP(xchg_r32_rm32)(void) // Opcode 0x87 +static void I386OP(xchg_r32_rm32)(i386_state *cpustate) // Opcode 0x87 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT32 src = LOAD_RM32(modrm); UINT32 dst = LOAD_REG32(modrm); STORE_REG32(modrm, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_XCHG_REG_REG); + CYCLES(cpustate,CYCLES_XCHG_REG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 src = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 src = READ32(cpustate,ea); UINT32 dst = LOAD_REG32(modrm); STORE_REG32(modrm, src); - WRITE32(ea, dst); - CYCLES(CYCLES_XCHG_REG_MEM); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_XCHG_REG_MEM); } } -static void I386OP(xor_rm32_r32)(void) // Opcode 0x31 +static void I386OP(xor_rm32_r32)(i386_state *cpustate) // Opcode 0x31 { UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG32(modrm); dst = LOAD_RM32(modrm); - dst = XOR32(dst, src); + dst = XOR32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG32(modrm); - dst = READ32(ea); - dst = XOR32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + dst = READ32(cpustate,ea); + dst = XOR32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(xor_r32_rm32)(void) // Opcode 0x33 +static void I386OP(xor_r32_rm32)(i386_state *cpustate) // Opcode 0x33 { UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM32(modrm); dst = LOAD_REG32(modrm); - dst = XOR32(dst, src); + dst = XOR32(cpustate,dst, src); STORE_REG32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ32(cpustate,ea); dst = LOAD_REG32(modrm); - dst = XOR32(dst, src); + dst = XOR32(cpustate,dst, src); STORE_REG32(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(xor_eax_i32)(void) // Opcode 0x35 +static void I386OP(xor_eax_i32)(i386_state *cpustate) // Opcode 0x35 { UINT32 src, dst; - src = FETCH32(); + src = FETCH32(cpustate); dst = REG32(EAX); - dst = XOR32(dst, src); + dst = XOR32(cpustate,dst, src); REG32(EAX) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(group81_32)(void) // Opcode 0x81 +static void I386OP(group81_32)(i386_state *cpustate) // Opcode 0x81 { UINT32 ea; UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); switch( (modrm >> 3) & 0x7 ) { case 0: // ADD Rm32, i32 if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - src = FETCH32(); - dst = ADD32(dst, src); + src = FETCH32(cpustate); + dst = ADD32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ32(ea); - src = FETCH32(); - dst = ADD32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + src = FETCH32(cpustate); + dst = ADD32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 1: // OR Rm32, i32 if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - src = FETCH32(); - dst = OR32(dst, src); + src = FETCH32(cpustate); + dst = OR32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ32(ea); - src = FETCH32(); - dst = OR32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + src = FETCH32(cpustate); + dst = OR32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 2: // ADC Rm32, i32 if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - src = FETCH32(); - src = ADD32(src, I.CF); - dst = ADD32(dst, src); + src = FETCH32(cpustate); + src = ADD32(cpustate,src, cpustate->CF); + dst = ADD32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ32(ea); - src = FETCH32(); - src = ADD32(src, I.CF); - dst = ADD32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + src = FETCH32(cpustate); + src = ADD32(cpustate,src, cpustate->CF); + dst = ADD32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 3: // SBB Rm32, i32 if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - src = FETCH32() + I.CF; - dst = SUB32(dst, src); + src = FETCH32(cpustate) + cpustate->CF; + dst = SUB32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ32(ea); - src = FETCH32() + I.CF; - dst = SUB32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + src = FETCH32(cpustate) + cpustate->CF; + dst = SUB32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 4: // AND Rm32, i32 if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - src = FETCH32(); - dst = AND32(dst, src); + src = FETCH32(cpustate); + dst = AND32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ32(ea); - src = FETCH32(); - dst = AND32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + src = FETCH32(cpustate); + dst = AND32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 5: // SUB Rm32, i32 if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - src = FETCH32(); - dst = SUB32(dst, src); + src = FETCH32(cpustate); + dst = SUB32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ32(ea); - src = FETCH32(); - dst = SUB32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + src = FETCH32(cpustate); + dst = SUB32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 6: // XOR Rm32, i32 if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - src = FETCH32(); - dst = XOR32(dst, src); + src = FETCH32(cpustate); + dst = XOR32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ32(ea); - src = FETCH32(); - dst = XOR32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + src = FETCH32(cpustate); + dst = XOR32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 7: // CMP Rm32, i32 if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - src = FETCH32(); - SUB32(dst, src); - CYCLES(CYCLES_CMP_REG_REG); + src = FETCH32(cpustate); + SUB32(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_REG); } else { - ea = GetEA(modrm); - dst = READ32(ea); - src = FETCH32(); - SUB32(dst, src); - CYCLES(CYCLES_CMP_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + src = FETCH32(cpustate); + SUB32(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_MEM); } break; } } -static void I386OP(group83_32)(void) // Opcode 0x83 +static void I386OP(group83_32)(i386_state *cpustate) // Opcode 0x83 { UINT32 ea; UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); switch( (modrm >> 3) & 0x7 ) { case 0: // ADD Rm32, i32 if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - src = (UINT32)(INT32)(INT8)FETCH(); - dst = ADD32(dst, src); + src = (UINT32)(INT32)(INT8)FETCH(cpustate); + dst = ADD32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ32(ea); - src = (UINT32)(INT32)(INT8)FETCH(); - dst = ADD32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + src = (UINT32)(INT32)(INT8)FETCH(cpustate); + dst = ADD32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 1: // OR Rm32, i32 if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - src = (UINT32)(INT32)(INT8)FETCH(); - dst = OR32(dst, src); + src = (UINT32)(INT32)(INT8)FETCH(cpustate); + dst = OR32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ32(ea); - src = (UINT32)(INT32)(INT8)FETCH(); - dst = OR32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + src = (UINT32)(INT32)(INT8)FETCH(cpustate); + dst = OR32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 2: // ADC Rm32, i32 if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - src = (UINT32)(INT32)(INT8)FETCH(); - src = ADD32(src, I.CF); - dst = ADD32(dst, src); + src = (UINT32)(INT32)(INT8)FETCH(cpustate); + src = ADD32(cpustate,src, cpustate->CF); + dst = ADD32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ32(ea); - src = (UINT32)(INT32)(INT8)FETCH(); - src = ADD32(src, I.CF); - dst = ADD32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + src = (UINT32)(INT32)(INT8)FETCH(cpustate); + src = ADD32(cpustate,src, cpustate->CF); + dst = ADD32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 3: // SBB Rm32, i32 if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - src = ((UINT32)(INT32)(INT8)FETCH()) + I.CF; - dst = SUB32(dst, src); + src = ((UINT32)(INT32)(INT8)FETCH(cpustate)) + cpustate->CF; + dst = SUB32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ32(ea); - src = ((UINT32)(INT32)(INT8)FETCH()) + I.CF; - dst = SUB32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + src = ((UINT32)(INT32)(INT8)FETCH(cpustate)) + cpustate->CF; + dst = SUB32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 4: // AND Rm32, i32 if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - src = (UINT32)(INT32)(INT8)FETCH(); - dst = AND32(dst, src); + src = (UINT32)(INT32)(INT8)FETCH(cpustate); + dst = AND32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ32(ea); - src = (UINT32)(INT32)(INT8)FETCH(); - dst = AND32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + src = (UINT32)(INT32)(INT8)FETCH(cpustate); + dst = AND32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 5: // SUB Rm32, i32 if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - src = (UINT32)(INT32)(INT8)FETCH(); - dst = SUB32(dst, src); + src = (UINT32)(INT32)(INT8)FETCH(cpustate); + dst = SUB32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ32(ea); - src = (UINT32)(INT32)(INT8)FETCH(); - dst = SUB32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + src = (UINT32)(INT32)(INT8)FETCH(cpustate); + dst = SUB32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 6: // XOR Rm32, i32 if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - src = (UINT32)(INT32)(INT8)FETCH(); - dst = XOR32(dst, src); + src = (UINT32)(INT32)(INT8)FETCH(cpustate); + dst = XOR32(cpustate,dst, src); STORE_RM32(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ32(ea); - src = (UINT32)(INT32)(INT8)FETCH(); - dst = XOR32(dst, src); - WRITE32(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + src = (UINT32)(INT32)(INT8)FETCH(cpustate); + dst = XOR32(cpustate,dst, src); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 7: // CMP Rm32, i32 if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - src = (UINT32)(INT32)(INT8)FETCH(); - SUB32(dst, src); - CYCLES(CYCLES_CMP_REG_REG); + src = (UINT32)(INT32)(INT8)FETCH(cpustate); + SUB32(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_REG); } else { - ea = GetEA(modrm); - dst = READ32(ea); - src = (UINT32)(INT32)(INT8)FETCH(); - SUB32(dst, src); - CYCLES(CYCLES_CMP_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + src = (UINT32)(INT32)(INT8)FETCH(cpustate); + SUB32(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_MEM); } break; } } -static void I386OP(groupC1_32)(void) // Opcode 0xc1 +static void I386OP(groupC1_32)(i386_state *cpustate) // Opcode 0xc1 { UINT32 dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 shift; if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - shift = FETCH() & 0x1f; - dst = i386_shift_rotate32(modrm, dst, shift); + shift = FETCH(cpustate) & 0x1f; + dst = i386_shift_rotate32(cpustate, modrm, dst, shift); STORE_RM32(modrm, dst); } else { - UINT32 ea = GetEA(modrm); - dst = READ32(ea); - shift = FETCH() & 0x1f; - dst = i386_shift_rotate32(modrm, dst, shift); - WRITE32(ea, dst); + UINT32 ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + shift = FETCH(cpustate) & 0x1f; + dst = i386_shift_rotate32(cpustate, modrm, dst, shift); + WRITE32(cpustate,ea, dst); } } -static void I386OP(groupD1_32)(void) // Opcode 0xd1 +static void I386OP(groupD1_32)(i386_state *cpustate) // Opcode 0xd1 { UINT32 dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - dst = i386_shift_rotate32(modrm, dst, 1); + dst = i386_shift_rotate32(cpustate, modrm, dst, 1); STORE_RM32(modrm, dst); } else { - UINT32 ea = GetEA(modrm); - dst = READ32(ea); - dst = i386_shift_rotate32(modrm, dst, 1); - WRITE32(ea, dst); + UINT32 ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + dst = i386_shift_rotate32(cpustate, modrm, dst, 1); + WRITE32(cpustate,ea, dst); } } -static void I386OP(groupD3_32)(void) // Opcode 0xd3 +static void I386OP(groupD3_32)(i386_state *cpustate) // Opcode 0xd3 { UINT32 dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { dst = LOAD_RM32(modrm); - dst = i386_shift_rotate32(modrm, dst, REG8(CL)); + dst = i386_shift_rotate32(cpustate, modrm, dst, REG8(CL)); STORE_RM32(modrm, dst); } else { - UINT32 ea = GetEA(modrm); - dst = READ32(ea); - dst = i386_shift_rotate32(modrm, dst, REG8(CL)); - WRITE32(ea, dst); + UINT32 ea = GetEA(cpustate,modrm); + dst = READ32(cpustate,ea); + dst = i386_shift_rotate32(cpustate, modrm, dst, REG8(CL)); + WRITE32(cpustate,ea, dst); } } -static void I386OP(groupF7_32)(void) // Opcode 0xf7 +static void I386OP(groupF7_32)(i386_state *cpustate) // Opcode 0xf7 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); switch( (modrm >> 3) & 0x7 ) { case 0: /* TEST Rm32, i32 */ if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); - UINT32 src = FETCH32(); + UINT32 src = FETCH32(cpustate); dst &= src; - I.CF = I.OF = I.AF = 0; + cpustate->CF = cpustate->OF = cpustate->AF = 0; SetSZPF32(dst); - CYCLES(CYCLES_TEST_IMM_REG); + CYCLES(cpustate,CYCLES_TEST_IMM_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); - UINT32 src = FETCH32(); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); + UINT32 src = FETCH32(cpustate); dst &= src; - I.CF = I.OF = I.AF = 0; + cpustate->CF = cpustate->OF = cpustate->AF = 0; SetSZPF32(dst); - CYCLES(CYCLES_TEST_IMM_MEM); + CYCLES(cpustate,CYCLES_TEST_IMM_MEM); } break; case 2: /* NOT Rm32 */ @@ -2376,27 +2376,27 @@ static void I386OP(groupF7_32)(void) // Opcode 0xf7 UINT32 dst = LOAD_RM32(modrm); dst = ~dst; STORE_RM32(modrm, dst); - CYCLES(CYCLES_NOT_REG); + CYCLES(cpustate,CYCLES_NOT_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); dst = ~dst; - WRITE32(ea, dst); - CYCLES(CYCLES_NOT_MEM); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_NOT_MEM); } break; case 3: /* NEG Rm32 */ if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); - dst = SUB32( 0, dst ); + dst = SUB32(cpustate, 0, dst ); STORE_RM32(modrm, dst); - CYCLES(CYCLES_NEG_REG); + CYCLES(cpustate,CYCLES_NEG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); - dst = SUB32( 0, dst ); - WRITE32(ea, dst); - CYCLES(CYCLES_NEG_MEM); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); + dst = SUB32(cpustate, 0, dst ); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_NEG_MEM); } break; case 4: /* MUL EAX, Rm32 */ @@ -2405,11 +2405,11 @@ static void I386OP(groupF7_32)(void) // Opcode 0xf7 UINT32 src, dst; if( modrm >= 0xc0 ) { src = LOAD_RM32(modrm); - CYCLES(CYCLES_MUL32_ACC_REG); /* TODO: Correct multiply timing */ + CYCLES(cpustate,CYCLES_MUL32_ACC_REG); /* TODO: Correct multiply timing */ } else { - UINT32 ea = GetEA(modrm); - src = READ32(ea); - CYCLES(CYCLES_MUL32_ACC_MEM); /* TODO: Correct multiply timing */ + UINT32 ea = GetEA(cpustate,modrm); + src = READ32(cpustate,ea); + CYCLES(cpustate,CYCLES_MUL32_ACC_MEM); /* TODO: Correct multiply timing */ } dst = REG32(EAX); @@ -2417,7 +2417,7 @@ static void I386OP(groupF7_32)(void) // Opcode 0xf7 REG32(EDX) = (UINT32)(result >> 32); REG32(EAX) = (UINT32)result; - I.CF = I.OF = (REG32(EDX) != 0); + cpustate->CF = cpustate->OF = (REG32(EDX) != 0); } break; case 5: /* IMUL EAX, Rm32 */ @@ -2426,11 +2426,11 @@ static void I386OP(groupF7_32)(void) // Opcode 0xf7 INT64 src, dst; if( modrm >= 0xc0 ) { src = (INT64)(INT32)LOAD_RM32(modrm); - CYCLES(CYCLES_IMUL32_ACC_REG); /* TODO: Correct multiply timing */ + CYCLES(cpustate,CYCLES_IMUL32_ACC_REG); /* TODO: Correct multiply timing */ } else { - UINT32 ea = GetEA(modrm); - src = (INT64)(INT32)READ32(ea); - CYCLES(CYCLES_IMUL32_ACC_MEM); /* TODO: Correct multiply timing */ + UINT32 ea = GetEA(cpustate,modrm); + src = (INT64)(INT32)READ32(cpustate,ea); + CYCLES(cpustate,CYCLES_IMUL32_ACC_MEM); /* TODO: Correct multiply timing */ } dst = (INT64)(INT32)REG32(EAX); @@ -2439,7 +2439,7 @@ static void I386OP(groupF7_32)(void) // Opcode 0xf7 REG32(EDX) = (UINT32)(result >> 32); REG32(EAX) = (UINT32)result; - I.CF = I.OF = !(result == (INT64)(INT32)result); + cpustate->CF = cpustate->OF = !(result == (INT64)(INT32)result); } break; case 6: /* DIV EAX, Rm32 */ @@ -2448,11 +2448,11 @@ static void I386OP(groupF7_32)(void) // Opcode 0xf7 UINT32 src; if( modrm >= 0xc0 ) { src = LOAD_RM32(modrm); - CYCLES(CYCLES_DIV32_ACC_REG); + CYCLES(cpustate,CYCLES_DIV32_ACC_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ32(ea); - CYCLES(CYCLES_DIV32_ACC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + src = READ32(cpustate,ea); + CYCLES(cpustate,CYCLES_DIV32_ACC_MEM); } quotient = ((UINT64)(REG32(EDX)) << 32) | (UINT64)(REG32(EAX)); @@ -2476,11 +2476,11 @@ static void I386OP(groupF7_32)(void) // Opcode 0xf7 UINT32 src; if( modrm >= 0xc0 ) { src = LOAD_RM32(modrm); - CYCLES(CYCLES_IDIV32_ACC_REG); + CYCLES(cpustate,CYCLES_IDIV32_ACC_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ32(ea); - CYCLES(CYCLES_IDIV32_ACC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + src = READ32(cpustate,ea); + CYCLES(cpustate,CYCLES_IDIV32_ACC_MEM); } quotient = (((INT64)REG32(EDX)) << 32) | ((UINT64)REG32(EAX)); @@ -2501,38 +2501,38 @@ static void I386OP(groupF7_32)(void) // Opcode 0xf7 } } -static void I386OP(groupFF_32)(void) // Opcode 0xff +static void I386OP(groupFF_32)(i386_state *cpustate) // Opcode 0xff { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); switch( (modrm >> 3) & 0x7 ) { case 0: /* INC Rm32 */ if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); - dst = INC32(dst); + dst = INC32(cpustate,dst); STORE_RM32(modrm, dst); - CYCLES(CYCLES_INC_REG); + CYCLES(cpustate,CYCLES_INC_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); - dst = INC32(dst); - WRITE32(ea, dst); - CYCLES(CYCLES_INC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); + dst = INC32(cpustate,dst); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_INC_MEM); } break; case 1: /* DEC Rm32 */ if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); - dst = DEC32(dst); + dst = DEC32(cpustate,dst); STORE_RM32(modrm, dst); - CYCLES(CYCLES_DEC_REG); + CYCLES(cpustate,CYCLES_DEC_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); - dst = DEC32(dst); - WRITE32(ea, dst); - CYCLES(CYCLES_DEC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); + dst = DEC32(cpustate,dst); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_DEC_MEM); } break; case 2: /* CALL Rm32 */ @@ -2540,15 +2540,15 @@ static void I386OP(groupFF_32)(void) // Opcode 0xff UINT32 address; if( modrm >= 0xc0 ) { address = LOAD_RM32(modrm); - CYCLES(CYCLES_CALL_REG); /* TODO: Timing = 7 + m */ + CYCLES(cpustate,CYCLES_CALL_REG); /* TODO: Timing = 7 + m */ } else { - UINT32 ea = GetEA(modrm); - address = READ32(ea); - CYCLES(CYCLES_CALL_MEM); /* TODO: Timing = 10 + m */ + UINT32 ea = GetEA(cpustate,modrm); + address = READ32(cpustate,ea); + CYCLES(cpustate,CYCLES_CALL_MEM); /* TODO: Timing = 10 + m */ } - PUSH32( I.eip ); - I.eip = address; - CHANGE_PC(I.eip); + PUSH32(cpustate, cpustate->eip ); + cpustate->eip = address; + CHANGE_PC(cpustate,cpustate->eip); } break; case 3: /* CALL FAR Rm32 */ @@ -2558,18 +2558,18 @@ static void I386OP(groupFF_32)(void) // Opcode 0xff if( modrm >= 0xc0 ) { fatalerror("NYI"); } else { - UINT32 ea = GetEA(modrm); - address = READ32(ea + 0); - selector = READ16(ea + 4); - CYCLES(CYCLES_CALL_MEM_INTERSEG); /* TODO: Timing = 10 + m */ + UINT32 ea = GetEA(cpustate,modrm); + address = READ32(cpustate,ea + 0); + selector = READ16(cpustate,ea + 4); + CYCLES(cpustate,CYCLES_CALL_MEM_INTERSEG); /* TODO: Timing = 10 + m */ } - PUSH32( I.sreg[CS].selector ); - PUSH32( I.eip ); - I.sreg[CS].selector = selector; - I.performed_intersegment_jump = 1; - i386_load_segment_descriptor( CS ); - I.eip = address; - CHANGE_PC(I.eip); + PUSH32(cpustate, cpustate->sreg[CS].selector ); + PUSH32(cpustate, cpustate->eip ); + cpustate->sreg[CS].selector = selector; + cpustate->performed_intersegment_jump = 1; + i386_load_segment_descriptor(cpustate, CS ); + cpustate->eip = address; + CHANGE_PC(cpustate,cpustate->eip); } break; case 4: /* JMP Rm32 */ @@ -2577,14 +2577,14 @@ static void I386OP(groupFF_32)(void) // Opcode 0xff UINT32 address; if( modrm >= 0xc0 ) { address = LOAD_RM32(modrm); - CYCLES(CYCLES_JMP_REG); /* TODO: Timing = 7 + m */ + CYCLES(cpustate,CYCLES_JMP_REG); /* TODO: Timing = 7 + m */ } else { - UINT32 ea = GetEA(modrm); - address = READ32(ea); - CYCLES(CYCLES_JMP_MEM); /* TODO: Timing = 10 + m */ + UINT32 ea = GetEA(cpustate,modrm); + address = READ32(cpustate,ea); + CYCLES(cpustate,CYCLES_JMP_MEM); /* TODO: Timing = 10 + m */ } - I.eip = address; - CHANGE_PC(I.eip); + cpustate->eip = address; + CHANGE_PC(cpustate,cpustate->eip); } break; case 5: /* JMP FAR Rm32 */ @@ -2594,16 +2594,16 @@ static void I386OP(groupFF_32)(void) // Opcode 0xff if( modrm >= 0xc0 ) { fatalerror("NYI"); } else { - UINT32 ea = GetEA(modrm); - address = READ32(ea + 0); - selector = READ16(ea + 4); - CYCLES(CYCLES_JMP_MEM_INTERSEG); /* TODO: Timing = 10 + m */ + UINT32 ea = GetEA(cpustate,modrm); + address = READ32(cpustate,ea + 0); + selector = READ16(cpustate,ea + 4); + CYCLES(cpustate,CYCLES_JMP_MEM_INTERSEG); /* TODO: Timing = 10 + m */ } - I.sreg[CS].selector = selector; - I.performed_intersegment_jump = 1; - i386_load_segment_descriptor( CS ); - I.eip = address; - CHANGE_PC(I.eip); + cpustate->sreg[CS].selector = selector; + cpustate->performed_intersegment_jump = 1; + i386_load_segment_descriptor(cpustate, CS ); + cpustate->eip = address; + CHANGE_PC(cpustate,cpustate->eip); } break; case 6: /* PUSH Rm32 */ @@ -2612,23 +2612,23 @@ static void I386OP(groupFF_32)(void) // Opcode 0xff if( modrm >= 0xc0 ) { value = LOAD_RM32(modrm); } else { - UINT32 ea = GetEA(modrm); - value = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + value = READ32(cpustate,ea); } - PUSH32(value); - CYCLES(CYCLES_PUSH_RM); + PUSH32(cpustate,value); + CYCLES(cpustate,CYCLES_PUSH_RM); } break; default: - fatalerror("i386: groupFF_32 /%d unimplemented at %08X", (modrm >> 3) & 0x7, I.pc-2); + fatalerror("i386: groupFF_32 /%d unimplemented at %08X", (modrm >> 3) & 0x7, cpustate->pc-2); break; } } -static void I386OP(group0F00_32)(void) // Opcode 0x0f 00 +static void I386OP(group0F00_32)(i386_state *cpustate) // Opcode 0x0f 00 { UINT32 address, ea; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); switch( (modrm >> 3) & 0x7 ) { @@ -2637,17 +2637,17 @@ static void I386OP(group0F00_32)(void) // Opcode 0x0f 00 { if( modrm >= 0xc0 ) { address = LOAD_RM32(modrm); - ea = i386_translate( CS, address ); - CYCLES(CYCLES_LLDT_REG); + ea = i386_translate(cpustate, CS, address ); + CYCLES(cpustate,CYCLES_LLDT_REG); } else { - ea = GetEA(modrm); - CYCLES(CYCLES_LLDT_MEM); + ea = GetEA(cpustate,modrm); + CYCLES(cpustate,CYCLES_LLDT_MEM); } - I.ldtr.segment = READ32(ea); + cpustate->ldtr.segment = READ32(cpustate,ea); } else { - i386_trap(6, 0); + i386_trap(cpustate,6, 0); } break; @@ -2656,17 +2656,17 @@ static void I386OP(group0F00_32)(void) // Opcode 0x0f 00 { if( modrm >= 0xc0 ) { address = LOAD_RM32(modrm); - ea = i386_translate( CS, address ); - CYCLES(CYCLES_LTR_REG); + ea = i386_translate(cpustate, CS, address ); + CYCLES(cpustate,CYCLES_LTR_REG); } else { - ea = GetEA(modrm); - CYCLES(CYCLES_LTR_MEM); + ea = GetEA(cpustate,modrm); + CYCLES(cpustate,CYCLES_LTR_MEM); } - I.task.segment = READ32(ea); + cpustate->task.segment = READ32(cpustate,ea); } else { - i386_trap(6, 0); + i386_trap(cpustate,6, 0); } break; @@ -2676,9 +2676,9 @@ static void I386OP(group0F00_32)(void) // Opcode 0x0f 00 } } -static void I386OP(group0F01_32)(void) // Opcode 0x0f 01 +static void I386OP(group0F01_32)(i386_state *cpustate) // Opcode 0x0f 01 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT32 address, ea; switch( (modrm >> 3) & 0x7 ) @@ -2687,13 +2687,13 @@ static void I386OP(group0F01_32)(void) // Opcode 0x0f 01 { if( modrm >= 0xc0 ) { address = LOAD_RM32(modrm); - ea = i386_translate( CS, address ); + ea = i386_translate(cpustate, CS, address ); } else { - ea = GetEA(modrm); + ea = GetEA(cpustate,modrm); } - WRITE16(ea, I.gdtr.limit); - WRITE32(ea + 2, I.gdtr.base); - CYCLES(CYCLES_SGDT); + WRITE16(cpustate,ea, cpustate->gdtr.limit); + WRITE32(cpustate,ea + 2, cpustate->gdtr.base); + CYCLES(cpustate,CYCLES_SGDT); break; } case 1: /* SIDT */ @@ -2701,161 +2701,161 @@ static void I386OP(group0F01_32)(void) // Opcode 0x0f 01 if (modrm >= 0xc0) { address = LOAD_RM32(modrm); - ea = i386_translate( CS, address ); + ea = i386_translate(cpustate, CS, address ); } else { - ea = GetEA(modrm); + ea = GetEA(cpustate,modrm); } - WRITE16(ea, I.idtr.limit); - WRITE32(ea + 2, I.idtr.base); - CYCLES(CYCLES_SIDT); + WRITE16(cpustate,ea, cpustate->idtr.limit); + WRITE32(cpustate,ea + 2, cpustate->idtr.base); + CYCLES(cpustate,CYCLES_SIDT); break; } case 2: /* LGDT */ { if( modrm >= 0xc0 ) { address = LOAD_RM32(modrm); - ea = i386_translate( CS, address ); + ea = i386_translate(cpustate, CS, address ); } else { - ea = GetEA(modrm); + ea = GetEA(cpustate,modrm); } - I.gdtr.limit = READ16(ea); - I.gdtr.base = READ32(ea + 2); - CYCLES(CYCLES_LGDT); + cpustate->gdtr.limit = READ16(cpustate,ea); + cpustate->gdtr.base = READ32(cpustate,ea + 2); + CYCLES(cpustate,CYCLES_LGDT); break; } case 3: /* LIDT */ { if( modrm >= 0xc0 ) { address = LOAD_RM32(modrm); - ea = i386_translate( CS, address ); + ea = i386_translate(cpustate, CS, address ); } else { - ea = GetEA(modrm); + ea = GetEA(cpustate,modrm); } - I.idtr.limit = READ16(ea); - I.idtr.base = READ32(ea + 2); - CYCLES(CYCLES_LIDT); + cpustate->idtr.limit = READ16(cpustate,ea); + cpustate->idtr.base = READ32(cpustate,ea + 2); + CYCLES(cpustate,CYCLES_LIDT); break; } default: - fatalerror("i386: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, I.eip - 2); + fatalerror("i386: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, cpustate->eip - 2); break; } } -static void I386OP(group0FBA_32)(void) // Opcode 0x0f ba +static void I386OP(group0FBA_32)(i386_state *cpustate) // Opcode 0x0f ba { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); switch( (modrm >> 3) & 0x7 ) { case 4: /* BT Rm32, i8 */ if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); - UINT8 bit = FETCH(); + UINT8 bit = FETCH(cpustate); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; - CYCLES(CYCLES_BT_IMM_REG); + CYCLES(cpustate,CYCLES_BT_IMM_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); - UINT8 bit = FETCH(); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); + UINT8 bit = FETCH(cpustate); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; - CYCLES(CYCLES_BT_IMM_MEM); + CYCLES(cpustate,CYCLES_BT_IMM_MEM); } break; case 5: /* BTS Rm32, i8 */ if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); - UINT8 bit = FETCH(); + UINT8 bit = FETCH(cpustate); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst |= (1 << bit); STORE_RM32(modrm, dst); - CYCLES(CYCLES_BTS_IMM_REG); + CYCLES(cpustate,CYCLES_BTS_IMM_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); - UINT8 bit = FETCH(); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); + UINT8 bit = FETCH(cpustate); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst |= (1 << bit); - WRITE32(ea, dst); - CYCLES(CYCLES_BTS_IMM_MEM); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_BTS_IMM_MEM); } break; case 6: /* BTR Rm32, i8 */ if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); - UINT8 bit = FETCH(); + UINT8 bit = FETCH(cpustate); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst &= ~(1 << bit); STORE_RM32(modrm, dst); - CYCLES(CYCLES_BTR_IMM_REG); + CYCLES(cpustate,CYCLES_BTR_IMM_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); - UINT8 bit = FETCH(); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); + UINT8 bit = FETCH(cpustate); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst &= ~(1 << bit); - WRITE32(ea, dst); - CYCLES(CYCLES_BTR_IMM_MEM); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_BTR_IMM_MEM); } break; case 7: /* BTC Rm32, i8 */ if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); - UINT8 bit = FETCH(); + UINT8 bit = FETCH(cpustate); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst ^= (1 << bit); STORE_RM32(modrm, dst); - CYCLES(CYCLES_BTC_IMM_REG); + CYCLES(cpustate,CYCLES_BTC_IMM_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); - UINT8 bit = FETCH(); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); + UINT8 bit = FETCH(cpustate); if( dst & (1 << bit) ) - I.CF = 1; + cpustate->CF = 1; else - I.CF = 0; + cpustate->CF = 0; dst ^= (1 << bit); - WRITE32(ea, dst); - CYCLES(CYCLES_BTC_IMM_MEM); + WRITE32(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_BTC_IMM_MEM); } break; default: @@ -2864,12 +2864,12 @@ static void I386OP(group0FBA_32)(void) // Opcode 0x0f ba } } -static void I386OP(bound_r32_m32_m32)(void) // Opcode 0x62 +static void I386OP(bound_r32_m32_m32)(i386_state *cpustate) // Opcode 0x62 { UINT8 modrm; INT32 val, low, high; - modrm = FETCH(); + modrm = FETCH(cpustate); if (modrm >= 0xc0) { @@ -2877,98 +2877,98 @@ static void I386OP(bound_r32_m32_m32)(void) // Opcode 0x62 } else { - UINT32 ea = GetEA(modrm); - low = READ32(ea + 0); - high = READ32(ea + 4); + UINT32 ea = GetEA(cpustate,modrm); + low = READ32(cpustate,ea + 0); + high = READ32(cpustate,ea + 4); } val = LOAD_REG32(modrm); if ((val < low) || (val > high)) { - CYCLES(CYCLES_BOUND_OUT_RANGE); - i386_trap(5, 0); + CYCLES(cpustate,CYCLES_BOUND_OUT_RANGE); + i386_trap(cpustate,5, 0); } else { - CYCLES(CYCLES_BOUND_IN_RANGE); + CYCLES(cpustate,CYCLES_BOUND_IN_RANGE); } } -static void I386OP(retf32)(void) // Opcode 0xcb +static void I386OP(retf32)(i386_state *cpustate) // Opcode 0xcb { - I.eip = POP32(); - I.sreg[CS].selector = POP32(); - i386_load_segment_descriptor( CS ); - CHANGE_PC(I.eip); + cpustate->eip = POP32(cpustate); + cpustate->sreg[CS].selector = POP32(cpustate); + i386_load_segment_descriptor(cpustate, CS ); + CHANGE_PC(cpustate,cpustate->eip); - CYCLES(CYCLES_RET_INTERSEG); + CYCLES(cpustate,CYCLES_RET_INTERSEG); } -static void I386OP(retf_i32)(void) // Opcode 0xca +static void I386OP(retf_i32)(i386_state *cpustate) // Opcode 0xca { - UINT16 count = FETCH16(); + UINT16 count = FETCH16(cpustate); - I.eip = POP32(); - I.sreg[CS].selector = POP32(); - i386_load_segment_descriptor( CS ); - CHANGE_PC(I.eip); + cpustate->eip = POP32(cpustate); + cpustate->sreg[CS].selector = POP32(cpustate); + i386_load_segment_descriptor(cpustate, CS ); + CHANGE_PC(cpustate,cpustate->eip); REG32(ESP) += count; - CYCLES(CYCLES_RET_IMM_INTERSEG); + CYCLES(cpustate,CYCLES_RET_IMM_INTERSEG); } -static void I386OP(xlat32)(void) // Opcode 0xd7 +static void I386OP(xlat32)(i386_state *cpustate) // Opcode 0xd7 { UINT32 ea; - if( I.segment_prefix ) { - ea = i386_translate( I.segment_override, REG32(EBX) + REG8(AL) ); + if( cpustate->segment_prefix ) { + ea = i386_translate(cpustate, cpustate->segment_override, REG32(EBX) + REG8(AL) ); } else { - ea = i386_translate( DS, REG32(EBX) + REG8(AL) ); + ea = i386_translate(cpustate, DS, REG32(EBX) + REG8(AL) ); } - REG8(AL) = READ8(ea); - CYCLES(CYCLES_XLAT); + REG8(AL) = READ8(cpustate,ea); + CYCLES(cpustate,CYCLES_XLAT); } -static void I386OP(load_far_pointer32)(int s) +static void I386OP(load_far_pointer32)(i386_state *cpustate, int s) { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { fatalerror("NYI"); } else { - UINT32 ea = GetEA(modrm); - STORE_REG32(modrm, READ32(ea + 0)); - I.sreg[s].selector = READ16(ea + 4); - i386_load_segment_descriptor( s ); + UINT32 ea = GetEA(cpustate,modrm); + STORE_REG32(modrm, READ32(cpustate,ea + 0)); + cpustate->sreg[s].selector = READ16(cpustate,ea + 4); + i386_load_segment_descriptor(cpustate, s ); } } -static void I386OP(lds32)(void) // Opcode 0xc5 +static void I386OP(lds32)(i386_state *cpustate) // Opcode 0xc5 { - I386OP(load_far_pointer32)(DS); - CYCLES(CYCLES_LDS); + I386OP(load_far_pointer32)(cpustate, DS); + CYCLES(cpustate,CYCLES_LDS); } -static void I386OP(lss32)(void) // Opcode 0x0f 0xb2 +static void I386OP(lss32)(i386_state *cpustate) // Opcode 0x0f 0xb2 { - I386OP(load_far_pointer32)(SS); - CYCLES(CYCLES_LSS); + I386OP(load_far_pointer32)(cpustate, SS); + CYCLES(cpustate,CYCLES_LSS); } -static void I386OP(les32)(void) // Opcode 0xc4 +static void I386OP(les32)(i386_state *cpustate) // Opcode 0xc4 { - I386OP(load_far_pointer16)(ES); - CYCLES(CYCLES_LES); + I386OP(load_far_pointer32)(cpustate, ES); + CYCLES(cpustate,CYCLES_LES); } -static void I386OP(lfs32)(void) // Opcode 0x0f 0xb4 +static void I386OP(lfs32)(i386_state *cpustate) // Opcode 0x0f 0xb4 { - I386OP(load_far_pointer16)(FS); - CYCLES(CYCLES_LFS); + I386OP(load_far_pointer32)(cpustate, FS); + CYCLES(cpustate,CYCLES_LFS); } -static void I386OP(lgs32)(void) // Opcode 0x0f 0xb5 +static void I386OP(lgs32)(i386_state *cpustate) // Opcode 0x0f 0xb5 { - I386OP(load_far_pointer32)(GS); - CYCLES(CYCLES_LGS); + I386OP(load_far_pointer32)(cpustate, GS); + CYCLES(cpustate,CYCLES_LGS); } diff --git a/src/emu/cpu/i386/i386ops.c b/src/emu/cpu/i386/i386ops.c index 8a98897e91f..8bc232d58d7 100644 --- a/src/emu/cpu/i386/i386ops.c +++ b/src/emu/cpu/i386/i386ops.c @@ -1,59 +1,59 @@ -static UINT8 I386OP(shift_rotate8)(UINT8 modrm, UINT32 value, UINT8 shift) +static UINT8 I386OP(shift_rotate8)(i386_state *cpustate, UINT8 modrm, UINT32 value, UINT8 shift) { UINT8 src = value; UINT8 dst = value; if( shift == 0 ) { - CYCLES_RM(modrm, 3, 7); + CYCLES_RM(cpustate,modrm, 3, 7); } else if( shift == 1 ) { switch( (modrm >> 3) & 0x7 ) { case 0: /* ROL rm8, 1 */ - I.CF = (src & 0x80) ? 1 : 0; - dst = (src << 1) + I.CF; - I.OF = ((src ^ dst) & 0x80) ? 1 : 0; - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + cpustate->CF = (src & 0x80) ? 1 : 0; + dst = (src << 1) + cpustate->CF; + cpustate->OF = ((src ^ dst) & 0x80) ? 1 : 0; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 1: /* ROR rm8, 1 */ - I.CF = (src & 0x1) ? 1 : 0; - dst = (I.CF << 7) | (src >> 1); - I.OF = ((src ^ dst) & 0x80) ? 1 : 0; - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + cpustate->CF = (src & 0x1) ? 1 : 0; + dst = (cpustate->CF << 7) | (src >> 1); + cpustate->OF = ((src ^ dst) & 0x80) ? 1 : 0; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 2: /* RCL rm8, 1 */ - dst = (src << 1) + I.CF; - I.CF = (src & 0x80) ? 1 : 0; - I.OF = ((src ^ dst) & 0x80) ? 1 : 0; - CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); + dst = (src << 1) + cpustate->CF; + cpustate->CF = (src & 0x80) ? 1 : 0; + cpustate->OF = ((src ^ dst) & 0x80) ? 1 : 0; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); break; case 3: /* RCR rm8, 1 */ - dst = (I.CF << 7) | (src >> 1); - I.CF = src & 0x1; - I.OF = ((src ^ dst) & 0x80) ? 1 : 0; - CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); + dst = (cpustate->CF << 7) | (src >> 1); + cpustate->CF = src & 0x1; + cpustate->OF = ((src ^ dst) & 0x80) ? 1 : 0; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); break; case 4: /* SHL/SAL rm8, 1 */ case 6: dst = src << 1; - I.CF = (src & 0x80) ? 1 : 0; - I.OF = (((I.CF << 7) ^ dst) & 0x80) ? 1 : 0; + cpustate->CF = (src & 0x80) ? 1 : 0; + cpustate->OF = (((cpustate->CF << 7) ^ dst) & 0x80) ? 1 : 0; SetSZPF8(dst); - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 5: /* SHR rm8, 1 */ dst = src >> 1; - I.CF = src & 0x1; - I.OF = (dst & 0x80) ? 1 : 0; + cpustate->CF = src & 0x1; + cpustate->OF = (dst & 0x80) ? 1 : 0; SetSZPF8(dst); - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 7: /* SAR rm8, 1 */ dst = (INT8)(src) >> 1; - I.CF = src & 0x1; - I.OF = 0; + cpustate->CF = src & 0x1; + cpustate->OF = 0; SetSZPF8(dst); - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; } @@ -64,47 +64,47 @@ static UINT8 I386OP(shift_rotate8)(UINT8 modrm, UINT32 value, UINT8 shift) case 0: /* ROL rm8, i8 */ dst = ((src & ((UINT8)0xff >> shift)) << shift) | ((src & ((UINT8)0xff << (8-shift))) >> (8-shift)); - I.CF = (src >> (8-shift)) & 0x1; - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + cpustate->CF = (src >> (8-shift)) & 0x1; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 1: /* ROR rm8, i8 */ dst = ((src & ((UINT8)0xff << shift)) >> shift) | ((src & ((UINT8)0xff >> (8-shift))) << (8-shift)); - I.CF = (src >> (shift-1)) & 0x1; - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + cpustate->CF = (src >> (shift-1)) & 0x1; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 2: /* RCL rm8, i8 */ dst = ((src & ((UINT8)0xff >> shift)) << shift) | ((src & ((UINT8)0xff << (9-shift))) >> (9-shift)) | - (I.CF << (shift-1)); - I.CF = (src >> (8-shift)) & 0x1; - CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); + (cpustate->CF << (shift-1)); + cpustate->CF = (src >> (8-shift)) & 0x1; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); break; case 3: /* RCR rm8, i8 */ dst = ((src & ((UINT8)0xff << shift)) >> shift) | ((src & ((UINT8)0xff >> (8-shift))) << (9-shift)) | - (I.CF << (8-shift)); - I.CF = (src >> (shift-1)) & 0x1; - CYCLES_RM(modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); + (cpustate->CF << (8-shift)); + cpustate->CF = (src >> (shift-1)) & 0x1; + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_CARRY_REG, CYCLES_ROTATE_CARRY_MEM); break; case 4: /* SHL/SAL rm8, i8 */ case 6: dst = src << shift; - I.CF = (src & (1 << (8-shift))) ? 1 : 0; + cpustate->CF = (src & (1 << (8-shift))) ? 1 : 0; SetSZPF8(dst); - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 5: /* SHR rm8, i8 */ dst = src >> shift; - I.CF = (src & (1 << (shift-1))) ? 1 : 0; + cpustate->CF = (src & (1 << (shift-1))) ? 1 : 0; SetSZPF8(dst); - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; case 7: /* SAR rm8, i8 */ dst = (INT8)src >> shift; - I.CF = (src & (1 << (shift-1))) ? 1 : 0; + cpustate->CF = (src & (1 << (shift-1))) ? 1 : 0; SetSZPF8(dst); - CYCLES_RM(modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); + CYCLES_RM(cpustate,modrm, CYCLES_ROTATE_REG, CYCLES_ROTATE_MEM); break; } } @@ -114,577 +114,577 @@ static UINT8 I386OP(shift_rotate8)(UINT8 modrm, UINT32 value, UINT8 shift) -static void I386OP(adc_rm8_r8)(void) // Opcode 0x10 +static void I386OP(adc_rm8_r8)(i386_state *cpustate) // Opcode 0x10 { UINT8 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG8(modrm); dst = LOAD_RM8(modrm); - src = ADD8(src, I.CF); - dst = ADD8(dst, src); + src = ADD8(cpustate,src, cpustate->CF); + dst = ADD8(cpustate,dst, src); STORE_RM8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG8(modrm); - dst = READ8(ea); - src = ADD8(src, I.CF); - dst = ADD8(dst, src); - WRITE8(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + dst = READ8(cpustate,ea); + src = ADD8(cpustate,src, cpustate->CF); + dst = ADD8(cpustate,dst, src); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(adc_r8_rm8)(void) // Opcode 0x12 +static void I386OP(adc_r8_rm8)(i386_state *cpustate) // Opcode 0x12 { UINT8 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM8(modrm); dst = LOAD_REG8(modrm); - src = ADD8(src, I.CF); - dst = ADD8(dst, src); + src = ADD8(cpustate,src, cpustate->CF); + dst = ADD8(cpustate,dst, src); STORE_REG8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ8(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ8(cpustate,ea); dst = LOAD_REG8(modrm); - src = ADD8(src, I.CF); - dst = ADD8(dst, src); + src = ADD8(cpustate,src, cpustate->CF); + dst = ADD8(cpustate,dst, src); STORE_REG8(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(adc_al_i8)(void) // Opcode 0x14 +static void I386OP(adc_al_i8)(i386_state *cpustate) // Opcode 0x14 { UINT8 src, dst; - src = FETCH(); + src = FETCH(cpustate); dst = REG8(AL); - src = ADD8(src, I.CF); - dst = ADD8(dst, src); + src = ADD8(cpustate,src, cpustate->CF); + dst = ADD8(cpustate,dst, src); REG8(AL) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(add_rm8_r8)(void) // Opcode 0x00 +static void I386OP(add_rm8_r8)(i386_state *cpustate) // Opcode 0x00 { UINT8 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG8(modrm); dst = LOAD_RM8(modrm); - dst = ADD8(dst, src); + dst = ADD8(cpustate,dst, src); STORE_RM8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG8(modrm); - dst = READ8(ea); - dst = ADD8(dst, src); - WRITE8(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + dst = READ8(cpustate,ea); + dst = ADD8(cpustate,dst, src); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(add_r8_rm8)(void) // Opcode 0x02 +static void I386OP(add_r8_rm8)(i386_state *cpustate) // Opcode 0x02 { UINT8 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM8(modrm); dst = LOAD_REG8(modrm); - dst = ADD8(dst, src); + dst = ADD8(cpustate,dst, src); STORE_REG8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ8(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ8(cpustate,ea); dst = LOAD_REG8(modrm); - dst = ADD8(dst, src); + dst = ADD8(cpustate,dst, src); STORE_REG8(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(add_al_i8)(void) // Opcode 0x04 +static void I386OP(add_al_i8)(i386_state *cpustate) // Opcode 0x04 { UINT8 src, dst; - src = FETCH(); + src = FETCH(cpustate); dst = REG8(AL); - dst = ADD8(dst, src); + dst = ADD8(cpustate,dst, src); REG8(AL) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(and_rm8_r8)(void) // Opcode 0x20 +static void I386OP(and_rm8_r8)(i386_state *cpustate) // Opcode 0x20 { UINT8 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG8(modrm); dst = LOAD_RM8(modrm); - dst = AND8(dst, src); + dst = AND8(cpustate,dst, src); STORE_RM8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG8(modrm); - dst = READ8(ea); - dst = AND8(dst, src); - WRITE8(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + dst = READ8(cpustate,ea); + dst = AND8(cpustate,dst, src); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(and_r8_rm8)(void) // Opcode 0x22 +static void I386OP(and_r8_rm8)(i386_state *cpustate) // Opcode 0x22 { UINT8 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM8(modrm); dst = LOAD_REG8(modrm); - dst = AND8(dst, src); + dst = AND8(cpustate,dst, src); STORE_REG8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ8(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ8(cpustate,ea); dst = LOAD_REG8(modrm); - dst = AND8(dst, src); + dst = AND8(cpustate,dst, src); STORE_REG8(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(and_al_i8)(void) // Opcode 0x24 +static void I386OP(and_al_i8)(i386_state *cpustate) // Opcode 0x24 { UINT8 src, dst; - src = FETCH(); + src = FETCH(cpustate); dst = REG8(AL); - dst = AND8(dst, src); + dst = AND8(cpustate,dst, src); REG8(AL) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(clc)(void) // Opcode 0xf8 +static void I386OP(clc)(i386_state *cpustate) // Opcode 0xf8 { - I.CF = 0; - CYCLES(CYCLES_CLC); + cpustate->CF = 0; + CYCLES(cpustate,CYCLES_CLC); } -static void I386OP(cld)(void) // Opcode 0xfc +static void I386OP(cld)(i386_state *cpustate) // Opcode 0xfc { - I.DF = 0; - CYCLES(CYCLES_CLD); + cpustate->DF = 0; + CYCLES(cpustate,CYCLES_CLD); } -static void I386OP(cli)(void) // Opcode 0xfa +static void I386OP(cli)(i386_state *cpustate) // Opcode 0xfa { - I.IF = 0; - CYCLES(CYCLES_CLI); + cpustate->IF = 0; + CYCLES(cpustate,CYCLES_CLI); } -static void I386OP(cmc)(void) // Opcode 0xf5 +static void I386OP(cmc)(i386_state *cpustate) // Opcode 0xf5 { - I.CF ^= 1; - CYCLES(CYCLES_CMC); + cpustate->CF ^= 1; + CYCLES(cpustate,CYCLES_CMC); } -static void I386OP(cmp_rm8_r8)(void) // Opcode 0x38 +static void I386OP(cmp_rm8_r8)(i386_state *cpustate) // Opcode 0x38 { UINT8 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG8(modrm); dst = LOAD_RM8(modrm); - SUB8(dst, src); - CYCLES(CYCLES_CMP_REG_REG); + SUB8(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG8(modrm); - dst = READ8(ea); - SUB8(dst, src); - CYCLES(CYCLES_CMP_REG_MEM); + dst = READ8(cpustate,ea); + SUB8(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_MEM); } } -static void I386OP(cmp_r8_rm8)(void) // Opcode 0x3a +static void I386OP(cmp_r8_rm8)(i386_state *cpustate) // Opcode 0x3a { UINT8 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM8(modrm); dst = LOAD_REG8(modrm); - SUB8(dst, src); - CYCLES(CYCLES_CMP_REG_REG); + SUB8(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ8(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ8(cpustate,ea); dst = LOAD_REG8(modrm); - SUB8(dst, src); - CYCLES(CYCLES_CMP_MEM_REG); + SUB8(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_MEM_REG); } } -static void I386OP(cmp_al_i8)(void) // Opcode 0x3c +static void I386OP(cmp_al_i8)(i386_state *cpustate) // Opcode 0x3c { UINT8 src, dst; - src = FETCH(); + src = FETCH(cpustate); dst = REG8(AL); - SUB8(dst, src); - CYCLES(CYCLES_CMP_IMM_ACC); + SUB8(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_IMM_ACC); } -static void I386OP(cmpsb)(void) // Opcode 0xa6 +static void I386OP(cmpsb)(i386_state *cpustate) // Opcode 0xa6 { UINT32 eas, ead; UINT8 src, dst; - if( I.segment_prefix ) { - eas = i386_translate( I.segment_override, I.address_size ? REG32(ESI) : REG16(SI) ); + if( cpustate->segment_prefix ) { + eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } else { - eas = i386_translate( DS, I.address_size ? REG32(ESI) : REG16(SI) ); + eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } - ead = i386_translate( ES, I.address_size ? REG32(EDI) : REG16(DI) ); - src = READ8(eas); - dst = READ8(ead); - SUB8(dst, src); - BUMP_SI(1); - BUMP_DI(1); - CYCLES(CYCLES_CMPS); + ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI) ); + src = READ8(cpustate,eas); + dst = READ8(cpustate,ead); + SUB8(cpustate,dst, src); + BUMP_SI(cpustate,1); + BUMP_DI(cpustate,1); + CYCLES(cpustate,CYCLES_CMPS); } -static void I386OP(in_al_i8)(void) // Opcode 0xe4 +static void I386OP(in_al_i8)(i386_state *cpustate) // Opcode 0xe4 { - UINT16 port = FETCH(); + UINT16 port = FETCH(cpustate); UINT8 data = READPORT8(port); REG8(AL) = data; - CYCLES(CYCLES_IN_VAR); + CYCLES(cpustate,CYCLES_IN_VAR); } -static void I386OP(in_al_dx)(void) // Opcode 0xec +static void I386OP(in_al_dx)(i386_state *cpustate) // Opcode 0xec { UINT16 port = REG16(DX); UINT8 data = READPORT8(port); REG8(AL) = data; - CYCLES(CYCLES_IN); + CYCLES(cpustate,CYCLES_IN); } -static void I386OP(ja_rel8)(void) // Opcode 0x77 +static void I386OP(ja_rel8)(i386_state *cpustate) // Opcode 0x77 { - INT8 disp = FETCH(); - if( I.CF == 0 && I.ZF == 0 ) { - NEAR_BRANCH(disp); - CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ + INT8 disp = FETCH(cpustate); + if( cpustate->CF == 0 && cpustate->ZF == 0 ) { + NEAR_BRANCH(cpustate,disp); + CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_DISP8_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH); } } -static void I386OP(jbe_rel8)(void) // Opcode 0x76 +static void I386OP(jbe_rel8)(i386_state *cpustate) // Opcode 0x76 { - INT8 disp = FETCH(); - if( I.CF != 0 || I.ZF != 0 ) { - NEAR_BRANCH(disp); - CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ + INT8 disp = FETCH(cpustate); + if( cpustate->CF != 0 || cpustate->ZF != 0 ) { + NEAR_BRANCH(cpustate,disp); + CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_DISP8_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH); } } -static void I386OP(jc_rel8)(void) // Opcode 0x72 +static void I386OP(jc_rel8)(i386_state *cpustate) // Opcode 0x72 { - INT8 disp = FETCH(); - if( I.CF != 0 ) { - NEAR_BRANCH(disp); - CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ + INT8 disp = FETCH(cpustate); + if( cpustate->CF != 0 ) { + NEAR_BRANCH(cpustate,disp); + CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_DISP8_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH); } } -static void I386OP(jg_rel8)(void) // Opcode 0x7f +static void I386OP(jg_rel8)(i386_state *cpustate) // Opcode 0x7f { - INT8 disp = FETCH(); - if( I.ZF == 0 && (I.SF == I.OF) ) { - NEAR_BRANCH(disp); - CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ + INT8 disp = FETCH(cpustate); + if( cpustate->ZF == 0 && (cpustate->SF == cpustate->OF) ) { + NEAR_BRANCH(cpustate,disp); + CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_DISP8_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH); } } -static void I386OP(jge_rel8)(void) // Opcode 0x7d +static void I386OP(jge_rel8)(i386_state *cpustate) // Opcode 0x7d { - INT8 disp = FETCH(); - if( (I.SF == I.OF) ) { - NEAR_BRANCH(disp); - CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ + INT8 disp = FETCH(cpustate); + if( (cpustate->SF == cpustate->OF) ) { + NEAR_BRANCH(cpustate,disp); + CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_DISP8_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH); } } -static void I386OP(jl_rel8)(void) // Opcode 0x7c +static void I386OP(jl_rel8)(i386_state *cpustate) // Opcode 0x7c { - INT8 disp = FETCH(); - if( (I.SF != I.OF) ) { - NEAR_BRANCH(disp); - CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ + INT8 disp = FETCH(cpustate); + if( (cpustate->SF != cpustate->OF) ) { + NEAR_BRANCH(cpustate,disp); + CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_DISP8_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH); } } -static void I386OP(jle_rel8)(void) // Opcode 0x7e +static void I386OP(jle_rel8)(i386_state *cpustate) // Opcode 0x7e { - INT8 disp = FETCH(); - if( I.ZF != 0 || (I.SF != I.OF) ) { - NEAR_BRANCH(disp); - CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ + INT8 disp = FETCH(cpustate); + if( cpustate->ZF != 0 || (cpustate->SF != cpustate->OF) ) { + NEAR_BRANCH(cpustate,disp); + CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_DISP8_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH); } } -static void I386OP(jnc_rel8)(void) // Opcode 0x73 +static void I386OP(jnc_rel8)(i386_state *cpustate) // Opcode 0x73 { - INT8 disp = FETCH(); - if( I.CF == 0 ) { - NEAR_BRANCH(disp); - CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ + INT8 disp = FETCH(cpustate); + if( cpustate->CF == 0 ) { + NEAR_BRANCH(cpustate,disp); + CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_DISP8_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH); } } -static void I386OP(jno_rel8)(void) // Opcode 0x71 +static void I386OP(jno_rel8)(i386_state *cpustate) // Opcode 0x71 { - INT8 disp = FETCH(); - if( I.OF == 0 ) { - NEAR_BRANCH(disp); - CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ + INT8 disp = FETCH(cpustate); + if( cpustate->OF == 0 ) { + NEAR_BRANCH(cpustate,disp); + CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_DISP8_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH); } } -static void I386OP(jnp_rel8)(void) // Opcode 0x7b +static void I386OP(jnp_rel8)(i386_state *cpustate) // Opcode 0x7b { - INT8 disp = FETCH(); - if( I.PF == 0 ) { - NEAR_BRANCH(disp); - CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ + INT8 disp = FETCH(cpustate); + if( cpustate->PF == 0 ) { + NEAR_BRANCH(cpustate,disp); + CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_DISP8_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH); } } -static void I386OP(jns_rel8)(void) // Opcode 0x79 +static void I386OP(jns_rel8)(i386_state *cpustate) // Opcode 0x79 { - INT8 disp = FETCH(); - if( I.SF == 0 ) { - NEAR_BRANCH(disp); - CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ + INT8 disp = FETCH(cpustate); + if( cpustate->SF == 0 ) { + NEAR_BRANCH(cpustate,disp); + CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_DISP8_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH); } } -static void I386OP(jnz_rel8)(void) // Opcode 0x75 +static void I386OP(jnz_rel8)(i386_state *cpustate) // Opcode 0x75 { - INT8 disp = FETCH(); - if( I.ZF == 0 ) { - NEAR_BRANCH(disp); - CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ + INT8 disp = FETCH(cpustate); + if( cpustate->ZF == 0 ) { + NEAR_BRANCH(cpustate,disp); + CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_DISP8_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH); } } -static void I386OP(jo_rel8)(void) // Opcode 0x70 +static void I386OP(jo_rel8)(i386_state *cpustate) // Opcode 0x70 { - INT8 disp = FETCH(); - if( I.OF != 0 ) { - NEAR_BRANCH(disp); - CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ + INT8 disp = FETCH(cpustate); + if( cpustate->OF != 0 ) { + NEAR_BRANCH(cpustate,disp); + CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_DISP8_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH); } } -static void I386OP(jp_rel8)(void) // Opcode 0x7a +static void I386OP(jp_rel8)(i386_state *cpustate) // Opcode 0x7a { - INT8 disp = FETCH(); - if( I.PF != 0 ) { - NEAR_BRANCH(disp); - CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ + INT8 disp = FETCH(cpustate); + if( cpustate->PF != 0 ) { + NEAR_BRANCH(cpustate,disp); + CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_DISP8_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH); } } -static void I386OP(js_rel8)(void) // Opcode 0x78 +static void I386OP(js_rel8)(i386_state *cpustate) // Opcode 0x78 { - INT8 disp = FETCH(); - if( I.SF != 0 ) { - NEAR_BRANCH(disp); - CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ + INT8 disp = FETCH(cpustate); + if( cpustate->SF != 0 ) { + NEAR_BRANCH(cpustate,disp); + CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_DISP8_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH); } } -static void I386OP(jz_rel8)(void) // Opcode 0x74 +static void I386OP(jz_rel8)(i386_state *cpustate) // Opcode 0x74 { - INT8 disp = FETCH(); - if( I.ZF != 0 ) { - NEAR_BRANCH(disp); - CYCLES(CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ + INT8 disp = FETCH(cpustate); + if( cpustate->ZF != 0 ) { + NEAR_BRANCH(cpustate,disp); + CYCLES(cpustate,CYCLES_JCC_DISP8); /* TODO: Timing = 7 + m */ } else { - CYCLES(CYCLES_JCC_DISP8_NOBRANCH); + CYCLES(cpustate,CYCLES_JCC_DISP8_NOBRANCH); } } -static void I386OP(jmp_rel8)(void) // Opcode 0xeb +static void I386OP(jmp_rel8)(i386_state *cpustate) // Opcode 0xeb { - INT8 disp = FETCH(); - NEAR_BRANCH(disp); - CYCLES(CYCLES_JMP_SHORT); /* TODO: Timing = 7 + m */ + INT8 disp = FETCH(cpustate); + NEAR_BRANCH(cpustate,disp); + CYCLES(cpustate,CYCLES_JMP_SHORT); /* TODO: Timing = 7 + m */ } -static void I386OP(lahf)(void) // Opcode 0x9f +static void I386OP(lahf)(i386_state *cpustate) // Opcode 0x9f { - REG8(AH) = get_flags() & 0xd7; - CYCLES(CYCLES_LAHF); + REG8(AH) = get_flags(cpustate) & 0xd7; + CYCLES(cpustate,CYCLES_LAHF); } -static void I386OP(lodsb)(void) // Opcode 0xac +static void I386OP(lodsb)(i386_state *cpustate) // Opcode 0xac { UINT32 eas; - if( I.segment_prefix ) { - eas = i386_translate( I.segment_override, I.address_size ? REG32(ESI) : REG16(SI) ); + if( cpustate->segment_prefix ) { + eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } else { - eas = i386_translate( DS, I.address_size ? REG32(ESI) : REG16(SI) ); + eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } - REG8(AL) = READ8(eas); - BUMP_SI(1); - CYCLES(CYCLES_LODS); + REG8(AL) = READ8(cpustate,eas); + BUMP_SI(cpustate,1); + CYCLES(cpustate,CYCLES_LODS); } -static void I386OP(mov_rm8_r8)(void) // Opcode 0x88 +static void I386OP(mov_rm8_r8)(i386_state *cpustate) // Opcode 0x88 { UINT8 src; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG8(modrm); STORE_RM8(modrm, src); - CYCLES(CYCLES_MOV_REG_REG); + CYCLES(cpustate,CYCLES_MOV_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG8(modrm); - WRITE8(ea, src); - CYCLES(CYCLES_MOV_REG_MEM); + WRITE8(cpustate,ea, src); + CYCLES(cpustate,CYCLES_MOV_REG_MEM); } } -static void I386OP(mov_r8_rm8)(void) // Opcode 0x8a +static void I386OP(mov_r8_rm8)(i386_state *cpustate) // Opcode 0x8a { UINT8 src; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM8(modrm); STORE_REG8(modrm, src); - CYCLES(CYCLES_MOV_REG_REG); + CYCLES(cpustate,CYCLES_MOV_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ8(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ8(cpustate,ea); STORE_REG8(modrm, src); - CYCLES(CYCLES_MOV_MEM_REG); + CYCLES(cpustate,CYCLES_MOV_MEM_REG); } } -static void I386OP(mov_rm8_i8)(void) // Opcode 0xc6 +static void I386OP(mov_rm8_i8)(i386_state *cpustate) // Opcode 0xc6 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { - UINT8 value = FETCH(); + UINT8 value = FETCH(cpustate); STORE_RM8(modrm, value); - CYCLES(CYCLES_MOV_IMM_REG); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } else { - UINT32 ea = GetEA(modrm); - UINT8 value = FETCH(); - WRITE8(ea, value); - CYCLES(CYCLES_MOV_IMM_MEM); + UINT32 ea = GetEA(cpustate,modrm); + UINT8 value = FETCH(cpustate); + WRITE8(cpustate,ea, value); + CYCLES(cpustate,CYCLES_MOV_IMM_MEM); } } -static void I386OP(mov_r32_cr)(void) // Opcode 0x0f 20 +static void I386OP(mov_r32_cr)(i386_state *cpustate) // Opcode 0x0f 20 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 cr = (modrm >> 3) & 0x7; - STORE_RM32(modrm, I.cr[cr]); - CYCLES(CYCLES_MOV_CR_REG); + STORE_RM32(modrm, cpustate->cr[cr]); + CYCLES(cpustate,CYCLES_MOV_CR_REG); } -static void I386OP(mov_r32_dr)(void) // Opcode 0x0f 21 +static void I386OP(mov_r32_dr)(i386_state *cpustate) // Opcode 0x0f 21 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 dr = (modrm >> 3) & 0x7; - STORE_RM32(modrm, I.dr[dr]); + STORE_RM32(modrm, cpustate->dr[dr]); switch(dr) { case 0: case 1: case 2: case 3: - CYCLES(CYCLES_MOV_REG_DR0_3); + CYCLES(cpustate,CYCLES_MOV_REG_DR0_3); break; case 6: case 7: - CYCLES(CYCLES_MOV_REG_DR6_7); + CYCLES(cpustate,CYCLES_MOV_REG_DR6_7); break; } } -static void I386OP(mov_cr_r32)(void) // Opcode 0x0f 22 +static void I386OP(mov_cr_r32)(i386_state *cpustate) // Opcode 0x0f 22 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 cr = (modrm >> 3) & 0x7; - I.cr[cr] = LOAD_RM32(modrm); + cpustate->cr[cr] = LOAD_RM32(modrm); switch(cr) { - case 0: CYCLES(CYCLES_MOV_REG_CR0); break; - case 2: CYCLES(CYCLES_MOV_REG_CR2); break; - case 3: CYCLES(CYCLES_MOV_REG_CR3); break; + case 0: CYCLES(cpustate,CYCLES_MOV_REG_CR0); break; + case 2: CYCLES(cpustate,CYCLES_MOV_REG_CR2); break; + case 3: CYCLES(cpustate,CYCLES_MOV_REG_CR3); break; default: fatalerror("i386: mov_cr_r32 CR%d !", cr); break; } } -static void I386OP(mov_dr_r32)(void) // Opcode 0x0f 23 +static void I386OP(mov_dr_r32)(i386_state *cpustate) // Opcode 0x0f 23 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 dr = (modrm >> 3) & 0x7; - I.dr[dr] = LOAD_RM32(modrm); + cpustate->dr[dr] = LOAD_RM32(modrm); switch(dr) { case 0: case 1: case 2: case 3: - CYCLES(CYCLES_MOV_DR0_3_REG); + CYCLES(cpustate,CYCLES_MOV_DR0_3_REG); break; case 6: case 7: - CYCLES(CYCLES_MOV_DR6_7_REG); + CYCLES(cpustate,CYCLES_MOV_DR6_7_REG); break; default: fatalerror("i386: mov_dr_r32 DR%d !", dr); @@ -692,331 +692,331 @@ static void I386OP(mov_dr_r32)(void) // Opcode 0x0f 23 } } -static void I386OP(mov_al_m8)(void) // Opcode 0xa0 +static void I386OP(mov_al_m8)(i386_state *cpustate) // Opcode 0xa0 { UINT32 offset, ea; - if( I.address_size ) { - offset = FETCH32(); + if( cpustate->address_size ) { + offset = FETCH32(cpustate); } else { - offset = FETCH16(); + offset = FETCH16(cpustate); } /* TODO: Not sure if this is correct... */ - if( I.segment_prefix ) { - ea = i386_translate( I.segment_override, offset ); + if( cpustate->segment_prefix ) { + ea = i386_translate(cpustate, cpustate->segment_override, offset ); } else { - ea = i386_translate( DS, offset ); + ea = i386_translate(cpustate, DS, offset ); } - REG8(AL) = READ8(ea); - CYCLES(CYCLES_MOV_IMM_MEM); + REG8(AL) = READ8(cpustate,ea); + CYCLES(cpustate,CYCLES_MOV_IMM_MEM); } -static void I386OP(mov_m8_al)(void) // Opcode 0xa2 +static void I386OP(mov_m8_al)(i386_state *cpustate) // Opcode 0xa2 { UINT32 offset, ea; - if( I.address_size ) { - offset = FETCH32(); + if( cpustate->address_size ) { + offset = FETCH32(cpustate); } else { - offset = FETCH16(); + offset = FETCH16(cpustate); } /* TODO: Not sure if this is correct... */ - if( I.segment_prefix ) { - ea = i386_translate( I.segment_override, offset ); + if( cpustate->segment_prefix ) { + ea = i386_translate(cpustate, cpustate->segment_override, offset ); } else { - ea = i386_translate( DS, offset ); + ea = i386_translate(cpustate, DS, offset ); } - WRITE8( ea, REG8(AL) ); - CYCLES(CYCLES_MOV_MEM_ACC); + WRITE8(cpustate, ea, REG8(AL) ); + CYCLES(cpustate,CYCLES_MOV_MEM_ACC); } -static void I386OP(mov_rm16_sreg)(void) // Opcode 0x8c +static void I386OP(mov_rm16_sreg)(i386_state *cpustate) // Opcode 0x8c { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); int s = (modrm >> 3) & 0x7; if( modrm >= 0xc0 ) { - STORE_RM16(modrm, I.sreg[s].selector); - CYCLES(CYCLES_MOV_SREG_REG); + STORE_RM16(modrm, cpustate->sreg[s].selector); + CYCLES(cpustate,CYCLES_MOV_SREG_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE16(ea, I.sreg[s].selector); - CYCLES(CYCLES_MOV_SREG_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE16(cpustate,ea, cpustate->sreg[s].selector); + CYCLES(cpustate,CYCLES_MOV_SREG_MEM); } } -static void I386OP(mov_sreg_rm16)(void) // Opcode 0x8e +static void I386OP(mov_sreg_rm16)(i386_state *cpustate) // Opcode 0x8e { UINT16 selector; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); int s = (modrm >> 3) & 0x7; if( modrm >= 0xc0 ) { selector = LOAD_RM16(modrm); - CYCLES(CYCLES_MOV_REG_SREG); + CYCLES(cpustate,CYCLES_MOV_REG_SREG); } else { - UINT32 ea = GetEA(modrm); - selector = READ16(ea); - CYCLES(CYCLES_MOV_MEM_SREG); + UINT32 ea = GetEA(cpustate,modrm); + selector = READ16(cpustate,ea); + CYCLES(cpustate,CYCLES_MOV_MEM_SREG); } - I.sreg[s].selector = selector; - i386_load_segment_descriptor( s ); + cpustate->sreg[s].selector = selector; + i386_load_segment_descriptor(cpustate, s ); } -static void I386OP(mov_al_i8)(void) // Opcode 0xb0 +static void I386OP(mov_al_i8)(i386_state *cpustate) // Opcode 0xb0 { - REG8(AL) = FETCH(); - CYCLES(CYCLES_MOV_IMM_REG); + REG8(AL) = FETCH(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_cl_i8)(void) // Opcode 0xb1 +static void I386OP(mov_cl_i8)(i386_state *cpustate) // Opcode 0xb1 { - REG8(CL) = FETCH(); - CYCLES(CYCLES_MOV_IMM_REG); + REG8(CL) = FETCH(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_dl_i8)(void) // Opcode 0xb2 +static void I386OP(mov_dl_i8)(i386_state *cpustate) // Opcode 0xb2 { - REG8(DL) = FETCH(); - CYCLES(CYCLES_MOV_IMM_REG); + REG8(DL) = FETCH(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_bl_i8)(void) // Opcode 0xb3 +static void I386OP(mov_bl_i8)(i386_state *cpustate) // Opcode 0xb3 { - REG8(BL) = FETCH(); - CYCLES(CYCLES_MOV_IMM_REG); + REG8(BL) = FETCH(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_ah_i8)(void) // Opcode 0xb4 +static void I386OP(mov_ah_i8)(i386_state *cpustate) // Opcode 0xb4 { - REG8(AH) = FETCH(); - CYCLES(CYCLES_MOV_IMM_REG); + REG8(AH) = FETCH(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_ch_i8)(void) // Opcode 0xb5 +static void I386OP(mov_ch_i8)(i386_state *cpustate) // Opcode 0xb5 { - REG8(CH) = FETCH(); - CYCLES(CYCLES_MOV_IMM_REG); + REG8(CH) = FETCH(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_dh_i8)(void) // Opcode 0xb6 +static void I386OP(mov_dh_i8)(i386_state *cpustate) // Opcode 0xb6 { - REG8(DH) = FETCH(); - CYCLES(CYCLES_MOV_IMM_REG); + REG8(DH) = FETCH(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(mov_bh_i8)(void) // Opcode 0xb7 +static void I386OP(mov_bh_i8)(i386_state *cpustate) // Opcode 0xb7 { - REG8(BH) = FETCH(); - CYCLES(CYCLES_MOV_IMM_REG); + REG8(BH) = FETCH(cpustate); + CYCLES(cpustate,CYCLES_MOV_IMM_REG); } -static void I386OP(movsb)(void) // Opcode 0xa4 +static void I386OP(movsb)(i386_state *cpustate) // Opcode 0xa4 { UINT32 eas, ead; UINT8 v; - if( I.segment_prefix ) { - eas = i386_translate( I.segment_override, I.address_size ? REG32(ESI) : REG16(SI) ); + if( cpustate->segment_prefix ) { + eas = i386_translate(cpustate, cpustate->segment_override, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } else { - eas = i386_translate( DS, I.address_size ? REG32(ESI) : REG16(SI) ); + eas = i386_translate(cpustate, DS, cpustate->address_size ? REG32(ESI) : REG16(SI) ); } - ead = i386_translate( ES, I.address_size ? REG32(EDI) : REG16(DI) ); - v = READ8(eas); - WRITE8(ead, v); - BUMP_SI(1); - BUMP_DI(1); - CYCLES(CYCLES_MOVS); + ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI) ); + v = READ8(cpustate,eas); + WRITE8(cpustate,ead, v); + BUMP_SI(cpustate,1); + BUMP_DI(cpustate,1); + CYCLES(cpustate,CYCLES_MOVS); } -static void I386OP(or_rm8_r8)(void) // Opcode 0x08 +static void I386OP(or_rm8_r8)(i386_state *cpustate) // Opcode 0x08 { UINT8 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG8(modrm); dst = LOAD_RM8(modrm); - dst = OR8(dst, src); + dst = OR8(cpustate,dst, src); STORE_RM8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG8(modrm); - dst = READ8(ea); - dst = OR8(dst, src); - WRITE8(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + dst = READ8(cpustate,ea); + dst = OR8(cpustate,dst, src); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(or_r8_rm8)(void) // Opcode 0x0a +static void I386OP(or_r8_rm8)(i386_state *cpustate) // Opcode 0x0a { UINT8 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM8(modrm); dst = LOAD_REG8(modrm); - dst = OR8(dst, src); + dst = OR8(cpustate,dst, src); STORE_REG8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ8(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ8(cpustate,ea); dst = LOAD_REG8(modrm); - dst = OR8(dst, src); + dst = OR8(cpustate,dst, src); STORE_REG8(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(or_al_i8)(void) // Opcode 0x0c +static void I386OP(or_al_i8)(i386_state *cpustate) // Opcode 0x0c { UINT8 src, dst; - src = FETCH(); + src = FETCH(cpustate); dst = REG8(AL); - dst = OR8(dst, src); + dst = OR8(cpustate,dst, src); REG8(EAX) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(out_al_i8)(void) // Opcode 0xe6 +static void I386OP(out_al_i8)(i386_state *cpustate) // Opcode 0xe6 { - UINT16 port = FETCH(); + UINT16 port = FETCH(cpustate); UINT8 data = REG8(AL); WRITEPORT8(port, data); - CYCLES(CYCLES_OUT_VAR); + CYCLES(cpustate,CYCLES_OUT_VAR); } -static void I386OP(out_al_dx)(void) // Opcode 0xee +static void I386OP(out_al_dx)(i386_state *cpustate) // Opcode 0xee { UINT16 port = REG16(DX); UINT8 data = REG8(AL); WRITEPORT8(port, data); - CYCLES(CYCLES_OUT); + CYCLES(cpustate,CYCLES_OUT); } -static void I386OP(push_i8)(void) // Opcode 0x6a +static void I386OP(push_i8)(i386_state *cpustate) // Opcode 0x6a { - UINT8 value = FETCH(); - PUSH8(value); - CYCLES(CYCLES_PUSH_IMM); + UINT8 value = FETCH(cpustate); + PUSH8(cpustate,value); + CYCLES(cpustate,CYCLES_PUSH_IMM); } -static void I386OP(ins_generic)(int size) +static void I386OP(ins_generic)(i386_state *cpustate, int size) { UINT32 ead; UINT8 vb; UINT16 vw; UINT32 vd; - ead = i386_translate( ES, I.address_size ? REG32(EDI) : REG16(DI) ); + ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI) ); switch(size) { case 1: vb = READPORT8(REG16(DX)); - WRITE8(ead, vb); + WRITE8(cpustate,ead, vb); break; case 2: vw = READPORT16(REG16(DX)); - WRITE16(ead, vw); + WRITE16(cpustate,ead, vw); break; case 4: vd = READPORT32(REG16(DX)); - WRITE32(ead, vd); + WRITE32(cpustate,ead, vd); break; } - REG32(EDI) += ((I.DF) ? -1 : 1) * size; - CYCLES(CYCLES_INS); // TODO: Confirm this value + REG32(EDI) += ((cpustate->DF) ? -1 : 1) * size; + CYCLES(cpustate,CYCLES_INS); // TODO: Confirm this value } -static void I386OP(insb)(void) // Opcode 0x6c +static void I386OP(insb)(i386_state *cpustate) // Opcode 0x6c { - I386OP(ins_generic)(1); + I386OP(ins_generic)(cpustate, 1); } -static void I386OP(insw)(void) // Opcode 0x6d +static void I386OP(insw)(i386_state *cpustate) // Opcode 0x6d { - I386OP(ins_generic)(2); + I386OP(ins_generic)(cpustate, 2); } -static void I386OP(insd)(void) // Opcode 0x6d +static void I386OP(insd)(i386_state *cpustate) // Opcode 0x6d { - I386OP(ins_generic)(4); + I386OP(ins_generic)(cpustate, 4); } -static void I386OP(outs_generic)(int size) +static void I386OP(outs_generic)(i386_state *cpustate, int size) { UINT32 eas; UINT8 vb; UINT16 vw; UINT32 vd; - if( I.segment_prefix ) { - eas = i386_translate( I.segment_override, REG32(ESI) ); + if( cpustate->segment_prefix ) { + eas = i386_translate(cpustate, cpustate->segment_override, REG32(ESI) ); } else { - eas = i386_translate( DS, REG32(ESI) ); + eas = i386_translate(cpustate, DS, REG32(ESI) ); } switch(size) { case 1: - vb = READ8(eas); + vb = READ8(cpustate,eas); WRITEPORT8(REG16(DX), vb); break; case 2: - vw = READ16(eas); + vw = READ16(cpustate,eas); WRITEPORT16(REG16(DX), vw); break; case 4: - vd = READ32(eas); + vd = READ32(cpustate,eas); WRITEPORT32(REG16(DX), vd); break; } - REG32(ESI) += ((I.DF) ? -1 : 1) * size; - CYCLES(CYCLES_OUTS); // TODO: Confirm this value + REG32(ESI) += ((cpustate->DF) ? -1 : 1) * size; + CYCLES(cpustate,CYCLES_OUTS); // TODO: Confirm this value } -static void I386OP(outsb)(void) // Opcode 0x6e +static void I386OP(outsb)(i386_state *cpustate) // Opcode 0x6e { - I386OP(outs_generic)(1); + I386OP(outs_generic)(cpustate, 1); } -static void I386OP(outsw)(void) // Opcode 0x6f +static void I386OP(outsw)(i386_state *cpustate) // Opcode 0x6f { - I386OP(outs_generic)(2); + I386OP(outs_generic)(cpustate, 2); } -static void I386OP(outsd)(void) // Opcode 0x6f +static void I386OP(outsd)(i386_state *cpustate) // Opcode 0x6f { - I386OP(outs_generic)(4); + I386OP(outs_generic)(cpustate, 4); } -static void I386OP(repeat)(int invert_flag) +static void I386OP(repeat)(i386_state *cpustate, int invert_flag) { - UINT32 repeated_eip = I.eip; - UINT32 repeated_pc = I.pc; - UINT8 opcode = FETCH(); + UINT32 repeated_eip = cpustate->eip; + UINT32 repeated_pc = cpustate->pc; + UINT8 opcode = FETCH(cpustate); UINT32 eas, ead; UINT32 count; INT32 cycle_base = 0, cycle_adjustment = 0; UINT8 *flag = NULL; - if( I.segment_prefix ) { - eas = i386_translate( I.segment_override, I.sreg[CS].d ? REG32(ESI) : REG16(SI) ); + if( cpustate->segment_prefix ) { + eas = i386_translate(cpustate, cpustate->segment_override, cpustate->sreg[CS].d ? REG32(ESI) : REG16(SI) ); } else { - eas = i386_translate( DS, I.sreg[CS].d ? REG32(ESI) : REG16(SI) ); + eas = i386_translate(cpustate, DS, cpustate->sreg[CS].d ? REG32(ESI) : REG16(SI) ); } - ead = i386_translate( ES, I.sreg[CS].d ? REG32(EDI) : REG16(DI) ); + ead = i386_translate(cpustate, ES, cpustate->sreg[CS].d ? REG32(EDI) : REG16(DI) ); if( opcode == 0x66 ) { - I.operand_size ^= 1; - repeated_eip = I.eip; - repeated_pc = I.pc; - opcode = FETCH(); + cpustate->operand_size ^= 1; + repeated_eip = cpustate->eip; + repeated_pc = cpustate->pc; + opcode = FETCH(cpustate); } if( opcode == 0x67 ) { - I.address_size ^= 1; - repeated_eip = I.eip; - repeated_pc = I.pc; - opcode = FETCH(); + cpustate->address_size ^= 1; + repeated_eip = cpustate->eip; + repeated_pc = cpustate->pc; + opcode = FETCH(cpustate); } switch(opcode) @@ -1052,7 +1052,7 @@ static void I386OP(repeat)(int invert_flag) /* CMPSB, CMPSW, CMPSD */ cycle_base = 5; cycle_adjustment = -1; - flag = &I.ZF; + flag = &cpustate->ZF; break; case 0xac: @@ -1076,7 +1076,7 @@ static void I386OP(repeat)(int invert_flag) /* SCASB, SCASW, SCASD */ cycle_base = 5; cycle_adjustment = 0; - flag = &I.ZF; + flag = &cpustate->ZF; break; default: @@ -1084,7 +1084,7 @@ static void I386OP(repeat)(int invert_flag) break; } - if( I.sreg[CS].d ) { + if( cpustate->sreg[CS].d ) { if( REG32(ECX) == 0 ) return; } else { @@ -1096,16 +1096,16 @@ static void I386OP(repeat)(int invert_flag) CYCLES_NUM(cycle_base); do { - I.eip = repeated_eip; - I.pc = repeated_pc; - I386OP(decode_opcode)(); + cpustate->eip = repeated_eip; + cpustate->pc = repeated_pc; + I386OP(decode_opcode)(cpustate); CYCLES_NUM(cycle_adjustment); - if (I.sreg[CS].d) + if (cpustate->sreg[CS].d) count = --REG32(ECX); else count = --REG16(CX); - if (I.cycles <= 0) + if (cpustate->cycles <= 0) goto outofcycles; } while( count && (!flag || (invert_flag ? !*flag : *flag)) ); @@ -1115,769 +1115,769 @@ outofcycles: /* if we run out of cycles to execute, and we are still in the repeat, we need * to exit this instruction in such a way to go right back into it when we have * time to execute cycles */ - I.eip = I.prev_eip; - CHANGE_PC(I.eip); + cpustate->eip = cpustate->prev_eip; + CHANGE_PC(cpustate,cpustate->eip); CYCLES_NUM(-cycle_base); } -static void I386OP(rep)(void) // Opcode 0xf3 +static void I386OP(rep)(i386_state *cpustate) // Opcode 0xf3 { - I386OP(repeat)(0); + I386OP(repeat)(cpustate, 0); } -static void I386OP(repne)(void) // Opcode 0xf2 +static void I386OP(repne)(i386_state *cpustate) // Opcode 0xf2 { - I386OP(repeat)(1); + I386OP(repeat)(cpustate, 1); } -static void I386OP(sahf)(void) // Opcode 0x9e +static void I386OP(sahf)(i386_state *cpustate) // Opcode 0x9e { - set_flags( (get_flags() & 0xffffff00) | (REG8(AH) & 0xd7) ); - CYCLES(CYCLES_SAHF); + set_flags(cpustate, (get_flags(cpustate) & 0xffffff00) | (REG8(AH) & 0xd7) ); + CYCLES(cpustate,CYCLES_SAHF); } -static void I386OP(sbb_rm8_r8)(void) // Opcode 0x18 +static void I386OP(sbb_rm8_r8)(i386_state *cpustate) // Opcode 0x18 { UINT8 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { - src = LOAD_REG8(modrm) + I.CF; + src = LOAD_REG8(modrm) + cpustate->CF; dst = LOAD_RM8(modrm); - dst = SUB8(dst, src); + dst = SUB8(cpustate,dst, src); STORE_RM8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = LOAD_REG8(modrm) + I.CF; - dst = READ8(ea); - dst = SUB8(dst, src); - WRITE8(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + UINT32 ea = GetEA(cpustate,modrm); + src = LOAD_REG8(modrm) + cpustate->CF; + dst = READ8(cpustate,ea); + dst = SUB8(cpustate,dst, src); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(sbb_r8_rm8)(void) // Opcode 0x1a +static void I386OP(sbb_r8_rm8)(i386_state *cpustate) // Opcode 0x1a { UINT8 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { - src = LOAD_RM8(modrm) + I.CF; + src = LOAD_RM8(modrm) + cpustate->CF; dst = LOAD_REG8(modrm); - dst = SUB8(dst, src); + dst = SUB8(cpustate,dst, src); STORE_REG8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ8(ea) + I.CF; + UINT32 ea = GetEA(cpustate,modrm); + src = READ8(cpustate,ea) + cpustate->CF; dst = LOAD_REG8(modrm); - dst = SUB8(dst, src); + dst = SUB8(cpustate,dst, src); STORE_REG8(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(sbb_al_i8)(void) // Opcode 0x1c +static void I386OP(sbb_al_i8)(i386_state *cpustate) // Opcode 0x1c { UINT8 src, dst; - src = FETCH() + I.CF; + src = FETCH(cpustate) + cpustate->CF; dst = REG8(AL); - dst = SUB8(dst, src); + dst = SUB8(cpustate,dst, src); REG8(EAX) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(scasb)(void) // Opcode 0xae +static void I386OP(scasb)(i386_state *cpustate) // Opcode 0xae { UINT32 eas; UINT8 src, dst; - eas = i386_translate( ES, I.address_size ? REG32(EDI) : REG16(DI) ); - src = READ8(eas); + eas = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI) ); + src = READ8(cpustate,eas); dst = REG8(AL); - SUB8(dst, src); - BUMP_DI(1); - CYCLES(CYCLES_SCAS); + SUB8(cpustate,dst, src); + BUMP_DI(cpustate,1); + CYCLES(cpustate,CYCLES_SCAS); } -static void I386OP(setalc)(void) // Opcode 0xd6 (undocumented) +static void I386OP(setalc)(i386_state *cpustate) // Opcode 0xd6 (undocumented) { - if( I.CF ) { + if( cpustate->CF ) { REG8(AL) = 0xff; } else { REG8(AL) = 0; } - CYCLES(3); + CYCLES(cpustate,3); } -static void I386OP(seta_rm8)(void) // Opcode 0x0f 97 +static void I386OP(seta_rm8)(i386_state *cpustate) // Opcode 0x0f 97 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 value = 0; - if( I.CF == 0 && I.ZF == 0 ) { + if( cpustate->CF == 0 && cpustate->ZF == 0 ) { value = 1; } if( modrm >= 0xc0 ) { STORE_RM8(modrm, value); - CYCLES(CYCLES_SETCC_REG); + CYCLES(cpustate,CYCLES_SETCC_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE8(ea, value); - CYCLES(CYCLES_SETCC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE8(cpustate,ea, value); + CYCLES(cpustate,CYCLES_SETCC_MEM); } } -static void I386OP(setbe_rm8)(void) // Opcode 0x0f 96 +static void I386OP(setbe_rm8)(i386_state *cpustate) // Opcode 0x0f 96 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 value = 0; - if( I.CF != 0 || I.ZF != 0 ) { + if( cpustate->CF != 0 || cpustate->ZF != 0 ) { value = 1; } if( modrm >= 0xc0 ) { STORE_RM8(modrm, value); - CYCLES(CYCLES_SETCC_REG); + CYCLES(cpustate,CYCLES_SETCC_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE8(ea, value); - CYCLES(CYCLES_SETCC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE8(cpustate,ea, value); + CYCLES(cpustate,CYCLES_SETCC_MEM); } } -static void I386OP(setc_rm8)(void) // Opcode 0x0f 92 +static void I386OP(setc_rm8)(i386_state *cpustate) // Opcode 0x0f 92 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 value = 0; - if( I.CF != 0 ) { + if( cpustate->CF != 0 ) { value = 1; } if( modrm >= 0xc0 ) { STORE_RM8(modrm, value); - CYCLES(CYCLES_SETCC_REG); + CYCLES(cpustate,CYCLES_SETCC_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE8(ea, value); - CYCLES(CYCLES_SETCC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE8(cpustate,ea, value); + CYCLES(cpustate,CYCLES_SETCC_MEM); } } -static void I386OP(setg_rm8)(void) // Opcode 0x0f 9f +static void I386OP(setg_rm8)(i386_state *cpustate) // Opcode 0x0f 9f { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 value = 0; - if( I.ZF == 0 && (I.SF == I.OF) ) { + if( cpustate->ZF == 0 && (cpustate->SF == cpustate->OF) ) { value = 1; } if( modrm >= 0xc0 ) { STORE_RM8(modrm, value); - CYCLES(CYCLES_SETCC_REG); + CYCLES(cpustate,CYCLES_SETCC_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE8(ea, value); - CYCLES(CYCLES_SETCC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE8(cpustate,ea, value); + CYCLES(cpustate,CYCLES_SETCC_MEM); } } -static void I386OP(setge_rm8)(void) // Opcode 0x0f 9d +static void I386OP(setge_rm8)(i386_state *cpustate) // Opcode 0x0f 9d { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 value = 0; - if( (I.SF == I.OF) ) { + if( (cpustate->SF == cpustate->OF) ) { value = 1; } if( modrm >= 0xc0 ) { STORE_RM8(modrm, value); - CYCLES(CYCLES_SETCC_REG); + CYCLES(cpustate,CYCLES_SETCC_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE8(ea, value); - CYCLES(CYCLES_SETCC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE8(cpustate,ea, value); + CYCLES(cpustate,CYCLES_SETCC_MEM); } } -static void I386OP(setl_rm8)(void) // Opcode 0x0f 9c +static void I386OP(setl_rm8)(i386_state *cpustate) // Opcode 0x0f 9c { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 value = 0; - if( I.SF != I.OF ) { + if( cpustate->SF != cpustate->OF ) { value = 1; } if( modrm >= 0xc0 ) { STORE_RM8(modrm, value); - CYCLES(CYCLES_SETCC_REG); + CYCLES(cpustate,CYCLES_SETCC_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE8(ea, value); - CYCLES(CYCLES_SETCC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE8(cpustate,ea, value); + CYCLES(cpustate,CYCLES_SETCC_MEM); } } -static void I386OP(setle_rm8)(void) // Opcode 0x0f 9e +static void I386OP(setle_rm8)(i386_state *cpustate) // Opcode 0x0f 9e { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 value = 0; - if( I.ZF != 0 || (I.SF != I.OF) ) { + if( cpustate->ZF != 0 || (cpustate->SF != cpustate->OF) ) { value = 1; } if( modrm >= 0xc0 ) { STORE_RM8(modrm, value); - CYCLES(CYCLES_SETCC_REG); + CYCLES(cpustate,CYCLES_SETCC_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE8(ea, value); - CYCLES(CYCLES_SETCC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE8(cpustate,ea, value); + CYCLES(cpustate,CYCLES_SETCC_MEM); } } -static void I386OP(setnc_rm8)(void) // Opcode 0x0f 93 +static void I386OP(setnc_rm8)(i386_state *cpustate) // Opcode 0x0f 93 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 value = 0; - if( I.CF == 0 ) { + if( cpustate->CF == 0 ) { value = 1; } if( modrm >= 0xc0 ) { STORE_RM8(modrm, value); - CYCLES(CYCLES_SETCC_REG); + CYCLES(cpustate,CYCLES_SETCC_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE8(ea, value); - CYCLES(CYCLES_SETCC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE8(cpustate,ea, value); + CYCLES(cpustate,CYCLES_SETCC_MEM); } } -static void I386OP(setno_rm8)(void) // Opcode 0x0f 91 +static void I386OP(setno_rm8)(i386_state *cpustate) // Opcode 0x0f 91 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 value = 0; - if( I.OF == 0 ) { + if( cpustate->OF == 0 ) { value = 1; } if( modrm >= 0xc0 ) { STORE_RM8(modrm, value); - CYCLES(CYCLES_SETCC_REG); + CYCLES(cpustate,CYCLES_SETCC_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE8(ea, value); - CYCLES(CYCLES_SETCC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE8(cpustate,ea, value); + CYCLES(cpustate,CYCLES_SETCC_MEM); } } -static void I386OP(setnp_rm8)(void) // Opcode 0x0f 9b +static void I386OP(setnp_rm8)(i386_state *cpustate) // Opcode 0x0f 9b { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 value = 0; - if( I.PF == 0 ) { + if( cpustate->PF == 0 ) { value = 1; } if( modrm >= 0xc0 ) { STORE_RM8(modrm, value); - CYCLES(CYCLES_SETCC_REG); + CYCLES(cpustate,CYCLES_SETCC_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE8(ea, value); - CYCLES(CYCLES_SETCC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE8(cpustate,ea, value); + CYCLES(cpustate,CYCLES_SETCC_MEM); } } -static void I386OP(setns_rm8)(void) // Opcode 0x0f 99 +static void I386OP(setns_rm8)(i386_state *cpustate) // Opcode 0x0f 99 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 value = 0; - if( I.SF == 0 ) { + if( cpustate->SF == 0 ) { value = 1; } if( modrm >= 0xc0 ) { STORE_RM8(modrm, value); - CYCLES(CYCLES_SETCC_REG); + CYCLES(cpustate,CYCLES_SETCC_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE8(ea, value); - CYCLES(CYCLES_SETCC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE8(cpustate,ea, value); + CYCLES(cpustate,CYCLES_SETCC_MEM); } } -static void I386OP(setnz_rm8)(void) // Opcode 0x0f 95 +static void I386OP(setnz_rm8)(i386_state *cpustate) // Opcode 0x0f 95 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 value = 0; - if( I.ZF == 0 ) { + if( cpustate->ZF == 0 ) { value = 1; } if( modrm >= 0xc0 ) { STORE_RM8(modrm, value); - CYCLES(CYCLES_SETCC_REG); + CYCLES(cpustate,CYCLES_SETCC_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE8(ea, value); - CYCLES(CYCLES_SETCC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE8(cpustate,ea, value); + CYCLES(cpustate,CYCLES_SETCC_MEM); } } -static void I386OP(seto_rm8)(void) // Opcode 0x0f 90 +static void I386OP(seto_rm8)(i386_state *cpustate) // Opcode 0x0f 90 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 value = 0; - if( I.OF != 0 ) { + if( cpustate->OF != 0 ) { value = 1; } if( modrm >= 0xc0 ) { STORE_RM8(modrm, value); - CYCLES(CYCLES_SETCC_REG); + CYCLES(cpustate,CYCLES_SETCC_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE8(ea, value); - CYCLES(CYCLES_SETCC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE8(cpustate,ea, value); + CYCLES(cpustate,CYCLES_SETCC_MEM); } } -static void I386OP(setp_rm8)(void) // Opcode 0x0f 9a +static void I386OP(setp_rm8)(i386_state *cpustate) // Opcode 0x0f 9a { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 value = 0; - if( I.PF != 0 ) { + if( cpustate->PF != 0 ) { value = 1; } if( modrm >= 0xc0 ) { STORE_RM8(modrm, value); - CYCLES(CYCLES_SETCC_REG); + CYCLES(cpustate,CYCLES_SETCC_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE8(ea, value); - CYCLES(CYCLES_SETCC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE8(cpustate,ea, value); + CYCLES(cpustate,CYCLES_SETCC_MEM); } } -static void I386OP(sets_rm8)(void) // Opcode 0x0f 98 +static void I386OP(sets_rm8)(i386_state *cpustate) // Opcode 0x0f 98 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 value = 0; - if( I.SF != 0 ) { + if( cpustate->SF != 0 ) { value = 1; } if( modrm >= 0xc0 ) { STORE_RM8(modrm, value); - CYCLES(CYCLES_SETCC_REG); + CYCLES(cpustate,CYCLES_SETCC_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE8(ea, value); - CYCLES(CYCLES_SETCC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE8(cpustate,ea, value); + CYCLES(cpustate,CYCLES_SETCC_MEM); } } -static void I386OP(setz_rm8)(void) // Opcode 0x0f 94 +static void I386OP(setz_rm8)(i386_state *cpustate) // Opcode 0x0f 94 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 value = 0; - if( I.ZF != 0 ) { + if( cpustate->ZF != 0 ) { value = 1; } if( modrm >= 0xc0 ) { STORE_RM8(modrm, value); - CYCLES(CYCLES_SETCC_REG); + CYCLES(cpustate,CYCLES_SETCC_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE8(ea, value); - CYCLES(CYCLES_SETCC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE8(cpustate,ea, value); + CYCLES(cpustate,CYCLES_SETCC_MEM); } } -static void I386OP(stc)(void) // Opcode 0xf9 +static void I386OP(stc)(i386_state *cpustate) // Opcode 0xf9 { - I.CF = 1; - CYCLES(CYCLES_STC); + cpustate->CF = 1; + CYCLES(cpustate,CYCLES_STC); } -static void I386OP(std)(void) // Opcode 0xfd +static void I386OP(std)(i386_state *cpustate) // Opcode 0xfd { - I.DF = 1; - CYCLES(CYCLES_STD); + cpustate->DF = 1; + CYCLES(cpustate,CYCLES_STD); } -static void I386OP(sti)(void) // Opcode 0xfb +static void I386OP(sti)(i386_state *cpustate) // Opcode 0xfb { - I.IF = 1; - CYCLES(CYCLES_STI); + cpustate->IF = 1; + CYCLES(cpustate,CYCLES_STI); } -static void I386OP(stosb)(void) // Opcode 0xaa +static void I386OP(stosb)(i386_state *cpustate) // Opcode 0xaa { UINT32 ead; - ead = i386_translate( ES, I.address_size ? REG32(EDI) : REG16(DI) ); - WRITE8(ead, REG8(AL)); - BUMP_DI(1); - CYCLES(CYCLES_STOS); + ead = i386_translate(cpustate, ES, cpustate->address_size ? REG32(EDI) : REG16(DI) ); + WRITE8(cpustate,ead, REG8(AL)); + BUMP_DI(cpustate,1); + CYCLES(cpustate,CYCLES_STOS); } -static void I386OP(sub_rm8_r8)(void) // Opcode 0x28 +static void I386OP(sub_rm8_r8)(i386_state *cpustate) // Opcode 0x28 { UINT8 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG8(modrm); dst = LOAD_RM8(modrm); - dst = SUB8(dst, src); + dst = SUB8(cpustate,dst, src); STORE_RM8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG8(modrm); - dst = READ8(ea); - dst = SUB8(dst, src); - WRITE8(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + dst = READ8(cpustate,ea); + dst = SUB8(cpustate,dst, src); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(sub_r8_rm8)(void) // Opcode 0x2a +static void I386OP(sub_r8_rm8)(i386_state *cpustate) // Opcode 0x2a { UINT8 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM8(modrm); dst = LOAD_REG8(modrm); - dst = SUB8(dst, src); + dst = SUB8(cpustate,dst, src); STORE_REG8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ8(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ8(cpustate,ea); dst = LOAD_REG8(modrm); - dst = SUB8(dst, src); + dst = SUB8(cpustate,dst, src); STORE_REG8(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(sub_al_i8)(void) // Opcode 0x2c +static void I386OP(sub_al_i8)(i386_state *cpustate) // Opcode 0x2c { UINT8 src, dst; - src = FETCH(); + src = FETCH(cpustate); dst = REG8(EAX); - dst = SUB8(dst, src); + dst = SUB8(cpustate,dst, src); REG8(EAX) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(test_al_i8)(void) // Opcode 0xa8 +static void I386OP(test_al_i8)(i386_state *cpustate) // Opcode 0xa8 { - UINT8 src = FETCH(); + UINT8 src = FETCH(cpustate); UINT8 dst = REG8(AL); dst = src & dst; SetSZPF8(dst); - I.CF = 0; - I.OF = 0; - CYCLES(CYCLES_ALU_IMM_ACC); + cpustate->CF = 0; + cpustate->OF = 0; + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(test_rm8_r8)(void) // Opcode 0x84 +static void I386OP(test_rm8_r8)(i386_state *cpustate) // Opcode 0x84 { UINT8 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG8(modrm); dst = LOAD_RM8(modrm); dst = src & dst; SetSZPF8(dst); - I.CF = 0; - I.OF = 0; - CYCLES(CYCLES_TEST_REG_REG); + cpustate->CF = 0; + cpustate->OF = 0; + CYCLES(cpustate,CYCLES_TEST_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG8(modrm); - dst = READ8(ea); + dst = READ8(cpustate,ea); dst = src & dst; SetSZPF8(dst); - I.CF = 0; - I.OF = 0; - CYCLES(CYCLES_TEST_REG_MEM); + cpustate->CF = 0; + cpustate->OF = 0; + CYCLES(cpustate,CYCLES_TEST_REG_MEM); } } -static void I386OP(xchg_r8_rm8)(void) // Opcode 0x86 +static void I386OP(xchg_r8_rm8)(i386_state *cpustate) // Opcode 0x86 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT8 src = LOAD_RM8(modrm); UINT8 dst = LOAD_REG8(modrm); STORE_REG8(modrm, src); STORE_RM8(modrm, dst); - CYCLES(CYCLES_XCHG_REG_REG); + CYCLES(cpustate,CYCLES_XCHG_REG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT8 src = READ8(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT8 src = READ8(cpustate,ea); UINT8 dst = LOAD_REG8(modrm); STORE_REG8(modrm, src); - WRITE8(ea, dst); - CYCLES(CYCLES_XCHG_REG_MEM); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_XCHG_REG_MEM); } } -static void I386OP(xor_rm8_r8)(void) // Opcode 0x30 +static void I386OP(xor_rm8_r8)(i386_state *cpustate) // Opcode 0x30 { UINT8 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_REG8(modrm); dst = LOAD_RM8(modrm); - dst = XOR8(dst, src); + dst = XOR8(cpustate,dst, src); STORE_RM8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); src = LOAD_REG8(modrm); - dst = READ8(ea); - dst = XOR8(dst, src); - WRITE8(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + dst = READ8(cpustate,ea); + dst = XOR8(cpustate,dst, src); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } } -static void I386OP(xor_r8_rm8)(void) // Opcode 0x32 +static void I386OP(xor_r8_rm8)(i386_state *cpustate) // Opcode 0x32 { UINT32 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { src = LOAD_RM8(modrm); dst = LOAD_REG8(modrm); - dst = XOR8(dst, src); + dst = XOR8(cpustate,dst, src); STORE_REG8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ8(ea); + UINT32 ea = GetEA(cpustate,modrm); + src = READ8(cpustate,ea); dst = LOAD_REG8(modrm); - dst = XOR8(dst, src); + dst = XOR8(cpustate,dst, src); STORE_REG8(modrm, dst); - CYCLES(CYCLES_ALU_MEM_REG); + CYCLES(cpustate,CYCLES_ALU_MEM_REG); } } -static void I386OP(xor_al_i8)(void) // Opcode 0x34 +static void I386OP(xor_al_i8)(i386_state *cpustate) // Opcode 0x34 { UINT8 src, dst; - src = FETCH(); + src = FETCH(cpustate); dst = REG8(AL); - dst = XOR8(dst, src); + dst = XOR8(cpustate,dst, src); REG8(AL) = dst; - CYCLES(CYCLES_ALU_IMM_ACC); + CYCLES(cpustate,CYCLES_ALU_IMM_ACC); } -static void I386OP(group80_8)(void) // Opcode 0x80 +static void I386OP(group80_8)(i386_state *cpustate) // Opcode 0x80 { UINT32 ea; UINT8 src, dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); switch( (modrm >> 3) & 0x7 ) { case 0: // ADD Rm8, i8 if( modrm >= 0xc0 ) { dst = LOAD_RM8(modrm); - src = FETCH(); - dst = ADD8(dst, src); + src = FETCH(cpustate); + dst = ADD8(cpustate,dst, src); STORE_RM8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ8(ea); - src = FETCH(); - dst = ADD8(dst, src); - WRITE8(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ8(cpustate,ea); + src = FETCH(cpustate); + dst = ADD8(cpustate,dst, src); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 1: // OR Rm8, i8 if( modrm >= 0xc0 ) { dst = LOAD_RM8(modrm); - src = FETCH(); - dst = OR8(dst, src); + src = FETCH(cpustate); + dst = OR8(cpustate,dst, src); STORE_RM8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ8(ea); - src = FETCH(); - dst = OR8(dst, src); - WRITE8(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ8(cpustate,ea); + src = FETCH(cpustate); + dst = OR8(cpustate,dst, src); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 2: // ADC Rm8, i8 if( modrm >= 0xc0 ) { dst = LOAD_RM8(modrm); - src = FETCH(); - src = ADD8(src, I.CF); - dst = ADD8(dst, src); + src = FETCH(cpustate); + src = ADD8(cpustate,src, cpustate->CF); + dst = ADD8(cpustate,dst, src); STORE_RM8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ8(ea); - src = FETCH(); - src = ADD8(src, I.CF); - dst = ADD8(dst, src); - WRITE8(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ8(cpustate,ea); + src = FETCH(cpustate); + src = ADD8(cpustate,src, cpustate->CF); + dst = ADD8(cpustate,dst, src); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 3: // SBB Rm8, i8 if( modrm >= 0xc0 ) { dst = LOAD_RM8(modrm); - src = FETCH() + I.CF; - dst = SUB8(dst, src); + src = FETCH(cpustate) + cpustate->CF; + dst = SUB8(cpustate,dst, src); STORE_RM8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ8(ea); - src = FETCH() + I.CF; - dst = SUB8(dst, src); - WRITE8(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ8(cpustate,ea); + src = FETCH(cpustate) + cpustate->CF; + dst = SUB8(cpustate,dst, src); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 4: // AND Rm8, i8 if( modrm >= 0xc0 ) { dst = LOAD_RM8(modrm); - src = FETCH(); - dst = AND8(dst, src); + src = FETCH(cpustate); + dst = AND8(cpustate,dst, src); STORE_RM8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ8(ea); - src = FETCH(); - dst = AND8(dst, src); - WRITE8(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ8(cpustate,ea); + src = FETCH(cpustate); + dst = AND8(cpustate,dst, src); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 5: // SUB Rm8, i8 if( modrm >= 0xc0 ) { dst = LOAD_RM8(modrm); - src = FETCH(); - dst = SUB8(dst, src); + src = FETCH(cpustate); + dst = SUB8(cpustate,dst, src); STORE_RM8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ8(ea); - src = FETCH(); - dst = SUB8(dst, src); - WRITE8(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ8(cpustate,ea); + src = FETCH(cpustate); + dst = SUB8(cpustate,dst, src); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 6: // XOR Rm8, i8 if( modrm >= 0xc0 ) { dst = LOAD_RM8(modrm); - src = FETCH(); - dst = XOR8(dst, src); + src = FETCH(cpustate); + dst = XOR8(cpustate,dst, src); STORE_RM8(modrm, dst); - CYCLES(CYCLES_ALU_REG_REG); + CYCLES(cpustate,CYCLES_ALU_REG_REG); } else { - ea = GetEA(modrm); - dst = READ8(ea); - src = FETCH(); - dst = XOR8(dst, src); - WRITE8(ea, dst); - CYCLES(CYCLES_ALU_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ8(cpustate,ea); + src = FETCH(cpustate); + dst = XOR8(cpustate,dst, src); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_ALU_REG_MEM); } break; case 7: // CMP Rm8, i8 if( modrm >= 0xc0 ) { dst = LOAD_RM8(modrm); - src = FETCH(); - SUB8(dst, src); - CYCLES(CYCLES_CMP_REG_REG); + src = FETCH(cpustate); + SUB8(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_REG); } else { - ea = GetEA(modrm); - dst = READ8(ea); - src = FETCH(); - SUB8(dst, src); - CYCLES(CYCLES_CMP_REG_MEM); + ea = GetEA(cpustate,modrm); + dst = READ8(cpustate,ea); + src = FETCH(cpustate); + SUB8(cpustate,dst, src); + CYCLES(cpustate,CYCLES_CMP_REG_MEM); } break; } } -static void I386OP(groupC0_8)(void) // Opcode 0xc0 +static void I386OP(groupC0_8)(i386_state *cpustate) // Opcode 0xc0 { UINT8 dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT8 shift; if( modrm >= 0xc0 ) { dst = LOAD_RM8(modrm); - shift = FETCH() & 0x1f; - dst = i386_shift_rotate8(modrm, dst, shift); + shift = FETCH(cpustate) & 0x1f; + dst = i386_shift_rotate8(cpustate, modrm, dst, shift); STORE_RM8(modrm, dst); } else { - UINT32 ea = GetEA(modrm); - dst = READ8(ea); - shift = FETCH() & 0x1f; - dst = i386_shift_rotate8(modrm, dst, shift); - WRITE8(ea, dst); + UINT32 ea = GetEA(cpustate,modrm); + dst = READ8(cpustate,ea); + shift = FETCH(cpustate) & 0x1f; + dst = i386_shift_rotate8(cpustate, modrm, dst, shift); + WRITE8(cpustate,ea, dst); } } -static void I386OP(groupD0_8)(void) // Opcode 0xd0 +static void I386OP(groupD0_8)(i386_state *cpustate) // Opcode 0xd0 { UINT8 dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { dst = LOAD_RM8(modrm); - dst = i386_shift_rotate8(modrm, dst, 1); + dst = i386_shift_rotate8(cpustate, modrm, dst, 1); STORE_RM8(modrm, dst); } else { - UINT32 ea = GetEA(modrm); - dst = READ8(ea); - dst = i386_shift_rotate8(modrm, dst, 1); - WRITE8(ea, dst); + UINT32 ea = GetEA(cpustate,modrm); + dst = READ8(cpustate,ea); + dst = i386_shift_rotate8(cpustate, modrm, dst, 1); + WRITE8(cpustate,ea, dst); } } -static void I386OP(groupD2_8)(void) // Opcode 0xd2 +static void I386OP(groupD2_8)(i386_state *cpustate) // Opcode 0xd2 { UINT8 dst; - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { dst = LOAD_RM8(modrm); - dst = i386_shift_rotate8(modrm, dst, REG8(CL)); + dst = i386_shift_rotate8(cpustate, modrm, dst, REG8(CL)); STORE_RM8(modrm, dst); } else { - UINT32 ea = GetEA(modrm); - dst = READ8(ea); - dst = i386_shift_rotate8(modrm, dst, REG8(CL)); - WRITE8(ea, dst); + UINT32 ea = GetEA(cpustate,modrm); + dst = READ8(cpustate,ea); + dst = i386_shift_rotate8(cpustate, modrm, dst, REG8(CL)); + WRITE8(cpustate,ea, dst); } } -static void I386OP(groupF6_8)(void) // Opcode 0xf6 +static void I386OP(groupF6_8)(i386_state *cpustate) // Opcode 0xf6 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); switch( (modrm >> 3) & 0x7 ) { case 0: /* TEST Rm8, i8 */ if( modrm >= 0xc0 ) { UINT8 dst = LOAD_RM8(modrm); - UINT8 src = FETCH(); + UINT8 src = FETCH(cpustate); dst &= src; - I.CF = I.OF = I.AF = 0; + cpustate->CF = cpustate->OF = cpustate->AF = 0; SetSZPF8(dst); - CYCLES(CYCLES_TEST_IMM_REG); + CYCLES(cpustate,CYCLES_TEST_IMM_REG); } else { - UINT32 ea = GetEA(modrm); - UINT8 dst = READ8(ea); - UINT8 src = FETCH(); + UINT32 ea = GetEA(cpustate,modrm); + UINT8 dst = READ8(cpustate,ea); + UINT8 src = FETCH(cpustate); dst &= src; - I.CF = I.OF = I.AF = 0; + cpustate->CF = cpustate->OF = cpustate->AF = 0; SetSZPF8(dst); - CYCLES(CYCLES_TEST_IMM_MEM); + CYCLES(cpustate,CYCLES_TEST_IMM_MEM); } break; case 2: /* NOT Rm8 */ @@ -1885,27 +1885,27 @@ static void I386OP(groupF6_8)(void) // Opcode 0xf6 UINT8 dst = LOAD_RM8(modrm); dst = ~dst; STORE_RM8(modrm, dst); - CYCLES(CYCLES_NOT_REG); + CYCLES(cpustate,CYCLES_NOT_REG); } else { - UINT32 ea = GetEA(modrm); - UINT8 dst = READ8(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT8 dst = READ8(cpustate,ea); dst = ~dst; - WRITE8(ea, dst); - CYCLES(CYCLES_NOT_MEM); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_NOT_MEM); } break; case 3: /* NEG Rm8 */ if( modrm >= 0xc0 ) { UINT8 dst = LOAD_RM8(modrm); - dst = SUB8( 0, dst ); + dst = SUB8(cpustate, 0, dst ); STORE_RM8(modrm, dst); - CYCLES(CYCLES_NEG_REG); + CYCLES(cpustate,CYCLES_NEG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT8 dst = READ8(ea); - dst = SUB8( 0, dst ); - WRITE8(ea, dst); - CYCLES(CYCLES_NEG_MEM); + UINT32 ea = GetEA(cpustate,modrm); + UINT8 dst = READ8(cpustate,ea); + dst = SUB8(cpustate, 0, dst ); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_NEG_MEM); } break; case 4: /* MUL AL, Rm8 */ @@ -1914,18 +1914,18 @@ static void I386OP(groupF6_8)(void) // Opcode 0xf6 UINT8 src, dst; if( modrm >= 0xc0 ) { src = LOAD_RM8(modrm); - CYCLES(CYCLES_MUL8_ACC_REG); /* TODO: Correct multiply timing */ + CYCLES(cpustate,CYCLES_MUL8_ACC_REG); /* TODO: Correct multiply timing */ } else { - UINT32 ea = GetEA(modrm); - src = READ8(ea); - CYCLES(CYCLES_MUL8_ACC_MEM); /* TODO: Correct multiply timing */ + UINT32 ea = GetEA(cpustate,modrm); + src = READ8(cpustate,ea); + CYCLES(cpustate,CYCLES_MUL8_ACC_MEM); /* TODO: Correct multiply timing */ } dst = REG8(AL); result = (UINT16)src * (UINT16)dst; REG16(AX) = (UINT16)result; - I.CF = I.OF = (REG16(AX) > 0xff); + cpustate->CF = cpustate->OF = (REG16(AX) > 0xff); } break; case 5: /* IMUL AL, Rm8 */ @@ -1934,11 +1934,11 @@ static void I386OP(groupF6_8)(void) // Opcode 0xf6 INT16 src, dst; if( modrm >= 0xc0 ) { src = (INT16)(INT8)LOAD_RM8(modrm); - CYCLES(CYCLES_IMUL8_ACC_REG); /* TODO: Correct multiply timing */ + CYCLES(cpustate,CYCLES_IMUL8_ACC_REG); /* TODO: Correct multiply timing */ } else { - UINT32 ea = GetEA(modrm); - src = (INT16)(INT8)READ8(ea); - CYCLES(CYCLES_IMUL8_ACC_MEM); /* TODO: Correct multiply timing */ + UINT32 ea = GetEA(cpustate,modrm); + src = (INT16)(INT8)READ8(cpustate,ea); + CYCLES(cpustate,CYCLES_IMUL8_ACC_MEM); /* TODO: Correct multiply timing */ } dst = (INT16)(INT8)REG8(AL); @@ -1946,7 +1946,7 @@ static void I386OP(groupF6_8)(void) // Opcode 0xf6 REG16(AX) = (UINT16)result; - I.CF = I.OF = !(result == (INT16)(INT8)result); + cpustate->CF = cpustate->OF = !(result == (INT16)(INT8)result); } break; case 6: /* DIV AL, Rm8 */ @@ -1955,11 +1955,11 @@ static void I386OP(groupF6_8)(void) // Opcode 0xf6 UINT8 src; if( modrm >= 0xc0 ) { src = LOAD_RM8(modrm); - CYCLES(CYCLES_DIV8_ACC_REG); + CYCLES(cpustate,CYCLES_DIV8_ACC_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ8(ea); - CYCLES(CYCLES_DIV8_ACC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + src = READ8(cpustate,ea); + CYCLES(cpustate,CYCLES_DIV8_ACC_MEM); } quotient = (UINT16)REG16(AX); @@ -1983,11 +1983,11 @@ static void I386OP(groupF6_8)(void) // Opcode 0xf6 UINT8 src; if( modrm >= 0xc0 ) { src = LOAD_RM8(modrm); - CYCLES(CYCLES_IDIV8_ACC_REG); + CYCLES(cpustate,CYCLES_IDIV8_ACC_REG); } else { - UINT32 ea = GetEA(modrm); - src = READ8(ea); - CYCLES(CYCLES_IDIV8_ACC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + src = READ8(cpustate,ea); + CYCLES(cpustate,CYCLES_IDIV8_ACC_MEM); } quotient = (INT16)REG16(AX); @@ -2008,38 +2008,38 @@ static void I386OP(groupF6_8)(void) // Opcode 0xf6 } } -static void I386OP(groupFE_8)(void) // Opcode 0xfe +static void I386OP(groupFE_8)(i386_state *cpustate) // Opcode 0xfe { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); switch( (modrm >> 3) & 0x7 ) { case 0: /* INC Rm8 */ if( modrm >= 0xc0 ) { UINT8 dst = LOAD_RM8(modrm); - dst = INC8(dst); + dst = INC8(cpustate,dst); STORE_RM8(modrm, dst); - CYCLES(CYCLES_INC_REG); + CYCLES(cpustate,CYCLES_INC_REG); } else { - UINT32 ea = GetEA(modrm); - UINT8 dst = READ8(ea); - dst = INC8(dst); - WRITE8(ea, dst); - CYCLES(CYCLES_INC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + UINT8 dst = READ8(cpustate,ea); + dst = INC8(cpustate,dst); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_INC_MEM); } break; case 1: /* DEC Rm8 */ if( modrm >= 0xc0 ) { UINT8 dst = LOAD_RM8(modrm); - dst = DEC8(dst); + dst = DEC8(cpustate,dst); STORE_RM8(modrm, dst); - CYCLES(CYCLES_DEC_REG); + CYCLES(cpustate,CYCLES_DEC_REG); } else { - UINT32 ea = GetEA(modrm); - UINT8 dst = READ8(ea); - dst = DEC8(dst); - WRITE8(ea, dst); - CYCLES(CYCLES_DEC_MEM); + UINT32 ea = GetEA(cpustate,modrm); + UINT8 dst = READ8(cpustate,ea); + dst = DEC8(cpustate,dst); + WRITE8(cpustate,ea, dst); + CYCLES(cpustate,CYCLES_DEC_MEM); } break; case 6: /* PUSH Rm8 */ @@ -2048,15 +2048,15 @@ static void I386OP(groupFE_8)(void) // Opcode 0xfe if( modrm >= 0xc0 ) { value = LOAD_RM8(modrm); } else { - UINT32 ea = GetEA(modrm); - value = READ8(ea); + UINT32 ea = GetEA(cpustate,modrm); + value = READ8(cpustate,ea); } - if( I.operand_size ) { - PUSH32(value); + if( cpustate->operand_size ) { + PUSH32(cpustate,value); } else { - PUSH16(value); + PUSH16(cpustate,value); } - CYCLES(CYCLES_PUSH_RM); + CYCLES(cpustate,CYCLES_PUSH_RM); } break; default: @@ -2067,240 +2067,240 @@ static void I386OP(groupFE_8)(void) // Opcode 0xfe -static void I386OP(segment_CS)(void) // Opcode 0x2e +static void I386OP(segment_CS)(i386_state *cpustate) // Opcode 0x2e { - I.segment_prefix = 1; - I.segment_override = CS; + cpustate->segment_prefix = 1; + cpustate->segment_override = CS; - I386OP(decode_opcode)(); + I386OP(decode_opcode)(cpustate); } -static void I386OP(segment_DS)(void) // Opcode 0x3e +static void I386OP(segment_DS)(i386_state *cpustate) // Opcode 0x3e { - I.segment_prefix = 1; - I.segment_override = DS; - CYCLES(0); // TODO: Specify cycle count - I386OP(decode_opcode)(); + cpustate->segment_prefix = 1; + cpustate->segment_override = DS; + CYCLES(cpustate,0); // TODO: Specify cycle count + I386OP(decode_opcode)(cpustate); } -static void I386OP(segment_ES)(void) // Opcode 0x26 +static void I386OP(segment_ES)(i386_state *cpustate) // Opcode 0x26 { - I.segment_prefix = 1; - I.segment_override = ES; - CYCLES(0); // TODO: Specify cycle count - I386OP(decode_opcode)(); + cpustate->segment_prefix = 1; + cpustate->segment_override = ES; + CYCLES(cpustate,0); // TODO: Specify cycle count + I386OP(decode_opcode)(cpustate); } -static void I386OP(segment_FS)(void) // Opcode 0x64 +static void I386OP(segment_FS)(i386_state *cpustate) // Opcode 0x64 { - I.segment_prefix = 1; - I.segment_override = FS; - CYCLES(1); // TODO: Specify cycle count - I386OP(decode_opcode)(); + cpustate->segment_prefix = 1; + cpustate->segment_override = FS; + CYCLES(cpustate,1); // TODO: Specify cycle count + I386OP(decode_opcode)(cpustate); } -static void I386OP(segment_GS)(void) // Opcode 0x65 +static void I386OP(segment_GS)(i386_state *cpustate) // Opcode 0x65 { - I.segment_prefix = 1; - I.segment_override = GS; - CYCLES(1); // TODO: Specify cycle count - I386OP(decode_opcode)(); + cpustate->segment_prefix = 1; + cpustate->segment_override = GS; + CYCLES(cpustate,1); // TODO: Specify cycle count + I386OP(decode_opcode)(cpustate); } -static void I386OP(segment_SS)(void) // Opcode 0x36 +static void I386OP(segment_SS)(i386_state *cpustate) // Opcode 0x36 { - I.segment_prefix = 1; - I.segment_override = SS; - CYCLES(0); // TODO: Specify cycle count - I386OP(decode_opcode)(); + cpustate->segment_prefix = 1; + cpustate->segment_override = SS; + CYCLES(cpustate,0); // TODO: Specify cycle count + I386OP(decode_opcode)(cpustate); } -static void I386OP(operand_size)(void) // Opcode 0x66 +static void I386OP(operand_size)(i386_state *cpustate) // Opcode 0x66 { - I.operand_size ^= 1; - I386OP(decode_opcode)(); + cpustate->operand_size ^= 1; + I386OP(decode_opcode)(cpustate); } -static void I386OP(address_size)(void) // Opcode 0x67 +static void I386OP(address_size)(i386_state *cpustate) // Opcode 0x67 { - I.address_size ^= 1; - I386OP(decode_opcode)(); + cpustate->address_size ^= 1; + I386OP(decode_opcode)(cpustate); } -static void I386OP(nop)(void) // Opcode 0x90 +static void I386OP(nop)(i386_state *cpustate) // Opcode 0x90 { - CYCLES(CYCLES_NOP); + CYCLES(cpustate,CYCLES_NOP); } -static void I386OP(int3)(void) // Opcode 0xcc +static void I386OP(int3)(i386_state *cpustate) // Opcode 0xcc { - CYCLES(CYCLES_INT3); - i386_trap(3, 1); + CYCLES(cpustate,CYCLES_INT3); + i386_trap(cpustate,3, 1); } -static void I386OP(int)(void) // Opcode 0xcd +static void I386OP(int)(i386_state *cpustate) // Opcode 0xcd { - int interrupt = FETCH(); - CYCLES(CYCLES_INT); - i386_trap(interrupt, 1); + int interrupt = FETCH(cpustate); + CYCLES(cpustate,CYCLES_INT); + i386_trap(cpustate,interrupt, 1); } -static void I386OP(into)(void) // Opcode 0xce +static void I386OP(into)(i386_state *cpustate) // Opcode 0xce { - if( I.OF ) { - i386_trap(4, 1); - CYCLES(CYCLES_INTO_OF1); + if( cpustate->OF ) { + i386_trap(cpustate,4, 1); + CYCLES(cpustate,CYCLES_INTO_OF1); } else { - CYCLES(CYCLES_INTO_OF0); + CYCLES(cpustate,CYCLES_INTO_OF0); } } -static void I386OP(escape)(void) // Opcodes 0xd8 - 0xdf +static void I386OP(escape)(i386_state *cpustate) // Opcodes 0xd8 - 0xdf { - UINT8 modrm = FETCH(); - CYCLES(3); // TODO: confirm this + UINT8 modrm = FETCH(cpustate); + CYCLES(cpustate,3); // TODO: confirm this (void) LOAD_RM8(modrm); } -static void I386OP(hlt)(void) // Opcode 0xf4 +static void I386OP(hlt)(i386_state *cpustate) // Opcode 0xf4 { // TODO: We need to raise an exception in protected mode and when // the current privilege level is not zero - I.halted = 1; - I.cycles = 0; - CYCLES(CYCLES_HLT); + cpustate->halted = 1; + cpustate->cycles = 0; + CYCLES(cpustate,CYCLES_HLT); } -static void I386OP(decimal_adjust)(int direction) +static void I386OP(decimal_adjust)(i386_state *cpustate, int direction) { UINT8 tmpAL = REG8(AL); - if (I.AF || ((REG8(AL) & 0xf) > 9)) + if (cpustate->AF || ((REG8(AL) & 0xf) > 9)) { REG8(AL) = REG8(AL) + (direction * 0x06); - I.AF = 1; + cpustate->AF = 1; if (REG8(AL) & 0x100) - I.CF = 1; + cpustate->CF = 1; if (direction > 0) tmpAL = REG8(AL); } - if (I.CF || (tmpAL > 0x9f)) + if (cpustate->CF || (tmpAL > 0x9f)) { REG8(AL) += (direction * 0x60); - I.CF = 1; + cpustate->CF = 1; } SetSZPF8(REG8(AL)); } -static void I386OP(daa)(void) // Opcode 0x27 +static void I386OP(daa)(i386_state *cpustate) // Opcode 0x27 { - I386OP(decimal_adjust)(+1); - CYCLES(CYCLES_DAA); + I386OP(decimal_adjust)(cpustate, +1); + CYCLES(cpustate,CYCLES_DAA); } -static void I386OP(das)(void) // Opcode 0x2f +static void I386OP(das)(i386_state *cpustate) // Opcode 0x2f { - I386OP(decimal_adjust)(-1); - CYCLES(CYCLES_DAS); + I386OP(decimal_adjust)(cpustate, -1); + CYCLES(cpustate,CYCLES_DAS); } -static void I386OP(aaa)(void) // Opcode 0x37 +static void I386OP(aaa)(i386_state *cpustate) // Opcode 0x37 { - if( (REG8(AL) & 0x0f) || I.AF != 0 ) { + if( (REG8(AL) & 0x0f) || cpustate->AF != 0 ) { REG16(AX) = REG16(AX) + 6; REG8(AH) = REG8(AH) + 1; - I.AF = 1; - I.CF = 1; + cpustate->AF = 1; + cpustate->CF = 1; } else { - I.AF = 0; - I.CF = 0; + cpustate->AF = 0; + cpustate->CF = 0; } REG8(AL) = REG8(AL) & 0x0f; - CYCLES(CYCLES_AAA); + CYCLES(cpustate,CYCLES_AAA); } -static void I386OP(aas)(void) // Opcode 0x3f +static void I386OP(aas)(i386_state *cpustate) // Opcode 0x3f { - if (I.AF || ((REG8(AL) & 0xf) > 9)) + if (cpustate->AF || ((REG8(AL) & 0xf) > 9)) { REG16(AX) -= 6; REG8(AH) -= 1; - I.AF = 1; - I.CF = 1; + cpustate->AF = 1; + cpustate->CF = 1; } else { - I.AF = 0; - I.CF = 0; + cpustate->AF = 0; + cpustate->CF = 0; } REG8(AL) &= 0x0f; - CYCLES(CYCLES_AAS); + CYCLES(cpustate,CYCLES_AAS); } -static void I386OP(aad)(void) // Opcode 0xd5 +static void I386OP(aad)(i386_state *cpustate) // Opcode 0xd5 { UINT8 tempAL = REG8(AL); UINT8 tempAH = REG8(AH); - UINT8 i = FETCH(); + UINT8 i = FETCH(cpustate); REG8(AL) = (tempAL + (tempAH * i)) & 0xff; REG8(AH) = 0; SetSZPF8( REG8(AL) ); - CYCLES(CYCLES_AAD); + CYCLES(cpustate,CYCLES_AAD); } -static void I386OP(aam)(void) // Opcode 0xd4 +static void I386OP(aam)(i386_state *cpustate) // Opcode 0xd4 { UINT8 tempAL = REG8(AL); - UINT8 i = FETCH(); + UINT8 i = FETCH(cpustate); REG8(AH) = tempAL / i; REG8(AL) = tempAL % i; SetSZPF8( REG8(AL) ); - CYCLES(CYCLES_AAM); + CYCLES(cpustate,CYCLES_AAM); } -static void I386OP(clts)(void) // Opcode 0x0f 0x06 +static void I386OP(clts)(i386_state *cpustate) // Opcode 0x0f 0x06 { // TODO: #GP(0) is executed - I.cr[0] &= ~0x08; /* clear TS bit */ - CYCLES(CYCLES_CLTS); + cpustate->cr[0] &= ~0x08; /* clear TS bit */ + CYCLES(cpustate,CYCLES_CLTS); } -static void I386OP(wait)(void) // Opcode 0x9B +static void I386OP(wait)(i386_state *cpustate) // Opcode 0x9B { // TODO } -static void I386OP(lock)(void) // Opcode 0xf0 +static void I386OP(lock)(i386_state *cpustate) // Opcode 0xf0 { - CYCLES(CYCLES_LOCK); // TODO: Determine correct cycle count - I386OP(decode_opcode)(); + CYCLES(cpustate,CYCLES_LOCK); // TODO: Determine correct cycle count + I386OP(decode_opcode)(cpustate); } -static void I386OP(mov_r32_tr)(void) // Opcode 0x0f 24 +static void I386OP(mov_r32_tr)(i386_state *cpustate) // Opcode 0x0f 24 { - FETCH(); - CYCLES(1); // TODO: correct cycle count + FETCH(cpustate); + CYCLES(cpustate,1); // TODO: correct cycle count } -static void I386OP(mov_tr_r32)(void) // Opcode 0x0f 26 +static void I386OP(mov_tr_r32)(i386_state *cpustate) // Opcode 0x0f 26 { - FETCH(); - CYCLES(1); // TODO: correct cycle count + FETCH(cpustate); + CYCLES(cpustate,1); // TODO: correct cycle count } -static void I386OP(unimplemented)(void) +static void I386OP(unimplemented)(i386_state *cpustate) { - fatalerror("i386: Unimplemented opcode %02X at %08X", I.opcode, I.pc - 1 ); + fatalerror("i386: Unimplemented opcode %02X at %08X", cpustate->opcode, cpustate->pc - 1 ); } -static void I386OP(invalid)(void) +static void I386OP(invalid)(i386_state *cpustate) { - //i386_trap(6); - fatalerror("i386: Invalid opcode %02X at %08X", I.opcode, I.pc - 1); + //i386_trap(cpustate,6); + fatalerror("i386: Invalid opcode %02X at %08X", cpustate->opcode, cpustate->pc - 1); } diff --git a/src/emu/cpu/i386/i386ops.h b/src/emu/cpu/i386/i386ops.h index 797d89f6b72..9d7b7e644e8 100644 --- a/src/emu/cpu/i386/i386ops.h +++ b/src/emu/cpu/i386/i386ops.h @@ -1,8 +1,8 @@ typedef struct { UINT8 opcode; UINT32 flags; - void (*handler16)(void); - void (*handler32)(void); + void (*handler16)(i386_state *cpustate); + void (*handler32)(i386_state *cpustate); } X86_OPCODE; #define OP_I386 0x1 diff --git a/src/emu/cpu/i386/i486ops.c b/src/emu/cpu/i386/i486ops.c index f14d6a6feab..0b37826c8bd 100644 --- a/src/emu/cpu/i386/i486ops.c +++ b/src/emu/cpu/i386/i486ops.c @@ -1,199 +1,199 @@ // Intel 486+ specific opcodes -static void I486OP(cpuid)(void) // Opcode 0x0F A2 +static void I486OP(cpuid)(i386_state *cpustate) // Opcode 0x0F A2 { switch (REG32(EAX)) { case 0: { - REG32(EAX) = I.cpuid_max_input_value_eax; - REG32(EBX) = I.cpuid_id0; - REG32(ECX) = I.cpuid_id2; - REG32(EDX) = I.cpuid_id1; - CYCLES(CYCLES_CPUID); + REG32(EAX) = cpustate->cpuid_max_input_value_eax; + REG32(EBX) = cpustate->cpuid_id0; + REG32(ECX) = cpustate->cpuid_id2; + REG32(EDX) = cpustate->cpuid_id1; + CYCLES(cpustate,CYCLES_CPUID); break; } case 1: { - REG32(EAX) = I.cpu_version; - REG32(EDX) = I.feature_flags; - CYCLES(CYCLES_CPUID_EAX1); + REG32(EAX) = cpustate->cpu_version; + REG32(EDX) = cpustate->feature_flags; + CYCLES(cpustate,CYCLES_CPUID_EAX1); break; } } } -static void I486OP(invd)(void) // Opcode 0x0f 08 +static void I486OP(invd)(i386_state *cpustate) // Opcode 0x0f 08 { // Nothing to do ? - CYCLES(CYCLES_INVD); + CYCLES(cpustate,CYCLES_INVD); } -static void I486OP(wbinvd)(void) // Opcode 0x0f 09 +static void I486OP(wbinvd)(i386_state *cpustate) // Opcode 0x0f 09 { // Nothing to do ? } -static void I486OP(cmpxchg_rm8_r8)(void) // Opcode 0x0f b0 +static void I486OP(cmpxchg_rm8_r8)(i386_state *cpustate) // Opcode 0x0f b0 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT8 dst = LOAD_RM8(modrm); UINT8 src = LOAD_REG8(modrm); if( REG8(AL) == dst ) { STORE_RM8(modrm, src); - I.ZF = 1; - CYCLES(CYCLES_CMPXCHG_REG_REG_T); + cpustate->ZF = 1; + CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_T); } else { REG8(AL) = dst; - I.ZF = 0; - CYCLES(CYCLES_CMPXCHG_REG_REG_F); + cpustate->ZF = 0; + CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_F); } } else { - UINT32 ea = GetEA(modrm); - UINT8 dst = READ8(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT8 dst = READ8(cpustate,ea); UINT8 src = LOAD_REG8(modrm); if( REG8(AL) == dst ) { - WRITE8(modrm, src); - I.ZF = 1; - CYCLES(CYCLES_CMPXCHG_REG_MEM_T); + WRITE8(cpustate,modrm, src); + cpustate->ZF = 1; + CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_T); } else { REG8(AL) = dst; - I.ZF = 0; - CYCLES(CYCLES_CMPXCHG_REG_MEM_F); + cpustate->ZF = 0; + CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_F); } } } -static void I486OP(cmpxchg_rm16_r16)(void) // Opcode 0x0f b1 +static void I486OP(cmpxchg_rm16_r16)(i386_state *cpustate) // Opcode 0x0f b1 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT16 dst = LOAD_RM16(modrm); UINT16 src = LOAD_REG16(modrm); if( REG16(AX) == dst ) { STORE_RM16(modrm, src); - I.ZF = 1; - CYCLES(CYCLES_CMPXCHG_REG_REG_T); + cpustate->ZF = 1; + CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_T); } else { REG16(AX) = dst; - I.ZF = 0; - CYCLES(CYCLES_CMPXCHG_REG_REG_F); + cpustate->ZF = 0; + CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_F); } } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); UINT16 src = LOAD_REG16(modrm); if( REG16(AX) == dst ) { - WRITE16(modrm, src); - I.ZF = 1; - CYCLES(CYCLES_CMPXCHG_REG_MEM_T); + WRITE16(cpustate,modrm, src); + cpustate->ZF = 1; + CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_T); } else { REG16(AX) = dst; - I.ZF = 0; - CYCLES(CYCLES_CMPXCHG_REG_MEM_F); + cpustate->ZF = 0; + CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_F); } } } -static void I486OP(cmpxchg_rm32_r32)(void) // Opcode 0x0f b1 +static void I486OP(cmpxchg_rm32_r32)(i386_state *cpustate) // Opcode 0x0f b1 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); UINT32 src = LOAD_REG32(modrm); if( REG32(EAX) == dst ) { STORE_RM32(modrm, src); - I.ZF = 1; - CYCLES(CYCLES_CMPXCHG_REG_REG_T); + cpustate->ZF = 1; + CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_T); } else { REG32(EAX) = dst; - I.ZF = 0; - CYCLES(CYCLES_CMPXCHG_REG_REG_F); + cpustate->ZF = 0; + CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_F); } } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); UINT32 src = LOAD_REG32(modrm); if( REG32(EAX) == dst ) { - WRITE32(ea, src); - I.ZF = 1; - CYCLES(CYCLES_CMPXCHG_REG_MEM_T); + WRITE32(cpustate,ea, src); + cpustate->ZF = 1; + CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_T); } else { REG32(EAX) = dst; - I.ZF = 0; - CYCLES(CYCLES_CMPXCHG_REG_MEM_F); + cpustate->ZF = 0; + CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_F); } } } -static void I486OP(xadd_rm8_r8)(void) // Opcode 0x0f c0 +static void I486OP(xadd_rm8_r8)(i386_state *cpustate) // Opcode 0x0f c0 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT8 dst = LOAD_RM8(modrm); UINT8 src = LOAD_REG8(modrm); STORE_RM16(modrm, dst + src); STORE_REG16(modrm, dst); - CYCLES(CYCLES_XADD_REG_REG); + CYCLES(cpustate,CYCLES_XADD_REG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT8 dst = READ8(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT8 dst = READ8(cpustate,ea); UINT8 src = LOAD_REG8(modrm); - WRITE8(ea, dst + src); + WRITE8(cpustate,ea, dst + src); STORE_REG8(modrm, dst); - CYCLES(CYCLES_XADD_REG_MEM); + CYCLES(cpustate,CYCLES_XADD_REG_MEM); } } -static void I486OP(xadd_rm16_r16)(void) // Opcode 0x0f c1 +static void I486OP(xadd_rm16_r16)(i386_state *cpustate) // Opcode 0x0f c1 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT16 dst = LOAD_RM16(modrm); UINT16 src = LOAD_REG16(modrm); STORE_RM16(modrm, dst + src); STORE_REG16(modrm, dst); - CYCLES(CYCLES_XADD_REG_REG); + CYCLES(cpustate,CYCLES_XADD_REG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT16 dst = READ16(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT16 dst = READ16(cpustate,ea); UINT16 src = LOAD_REG16(modrm); - WRITE16(ea, dst + src); + WRITE16(cpustate,ea, dst + src); STORE_REG16(modrm, dst); - CYCLES(CYCLES_XADD_REG_MEM); + CYCLES(cpustate,CYCLES_XADD_REG_MEM); } } -static void I486OP(xadd_rm32_r32)(void) // Opcode 0x0f c1 +static void I486OP(xadd_rm32_r32)(i386_state *cpustate) // Opcode 0x0f c1 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT32 dst = LOAD_RM32(modrm); UINT32 src = LOAD_REG32(modrm); STORE_RM32(modrm, dst + src); STORE_REG32(modrm, dst); - CYCLES(CYCLES_XADD_REG_REG); + CYCLES(cpustate,CYCLES_XADD_REG_REG); } else { - UINT32 ea = GetEA(modrm); - UINT32 dst = READ32(ea); + UINT32 ea = GetEA(cpustate,modrm); + UINT32 dst = READ32(cpustate,ea); UINT32 src = LOAD_REG32(modrm); - WRITE32(ea, dst + src); + WRITE32(cpustate,ea, dst + src); STORE_REG32(modrm, dst); - CYCLES(CYCLES_XADD_REG_MEM); + CYCLES(cpustate,CYCLES_XADD_REG_MEM); } } -static void I486OP(group0F01_16)(void) // Opcode 0x0f 01 +static void I486OP(group0F01_16)(i386_state *cpustate) // Opcode 0x0f 01 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT16 address; UINT32 ea; @@ -203,13 +203,13 @@ static void I486OP(group0F01_16)(void) // Opcode 0x0f 01 { if( modrm >= 0xc0 ) { address = LOAD_RM16(modrm); - ea = i386_translate( CS, address ); + ea = i386_translate( cpustate, CS, address ); } else { - ea = GetEA(modrm); + ea = GetEA(cpustate,modrm); } - WRITE16(ea, I.gdtr.limit); - WRITE32(ea + 2, I.gdtr.base & 0xffffff); - CYCLES(CYCLES_SGDT); + WRITE16(cpustate,ea, cpustate->gdtr.limit); + WRITE32(cpustate,ea + 2, cpustate->gdtr.base & 0xffffff); + CYCLES(cpustate,CYCLES_SGDT); break; } case 1: /* SIDT */ @@ -217,52 +217,52 @@ static void I486OP(group0F01_16)(void) // Opcode 0x0f 01 if (modrm >= 0xc0) { address = LOAD_RM16(modrm); - ea = i386_translate( CS, address ); + ea = i386_translate( cpustate, CS, address ); } else { - ea = GetEA(modrm); + ea = GetEA(cpustate,modrm); } - WRITE16(ea, I.idtr.limit); - WRITE32(ea + 2, I.idtr.base & 0xffffff); - CYCLES(CYCLES_SIDT); + WRITE16(cpustate,ea, cpustate->idtr.limit); + WRITE32(cpustate,ea + 2, cpustate->idtr.base & 0xffffff); + CYCLES(cpustate,CYCLES_SIDT); break; } case 2: /* LGDT */ { if( modrm >= 0xc0 ) { address = LOAD_RM16(modrm); - ea = i386_translate( CS, address ); + ea = i386_translate( cpustate, CS, address ); } else { - ea = GetEA(modrm); + ea = GetEA(cpustate,modrm); } - I.gdtr.limit = READ16(ea); - I.gdtr.base = READ32(ea + 2) & 0xffffff; - CYCLES(CYCLES_LGDT); + cpustate->gdtr.limit = READ16(cpustate,ea); + cpustate->gdtr.base = READ32(cpustate,ea + 2) & 0xffffff; + CYCLES(cpustate,CYCLES_LGDT); break; } case 3: /* LIDT */ { if( modrm >= 0xc0 ) { address = LOAD_RM16(modrm); - ea = i386_translate( CS, address ); + ea = i386_translate( cpustate, CS, address ); } else { - ea = GetEA(modrm); + ea = GetEA(cpustate,modrm); } - I.idtr.limit = READ16(ea); - I.idtr.base = READ32(ea + 2) & 0xffffff; - CYCLES(CYCLES_LIDT); + cpustate->idtr.limit = READ16(cpustate,ea); + cpustate->idtr.base = READ32(cpustate,ea + 2) & 0xffffff; + CYCLES(cpustate,CYCLES_LIDT); break; } case 4: /* SMSW */ { if( modrm >= 0xc0 ) { - STORE_RM16(modrm, I.cr[0]); - CYCLES(CYCLES_SMSW_REG); + STORE_RM16(modrm, cpustate->cr[0]); + CYCLES(cpustate,CYCLES_SMSW_REG); } else { - UINT32 ea = GetEA(modrm); - WRITE16(ea, I.cr[0]); - CYCLES(CYCLES_SMSW_MEM); + UINT32 ea = GetEA(cpustate,modrm); + WRITE16(cpustate,ea, cpustate->cr[0]); + CYCLES(cpustate,CYCLES_SMSW_MEM); } break; } @@ -272,14 +272,14 @@ static void I486OP(group0F01_16)(void) // Opcode 0x0f 01 UINT8 b; if( modrm >= 0xc0 ) { b = LOAD_RM8(modrm); - CYCLES(CYCLES_LMSW_REG); + CYCLES(cpustate,CYCLES_LMSW_REG); } else { - ea = GetEA(modrm); - CYCLES(CYCLES_LMSW_MEM); - b = READ8(ea); + ea = GetEA(cpustate,modrm); + CYCLES(cpustate,CYCLES_LMSW_MEM); + b = READ8(cpustate,ea); } - I.cr[0] &= ~0x03; - I.cr[0] |= b & 0x03; + cpustate->cr[0] &= ~0x03; + cpustate->cr[0] |= b & 0x03; break; } case 7: /* INVLPG */ @@ -288,14 +288,14 @@ static void I486OP(group0F01_16)(void) // Opcode 0x0f 01 break; } default: - fatalerror("i486: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, I.eip - 2); + fatalerror("i486: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, cpustate->eip - 2); break; } } -static void I486OP(group0F01_32)(void) // Opcode 0x0f 01 +static void I486OP(group0F01_32)(i386_state *cpustate) // Opcode 0x0f 01 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); UINT32 address, ea; switch( (modrm >> 3) & 0x7 ) @@ -304,13 +304,13 @@ static void I486OP(group0F01_32)(void) // Opcode 0x0f 01 { if( modrm >= 0xc0 ) { address = LOAD_RM32(modrm); - ea = i386_translate( CS, address ); + ea = i386_translate( cpustate, CS, address ); } else { - ea = GetEA(modrm); + ea = GetEA(cpustate,modrm); } - WRITE16(ea, I.gdtr.limit); - WRITE32(ea + 2, I.gdtr.base); - CYCLES(CYCLES_SGDT); + WRITE16(cpustate,ea, cpustate->gdtr.limit); + WRITE32(cpustate,ea + 2, cpustate->gdtr.base); + CYCLES(cpustate,CYCLES_SGDT); break; } case 1: /* SIDT */ @@ -318,41 +318,41 @@ static void I486OP(group0F01_32)(void) // Opcode 0x0f 01 if (modrm >= 0xc0) { address = LOAD_RM32(modrm); - ea = i386_translate( CS, address ); + ea = i386_translate( cpustate, CS, address ); } else { - ea = GetEA(modrm); + ea = GetEA(cpustate,modrm); } - WRITE16(ea, I.idtr.limit); - WRITE32(ea + 2, I.idtr.base); - CYCLES(CYCLES_SIDT); + WRITE16(cpustate,ea, cpustate->idtr.limit); + WRITE32(cpustate,ea + 2, cpustate->idtr.base); + CYCLES(cpustate,CYCLES_SIDT); break; } case 2: /* LGDT */ { if( modrm >= 0xc0 ) { address = LOAD_RM32(modrm); - ea = i386_translate( CS, address ); + ea = i386_translate( cpustate, CS, address ); } else { - ea = GetEA(modrm); + ea = GetEA(cpustate,modrm); } - I.gdtr.limit = READ16(ea); - I.gdtr.base = READ32(ea + 2); - CYCLES(CYCLES_LGDT); + cpustate->gdtr.limit = READ16(cpustate,ea); + cpustate->gdtr.base = READ32(cpustate,ea + 2); + CYCLES(cpustate,CYCLES_LGDT); break; } case 3: /* LIDT */ { if( modrm >= 0xc0 ) { address = LOAD_RM32(modrm); - ea = i386_translate( CS, address ); + ea = i386_translate( cpustate, CS, address ); } else { - ea = GetEA(modrm); + ea = GetEA(cpustate,modrm); } - I.idtr.limit = READ16(ea); - I.idtr.base = READ32(ea + 2); - CYCLES(CYCLES_LIDT); + cpustate->idtr.limit = READ16(cpustate,ea); + cpustate->idtr.base = READ32(cpustate,ea + 2); + CYCLES(cpustate,CYCLES_LIDT); break; } case 7: /* INVLPG */ @@ -361,7 +361,7 @@ static void I486OP(group0F01_32)(void) // Opcode 0x0f 01 break; } default: - fatalerror("i486: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, I.eip - 2); + fatalerror("i486: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, cpustate->eip - 2); break; } } diff --git a/src/emu/cpu/i386/pentops.c b/src/emu/cpu/i386/pentops.c index b7fb394e301..6a6ee1aa187 100644 --- a/src/emu/cpu/i386/pentops.c +++ b/src/emu/cpu/i386/pentops.c @@ -1,51 +1,51 @@ // Pentium+ specific opcodes -static void PENTIUMOP(rdmsr)(void) // Opcode 0x0f 32 +static void PENTIUMOP(rdmsr)(i386_state *cpustate) // Opcode 0x0f 32 { // TODO - CYCLES(CYCLES_RDMSR); + CYCLES(cpustate,CYCLES_RDMSR); } -static void PENTIUMOP(wrmsr)(void) // Opcode 0x0f 30 +static void PENTIUMOP(wrmsr)(i386_state *cpustate) // Opcode 0x0f 30 { // TODO - CYCLES(1); // TODO: correct cycle count + CYCLES(cpustate,1); // TODO: correct cycle count } -static void PENTIUMOP(rdtsc)(void) // Opcode 0x0f 31 +static void PENTIUMOP(rdtsc)(i386_state *cpustate) // Opcode 0x0f 31 { - UINT64 ts = I.tsc + (I.base_cycles - I.cycles); + UINT64 ts = cpustate->tsc + (cpustate->base_cycles - cpustate->cycles); REG32(EAX) = (UINT32)(ts); REG32(EDX) = (UINT32)(ts >> 32); - CYCLES(CYCLES_RDTSC); + CYCLES(cpustate,CYCLES_RDTSC); } -static void I386OP(cyrix_unknown)(void) // Opcode 0x0f 74 +static void I386OP(cyrix_unknown)(i386_state *cpustate) // Opcode 0x0f 74 { - CYCLES(1); + CYCLES(cpustate,1); } -static void PENTIUMOP(cmpxchg8b_m64)(void) // Opcode 0x0f c7 +static void PENTIUMOP(cmpxchg8b_m64)(i386_state *cpustate) // Opcode 0x0f c7 { - UINT8 modm = FETCH(); + UINT8 modm = FETCH(cpustate); if( modm >= 0xc0 ) { fatalerror("invalid modm"); } else { - UINT32 ea = GetEA(modm); - UINT64 value = READ64(ea); + UINT32 ea = GetEA(cpustate,modm); + UINT64 value = READ64(cpustate,ea); UINT64 edx_eax = (((UINT64) REG32(EDX)) << 32) | REG32(EAX); UINT64 ecx_ebx = (((UINT64) REG32(ECX)) << 32) | REG32(EBX); if( value == edx_eax ) { - WRITE64(ea, ecx_ebx); - I.ZF = 1; - CYCLES(CYCLES_CMPXCHG_REG_MEM_T); + WRITE64(cpustate,ea, ecx_ebx); + cpustate->ZF = 1; + CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_T); } else { REG32(EDX) = (UINT32) (value >> 32); REG32(EAX) = (UINT32) (value >> 0); - I.ZF = 0; - CYCLES(CYCLES_CMPXCHG_REG_MEM_F); + cpustate->ZF = 0; + CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_F); } } } diff --git a/src/emu/cpu/i386/x87ops.c b/src/emu/cpu/i386/x87ops.c index abcf05754e2..8425dd92d56 100644 --- a/src/emu/cpu/i386/x87ops.c +++ b/src/emu/cpu/i386/x87ops.c @@ -1,6 +1,6 @@ // Intel x87 FPU opcodes -#define ST(x) (I.fpu_reg[(I.fpu_top + (x)) & 7]) +#define ST(x) (cpustate->fpu_reg[(cpustate->fpu_top + (x)) & 7]) #define FPU_INFINITY_DOUBLE U64(0x7ff0000000000000) #define FPU_INFINITY_SINGLE (0x7f800000) #define FPU_SIGN_BIT_DOUBLE U64(0x8000000000000000) @@ -30,64 +30,64 @@ #define FPU_EXCEPTION_DENORMAL_OP 0x0002 #define FPU_EXCEPTION_INVALID_OP 0x0001 -INLINE void FPU_PUSH(X87_REG value) +INLINE void FPU_PUSH(i386_state *cpustate, X87_REG value) { - I.fpu_top--; - if (I.fpu_top < 0) + cpustate->fpu_top--; + if (cpustate->fpu_top < 0) { - I.fpu_top = 7; + cpustate->fpu_top = 7; } - I.fpu_reg[I.fpu_top] = value; + cpustate->fpu_reg[cpustate->fpu_top] = value; } -INLINE X87_REG FPU_POP(void) +INLINE X87_REG FPU_POP(i386_state *cpustate) { - X87_REG value = I.fpu_reg[I.fpu_top]; + X87_REG value = cpustate->fpu_reg[cpustate->fpu_top]; - I.fpu_tag_word |= 3 << (I.fpu_top * 2); // set FPU register tag to 3 (empty) + cpustate->fpu_tag_word |= 3 << (cpustate->fpu_top * 2); // set FPU register tag to 3 (empty) - I.fpu_top++; - if (I.fpu_top > 7) + cpustate->fpu_top++; + if (cpustate->fpu_top > 7) { - I.fpu_top = 0; + cpustate->fpu_top = 0; } return value; } -static void I386OP(fpu_group_d8)(void) // Opcode 0xd8 +static void I386OP(fpu_group_d8)(i386_state *cpustate) // Opcode 0xd8 { - UINT8 modrm = FETCH(); - fatalerror("I386: FPU Op D8 %02X at %08X", modrm, I.pc-2); + UINT8 modrm = FETCH(cpustate); + fatalerror("I386: FPU Op D8 %02X at %08X", modrm, cpustate->pc-2); } -static void I386OP(fpu_group_d9)(void) // Opcode 0xd9 +static void I386OP(fpu_group_d9)(i386_state *cpustate) // Opcode 0xd9 { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if (modrm < 0xc0) { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); switch ((modrm >> 3) & 0x7) { case 5: // FLDCW { - I.fpu_control_word = READ16(ea); - CYCLES(1); // TODO + cpustate->fpu_control_word = READ16(cpustate,ea); + CYCLES(cpustate,1); // TODO break; } case 7: // FSTCW { - WRITE16(ea, I.fpu_control_word); - CYCLES(1); // TODO + WRITE16(cpustate,ea, cpustate->fpu_control_word); + CYCLES(cpustate,1); // TODO break; } default: - fatalerror("I386: FPU Op D9 %02X at %08X", modrm, I.pc-2); + fatalerror("I386: FPU Op D9 %02X at %08X", modrm, cpustate->pc-2); } } else @@ -98,15 +98,15 @@ static void I386OP(fpu_group_d9)(void) // Opcode 0xd9 case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: { X87_REG t = ST(modrm & 7); - FPU_PUSH(t); - CYCLES(1); // TODO + FPU_PUSH(cpustate,t); + CYCLES(cpustate,1); // TODO break; } case 0x20: // FCHS { ST(0).i ^= FPU_SIGN_BIT_DOUBLE; - CYCLES(1); // TODO + CYCLES(cpustate,1); // TODO break; } @@ -114,8 +114,8 @@ static void I386OP(fpu_group_d9)(void) // Opcode 0xd9 { X87_REG t; t.f = 1.0; - FPU_PUSH(t); - CYCLES(1); // TODO + FPU_PUSH(cpustate,t); + CYCLES(cpustate,1); // TODO break; } @@ -123,29 +123,29 @@ static void I386OP(fpu_group_d9)(void) // Opcode 0xd9 { X87_REG t; t.f = 0.0; - FPU_PUSH(t); - CYCLES(1); // TODO + FPU_PUSH(cpustate,t); + CYCLES(cpustate,1); // TODO break; } default: - fatalerror("I386: FPU Op D9 %02X at %08X", modrm, I.pc-2); + fatalerror("I386: FPU Op D9 %02X at %08X", modrm, cpustate->pc-2); } } } -static void I386OP(fpu_group_da)(void) // Opcode 0xda +static void I386OP(fpu_group_da)(i386_state *cpustate) // Opcode 0xda { - UINT8 modrm = FETCH(); - fatalerror("I386: FPU Op DA %02X at %08X", modrm, I.pc-2); + UINT8 modrm = FETCH(cpustate); + fatalerror("I386: FPU Op DA %02X at %08X", modrm, cpustate->pc-2); } -static void I386OP(fpu_group_db)(void) // Opcode 0xdb +static void I386OP(fpu_group_db)(i386_state *cpustate) // Opcode 0xdb { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if (modrm < 0xc0) { - fatalerror("I386: FPU Op DB %02X at %08X", modrm, I.pc-2); + fatalerror("I386: FPU Op DB %02X at %08X", modrm, cpustate->pc-2); } else { @@ -153,41 +153,41 @@ static void I386OP(fpu_group_db)(void) // Opcode 0xdb { case 0x23: // FINIT { - I.fpu_control_word = 0x37f; - I.fpu_status_word = 0; - I.fpu_tag_word = 0xffff; - I.fpu_data_ptr = 0; - I.fpu_inst_ptr = 0; - I.fpu_opcode = 0; - - CYCLES(1); // TODO + cpustate->fpu_control_word = 0x37f; + cpustate->fpu_status_word = 0; + cpustate->fpu_tag_word = 0xffff; + cpustate->fpu_data_ptr = 0; + cpustate->fpu_inst_ptr = 0; + cpustate->fpu_opcode = 0; + + CYCLES(cpustate,1); // TODO break; } case 0x24: // FSETPM (treated as nop on 387+) { - CYCLES(1); + CYCLES(cpustate,1); break; } default: - fatalerror("I386: FPU Op DB %02X at %08X", modrm, I.pc-2); + fatalerror("I386: FPU Op DB %02X at %08X", modrm, cpustate->pc-2); } } } -static void I386OP(fpu_group_dc)(void) // Opcode 0xdc +static void I386OP(fpu_group_dc)(i386_state *cpustate) // Opcode 0xdc { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if (modrm < 0xc0) { - //UINT32 ea = GetEA(modrm); + //UINT32 ea = GetEA(cpustate,modrm); switch ((modrm >> 3) & 0x7) { default: - fatalerror("I386: FPU Op DC %02X at %08X", modrm, I.pc-2); + fatalerror("I386: FPU Op DC %02X at %08X", modrm, cpustate->pc-2); } } else @@ -200,7 +200,7 @@ static void I386OP(fpu_group_dc)(void) // Opcode 0xdc if ((ST(modrm & 7).i & U64(0x7fffffffffffffff)) == 0) { // set result as infinity if zero divide is masked - if (I.fpu_control_word & FPU_MASK_ZERO_DIVIDE) + if (cpustate->fpu_control_word & FPU_MASK_ZERO_DIVIDE) { ST(modrm & 7).i |= FPU_INFINITY_DOUBLE; } @@ -209,35 +209,35 @@ static void I386OP(fpu_group_dc)(void) // Opcode 0xdc { ST(modrm & 7).f = ST(0).f / ST(modrm & 7).f; } - CYCLES(1); // TODO + CYCLES(cpustate,1); // TODO break; } default: - fatalerror("I386: FPU Op DC %02X at %08X", modrm, I.pc-2); + fatalerror("I386: FPU Op DC %02X at %08X", modrm, cpustate->pc-2); } } } -static void I386OP(fpu_group_dd)(void) // Opcode 0xdd +static void I386OP(fpu_group_dd)(i386_state *cpustate) // Opcode 0xdd { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if (modrm < 0xc0) { - UINT32 ea = GetEA(modrm); + UINT32 ea = GetEA(cpustate,modrm); switch ((modrm >> 3) & 0x7) { case 7: // FSTSW { - WRITE16(ea, (I.fpu_status_word & ~FPU_STACK_TOP_MASK) | (I.fpu_top << 10)); - CYCLES(1); // TODO + WRITE16(cpustate,ea, (cpustate->fpu_status_word & ~FPU_STACK_TOP_MASK) | (cpustate->fpu_top << 10)); + CYCLES(cpustate,1); // TODO break; } default: - fatalerror("I386: FPU Op DD %02X at %08X", modrm, I.pc-2); + fatalerror("I386: FPU Op DD %02X at %08X", modrm, cpustate->pc-2); } } else @@ -245,23 +245,23 @@ static void I386OP(fpu_group_dd)(void) // Opcode 0xdd switch (modrm & 0x3f) { default: - fatalerror("I386: FPU Op DD %02X at %08X", modrm, I.pc-2); + fatalerror("I386: FPU Op DD %02X at %08X", modrm, cpustate->pc-2); } } } -static void I386OP(fpu_group_de)(void) // Opcode 0xde +static void I386OP(fpu_group_de)(i386_state *cpustate) // Opcode 0xde { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if (modrm < 0xc0) { - // UINT32 ea = GetEA(modrm); + // UINT32 ea = GetEA(cpustate,modrm); switch ((modrm >> 3) & 0x7) { default: - fatalerror("I386: FPU Op DE %02X at %08X", modrm, I.pc-2); + fatalerror("I386: FPU Op DE %02X at %08X", modrm, cpustate->pc-2); } } else @@ -270,27 +270,27 @@ static void I386OP(fpu_group_de)(void) // Opcode 0xde { case 0x19: // FCOMPP { - I.fpu_status_word &= ~(FPU_C3 | FPU_C2 | FPU_C0); + cpustate->fpu_status_word &= ~(FPU_C3 | FPU_C2 | FPU_C0); if (ST(0).f > ST(1).f) { // C3 = 0, C2 = 0, C0 = 0 } else if (ST(0).f < ST(1).f) { - I.fpu_status_word |= FPU_C0; + cpustate->fpu_status_word |= FPU_C0; } else if (ST(0).f == ST(1).f) { - I.fpu_status_word |= FPU_C3; + cpustate->fpu_status_word |= FPU_C3; } else { // unordered - I.fpu_status_word |= (FPU_C3 | FPU_C2 | FPU_C0); + cpustate->fpu_status_word |= (FPU_C3 | FPU_C2 | FPU_C0); } - FPU_POP(); - FPU_POP(); - CYCLES(1); // TODO + FPU_POP(cpustate); + FPU_POP(cpustate); + CYCLES(cpustate,1); // TODO break; } @@ -300,7 +300,7 @@ static void I386OP(fpu_group_de)(void) // Opcode 0xde if ((ST(0).i & U64(0x7fffffffffffffff)) == 0) { // set result as infinity if zero divide is masked - if (I.fpu_control_word & FPU_MASK_ZERO_DIVIDE) + if (cpustate->fpu_control_word & FPU_MASK_ZERO_DIVIDE) { ST(modrm & 7).i |= FPU_INFINITY_DOUBLE; } @@ -309,29 +309,29 @@ static void I386OP(fpu_group_de)(void) // Opcode 0xde { ST(modrm & 7).f = ST(modrm & 7).f / ST(0).f; } - FPU_POP(); - CYCLES(1); // TODO + FPU_POP(cpustate); + CYCLES(cpustate,1); // TODO break; } default: - fatalerror("I386: FPU Op DE %02X at %08X", modrm, I.pc-2); + fatalerror("I386: FPU Op DE %02X at %08X", modrm, cpustate->pc-2); } } } -static void I386OP(fpu_group_df)(void) // Opcode 0xdf +static void I386OP(fpu_group_df)(i386_state *cpustate) // Opcode 0xdf { - UINT8 modrm = FETCH(); + UINT8 modrm = FETCH(cpustate); if (modrm < 0xc0) { - // UINT32 ea = GetEA(modrm); + // UINT32 ea = GetEA(cpustate,modrm); switch ((modrm >> 3) & 0x7) { default: - fatalerror("I386: FPU Op DF %02X at %08X", modrm, I.pc-2); + fatalerror("I386: FPU Op DF %02X at %08X", modrm, cpustate->pc-2); } } else @@ -340,13 +340,13 @@ static void I386OP(fpu_group_df)(void) // Opcode 0xdf { case 0x20: // FSTSW AX { - REG16(AX) = (I.fpu_status_word & ~FPU_STACK_TOP_MASK) | (I.fpu_top << 10); - CYCLES(1); // TODO + REG16(AX) = (cpustate->fpu_status_word & ~FPU_STACK_TOP_MASK) | (cpustate->fpu_top << 10); + CYCLES(cpustate,1); // TODO break; } default: - fatalerror("I386: FPU Op DF %02X at %08X", modrm, I.pc-2); + fatalerror("I386: FPU Op DF %02X at %08X", modrm, cpustate->pc-2); } } } |