diff options
Diffstat (limited to 'src/devices')
44 files changed, 1950 insertions, 1963 deletions
diff --git a/src/devices/bus/cbm2/hrg.h b/src/devices/bus/cbm2/hrg.h index 25f68a5c7a2..61773cbc559 100644 --- a/src/devices/bus/cbm2/hrg.h +++ b/src/devices/bus/cbm2/hrg.h @@ -28,7 +28,7 @@ class cbm2_graphic_cartridge_device : public device_t, public: // construction/destruction cbm2_graphic_cartridge_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source); - + // optional information overrides virtual const rom_entry *device_rom_region() const override; diff --git a/src/devices/bus/centronics/epson_ex800.h b/src/devices/bus/centronics/epson_ex800.h index 26d862cf098..2b28229c0df 100644 --- a/src/devices/bus/centronics/epson_ex800.h +++ b/src/devices/bus/centronics/epson_ex800.h @@ -30,7 +30,7 @@ class epson_ex800_t : public device_t, public: // construction/destruction epson_ex800_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // optional information overrides virtual const rom_entry *device_rom_region() const override; virtual machine_config_constructor device_mconfig_additions() const override; diff --git a/src/devices/bus/gameboy/rom.h b/src/devices/bus/gameboy/rom.h index 80fedd7a838..343d30195b0 100644 --- a/src/devices/bus/gameboy/rom.h +++ b/src/devices/bus/gameboy/rom.h @@ -44,7 +44,7 @@ public: virtual DECLARE_READ8_MEMBER(read_rom) override; virtual DECLARE_READ8_MEMBER(read_ram) override; virtual DECLARE_WRITE8_MEMBER(write_ram) override; - + UINT16 m_tama5_data, m_tama5_addr, m_tama5_cmd; UINT8 m_regs[32]; UINT8 m_rtc_reg; diff --git a/src/devices/bus/pet/hsg.h b/src/devices/bus/pet/hsg.h index 30f958f74b1..1562eadedd3 100644 --- a/src/devices/bus/pet/hsg.h +++ b/src/devices/bus/pet/hsg.h @@ -28,7 +28,7 @@ class cbm8000_hsg_t : public device_t, public: // construction/destruction cbm8000_hsg_t(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source); - + // optional information overrides virtual const rom_entry *device_rom_region() const override; diff --git a/src/devices/bus/ql/cst_q_plus4.h b/src/devices/bus/ql/cst_q_plus4.h index 03ba20bef06..eba0f3ac712 100644 --- a/src/devices/bus/ql/cst_q_plus4.h +++ b/src/devices/bus/ql/cst_q_plus4.h @@ -28,7 +28,7 @@ class cst_q_plus4_t : public device_t, public: // construction/destruction cst_q_plus4_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // optional information overrides virtual const rom_entry *device_rom_region() const override; virtual machine_config_constructor device_mconfig_additions() const override; diff --git a/src/devices/bus/ql/cst_qdisc.h b/src/devices/bus/ql/cst_qdisc.h index 35fe9f6e257..d2ddae10b2e 100644 --- a/src/devices/bus/ql/cst_qdisc.h +++ b/src/devices/bus/ql/cst_qdisc.h @@ -27,7 +27,7 @@ class cst_ql_disc_interface_t : public device_t, public: // construction/destruction cst_ql_disc_interface_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // optional information overrides virtual const rom_entry *device_rom_region() const override; diff --git a/src/devices/bus/ql/cumana_fdi.h b/src/devices/bus/ql/cumana_fdi.h index eb9c75f991e..9ac1b9ba01e 100644 --- a/src/devices/bus/ql/cumana_fdi.h +++ b/src/devices/bus/ql/cumana_fdi.h @@ -27,7 +27,7 @@ class cumana_floppy_disk_interface_t : public device_t, public: // construction/destruction cumana_floppy_disk_interface_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // optional information overrides virtual const rom_entry *device_rom_region() const override; diff --git a/src/devices/bus/ql/kempston_di.h b/src/devices/bus/ql/kempston_di.h index 97082e1a68e..041bdc65544 100644 --- a/src/devices/bus/ql/kempston_di.h +++ b/src/devices/bus/ql/kempston_di.h @@ -27,7 +27,7 @@ class kempston_disk_interface_t : public device_t, public: // construction/destruction kempston_disk_interface_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // optional information overrides virtual const rom_entry *device_rom_region() const override; diff --git a/src/devices/bus/ql/miracle_gold_card.h b/src/devices/bus/ql/miracle_gold_card.h index c60f490c6d9..176f7556fdf 100644 --- a/src/devices/bus/ql/miracle_gold_card.h +++ b/src/devices/bus/ql/miracle_gold_card.h @@ -27,7 +27,7 @@ class miracle_gold_card_t : public device_t, public: // construction/destruction miracle_gold_card_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // optional information overrides virtual const rom_entry *device_rom_region() const override; diff --git a/src/devices/bus/ql/miracle_hd.h b/src/devices/bus/ql/miracle_hd.h index 7c24af7aa95..c4aeaa6d74b 100644 --- a/src/devices/bus/ql/miracle_hd.h +++ b/src/devices/bus/ql/miracle_hd.h @@ -27,7 +27,7 @@ class miracle_hard_disk_t : public device_t, public: // construction/destruction miracle_hard_disk_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // optional information overrides virtual const rom_entry *device_rom_region() const override; diff --git a/src/devices/bus/ql/mp_fdi.h b/src/devices/bus/ql/mp_fdi.h index a064ffcff86..57681f30d28 100644 --- a/src/devices/bus/ql/mp_fdi.h +++ b/src/devices/bus/ql/mp_fdi.h @@ -27,7 +27,7 @@ class micro_peripherals_floppy_disk_interface_t : public device_t, public: // construction/destruction micro_peripherals_floppy_disk_interface_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // optional information overrides virtual const rom_entry *device_rom_region() const override; diff --git a/src/devices/bus/ql/opd_basic_master.h b/src/devices/bus/ql/opd_basic_master.h index 793bfeb9370..16608210cf2 100644 --- a/src/devices/bus/ql/opd_basic_master.h +++ b/src/devices/bus/ql/opd_basic_master.h @@ -27,7 +27,7 @@ class opd_basic_master_t : public device_t, public: // construction/destruction opd_basic_master_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // optional information overrides virtual const rom_entry *device_rom_region() const override; diff --git a/src/devices/bus/ql/pcml_qdisk.h b/src/devices/bus/ql/pcml_qdisk.h index 47cbe4ab85e..29a011b7455 100644 --- a/src/devices/bus/ql/pcml_qdisk.h +++ b/src/devices/bus/ql/pcml_qdisk.h @@ -27,7 +27,7 @@ class pcml_q_disk_interface_t : public device_t, public: // construction/destruction pcml_q_disk_interface_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // optional information overrides virtual const rom_entry *device_rom_region() const override; diff --git a/src/devices/bus/ql/qubide.h b/src/devices/bus/ql/qubide.h index d64b05cf742..f8a363b55a2 100644 --- a/src/devices/bus/ql/qubide.h +++ b/src/devices/bus/ql/qubide.h @@ -28,7 +28,7 @@ class qubide_t : public device_t, public: // construction/destruction qubide_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // optional information overrides virtual const rom_entry *device_rom_region() const override; virtual machine_config_constructor device_mconfig_additions() const override; diff --git a/src/devices/cpu/avr8/avr8.cpp b/src/devices/cpu/avr8/avr8.cpp index 085700da53f..f8f357a2a9b 100644 --- a/src/devices/cpu/avr8/avr8.cpp +++ b/src/devices/cpu/avr8/avr8.cpp @@ -1316,7 +1316,7 @@ void avr8_device::timer1_tick() //UINT8 compare_mode[2] = { (m_r[AVR8_REGIDX_TCCR1A] & AVR8_TCCR1A_COM1A_MASK) >> AVR8_TCCR1A_COM1A_SHIFT, //(m_r[AVR8_REGIDX_TCCR1A] & AVR8_TCCR1A_COM1B_MASK) >> AVR8_TCCR1A_COM1B_SHIFT }; UINT16 ocr1[2] = { static_cast<UINT16>((m_r[AVR8_REGIDX_OCR1AH] << 8) | m_r[AVR8_REGIDX_OCR1AL]), - static_cast<UINT16>((m_r[AVR8_REGIDX_OCR1BH] << 8) | m_r[AVR8_REGIDX_OCR1BL]) }; + static_cast<UINT16>((m_r[AVR8_REGIDX_OCR1BH] << 8) | m_r[AVR8_REGIDX_OCR1BL]) }; UINT8 ocf1[2] = { (1 << AVR8_TIFR1_OCF1A_SHIFT), (1 << AVR8_TIFR1_OCF1B_SHIFT) }; UINT8 int1[2] = { AVR8_INTIDX_OCF1A, AVR8_INTIDX_OCF1B }; INT32 increment = m_timer_increment[1]; @@ -1712,7 +1712,7 @@ void avr8_device::timer4_tick() //UINT8 compare_mode[2] = { (m_r[AVR8_REGIDX_TCCR1A] & AVR8_TCCR1A_COM1A_MASK) >> AVR8_TCCR1A_COM1A_SHIFT, //(m_r[AVR8_REGIDX_TCCR1A] & AVR8_TCCR1A_COM1B_MASK) >> AVR8_TCCR1A_COM1B_SHIFT }; UINT16 ocr4[2] = { static_cast<UINT16>((m_r[AVR8_REGIDX_OCR4AH] << 8) | m_r[AVR8_REGIDX_OCR4AL]), - static_cast<UINT16>((m_r[AVR8_REGIDX_OCR4BH] << 8) | m_r[AVR8_REGIDX_OCR4BL]) }; + static_cast<UINT16>((m_r[AVR8_REGIDX_OCR4BH] << 8) | m_r[AVR8_REGIDX_OCR4BL]) }; //TODO UINT8 ocf4[2] = { (1 << AVR8_TIFR4_OCF4A_SHIFT), (1 << AVR8_TIFR4_OCF4B_SHIFT) }; //TODO UINT8 int4[2] = { AVR8_INTIDX_OCF4A, AVR8_INTIDX_OCF4B }; INT32 increment = m_timer_increment[4]; diff --git a/src/devices/cpu/drcuml.cpp b/src/devices/cpu/drcuml.cpp index 921d09d30bd..4cf2fc981c0 100644 --- a/src/devices/cpu/drcuml.cpp +++ b/src/devices/cpu/drcuml.cpp @@ -126,7 +126,7 @@ drcuml_state::drcuml_state(device_t &device, drc_cache &cache, UINT32 flags, int std::unique_ptr<drcbe_interface>{ std::make_unique<drcbe_native>(*this, device, cache, flags, modes, addrbits, ignorebits) }), m_beintf(*m_drcbe_interface.get()), m_umllog(nullptr) -{ +{ // if we're to log, create the logfile if (device.machine().options().drc_log_uml()) { diff --git a/src/devices/cpu/hphybrid/hphybrid.cpp b/src/devices/cpu/hphybrid/hphybrid.cpp index ddfd740d90b..855931b59ee 100644 --- a/src/devices/cpu/hphybrid/hphybrid.cpp +++ b/src/devices/cpu/hphybrid/hphybrid.cpp @@ -18,21 +18,21 @@ enum { HPHYBRID_DMAMA, HPHYBRID_DMAC, HPHYBRID_I, - HPHYBRID_W, - HPHYBRID_AR2, - HPHYBRID_AR2_2, - HPHYBRID_AR2_3, - HPHYBRID_AR2_4, - HPHYBRID_SE, - HPHYBRID_R25, - HPHYBRID_R26, - HPHYBRID_R27, - HPHYBRID_R32, - HPHYBRID_R33, - HPHYBRID_R34, - HPHYBRID_R35, - HPHYBRID_R36, - HPHYBRID_R37 + HPHYBRID_W, + HPHYBRID_AR2, + HPHYBRID_AR2_2, + HPHYBRID_AR2_3, + HPHYBRID_AR2_4, + HPHYBRID_SE, + HPHYBRID_R25, + HPHYBRID_R26, + HPHYBRID_R27, + HPHYBRID_R32, + HPHYBRID_R33, + HPHYBRID_R34, + HPHYBRID_R35, + HPHYBRID_R36, + HPHYBRID_R37 }; #define BIT_MASK(n) (1U << (n)) @@ -84,36 +84,36 @@ WRITE_LINE_MEMBER(hp_hybrid_cpu_device::dmar_w) WRITE_LINE_MEMBER(hp_hybrid_cpu_device::halt_w) { - if (state) { - BIT_SET(m_flags , HPHYBRID_HALT_BIT); - } else { - BIT_CLR(m_flags , HPHYBRID_HALT_BIT); - } + if (state) { + BIT_SET(m_flags , HPHYBRID_HALT_BIT); + } else { + BIT_CLR(m_flags , HPHYBRID_HALT_BIT); + } } WRITE_LINE_MEMBER(hp_hybrid_cpu_device::status_w) { - if (state) { - BIT_SET(m_flags , HPHYBRID_STS_BIT); - } else { - BIT_CLR(m_flags , HPHYBRID_STS_BIT); - } + if (state) { + BIT_SET(m_flags , HPHYBRID_STS_BIT); + } else { + BIT_CLR(m_flags , HPHYBRID_STS_BIT); + } } WRITE_LINE_MEMBER(hp_hybrid_cpu_device::flag_w) { - if (state) { - BIT_SET(m_flags , HPHYBRID_FLG_BIT); - } else { - BIT_CLR(m_flags , HPHYBRID_FLG_BIT); - } + if (state) { + BIT_SET(m_flags , HPHYBRID_FLG_BIT); + } else { + BIT_CLR(m_flags , HPHYBRID_FLG_BIT); + } } hp_hybrid_cpu_device::hp_hybrid_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname , UINT8 addrwidth) - : cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__), - m_pa_changed_func(*this), - m_program_config("program", ENDIANNESS_BIG, 16, addrwidth, -1), - m_io_config("io", ENDIANNESS_BIG, 16, 6, -1) + : cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__), + m_pa_changed_func(*this), + m_program_config("program", ENDIANNESS_BIG, 16, addrwidth, -1), + m_io_config("io", ENDIANNESS_BIG, 16, 6, -1) { } @@ -129,13 +129,13 @@ void hp_hybrid_cpu_device::device_start() m_reg_PA[ 0 ] = 0; m_reg_PA[ 1 ] = 0; m_reg_PA[ 2 ] = 0; - m_reg_W = 0; + m_reg_W = 0; m_flags = 0; m_dmapa = 0; m_dmama = 0; m_dmac = 0; m_reg_I = 0; - m_forced_bsc_25 = false; + m_forced_bsc_25 = false; { state_add(HPHYBRID_A, "A", m_reg_A); @@ -148,7 +148,7 @@ void hp_hybrid_cpu_device::device_start() state_add(STATE_GENSP, "GENSP", m_reg_R).noshow(); state_add(HPHYBRID_IV, "IV", m_reg_IV); state_add(HPHYBRID_PA, "PA", m_reg_PA[ 0 ]); - state_add(HPHYBRID_W, "W", m_reg_W).noshow(); + state_add(HPHYBRID_W, "W", m_reg_W).noshow(); state_add(STATE_GENFLAGS, "GENFLAGS", m_flags).noshow().formatstr("%9s"); state_add(HPHYBRID_DMAPA , "DMAPA" , m_dmapa).noshow(); state_add(HPHYBRID_DMAMA , "DMAMA" , m_dmama).noshow(); @@ -170,17 +170,17 @@ void hp_hybrid_cpu_device::device_start() save_item(NAME(m_reg_PA[0])); save_item(NAME(m_reg_PA[1])); save_item(NAME(m_reg_PA[2])); - save_item(NAME(m_reg_W)); + save_item(NAME(m_reg_W)); save_item(NAME(m_flags)); save_item(NAME(m_dmapa)); save_item(NAME(m_dmama)); save_item(NAME(m_dmac)); save_item(NAME(m_reg_I)); - save_item(NAME(m_forced_bsc_25)); + save_item(NAME(m_forced_bsc_25)); m_icountptr = &m_icount; - m_pa_changed_func.resolve_safe(); + m_pa_changed_func.resolve_safe(); } void hp_hybrid_cpu_device::device_reset() @@ -506,11 +506,11 @@ UINT16 hp_hybrid_cpu_device::execute_one_sub(UINT16 opcode) if (BIT(m_flags , HPHYBRID_IRH_SVC_BIT)) { BIT_CLR(m_flags , HPHYBRID_IRH_SVC_BIT); memmove(&m_reg_PA[ 0 ] , &m_reg_PA[ 1 ] , HPHYBRID_INT_LVLS); - m_pa_changed_func((UINT8)CURRENT_PA); + m_pa_changed_func((UINT8)CURRENT_PA); } else if (BIT(m_flags , HPHYBRID_IRL_SVC_BIT)) { BIT_CLR(m_flags , HPHYBRID_IRL_SVC_BIT); memmove(&m_reg_PA[ 0 ] , &m_reg_PA[ 1 ] , HPHYBRID_INT_LVLS); - m_pa_changed_func((UINT8)CURRENT_PA); + m_pa_changed_func((UINT8)CURRENT_PA); } } tmp = RM(AEC_CASE_C , m_reg_R--) + (opcode & 0x1f); @@ -604,14 +604,14 @@ UINT16 hp_hybrid_cpu_device::execute_one_sub(UINT16 opcode) break; default: - // Unrecognized instruction: pass it on for further processing (by EMC if present) - return execute_no_bpc_ioc(opcode); - } - } - } - } - } - } + // Unrecognized instruction: pass it on for further processing (by EMC if present) + return execute_no_bpc_ioc(opcode); + } + } + } + } + } + } return m_reg_P + 1; } @@ -635,204 +635,204 @@ offs_t hp_hybrid_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const U UINT16 hp_hybrid_cpu_device::remove_mae(UINT32 addr) { - return (UINT16)(addr & 0xffff); + return (UINT16)(addr & 0xffff); } UINT16 hp_hybrid_cpu_device::RM(aec_cases_t aec_case , UINT16 addr) { - return RM(add_mae(aec_case , addr)); + return RM(add_mae(aec_case , addr)); } UINT16 hp_hybrid_cpu_device::RM(UINT32 addr) { - UINT16 tmp; - UINT16 addr_wo_bsc = remove_mae(addr); - - if (addr_wo_bsc <= HP_REG_LAST_ADDR) { - // Any access to internal registers removes forcing of BSC 2x - m_forced_bsc_25 = false; - - // Memory mapped registers that are present in both 3001 & 3011 - switch (addr_wo_bsc) { - case HP_REG_A_ADDR: - return m_reg_A; - - case HP_REG_B_ADDR: - return m_reg_B; - - case HP_REG_P_ADDR: - return m_reg_P; - - case HP_REG_R_ADDR: - return m_reg_R; - - case HP_REG_R4_ADDR: - case HP_REG_R5_ADDR: - case HP_REG_R6_ADDR: - case HP_REG_R7_ADDR: - return RIO(CURRENT_PA , addr_wo_bsc - HP_REG_R4_ADDR); - - case HP_REG_IV_ADDR: - // Correct? - if (!BIT(m_flags , HPHYBRID_IRH_SVC_BIT) && !BIT(m_flags , HPHYBRID_IRL_SVC_BIT)) { - return m_reg_IV; - } else { - return m_reg_IV | CURRENT_PA; - } - - case HP_REG_PA_ADDR: - return CURRENT_PA; - - case HP_REG_W_ADDR: - return m_reg_W; - - case HP_REG_DMAPA_ADDR: - tmp = m_dmapa & HP_REG_PA_MASK; - if (BIT(m_flags , HPHYBRID_CB_BIT)) { - BIT_SET(tmp , 15); - } - if (BIT(m_flags , HPHYBRID_DB_BIT)) { - BIT_SET(tmp , 14); - } - return tmp; - - case HP_REG_DMAMA_ADDR: - return m_dmama; - - case HP_REG_DMAC_ADDR: - return m_dmac; - - case HP_REG_C_ADDR: - return m_reg_C; - - case HP_REG_D_ADDR: - return m_reg_D; - - default: - return read_non_common_reg(addr_wo_bsc); - } - } else { - return m_direct->read_word(addr << 1); - } + UINT16 tmp; + UINT16 addr_wo_bsc = remove_mae(addr); + + if (addr_wo_bsc <= HP_REG_LAST_ADDR) { + // Any access to internal registers removes forcing of BSC 2x + m_forced_bsc_25 = false; + + // Memory mapped registers that are present in both 3001 & 3011 + switch (addr_wo_bsc) { + case HP_REG_A_ADDR: + return m_reg_A; + + case HP_REG_B_ADDR: + return m_reg_B; + + case HP_REG_P_ADDR: + return m_reg_P; + + case HP_REG_R_ADDR: + return m_reg_R; + + case HP_REG_R4_ADDR: + case HP_REG_R5_ADDR: + case HP_REG_R6_ADDR: + case HP_REG_R7_ADDR: + return RIO(CURRENT_PA , addr_wo_bsc - HP_REG_R4_ADDR); + + case HP_REG_IV_ADDR: + // Correct? + if (!BIT(m_flags , HPHYBRID_IRH_SVC_BIT) && !BIT(m_flags , HPHYBRID_IRL_SVC_BIT)) { + return m_reg_IV; + } else { + return m_reg_IV | CURRENT_PA; + } + + case HP_REG_PA_ADDR: + return CURRENT_PA; + + case HP_REG_W_ADDR: + return m_reg_W; + + case HP_REG_DMAPA_ADDR: + tmp = m_dmapa & HP_REG_PA_MASK; + if (BIT(m_flags , HPHYBRID_CB_BIT)) { + BIT_SET(tmp , 15); + } + if (BIT(m_flags , HPHYBRID_DB_BIT)) { + BIT_SET(tmp , 14); + } + return tmp; + + case HP_REG_DMAMA_ADDR: + return m_dmama; + + case HP_REG_DMAC_ADDR: + return m_dmac; + + case HP_REG_C_ADDR: + return m_reg_C; + + case HP_REG_D_ADDR: + return m_reg_D; + + default: + return read_non_common_reg(addr_wo_bsc); + } + } else { + return m_direct->read_word(addr << 1); + } } void hp_hybrid_cpu_device::WM(aec_cases_t aec_case , UINT16 addr , UINT16 v) { - WM(add_mae(aec_case , addr) , v); + WM(add_mae(aec_case , addr) , v); } void hp_hybrid_cpu_device::WM(UINT32 addr , UINT16 v) { - UINT16 addr_wo_bsc = remove_mae(addr); - - if (addr_wo_bsc <= HP_REG_LAST_ADDR) { - // Any access to internal registers removes forcing of BSC 2x - m_forced_bsc_25 = false; - - // Memory mapped registers - switch (addr_wo_bsc) { - case HP_REG_A_ADDR: - m_reg_A = v; - break; - - case HP_REG_B_ADDR: - m_reg_B = v; - break; - - case HP_REG_P_ADDR: - m_reg_P = v; - break; - - case HP_REG_R_ADDR: - m_reg_R = v; - break; - - case HP_REG_R4_ADDR: - case HP_REG_R5_ADDR: - case HP_REG_R6_ADDR: - case HP_REG_R7_ADDR: - WIO(CURRENT_PA , addr_wo_bsc - HP_REG_R4_ADDR , v); - break; - - case HP_REG_IV_ADDR: - m_reg_IV = v & HP_REG_IV_MASK; - break; - - case HP_REG_PA_ADDR: - CURRENT_PA = v & HP_REG_PA_MASK; - m_pa_changed_func((UINT8)CURRENT_PA); - break; - - case HP_REG_W_ADDR: - m_reg_W = v; - break; - - case HP_REG_DMAPA_ADDR: - m_dmapa = v & HP_REG_PA_MASK; - break; - - case HP_REG_DMAMA_ADDR: - m_dmama = v; - break; - - case HP_REG_DMAC_ADDR: - m_dmac = v; - break; - - case HP_REG_C_ADDR: - m_reg_C = v; - break; - - case HP_REG_D_ADDR: - m_reg_D = v; - break; - - default: - write_non_common_reg(addr_wo_bsc , v); - break; - } - } else { - m_program->write_word(addr << 1 , v); - } + UINT16 addr_wo_bsc = remove_mae(addr); + + if (addr_wo_bsc <= HP_REG_LAST_ADDR) { + // Any access to internal registers removes forcing of BSC 2x + m_forced_bsc_25 = false; + + // Memory mapped registers + switch (addr_wo_bsc) { + case HP_REG_A_ADDR: + m_reg_A = v; + break; + + case HP_REG_B_ADDR: + m_reg_B = v; + break; + + case HP_REG_P_ADDR: + m_reg_P = v; + break; + + case HP_REG_R_ADDR: + m_reg_R = v; + break; + + case HP_REG_R4_ADDR: + case HP_REG_R5_ADDR: + case HP_REG_R6_ADDR: + case HP_REG_R7_ADDR: + WIO(CURRENT_PA , addr_wo_bsc - HP_REG_R4_ADDR , v); + break; + + case HP_REG_IV_ADDR: + m_reg_IV = v & HP_REG_IV_MASK; + break; + + case HP_REG_PA_ADDR: + CURRENT_PA = v & HP_REG_PA_MASK; + m_pa_changed_func((UINT8)CURRENT_PA); + break; + + case HP_REG_W_ADDR: + m_reg_W = v; + break; + + case HP_REG_DMAPA_ADDR: + m_dmapa = v & HP_REG_PA_MASK; + break; + + case HP_REG_DMAMA_ADDR: + m_dmama = v; + break; + + case HP_REG_DMAC_ADDR: + m_dmac = v; + break; + + case HP_REG_C_ADDR: + m_reg_C = v; + break; + + case HP_REG_D_ADDR: + m_reg_D = v; + break; + + default: + write_non_common_reg(addr_wo_bsc , v); + break; + } + } else { + m_program->write_word(addr << 1 , v); + } } UINT16 hp_hybrid_cpu_device::fetch(void) { - m_genpc = add_mae(AEC_CASE_A , m_reg_P); - return RM(m_genpc); + m_genpc = add_mae(AEC_CASE_A , m_reg_P); + return RM(m_genpc); } UINT32 hp_hybrid_cpu_device::get_ea(UINT16 opcode) { - UINT16 base; - UINT16 off; - aec_cases_t aec; - - if (BIT(opcode , 10)) { - // Current page - base = m_reg_P; - aec = AEC_CASE_A; - } else { - // Base page - base = 0; - aec = AEC_CASE_B; - } - - off = opcode & 0x3ff; - if (off & 0x200) { - off -= 0x400; - } - - base += off; - - if (BIT(opcode , 15)) { - // Indirect addressing - m_icount -= 6; - return add_mae(AEC_CASE_C , RM(aec , base)); - } else { - // Direct addressing - return add_mae(aec , base); - } + UINT16 base; + UINT16 off; + aec_cases_t aec; + + if (BIT(opcode , 10)) { + // Current page + base = m_reg_P; + aec = AEC_CASE_A; + } else { + // Base page + base = 0; + aec = AEC_CASE_B; + } + + off = opcode & 0x3ff; + if (off & 0x200) { + off -= 0x400; + } + + base += off; + + if (BIT(opcode , 15)) { + // Indirect addressing + m_icount -= 6; + return add_mae(AEC_CASE_C , RM(aec , base)); + } else { + // Direct addressing + return add_mae(aec , base); + } } void hp_hybrid_cpu_device::do_add(UINT16& addend1 , UINT16 addend2) @@ -949,22 +949,22 @@ void hp_hybrid_cpu_device::do_pw(UINT16 opcode) if (m_flags & b_mask) { tmp_addr |= 0x10000; } - if (tmp_addr <= (HP_REG_LAST_ADDR * 2 + 1)) { - // Single bytes can be written to registers. - // The addressed register gets the written byte in the proper position - // and a 0 in the other byte because access to registers is always done in - // 16 bits units. - if (BIT(tmp_addr , 0)) { - tmp &= 0xff; - } else { - tmp <<= 8; - } - WM(tmp_addr >> 1 , tmp); - } else { - // Extend address, preserve LSB & form byte address - tmp_addr = (add_mae(AEC_CASE_C , tmp_addr >> 1) << 1) | (tmp_addr & 1); - m_program->write_byte(tmp_addr , (UINT8)tmp); - } + if (tmp_addr <= (HP_REG_LAST_ADDR * 2 + 1)) { + // Single bytes can be written to registers. + // The addressed register gets the written byte in the proper position + // and a 0 in the other byte because access to registers is always done in + // 16 bits units. + if (BIT(tmp_addr , 0)) { + tmp &= 0xff; + } else { + tmp <<= 8; + } + WM(tmp_addr >> 1 , tmp); + } else { + // Extend address, preserve LSB & form byte address + tmp_addr = (add_mae(AEC_CASE_C , tmp_addr >> 1) << 1) | (tmp_addr & 1); + m_program->write_byte(tmp_addr , (UINT8)tmp); + } } else { // Word WM(AEC_CASE_C , *ptr_reg , tmp); @@ -1013,7 +1013,7 @@ void hp_hybrid_cpu_device::check_for_interrupts(void) CURRENT_PA = new_PA; - m_pa_changed_func((UINT8)CURRENT_PA); + m_pa_changed_func((UINT8)CURRENT_PA); // Is this correct? Patent @ pg 210 suggests that the whole interrupt recognition sequence // lasts for 32 cycles (6 are already accounted for in get_ea for one indirection) @@ -1033,7 +1033,7 @@ void hp_hybrid_cpu_device::handle_dma(void) if (BIT(m_flags , HPHYBRID_DMADIR_BIT)) { // "Outward" DMA: memory -> peripheral - tmp = RM(AEC_CASE_D , m_dmama++); + tmp = RM(AEC_CASE_D , m_dmama++); WIO(m_dmapa , tc ? 2 : 0 , tmp); m_icount -= 10; } else { @@ -1062,545 +1062,544 @@ void hp_hybrid_cpu_device::WIO(UINT8 pa , UINT8 ic , UINT16 v) } hp_5061_3001_cpu_device::hp_5061_3001_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : hp_hybrid_cpu_device(mconfig, HP_5061_3001, "HP-5061-3001", tag, owner, clock, "5061-3001", 22), - m_boot_mode(false) + : hp_hybrid_cpu_device(mconfig, HP_5061_3001, "HP-5061-3001", tag, owner, clock, "5061-3001", 22), + m_boot_mode(false) { } void hp_5061_3001_cpu_device::device_start() { - hp_hybrid_cpu_device::device_start(); - - state_add(HPHYBRID_AR2, "Ar2" , m_reg_ar2[ 0 ]); - state_add(HPHYBRID_AR2_2, "Ar2_2" , m_reg_ar2[ 1 ]); - state_add(HPHYBRID_AR2_3, "Ar2_3" , m_reg_ar2[ 2 ]); - state_add(HPHYBRID_AR2_4, "Ar2_4" , m_reg_ar2[ 3 ]); - state_add(HPHYBRID_SE, "SE" , m_reg_se); - state_add(HPHYBRID_R25, "R25" , m_reg_r25).noshow(); - state_add(HPHYBRID_R26, "R26" , m_reg_r26).noshow(); - state_add(HPHYBRID_R27, "R27" , m_reg_r27).noshow(); - state_add(HPHYBRID_R32, "R32" , m_reg_aec[ 0 ]); - state_add(HPHYBRID_R33, "R33" , m_reg_aec[ 1 ]); - state_add(HPHYBRID_R34, "R34" , m_reg_aec[ 2 ]); - state_add(HPHYBRID_R35, "R35" , m_reg_aec[ 3 ]); - state_add(HPHYBRID_R36, "R36" , m_reg_aec[ 4 ]); - state_add(HPHYBRID_R37, "R37" , m_reg_aec[ 5 ]); - - save_item(NAME(m_reg_ar2[ 0 ])); - save_item(NAME(m_reg_ar2[ 1 ])); - save_item(NAME(m_reg_ar2[ 2 ])); - save_item(NAME(m_reg_ar2[ 3 ])); - save_item(NAME(m_reg_se)); - save_item(NAME(m_reg_r25)); - save_item(NAME(m_reg_r26)); - save_item(NAME(m_reg_r27)); - save_item(NAME(m_reg_aec[ 0 ])); - save_item(NAME(m_reg_aec[ 1 ])); - save_item(NAME(m_reg_aec[ 2 ])); - save_item(NAME(m_reg_aec[ 3 ])); - save_item(NAME(m_reg_aec[ 4 ])); - save_item(NAME(m_reg_aec[ 5 ])); + hp_hybrid_cpu_device::device_start(); + + state_add(HPHYBRID_AR2, "Ar2" , m_reg_ar2[ 0 ]); + state_add(HPHYBRID_AR2_2, "Ar2_2" , m_reg_ar2[ 1 ]); + state_add(HPHYBRID_AR2_3, "Ar2_3" , m_reg_ar2[ 2 ]); + state_add(HPHYBRID_AR2_4, "Ar2_4" , m_reg_ar2[ 3 ]); + state_add(HPHYBRID_SE, "SE" , m_reg_se); + state_add(HPHYBRID_R25, "R25" , m_reg_r25).noshow(); + state_add(HPHYBRID_R26, "R26" , m_reg_r26).noshow(); + state_add(HPHYBRID_R27, "R27" , m_reg_r27).noshow(); + state_add(HPHYBRID_R32, "R32" , m_reg_aec[ 0 ]); + state_add(HPHYBRID_R33, "R33" , m_reg_aec[ 1 ]); + state_add(HPHYBRID_R34, "R34" , m_reg_aec[ 2 ]); + state_add(HPHYBRID_R35, "R35" , m_reg_aec[ 3 ]); + state_add(HPHYBRID_R36, "R36" , m_reg_aec[ 4 ]); + state_add(HPHYBRID_R37, "R37" , m_reg_aec[ 5 ]); + + save_item(NAME(m_reg_ar2[ 0 ])); + save_item(NAME(m_reg_ar2[ 1 ])); + save_item(NAME(m_reg_ar2[ 2 ])); + save_item(NAME(m_reg_ar2[ 3 ])); + save_item(NAME(m_reg_se)); + save_item(NAME(m_reg_r25)); + save_item(NAME(m_reg_r26)); + save_item(NAME(m_reg_r27)); + save_item(NAME(m_reg_aec[ 0 ])); + save_item(NAME(m_reg_aec[ 1 ])); + save_item(NAME(m_reg_aec[ 2 ])); + save_item(NAME(m_reg_aec[ 3 ])); + save_item(NAME(m_reg_aec[ 4 ])); + save_item(NAME(m_reg_aec[ 5 ])); } void hp_5061_3001_cpu_device::device_reset() { - // Initial state of AEC registers: - // R32 0 - // R33 5 - // R34 0 - // R35 0 - // R36 0 - // R37 0 - m_reg_aec[ 0 ] = 0; - m_reg_aec[ 1 ] = 5; - m_reg_aec[ 2 ] = 0; - m_reg_aec[ 3 ] = 0; - m_reg_aec[ 4 ] = 0; - m_reg_aec[ 5 ] = 0; - - m_forced_bsc_25 = m_boot_mode; - - hp_hybrid_cpu_device::device_reset(); + // Initial state of AEC registers: + // R32 0 + // R33 5 + // R34 0 + // R35 0 + // R36 0 + // R37 0 + m_reg_aec[ 0 ] = 0; + m_reg_aec[ 1 ] = 5; + m_reg_aec[ 2 ] = 0; + m_reg_aec[ 3 ] = 0; + m_reg_aec[ 4 ] = 0; + m_reg_aec[ 5 ] = 0; + + m_forced_bsc_25 = m_boot_mode; + + hp_hybrid_cpu_device::device_reset(); } UINT8 hp_5061_3001_cpu_device::do_dec_shift_r(UINT8 d1 , UINT64& mantissa) { - UINT8 d12 = (UINT8)(mantissa & 0xf); + UINT8 d12 = (UINT8)(mantissa & 0xf); - mantissa = (mantissa >> 4) | ((UINT64)d1 << 44); + mantissa = (mantissa >> 4) | ((UINT64)d1 << 44); - return d12; + return d12; } UINT8 hp_5061_3001_cpu_device::do_dec_shift_l(UINT8 d12 , UINT64& mantissa) { - UINT8 d1 = (UINT8)((mantissa >> 44) & 0xf); + UINT8 d1 = (UINT8)((mantissa >> 44) & 0xf); - mantissa = (mantissa << 4) | ((UINT64)d12); - mantissa &= 0xffffffffffffULL; + mantissa = (mantissa << 4) | ((UINT64)d12); + mantissa &= 0xffffffffffffULL; - return d1; + return d1; } UINT64 hp_5061_3001_cpu_device::get_ar1(void) { - UINT32 addr; - UINT64 tmp; + UINT32 addr; + UINT64 tmp; - addr = add_mae(AEC_CASE_B , HP_REG_AR1_ADDR + 1); - tmp = (UINT64)RM(addr++); - tmp <<= 16; - tmp |= (UINT64)RM(addr++); - tmp <<= 16; - tmp |= (UINT64)RM(addr); + addr = add_mae(AEC_CASE_B , HP_REG_AR1_ADDR + 1); + tmp = (UINT64)RM(addr++); + tmp <<= 16; + tmp |= (UINT64)RM(addr++); + tmp <<= 16; + tmp |= (UINT64)RM(addr); - return tmp; + return tmp; } void hp_5061_3001_cpu_device::set_ar1(UINT64 v) { - UINT32 addr; - - addr = add_mae(AEC_CASE_B , HP_REG_AR1_ADDR + 3); - WM(addr-- , (UINT16)(v & 0xffff)); - v >>= 16; - WM(addr-- , (UINT16)(v & 0xffff)); - v >>= 16; - WM(addr , (UINT16)(v & 0xffff)); + UINT32 addr; + + addr = add_mae(AEC_CASE_B , HP_REG_AR1_ADDR + 3); + WM(addr-- , (UINT16)(v & 0xffff)); + v >>= 16; + WM(addr-- , (UINT16)(v & 0xffff)); + v >>= 16; + WM(addr , (UINT16)(v & 0xffff)); } UINT64 hp_5061_3001_cpu_device::get_ar2(void) const { - UINT64 tmp; + UINT64 tmp; - tmp = (UINT64)m_reg_ar2[ 1 ]; - tmp <<= 16; - tmp |= (UINT64)m_reg_ar2[ 2 ]; - tmp <<= 16; - tmp |= (UINT64)m_reg_ar2[ 3 ]; + tmp = (UINT64)m_reg_ar2[ 1 ]; + tmp <<= 16; + tmp |= (UINT64)m_reg_ar2[ 2 ]; + tmp <<= 16; + tmp |= (UINT64)m_reg_ar2[ 3 ]; - return tmp; + return tmp; } void hp_5061_3001_cpu_device::set_ar2(UINT64 v) { - m_reg_ar2[ 3 ] = (UINT16)(v & 0xffff); - v >>= 16; - m_reg_ar2[ 2 ] = (UINT16)(v & 0xffff); - v >>= 16; - m_reg_ar2[ 1 ] = (UINT16)(v & 0xffff); + m_reg_ar2[ 3 ] = (UINT16)(v & 0xffff); + v >>= 16; + m_reg_ar2[ 2 ] = (UINT16)(v & 0xffff); + v >>= 16; + m_reg_ar2[ 1 ] = (UINT16)(v & 0xffff); } UINT64 hp_5061_3001_cpu_device::do_mrxy(UINT64 ar) { - UINT8 n; - - n = m_reg_B & 0xf; - m_reg_A &= 0xf; - m_reg_se = m_reg_A; - while (n--) { - m_reg_se = do_dec_shift_r(m_reg_A , ar); - m_reg_A = 0; - m_icount -= 4; - } - m_reg_A = m_reg_se; - BIT_CLR(m_flags , HPHYBRID_DC_BIT); - - return ar; + UINT8 n; + + n = m_reg_B & 0xf; + m_reg_A &= 0xf; + m_reg_se = m_reg_A; + while (n--) { + m_reg_se = do_dec_shift_r(m_reg_A , ar); + m_reg_A = 0; + m_icount -= 4; + } + m_reg_A = m_reg_se; + BIT_CLR(m_flags , HPHYBRID_DC_BIT); + + return ar; } bool hp_5061_3001_cpu_device::do_dec_add(bool carry_in , UINT64& a , UINT64 b) { - UINT64 tmp = 0; - unsigned i; - UINT8 digit_a , digit_b; + UINT64 tmp = 0; + unsigned i; + UINT8 digit_a , digit_b; - for (i = 0; i < 12; i++) { - digit_a = (UINT8)(a & 0xf); - digit_b = (UINT8)(b & 0xf); + for (i = 0; i < 12; i++) { + digit_a = (UINT8)(a & 0xf); + digit_b = (UINT8)(b & 0xf); - if (carry_in) { - digit_a++; - } + if (carry_in) { + digit_a++; + } - digit_a += digit_b; + digit_a += digit_b; - carry_in = digit_a >= 10; + carry_in = digit_a >= 10; - if (carry_in) { - digit_a = (digit_a - 10) & 0xf; - } + if (carry_in) { + digit_a = (digit_a - 10) & 0xf; + } - tmp |= (UINT64)digit_a << (4 * i); + tmp |= (UINT64)digit_a << (4 * i); - a >>= 4; - b >>= 4; - } + a >>= 4; + b >>= 4; + } - a = tmp; + a = tmp; - return carry_in; + return carry_in; } void hp_5061_3001_cpu_device::do_mpy(void) { - INT32 a = (INT16)m_reg_A; - INT32 b = (INT16)m_reg_B; - INT32 p = a * b; + INT32 a = (INT16)m_reg_A; + INT32 b = (INT16)m_reg_B; + INT32 p = a * b; - m_reg_A = (UINT16)(p & 0xffff); - m_reg_B = (UINT16)((p >> 16) & 0xffff); + m_reg_A = (UINT16)(p & 0xffff); + m_reg_B = (UINT16)((p >> 16) & 0xffff); - // Not entirely correct, timing depends on initial content of A register - m_icount -= 65; + // Not entirely correct, timing depends on initial content of A register + m_icount -= 65; } UINT16 hp_5061_3001_cpu_device::execute_no_bpc_ioc(UINT16 opcode) { - // EMC instructions - UINT8 n; - UINT16 tmp1; - UINT16 tmp2; - UINT64 tmp_ar; - UINT64 tmp_ar2; - bool carry; - - switch (opcode & 0xfff0) { - case 0x7300: - // XFR - tmp1 = m_reg_A; - tmp2 = m_reg_B; - n = (opcode & 0xf) + 1; - m_icount -= 21; - while (n--) { - m_icount -= 12; - WM(AEC_CASE_C , tmp2 , RM(AEC_CASE_C , tmp1)); - tmp1++; - tmp2++; - } - break; - - case 0x7380: - // CLR - tmp1 = m_reg_A; - n = (opcode & 0xf) + 1; - m_icount -= 16; - while (n--) { - m_icount -= 6; - WM(AEC_CASE_C , tmp1 , 0); - tmp1++; - } - break; - - default: - switch (opcode) { - case 0x7200: - // MWA - m_icount -= 28; - tmp_ar2 = get_ar2(); - carry = do_dec_add(BIT(m_flags , HPHYBRID_DC_BIT) , tmp_ar2 , m_reg_B); - set_ar2(tmp_ar2); - if (carry) { - BIT_SET(m_flags, HPHYBRID_DC_BIT); - } else { - BIT_CLR(m_flags, HPHYBRID_DC_BIT); - } - break; - - case 0x7220: - // CMY - m_icount -= 23; - tmp_ar2 = get_ar2(); - tmp_ar2 = 0x999999999999ULL - tmp_ar2; - do_dec_add(true , tmp_ar2 , 0); - set_ar2(tmp_ar2); - BIT_CLR(m_flags , HPHYBRID_DC_BIT); - break; - - case 0x7260: - // CMX - m_icount -= 59; - tmp_ar = get_ar1(); - tmp_ar = 0x999999999999ULL - tmp_ar; - do_dec_add(true , tmp_ar , 0); - set_ar1(tmp_ar); - BIT_CLR(m_flags , HPHYBRID_DC_BIT); - break; - - case 0x7280: - // FXA - m_icount -= 40; - tmp_ar2 = get_ar2(); - carry = do_dec_add(BIT(m_flags , HPHYBRID_DC_BIT) , tmp_ar2 , get_ar1()); - set_ar2(tmp_ar2); - if (carry) { - BIT_SET(m_flags, HPHYBRID_DC_BIT); - } else { - BIT_CLR(m_flags, HPHYBRID_DC_BIT); - } - break; - - case 0x7340: - // NRM - tmp_ar2 = get_ar2(); - m_icount -= 23; - for (n = 0; n < 12 && (tmp_ar2 & 0xf00000000000ULL) == 0; n++) { - do_dec_shift_l(0 , tmp_ar2); - m_icount--; - } - m_reg_B = n; - if (n < 12) { - BIT_CLR(m_flags , HPHYBRID_DC_BIT); - set_ar2(tmp_ar2); - } else { - BIT_SET(m_flags , HPHYBRID_DC_BIT); - // When ar2 is 0, total time is 69 cycles - // (salcazzo che cosa fa per altri 34 cicli) - m_icount -= 34; - } - break; - - case 0x73c0: - // CDC - m_icount -= 11; - BIT_CLR(m_flags , HPHYBRID_DC_BIT); - break; - - case 0x7a00: - // FMP - m_icount -= 42; - m_reg_A = 0; - tmp_ar = get_ar1(); - tmp_ar2 = get_ar2(); - for (n = m_reg_B & 0xf; n > 0; n--) { - m_icount -= 13; - if (do_dec_add(BIT(m_flags , HPHYBRID_DC_BIT) , tmp_ar2 , tmp_ar)) { - m_reg_A++; - } - BIT_CLR(m_flags , HPHYBRID_DC_BIT); - } - set_ar2(tmp_ar2); - break; - - case 0x7a21: - // FDV - // No doc mentions any limit on the iterations done by this instruction. - // Here we stop at 15 (after all there are only 4 bits in the loop counter). But is it correct? - m_icount -= 37; - m_reg_B = 0; - tmp_ar = get_ar1(); - tmp_ar2 = get_ar2(); - while (m_reg_B < 15 && !do_dec_add(BIT(m_flags , HPHYBRID_DC_BIT) , tmp_ar2 , tmp_ar)) { - m_icount -= 13; - BIT_CLR(m_flags , HPHYBRID_DC_BIT); - m_reg_B++; - } - set_ar2(tmp_ar2); - break; - - case 0x7b00: - // MRX - set_ar1(do_mrxy(get_ar1())); - m_icount -= 62; - break; - - case 0x7b21: - // DRS - tmp_ar = get_ar1(); - m_icount -= 56; - m_reg_A = m_reg_se = do_dec_shift_r(0 , tmp_ar); - set_ar1(tmp_ar); - BIT_CLR(m_flags , HPHYBRID_DC_BIT); - break; - - case 0x7b40: - // MRY - set_ar2(do_mrxy(get_ar2())); - m_icount -= 33; - break; - - case 0x7b61: - // MLY - tmp_ar2 = get_ar2(); - m_icount -= 32; - m_reg_A = m_reg_se = do_dec_shift_l(m_reg_A & 0xf , tmp_ar2); - set_ar2(tmp_ar2); - BIT_CLR(m_flags , HPHYBRID_DC_BIT); - break; - - case 0x7b8f: - // MPY - do_mpy(); - break; - - default: - if ((opcode & 0xfec0) == 0x74c0) { - // SDS - // SDC - m_icount -= 14; - return get_skip_addr(opcode , !BIT(m_flags , HPHYBRID_DC_BIT)); - } else { - // Unrecognized instructions: NOP - // Execution time is fictional - logerror("hp-5061-3001: unknown opcode %04x @ %06x\n" , opcode , m_genpc); - m_icount -= 6; - } - break; - } - } - - return m_reg_P + 1; + // EMC instructions + UINT8 n; + UINT16 tmp1; + UINT16 tmp2; + UINT64 tmp_ar; + UINT64 tmp_ar2; + bool carry; + + switch (opcode & 0xfff0) { + case 0x7300: + // XFR + tmp1 = m_reg_A; + tmp2 = m_reg_B; + n = (opcode & 0xf) + 1; + m_icount -= 21; + while (n--) { + m_icount -= 12; + WM(AEC_CASE_C , tmp2 , RM(AEC_CASE_C , tmp1)); + tmp1++; + tmp2++; + } + break; + + case 0x7380: + // CLR + tmp1 = m_reg_A; + n = (opcode & 0xf) + 1; + m_icount -= 16; + while (n--) { + m_icount -= 6; + WM(AEC_CASE_C , tmp1 , 0); + tmp1++; + } + break; + + default: + switch (opcode) { + case 0x7200: + // MWA + m_icount -= 28; + tmp_ar2 = get_ar2(); + carry = do_dec_add(BIT(m_flags , HPHYBRID_DC_BIT) , tmp_ar2 , m_reg_B); + set_ar2(tmp_ar2); + if (carry) { + BIT_SET(m_flags, HPHYBRID_DC_BIT); + } else { + BIT_CLR(m_flags, HPHYBRID_DC_BIT); + } + break; + + case 0x7220: + // CMY + m_icount -= 23; + tmp_ar2 = get_ar2(); + tmp_ar2 = 0x999999999999ULL - tmp_ar2; + do_dec_add(true , tmp_ar2 , 0); + set_ar2(tmp_ar2); + BIT_CLR(m_flags , HPHYBRID_DC_BIT); + break; + + case 0x7260: + // CMX + m_icount -= 59; + tmp_ar = get_ar1(); + tmp_ar = 0x999999999999ULL - tmp_ar; + do_dec_add(true , tmp_ar , 0); + set_ar1(tmp_ar); + BIT_CLR(m_flags , HPHYBRID_DC_BIT); + break; + + case 0x7280: + // FXA + m_icount -= 40; + tmp_ar2 = get_ar2(); + carry = do_dec_add(BIT(m_flags , HPHYBRID_DC_BIT) , tmp_ar2 , get_ar1()); + set_ar2(tmp_ar2); + if (carry) { + BIT_SET(m_flags, HPHYBRID_DC_BIT); + } else { + BIT_CLR(m_flags, HPHYBRID_DC_BIT); + } + break; + + case 0x7340: + // NRM + tmp_ar2 = get_ar2(); + m_icount -= 23; + for (n = 0; n < 12 && (tmp_ar2 & 0xf00000000000ULL) == 0; n++) { + do_dec_shift_l(0 , tmp_ar2); + m_icount--; + } + m_reg_B = n; + if (n < 12) { + BIT_CLR(m_flags , HPHYBRID_DC_BIT); + set_ar2(tmp_ar2); + } else { + BIT_SET(m_flags , HPHYBRID_DC_BIT); + // When ar2 is 0, total time is 69 cycles + // (salcazzo che cosa fa per altri 34 cicli) + m_icount -= 34; + } + break; + + case 0x73c0: + // CDC + m_icount -= 11; + BIT_CLR(m_flags , HPHYBRID_DC_BIT); + break; + + case 0x7a00: + // FMP + m_icount -= 42; + m_reg_A = 0; + tmp_ar = get_ar1(); + tmp_ar2 = get_ar2(); + for (n = m_reg_B & 0xf; n > 0; n--) { + m_icount -= 13; + if (do_dec_add(BIT(m_flags , HPHYBRID_DC_BIT) , tmp_ar2 , tmp_ar)) { + m_reg_A++; + } + BIT_CLR(m_flags , HPHYBRID_DC_BIT); + } + set_ar2(tmp_ar2); + break; + + case 0x7a21: + // FDV + // No doc mentions any limit on the iterations done by this instruction. + // Here we stop at 15 (after all there are only 4 bits in the loop counter). But is it correct? + m_icount -= 37; + m_reg_B = 0; + tmp_ar = get_ar1(); + tmp_ar2 = get_ar2(); + while (m_reg_B < 15 && !do_dec_add(BIT(m_flags , HPHYBRID_DC_BIT) , tmp_ar2 , tmp_ar)) { + m_icount -= 13; + BIT_CLR(m_flags , HPHYBRID_DC_BIT); + m_reg_B++; + } + set_ar2(tmp_ar2); + break; + + case 0x7b00: + // MRX + set_ar1(do_mrxy(get_ar1())); + m_icount -= 62; + break; + + case 0x7b21: + // DRS + tmp_ar = get_ar1(); + m_icount -= 56; + m_reg_A = m_reg_se = do_dec_shift_r(0 , tmp_ar); + set_ar1(tmp_ar); + BIT_CLR(m_flags , HPHYBRID_DC_BIT); + break; + + case 0x7b40: + // MRY + set_ar2(do_mrxy(get_ar2())); + m_icount -= 33; + break; + + case 0x7b61: + // MLY + tmp_ar2 = get_ar2(); + m_icount -= 32; + m_reg_A = m_reg_se = do_dec_shift_l(m_reg_A & 0xf , tmp_ar2); + set_ar2(tmp_ar2); + BIT_CLR(m_flags , HPHYBRID_DC_BIT); + break; + + case 0x7b8f: + // MPY + do_mpy(); + break; + + default: + if ((opcode & 0xfec0) == 0x74c0) { + // SDS + // SDC + m_icount -= 14; + return get_skip_addr(opcode , !BIT(m_flags , HPHYBRID_DC_BIT)); + } else { + // Unrecognized instructions: NOP + // Execution time is fictional + logerror("hp-5061-3001: unknown opcode %04x @ %06x\n" , opcode , m_genpc); + m_icount -= 6; + } + break; + } + } + + return m_reg_P + 1; } offs_t hp_5061_3001_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { - extern CPU_DISASSEMBLE(hp_5061_3001); - return CPU_DISASSEMBLE_NAME(hp_5061_3001)(this, buffer, pc, oprom, opram, options); + extern CPU_DISASSEMBLE(hp_5061_3001); + return CPU_DISASSEMBLE_NAME(hp_5061_3001)(this, buffer, pc, oprom, opram, options); } UINT32 hp_5061_3001_cpu_device::add_mae(aec_cases_t aec_case , UINT16 addr) { - UINT16 bsc_reg; - bool top_half = BIT(addr , 15) != 0; + UINT16 bsc_reg; + bool top_half = BIT(addr , 15) != 0; - // Detect accesses to top half of base page - if (aec_case == AEC_CASE_C && (addr & 0xfe00) == 0xfe00) { - aec_case = AEC_CASE_B; - } + // Detect accesses to top half of base page + if (aec_case == AEC_CASE_C && (addr & 0xfe00) == 0xfe00) { + aec_case = AEC_CASE_B; + } - switch (aec_case) { - case AEC_CASE_A: - bsc_reg = top_half ? HP_REG_R34_ADDR : HP_REG_R33_ADDR; - break; + switch (aec_case) { + case AEC_CASE_A: + bsc_reg = top_half ? HP_REG_R34_ADDR : HP_REG_R33_ADDR; + break; - case AEC_CASE_B: - bsc_reg = top_half ? HP_REG_R36_ADDR : HP_REG_R33_ADDR; - break; + case AEC_CASE_B: + bsc_reg = top_half ? HP_REG_R36_ADDR : HP_REG_R33_ADDR; + break; - case AEC_CASE_C: - bsc_reg = top_half ? HP_REG_R32_ADDR : HP_REG_R35_ADDR; - break; + case AEC_CASE_C: + bsc_reg = top_half ? HP_REG_R32_ADDR : HP_REG_R35_ADDR; + break; - case AEC_CASE_D: - bsc_reg = HP_REG_R37_ADDR; - break; + case AEC_CASE_D: + bsc_reg = HP_REG_R37_ADDR; + break; - default: - logerror("hphybrid: aec_case=%d\n" , aec_case); - return 0; - } + default: + logerror("hphybrid: aec_case=%d\n" , aec_case); + return 0; + } - UINT16 aec_reg = m_reg_aec[ bsc_reg - HP_REG_R32_ADDR ] & BSC_REG_MASK; + UINT16 aec_reg = m_reg_aec[ bsc_reg - HP_REG_R32_ADDR ] & BSC_REG_MASK; - if (m_forced_bsc_25) { - aec_reg = (aec_reg & 0xf) | 0x20; - } + if (m_forced_bsc_25) { + aec_reg = (aec_reg & 0xf) | 0x20; + } - return (UINT32)addr | ((UINT32)aec_reg << 16); + return (UINT32)addr | ((UINT32)aec_reg << 16); } UINT16 hp_5061_3001_cpu_device::read_non_common_reg(UINT16 addr) { - switch (addr) { - case HP_REG_AR2_ADDR: - case HP_REG_AR2_ADDR + 1: - case HP_REG_AR2_ADDR + 2: - case HP_REG_AR2_ADDR + 3: - return m_reg_ar2[ addr - HP_REG_AR2_ADDR ]; - - case HP_REG_SE_ADDR: - return m_reg_se; - - case HP_REG_R25_ADDR: - return m_reg_r25; - - case HP_REG_R26_ADDR: - return m_reg_r26; - - case HP_REG_R27_ADDR: - return m_reg_r27; - - case HP_REG_R32_ADDR: - case HP_REG_R33_ADDR: - case HP_REG_R34_ADDR: - case HP_REG_R35_ADDR: - case HP_REG_R36_ADDR: - case HP_REG_R37_ADDR: - return m_reg_aec[ addr - HP_REG_R32_ADDR ]; - - default: - return 0; - } + switch (addr) { + case HP_REG_AR2_ADDR: + case HP_REG_AR2_ADDR + 1: + case HP_REG_AR2_ADDR + 2: + case HP_REG_AR2_ADDR + 3: + return m_reg_ar2[ addr - HP_REG_AR2_ADDR ]; + + case HP_REG_SE_ADDR: + return m_reg_se; + + case HP_REG_R25_ADDR: + return m_reg_r25; + + case HP_REG_R26_ADDR: + return m_reg_r26; + + case HP_REG_R27_ADDR: + return m_reg_r27; + + case HP_REG_R32_ADDR: + case HP_REG_R33_ADDR: + case HP_REG_R34_ADDR: + case HP_REG_R35_ADDR: + case HP_REG_R36_ADDR: + case HP_REG_R37_ADDR: + return m_reg_aec[ addr - HP_REG_R32_ADDR ]; + + default: + return 0; + } } void hp_5061_3001_cpu_device::write_non_common_reg(UINT16 addr , UINT16 v) { - switch (addr) { - case HP_REG_AR2_ADDR: - case HP_REG_AR2_ADDR + 1: - case HP_REG_AR2_ADDR + 2: - case HP_REG_AR2_ADDR + 3: - m_reg_ar2[ addr - HP_REG_AR2_ADDR ] = v; - break; - - case HP_REG_SE_ADDR: - m_reg_se = v & HP_REG_SE_MASK; - break; - - case HP_REG_R25_ADDR: - m_reg_r25 = v; - break; - - case HP_REG_R26_ADDR: - m_reg_r26 = v; - break; - - case HP_REG_R27_ADDR: - m_reg_r27 = v; - break; - - case HP_REG_R32_ADDR: - case HP_REG_R33_ADDR: - case HP_REG_R34_ADDR: - case HP_REG_R35_ADDR: - case HP_REG_R36_ADDR: - case HP_REG_R37_ADDR: - m_reg_aec[ addr - HP_REG_R32_ADDR ] = v; - break; - - default: - break; - } + switch (addr) { + case HP_REG_AR2_ADDR: + case HP_REG_AR2_ADDR + 1: + case HP_REG_AR2_ADDR + 2: + case HP_REG_AR2_ADDR + 3: + m_reg_ar2[ addr - HP_REG_AR2_ADDR ] = v; + break; + + case HP_REG_SE_ADDR: + m_reg_se = v & HP_REG_SE_MASK; + break; + + case HP_REG_R25_ADDR: + m_reg_r25 = v; + break; + + case HP_REG_R26_ADDR: + m_reg_r26 = v; + break; + + case HP_REG_R27_ADDR: + m_reg_r27 = v; + break; + + case HP_REG_R32_ADDR: + case HP_REG_R33_ADDR: + case HP_REG_R34_ADDR: + case HP_REG_R35_ADDR: + case HP_REG_R36_ADDR: + case HP_REG_R37_ADDR: + m_reg_aec[ addr - HP_REG_R32_ADDR ] = v; + break; + + default: + break; + } } hp_5061_3011_cpu_device::hp_5061_3011_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : hp_hybrid_cpu_device(mconfig, HP_5061_3011, "HP-5061-3011", tag, owner, clock, "5061-3011", 16) + : hp_hybrid_cpu_device(mconfig, HP_5061_3011, "HP-5061-3011", tag, owner, clock, "5061-3011", 16) { } UINT16 hp_5061_3011_cpu_device::execute_no_bpc_ioc(UINT16 opcode) { - // Unrecognized instructions: NOP - // Execution time is fictional - m_icount -= 6; + // Unrecognized instructions: NOP + // Execution time is fictional + m_icount -= 6; - return m_reg_P + 1; + return m_reg_P + 1; } UINT32 hp_5061_3011_cpu_device::add_mae(aec_cases_t aec_case , UINT16 addr) { - // No MAE on 3011 - return addr; + // No MAE on 3011 + return addr; } UINT16 hp_5061_3011_cpu_device::read_non_common_reg(UINT16 addr) { - // Non-existing registers are returned as 0 - return 0; + // Non-existing registers are returned as 0 + return 0; } void hp_5061_3011_cpu_device::write_non_common_reg(UINT16 addr , UINT16 v) { - // Non-existing registers are silently discarded + // Non-existing registers are silently discarded } - diff --git a/src/devices/cpu/hphybrid/hphybrid.h b/src/devices/cpu/hphybrid/hphybrid.h index 6526b87020d..57609e24e63 100644 --- a/src/devices/cpu/hphybrid/hphybrid.h +++ b/src/devices/cpu/hphybrid/hphybrid.h @@ -77,166 +77,166 @@ // PA changed callback #define MCFG_HPHYBRID_PA_CHANGED(_devcb) \ - hp_hybrid_cpu_device::set_pa_changed_func(*device , DEVCB_##_devcb); + hp_hybrid_cpu_device::set_pa_changed_func(*device , DEVCB_##_devcb); class hp_hybrid_cpu_device : public cpu_device { public: - DECLARE_WRITE_LINE_MEMBER(dmar_w); - DECLARE_WRITE_LINE_MEMBER(halt_w); - DECLARE_WRITE_LINE_MEMBER(status_w); - DECLARE_WRITE_LINE_MEMBER(flag_w); + DECLARE_WRITE_LINE_MEMBER(dmar_w); + DECLARE_WRITE_LINE_MEMBER(halt_w); + DECLARE_WRITE_LINE_MEMBER(status_w); + DECLARE_WRITE_LINE_MEMBER(flag_w); - template<class _Object> static devcb_base &set_pa_changed_func(device_t &device, _Object object) { return downcast<hp_hybrid_cpu_device &>(device).m_pa_changed_func.set_callback(object); } + template<class _Object> static devcb_base &set_pa_changed_func(device_t &device, _Object object) { return downcast<hp_hybrid_cpu_device &>(device).m_pa_changed_func.set_callback(object); } protected: - hp_hybrid_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname , UINT8 addrwidth); - - // device-level overrides - virtual void device_start() override; - virtual void device_reset() override; - - // device_execute_interface overrides - virtual UINT32 execute_min_cycles() const override { return 6; } - virtual UINT32 execute_input_lines() const override { return 2; } - virtual UINT32 execute_default_irq_vector() const override { return 0xffff; } - virtual void execute_run() override; - virtual void execute_set_input(int inputnum, int state) override; - - UINT16 execute_one(UINT16 opcode); - UINT16 execute_one_sub(UINT16 opcode); - // Execute an instruction that doesn't belong to either BPC or IOC - virtual UINT16 execute_no_bpc_ioc(UINT16 opcode) = 0; - - // device_memory_interface overrides - virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const override { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); } - - // device_state_interface overrides - void state_string_export(const device_state_entry &entry, std::string &str) override; - - // device_disasm_interface overrides - virtual UINT32 disasm_min_opcode_bytes() const override { return 2; } - virtual UINT32 disasm_max_opcode_bytes() const override { return 2; } - virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) override; - - // Different cases of memory access - // See patent @ pg 361 - typedef enum { - AEC_CASE_A, // Instr. fetches, non-base page fetches of link pointers, BPC direct non-base page accesses - AEC_CASE_B, // Base page fetches of link pointers, BPC direct base page accesses - AEC_CASE_C, // IOC, EMC & BPC indirect final destination accesses - AEC_CASE_D // DMA accesses - } aec_cases_t; - - // do memory address extension - virtual UINT32 add_mae(aec_cases_t aec_case , UINT16 addr) = 0; - - UINT16 remove_mae(UINT32 addr); - - UINT16 RM(aec_cases_t aec_case , UINT16 addr); - UINT16 RM(UINT32 addr); - virtual UINT16 read_non_common_reg(UINT16 addr) = 0; - - void WM(aec_cases_t aec_case , UINT16 addr , UINT16 v); - void WM(UINT32 addr , UINT16 v); - virtual void write_non_common_reg(UINT16 addr , UINT16 v) = 0; - - UINT16 fetch(void); - - UINT16 get_skip_addr(UINT16 opcode , bool condition) const; - - devcb_write8 m_pa_changed_func; - - int m_icount; - bool m_forced_bsc_25; - - // State of processor - UINT16 m_reg_A; // Register A - UINT16 m_reg_B; // Register B - UINT16 m_reg_P; // Register P - UINT16 m_reg_R; // Register R - UINT16 m_reg_C; // Register C - UINT16 m_reg_D; // Register D - UINT16 m_reg_IV; // Register IV - UINT16 m_reg_W; // Register W - UINT8 m_reg_PA[ HPHYBRID_INT_LVLS + 1 ]; // Stack of register PA (4 bit-long) - UINT16 m_flags; // Flags - UINT8 m_dmapa; // DMA peripheral address (4 bits) - UINT16 m_dmama; // DMA address - UINT16 m_dmac; // DMA counter - UINT16 m_reg_I; // Instruction register - UINT32 m_genpc; // Full PC + hp_hybrid_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname , UINT8 addrwidth); + + // device-level overrides + virtual void device_start() override; + virtual void device_reset() override; + + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const override { return 6; } + virtual UINT32 execute_input_lines() const override { return 2; } + virtual UINT32 execute_default_irq_vector() const override { return 0xffff; } + virtual void execute_run() override; + virtual void execute_set_input(int inputnum, int state) override; + + UINT16 execute_one(UINT16 opcode); + UINT16 execute_one_sub(UINT16 opcode); + // Execute an instruction that doesn't belong to either BPC or IOC + virtual UINT16 execute_no_bpc_ioc(UINT16 opcode) = 0; + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const override { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); } + + // device_state_interface overrides + void state_string_export(const device_state_entry &entry, std::string &str) override; + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const override { return 2; } + virtual UINT32 disasm_max_opcode_bytes() const override { return 2; } + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) override; + + // Different cases of memory access + // See patent @ pg 361 + typedef enum { + AEC_CASE_A, // Instr. fetches, non-base page fetches of link pointers, BPC direct non-base page accesses + AEC_CASE_B, // Base page fetches of link pointers, BPC direct base page accesses + AEC_CASE_C, // IOC, EMC & BPC indirect final destination accesses + AEC_CASE_D // DMA accesses + } aec_cases_t; + + // do memory address extension + virtual UINT32 add_mae(aec_cases_t aec_case , UINT16 addr) = 0; + + UINT16 remove_mae(UINT32 addr); + + UINT16 RM(aec_cases_t aec_case , UINT16 addr); + UINT16 RM(UINT32 addr); + virtual UINT16 read_non_common_reg(UINT16 addr) = 0; + + void WM(aec_cases_t aec_case , UINT16 addr , UINT16 v); + void WM(UINT32 addr , UINT16 v); + virtual void write_non_common_reg(UINT16 addr , UINT16 v) = 0; + + UINT16 fetch(void); + + UINT16 get_skip_addr(UINT16 opcode , bool condition) const; + + devcb_write8 m_pa_changed_func; + + int m_icount; + bool m_forced_bsc_25; + + // State of processor + UINT16 m_reg_A; // Register A + UINT16 m_reg_B; // Register B + UINT16 m_reg_P; // Register P + UINT16 m_reg_R; // Register R + UINT16 m_reg_C; // Register C + UINT16 m_reg_D; // Register D + UINT16 m_reg_IV; // Register IV + UINT16 m_reg_W; // Register W + UINT8 m_reg_PA[ HPHYBRID_INT_LVLS + 1 ]; // Stack of register PA (4 bit-long) + UINT16 m_flags; // Flags + UINT8 m_dmapa; // DMA peripheral address (4 bits) + UINT16 m_dmama; // DMA address + UINT16 m_dmac; // DMA counter + UINT16 m_reg_I; // Instruction register + UINT32 m_genpc; // Full PC private: - address_space_config m_program_config; - address_space_config m_io_config; - - address_space *m_program; - direct_read_data *m_direct; - address_space *m_io; - - UINT32 get_ea(UINT16 opcode); - void do_add(UINT16& addend1 , UINT16 addend2); - UINT16 get_skip_addr_sc(UINT16 opcode , UINT16& v , unsigned n); - void do_pw(UINT16 opcode); - void check_for_interrupts(void); - void handle_dma(void); - - UINT16 RIO(UINT8 pa , UINT8 ic); - void WIO(UINT8 pa , UINT8 ic , UINT16 v); + address_space_config m_program_config; + address_space_config m_io_config; + + address_space *m_program; + direct_read_data *m_direct; + address_space *m_io; + + UINT32 get_ea(UINT16 opcode); + void do_add(UINT16& addend1 , UINT16 addend2); + UINT16 get_skip_addr_sc(UINT16 opcode , UINT16& v , unsigned n); + void do_pw(UINT16 opcode); + void check_for_interrupts(void); + void handle_dma(void); + + UINT16 RIO(UINT8 pa , UINT8 ic); + void WIO(UINT8 pa , UINT8 ic , UINT16 v); }; class hp_5061_3001_cpu_device : public hp_hybrid_cpu_device { public: - hp_5061_3001_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + hp_5061_3001_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); static void set_boot_mode_static(device_t &device, bool mode) { downcast<hp_5061_3001_cpu_device &>(device).m_boot_mode = mode; } protected: - virtual void device_start() override; - virtual void device_reset() override; - virtual UINT32 execute_max_cycles() const override { return 237; } // FMP 15 - - static UINT8 do_dec_shift_r(UINT8 d1 , UINT64& mantissa); - static UINT8 do_dec_shift_l(UINT8 d12 , UINT64& mantissa); - UINT64 get_ar1(void); - void set_ar1(UINT64 v); - UINT64 get_ar2(void) const; - void set_ar2(UINT64 v); - UINT64 do_mrxy(UINT64 ar); - bool do_dec_add(bool carry_in , UINT64& a , UINT64 b); - void do_mpy(void); - - virtual UINT16 execute_no_bpc_ioc(UINT16 opcode) override; - virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) override; - virtual UINT32 add_mae(aec_cases_t aec_case , UINT16 addr) override; - virtual UINT16 read_non_common_reg(UINT16 addr) override; - virtual void write_non_common_reg(UINT16 addr , UINT16 v) override; + virtual void device_start() override; + virtual void device_reset() override; + virtual UINT32 execute_max_cycles() const override { return 237; } // FMP 15 + + static UINT8 do_dec_shift_r(UINT8 d1 , UINT64& mantissa); + static UINT8 do_dec_shift_l(UINT8 d12 , UINT64& mantissa); + UINT64 get_ar1(void); + void set_ar1(UINT64 v); + UINT64 get_ar2(void) const; + void set_ar2(UINT64 v); + UINT64 do_mrxy(UINT64 ar); + bool do_dec_add(bool carry_in , UINT64& a , UINT64 b); + void do_mpy(void); + + virtual UINT16 execute_no_bpc_ioc(UINT16 opcode) override; + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) override; + virtual UINT32 add_mae(aec_cases_t aec_case , UINT16 addr) override; + virtual UINT16 read_non_common_reg(UINT16 addr) override; + virtual void write_non_common_reg(UINT16 addr , UINT16 v) override; private: - bool m_boot_mode; - - // Additional state of processor - UINT16 m_reg_ar2[ 4 ]; // AR2 register - UINT16 m_reg_se; // SE register (4 bits) - UINT16 m_reg_r25; // R25 register - UINT16 m_reg_r26; // R26 register - UINT16 m_reg_r27; // R27 register - UINT16 m_reg_aec[ HP_REG_R37_ADDR - HP_REG_R32_ADDR + 1 ]; // AEC registers R32-R37 + bool m_boot_mode; + + // Additional state of processor + UINT16 m_reg_ar2[ 4 ]; // AR2 register + UINT16 m_reg_se; // SE register (4 bits) + UINT16 m_reg_r25; // R25 register + UINT16 m_reg_r26; // R26 register + UINT16 m_reg_r27; // R27 register + UINT16 m_reg_aec[ HP_REG_R37_ADDR - HP_REG_R32_ADDR + 1 ]; // AEC registers R32-R37 }; class hp_5061_3011_cpu_device : public hp_hybrid_cpu_device { public: - hp_5061_3011_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + hp_5061_3011_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); protected: - virtual UINT32 execute_max_cycles() const override { return 25; } - virtual UINT16 execute_no_bpc_ioc(UINT16 opcode) override; - virtual UINT32 add_mae(aec_cases_t aec_case , UINT16 addr) override; - virtual UINT16 read_non_common_reg(UINT16 addr) override; - virtual void write_non_common_reg(UINT16 addr , UINT16 v) override; + virtual UINT32 execute_max_cycles() const override { return 25; } + virtual UINT16 execute_no_bpc_ioc(UINT16 opcode) override; + virtual UINT32 add_mae(aec_cases_t aec_case , UINT16 addr) override; + virtual UINT16 read_non_common_reg(UINT16 addr) override; + virtual void write_non_common_reg(UINT16 addr , UINT16 v) override; }; diff --git a/src/devices/cpu/hphybrid/hphybrid_dasm.cpp b/src/devices/cpu/hphybrid/hphybrid_dasm.cpp index 3c6efb68f58..48b03b4afb4 100644 --- a/src/devices/cpu/hphybrid/hphybrid_dasm.cpp +++ b/src/devices/cpu/hphybrid/hphybrid_dasm.cpp @@ -20,151 +20,151 @@ typedef struct { static void addr_2_str(char *buffer , UINT16 addr , bool indirect , bool is_3001) { - char *s = buffer + strlen(buffer); + char *s = buffer + strlen(buffer); - s += sprintf(s , "$%04x" , addr); - - if (is_3001) { - switch (addr) { - case HP_REG_AR1_ADDR: - strcpy(s , "(Ar1)"); - break; + s += sprintf(s , "$%04x" , addr); - case HP_REG_AR1_ADDR + 1: - strcpy(s , "(Ar1_2)"); - break; + if (is_3001) { + switch (addr) { + case HP_REG_AR1_ADDR: + strcpy(s , "(Ar1)"); + break; - case HP_REG_AR1_ADDR + 2: - strcpy(s , "(Ar1_3)"); - break; + case HP_REG_AR1_ADDR + 1: + strcpy(s , "(Ar1_2)"); + break; - case HP_REG_AR1_ADDR + 3: - strcpy(s , "(Ar1_4)"); - break; + case HP_REG_AR1_ADDR + 2: + strcpy(s , "(Ar1_3)"); + break; - case HP_REG_AR2_ADDR: - strcpy(s , "(Ar2)"); - break; + case HP_REG_AR1_ADDR + 3: + strcpy(s , "(Ar1_4)"); + break; - case HP_REG_AR2_ADDR + 1: - strcpy(s , "(Ar2_2)"); - break; + case HP_REG_AR2_ADDR: + strcpy(s , "(Ar2)"); + break; - case HP_REG_AR2_ADDR + 2: - strcpy(s , "(Ar2_3)"); - break; + case HP_REG_AR2_ADDR + 1: + strcpy(s , "(Ar2_2)"); + break; - case HP_REG_AR2_ADDR + 3: - strcpy(s , "(Ar2_4)"); - break; + case HP_REG_AR2_ADDR + 2: + strcpy(s , "(Ar2_3)"); + break; - case HP_REG_SE_ADDR: - strcpy(s , "(SE)"); - break; + case HP_REG_AR2_ADDR + 3: + strcpy(s , "(Ar2_4)"); + break; - case HP_REG_R25_ADDR: - strcpy(s , "(R25)"); - break; - - case HP_REG_R26_ADDR: - strcpy(s , "(R26)"); - break; - - case HP_REG_R27_ADDR: - strcpy(s , "(R27)"); - break; - - case HP_REG_R32_ADDR: - strcpy(s , "(R32)"); - break; - - case HP_REG_R33_ADDR: - strcpy(s , "(R33)"); - break; - - case HP_REG_R34_ADDR: - strcpy(s , "(R34)"); - break; - - case HP_REG_R35_ADDR: - strcpy(s , "(R35)"); - break; - - case HP_REG_R36_ADDR: - strcpy(s , "(R36)"); - break; - - case HP_REG_R37_ADDR: - strcpy(s , "(R37)"); - break; - } - } - - switch (addr) { - case HP_REG_A_ADDR: - strcpy(s , "(A)"); - break; - - case HP_REG_B_ADDR: - strcpy(s , "(B)"); - break; - - case HP_REG_P_ADDR: - strcpy(s , "(P)"); - break; - - case HP_REG_R_ADDR: - strcpy(s , "(R)"); - break; - - case HP_REG_R4_ADDR: - strcpy(s , "(R4)"); - break; - - case HP_REG_R5_ADDR: - strcpy(s , "(R5)"); - break; - - case HP_REG_R6_ADDR: - strcpy(s , "(R6)"); - break; - - case HP_REG_R7_ADDR: - strcpy(s , "(R7)"); - break; - - case HP_REG_IV_ADDR: - strcpy(s , "(IV)"); - break; - - case HP_REG_PA_ADDR: - strcpy(s , "(PA)"); - break; - - case HP_REG_DMAPA_ADDR: - strcpy(s , "(DMAPA)"); - break; - - case HP_REG_DMAMA_ADDR: - strcpy(s , "(DMAMA)"); - break; - - case HP_REG_DMAC_ADDR: - strcpy(s , "(DMAC)"); - break; - - case HP_REG_C_ADDR: - strcpy(s , "(C)"); - break; - - case HP_REG_D_ADDR: - strcpy(s , "(D)"); - break; - } - - if (indirect) { - strcat(s , ",I"); - } + case HP_REG_SE_ADDR: + strcpy(s , "(SE)"); + break; + + case HP_REG_R25_ADDR: + strcpy(s , "(R25)"); + break; + + case HP_REG_R26_ADDR: + strcpy(s , "(R26)"); + break; + + case HP_REG_R27_ADDR: + strcpy(s , "(R27)"); + break; + + case HP_REG_R32_ADDR: + strcpy(s , "(R32)"); + break; + + case HP_REG_R33_ADDR: + strcpy(s , "(R33)"); + break; + + case HP_REG_R34_ADDR: + strcpy(s , "(R34)"); + break; + + case HP_REG_R35_ADDR: + strcpy(s , "(R35)"); + break; + + case HP_REG_R36_ADDR: + strcpy(s , "(R36)"); + break; + + case HP_REG_R37_ADDR: + strcpy(s , "(R37)"); + break; + } + } + + switch (addr) { + case HP_REG_A_ADDR: + strcpy(s , "(A)"); + break; + + case HP_REG_B_ADDR: + strcpy(s , "(B)"); + break; + + case HP_REG_P_ADDR: + strcpy(s , "(P)"); + break; + + case HP_REG_R_ADDR: + strcpy(s , "(R)"); + break; + + case HP_REG_R4_ADDR: + strcpy(s , "(R4)"); + break; + + case HP_REG_R5_ADDR: + strcpy(s , "(R5)"); + break; + + case HP_REG_R6_ADDR: + strcpy(s , "(R6)"); + break; + + case HP_REG_R7_ADDR: + strcpy(s , "(R7)"); + break; + + case HP_REG_IV_ADDR: + strcpy(s , "(IV)"); + break; + + case HP_REG_PA_ADDR: + strcpy(s , "(PA)"); + break; + + case HP_REG_DMAPA_ADDR: + strcpy(s , "(DMAPA)"); + break; + + case HP_REG_DMAMA_ADDR: + strcpy(s , "(DMAMA)"); + break; + + case HP_REG_DMAC_ADDR: + strcpy(s , "(DMAC)"); + break; + + case HP_REG_C_ADDR: + strcpy(s , "(C)"); + break; + + case HP_REG_D_ADDR: + strcpy(s , "(D)"); + break; + } + + if (indirect) { + strcat(s , ",I"); + } } static void param_none(char *buffer , offs_t pc , UINT16 opcode , bool is_3001) @@ -337,77 +337,76 @@ static const dis_entry_t dis_table[] = { }; static const dis_entry_t dis_table_emc[] = { - // *** EMC Instructions *** - {0xffff , 0x7200 , "MWA" , param_none , 0 }, - {0xffff , 0x7220 , "CMY" , param_none , 0 }, - {0xffff , 0x7260 , "CMX" , param_none , 0 }, - {0xffff , 0x7280 , "FXA" , param_none , 0 }, - {0xfff0 , 0x7300 , "XFR" , param_n16 , 0 }, - {0xffff , 0x7340 , "NRM" , param_none , 0 }, - {0xfff0 , 0x7380 , "CLR" , param_n16 , 0 }, - {0xffff , 0x73c0 , "CDC" , param_none , 0 }, - {0xffc0 , 0x74c0 , "SDS" , param_skip , 0 }, - {0xffc0 , 0x75c0 , "SDC" , param_skip , 0 }, - {0xffff , 0x7a00 , "FMP" , param_none , 0 }, - {0xffff , 0x7a21 , "FDV" , param_none , 0 }, - {0xffff , 0x7b00 , "MRX" , param_none , 0 }, - {0xffff , 0x7b21 , "DRS" , param_none , 0 }, - {0xffff , 0x7b40 , "MRY" , param_none , 0 }, - {0xffff , 0x7b61 , "MLY" , param_none , 0 }, - {0xffff , 0x7b8f , "MPY" , param_none , 0 }, - // *** END *** - {0 , 0 , nullptr , nullptr , 0 } + // *** EMC Instructions *** + {0xffff , 0x7200 , "MWA" , param_none , 0 }, + {0xffff , 0x7220 , "CMY" , param_none , 0 }, + {0xffff , 0x7260 , "CMX" , param_none , 0 }, + {0xffff , 0x7280 , "FXA" , param_none , 0 }, + {0xfff0 , 0x7300 , "XFR" , param_n16 , 0 }, + {0xffff , 0x7340 , "NRM" , param_none , 0 }, + {0xfff0 , 0x7380 , "CLR" , param_n16 , 0 }, + {0xffff , 0x73c0 , "CDC" , param_none , 0 }, + {0xffc0 , 0x74c0 , "SDS" , param_skip , 0 }, + {0xffc0 , 0x75c0 , "SDC" , param_skip , 0 }, + {0xffff , 0x7a00 , "FMP" , param_none , 0 }, + {0xffff , 0x7a21 , "FDV" , param_none , 0 }, + {0xffff , 0x7b00 , "MRX" , param_none , 0 }, + {0xffff , 0x7b21 , "DRS" , param_none , 0 }, + {0xffff , 0x7b40 , "MRY" , param_none , 0 }, + {0xffff , 0x7b61 , "MLY" , param_none , 0 }, + {0xffff , 0x7b8f , "MPY" , param_none , 0 }, + // *** END *** + {0 , 0 , nullptr , nullptr , 0 } }; static offs_t disassemble_table(UINT16 opcode , offs_t pc , const dis_entry_t *table , bool is_3001 , char *buffer) { - const dis_entry_t *p; - - for (p = table; p->m_op_mask; p++) { - if ((opcode & p->m_op_mask) == p->m_opcode) { - strcpy(buffer , p->m_mnemonic); - strcat(buffer , " "); - p->m_param_fn(buffer , pc , opcode , is_3001); - return 1 | p->m_dasm_flags | DASMFLAG_SUPPORTED; - } - } - - return 0; + const dis_entry_t *p; + + for (p = table; p->m_op_mask; p++) { + if ((opcode & p->m_op_mask) == p->m_opcode) { + strcpy(buffer , p->m_mnemonic); + strcat(buffer , " "); + p->m_param_fn(buffer , pc , opcode , is_3001); + return 1 | p->m_dasm_flags | DASMFLAG_SUPPORTED; + } + } + + return 0; } CPU_DISASSEMBLE(hp_hybrid) { - UINT16 opcode = ((UINT16)oprom[ 0 ] << 8) | oprom[ 1 ]; - offs_t res; + UINT16 opcode = ((UINT16)oprom[ 0 ] << 8) | oprom[ 1 ]; + offs_t res; - res = disassemble_table(opcode , pc , dis_table , false , buffer); + res = disassemble_table(opcode , pc , dis_table , false , buffer); - if (res == 0) { - // Unknown opcode - strcpy(buffer , "???"); - res = 1 | DASMFLAG_SUPPORTED; - } + if (res == 0) { + // Unknown opcode + strcpy(buffer , "???"); + res = 1 | DASMFLAG_SUPPORTED; + } - return res; + return res; } CPU_DISASSEMBLE(hp_5061_3001) { - UINT16 opcode = ((UINT16)oprom[ 0 ] << 8) | oprom[ 1 ]; - offs_t res; + UINT16 opcode = ((UINT16)oprom[ 0 ] << 8) | oprom[ 1 ]; + offs_t res; - res = disassemble_table(opcode , pc , dis_table_emc , true , buffer); + res = disassemble_table(opcode , pc , dis_table_emc , true , buffer); - if (res == 0) { - res = disassemble_table(opcode , pc , dis_table , true , buffer); - } + if (res == 0) { + res = disassemble_table(opcode , pc , dis_table , true , buffer); + } - if (res == 0) { - // Unknown opcode - strcpy(buffer , "???"); - res = 1 | DASMFLAG_SUPPORTED; - } + if (res == 0) { + // Unknown opcode + strcpy(buffer , "???"); + res = 1 | DASMFLAG_SUPPORTED; + } - return res; + return res; } - diff --git a/src/devices/cpu/m68000/m68kfpu.inc b/src/devices/cpu/m68000/m68kfpu.inc index 133bb898e84..b5275bd314a 100644 --- a/src/devices/cpu/m68000/m68kfpu.inc +++ b/src/devices/cpu/m68000/m68kfpu.inc @@ -1681,7 +1681,7 @@ static void fmove_fpcr(m68000_base_device *m68k, UINT16 w2) int rnd = (REG_FPCR(m68k) >> 4) & 3; int prec = (REG_FPCR(m68k) >> 6) & 3; -// m68k->logerror("m68k_fpsp:fmove_fpcr fpcr=%04x prec=%d rnd=%d\n", REG_FPCR(m68k), prec, rnd); +// m68k->logerror("m68k_fpsp:fmove_fpcr fpcr=%04x prec=%d rnd=%d\n", REG_FPCR(m68k), prec, rnd); #ifdef FLOATX80 switch (prec) diff --git a/src/devices/cpu/m6805/m6805.h b/src/devices/cpu/m6805/m6805.h index a56443f1880..063fe0f4689 100644 --- a/src/devices/cpu/m6805/m6805.h +++ b/src/devices/cpu/m6805/m6805.h @@ -119,7 +119,7 @@ protected: void rorx(); void asrx(); void aslx(); -// void lslx(); +// void lslx(); void rolx(); void decx(); void incx(); diff --git a/src/devices/cpu/patinhofeio/patinho_feio.cpp b/src/devices/cpu/patinhofeio/patinho_feio.cpp index 9377ad259f8..78fc92a8270 100644 --- a/src/devices/cpu/patinhofeio/patinho_feio.cpp +++ b/src/devices/cpu/patinhofeio/patinho_feio.cpp @@ -28,14 +28,14 @@ #define INCREMENT_PC_4K (PC = (PC+1) & ADDRESS_MASK_4K) unsigned int patinho_feio_cpu_device::compute_effective_address(unsigned int addr){ - unsigned int retval = addr; - if (m_indirect_addressing){ - retval = READ_WORD_PATINHO(addr); - if (retval & 0x1000) - return compute_effective_address(retval & 0xFFF); - } - - return retval; + unsigned int retval = addr; + if (m_indirect_addressing){ + retval = READ_WORD_PATINHO(addr); + if (retval & 0x1000) + return compute_effective_address(retval & 0xFFF); + } + + return retval; } const device_type PATINHO_FEIO = &device_creator<patinho_feio_cpu_device>; @@ -43,494 +43,493 @@ const device_type PATINHO_FEIO = &device_creator<patinho_feio_cpu_device>; //Internal 4kbytes of RAM static ADDRESS_MAP_START(prog_8bit, AS_PROGRAM, 8, patinho_feio_cpu_device) - AM_RANGE(0x0000, 0x0fff) AM_RAM AM_SHARE("internalram") + AM_RANGE(0x0000, 0x0fff) AM_RAM AM_SHARE("internalram") ADDRESS_MAP_END patinho_feio_cpu_device::patinho_feio_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : cpu_device(mconfig, PATINHO_FEIO, "PATINHO FEIO", tag, owner, clock, "patinho_feio_cpu", __FILE__), - m_program_config("program", ENDIANNESS_LITTLE, 8, 12, 0, ADDRESS_MAP_NAME(prog_8bit)), - m_icount(0), - m_rc_read_cb(*this) + : cpu_device(mconfig, PATINHO_FEIO, "PATINHO FEIO", tag, owner, clock, "patinho_feio_cpu", __FILE__), + m_program_config("program", ENDIANNESS_LITTLE, 8, 12, 0, ADDRESS_MAP_NAME(prog_8bit)), + m_icount(0), + m_rc_read_cb(*this) { } UINT16 patinho_feio_cpu_device::read_panel_keys_register(){ - if (!m_rc_read_cb.isnull()) - m_rc = m_rc_read_cb(0); - else - m_rc = 0; + if (!m_rc_read_cb.isnull()) + m_rc = m_rc_read_cb(0); + else + m_rc = 0; - return m_rc; + return m_rc; } void patinho_feio_cpu_device::device_start() { - m_program = &space(AS_PROGRAM); - - save_item(NAME(m_pc)); - save_item(NAME(m_acc)); - save_item(NAME(m_rc)); - save_item(NAME(m_idx)); - save_item(NAME(m_flags)); - - // Register state for debugger - state_add( PATINHO_FEIO_CI, "CI", m_pc ).mask(0xFFF); - state_add( PATINHO_FEIO_RC, "RC", m_rc ).mask(0xFFF); - state_add( PATINHO_FEIO_ACC, "ACC", m_acc ).mask(0xFF); - state_add( PATINHO_FEIO_IDX, "IDX", m_idx ).mask(0xFF); - state_add(STATE_GENPC, "GENPC", m_pc).formatstr("0%06O").noshow(); - state_add(STATE_GENFLAGS, "GENFLAGS", m_flags).noshow().formatstr("%8s"); - - if (m_rc_read_cb.isnull()){ - fatalerror("Panel keys register not found!"); - } else { - m_rc_read_cb.resolve(); - } - - m_icountptr = &m_icount; + m_program = &space(AS_PROGRAM); + + save_item(NAME(m_pc)); + save_item(NAME(m_acc)); + save_item(NAME(m_rc)); + save_item(NAME(m_idx)); + save_item(NAME(m_flags)); + + // Register state for debugger + state_add( PATINHO_FEIO_CI, "CI", m_pc ).mask(0xFFF); + state_add( PATINHO_FEIO_RC, "RC", m_rc ).mask(0xFFF); + state_add( PATINHO_FEIO_ACC, "ACC", m_acc ).mask(0xFF); + state_add( PATINHO_FEIO_IDX, "IDX", m_idx ).mask(0xFF); + state_add(STATE_GENPC, "GENPC", m_pc).formatstr("0%06O").noshow(); + state_add(STATE_GENFLAGS, "GENFLAGS", m_flags).noshow().formatstr("%8s"); + + if (m_rc_read_cb.isnull()){ + fatalerror("Panel keys register not found!"); + } else { + m_rc_read_cb.resolve(); + } + + m_icountptr = &m_icount; } void patinho_feio_cpu_device::device_reset() { - m_pc = 0x006; - m_acc = 0; - m_rc = 0; - m_idx = READ_INDEX_REG(); - m_flags = 0; - m_run = true; - m_scheduled_IND_bit_reset = false; - m_indirect_addressing = false; + m_pc = 0x006; + m_acc = 0; + m_rc = 0; + m_idx = READ_INDEX_REG(); + m_flags = 0; + m_run = true; + m_scheduled_IND_bit_reset = false; + m_indirect_addressing = false; } /* execute instructions on this CPU until icount expires */ void patinho_feio_cpu_device::execute_run() { - do - { - if ((! m_run)){ - m_icount = 0; /* if processor is stopped, just burn cycles */ - } else { - m_idx = READ_INDEX_REG(); - read_panel_keys_register(); - - execute_instruction(); - m_icount --; - } - } - while (m_icount > 0); + do + { + if ((! m_run)){ + m_icount = 0; /* if processor is stopped, just burn cycles */ + } else { + m_idx = READ_INDEX_REG(); + read_panel_keys_register(); + + execute_instruction(); + m_icount --; + } + } + while (m_icount > 0); } /* execute one instruction */ void patinho_feio_cpu_device::execute_instruction() { - debugger_instruction_hook(this, PC); - offs_t addr; - bool skip; - unsigned int tmp; - unsigned char value, channel, function; - unsigned char opcode = READ_BYTE_PATINHO(PC); - INCREMENT_PC_4K; - - if (m_scheduled_IND_bit_reset) - m_indirect_addressing = false; - - if (m_indirect_addressing) - m_scheduled_IND_bit_reset = true; - - switch (opcode){ - case 0xD2: - //XOR: Computes the bitwise XOR of an immediate into the accumulator - ACC ^= READ_BYTE_PATINHO(PC); - INCREMENT_PC_4K; - //TODO: update T and V flags - return; - case 0xD4: - //NAND: Computes the bitwise XOR of an immediate into the accumulator - ACC = ~(ACC & READ_BYTE_PATINHO(PC)); - INCREMENT_PC_4K; - //TODO: update T and V flags - return; - case 0xD8: - //SOMI="Soma Imediato": - // Add an immediate into the accumulator - ACC += READ_BYTE_PATINHO(PC); - INCREMENT_PC_4K; - //TODO: update T and V flags - return; - case 0xDA: - //CARI="Carrega Imediato": - // Load an immediate into the accumulator - ACC = READ_BYTE_PATINHO(PC); - INCREMENT_PC_4K; - return; - case 0x80: - //LIMPO: - // Clear accumulator and flags - ACC = 0; - FLAGS = 0; - return; - case 0x81: - //UM="One": - // Load 1 into accumulator - // and clear the flags - ACC = 1; - FLAGS = 0; - return; - case 0x82: - //CMP1: - // Compute One's complement of the accumulator - // and clear the flags - ACC = ~ACC; - FLAGS = 0; - return; - case 0x83: - //CMP2: - // Compute Two's complement of the accumulator - // and updates flags according to the result of the operation - ACC = ~ACC + 1; - FLAGS = 0; //TODO: fix-me (I'm not sure yet how to compute the flags here) - return; - case 0x84: - //LIM="Limpa": - // Clear flags - FLAGS = 0; - return; - case 0x85: - //INC: - // Increment accumulator - ACC++; - FLAGS = 0; //TODO: fix-me (I'm not sure yet how to compute the flags here) - return; - case 0x86: - //UNEG="Um Negativo": - // Load -1 into accumulator and clear flags - ACC = -1; - FLAGS = 0; - return; - case 0x87: - //LIMP1: - // Clear accumulator, reset T and set V - ACC = 0; - FLAGS = V; - return; - case 0x88: - //PNL 0: - ACC = (RC & 0xFF); - FLAGS = 0; - return; - case 0x89: - //PNL 1: - ACC = (RC & 0xFF) + 1; - //TODO: FLAGS = ?; - return; - case 0x8A: - //PNL 2: - ACC = (RC & 0xFF) - ACC - 1; - //TODO: FLAGS = ?; - return; - case 0x8B: - //PNL 3: - ACC = (RC & 0xFF) - ACC; - //TODO: FLAGS = ?; - return; - case 0x8C: - //PNL 4: - ACC = (RC & 0xFF) + ACC; - //TODO: FLAGS = ?; - return; - case 0x8D: - //PNL 5: - ACC = (RC & 0xFF) + ACC + 1; - //TODO: FLAGS = ?; - return; - case 0x8E: - //PNL 6: - ACC = (RC & 0xFF) - 1; - //TODO: FLAGS = ?; - return; - case 0x8F: - //PNL 7: - ACC = (RC & 0xFF); - FLAGS = V; - return; - case 0x9A: - //INIB="Inibe" - // disables interrupts - m_interrupts_enabled = false; - return; - case 0x9B: - //PERM="Permite" - // enables interrupts - m_interrupts_enabled = true; - return; - case 0x9C: - //ESP="Espera": - // Holds execution and waits for an interrupt to occur. - m_run = false; - m_wait_for_interrupt = true; - return; - case 0x9D: - //PARE="Pare": - // Holds execution. This can only be recovered by - // manually triggering execution again by - // pressing the "Partida" (start) button in the panel - m_run = false; - m_wait_for_interrupt = false; - return; - case 0x9E: - //TRI="Troca com Indexador": - // Exchange the value of the accumulator with the index register - value = ACC; - ACC = READ_INDEX_REG(); - WRITE_INDEX_REG(value); - return; - case 0x9F: - //IND="Enderecamento indireto": - // Sets memory addressing for the next instruction to be indirect. - m_indirect_addressing = true; - m_scheduled_IND_bit_reset = false; //the next instruction execution will schedule it. - return; - case 0xD1: - //Bit-Shift/Bit-Rotate instructions - value = READ_BYTE_PATINHO(PC); - INCREMENT_PC_4K; - for (int i=0; i<4; i++){ - if (value & (1<<i)){ - /* The number of shifts or rotations is determined by the - ammount of 1 bits in the lower 4 bits of 'value' */ - switch(value & 0xF0) - { - case 0x00: - //DD="Deslocamento para a Direita" - // Shift right - FLAGS &= ~V; - if (ACC & 1) - FLAGS |= V; - - ACC >>= 1; - break; - case 0x20: - //GD="Giro para a Direita" - // Rotate right - FLAGS &= ~V; - if (ACC & 1) - FLAGS |= V; - - ACC = ((ACC & 1) << 7) | (ACC >> 1); - break; - case 0x10: //DDV="Deslocamento para a Direita com Vai-um" - // Shift right with Carry - case 0x30: //GDV="Giro para a Direita com Vai-um" - // Rotate right with Carry - - //both instructions are equivalent - if (FLAGS & V) - tmp = 0x100 | ACC; - else - tmp = ACC; - - FLAGS &= ~V; - if (ACC & 1) - FLAGS |= V; - - ACC = tmp >> 1; - break; - case 0x40: //DE="Deslocamento para a Esquerda" - // Shift left - FLAGS &= ~V; - if (ACC & (1<<7)) - FLAGS |= V; - - ACC <<= 1; - break; - case 0x60: //GE="Giro para a Esquerda" - // Rotate left - FLAGS &= ~V; - if (ACC & (1<<7)) - FLAGS |= V; - - ACC = (ACC << 1) | ((ACC >> 7) & 1); - break; - case 0x50: //DEV="Deslocamento para a Esquerda com Vai-um" - // Shift left with Carry - case 0x70: //GEV="Giro para a Esquerda com Vai-um" - // Rotate left with Carry - - //both instructions are equivalent - if (FLAGS & V) - tmp = (ACC << 1) | 1; - else - tmp = (ACC << 1); - - FLAGS &= ~V; - if (tmp & (1<<8)) - FLAGS |= V; - - ACC = tmp & 0xFF; - break; - case 0x80: //DDS="Deslocamento para a Direita com duplicacao de Sinal" - // Rotate right with signal duplication - FLAGS &= ~V; - if (ACC & 1) - FLAGS |= V; - - ACC = (ACC & (1 << 7)) | ACC >> 1; - break; - default: - printf("Illegal instruction: %02X %02X\n", opcode, value); - return; - } - } - } - return; - } - - switch (opcode & 0xF0){ - case 0x00: - //PLA = "Pula": Jump to address - addr = compute_effective_address((opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC)); - INCREMENT_PC_4K; - PC = addr; - return; - case 0x10: - //PLAX = "Pula indexado": Jump to indexed address - tmp = (opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC); - INCREMENT_PC_4K; - m_idx = READ_INDEX_REG(); - PC = compute_effective_address(m_idx + tmp); - return; - case 0x20: - //ARM = "Armazena": Store the value of the accumulator into a given memory position - addr = compute_effective_address((opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC)); - INCREMENT_PC_4K; - WRITE_BYTE_PATINHO(addr, ACC); - return; - case 0x30: - //ARMX = "Armazena indexado": Store the value of the accumulator into a given indexed memory position - tmp = (opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC); - INCREMENT_PC_4K; - m_idx = READ_INDEX_REG(); - addr = compute_effective_address(m_idx + tmp); - WRITE_BYTE_PATINHO(addr, ACC); - return; - case 0x40: - //CAR = "Carrega": Load a value from a given memory position into the accumulator - addr = compute_effective_address((opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC)); - INCREMENT_PC_4K; - ACC = READ_BYTE_PATINHO(addr); - return; - case 0x50: - //CARX = "Carga indexada": Load a value from a given indexed memory position into the accumulator - tmp = (opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC); - INCREMENT_PC_4K; - m_idx = READ_INDEX_REG(); - addr = compute_effective_address(m_idx + tmp); - ACC = READ_BYTE_PATINHO(addr); - return; - case 0x60: - //SOM = "Soma": Add a value from a given memory position into the accumulator - addr = compute_effective_address((opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC)); - INCREMENT_PC_4K; - ACC += READ_BYTE_PATINHO(addr); - //TODO: update V and T flags - return; - case 0x70: - //SOMX = "Soma indexada": Add a value from a given indexed memory position into the accumulator - tmp = (opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC); - INCREMENT_PC_4K; - m_idx = READ_INDEX_REG(); - addr = compute_effective_address(m_idx + tmp); - ACC += READ_BYTE_PATINHO(addr); - //TODO: update V and T flags - return; - case 0xA0: - //PLAN = "Pula se ACC negativo": Jump to a given address if ACC is negative - addr = compute_effective_address((opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC)); - INCREMENT_PC_4K; - if ((signed char) ACC < 0) - PC = addr; - return; - case 0xB0: - //PLAZ = "Pula se ACC for zero": Jump to a given address if ACC is zero - addr = compute_effective_address((opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC)); - INCREMENT_PC_4K; - if (ACC == 0) - PC = addr; - return; - case 0xC0: - //Executes I/O functions - //TODO: Implement-me! - value = READ_BYTE_PATINHO(PC); - INCREMENT_PC_4K; - channel = opcode & 0x0F; - function = value & 0x0F; - switch(value & 0xF0){ - case 0x10: - printf("Unimplemented FNC /%X%X instruction\n", channel, function); - break; - case 0x20: - //SAL="Salta" - // Skips a couple bytes if a condition is met - skip = false; - switch(function) - { - case 1: - if (m_peripherals[channel].io_status == DEVICE_READY) - skip = true; - break; - case 2: - if (m_peripherals[channel].device_is_ok) - skip = true; - break; - case 4: - if (m_peripherals[channel].IRQ_request == true) - skip = true; - break; - } - - if (skip){ - INCREMENT_PC_4K; - INCREMENT_PC_4K; - } - break; - case 0x40: - printf("Unimplemented ENTR /%X0 instruction\n", channel); - break; - case 0x80: - printf("Unimplemented SAI /%X0 instruction (ACC = 0x%02X '%c')\n", channel, ACC, ACC); - break; - } - return; - case 0xE0: - //SUS = "Subtrai um ou Salta": Subtract one from the data in the given address - // or, if the data is zero, then simply skip a couple bytes. - addr = compute_effective_address((opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC)); - INCREMENT_PC_4K; - value = READ_BYTE_PATINHO(addr); - if (value > 0){ - WRITE_BYTE_PATINHO(addr, value-1); - } else { - INCREMENT_PC_4K; - INCREMENT_PC_4K; - } - return; - case 0xF0: - //PUG = "Pula e guarda": Jump and store. - // It stores the return address to addr and addr+1 - // And then jumps to addr+2 - addr = compute_effective_address((opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC)); - INCREMENT_PC_4K; - WRITE_BYTE_PATINHO(addr, (PC >> 8) & 0x0F); - WRITE_BYTE_PATINHO(addr+1, PC & 0xFF); - PC = addr+2; - return; - } - printf("unimplemented opcode: 0x%02X\n", opcode); + debugger_instruction_hook(this, PC); + offs_t addr; + bool skip; + unsigned int tmp; + unsigned char value, channel, function; + unsigned char opcode = READ_BYTE_PATINHO(PC); + INCREMENT_PC_4K; + + if (m_scheduled_IND_bit_reset) + m_indirect_addressing = false; + + if (m_indirect_addressing) + m_scheduled_IND_bit_reset = true; + + switch (opcode){ + case 0xD2: + //XOR: Computes the bitwise XOR of an immediate into the accumulator + ACC ^= READ_BYTE_PATINHO(PC); + INCREMENT_PC_4K; + //TODO: update T and V flags + return; + case 0xD4: + //NAND: Computes the bitwise XOR of an immediate into the accumulator + ACC = ~(ACC & READ_BYTE_PATINHO(PC)); + INCREMENT_PC_4K; + //TODO: update T and V flags + return; + case 0xD8: + //SOMI="Soma Imediato": + // Add an immediate into the accumulator + ACC += READ_BYTE_PATINHO(PC); + INCREMENT_PC_4K; + //TODO: update T and V flags + return; + case 0xDA: + //CARI="Carrega Imediato": + // Load an immediate into the accumulator + ACC = READ_BYTE_PATINHO(PC); + INCREMENT_PC_4K; + return; + case 0x80: + //LIMPO: + // Clear accumulator and flags + ACC = 0; + FLAGS = 0; + return; + case 0x81: + //UM="One": + // Load 1 into accumulator + // and clear the flags + ACC = 1; + FLAGS = 0; + return; + case 0x82: + //CMP1: + // Compute One's complement of the accumulator + // and clear the flags + ACC = ~ACC; + FLAGS = 0; + return; + case 0x83: + //CMP2: + // Compute Two's complement of the accumulator + // and updates flags according to the result of the operation + ACC = ~ACC + 1; + FLAGS = 0; //TODO: fix-me (I'm not sure yet how to compute the flags here) + return; + case 0x84: + //LIM="Limpa": + // Clear flags + FLAGS = 0; + return; + case 0x85: + //INC: + // Increment accumulator + ACC++; + FLAGS = 0; //TODO: fix-me (I'm not sure yet how to compute the flags here) + return; + case 0x86: + //UNEG="Um Negativo": + // Load -1 into accumulator and clear flags + ACC = -1; + FLAGS = 0; + return; + case 0x87: + //LIMP1: + // Clear accumulator, reset T and set V + ACC = 0; + FLAGS = V; + return; + case 0x88: + //PNL 0: + ACC = (RC & 0xFF); + FLAGS = 0; + return; + case 0x89: + //PNL 1: + ACC = (RC & 0xFF) + 1; + //TODO: FLAGS = ?; + return; + case 0x8A: + //PNL 2: + ACC = (RC & 0xFF) - ACC - 1; + //TODO: FLAGS = ?; + return; + case 0x8B: + //PNL 3: + ACC = (RC & 0xFF) - ACC; + //TODO: FLAGS = ?; + return; + case 0x8C: + //PNL 4: + ACC = (RC & 0xFF) + ACC; + //TODO: FLAGS = ?; + return; + case 0x8D: + //PNL 5: + ACC = (RC & 0xFF) + ACC + 1; + //TODO: FLAGS = ?; + return; + case 0x8E: + //PNL 6: + ACC = (RC & 0xFF) - 1; + //TODO: FLAGS = ?; + return; + case 0x8F: + //PNL 7: + ACC = (RC & 0xFF); + FLAGS = V; + return; + case 0x9A: + //INIB="Inibe" + // disables interrupts + m_interrupts_enabled = false; + return; + case 0x9B: + //PERM="Permite" + // enables interrupts + m_interrupts_enabled = true; + return; + case 0x9C: + //ESP="Espera": + // Holds execution and waits for an interrupt to occur. + m_run = false; + m_wait_for_interrupt = true; + return; + case 0x9D: + //PARE="Pare": + // Holds execution. This can only be recovered by + // manually triggering execution again by + // pressing the "Partida" (start) button in the panel + m_run = false; + m_wait_for_interrupt = false; + return; + case 0x9E: + //TRI="Troca com Indexador": + // Exchange the value of the accumulator with the index register + value = ACC; + ACC = READ_INDEX_REG(); + WRITE_INDEX_REG(value); + return; + case 0x9F: + //IND="Enderecamento indireto": + // Sets memory addressing for the next instruction to be indirect. + m_indirect_addressing = true; + m_scheduled_IND_bit_reset = false; //the next instruction execution will schedule it. + return; + case 0xD1: + //Bit-Shift/Bit-Rotate instructions + value = READ_BYTE_PATINHO(PC); + INCREMENT_PC_4K; + for (int i=0; i<4; i++){ + if (value & (1<<i)){ + /* The number of shifts or rotations is determined by the + ammount of 1 bits in the lower 4 bits of 'value' */ + switch(value & 0xF0) + { + case 0x00: + //DD="Deslocamento para a Direita" + // Shift right + FLAGS &= ~V; + if (ACC & 1) + FLAGS |= V; + + ACC >>= 1; + break; + case 0x20: + //GD="Giro para a Direita" + // Rotate right + FLAGS &= ~V; + if (ACC & 1) + FLAGS |= V; + + ACC = ((ACC & 1) << 7) | (ACC >> 1); + break; + case 0x10: //DDV="Deslocamento para a Direita com Vai-um" + // Shift right with Carry + case 0x30: //GDV="Giro para a Direita com Vai-um" + // Rotate right with Carry + + //both instructions are equivalent + if (FLAGS & V) + tmp = 0x100 | ACC; + else + tmp = ACC; + + FLAGS &= ~V; + if (ACC & 1) + FLAGS |= V; + + ACC = tmp >> 1; + break; + case 0x40: //DE="Deslocamento para a Esquerda" + // Shift left + FLAGS &= ~V; + if (ACC & (1<<7)) + FLAGS |= V; + + ACC <<= 1; + break; + case 0x60: //GE="Giro para a Esquerda" + // Rotate left + FLAGS &= ~V; + if (ACC & (1<<7)) + FLAGS |= V; + + ACC = (ACC << 1) | ((ACC >> 7) & 1); + break; + case 0x50: //DEV="Deslocamento para a Esquerda com Vai-um" + // Shift left with Carry + case 0x70: //GEV="Giro para a Esquerda com Vai-um" + // Rotate left with Carry + + //both instructions are equivalent + if (FLAGS & V) + tmp = (ACC << 1) | 1; + else + tmp = (ACC << 1); + + FLAGS &= ~V; + if (tmp & (1<<8)) + FLAGS |= V; + + ACC = tmp & 0xFF; + break; + case 0x80: //DDS="Deslocamento para a Direita com duplicacao de Sinal" + // Rotate right with signal duplication + FLAGS &= ~V; + if (ACC & 1) + FLAGS |= V; + + ACC = (ACC & (1 << 7)) | ACC >> 1; + break; + default: + printf("Illegal instruction: %02X %02X\n", opcode, value); + return; + } + } + } + return; + } + + switch (opcode & 0xF0){ + case 0x00: + //PLA = "Pula": Jump to address + addr = compute_effective_address((opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC)); + INCREMENT_PC_4K; + PC = addr; + return; + case 0x10: + //PLAX = "Pula indexado": Jump to indexed address + tmp = (opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC); + INCREMENT_PC_4K; + m_idx = READ_INDEX_REG(); + PC = compute_effective_address(m_idx + tmp); + return; + case 0x20: + //ARM = "Armazena": Store the value of the accumulator into a given memory position + addr = compute_effective_address((opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC)); + INCREMENT_PC_4K; + WRITE_BYTE_PATINHO(addr, ACC); + return; + case 0x30: + //ARMX = "Armazena indexado": Store the value of the accumulator into a given indexed memory position + tmp = (opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC); + INCREMENT_PC_4K; + m_idx = READ_INDEX_REG(); + addr = compute_effective_address(m_idx + tmp); + WRITE_BYTE_PATINHO(addr, ACC); + return; + case 0x40: + //CAR = "Carrega": Load a value from a given memory position into the accumulator + addr = compute_effective_address((opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC)); + INCREMENT_PC_4K; + ACC = READ_BYTE_PATINHO(addr); + return; + case 0x50: + //CARX = "Carga indexada": Load a value from a given indexed memory position into the accumulator + tmp = (opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC); + INCREMENT_PC_4K; + m_idx = READ_INDEX_REG(); + addr = compute_effective_address(m_idx + tmp); + ACC = READ_BYTE_PATINHO(addr); + return; + case 0x60: + //SOM = "Soma": Add a value from a given memory position into the accumulator + addr = compute_effective_address((opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC)); + INCREMENT_PC_4K; + ACC += READ_BYTE_PATINHO(addr); + //TODO: update V and T flags + return; + case 0x70: + //SOMX = "Soma indexada": Add a value from a given indexed memory position into the accumulator + tmp = (opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC); + INCREMENT_PC_4K; + m_idx = READ_INDEX_REG(); + addr = compute_effective_address(m_idx + tmp); + ACC += READ_BYTE_PATINHO(addr); + //TODO: update V and T flags + return; + case 0xA0: + //PLAN = "Pula se ACC negativo": Jump to a given address if ACC is negative + addr = compute_effective_address((opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC)); + INCREMENT_PC_4K; + if ((signed char) ACC < 0) + PC = addr; + return; + case 0xB0: + //PLAZ = "Pula se ACC for zero": Jump to a given address if ACC is zero + addr = compute_effective_address((opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC)); + INCREMENT_PC_4K; + if (ACC == 0) + PC = addr; + return; + case 0xC0: + //Executes I/O functions + //TODO: Implement-me! + value = READ_BYTE_PATINHO(PC); + INCREMENT_PC_4K; + channel = opcode & 0x0F; + function = value & 0x0F; + switch(value & 0xF0){ + case 0x10: + printf("Unimplemented FNC /%X%X instruction\n", channel, function); + break; + case 0x20: + //SAL="Salta" + // Skips a couple bytes if a condition is met + skip = false; + switch(function) + { + case 1: + if (m_peripherals[channel].io_status == DEVICE_READY) + skip = true; + break; + case 2: + if (m_peripherals[channel].device_is_ok) + skip = true; + break; + case 4: + if (m_peripherals[channel].IRQ_request == true) + skip = true; + break; + } + + if (skip){ + INCREMENT_PC_4K; + INCREMENT_PC_4K; + } + break; + case 0x40: + printf("Unimplemented ENTR /%X0 instruction\n", channel); + break; + case 0x80: + printf("Unimplemented SAI /%X0 instruction (ACC = 0x%02X '%c')\n", channel, ACC, ACC); + break; + } + return; + case 0xE0: + //SUS = "Subtrai um ou Salta": Subtract one from the data in the given address + // or, if the data is zero, then simply skip a couple bytes. + addr = compute_effective_address((opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC)); + INCREMENT_PC_4K; + value = READ_BYTE_PATINHO(addr); + if (value > 0){ + WRITE_BYTE_PATINHO(addr, value-1); + } else { + INCREMENT_PC_4K; + INCREMENT_PC_4K; + } + return; + case 0xF0: + //PUG = "Pula e guarda": Jump and store. + // It stores the return address to addr and addr+1 + // And then jumps to addr+2 + addr = compute_effective_address((opcode & 0x0F) << 8 | READ_BYTE_PATINHO(PC)); + INCREMENT_PC_4K; + WRITE_BYTE_PATINHO(addr, (PC >> 8) & 0x0F); + WRITE_BYTE_PATINHO(addr+1, PC & 0xFF); + PC = addr+2; + return; + } + printf("unimplemented opcode: 0x%02X\n", opcode); } offs_t patinho_feio_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { - extern CPU_DISASSEMBLE( patinho_feio ); - return CPU_DISASSEMBLE_NAME(patinho_feio)(this, buffer, pc, oprom, opram, options); + extern CPU_DISASSEMBLE( patinho_feio ); + return CPU_DISASSEMBLE_NAME(patinho_feio)(this, buffer, pc, oprom, opram, options); } - diff --git a/src/devices/cpu/patinhofeio/patinho_feio.h b/src/devices/cpu/patinhofeio/patinho_feio.h index 030077ea78e..df80799d592 100644 --- a/src/devices/cpu/patinhofeio/patinho_feio.h +++ b/src/devices/cpu/patinhofeio/patinho_feio.h @@ -6,99 +6,99 @@ #define __PATINHOFEIO_H__ #define MCFG_PATINHO_RC_READ_CB(_devcb) \ - devcb = &patinho_feio_cpu_device::set_rc_read_callback(*device, DEVCB_##_devcb); + devcb = &patinho_feio_cpu_device::set_rc_read_callback(*device, DEVCB_##_devcb); /* register IDs */ enum { - PATINHO_FEIO_CI=1, PATINHO_FEIO_ACC, PATINHO_FEIO_IDX, PATINHO_FEIO_RC + PATINHO_FEIO_CI=1, PATINHO_FEIO_ACC, PATINHO_FEIO_IDX, PATINHO_FEIO_RC }; enum { - DEVICE_BUSY=0, - DEVICE_READY=1 + DEVICE_BUSY=0, + DEVICE_READY=1 }; class patinho_feio_peripheral { public: - patinho_feio_peripheral() - : io_status(DEVICE_READY) - , device_is_ok(true) - , IRQ_request(false) - { }; - - int io_status; - bool device_is_ok; - bool IRQ_request; + patinho_feio_peripheral() + : io_status(DEVICE_READY) + , device_is_ok(true) + , IRQ_request(false) + { }; + + int io_status; + bool device_is_ok; + bool IRQ_request; }; class patinho_feio_cpu_device : public cpu_device { public: - // construction/destruction - patinho_feio_cpu_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock); + // construction/destruction + patinho_feio_cpu_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock); - template<class _Object> static devcb_base &set_rc_read_callback(device_t &device, _Object object) { return downcast<patinho_feio_cpu_device &>(device).m_rc_read_cb.set_callback(object); } + template<class _Object> static devcb_base &set_rc_read_callback(device_t &device, _Object object) { return downcast<patinho_feio_cpu_device &>(device).m_rc_read_cb.set_callback(object); } protected: - - virtual void execute_run() override; - virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) override; - address_space_config m_program_config; + virtual void execute_run() override; + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) override; - /* processor registers */ - unsigned char m_acc; /* accumulator (8 bits) */ - unsigned int m_pc; /* program counter (12 bits) + address_space_config m_program_config; + + /* processor registers */ + unsigned char m_acc; /* accumulator (8 bits) */ + unsigned int m_pc; /* program counter (12 bits) * Actual register name is CI, which * stands for "Contador de Instrucao" * or "instructions counter". */ - unsigned int m_rc; /* RC = "Registrador de Chaves" (Keys Register) + unsigned int m_rc; /* RC = "Registrador de Chaves" (Keys Register) * It represents the 12 bits of input data * from toggle switches in the computer panel */ - unsigned char m_idx; + unsigned char m_idx; + + /* processor state flip-flops */ + bool m_run; /* processor is running */ + bool m_wait_for_interrupt; + bool m_interrupts_enabled; + bool m_scheduled_IND_bit_reset; + bool m_indirect_addressing; - /* processor state flip-flops */ - bool m_run; /* processor is running */ - bool m_wait_for_interrupt; - bool m_interrupts_enabled; - bool m_scheduled_IND_bit_reset; - bool m_indirect_addressing; + int m_flags; + // V = "Vai um" (Carry flag) + // T = "Transbordo" (Overflow flag) - int m_flags; - // V = "Vai um" (Carry flag) - // T = "Transbordo" (Overflow flag) - - patinho_feio_peripheral m_peripherals[16]; + patinho_feio_peripheral m_peripherals[16]; - int m_address_mask; /* address mask */ - int m_icount; + int m_address_mask; /* address mask */ + int m_icount; - address_space *m_program; + address_space *m_program; - // device-level overrides - virtual void device_start() override; - virtual void device_reset() override; + // device-level overrides + virtual void device_start() override; + virtual void device_reset() override; - // device_execute_interface overrides - virtual UINT32 execute_min_cycles() const override { return 1; } - virtual UINT32 execute_max_cycles() const override { return 2; } + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const override { return 1; } + virtual UINT32 execute_max_cycles() const override { return 2; } - // device_memory_interface overrides - virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const override { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; } + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const override { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; } - // device_disasm_interface overrides - virtual UINT32 disasm_min_opcode_bytes() const override { return 1; } - virtual UINT32 disasm_max_opcode_bytes() const override { return 2; } + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const override { return 1; } + virtual UINT32 disasm_max_opcode_bytes() const override { return 2; } private: - void execute_instruction(); - unsigned int compute_effective_address(unsigned int addr); - UINT16 read_panel_keys_register(); - devcb_read16 m_rc_read_cb; + void execute_instruction(); + unsigned int compute_effective_address(unsigned int addr); + UINT16 read_panel_keys_register(); + devcb_read16 m_rc_read_cb; }; diff --git a/src/devices/cpu/patinhofeio/patinho_feio_dasm.cpp b/src/devices/cpu/patinhofeio/patinho_feio_dasm.cpp index ac78ef4be73..f2f2899af6e 100644 --- a/src/devices/cpu/patinhofeio/patinho_feio_dasm.cpp +++ b/src/devices/cpu/patinhofeio/patinho_feio_dasm.cpp @@ -5,161 +5,161 @@ CPU_DISASSEMBLE( patinho_feio ) { - int addr, value, n, f; + int addr, value, n, f; - switch (oprom[0] & 0xF0) - { - case 0x00: - //PLA = "Pula": Unconditionally JUMP to effective address - addr = (oprom[0] & 0x0F) << 8 | oprom[1]; - sprintf (buffer, "PLA /%03X", addr); - return 2; - case 0x10: - //PLAX = "Pulo indexado": Unconditionally JUMP to indexed address - addr = (oprom[0] & 0x0F) << 8 | oprom[1]; - sprintf (buffer, "PLAX (IDX) + /%03X", addr); - return 2; - case 0x20: - //ARM = "Armazena": Stores the contents of the - // accumulator in the given 12bit address - addr = (oprom[0] & 0x0F) << 8 | oprom[1]; - if (addr==0){ - sprintf (buffer, "ARM (IDX)"); - }else{ - sprintf (buffer, "ARM /%03X", addr); - } - return 2; - case 0x30: - //ARMX = "Armazenamento indexado": Stores the contents of the accumulator in the - // given 12bit address (indexed by IDX) - addr = (oprom[0] & 0x0F) << 8 | oprom[1]; - sprintf (buffer, "ARMX (IDX) + /%03X", addr); - return 2; - case 0x40: - //CAR = "Carrega": Loads the contents of the given 12bit address - // into the accumulator - addr = (oprom[0] & 0x0F) << 8 | oprom[1]; - if (addr==0){ - sprintf (buffer, "CAR (IDX)"); - }else{ - sprintf (buffer, "CAR /%03X", addr); - } - return 2; - case 0x50: - //CARX = "Carga indexada": Loads the contents of the given 12bit address - // (indexed by IDX) into the accumulator - addr = (oprom[0] & 0x0F) << 8 | oprom[1]; - sprintf (buffer, "CARX (IDX) + /%03X", addr); - return 2; - case 0x60: - //SOM = "Soma": Adds the contents of the given 12bit address - // into the accumulator - addr = (oprom[0] & 0x0F) << 8 | oprom[1]; - sprintf (buffer, "SOM /%03X", addr); - return 2; - case 0x70: - //SOMX = "Soma indexada": Adds the contents of the given 12bit address - // (indexed by IDX) into the accumulator - addr = (oprom[0] & 0x0F) << 8 | oprom[1]; - sprintf (buffer, "SOMX (IDX) + /%03X", addr); - return 2; - case 0xA0: - //PLAN = "Pula se ACC for negativo": Jumps to the 12bit address - // if the accumulator is negative - addr = (oprom[0] & 0x0F) << 8 | oprom[1]; - sprintf (buffer, "PLAN /%03X", addr); - return 2; - case 0xB0: - //PLAZ = "Pula se ACC for zero": Jumps to the 12bit address - // if the accumulator is zero - addr = (oprom[0] & 0x0F) << 8 | oprom[1]; - sprintf (buffer, "PLAZ /%03X", addr); - return 2; - case 0xC0: - n = (oprom[0] & 0x0F); - f = (oprom[1] & 0x0F); - n+= (n < 10) ? '0' : 'A'-10; - f+= (f < 10) ? '0' : 'A'-10; - switch(oprom[1] & 0xF0) - { - case 0x10: sprintf (buffer, "FNC /%c%c", n, f); return 2; - case 0x20: sprintf (buffer, "SAL /%c%c", n, f); return 2; - case 0x40: sprintf (buffer, "ENTR /%c0", n); return 2; - case 0x80: sprintf (buffer, "SAI /%c0", n); return 2; - } - break; - case 0xD0: - value = oprom[1] & 0x0F; - switch (oprom[0] & 0x0F) - { - case 0x01: - switch (oprom[1] & 0xF0) - { - case 0x00: sprintf (buffer, "DD /%01X", value); return 2; //DD = "Deslocamento para a direita": Shift right - case 0x10: sprintf (buffer, "DDV /%01X", value); return 2; //DDV = "Deslocamento para a direita c/ V": Shift right with carry - case 0x20: sprintf (buffer, "GD /%01X", value); return 2; //GD = "Giro para a direita": Rotate right - case 0x30: sprintf (buffer, "GDV /%01X", value); return 2; //GDV = "Giro para a direita c/ V": Rotate right with carry - case 0x40: sprintf (buffer, "DE /%01X", value); return 2; //DE = "Deslocamento para a esquerda": Shift right - case 0x50: sprintf (buffer, "DEV /%01X", value); return 2; //DEV = "Deslocamento para a esquerda c/ V": Shift right with carry - case 0x60: sprintf (buffer, "GE /%01X", value); return 2; //GE = "Giro para a esquerda": Rotate right - case 0x70: sprintf (buffer, "GEV /%01X", value); return 2; //GEV = "Giro para a esquerda c/ V": Rotate right with carry - case 0x80: sprintf (buffer, "DDS /%01X", value); return 2; //DDS = "Deslocamento para a direita com duplicacao de sinal": Shift right with sign duplication - } - break; - case 0x02: sprintf (buffer, "XOR /%02X", oprom[1]); return 2; //Logical XOR - case 0x04: sprintf (buffer, "NAND /%02X", oprom[1]); return 2; //Logical NAND - case 0x08: sprintf (buffer, "SOMI /%02X", oprom[1]); return 2; //SOMI = "Soma imediata": Add immediate value into accumulator - case 0x0A: sprintf (buffer, "CARI /%02X", oprom[1]); return 2; //CARI = "Carrega imediato": Loads an immediate value into the accumulator - } - break; - case 0xE0: - //SUS = "Subtrai um ou salta" - addr = (oprom[0] & 0x0F) << 8 | oprom[1]; - sprintf (buffer, "SUS /%03X", addr); - return 2; - case 0xF0: - //PUG = "Pula e guarda" - addr = (oprom[0] & 0x0F) << 8 | oprom[1]; - sprintf (buffer, "PUG /%03X", addr); - return 2; - } + switch (oprom[0] & 0xF0) + { + case 0x00: + //PLA = "Pula": Unconditionally JUMP to effective address + addr = (oprom[0] & 0x0F) << 8 | oprom[1]; + sprintf (buffer, "PLA /%03X", addr); + return 2; + case 0x10: + //PLAX = "Pulo indexado": Unconditionally JUMP to indexed address + addr = (oprom[0] & 0x0F) << 8 | oprom[1]; + sprintf (buffer, "PLAX (IDX) + /%03X", addr); + return 2; + case 0x20: + //ARM = "Armazena": Stores the contents of the + // accumulator in the given 12bit address + addr = (oprom[0] & 0x0F) << 8 | oprom[1]; + if (addr==0){ + sprintf (buffer, "ARM (IDX)"); + }else{ + sprintf (buffer, "ARM /%03X", addr); + } + return 2; + case 0x30: + //ARMX = "Armazenamento indexado": Stores the contents of the accumulator in the + // given 12bit address (indexed by IDX) + addr = (oprom[0] & 0x0F) << 8 | oprom[1]; + sprintf (buffer, "ARMX (IDX) + /%03X", addr); + return 2; + case 0x40: + //CAR = "Carrega": Loads the contents of the given 12bit address + // into the accumulator + addr = (oprom[0] & 0x0F) << 8 | oprom[1]; + if (addr==0){ + sprintf (buffer, "CAR (IDX)"); + }else{ + sprintf (buffer, "CAR /%03X", addr); + } + return 2; + case 0x50: + //CARX = "Carga indexada": Loads the contents of the given 12bit address + // (indexed by IDX) into the accumulator + addr = (oprom[0] & 0x0F) << 8 | oprom[1]; + sprintf (buffer, "CARX (IDX) + /%03X", addr); + return 2; + case 0x60: + //SOM = "Soma": Adds the contents of the given 12bit address + // into the accumulator + addr = (oprom[0] & 0x0F) << 8 | oprom[1]; + sprintf (buffer, "SOM /%03X", addr); + return 2; + case 0x70: + //SOMX = "Soma indexada": Adds the contents of the given 12bit address + // (indexed by IDX) into the accumulator + addr = (oprom[0] & 0x0F) << 8 | oprom[1]; + sprintf (buffer, "SOMX (IDX) + /%03X", addr); + return 2; + case 0xA0: + //PLAN = "Pula se ACC for negativo": Jumps to the 12bit address + // if the accumulator is negative + addr = (oprom[0] & 0x0F) << 8 | oprom[1]; + sprintf (buffer, "PLAN /%03X", addr); + return 2; + case 0xB0: + //PLAZ = "Pula se ACC for zero": Jumps to the 12bit address + // if the accumulator is zero + addr = (oprom[0] & 0x0F) << 8 | oprom[1]; + sprintf (buffer, "PLAZ /%03X", addr); + return 2; + case 0xC0: + n = (oprom[0] & 0x0F); + f = (oprom[1] & 0x0F); + n+= (n < 10) ? '0' : 'A'-10; + f+= (f < 10) ? '0' : 'A'-10; + switch(oprom[1] & 0xF0) + { + case 0x10: sprintf (buffer, "FNC /%c%c", n, f); return 2; + case 0x20: sprintf (buffer, "SAL /%c%c", n, f); return 2; + case 0x40: sprintf (buffer, "ENTR /%c0", n); return 2; + case 0x80: sprintf (buffer, "SAI /%c0", n); return 2; + } + break; + case 0xD0: + value = oprom[1] & 0x0F; + switch (oprom[0] & 0x0F) + { + case 0x01: + switch (oprom[1] & 0xF0) + { + case 0x00: sprintf (buffer, "DD /%01X", value); return 2; //DD = "Deslocamento para a direita": Shift right + case 0x10: sprintf (buffer, "DDV /%01X", value); return 2; //DDV = "Deslocamento para a direita c/ V": Shift right with carry + case 0x20: sprintf (buffer, "GD /%01X", value); return 2; //GD = "Giro para a direita": Rotate right + case 0x30: sprintf (buffer, "GDV /%01X", value); return 2; //GDV = "Giro para a direita c/ V": Rotate right with carry + case 0x40: sprintf (buffer, "DE /%01X", value); return 2; //DE = "Deslocamento para a esquerda": Shift right + case 0x50: sprintf (buffer, "DEV /%01X", value); return 2; //DEV = "Deslocamento para a esquerda c/ V": Shift right with carry + case 0x60: sprintf (buffer, "GE /%01X", value); return 2; //GE = "Giro para a esquerda": Rotate right + case 0x70: sprintf (buffer, "GEV /%01X", value); return 2; //GEV = "Giro para a esquerda c/ V": Rotate right with carry + case 0x80: sprintf (buffer, "DDS /%01X", value); return 2; //DDS = "Deslocamento para a direita com duplicacao de sinal": Shift right with sign duplication + } + break; + case 0x02: sprintf (buffer, "XOR /%02X", oprom[1]); return 2; //Logical XOR + case 0x04: sprintf (buffer, "NAND /%02X", oprom[1]); return 2; //Logical NAND + case 0x08: sprintf (buffer, "SOMI /%02X", oprom[1]); return 2; //SOMI = "Soma imediata": Add immediate value into accumulator + case 0x0A: sprintf (buffer, "CARI /%02X", oprom[1]); return 2; //CARI = "Carrega imediato": Loads an immediate value into the accumulator + } + break; + case 0xE0: + //SUS = "Subtrai um ou salta" + addr = (oprom[0] & 0x0F) << 8 | oprom[1]; + sprintf (buffer, "SUS /%03X", addr); + return 2; + case 0xF0: + //PUG = "Pula e guarda" + addr = (oprom[0] & 0x0F) << 8 | oprom[1]; + sprintf (buffer, "PUG /%03X", addr); + return 2; + } - switch (oprom[0]) - { - case 0x80: sprintf (buffer, "LIMPO"); return 1; - case 0x81: sprintf (buffer, "UM"); return 1; - case 0x82: sprintf (buffer, "CMP1"); return 1; - case 0x83: sprintf (buffer, "CMP2"); return 1; - case 0x84: sprintf (buffer, "LIN"); return 1; - case 0x85: sprintf (buffer, "INC"); return 1; - case 0x86: sprintf (buffer, "UNEG"); return 1; - case 0x87: sprintf (buffer, "LIMP1"); return 1; - case 0x88: sprintf (buffer, "PNL 0"); return 1; - case 0x89: sprintf (buffer, "PNL 1"); return 1; - case 0x8A: sprintf (buffer, "PNL 2"); return 1; - case 0x8B: sprintf (buffer, "PNL 3"); return 1; - case 0x8C: sprintf (buffer, "PNL 4"); return 1; - case 0x8D: sprintf (buffer, "PNL 5"); return 1; - case 0x8E: sprintf (buffer, "PNL 6"); return 1; - case 0x8F: sprintf (buffer, "PNL 7"); return 1; - case 0x90: sprintf (buffer, "ST 0"); return 1; - case 0x91: sprintf (buffer, "STM 0"); return 1; - case 0x92: sprintf (buffer, "ST 1"); return 1; - case 0x93: sprintf (buffer, "STM 1"); return 1; - case 0x94: sprintf (buffer, "SV 0"); return 1; - case 0x95: sprintf (buffer, "SVM 0"); return 1; - case 0x96: sprintf (buffer, "SV 1"); return 1; - case 0x97: sprintf (buffer, "SVM 1"); return 1; - case 0x98: sprintf (buffer, "PUL"); return 1; - case 0x99: sprintf (buffer, "TRE"); return 1; - case 0x9A: sprintf (buffer, "INIB"); return 1; - case 0x9B: sprintf (buffer, "PERM"); return 1; - case 0x9C: sprintf (buffer, "ESP"); return 1; - case 0x9D: sprintf (buffer, "PARE"); return 1; - case 0x9E: sprintf (buffer, "TRI"); return 1; - case 0x9F: sprintf (buffer, "IND"); return 1; - } + switch (oprom[0]) + { + case 0x80: sprintf (buffer, "LIMPO"); return 1; + case 0x81: sprintf (buffer, "UM"); return 1; + case 0x82: sprintf (buffer, "CMP1"); return 1; + case 0x83: sprintf (buffer, "CMP2"); return 1; + case 0x84: sprintf (buffer, "LIN"); return 1; + case 0x85: sprintf (buffer, "INC"); return 1; + case 0x86: sprintf (buffer, "UNEG"); return 1; + case 0x87: sprintf (buffer, "LIMP1"); return 1; + case 0x88: sprintf (buffer, "PNL 0"); return 1; + case 0x89: sprintf (buffer, "PNL 1"); return 1; + case 0x8A: sprintf (buffer, "PNL 2"); return 1; + case 0x8B: sprintf (buffer, "PNL 3"); return 1; + case 0x8C: sprintf (buffer, "PNL 4"); return 1; + case 0x8D: sprintf (buffer, "PNL 5"); return 1; + case 0x8E: sprintf (buffer, "PNL 6"); return 1; + case 0x8F: sprintf (buffer, "PNL 7"); return 1; + case 0x90: sprintf (buffer, "ST 0"); return 1; + case 0x91: sprintf (buffer, "STM 0"); return 1; + case 0x92: sprintf (buffer, "ST 1"); return 1; + case 0x93: sprintf (buffer, "STM 1"); return 1; + case 0x94: sprintf (buffer, "SV 0"); return 1; + case 0x95: sprintf (buffer, "SVM 0"); return 1; + case 0x96: sprintf (buffer, "SV 1"); return 1; + case 0x97: sprintf (buffer, "SVM 1"); return 1; + case 0x98: sprintf (buffer, "PUL"); return 1; + case 0x99: sprintf (buffer, "TRE"); return 1; + case 0x9A: sprintf (buffer, "INIB"); return 1; + case 0x9B: sprintf (buffer, "PERM"); return 1; + case 0x9C: sprintf (buffer, "ESP"); return 1; + case 0x9D: sprintf (buffer, "PARE"); return 1; + case 0x9E: sprintf (buffer, "TRI"); return 1; + case 0x9F: sprintf (buffer, "IND"); return 1; + } - sprintf (buffer, "illegal instruction"); - return 1; + sprintf (buffer, "illegal instruction"); + return 1; } diff --git a/src/devices/cpu/tms32051/32051ops.inc b/src/devices/cpu/tms32051/32051ops.inc index fb78b3a5f18..27827d8cc70 100644 --- a/src/devices/cpu/tms32051/32051ops.inc +++ b/src/devices/cpu/tms32051/32051ops.inc @@ -388,7 +388,7 @@ void tms32051_device::op_and_mem() { UINT16 ea = GET_ADDRESS(); UINT16 data = DM_READ16(ea); - + m_acc &= (UINT32)(data); CYCLES(1); @@ -1359,7 +1359,7 @@ void tms32051_device::op_out() { UINT16 port = ROPCODE(); UINT16 ea = GET_ADDRESS(); - + UINT16 data = DM_READ16(ea); m_io->write_word(port << 1, data); diff --git a/src/devices/cpu/tms32051/tms32051.cpp b/src/devices/cpu/tms32051/tms32051.cpp index d4b565675fc..983678bbf82 100644 --- a/src/devices/cpu/tms32051/tms32051.cpp +++ b/src/devices/cpu/tms32051/tms32051.cpp @@ -387,7 +387,7 @@ void tms32051_device::execute_run() { CHANGE_PC(m_pasr); } - + m_brcr--; if (m_brcr <= 0) { @@ -492,10 +492,10 @@ READ16_MEMBER( tms32051_device::cpuregs_r ) case 0x28: // PDWSR return 0; - case 0x37: // ABU BKR + case 0x37: // ABU BKR return 0; - case 0x50: // Memory-mapped I/O ports + case 0x50: // Memory-mapped I/O ports case 0x51: case 0x52: case 0x53: @@ -606,7 +606,7 @@ WRITE16_MEMBER( tms32051_device::cpuregs_w ) case 0x2a: // CWSR break; - case 0x50: // Memory-mapped I/O ports + case 0x50: // Memory-mapped I/O ports case 0x51: case 0x52: case 0x53: @@ -684,4 +684,4 @@ void tms32053_device::device_config_complete() { m_program_config = address_space_config("program", ENDIANNESS_LITTLE, 16, 16, -1, ADDRESS_MAP_NAME(tms32053_internal_pgm)); m_data_config = address_space_config("data", ENDIANNESS_LITTLE, 16, 16, -1, ADDRESS_MAP_NAME(tms32053_internal_data)); -}
\ No newline at end of file +} diff --git a/src/devices/cpu/tms32082/dis_mp.cpp b/src/devices/cpu/tms32082/dis_mp.cpp index aa13351b88b..e7083901fc7 100644 --- a/src/devices/cpu/tms32082/dis_mp.cpp +++ b/src/devices/cpu/tms32082/dis_mp.cpp @@ -231,14 +231,14 @@ static offs_t tms32082_disasm_mp(char *buffer, offs_t pc, const UINT8 *oprom) case 0x00: print("illop0 "); break; case 0x01: print("trap %d", UIMM15(uimm15)); break; case 0x02: print("cmnd 0x%04X", UIMM15(uimm15)); break; - + case 0x04: if (op == 0x00020000) print("nop "); else print("rdcr %s, R%d", get_creg_name(UIMM15(uimm15)), rd); break; - + case 0x05: print("swcr R%d, %s, R%d", rd, get_creg_name(UIMM15(uimm15)), rs); break; case 0x06: print("brcr %s", get_creg_name(UIMM15(uimm15))); break; case 0x08: print("shift%s.dz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; diff --git a/src/devices/cpu/x86log.h b/src/devices/cpu/x86log.h index 82a8990b59e..ac7195c99bd 100644 --- a/src/devices/cpu/x86log.h +++ b/src/devices/cpu/x86log.h @@ -35,34 +35,34 @@ constexpr int COMMENT_POOL_SIZE{MAX_COMMENTS * 40}; /* code logging info */ struct log_comment { - x86code* base; - const char* string; + x86code* base; + const char* string; }; /* data ranges */ struct data_range_t { - x86code* base; - x86code* end; - int size; + x86code* base; + x86code* end; + int size; }; /* the code logging context */ struct x86log_context { - std::string filename; /* name of the file */ - FILE* file; /* file we are logging to */ + std::string filename; /* name of the file */ + FILE* file; /* file we are logging to */ - data_range_t data_range[MAX_DATA_RANGES]; /* list of data ranges */ - int data_range_count; /* number of data ranges */ + data_range_t data_range[MAX_DATA_RANGES]; /* list of data ranges */ + int data_range_count; /* number of data ranges */ - log_comment comment_list[MAX_COMMENTS]; /* list of comments */ - int comment_count; /* number of live comments */ + log_comment comment_list[MAX_COMMENTS]; /* list of comments */ + int comment_count; /* number of live comments */ - char comment_pool[COMMENT_POOL_SIZE]; /* string pool to hold comments */ - char* comment_pool_next; /* pointer to next string pool location */ + char comment_pool[COMMENT_POOL_SIZE]; /* string pool to hold comments */ + char* comment_pool_next; /* pointer to next string pool location */ }; @@ -80,15 +80,15 @@ void x86log_free_context(x86log_context* log) noexcept; /* add a comment associated with a given code pointer */ template <typename... Ts> inline void x86log_add_comment( - x86log_context* log, x86code* base, const char* format, Ts&&... xs); + x86log_context* log, x86code* base, const char* format, Ts&&... xs); /* mark a given range as data for logging purposes */ void x86log_mark_as_data( - x86log_context* log, x86code* base, x86code* end, int size) noexcept; + x86log_context* log, x86code* base, x86code* end, int size) noexcept; /* disassemble a range of code and reset accumulated information */ void x86log_disasm_code_range( - x86log_context* log, const char* label, x86code* start, x86code* stop); + x86log_context* log, const char* label, x86code* start, x86code* stop); /* manually printf information to the log file */ template <typename... Ts> @@ -102,33 +102,33 @@ inline void x86log_printf(x86log_context* log, const char* format, Ts&&... xs); template <typename... Ts> inline void x86log_add_comment( - x86log_context* log, x86code* base, const char* format, Ts&&... xs) + x86log_context* log, x86code* base, const char* format, Ts&&... xs) { - char* string = log->comment_pool_next; - log_comment* comment; - - assert(log->comment_count < MAX_COMMENTS); - assert(log->comment_pool_next + strlen(format) + 256 < - log->comment_pool + COMMENT_POOL_SIZE); - - /* we assume comments are registered in order; enforce this */ - assert(log->comment_count == 0 || - base >= log->comment_list[log->comment_count - 1].base); - - /* if we exceed the maxima, skip it */ - if(log->comment_count >= MAX_COMMENTS) return; - if(log->comment_pool_next + strlen(format) + 256 >= - log->comment_pool + COMMENT_POOL_SIZE) - return; - - /* do the printf to the string pool */ - log->comment_pool_next += - sprintf(log->comment_pool_next, format, std::forward<Ts>(xs)...) + 1; - - /* fill in the new comment */ - comment = &log->comment_list[log->comment_count++]; - comment->base = base; - comment->string = string; + char* string = log->comment_pool_next; + log_comment* comment; + + assert(log->comment_count < MAX_COMMENTS); + assert(log->comment_pool_next + strlen(format) + 256 < + log->comment_pool + COMMENT_POOL_SIZE); + + /* we assume comments are registered in order; enforce this */ + assert(log->comment_count == 0 || + base >= log->comment_list[log->comment_count - 1].base); + + /* if we exceed the maxima, skip it */ + if(log->comment_count >= MAX_COMMENTS) return; + if(log->comment_pool_next + strlen(format) + 256 >= + log->comment_pool + COMMENT_POOL_SIZE) + return; + + /* do the printf to the string pool */ + log->comment_pool_next += + sprintf(log->comment_pool_next, format, std::forward<Ts>(xs)...) + 1; + + /* fill in the new comment */ + comment = &log->comment_list[log->comment_count++]; + comment->base = base; + comment->string = string; } @@ -140,21 +140,21 @@ inline void x86log_add_comment( template <typename... Ts> inline void x86log_printf(x86log_context* log, const char* format, Ts&&... xs) { - /* open the file, creating it if necessary */ - if(log->file == nullptr) - { - log->file = fopen(log->filename.c_str(), "w"); + /* open the file, creating it if necessary */ + if(log->file == nullptr) + { + log->file = fopen(log->filename.c_str(), "w"); - if(log->file == nullptr) return; - } + if(log->file == nullptr) return; + } - assert(log->file != nullptr); + assert(log->file != nullptr); - /* do the printf */ - fprintf(log->file, format, std::forward<Ts>(xs)...); + /* do the printf */ + fprintf(log->file, format, std::forward<Ts>(xs)...); - /* flush the file */ - fflush(log->file); + /* flush the file */ + fflush(log->file); } #endif /* __X86LOG_H__ */ diff --git a/src/devices/machine/i8271.cpp b/src/devices/machine/i8271.cpp index 3d1d602dd74..cd8c0faf5bf 100644 --- a/src/devices/machine/i8271.cpp +++ b/src/devices/machine/i8271.cpp @@ -1541,7 +1541,6 @@ void i8271_device::device_timer(emu_timer &timer, device_timer_id id, int param, void i8271_device::index_callback(floppy_image_device *floppy, int state) { for(auto & fi : flopi) { - if(fi.dev != floppy) continue; diff --git a/src/devices/machine/k053252.cpp b/src/devices/machine/k053252.cpp index 6bd561233b4..45020926ace 100644 --- a/src/devices/machine/k053252.cpp +++ b/src/devices/machine/k053252.cpp @@ -123,7 +123,7 @@ void k053252_device::device_reset() m_regs[i] = 0; m_regs[0x08] = 1; // Xexex apparently does a wrong assignment for VC (sets up the INT enable register instead) - + reset_internal_state(); } @@ -173,14 +173,14 @@ void k053252_device::res_change() //(HC+1) - HFP - HBP - 8*(HSW+1) //VC - VFP - VBP - (VSW+1) attoseconds_t refresh = HZ_TO_ATTOSECONDS(clock()) * (m_hc) * m_vc; - + visarea.min_x = m_offsx; visarea.min_y = m_offsy; visarea.max_x = m_offsx + m_hc - m_hfp - m_hbp - 8*(m_hsw) - 1; visarea.max_y = m_offsy + m_vc - m_vfp - m_vbp - (m_vsw) - 1; - + m_screen->configure(m_hc, m_vc, visarea, refresh); - + if (m_slave_screen) m_slave_screen->configure(m_hc, m_vc, visarea, refresh); @@ -189,7 +189,7 @@ void k053252_device::res_change() printf("H %d HFP %d HSW %d HBP %d\n",m_hc,m_hfp,m_hsw*8,m_hbp); printf("V %d VFP %d VSW %d VBP %d\n",m_vc,m_vfp,m_vsw,m_vbp); // L stands for Legacy ... - printf("L %d %d\n",m_offsx,m_offsy); + printf("L %d %d\n",m_offsx,m_offsy); printf("Screen params: Clock: %u V-Sync %.2f H-Sync %.f\n",clock(),ATTOSECONDS_TO_HZ(refresh),ATTOSECONDS_TO_HZ(hsync)); printf("visible screen area: %d x %d\n\n",(visarea.max_x - visarea.min_x) + 1,(visarea.max_y - visarea.min_y) + 1); #endif @@ -251,7 +251,7 @@ WRITE8_MEMBER( k053252_device::write ) logerror("%02x VSW / %02x HSW set\n",m_vsw,m_hsw); res_change(); break; - + //case 0x0d: m_int_time(data); break; case 0x0e: m_int1_ack_cb(1); break; case 0x0f: m_int2_ack_cb(1); break; diff --git a/src/devices/machine/k053252.h b/src/devices/machine/k053252.h index a33b0f60698..a00743789ad 100644 --- a/src/devices/machine/k053252.h +++ b/src/devices/machine/k053252.h @@ -48,18 +48,18 @@ public: DECLARE_WRITE8_MEMBER( write ); void res_change(); - - + + static void static_set_slave_screen(device_t &device, const char *tag); protected: // device-level overrides virtual void device_start() override; - virtual void device_reset() override; + virtual void device_reset() override; virtual void device_clock_changed() override { reset_internal_state(); } void reset_internal_state(); - + private: // internal state UINT8 m_regs[16]; @@ -75,7 +75,7 @@ protected: int m_offsx; int m_offsy; - const char * m_slave_screen_tag; + const char * m_slave_screen_tag; screen_device * m_slave_screen; }; diff --git a/src/devices/machine/laserdsc.cpp b/src/devices/machine/laserdsc.cpp index b8ecf53611c..7dbae408ba7 100644 --- a/src/devices/machine/laserdsc.cpp +++ b/src/devices/machine/laserdsc.cpp @@ -805,7 +805,7 @@ void laserdisc_device::init_video() for (auto & frame : m_frame) { // first allocate a YUY16 bitmap at 2x the height - + frame.m_bitmap.allocate(m_width, m_height * 2); frame.m_bitmap.set_palette(m_videopalette); fillbitmap_yuy16(frame.m_bitmap, 40, 109, 240); diff --git a/src/devices/machine/pdc.cpp b/src/devices/machine/pdc.cpp index 0df1621f980..4a882d12a04 100644 --- a/src/devices/machine/pdc.cpp +++ b/src/devices/machine/pdc.cpp @@ -7,87 +7,87 @@ **********************************************************************/ /* - Device PDCN - Board Copyright - IBM Corp 1989 Made in USA - - Labels: - * 96D1975 - MN 90594C - - * EC# A6466SP - MFG 85575 - - Hardware: - * CPU - Zilog Z0840006PSC Z80 @ 5MHz - U19 - * FDC - NEC D765AC-2 9002P7004 - U35 - * HDC - HDC9224 SMC E8838 8/90 - U59 - * DMA - P8237A-5 L1041330 - U34 - * Channel 0 - FDC - * Channel 1 - Main system ram - * Memory - HM6264ALP-12 SRAM 8KB - U16 - * Memory - HM6116P-2 SRAM 2KB - U33 - Logic: - * U1 - PLS105AN Label: 59D9101 - * U11 - ?? Label: 59D10001 - * U27 - ?? Label: 96D1978 - * U28 - ?? Label: 97D8750 - * U31 - TIBPAL20L8-25CNT Label: 96D1987 - * U32 - ?? Label: 59D1001 - * U37 - PLS100N Label: 72D2701 - * U38 - PLS100N Label: 58D9201 - * U39 - ?? Label: 96D1981 - * U40 - ?? Label: 96D1984 - * U68 - ?? Label: 91D4301 - * U69 - ?? Label: 59D1001 - * U70 - ?? Label: 59D1001 - - Switches: - * S1 - Hard drive format configuration (Default all off) - * S2 - Floppy drive format configuration (Default 1-7 off, 8 on) - - Program Memory: - * 0x0000 - 0x3FFF : ROM 27128 Label: 97D9988 - * 0x8000 - 0x9FFF : SRAM HM6264ALP-12 8KB - * 0xC000 - 0xC7FF : SRAM HM6116P-2 2KB - - IO Memory: - * 0x00 - 0x01 : Old style command [0x5FF041B0] - * 0x02 - 0x03 : FDC command address [0x5FF0C0B0][0x5FF0C1B0] - * 0x04 - 0x05 : FDC command completion status [0x5FF030B0] - * 0x06 - 0x07 : FDC data address [0x5FF080B0] - * 0x10 - 0x18 : HDC registers (unknown) - * 0x21 - 0x21 : FDC unknown, resets bit 1 on 0x38 - * 0x22 - 0x22 : FDC unknown - * 0x23 - 0x24 : FDC Active DMA host address (auto increments) - * 0x25 - 0x25 : FDC unknown - * 0x26 - 0x26 : DREQ1 on - * 0x27 - 0x27 : FDC unknown - * 0x28 - 0x2A : Possibly LED lights - * 0x2C - 0x2C : DREQ1 off - * 0x2D - 0x2D : Unknown - * 0x2E - 0x2E : Transfer direction 0x80 = PDC -> Host (read data) - 0x00 = Host -> PDC (Commands, write data) - * 0x2F - 0x2F : Unknown - * 0x38 - 0x38 : FDC command request - Bit 1: Debug? - Bit 2: Command complete - Bit 3: Unknown - Bit 5: Unknown - Bit 6-7: Error conditions - * 0x39 - 0x39 : Interrupt status - Bit 0: HDC9224 interrupt - Bit 1: Incoming command - Bit 3: FDD related, maybe uPD interrupt pin? - * 0x3C - 0x3D : Dipswitch 2 and 1 - * 0x40 - 0x40 : HDC9224 DATA register - * 0x41 - 0x41 : HDC9224 COMMAND register - * 0x42 - 0x42 : uPD765 STATUS register - * 0x43 - 0x43 : uPD765 DATA register - * 0x50 - 0x51 : Unknown - reset latch maybe? - * 0x52 - 0x52 : FDD Master motor control - * 0x53 - 0x53 : Unknown - * 0x54 - 0x57 : FDD motor control (Units 1-4) - * 0x60 - 0x6F : P8237A DMA controller register set + Device PDCN + Board Copyright - IBM Corp 1989 Made in USA + + Labels: + * 96D1975 + MN 90594C + + * EC# A6466SP + MFG 85575 + + Hardware: + * CPU - Zilog Z0840006PSC Z80 @ 5MHz - U19 + * FDC - NEC D765AC-2 9002P7004 - U35 + * HDC - HDC9224 SMC E8838 8/90 - U59 + * DMA - P8237A-5 L1041330 - U34 + * Channel 0 - FDC + * Channel 1 - Main system ram + * Memory - HM6264ALP-12 SRAM 8KB - U16 + * Memory - HM6116P-2 SRAM 2KB - U33 + Logic: + * U1 - PLS105AN Label: 59D9101 + * U11 - ?? Label: 59D10001 + * U27 - ?? Label: 96D1978 + * U28 - ?? Label: 97D8750 + * U31 - TIBPAL20L8-25CNT Label: 96D1987 + * U32 - ?? Label: 59D1001 + * U37 - PLS100N Label: 72D2701 + * U38 - PLS100N Label: 58D9201 + * U39 - ?? Label: 96D1981 + * U40 - ?? Label: 96D1984 + * U68 - ?? Label: 91D4301 + * U69 - ?? Label: 59D1001 + * U70 - ?? Label: 59D1001 + + Switches: + * S1 - Hard drive format configuration (Default all off) + * S2 - Floppy drive format configuration (Default 1-7 off, 8 on) + + Program Memory: + * 0x0000 - 0x3FFF : ROM 27128 Label: 97D9988 + * 0x8000 - 0x9FFF : SRAM HM6264ALP-12 8KB + * 0xC000 - 0xC7FF : SRAM HM6116P-2 2KB + + IO Memory: + * 0x00 - 0x01 : Old style command [0x5FF041B0] + * 0x02 - 0x03 : FDC command address [0x5FF0C0B0][0x5FF0C1B0] + * 0x04 - 0x05 : FDC command completion status [0x5FF030B0] + * 0x06 - 0x07 : FDC data address [0x5FF080B0] + * 0x10 - 0x18 : HDC registers (unknown) + * 0x21 - 0x21 : FDC unknown, resets bit 1 on 0x38 + * 0x22 - 0x22 : FDC unknown + * 0x23 - 0x24 : FDC Active DMA host address (auto increments) + * 0x25 - 0x25 : FDC unknown + * 0x26 - 0x26 : DREQ1 on + * 0x27 - 0x27 : FDC unknown + * 0x28 - 0x2A : Possibly LED lights + * 0x2C - 0x2C : DREQ1 off + * 0x2D - 0x2D : Unknown + * 0x2E - 0x2E : Transfer direction 0x80 = PDC -> Host (read data) + 0x00 = Host -> PDC (Commands, write data) + * 0x2F - 0x2F : Unknown + * 0x38 - 0x38 : FDC command request + Bit 1: Debug? + Bit 2: Command complete + Bit 3: Unknown + Bit 5: Unknown + Bit 6-7: Error conditions + * 0x39 - 0x39 : Interrupt status + Bit 0: HDC9224 interrupt + Bit 1: Incoming command + Bit 3: FDD related, maybe uPD interrupt pin? + * 0x3C - 0x3D : Dipswitch 2 and 1 + * 0x40 - 0x40 : HDC9224 DATA register + * 0x41 - 0x41 : HDC9224 COMMAND register + * 0x42 - 0x42 : uPD765 STATUS register + * 0x43 - 0x43 : uPD765 DATA register + * 0x50 - 0x51 : Unknown - reset latch maybe? + * 0x52 - 0x52 : FDD Master motor control + * 0x53 - 0x53 : Unknown + * 0x54 - 0x57 : FDD motor control (Units 1-4) + * 0x60 - 0x6F : P8237A DMA controller register set */ @@ -98,10 +98,10 @@ // MACROS / CONSTANTS //************************************************************************** -#define Z80_TAG "pdc_z80" // U19 +#define Z80_TAG "pdc_z80" // U19 #define FDC_TAG "fdc" -#define HDC_TAG "hdc" -#define FDCDMA_TAG "i8237dma" +#define HDC_TAG "hdc" +#define FDCDMA_TAG "i8237dma" #define TRACE_PDC_FDC 0 #define TRACE_PDC_HDC 0 @@ -119,8 +119,8 @@ const device_type PDC = &device_creator<pdc_device>; //------------------------------------------------- ROM_START( pdc ) - ROM_REGION( 0x4000, "rom", 0 ) - ROM_LOAD( "97d9988.27128.pdc.u17", 0x0000, 0x4000, CRC(d96ccaa6) SHA1(e1a465c2274a63e81dba7a71fc8b30f10c03baf0) ) // Label: "97D9988" 27128 @U17 + ROM_REGION( 0x4000, "rom", 0 ) + ROM_LOAD( "97d9988.27128.pdc.u17", 0x0000, 0x4000, CRC(d96ccaa6) SHA1(e1a465c2274a63e81dba7a71fc8b30f10c03baf0) ) // Label: "97D9988" 27128 @U17 ROM_END //------------------------------------------------- @@ -129,7 +129,7 @@ ROM_END const rom_entry *pdc_device::device_rom_region() const { - return ROM_NAME( pdc ); + return ROM_NAME( pdc ); } //------------------------------------------------- @@ -232,10 +232,10 @@ SLOT_INTERFACE_END //------------------------------------------------- static SLOT_INTERFACE_START( pdc_harddisks ) - SLOT_INTERFACE( "generic", MFMHD_GENERIC ) // Generic hard disk (self-adapting to image) - SLOT_INTERFACE( "st213", MFMHD_ST213 ) // Seagate ST-213 (10 MB) - SLOT_INTERFACE( "st225", MFMHD_ST225 ) // Seagate ST-225 (20 MB) - SLOT_INTERFACE( "st251", MFMHD_ST251 ) // Seagate ST-251 (40 MB) + SLOT_INTERFACE( "generic", MFMHD_GENERIC ) // Generic hard disk (self-adapting to image) + SLOT_INTERFACE( "st213", MFMHD_ST213 ) // Seagate ST-213 (10 MB) + SLOT_INTERFACE( "st225", MFMHD_ST225 ) // Seagate ST-225 (20 MB) + SLOT_INTERFACE( "st251", MFMHD_ST251 ) // Seagate ST-251 (40 MB) SLOT_INTERFACE_END //------------------------------------------------- @@ -243,7 +243,7 @@ SLOT_INTERFACE_END //------------------------------------------------- FLOPPY_FORMATS_MEMBER( pdc_device::floppy_formats ) - FLOPPY_PC_FORMAT + FLOPPY_PC_FORMAT FLOPPY_FORMATS_END //------------------------------------------------- @@ -252,8 +252,8 @@ FLOPPY_FORMATS_END static MACHINE_CONFIG_FRAGMENT( pdc ) /* CPU - Zilog Z0840006PSC */ - MCFG_CPU_ADD(Z80_TAG, Z80, XTAL_10MHz / 2) - MCFG_CPU_PROGRAM_MAP(pdc_mem) + MCFG_CPU_ADD(Z80_TAG, Z80, XTAL_10MHz / 2) + MCFG_CPU_PROGRAM_MAP(pdc_mem) MCFG_CPU_IO_MAP(pdc_io) //MCFG_QUANTUM_PERFECT_CPU(M6502_TAG) @@ -290,7 +290,7 @@ MACHINE_CONFIG_END machine_config_constructor pdc_device::device_mconfig_additions() const { - return MACHINE_CONFIG_NAME( pdc ); + return MACHINE_CONFIG_NAME( pdc ); } ioport_constructor pdc_device::device_input_ports() const @@ -308,7 +308,7 @@ ioport_constructor pdc_device::device_input_ports() const pdc_device::pdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : device_t(mconfig, PDC, "ROLM PDC", tag, owner, clock, "pdc", __FILE__), - m_pdccpu(*this, Z80_TAG), + m_pdccpu(*this, Z80_TAG), m_dma8237(*this, FDCDMA_TAG), m_fdc(*this, FDC_TAG), m_hdc9224(*this, HDC_TAG), @@ -338,7 +338,7 @@ void pdc_device::device_reset() //reg_p38 |= 0x20; // no idea at all - bit 5 (32) /* Reset CPU */ - m_pdccpu->reset(); + m_pdccpu->reset(); /* Resolve callbacks */ m_m68k_r_cb.resolve_safe(0); diff --git a/src/devices/machine/pdc.h b/src/devices/machine/pdc.h index ac085ea02cd..c1f3a3cbf51 100644 --- a/src/devices/machine/pdc.h +++ b/src/devices/machine/pdc.h @@ -34,11 +34,11 @@ class pdc_device : public device_t { public: - /* Constructor and Destructor */ + /* Constructor and Destructor */ pdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - /* Optional information overrides */ - virtual machine_config_constructor device_mconfig_additions() const override; + /* Optional information overrides */ + virtual machine_config_constructor device_mconfig_additions() const override; virtual ioport_constructor device_input_ports() const override; virtual const rom_entry *device_rom_region() const override; @@ -69,7 +69,7 @@ public: DECLARE_WRITE8_MEMBER(m68k_dma_w); DECLARE_WRITE_LINE_MEMBER(fdc_irq); - DECLARE_FLOPPY_FORMATS( floppy_formats ); + DECLARE_FLOPPY_FORMATS( floppy_formats ); /* Main CPU accessible registers */ UINT8 reg_p0; @@ -84,16 +84,16 @@ public: UINT8 reg_p38; UINT32 fdd_68k_dma_address; /* FDD <-> m68k DMA read/write address */ protected: - /* Device-level overrides */ - virtual void device_start() override; - virtual void device_reset() override; + /* Device-level overrides */ + virtual void device_start() override; + virtual void device_reset() override; /* Protected variables */ //UINT32 fdd_68k_dma_address; bool b_fdc_irq; /* Attached devices */ - required_device<cpu_device> m_pdccpu; + required_device<cpu_device> m_pdccpu; required_device<am9517a_device> m_dma8237; required_device<upd765a_device> m_fdc; //required_device<floppy_connector> m_floppy; @@ -103,8 +103,8 @@ protected: required_shared_ptr<UINT8> m_pdc_ram; /* Callbacks */ - devcb_read8 m_m68k_r_cb; - devcb_write8 m_m68k_w_cb; + devcb_read8 m_m68k_r_cb; + devcb_write8 m_m68k_w_cb; }; /* Device type */ diff --git a/src/devices/machine/pla.cpp b/src/devices/machine/pla.cpp index 417fb4e6c3f..f96a2bd8f60 100644 --- a/src/devices/machine/pla.cpp +++ b/src/devices/machine/pla.cpp @@ -148,8 +148,6 @@ UINT32 pla_device::read(UINT32 input) for (auto cache2_entry : m_cache2) { - - if ((UINT32)cache2_entry == input) { // cache2 hit diff --git a/src/devices/machine/tms6100.cpp b/src/devices/machine/tms6100.cpp index fc340de9247..402ba1ad7ca 100644 --- a/src/devices/machine/tms6100.cpp +++ b/src/devices/machine/tms6100.cpp @@ -206,7 +206,7 @@ WRITE_LINE_MEMBER(tms6100_device::romclock_w) UINT8 word = m_rom[m_address >> 3]; if (m_reverse_bits) word = BITSWAP8(word,0,1,2,3,4,5,6,7); - + if (m_4bit_read) { m_data = word >> (m_address & 4) & 0xf; diff --git a/src/devices/machine/upd765.cpp b/src/devices/machine/upd765.cpp index 6587c44d360..48901ef2314 100644 --- a/src/devices/machine/upd765.cpp +++ b/src/devices/machine/upd765.cpp @@ -2247,7 +2247,6 @@ void upd765_family_device::run_drive_ready_polling() void upd765_family_device::index_callback(floppy_image_device *floppy, int state) { for(auto & fi : flopi) { - if(fi.dev != floppy) continue; diff --git a/src/devices/machine/z80ctc.cpp b/src/devices/machine/z80ctc.cpp index 13c4844c9e3..276254d96f1 100644 --- a/src/devices/machine/z80ctc.cpp +++ b/src/devices/machine/z80ctc.cpp @@ -185,8 +185,6 @@ int z80ctc_device::z80daisy_irq_state() int state = 0; for (auto & channel : m_channel) { - - // if we're servicing a request, don't indicate more interrupts if (channel.m_int_state & Z80_DAISY_IEO) { diff --git a/src/devices/machine/z80scc.h b/src/devices/machine/z80scc.h index edd0d9b6992..7f956ec9b74 100644 --- a/src/devices/machine/z80scc.h +++ b/src/devices/machine/z80scc.h @@ -137,7 +137,7 @@ public: UINT8 do_sccreg_rr5(); UINT8 do_sccreg_rr6(); UINT8 do_sccreg_rr7(); -// UINT8 do_sccreg_rr8(); +// UINT8 do_sccreg_rr8(); UINT8 do_sccreg_rr9(); UINT8 do_sccreg_rr10(); UINT8 do_sccreg_rr11(); diff --git a/src/devices/sound/k053260.cpp b/src/devices/sound/k053260.cpp index 134598a1f7c..f3ebc4b2445 100644 --- a/src/devices/sound/k053260.cpp +++ b/src/devices/sound/k053260.cpp @@ -274,7 +274,6 @@ void k053260_device::sound_stream_update(sound_stream &stream, stream_sample_t * for (auto & voice : m_voice) { - if (voice.playing()) voice.play(buffer); } diff --git a/src/devices/sound/qs1000.cpp b/src/devices/sound/qs1000.cpp index 44ff9017ea4..a892945adad 100644 --- a/src/devices/sound/qs1000.cpp +++ b/src/devices/sound/qs1000.cpp @@ -488,8 +488,6 @@ void qs1000_device::sound_stream_update(sound_stream &stream, stream_sample_t ** // Iterate over voices and accumulate sample data for (auto & chan : m_channels) { - - UINT8 lvol = chan.m_regs[6]; UINT8 rvol = chan.m_regs[7]; UINT8 vol = chan.m_regs[8]; diff --git a/src/devices/video/315_5313.h b/src/devices/video/315_5313.h index 5994d47bb47..d7ca05ee2e6 100644 --- a/src/devices/video/315_5313.h +++ b/src/devices/video/315_5313.h @@ -294,7 +294,7 @@ private: int m_vdp_pal; int m_use_cram; // c2 uses it's own palette ram, so it sets this to 0 int m_dma_delay; // SVP and SegaCD have some 'lag' in DMA transfers - + std::unique_ptr<UINT16[]> m_regs; std::unique_ptr<UINT16[]> m_vram; std::unique_ptr<UINT16[]> m_cram; diff --git a/src/devices/video/ef9365.cpp b/src/devices/video/ef9365.cpp index 0a5405fcf65..f923cfd0813 100644 --- a/src/devices/video/ef9365.cpp +++ b/src/devices/video/ef9365.cpp @@ -1,67 +1,67 @@ // license:BSD-3-Clause -// copyright-holders:Jean-François DEL NERO +// copyright-holders:Jean-Francois DEL NERO /********************************************************************* - ef9365.c - - Thomson EF9365/EF9366 video controller emulator code - - The EF9365/EF9366 is a video controller driving a frame buffer - and having built-in vectors and characters drawing engines. - This is natively a "black and white" chip (1 bitplane), - but it is possible to add more bitplanes to have colors with a - hardware trick. The system don't have direct access to the video - memory, but indirect access is possible through the 0x0F command - and some hardware glue logics. - The current implementation emulate the main functions : - - Video modes supported (Hardware implementation dependent): - - 256 x 256 (EF9365 with 4 bits shifters per bitplane and FMAT to VSS) - - 512 x 512 interlaced (EF9365 with 8 bits shifters per bitplane and FMAT to VCC) - - 512 x 256 non interlaced (EF9366 with 8 bits shifters per bitplane) - - 128 x 128 (EF9365 with 2 bits shifters per bitplane and FMAT to VSS) - - 64 x 64 (EF9365 with FMAT to VSS) - - - 1 bitplane up to 8 bitplanes hardware configuration. - - 2 up to 256 colors fixed palette. - - Character & block drawing : - - Normal / Titled mode - - Horizontal / Vertical orientation - - P & Q Zoom factors (1 up to 16) - - Vector drawing : - - Normal / Dotted / Dashed / Dotted-Dashed mode - - All directions and size supported. - - General : - - Clear Screen - - Fill Screen - - Clear X & Y registers - - Video RAM readback supported (Command 0x0F) - - What is NOT yet currently implemented: - - Light pen support - (To be done when i will find a software using the lightpen) - - What is implemented but not really tested: - - Interrupts output. - My target system (Squale Apollo 7) doesn't use the interruption - for this chip. So i add the interrupt line support, but - bug(s) is possible. - - The needed charset file charset_ef9365.rom (CRC 8d3053be) is available - there : http://hxc2001.free.fr/Squale/rom/charset_ef9365.zip - This ROM charset is into the EF9365/EF9366. - - To see how to use this driver, have a look to the Squale machine - driver (squale.cpp). - If you have any question, don't hesitate to contact me at the email - present on this website : http://hxc2001.free.fr/ - - 12/29/2015 - Jean-François DEL NERO + ef9365.c + + Thomson EF9365/EF9366 video controller emulator code + + The EF9365/EF9366 is a video controller driving a frame buffer + and having built-in vectors and characters drawing engines. + This is natively a "black and white" chip (1 bitplane), + but it is possible to add more bitplanes to have colors with a + hardware trick. The system don't have direct access to the video + memory, but indirect access is possible through the 0x0F command + and some hardware glue logics. + The current implementation emulate the main functions : + + Video modes supported (Hardware implementation dependent): + - 256 x 256 (EF9365 with 4 bits shifters per bitplane and FMAT to VSS) + - 512 x 512 interlaced (EF9365 with 8 bits shifters per bitplane and FMAT to VCC) + - 512 x 256 non interlaced (EF9366 with 8 bits shifters per bitplane) + - 128 x 128 (EF9365 with 2 bits shifters per bitplane and FMAT to VSS) + - 64 x 64 (EF9365 with FMAT to VSS) + + - 1 bitplane up to 8 bitplanes hardware configuration. + - 2 up to 256 colors fixed palette. + + Character & block drawing : + - Normal / Titled mode + - Horizontal / Vertical orientation + - P & Q Zoom factors (1 up to 16) + + Vector drawing : + - Normal / Dotted / Dashed / Dotted-Dashed mode + - All directions and size supported. + + General : + - Clear Screen + - Fill Screen + - Clear X & Y registers + - Video RAM readback supported (Command 0x0F) + + What is NOT yet currently implemented: + - Light pen support + (To be done when i will find a software using the lightpen) + + What is implemented but not really tested: + - Interrupts output. + My target system (Squale Apollo 7) doesn't use the interruption + for this chip. So i add the interrupt line support, but + bug(s) is possible. + + The needed charset file charset_ef9365.rom (CRC 8d3053be) is available + there : http://hxc2001.free.fr/Squale/rom/charset_ef9365.zip + This ROM charset is into the EF9365/EF9366. + + To see how to use this driver, have a look to the Squale machine + driver (squale.cpp). + If you have any question, don't hesitate to contact me at the email + present on this website : http://hxc2001.free.fr/ + + 12/29/2015 + Jean-Francois DEL NERO *********************************************************************/ #include "emu.h" @@ -343,8 +343,8 @@ void ef9365_device::device_reset() void ef9365_device::update_interrupts() { int new_state = ( m_irq_vb && (m_registers[EF936X_REG_CTRL1] & 0x20) ) - || ( m_irq_rdy && (m_registers[EF936X_REG_CTRL1] & 0x40) ) - || ( m_irq_lb && (m_registers[EF936X_REG_CTRL1] & 0x10) ); + || ( m_irq_rdy && (m_registers[EF936X_REG_CTRL1] & 0x40) ) + || ( m_irq_lb && (m_registers[EF936X_REG_CTRL1] & 0x10) ); if (new_state != m_irq_state) { @@ -471,7 +471,6 @@ UINT8 ef9365_device::get_last_readback_word(int bitplane_number, int * pixel_off void ef9365_device::draw_border(UINT16 line) { - } //------------------------------------------------- @@ -792,7 +791,7 @@ int ef9365_device::draw_character( unsigned char c, int block, int smallblock ) for(p = 0; p < p_factor; p++) { if( !(m_registers[EF936X_REG_CTRL2] & 0x08) ) - { // Titled - Horizontal orientation + { // Titled - Horizontal orientation plot( x + ( (y_char*q_factor) + q ) + ( (x_char*p_factor) + p ), y + ( (y_char*q_factor) + q ) @@ -816,14 +815,14 @@ int ef9365_device::draw_character( unsigned char c, int block, int smallblock ) for(p = 0; p < p_factor; p++) { if( !(m_registers[EF936X_REG_CTRL2] & 0x08) ) - { // Normal - Horizontal orientation + { // Normal - Horizontal orientation plot( x + ( (x_char*p_factor) + p ), y + ( (y_char*q_factor) + q ) ); } else - { // Normal - Vertical orientation + { // Normal - Vertical orientation plot( x - ( (y_char*q_factor) + q ), y + ( (x_char*p_factor) + p ) @@ -1046,29 +1045,29 @@ void ef9365_device::ef9365_exec(UINT8 cmd) switch ( cmd & 0x7 ) // Direction code { case 0x1: - busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() + tmp_delta_x, get_y_reg() + tmp_delta_y); + busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() + tmp_delta_x, get_y_reg() + tmp_delta_y); break; case 0x3: - busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() - tmp_delta_x, get_y_reg() + tmp_delta_y); + busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() - tmp_delta_x, get_y_reg() + tmp_delta_y); break; case 0x5: - busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() + tmp_delta_x, get_y_reg() - tmp_delta_y); + busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() + tmp_delta_x, get_y_reg() - tmp_delta_y); break; case 0x7: - busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() - tmp_delta_x, get_y_reg() - tmp_delta_y); + busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() - tmp_delta_x, get_y_reg() - tmp_delta_y); break; case 0x0: - busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() + tmp_delta_x, get_y_reg() ); + busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() + tmp_delta_x, get_y_reg() ); break; case 0x2: - busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg(), get_y_reg() + tmp_delta_y); + busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg(), get_y_reg() + tmp_delta_y); break; case 0x4: - busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg(), get_y_reg() - tmp_delta_y); + busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg(), get_y_reg() - tmp_delta_y); break; case 0x6: - busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() - tmp_delta_x, get_y_reg() ); + busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() - tmp_delta_x, get_y_reg() ); break; } set_busy_flag( cycles_to_us( busy_cycles ) ); @@ -1088,29 +1087,29 @@ void ef9365_device::ef9365_exec(UINT8 cmd) switch ( cmd & 0x7 ) // Direction code { case 0x1: - busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() + tmp_delta_x, get_y_reg() + tmp_delta_y); + busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() + tmp_delta_x, get_y_reg() + tmp_delta_y); break; case 0x3: - busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() - tmp_delta_x, get_y_reg() + tmp_delta_y); + busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() - tmp_delta_x, get_y_reg() + tmp_delta_y); break; case 0x5: - busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() + tmp_delta_x, get_y_reg() - tmp_delta_y); + busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() + tmp_delta_x, get_y_reg() - tmp_delta_y); break; case 0x7: - busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() - tmp_delta_x, get_y_reg() - tmp_delta_y); + busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() - tmp_delta_x, get_y_reg() - tmp_delta_y); break; case 0x0: - busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() + tmp_delta_x, get_y_reg() ); + busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() + tmp_delta_x, get_y_reg() ); break; case 0x2: - busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg(), get_y_reg() + tmp_delta_y); + busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg(), get_y_reg() + tmp_delta_y); break; case 0x4: - busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg(), get_y_reg() - tmp_delta_y); + busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg(), get_y_reg() - tmp_delta_y); break; case 0x6: - busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() - tmp_delta_x, get_y_reg() ); + busy_cycles = draw_vector ( get_x_reg(), get_y_reg(), get_x_reg() - tmp_delta_x, get_y_reg() ); break; } diff --git a/src/devices/video/ef9365.h b/src/devices/video/ef9365.h index 9127bf8965e..e29b3adca33 100644 --- a/src/devices/video/ef9365.h +++ b/src/devices/video/ef9365.h @@ -1,5 +1,5 @@ // license:BSD-3-Clause -// copyright-holders:Jean-François DEL NERO +// copyright-holders:Jean-Francois DEL NERO /********************************************************************* ef9365.h @@ -88,7 +88,7 @@ private: void set_video_mode(void); void draw_border(UINT16 line); void ef9365_exec(UINT8 cmd); - int cycles_to_us(int cycles); + int cycles_to_us(int cycles); void dump_bitplanes_word(); void update_interrupts(); |
