diff options
Diffstat (limited to 'src/devices/cpu/hphybrid/hphybrid.cpp')
-rw-r--r-- | src/devices/cpu/hphybrid/hphybrid.cpp | 1337 |
1 files changed, 668 insertions, 669 deletions
diff --git a/src/devices/cpu/hphybrid/hphybrid.cpp b/src/devices/cpu/hphybrid/hphybrid.cpp index ddfd740d90b..855931b59ee 100644 --- a/src/devices/cpu/hphybrid/hphybrid.cpp +++ b/src/devices/cpu/hphybrid/hphybrid.cpp @@ -18,21 +18,21 @@ enum { HPHYBRID_DMAMA, HPHYBRID_DMAC, HPHYBRID_I, - HPHYBRID_W, - HPHYBRID_AR2, - HPHYBRID_AR2_2, - HPHYBRID_AR2_3, - HPHYBRID_AR2_4, - HPHYBRID_SE, - HPHYBRID_R25, - HPHYBRID_R26, - HPHYBRID_R27, - HPHYBRID_R32, - HPHYBRID_R33, - HPHYBRID_R34, - HPHYBRID_R35, - HPHYBRID_R36, - HPHYBRID_R37 + HPHYBRID_W, + HPHYBRID_AR2, + HPHYBRID_AR2_2, + HPHYBRID_AR2_3, + HPHYBRID_AR2_4, + HPHYBRID_SE, + HPHYBRID_R25, + HPHYBRID_R26, + HPHYBRID_R27, + HPHYBRID_R32, + HPHYBRID_R33, + HPHYBRID_R34, + HPHYBRID_R35, + HPHYBRID_R36, + HPHYBRID_R37 }; #define BIT_MASK(n) (1U << (n)) @@ -84,36 +84,36 @@ WRITE_LINE_MEMBER(hp_hybrid_cpu_device::dmar_w) WRITE_LINE_MEMBER(hp_hybrid_cpu_device::halt_w) { - if (state) { - BIT_SET(m_flags , HPHYBRID_HALT_BIT); - } else { - BIT_CLR(m_flags , HPHYBRID_HALT_BIT); - } + if (state) { + BIT_SET(m_flags , HPHYBRID_HALT_BIT); + } else { + BIT_CLR(m_flags , HPHYBRID_HALT_BIT); + } } WRITE_LINE_MEMBER(hp_hybrid_cpu_device::status_w) { - if (state) { - BIT_SET(m_flags , HPHYBRID_STS_BIT); - } else { - BIT_CLR(m_flags , HPHYBRID_STS_BIT); - } + if (state) { + BIT_SET(m_flags , HPHYBRID_STS_BIT); + } else { + BIT_CLR(m_flags , HPHYBRID_STS_BIT); + } } WRITE_LINE_MEMBER(hp_hybrid_cpu_device::flag_w) { - if (state) { - BIT_SET(m_flags , HPHYBRID_FLG_BIT); - } else { - BIT_CLR(m_flags , HPHYBRID_FLG_BIT); - } + if (state) { + BIT_SET(m_flags , HPHYBRID_FLG_BIT); + } else { + BIT_CLR(m_flags , HPHYBRID_FLG_BIT); + } } hp_hybrid_cpu_device::hp_hybrid_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname , UINT8 addrwidth) - : cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__), - m_pa_changed_func(*this), - m_program_config("program", ENDIANNESS_BIG, 16, addrwidth, -1), - m_io_config("io", ENDIANNESS_BIG, 16, 6, -1) + : cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__), + m_pa_changed_func(*this), + m_program_config("program", ENDIANNESS_BIG, 16, addrwidth, -1), + m_io_config("io", ENDIANNESS_BIG, 16, 6, -1) { } @@ -129,13 +129,13 @@ void hp_hybrid_cpu_device::device_start() m_reg_PA[ 0 ] = 0; m_reg_PA[ 1 ] = 0; m_reg_PA[ 2 ] = 0; - m_reg_W = 0; + m_reg_W = 0; m_flags = 0; m_dmapa = 0; m_dmama = 0; m_dmac = 0; m_reg_I = 0; - m_forced_bsc_25 = false; + m_forced_bsc_25 = false; { state_add(HPHYBRID_A, "A", m_reg_A); @@ -148,7 +148,7 @@ void hp_hybrid_cpu_device::device_start() state_add(STATE_GENSP, "GENSP", m_reg_R).noshow(); state_add(HPHYBRID_IV, "IV", m_reg_IV); state_add(HPHYBRID_PA, "PA", m_reg_PA[ 0 ]); - state_add(HPHYBRID_W, "W", m_reg_W).noshow(); + state_add(HPHYBRID_W, "W", m_reg_W).noshow(); state_add(STATE_GENFLAGS, "GENFLAGS", m_flags).noshow().formatstr("%9s"); state_add(HPHYBRID_DMAPA , "DMAPA" , m_dmapa).noshow(); state_add(HPHYBRID_DMAMA , "DMAMA" , m_dmama).noshow(); @@ -170,17 +170,17 @@ void hp_hybrid_cpu_device::device_start() save_item(NAME(m_reg_PA[0])); save_item(NAME(m_reg_PA[1])); save_item(NAME(m_reg_PA[2])); - save_item(NAME(m_reg_W)); + save_item(NAME(m_reg_W)); save_item(NAME(m_flags)); save_item(NAME(m_dmapa)); save_item(NAME(m_dmama)); save_item(NAME(m_dmac)); save_item(NAME(m_reg_I)); - save_item(NAME(m_forced_bsc_25)); + save_item(NAME(m_forced_bsc_25)); m_icountptr = &m_icount; - m_pa_changed_func.resolve_safe(); + m_pa_changed_func.resolve_safe(); } void hp_hybrid_cpu_device::device_reset() @@ -506,11 +506,11 @@ UINT16 hp_hybrid_cpu_device::execute_one_sub(UINT16 opcode) if (BIT(m_flags , HPHYBRID_IRH_SVC_BIT)) { BIT_CLR(m_flags , HPHYBRID_IRH_SVC_BIT); memmove(&m_reg_PA[ 0 ] , &m_reg_PA[ 1 ] , HPHYBRID_INT_LVLS); - m_pa_changed_func((UINT8)CURRENT_PA); + m_pa_changed_func((UINT8)CURRENT_PA); } else if (BIT(m_flags , HPHYBRID_IRL_SVC_BIT)) { BIT_CLR(m_flags , HPHYBRID_IRL_SVC_BIT); memmove(&m_reg_PA[ 0 ] , &m_reg_PA[ 1 ] , HPHYBRID_INT_LVLS); - m_pa_changed_func((UINT8)CURRENT_PA); + m_pa_changed_func((UINT8)CURRENT_PA); } } tmp = RM(AEC_CASE_C , m_reg_R--) + (opcode & 0x1f); @@ -604,14 +604,14 @@ UINT16 hp_hybrid_cpu_device::execute_one_sub(UINT16 opcode) break; default: - // Unrecognized instruction: pass it on for further processing (by EMC if present) - return execute_no_bpc_ioc(opcode); - } - } - } - } - } - } + // Unrecognized instruction: pass it on for further processing (by EMC if present) + return execute_no_bpc_ioc(opcode); + } + } + } + } + } + } return m_reg_P + 1; } @@ -635,204 +635,204 @@ offs_t hp_hybrid_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const U UINT16 hp_hybrid_cpu_device::remove_mae(UINT32 addr) { - return (UINT16)(addr & 0xffff); + return (UINT16)(addr & 0xffff); } UINT16 hp_hybrid_cpu_device::RM(aec_cases_t aec_case , UINT16 addr) { - return RM(add_mae(aec_case , addr)); + return RM(add_mae(aec_case , addr)); } UINT16 hp_hybrid_cpu_device::RM(UINT32 addr) { - UINT16 tmp; - UINT16 addr_wo_bsc = remove_mae(addr); - - if (addr_wo_bsc <= HP_REG_LAST_ADDR) { - // Any access to internal registers removes forcing of BSC 2x - m_forced_bsc_25 = false; - - // Memory mapped registers that are present in both 3001 & 3011 - switch (addr_wo_bsc) { - case HP_REG_A_ADDR: - return m_reg_A; - - case HP_REG_B_ADDR: - return m_reg_B; - - case HP_REG_P_ADDR: - return m_reg_P; - - case HP_REG_R_ADDR: - return m_reg_R; - - case HP_REG_R4_ADDR: - case HP_REG_R5_ADDR: - case HP_REG_R6_ADDR: - case HP_REG_R7_ADDR: - return RIO(CURRENT_PA , addr_wo_bsc - HP_REG_R4_ADDR); - - case HP_REG_IV_ADDR: - // Correct? - if (!BIT(m_flags , HPHYBRID_IRH_SVC_BIT) && !BIT(m_flags , HPHYBRID_IRL_SVC_BIT)) { - return m_reg_IV; - } else { - return m_reg_IV | CURRENT_PA; - } - - case HP_REG_PA_ADDR: - return CURRENT_PA; - - case HP_REG_W_ADDR: - return m_reg_W; - - case HP_REG_DMAPA_ADDR: - tmp = m_dmapa & HP_REG_PA_MASK; - if (BIT(m_flags , HPHYBRID_CB_BIT)) { - BIT_SET(tmp , 15); - } - if (BIT(m_flags , HPHYBRID_DB_BIT)) { - BIT_SET(tmp , 14); - } - return tmp; - - case HP_REG_DMAMA_ADDR: - return m_dmama; - - case HP_REG_DMAC_ADDR: - return m_dmac; - - case HP_REG_C_ADDR: - return m_reg_C; - - case HP_REG_D_ADDR: - return m_reg_D; - - default: - return read_non_common_reg(addr_wo_bsc); - } - } else { - return m_direct->read_word(addr << 1); - } + UINT16 tmp; + UINT16 addr_wo_bsc = remove_mae(addr); + + if (addr_wo_bsc <= HP_REG_LAST_ADDR) { + // Any access to internal registers removes forcing of BSC 2x + m_forced_bsc_25 = false; + + // Memory mapped registers that are present in both 3001 & 3011 + switch (addr_wo_bsc) { + case HP_REG_A_ADDR: + return m_reg_A; + + case HP_REG_B_ADDR: + return m_reg_B; + + case HP_REG_P_ADDR: + return m_reg_P; + + case HP_REG_R_ADDR: + return m_reg_R; + + case HP_REG_R4_ADDR: + case HP_REG_R5_ADDR: + case HP_REG_R6_ADDR: + case HP_REG_R7_ADDR: + return RIO(CURRENT_PA , addr_wo_bsc - HP_REG_R4_ADDR); + + case HP_REG_IV_ADDR: + // Correct? + if (!BIT(m_flags , HPHYBRID_IRH_SVC_BIT) && !BIT(m_flags , HPHYBRID_IRL_SVC_BIT)) { + return m_reg_IV; + } else { + return m_reg_IV | CURRENT_PA; + } + + case HP_REG_PA_ADDR: + return CURRENT_PA; + + case HP_REG_W_ADDR: + return m_reg_W; + + case HP_REG_DMAPA_ADDR: + tmp = m_dmapa & HP_REG_PA_MASK; + if (BIT(m_flags , HPHYBRID_CB_BIT)) { + BIT_SET(tmp , 15); + } + if (BIT(m_flags , HPHYBRID_DB_BIT)) { + BIT_SET(tmp , 14); + } + return tmp; + + case HP_REG_DMAMA_ADDR: + return m_dmama; + + case HP_REG_DMAC_ADDR: + return m_dmac; + + case HP_REG_C_ADDR: + return m_reg_C; + + case HP_REG_D_ADDR: + return m_reg_D; + + default: + return read_non_common_reg(addr_wo_bsc); + } + } else { + return m_direct->read_word(addr << 1); + } } void hp_hybrid_cpu_device::WM(aec_cases_t aec_case , UINT16 addr , UINT16 v) { - WM(add_mae(aec_case , addr) , v); + WM(add_mae(aec_case , addr) , v); } void hp_hybrid_cpu_device::WM(UINT32 addr , UINT16 v) { - UINT16 addr_wo_bsc = remove_mae(addr); - - if (addr_wo_bsc <= HP_REG_LAST_ADDR) { - // Any access to internal registers removes forcing of BSC 2x - m_forced_bsc_25 = false; - - // Memory mapped registers - switch (addr_wo_bsc) { - case HP_REG_A_ADDR: - m_reg_A = v; - break; - - case HP_REG_B_ADDR: - m_reg_B = v; - break; - - case HP_REG_P_ADDR: - m_reg_P = v; - break; - - case HP_REG_R_ADDR: - m_reg_R = v; - break; - - case HP_REG_R4_ADDR: - case HP_REG_R5_ADDR: - case HP_REG_R6_ADDR: - case HP_REG_R7_ADDR: - WIO(CURRENT_PA , addr_wo_bsc - HP_REG_R4_ADDR , v); - break; - - case HP_REG_IV_ADDR: - m_reg_IV = v & HP_REG_IV_MASK; - break; - - case HP_REG_PA_ADDR: - CURRENT_PA = v & HP_REG_PA_MASK; - m_pa_changed_func((UINT8)CURRENT_PA); - break; - - case HP_REG_W_ADDR: - m_reg_W = v; - break; - - case HP_REG_DMAPA_ADDR: - m_dmapa = v & HP_REG_PA_MASK; - break; - - case HP_REG_DMAMA_ADDR: - m_dmama = v; - break; - - case HP_REG_DMAC_ADDR: - m_dmac = v; - break; - - case HP_REG_C_ADDR: - m_reg_C = v; - break; - - case HP_REG_D_ADDR: - m_reg_D = v; - break; - - default: - write_non_common_reg(addr_wo_bsc , v); - break; - } - } else { - m_program->write_word(addr << 1 , v); - } + UINT16 addr_wo_bsc = remove_mae(addr); + + if (addr_wo_bsc <= HP_REG_LAST_ADDR) { + // Any access to internal registers removes forcing of BSC 2x + m_forced_bsc_25 = false; + + // Memory mapped registers + switch (addr_wo_bsc) { + case HP_REG_A_ADDR: + m_reg_A = v; + break; + + case HP_REG_B_ADDR: + m_reg_B = v; + break; + + case HP_REG_P_ADDR: + m_reg_P = v; + break; + + case HP_REG_R_ADDR: + m_reg_R = v; + break; + + case HP_REG_R4_ADDR: + case HP_REG_R5_ADDR: + case HP_REG_R6_ADDR: + case HP_REG_R7_ADDR: + WIO(CURRENT_PA , addr_wo_bsc - HP_REG_R4_ADDR , v); + break; + + case HP_REG_IV_ADDR: + m_reg_IV = v & HP_REG_IV_MASK; + break; + + case HP_REG_PA_ADDR: + CURRENT_PA = v & HP_REG_PA_MASK; + m_pa_changed_func((UINT8)CURRENT_PA); + break; + + case HP_REG_W_ADDR: + m_reg_W = v; + break; + + case HP_REG_DMAPA_ADDR: + m_dmapa = v & HP_REG_PA_MASK; + break; + + case HP_REG_DMAMA_ADDR: + m_dmama = v; + break; + + case HP_REG_DMAC_ADDR: + m_dmac = v; + break; + + case HP_REG_C_ADDR: + m_reg_C = v; + break; + + case HP_REG_D_ADDR: + m_reg_D = v; + break; + + default: + write_non_common_reg(addr_wo_bsc , v); + break; + } + } else { + m_program->write_word(addr << 1 , v); + } } UINT16 hp_hybrid_cpu_device::fetch(void) { - m_genpc = add_mae(AEC_CASE_A , m_reg_P); - return RM(m_genpc); + m_genpc = add_mae(AEC_CASE_A , m_reg_P); + return RM(m_genpc); } UINT32 hp_hybrid_cpu_device::get_ea(UINT16 opcode) { - UINT16 base; - UINT16 off; - aec_cases_t aec; - - if (BIT(opcode , 10)) { - // Current page - base = m_reg_P; - aec = AEC_CASE_A; - } else { - // Base page - base = 0; - aec = AEC_CASE_B; - } - - off = opcode & 0x3ff; - if (off & 0x200) { - off -= 0x400; - } - - base += off; - - if (BIT(opcode , 15)) { - // Indirect addressing - m_icount -= 6; - return add_mae(AEC_CASE_C , RM(aec , base)); - } else { - // Direct addressing - return add_mae(aec , base); - } + UINT16 base; + UINT16 off; + aec_cases_t aec; + + if (BIT(opcode , 10)) { + // Current page + base = m_reg_P; + aec = AEC_CASE_A; + } else { + // Base page + base = 0; + aec = AEC_CASE_B; + } + + off = opcode & 0x3ff; + if (off & 0x200) { + off -= 0x400; + } + + base += off; + + if (BIT(opcode , 15)) { + // Indirect addressing + m_icount -= 6; + return add_mae(AEC_CASE_C , RM(aec , base)); + } else { + // Direct addressing + return add_mae(aec , base); + } } void hp_hybrid_cpu_device::do_add(UINT16& addend1 , UINT16 addend2) @@ -949,22 +949,22 @@ void hp_hybrid_cpu_device::do_pw(UINT16 opcode) if (m_flags & b_mask) { tmp_addr |= 0x10000; } - if (tmp_addr <= (HP_REG_LAST_ADDR * 2 + 1)) { - // Single bytes can be written to registers. - // The addressed register gets the written byte in the proper position - // and a 0 in the other byte because access to registers is always done in - // 16 bits units. - if (BIT(tmp_addr , 0)) { - tmp &= 0xff; - } else { - tmp <<= 8; - } - WM(tmp_addr >> 1 , tmp); - } else { - // Extend address, preserve LSB & form byte address - tmp_addr = (add_mae(AEC_CASE_C , tmp_addr >> 1) << 1) | (tmp_addr & 1); - m_program->write_byte(tmp_addr , (UINT8)tmp); - } + if (tmp_addr <= (HP_REG_LAST_ADDR * 2 + 1)) { + // Single bytes can be written to registers. + // The addressed register gets the written byte in the proper position + // and a 0 in the other byte because access to registers is always done in + // 16 bits units. + if (BIT(tmp_addr , 0)) { + tmp &= 0xff; + } else { + tmp <<= 8; + } + WM(tmp_addr >> 1 , tmp); + } else { + // Extend address, preserve LSB & form byte address + tmp_addr = (add_mae(AEC_CASE_C , tmp_addr >> 1) << 1) | (tmp_addr & 1); + m_program->write_byte(tmp_addr , (UINT8)tmp); + } } else { // Word WM(AEC_CASE_C , *ptr_reg , tmp); @@ -1013,7 +1013,7 @@ void hp_hybrid_cpu_device::check_for_interrupts(void) CURRENT_PA = new_PA; - m_pa_changed_func((UINT8)CURRENT_PA); + m_pa_changed_func((UINT8)CURRENT_PA); // Is this correct? Patent @ pg 210 suggests that the whole interrupt recognition sequence // lasts for 32 cycles (6 are already accounted for in get_ea for one indirection) @@ -1033,7 +1033,7 @@ void hp_hybrid_cpu_device::handle_dma(void) if (BIT(m_flags , HPHYBRID_DMADIR_BIT)) { // "Outward" DMA: memory -> peripheral - tmp = RM(AEC_CASE_D , m_dmama++); + tmp = RM(AEC_CASE_D , m_dmama++); WIO(m_dmapa , tc ? 2 : 0 , tmp); m_icount -= 10; } else { @@ -1062,545 +1062,544 @@ void hp_hybrid_cpu_device::WIO(UINT8 pa , UINT8 ic , UINT16 v) } hp_5061_3001_cpu_device::hp_5061_3001_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : hp_hybrid_cpu_device(mconfig, HP_5061_3001, "HP-5061-3001", tag, owner, clock, "5061-3001", 22), - m_boot_mode(false) + : hp_hybrid_cpu_device(mconfig, HP_5061_3001, "HP-5061-3001", tag, owner, clock, "5061-3001", 22), + m_boot_mode(false) { } void hp_5061_3001_cpu_device::device_start() { - hp_hybrid_cpu_device::device_start(); - - state_add(HPHYBRID_AR2, "Ar2" , m_reg_ar2[ 0 ]); - state_add(HPHYBRID_AR2_2, "Ar2_2" , m_reg_ar2[ 1 ]); - state_add(HPHYBRID_AR2_3, "Ar2_3" , m_reg_ar2[ 2 ]); - state_add(HPHYBRID_AR2_4, "Ar2_4" , m_reg_ar2[ 3 ]); - state_add(HPHYBRID_SE, "SE" , m_reg_se); - state_add(HPHYBRID_R25, "R25" , m_reg_r25).noshow(); - state_add(HPHYBRID_R26, "R26" , m_reg_r26).noshow(); - state_add(HPHYBRID_R27, "R27" , m_reg_r27).noshow(); - state_add(HPHYBRID_R32, "R32" , m_reg_aec[ 0 ]); - state_add(HPHYBRID_R33, "R33" , m_reg_aec[ 1 ]); - state_add(HPHYBRID_R34, "R34" , m_reg_aec[ 2 ]); - state_add(HPHYBRID_R35, "R35" , m_reg_aec[ 3 ]); - state_add(HPHYBRID_R36, "R36" , m_reg_aec[ 4 ]); - state_add(HPHYBRID_R37, "R37" , m_reg_aec[ 5 ]); - - save_item(NAME(m_reg_ar2[ 0 ])); - save_item(NAME(m_reg_ar2[ 1 ])); - save_item(NAME(m_reg_ar2[ 2 ])); - save_item(NAME(m_reg_ar2[ 3 ])); - save_item(NAME(m_reg_se)); - save_item(NAME(m_reg_r25)); - save_item(NAME(m_reg_r26)); - save_item(NAME(m_reg_r27)); - save_item(NAME(m_reg_aec[ 0 ])); - save_item(NAME(m_reg_aec[ 1 ])); - save_item(NAME(m_reg_aec[ 2 ])); - save_item(NAME(m_reg_aec[ 3 ])); - save_item(NAME(m_reg_aec[ 4 ])); - save_item(NAME(m_reg_aec[ 5 ])); + hp_hybrid_cpu_device::device_start(); + + state_add(HPHYBRID_AR2, "Ar2" , m_reg_ar2[ 0 ]); + state_add(HPHYBRID_AR2_2, "Ar2_2" , m_reg_ar2[ 1 ]); + state_add(HPHYBRID_AR2_3, "Ar2_3" , m_reg_ar2[ 2 ]); + state_add(HPHYBRID_AR2_4, "Ar2_4" , m_reg_ar2[ 3 ]); + state_add(HPHYBRID_SE, "SE" , m_reg_se); + state_add(HPHYBRID_R25, "R25" , m_reg_r25).noshow(); + state_add(HPHYBRID_R26, "R26" , m_reg_r26).noshow(); + state_add(HPHYBRID_R27, "R27" , m_reg_r27).noshow(); + state_add(HPHYBRID_R32, "R32" , m_reg_aec[ 0 ]); + state_add(HPHYBRID_R33, "R33" , m_reg_aec[ 1 ]); + state_add(HPHYBRID_R34, "R34" , m_reg_aec[ 2 ]); + state_add(HPHYBRID_R35, "R35" , m_reg_aec[ 3 ]); + state_add(HPHYBRID_R36, "R36" , m_reg_aec[ 4 ]); + state_add(HPHYBRID_R37, "R37" , m_reg_aec[ 5 ]); + + save_item(NAME(m_reg_ar2[ 0 ])); + save_item(NAME(m_reg_ar2[ 1 ])); + save_item(NAME(m_reg_ar2[ 2 ])); + save_item(NAME(m_reg_ar2[ 3 ])); + save_item(NAME(m_reg_se)); + save_item(NAME(m_reg_r25)); + save_item(NAME(m_reg_r26)); + save_item(NAME(m_reg_r27)); + save_item(NAME(m_reg_aec[ 0 ])); + save_item(NAME(m_reg_aec[ 1 ])); + save_item(NAME(m_reg_aec[ 2 ])); + save_item(NAME(m_reg_aec[ 3 ])); + save_item(NAME(m_reg_aec[ 4 ])); + save_item(NAME(m_reg_aec[ 5 ])); } void hp_5061_3001_cpu_device::device_reset() { - // Initial state of AEC registers: - // R32 0 - // R33 5 - // R34 0 - // R35 0 - // R36 0 - // R37 0 - m_reg_aec[ 0 ] = 0; - m_reg_aec[ 1 ] = 5; - m_reg_aec[ 2 ] = 0; - m_reg_aec[ 3 ] = 0; - m_reg_aec[ 4 ] = 0; - m_reg_aec[ 5 ] = 0; - - m_forced_bsc_25 = m_boot_mode; - - hp_hybrid_cpu_device::device_reset(); + // Initial state of AEC registers: + // R32 0 + // R33 5 + // R34 0 + // R35 0 + // R36 0 + // R37 0 + m_reg_aec[ 0 ] = 0; + m_reg_aec[ 1 ] = 5; + m_reg_aec[ 2 ] = 0; + m_reg_aec[ 3 ] = 0; + m_reg_aec[ 4 ] = 0; + m_reg_aec[ 5 ] = 0; + + m_forced_bsc_25 = m_boot_mode; + + hp_hybrid_cpu_device::device_reset(); } UINT8 hp_5061_3001_cpu_device::do_dec_shift_r(UINT8 d1 , UINT64& mantissa) { - UINT8 d12 = (UINT8)(mantissa & 0xf); + UINT8 d12 = (UINT8)(mantissa & 0xf); - mantissa = (mantissa >> 4) | ((UINT64)d1 << 44); + mantissa = (mantissa >> 4) | ((UINT64)d1 << 44); - return d12; + return d12; } UINT8 hp_5061_3001_cpu_device::do_dec_shift_l(UINT8 d12 , UINT64& mantissa) { - UINT8 d1 = (UINT8)((mantissa >> 44) & 0xf); + UINT8 d1 = (UINT8)((mantissa >> 44) & 0xf); - mantissa = (mantissa << 4) | ((UINT64)d12); - mantissa &= 0xffffffffffffULL; + mantissa = (mantissa << 4) | ((UINT64)d12); + mantissa &= 0xffffffffffffULL; - return d1; + return d1; } UINT64 hp_5061_3001_cpu_device::get_ar1(void) { - UINT32 addr; - UINT64 tmp; + UINT32 addr; + UINT64 tmp; - addr = add_mae(AEC_CASE_B , HP_REG_AR1_ADDR + 1); - tmp = (UINT64)RM(addr++); - tmp <<= 16; - tmp |= (UINT64)RM(addr++); - tmp <<= 16; - tmp |= (UINT64)RM(addr); + addr = add_mae(AEC_CASE_B , HP_REG_AR1_ADDR + 1); + tmp = (UINT64)RM(addr++); + tmp <<= 16; + tmp |= (UINT64)RM(addr++); + tmp <<= 16; + tmp |= (UINT64)RM(addr); - return tmp; + return tmp; } void hp_5061_3001_cpu_device::set_ar1(UINT64 v) { - UINT32 addr; - - addr = add_mae(AEC_CASE_B , HP_REG_AR1_ADDR + 3); - WM(addr-- , (UINT16)(v & 0xffff)); - v >>= 16; - WM(addr-- , (UINT16)(v & 0xffff)); - v >>= 16; - WM(addr , (UINT16)(v & 0xffff)); + UINT32 addr; + + addr = add_mae(AEC_CASE_B , HP_REG_AR1_ADDR + 3); + WM(addr-- , (UINT16)(v & 0xffff)); + v >>= 16; + WM(addr-- , (UINT16)(v & 0xffff)); + v >>= 16; + WM(addr , (UINT16)(v & 0xffff)); } UINT64 hp_5061_3001_cpu_device::get_ar2(void) const { - UINT64 tmp; + UINT64 tmp; - tmp = (UINT64)m_reg_ar2[ 1 ]; - tmp <<= 16; - tmp |= (UINT64)m_reg_ar2[ 2 ]; - tmp <<= 16; - tmp |= (UINT64)m_reg_ar2[ 3 ]; + tmp = (UINT64)m_reg_ar2[ 1 ]; + tmp <<= 16; + tmp |= (UINT64)m_reg_ar2[ 2 ]; + tmp <<= 16; + tmp |= (UINT64)m_reg_ar2[ 3 ]; - return tmp; + return tmp; } void hp_5061_3001_cpu_device::set_ar2(UINT64 v) { - m_reg_ar2[ 3 ] = (UINT16)(v & 0xffff); - v >>= 16; - m_reg_ar2[ 2 ] = (UINT16)(v & 0xffff); - v >>= 16; - m_reg_ar2[ 1 ] = (UINT16)(v & 0xffff); + m_reg_ar2[ 3 ] = (UINT16)(v & 0xffff); + v >>= 16; + m_reg_ar2[ 2 ] = (UINT16)(v & 0xffff); + v >>= 16; + m_reg_ar2[ 1 ] = (UINT16)(v & 0xffff); } UINT64 hp_5061_3001_cpu_device::do_mrxy(UINT64 ar) { - UINT8 n; - - n = m_reg_B & 0xf; - m_reg_A &= 0xf; - m_reg_se = m_reg_A; - while (n--) { - m_reg_se = do_dec_shift_r(m_reg_A , ar); - m_reg_A = 0; - m_icount -= 4; - } - m_reg_A = m_reg_se; - BIT_CLR(m_flags , HPHYBRID_DC_BIT); - - return ar; + UINT8 n; + + n = m_reg_B & 0xf; + m_reg_A &= 0xf; + m_reg_se = m_reg_A; + while (n--) { + m_reg_se = do_dec_shift_r(m_reg_A , ar); + m_reg_A = 0; + m_icount -= 4; + } + m_reg_A = m_reg_se; + BIT_CLR(m_flags , HPHYBRID_DC_BIT); + + return ar; } bool hp_5061_3001_cpu_device::do_dec_add(bool carry_in , UINT64& a , UINT64 b) { - UINT64 tmp = 0; - unsigned i; - UINT8 digit_a , digit_b; + UINT64 tmp = 0; + unsigned i; + UINT8 digit_a , digit_b; - for (i = 0; i < 12; i++) { - digit_a = (UINT8)(a & 0xf); - digit_b = (UINT8)(b & 0xf); + for (i = 0; i < 12; i++) { + digit_a = (UINT8)(a & 0xf); + digit_b = (UINT8)(b & 0xf); - if (carry_in) { - digit_a++; - } + if (carry_in) { + digit_a++; + } - digit_a += digit_b; + digit_a += digit_b; - carry_in = digit_a >= 10; + carry_in = digit_a >= 10; - if (carry_in) { - digit_a = (digit_a - 10) & 0xf; - } + if (carry_in) { + digit_a = (digit_a - 10) & 0xf; + } - tmp |= (UINT64)digit_a << (4 * i); + tmp |= (UINT64)digit_a << (4 * i); - a >>= 4; - b >>= 4; - } + a >>= 4; + b >>= 4; + } - a = tmp; + a = tmp; - return carry_in; + return carry_in; } void hp_5061_3001_cpu_device::do_mpy(void) { - INT32 a = (INT16)m_reg_A; - INT32 b = (INT16)m_reg_B; - INT32 p = a * b; + INT32 a = (INT16)m_reg_A; + INT32 b = (INT16)m_reg_B; + INT32 p = a * b; - m_reg_A = (UINT16)(p & 0xffff); - m_reg_B = (UINT16)((p >> 16) & 0xffff); + m_reg_A = (UINT16)(p & 0xffff); + m_reg_B = (UINT16)((p >> 16) & 0xffff); - // Not entirely correct, timing depends on initial content of A register - m_icount -= 65; + // Not entirely correct, timing depends on initial content of A register + m_icount -= 65; } UINT16 hp_5061_3001_cpu_device::execute_no_bpc_ioc(UINT16 opcode) { - // EMC instructions - UINT8 n; - UINT16 tmp1; - UINT16 tmp2; - UINT64 tmp_ar; - UINT64 tmp_ar2; - bool carry; - - switch (opcode & 0xfff0) { - case 0x7300: - // XFR - tmp1 = m_reg_A; - tmp2 = m_reg_B; - n = (opcode & 0xf) + 1; - m_icount -= 21; - while (n--) { - m_icount -= 12; - WM(AEC_CASE_C , tmp2 , RM(AEC_CASE_C , tmp1)); - tmp1++; - tmp2++; - } - break; - - case 0x7380: - // CLR - tmp1 = m_reg_A; - n = (opcode & 0xf) + 1; - m_icount -= 16; - while (n--) { - m_icount -= 6; - WM(AEC_CASE_C , tmp1 , 0); - tmp1++; - } - break; - - default: - switch (opcode) { - case 0x7200: - // MWA - m_icount -= 28; - tmp_ar2 = get_ar2(); - carry = do_dec_add(BIT(m_flags , HPHYBRID_DC_BIT) , tmp_ar2 , m_reg_B); - set_ar2(tmp_ar2); - if (carry) { - BIT_SET(m_flags, HPHYBRID_DC_BIT); - } else { - BIT_CLR(m_flags, HPHYBRID_DC_BIT); - } - break; - - case 0x7220: - // CMY - m_icount -= 23; - tmp_ar2 = get_ar2(); - tmp_ar2 = 0x999999999999ULL - tmp_ar2; - do_dec_add(true , tmp_ar2 , 0); - set_ar2(tmp_ar2); - BIT_CLR(m_flags , HPHYBRID_DC_BIT); - break; - - case 0x7260: - // CMX - m_icount -= 59; - tmp_ar = get_ar1(); - tmp_ar = 0x999999999999ULL - tmp_ar; - do_dec_add(true , tmp_ar , 0); - set_ar1(tmp_ar); - BIT_CLR(m_flags , HPHYBRID_DC_BIT); - break; - - case 0x7280: - // FXA - m_icount -= 40; - tmp_ar2 = get_ar2(); - carry = do_dec_add(BIT(m_flags , HPHYBRID_DC_BIT) , tmp_ar2 , get_ar1()); - set_ar2(tmp_ar2); - if (carry) { - BIT_SET(m_flags, HPHYBRID_DC_BIT); - } else { - BIT_CLR(m_flags, HPHYBRID_DC_BIT); - } - break; - - case 0x7340: - // NRM - tmp_ar2 = get_ar2(); - m_icount -= 23; - for (n = 0; n < 12 && (tmp_ar2 & 0xf00000000000ULL) == 0; n++) { - do_dec_shift_l(0 , tmp_ar2); - m_icount--; - } - m_reg_B = n; - if (n < 12) { - BIT_CLR(m_flags , HPHYBRID_DC_BIT); - set_ar2(tmp_ar2); - } else { - BIT_SET(m_flags , HPHYBRID_DC_BIT); - // When ar2 is 0, total time is 69 cycles - // (salcazzo che cosa fa per altri 34 cicli) - m_icount -= 34; - } - break; - - case 0x73c0: - // CDC - m_icount -= 11; - BIT_CLR(m_flags , HPHYBRID_DC_BIT); - break; - - case 0x7a00: - // FMP - m_icount -= 42; - m_reg_A = 0; - tmp_ar = get_ar1(); - tmp_ar2 = get_ar2(); - for (n = m_reg_B & 0xf; n > 0; n--) { - m_icount -= 13; - if (do_dec_add(BIT(m_flags , HPHYBRID_DC_BIT) , tmp_ar2 , tmp_ar)) { - m_reg_A++; - } - BIT_CLR(m_flags , HPHYBRID_DC_BIT); - } - set_ar2(tmp_ar2); - break; - - case 0x7a21: - // FDV - // No doc mentions any limit on the iterations done by this instruction. - // Here we stop at 15 (after all there are only 4 bits in the loop counter). But is it correct? - m_icount -= 37; - m_reg_B = 0; - tmp_ar = get_ar1(); - tmp_ar2 = get_ar2(); - while (m_reg_B < 15 && !do_dec_add(BIT(m_flags , HPHYBRID_DC_BIT) , tmp_ar2 , tmp_ar)) { - m_icount -= 13; - BIT_CLR(m_flags , HPHYBRID_DC_BIT); - m_reg_B++; - } - set_ar2(tmp_ar2); - break; - - case 0x7b00: - // MRX - set_ar1(do_mrxy(get_ar1())); - m_icount -= 62; - break; - - case 0x7b21: - // DRS - tmp_ar = get_ar1(); - m_icount -= 56; - m_reg_A = m_reg_se = do_dec_shift_r(0 , tmp_ar); - set_ar1(tmp_ar); - BIT_CLR(m_flags , HPHYBRID_DC_BIT); - break; - - case 0x7b40: - // MRY - set_ar2(do_mrxy(get_ar2())); - m_icount -= 33; - break; - - case 0x7b61: - // MLY - tmp_ar2 = get_ar2(); - m_icount -= 32; - m_reg_A = m_reg_se = do_dec_shift_l(m_reg_A & 0xf , tmp_ar2); - set_ar2(tmp_ar2); - BIT_CLR(m_flags , HPHYBRID_DC_BIT); - break; - - case 0x7b8f: - // MPY - do_mpy(); - break; - - default: - if ((opcode & 0xfec0) == 0x74c0) { - // SDS - // SDC - m_icount -= 14; - return get_skip_addr(opcode , !BIT(m_flags , HPHYBRID_DC_BIT)); - } else { - // Unrecognized instructions: NOP - // Execution time is fictional - logerror("hp-5061-3001: unknown opcode %04x @ %06x\n" , opcode , m_genpc); - m_icount -= 6; - } - break; - } - } - - return m_reg_P + 1; + // EMC instructions + UINT8 n; + UINT16 tmp1; + UINT16 tmp2; + UINT64 tmp_ar; + UINT64 tmp_ar2; + bool carry; + + switch (opcode & 0xfff0) { + case 0x7300: + // XFR + tmp1 = m_reg_A; + tmp2 = m_reg_B; + n = (opcode & 0xf) + 1; + m_icount -= 21; + while (n--) { + m_icount -= 12; + WM(AEC_CASE_C , tmp2 , RM(AEC_CASE_C , tmp1)); + tmp1++; + tmp2++; + } + break; + + case 0x7380: + // CLR + tmp1 = m_reg_A; + n = (opcode & 0xf) + 1; + m_icount -= 16; + while (n--) { + m_icount -= 6; + WM(AEC_CASE_C , tmp1 , 0); + tmp1++; + } + break; + + default: + switch (opcode) { + case 0x7200: + // MWA + m_icount -= 28; + tmp_ar2 = get_ar2(); + carry = do_dec_add(BIT(m_flags , HPHYBRID_DC_BIT) , tmp_ar2 , m_reg_B); + set_ar2(tmp_ar2); + if (carry) { + BIT_SET(m_flags, HPHYBRID_DC_BIT); + } else { + BIT_CLR(m_flags, HPHYBRID_DC_BIT); + } + break; + + case 0x7220: + // CMY + m_icount -= 23; + tmp_ar2 = get_ar2(); + tmp_ar2 = 0x999999999999ULL - tmp_ar2; + do_dec_add(true , tmp_ar2 , 0); + set_ar2(tmp_ar2); + BIT_CLR(m_flags , HPHYBRID_DC_BIT); + break; + + case 0x7260: + // CMX + m_icount -= 59; + tmp_ar = get_ar1(); + tmp_ar = 0x999999999999ULL - tmp_ar; + do_dec_add(true , tmp_ar , 0); + set_ar1(tmp_ar); + BIT_CLR(m_flags , HPHYBRID_DC_BIT); + break; + + case 0x7280: + // FXA + m_icount -= 40; + tmp_ar2 = get_ar2(); + carry = do_dec_add(BIT(m_flags , HPHYBRID_DC_BIT) , tmp_ar2 , get_ar1()); + set_ar2(tmp_ar2); + if (carry) { + BIT_SET(m_flags, HPHYBRID_DC_BIT); + } else { + BIT_CLR(m_flags, HPHYBRID_DC_BIT); + } + break; + + case 0x7340: + // NRM + tmp_ar2 = get_ar2(); + m_icount -= 23; + for (n = 0; n < 12 && (tmp_ar2 & 0xf00000000000ULL) == 0; n++) { + do_dec_shift_l(0 , tmp_ar2); + m_icount--; + } + m_reg_B = n; + if (n < 12) { + BIT_CLR(m_flags , HPHYBRID_DC_BIT); + set_ar2(tmp_ar2); + } else { + BIT_SET(m_flags , HPHYBRID_DC_BIT); + // When ar2 is 0, total time is 69 cycles + // (salcazzo che cosa fa per altri 34 cicli) + m_icount -= 34; + } + break; + + case 0x73c0: + // CDC + m_icount -= 11; + BIT_CLR(m_flags , HPHYBRID_DC_BIT); + break; + + case 0x7a00: + // FMP + m_icount -= 42; + m_reg_A = 0; + tmp_ar = get_ar1(); + tmp_ar2 = get_ar2(); + for (n = m_reg_B & 0xf; n > 0; n--) { + m_icount -= 13; + if (do_dec_add(BIT(m_flags , HPHYBRID_DC_BIT) , tmp_ar2 , tmp_ar)) { + m_reg_A++; + } + BIT_CLR(m_flags , HPHYBRID_DC_BIT); + } + set_ar2(tmp_ar2); + break; + + case 0x7a21: + // FDV + // No doc mentions any limit on the iterations done by this instruction. + // Here we stop at 15 (after all there are only 4 bits in the loop counter). But is it correct? + m_icount -= 37; + m_reg_B = 0; + tmp_ar = get_ar1(); + tmp_ar2 = get_ar2(); + while (m_reg_B < 15 && !do_dec_add(BIT(m_flags , HPHYBRID_DC_BIT) , tmp_ar2 , tmp_ar)) { + m_icount -= 13; + BIT_CLR(m_flags , HPHYBRID_DC_BIT); + m_reg_B++; + } + set_ar2(tmp_ar2); + break; + + case 0x7b00: + // MRX + set_ar1(do_mrxy(get_ar1())); + m_icount -= 62; + break; + + case 0x7b21: + // DRS + tmp_ar = get_ar1(); + m_icount -= 56; + m_reg_A = m_reg_se = do_dec_shift_r(0 , tmp_ar); + set_ar1(tmp_ar); + BIT_CLR(m_flags , HPHYBRID_DC_BIT); + break; + + case 0x7b40: + // MRY + set_ar2(do_mrxy(get_ar2())); + m_icount -= 33; + break; + + case 0x7b61: + // MLY + tmp_ar2 = get_ar2(); + m_icount -= 32; + m_reg_A = m_reg_se = do_dec_shift_l(m_reg_A & 0xf , tmp_ar2); + set_ar2(tmp_ar2); + BIT_CLR(m_flags , HPHYBRID_DC_BIT); + break; + + case 0x7b8f: + // MPY + do_mpy(); + break; + + default: + if ((opcode & 0xfec0) == 0x74c0) { + // SDS + // SDC + m_icount -= 14; + return get_skip_addr(opcode , !BIT(m_flags , HPHYBRID_DC_BIT)); + } else { + // Unrecognized instructions: NOP + // Execution time is fictional + logerror("hp-5061-3001: unknown opcode %04x @ %06x\n" , opcode , m_genpc); + m_icount -= 6; + } + break; + } + } + + return m_reg_P + 1; } offs_t hp_5061_3001_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { - extern CPU_DISASSEMBLE(hp_5061_3001); - return CPU_DISASSEMBLE_NAME(hp_5061_3001)(this, buffer, pc, oprom, opram, options); + extern CPU_DISASSEMBLE(hp_5061_3001); + return CPU_DISASSEMBLE_NAME(hp_5061_3001)(this, buffer, pc, oprom, opram, options); } UINT32 hp_5061_3001_cpu_device::add_mae(aec_cases_t aec_case , UINT16 addr) { - UINT16 bsc_reg; - bool top_half = BIT(addr , 15) != 0; + UINT16 bsc_reg; + bool top_half = BIT(addr , 15) != 0; - // Detect accesses to top half of base page - if (aec_case == AEC_CASE_C && (addr & 0xfe00) == 0xfe00) { - aec_case = AEC_CASE_B; - } + // Detect accesses to top half of base page + if (aec_case == AEC_CASE_C && (addr & 0xfe00) == 0xfe00) { + aec_case = AEC_CASE_B; + } - switch (aec_case) { - case AEC_CASE_A: - bsc_reg = top_half ? HP_REG_R34_ADDR : HP_REG_R33_ADDR; - break; + switch (aec_case) { + case AEC_CASE_A: + bsc_reg = top_half ? HP_REG_R34_ADDR : HP_REG_R33_ADDR; + break; - case AEC_CASE_B: - bsc_reg = top_half ? HP_REG_R36_ADDR : HP_REG_R33_ADDR; - break; + case AEC_CASE_B: + bsc_reg = top_half ? HP_REG_R36_ADDR : HP_REG_R33_ADDR; + break; - case AEC_CASE_C: - bsc_reg = top_half ? HP_REG_R32_ADDR : HP_REG_R35_ADDR; - break; + case AEC_CASE_C: + bsc_reg = top_half ? HP_REG_R32_ADDR : HP_REG_R35_ADDR; + break; - case AEC_CASE_D: - bsc_reg = HP_REG_R37_ADDR; - break; + case AEC_CASE_D: + bsc_reg = HP_REG_R37_ADDR; + break; - default: - logerror("hphybrid: aec_case=%d\n" , aec_case); - return 0; - } + default: + logerror("hphybrid: aec_case=%d\n" , aec_case); + return 0; + } - UINT16 aec_reg = m_reg_aec[ bsc_reg - HP_REG_R32_ADDR ] & BSC_REG_MASK; + UINT16 aec_reg = m_reg_aec[ bsc_reg - HP_REG_R32_ADDR ] & BSC_REG_MASK; - if (m_forced_bsc_25) { - aec_reg = (aec_reg & 0xf) | 0x20; - } + if (m_forced_bsc_25) { + aec_reg = (aec_reg & 0xf) | 0x20; + } - return (UINT32)addr | ((UINT32)aec_reg << 16); + return (UINT32)addr | ((UINT32)aec_reg << 16); } UINT16 hp_5061_3001_cpu_device::read_non_common_reg(UINT16 addr) { - switch (addr) { - case HP_REG_AR2_ADDR: - case HP_REG_AR2_ADDR + 1: - case HP_REG_AR2_ADDR + 2: - case HP_REG_AR2_ADDR + 3: - return m_reg_ar2[ addr - HP_REG_AR2_ADDR ]; - - case HP_REG_SE_ADDR: - return m_reg_se; - - case HP_REG_R25_ADDR: - return m_reg_r25; - - case HP_REG_R26_ADDR: - return m_reg_r26; - - case HP_REG_R27_ADDR: - return m_reg_r27; - - case HP_REG_R32_ADDR: - case HP_REG_R33_ADDR: - case HP_REG_R34_ADDR: - case HP_REG_R35_ADDR: - case HP_REG_R36_ADDR: - case HP_REG_R37_ADDR: - return m_reg_aec[ addr - HP_REG_R32_ADDR ]; - - default: - return 0; - } + switch (addr) { + case HP_REG_AR2_ADDR: + case HP_REG_AR2_ADDR + 1: + case HP_REG_AR2_ADDR + 2: + case HP_REG_AR2_ADDR + 3: + return m_reg_ar2[ addr - HP_REG_AR2_ADDR ]; + + case HP_REG_SE_ADDR: + return m_reg_se; + + case HP_REG_R25_ADDR: + return m_reg_r25; + + case HP_REG_R26_ADDR: + return m_reg_r26; + + case HP_REG_R27_ADDR: + return m_reg_r27; + + case HP_REG_R32_ADDR: + case HP_REG_R33_ADDR: + case HP_REG_R34_ADDR: + case HP_REG_R35_ADDR: + case HP_REG_R36_ADDR: + case HP_REG_R37_ADDR: + return m_reg_aec[ addr - HP_REG_R32_ADDR ]; + + default: + return 0; + } } void hp_5061_3001_cpu_device::write_non_common_reg(UINT16 addr , UINT16 v) { - switch (addr) { - case HP_REG_AR2_ADDR: - case HP_REG_AR2_ADDR + 1: - case HP_REG_AR2_ADDR + 2: - case HP_REG_AR2_ADDR + 3: - m_reg_ar2[ addr - HP_REG_AR2_ADDR ] = v; - break; - - case HP_REG_SE_ADDR: - m_reg_se = v & HP_REG_SE_MASK; - break; - - case HP_REG_R25_ADDR: - m_reg_r25 = v; - break; - - case HP_REG_R26_ADDR: - m_reg_r26 = v; - break; - - case HP_REG_R27_ADDR: - m_reg_r27 = v; - break; - - case HP_REG_R32_ADDR: - case HP_REG_R33_ADDR: - case HP_REG_R34_ADDR: - case HP_REG_R35_ADDR: - case HP_REG_R36_ADDR: - case HP_REG_R37_ADDR: - m_reg_aec[ addr - HP_REG_R32_ADDR ] = v; - break; - - default: - break; - } + switch (addr) { + case HP_REG_AR2_ADDR: + case HP_REG_AR2_ADDR + 1: + case HP_REG_AR2_ADDR + 2: + case HP_REG_AR2_ADDR + 3: + m_reg_ar2[ addr - HP_REG_AR2_ADDR ] = v; + break; + + case HP_REG_SE_ADDR: + m_reg_se = v & HP_REG_SE_MASK; + break; + + case HP_REG_R25_ADDR: + m_reg_r25 = v; + break; + + case HP_REG_R26_ADDR: + m_reg_r26 = v; + break; + + case HP_REG_R27_ADDR: + m_reg_r27 = v; + break; + + case HP_REG_R32_ADDR: + case HP_REG_R33_ADDR: + case HP_REG_R34_ADDR: + case HP_REG_R35_ADDR: + case HP_REG_R36_ADDR: + case HP_REG_R37_ADDR: + m_reg_aec[ addr - HP_REG_R32_ADDR ] = v; + break; + + default: + break; + } } hp_5061_3011_cpu_device::hp_5061_3011_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : hp_hybrid_cpu_device(mconfig, HP_5061_3011, "HP-5061-3011", tag, owner, clock, "5061-3011", 16) + : hp_hybrid_cpu_device(mconfig, HP_5061_3011, "HP-5061-3011", tag, owner, clock, "5061-3011", 16) { } UINT16 hp_5061_3011_cpu_device::execute_no_bpc_ioc(UINT16 opcode) { - // Unrecognized instructions: NOP - // Execution time is fictional - m_icount -= 6; + // Unrecognized instructions: NOP + // Execution time is fictional + m_icount -= 6; - return m_reg_P + 1; + return m_reg_P + 1; } UINT32 hp_5061_3011_cpu_device::add_mae(aec_cases_t aec_case , UINT16 addr) { - // No MAE on 3011 - return addr; + // No MAE on 3011 + return addr; } UINT16 hp_5061_3011_cpu_device::read_non_common_reg(UINT16 addr) { - // Non-existing registers are returned as 0 - return 0; + // Non-existing registers are returned as 0 + return 0; } void hp_5061_3011_cpu_device::write_non_common_reg(UINT16 addr , UINT16 v) { - // Non-existing registers are silently discarded + // Non-existing registers are silently discarded } - |