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author Vas Crabb <vas@vastheman.com>2018-10-28 00:44:20 +1100
committer Vas Crabb <vas@vastheman.com>2018-10-28 00:44:20 +1100
commite4862a24a3e8a6e0bcfa9e43f1aa856a1c6ce1aa (patch)
tree3cdb1dd239dac2c794a915ca7347b3984e404244 /src
parent5fb58cf848d7fe13f4aeb86ea76e69d7d97360ed (diff)
misc cleanup (nw)
Diffstat (limited to 'src')
-rw-r--r--src/devices/cpu/m68000/m68kdasm.cpp9
-rw-r--r--src/devices/cpu/m68000/m68kmmu.h43
-rw-r--r--src/devices/machine/msm58321.cpp11
-rw-r--r--src/devices/machine/scc2698b.cpp186
-rw-r--r--src/devices/machine/scc2698b.h95
-rw-r--r--src/devices/machine/smioc.cpp104
-rw-r--r--src/devices/machine/smioc.h2
-rw-r--r--src/devices/machine/tms9914.cpp31
-rw-r--r--src/devices/sound/pokey.cpp44
-rw-r--r--src/emu/dirtc.cpp4
-rw-r--r--src/emu/emuopts.cpp2
-rw-r--r--src/mame/drivers/crystal.cpp25
-rw-r--r--src/mame/drivers/r9751.cpp7
-rw-r--r--src/mame/drivers/toypop.cpp87
14 files changed, 266 insertions, 384 deletions
diff --git a/src/devices/cpu/m68000/m68kdasm.cpp b/src/devices/cpu/m68000/m68kdasm.cpp
index 78d240ad737..a61acff8631 100644
--- a/src/devices/cpu/m68000/m68kdasm.cpp
+++ b/src/devices/cpu/m68000/m68kdasm.cpp
@@ -53,7 +53,8 @@ std::string m68k_disassembler::make_signed_hex_str_32(u32 val)
std::string m68k_disassembler::get_imm_str_s(u32 size)
{
- switch(size) {
+ switch(size)
+ {
case 0: return util::string_format("#%s", make_signed_hex_str_8(read_imm_8()));
case 1: return util::string_format("#%s", make_signed_hex_str_16(read_imm_16()));
case 2: return util::string_format("#%s", make_signed_hex_str_32(read_imm_32()));
@@ -63,7 +64,8 @@ std::string m68k_disassembler::get_imm_str_s(u32 size)
std::string m68k_disassembler::get_imm_str_u(u32 size)
{
- switch(size) {
+ switch(size)
+ {
case 0: return util::string_format("#$%x", read_imm_8());
case 1: return util::string_format("#$%x", read_imm_16());
case 2: return util::string_format("#$%x", read_imm_32());
@@ -2996,7 +2998,8 @@ std::string m68k_disassembler::d68851_p000()
if ((modes & 0xe000) == 0x8000) // PTEST
{
- if (modes & 0x100) {
+ if (modes & 0x100)
+ {
return util::string_format("ptest%c %s, %s, %d, @A%d",
(modes & 0x200) ? 'r' : 'w',
fc_to_string(modes),
diff --git a/src/devices/cpu/m68000/m68kmmu.h b/src/devices/cpu/m68000/m68kmmu.h
index 5abd2b8f29e..a8a415501af 100644
--- a/src/devices/cpu/m68000/m68kmmu.h
+++ b/src/devices/cpu/m68000/m68kmmu.h
@@ -130,7 +130,7 @@ void pmmu_atc_add(uint32_t logical, uint32_t physical, int fc)
// get page size (i.e. # of bits to ignore); is 10 for Apollo
int ps = (m_mmu_tc >> 20) & 0xf;
// Note: exact emulation would use (logical >> ps) << (ps-8)
- uint32_t atc_tag = M68K_MMU_ATC_VALID | ((fc &7) << 24)| logical >> ps;
+ uint32_t atc_tag = M68K_MMU_ATC_VALID | ((fc & 7) << 24)| logical >> ps;
// first see if this is already in the cache
for (i = 0; i < MMU_ATC_ENTRIES; i++)
@@ -165,9 +165,9 @@ void pmmu_atc_add(uint32_t logical, uint32_t physical, int fc)
}
// add the entry
- MMULOG("ATC[%2d] add: log %08x -> phys %08x (fc=%d)\n", found, (logical>>ps) << ps, (physical >> ps) << ps, fc);
+ MMULOG("ATC[%2d] add: log %08x -> phys %08x (fc=%d)\n", found, (logical >> ps) << ps, (physical >> ps) << ps, fc);
m_mmu_atc_tag[found] = atc_tag;
- m_mmu_atc_data[found] = (physical >> ps) << (ps-8);
+ m_mmu_atc_data[found] = (physical >> ps) << (ps - 8);
if (m_mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT)
{
@@ -248,7 +248,8 @@ bool pmmu_atc_lookup(const uint32_t addr_in, const int fc,
const int ps = (m_mmu_tc >> 20) & 0xf;
const uint32_t atc_tag = M68K_MMU_ATC_VALID | ((fc & 7) << 24) | (addr_in >> ps);
- for (int i = 0; i < MMU_ATC_ENTRIES; i++) {
+ for (int i = 0; i < MMU_ATC_ENTRIES; i++)
+ {
if (m_mmu_atc_tag[i] != atc_tag)
continue;
@@ -258,10 +259,13 @@ bool pmmu_atc_lookup(const uint32_t addr_in, const int fc,
continue;
// read access or write access and not write protected
- if (!ptest) {
+ if (!ptest)
+ {
// FIXME: must set modified in PMMU tables as well
m_mmu_atc_data[i] |= (!m_mmu_tmp_rw ? M68K_MMU_ATC_MODIFIED : 0);
- } else {
+ }
+ else
+ {
uint16_t sr = 0;
if (m_mmu_atc_data[i] & M68K_MMU_ATC_MODIFIED)
@@ -441,14 +445,14 @@ uint32_t pmmu_translate_addr_with_fc_040(uint32_t addr_in, uint8_t fc, uint8_t p
}
else
{
- fatalerror("68040: function code %d is neither data nor program!\n", fc&7);
+ fatalerror("68040: function code %d is neither data nor program!\n", fc & 7);
}
if (tt0 & 0x8000)
{
- static int fcmask[4] = { 4, 4, 0, 0 };
- static int fcmatch[4] = { 0, 4, 0, 0 };
- uint32_t mask = (tt0>>16) & 0xff;
+ static constexpr int fcmask[4] = { 4, 4, 0, 0 };
+ static constexpr int fcmatch[4] = { 0, 4, 0, 0 };
+ uint32_t mask = (tt0 >> 16) & 0xff;
mask ^= 0xff;
mask <<= 24;
@@ -468,7 +472,7 @@ uint32_t pmmu_translate_addr_with_fc_040(uint32_t addr_in, uint8_t fc, uint8_t p
{
static int fcmask[4] = { 4, 4, 0, 0 };
static int fcmatch[4] = { 0, 4, 0, 0 };
- uint32_t mask = (tt1>>16) & 0xff;
+ uint32_t mask = (tt1 >> 16) & 0xff;
mask ^= 0xff;
mask <<= 24;
@@ -486,8 +490,8 @@ uint32_t pmmu_translate_addr_with_fc_040(uint32_t addr_in, uint8_t fc, uint8_t p
if (m_pmmu_enabled)
{
- uint32_t root_idx = (addr_in>>25) & 0x7f;
- uint32_t ptr_idx = (addr_in>>18) & 0x7f;
+ uint32_t root_idx = (addr_in >> 25) & 0x7f;
+ uint32_t ptr_idx = (addr_in >> 18) & 0x7f;
uint32_t page_idx, page;
uint32_t root_ptr, pointer_ptr, page_ptr;
uint32_t root_entry, pointer_entry, page_entry;
@@ -599,7 +603,7 @@ uint32_t pmmu_translate_addr_with_fc_040(uint32_t addr_in, uint8_t fc, uint8_t p
m_mmu_last_page_entry = page_entry;
// is the page write protected or supervisor protected?
- if ((((page_entry & 4) && !m_mmu_tmp_rw) || ((page_entry & 0x80) && !(fc&4))) && !ptest)
+ if ((((page_entry & 4) && !m_mmu_tmp_rw) || ((page_entry & 0x80) && !(fc & 4))) && !ptest)
{
pmmu_set_buserror(addr_in);
return addr_in;
@@ -678,7 +682,8 @@ uint32_t pmmu_translate_addr(uint32_t addr_in)
addr_out = pmmu_translate_addr_with_fc(addr_in, m_mmu_tmp_fc, 0);
}
-// if (m_mmu_tmp_buserror_occurred > 0) {
+// if (m_mmu_tmp_buserror_occurred > 0)
+// {
// MMULOG("PMMU: pc=%08x sp=%08x va=%08x pa=%08x - invalid Table mode for level=%d (buserror %d)\n",
// m_ppc, REG_A()[7], addr_in, addr_out, m_mmu_tmp_sr & M68K_MMU_SR_LEVEL_3,
// m_mmu_tmp_buserror_occurred);
@@ -908,7 +913,7 @@ void m68851_pmove_put(uint32_t ea, uint16_t modes)
void m68851_pmove(uint32_t ea, uint16_t modes)
{
- switch ((modes>>13) & 0x7)
+ switch ((modes >> 13) & 0x7)
{
case 0: // MC68030/040 form with FD bit
case 2: // MC68851 form, FD never set
@@ -934,7 +939,7 @@ void m68851_pmove(uint32_t ea, uint16_t modes)
break;
default:
- logerror("680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes>>13) & 0x7, modes, m_pc);
+ logerror("680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes >> 13) & 0x7, modes, m_pc);
break;
}
@@ -964,7 +969,7 @@ void m68851_mmu_ops()
}
else // the rest are 1111000xxxXXXXXX where xxx is the instruction family
{
- switch ((m_ir>>9) & 0x7)
+ switch ((m_ir >> 9) & 0x7)
{
case 0:
modes = OPER_I_16();
@@ -1006,7 +1011,7 @@ void m68851_mmu_ops()
break;
default:
- logerror("680x0: unknown PMMU instruction group %d\n", (m_ir>>9) & 0x7);
+ logerror("680x0: unknown PMMU instruction group %d\n", (m_ir >> 9) & 0x7);
break;
}
}
diff --git a/src/devices/machine/msm58321.cpp b/src/devices/machine/msm58321.cpp
index 550645b5255..2dc268d8bc1 100644
--- a/src/devices/machine/msm58321.cpp
+++ b/src/devices/machine/msm58321.cpp
@@ -129,7 +129,8 @@ inline void msm58321_device::write_counter(int address, int data)
{
int flag = 0;
- switch (address) {
+ switch (address)
+ {
case REGISTER_H1:
flag = m_reg[REGISTER_H10] & H10_24;
if (!flag)
@@ -160,8 +161,8 @@ inline void msm58321_device::write_counter(int address, int data)
// msm58321_device - constructor
//-------------------------------------------------
-msm58321_device::msm58321_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : device_t(mconfig, MSM58321, tag, owner, clock),
+msm58321_device::msm58321_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
+ device_t(mconfig, MSM58321, tag, owner, clock),
device_rtc_interface(mconfig, *this),
device_nvram_interface(mconfig, *this),
m_year0(0),
@@ -254,7 +255,9 @@ void msm58321_device::device_timer(emu_timer &timer, device_timer_id id, int par
{
m_reg[REGISTER_REF0] |= 1;
m_reg[REGISTER_REF1] |= 1;
- } else {
+ }
+ else
+ {
m_reg[REGISTER_REF0] &= ~1;
m_reg[REGISTER_REF1] &= ~1;
}
diff --git a/src/devices/machine/scc2698b.cpp b/src/devices/machine/scc2698b.cpp
index fce6ada6a66..1f6c537f52d 100644
--- a/src/devices/machine/scc2698b.cpp
+++ b/src/devices/machine/scc2698b.cpp
@@ -2,23 +2,23 @@
// copyright-holders:Brandon Munger, Stephen Stair
/*********************************************************************
- scc2698b.cpp
+ scc2698b.cpp
- Enhanced Octal Universal Asynchronous Receiver/Transmitter
+ Enhanced Octal Universal Asynchronous Receiver/Transmitter
Notes:
- This device is similiar to four 2681 DUART chips tied together
- in a single package, with some shared resources.
- The 2681 DUART is implemented in scn2681_device - but this
- chip is being independently emulated seperately for mainly
- educational purposes. When functionality for this device is
- completed we will consider merging the devices if it's
- practical.
+ This device is similiar to four 2681 DUART chips tied together
+ in a single package, with some shared resources.
+ The 2681 DUART is implemented in scn2681_device - but this
+ chip is being independently emulated seperately for mainly
+ educational purposes. When functionality for this device is
+ completed we will consider merging the devices if it's
+ practical.
Quirks:
- * Reading the RX Holding register will advance the HW FIFO even if
- there is no data to be read. This is not currently emulated but
- might be interesting to characterize in HW and emulate properly.
+ * Reading the RX Holding register will advance the HW FIFO even if
+ there is no data to be read. This is not currently emulated but
+ might be interesting to characterize in HW and emulate properly.
*********************************************************************/
@@ -26,24 +26,28 @@ Quirks:
#include "emu.h"
#include "scc2698b.h"
-DEFINE_DEVICE_TYPE(SCC2698B, scc2698b_device, "scc2698b", "SCC2698B Octal UART")
-DEFINE_DEVICE_TYPE(SCC2698B_CHANNEL, scc2698b_channel, "scc2698b_channel", "UART channel")
+#define LOG_GENERAL (1U << 0)
+#define LOG_CONFIG_CHANGE (1U << 1)
-#define TRACE_ENABLE 0
-#define TRACE_CONFIG_CHANGE 0
+//#define VERBOSE (LOG_GENERAL | LOG_CONFIG_CHANGE)
+#include "logmacro.h"
+#define TRACE_REGISTER_WRITE(ofs, data, reg_name) LOG("[0x%02X] << 0x%02X (%s)\n", (ofs), (data), (reg_name));
+#define TRACE_REGISTER_READ(ofs, data, reg_name) LOG("[0x%02X] >> 0x%02X (%s)\n", (ofs), (data), (reg_name));
+#define TRACE_CONFIG(...) LOGMASKED(LOG_CONFIG_CHANGE, __VA_ARGS__)
+
+
+DEFINE_DEVICE_TYPE(SCC2698B, scc2698b_device, "scc2698b", "SCC2698B Octal UART")
+DEFINE_DEVICE_TYPE(SCC2698B_CHANNEL, scc2698b_channel, "scc2698b_channel", "UART channel")
-#define TRACE_REGISTER_WRITE(ofs, data, reg_name) if(TRACE_ENABLE) { log_register_access((ofs), (data), "<<", (reg_name)); }
-#define TRACE_REGISTER_READ(ofs, data, reg_name) if(TRACE_ENABLE) { log_register_access((ofs), (data), ">>", (reg_name)); }
-#define TRACE_CONFIG if(TRACE_CONFIG_CHANGE) logerror
// Divider values for baud rate generation
// Expecting a crystal of 3.6864MHz, baud rate is crystal frequency / (divider value * 8)
-static const int BAUD_DIVIDER_ACR7_0[16] =
+static constexpr int BAUD_DIVIDER_ACR7_0[16] =
{
9216,4189,3426,2304,1536,768,384,439,192,96,64,48,12,0,0,0
};
-static const int BAUD_DIVIDER_ACR7_1[16] =
+static constexpr int BAUD_DIVIDER_ACR7_1[16] =
{
6144,4189,12,3072,1536,768,384,230,192,96,256,48,24,0,0,0
};
@@ -86,7 +90,7 @@ void scc2698b_channel::rcv_complete()
// Completed Byte Receive
receive_register_extract();
- if (rx_enable == false)
+ if (!rx_enable)
{
// Skip receive
return;
@@ -126,7 +130,7 @@ void scc2698b_channel::tra_callback()
void scc2698b_channel::write_TXH(int txh)
{
- if (tx_enable == false)
+ if (!tx_enable)
{
logerror("Warning: TX Holding byte ignored because transmitter is disabled.\n");
return;
@@ -206,7 +210,7 @@ void scc2698b_channel::set_tx_enable(bool enable)
}
void scc2698b_channel::set_rx_enable(bool enable)
{
- if (rx_enable == false && enable == true)
+ if (!rx_enable && enable)
{
receive_register_reset();
}
@@ -218,7 +222,7 @@ void scc2698b_channel::set_rx_enable(bool enable)
void scc2698b_channel::update_serial_configuration()
{
// void set_data_frame(int start_bit_count, int data_bit_count, parity_t parity, stop_bits_t stop_bits);
-
+
// Note: unimplemented RTS/CTS control, Error mode bit.
int start_bit_count = 1;
@@ -266,11 +270,10 @@ void scc2698b_channel::update_serial_configuration()
logerror("Warning: Unsupported channel mode selected.\n");
}
- const char* parity_strings[] = { "None", "Odd", "Even", "Mark", "Space" };
- const char* stop_bit_strings[] = { "0","1","1.5","2" };
+ static char const *const parity_strings[] = { "None", "Odd", "Even", "Mark", "Space" };
+ static char const *const stop_bit_strings[] = { "0","1","1.5","2" };
TRACE_CONFIG("Reconfigured channel to %d data bits, %s Parity, %s stop bits\n", data_bit_count, parity_strings[parity_mode], stop_bit_strings[stop_bits]);
-
set_data_frame(start_bit_count, data_bit_count, parity_mode, stop_bits);
}
@@ -324,13 +327,13 @@ void scc2698b_channel::recompute_pin_output(bool force)
if (new_mpp1 != mpp1_value || force)
{
- if (TRACE_ENABLE) logerror("Channel %d MPP1 => %d\n", channel_port, new_mpp1);
+ LOG("Channel %d MPP1 => %d\n", channel_port, new_mpp1);
parent->write_line_mpp1(channel_port, new_mpp1);
mpp1_value = new_mpp1;
}
if (new_mpp2 != mpp2_value || force)
{
- if(TRACE_ENABLE) logerror("Channel %d MPP2 => %d\n", channel_port, new_mpp2);
+ LOG("Channel %d MPP2 => %d\n", channel_port, new_mpp2);
parent->write_line_mpp2(channel_port, new_mpp2);
mpp2_value = new_mpp2;
}
@@ -356,10 +359,10 @@ scc2698b_device::scc2698b_device(const machine_config &mconfig, const char *tag,
write_intr_B(*this),
write_intr_C(*this),
write_intr_D(*this),
- write_a_tx(*this), write_b_tx(*this), write_c_tx(*this), write_d_tx(*this), write_e_tx(*this), write_f_tx(*this), write_g_tx(*this), write_h_tx(*this),
- write_a_mpp1(*this), write_b_mpp1(*this), write_c_mpp1(*this), write_d_mpp1(*this), write_e_mpp1(*this), write_f_mpp1(*this), write_g_mpp1(*this), write_h_mpp1(*this),
- write_a_mpp2(*this), write_b_mpp2(*this), write_c_mpp2(*this), write_d_mpp2(*this), write_e_mpp2(*this), write_f_mpp2(*this), write_g_mpp2(*this), write_h_mpp2(*this),
- write_a_mpo(*this), write_b_mpo(*this), write_c_mpo(*this), write_d_mpo(*this), write_e_mpo(*this), write_f_mpo(*this), write_g_mpo(*this), write_h_mpo(*this)
+ write_tx{ { *this }, { *this }, { *this }, { *this }, { *this }, { *this }, { *this }, { *this} },
+ write_mpp1{ { *this }, { *this }, { *this }, { *this }, { *this }, { *this }, { *this }, { *this } },
+ write_mpp2{ { *this }, { *this }, { *this }, { *this }, { *this }, { *this }, { *this }, { *this } },
+ write_mpo{ { *this }, { *this }, { *this }, { *this }, { *this }, { *this }, { *this }, { *this } }
{
@@ -380,38 +383,14 @@ void scc2698b_device::device_start()
write_intr_C.resolve_safe();
write_intr_D.resolve_safe();
- write_a_tx.resolve_safe();
- write_b_tx.resolve_safe();
- write_c_tx.resolve_safe();
- write_d_tx.resolve_safe();
- write_e_tx.resolve_safe();
- write_f_tx.resolve_safe();
- write_g_tx.resolve_safe();
- write_h_tx.resolve_safe();
- write_a_mpp1.resolve_safe();
- write_b_mpp1.resolve_safe();
- write_c_mpp1.resolve_safe();
- write_d_mpp1.resolve_safe();
- write_e_mpp1.resolve_safe();
- write_f_mpp1.resolve_safe();
- write_g_mpp1.resolve_safe();
- write_h_mpp1.resolve_safe();
- write_a_mpp2.resolve_safe();
- write_b_mpp2.resolve_safe();
- write_c_mpp2.resolve_safe();
- write_d_mpp2.resolve_safe();
- write_e_mpp2.resolve_safe();
- write_f_mpp2.resolve_safe();
- write_g_mpp2.resolve_safe();
- write_h_mpp2.resolve_safe();
- write_a_mpo.resolve_safe();
- write_b_mpo.resolve_safe();
- write_c_mpo.resolve_safe();
- write_d_mpo.resolve_safe();
- write_e_mpo.resolve_safe();
- write_f_mpo.resolve_safe();
- write_g_mpo.resolve_safe();
- write_h_mpo.resolve_safe();
+ for (auto &cb : write_tx)
+ cb.resolve_safe();
+ for (auto &cb : write_mpp1)
+ cb.resolve_safe();
+ for (auto &cb : write_mpp2)
+ cb.resolve_safe();
+ for (auto &cb : write_mpo)
+ cb.resolve_safe();
for (int i = 0; i < 8; i++)
{
@@ -430,64 +409,34 @@ void scc2698b_device::device_reset()
void scc2698b_device::write_line_tx(int port, int value)
{
- switch (port)
- {
- case 0: write_a_tx(value); break;
- case 1: write_b_tx(value); break;
- case 2: write_c_tx(value); break;
- case 3: write_d_tx(value); break;
- case 4: write_e_tx(value); break;
- case 5: write_f_tx(value); break;
- case 6: write_g_tx(value); break;
- case 7: write_h_tx(value); break;
- default: logerror("Unsupported port %d in write_line_tx\n", port);
- }
+ if ((0 <= port) && (ARRAY_LENGTH(write_tx) > port))
+ write_tx[port](value);
+ else
+ logerror("Unsupported port %d in write_line_tx\n", port);
}
+
void scc2698b_device::write_line_mpp1(int port, int value)
{
- switch (port)
- {
- case 0: write_a_mpp1(value); break;
- case 1: write_b_mpp1(value); break;
- case 2: write_c_mpp1(value); break;
- case 3: write_d_mpp1(value); break;
- case 4: write_e_mpp1(value); break;
- case 5: write_f_mpp1(value); break;
- case 6: write_g_mpp1(value); break;
- case 7: write_h_mpp1(value); break;
- default: logerror("Unsupported port %d in write_line_mpp1\n", port);
- }
+ if ((0 <= port) && (ARRAY_LENGTH(write_mpp1) > port))
+ write_mpp1[port](value);
+ else
+ logerror("Unsupported port %d in write_line_mpp1\n", port);
}
void scc2698b_device::write_line_mpp2(int port, int value)
{
- switch (port)
- {
- case 0: write_a_mpp2(value); break;
- case 1: write_b_mpp2(value); break;
- case 2: write_c_mpp2(value); break;
- case 3: write_d_mpp2(value); break;
- case 4: write_e_mpp2(value); break;
- case 5: write_f_mpp2(value); break;
- case 6: write_g_mpp2(value); break;
- case 7: write_h_mpp2(value); break;
- default: logerror("Unsupported port %d in write_line_mpp2\n", port);
- }
+ if ((0 <= port) && (ARRAY_LENGTH(write_mpp2) > port))
+ write_mpp2[port](value);
+ else
+ logerror("Unsupported port %d in write_line_mpp2\n", port);
}
+
void scc2698b_device::write_line_mpo(int port, int value)
{
- switch (port)
- {
- case 0: write_a_mpo(value); break;
- case 1: write_b_mpo(value); break;
- case 2: write_c_mpo(value); break;
- case 3: write_d_mpo(value); break;
- case 4: write_e_mpo(value); break;
- case 5: write_f_mpo(value); break;
- case 6: write_g_mpo(value); break;
- case 7: write_h_mpo(value); break;
- default: logerror("Unsupported port %d in write_line_mpo\n", port);
- }
+ if ((0 <= port) && (ARRAY_LENGTH(write_mpo) > port))
+ write_mpo[port](value);
+ else
+ logerror("Unsupported port %d in write_line_mpo\n", port);
}
@@ -502,13 +451,6 @@ WRITE8_MEMBER(scc2698b_device::write)
}
-void scc2698b_device::log_register_access(int offset, int value, const char* direction, const char* reg_name)
-{
- logerror("[0x%02X] %s 0x%02X (%s)\n", offset, direction, value, reg_name);
-}
-
-
-
uint8_t scc2698b_device::read_reg(int offset)
{
int device = (offset >> 4) & 3;
@@ -694,7 +636,7 @@ void scc2698b_device::write_MR(int port, int value)
void scc2698b_device::write_CSR(int port, int value)
{
scc2698b_channel* channel = get_channel(port);
-
+
channel->CSR = value;
update_port_baudrate(port);
}
diff --git a/src/devices/machine/scc2698b.h b/src/devices/machine/scc2698b.h
index da9ab7ad8b2..fe045aee1b6 100644
--- a/src/devices/machine/scc2698b.h
+++ b/src/devices/machine/scc2698b.h
@@ -1,20 +1,16 @@
// license:GPL-2.0+
// copyright-holders:Brandon Munger, Stephen Stair
-
-
#ifndef MAME_MACHINE_SCC2698B_H
#define MAME_MACHINE_SCC2698B_H
-class scc2698b_device;
-
#include "diserial.h"
-#define SCC2698B_RX_FIFO_SIZE 3
-
// _port should be a letter port index from "a" .. "h"
+class scc2698b_device;
+
class scc2698b_channel : public device_t, public device_serial_interface
{
friend class scc2698b_device;
@@ -49,10 +45,12 @@ public:
int read_SR();
protected:
+ static constexpr unsigned SCC2698B_RX_FIFO_SIZE = 3;
+
virtual void device_start() override;
virtual void device_reset() override;
-// devcb_write_line write_tx, write_mpp1, write_mpp2, write_mpo;
+// devcb_write_line write_tx, write_mpp1, write_mpp2, write_mpo;
int moderegister_ptr;
@@ -88,10 +86,10 @@ public:
void write_reg(int offset, uint8_t data);
uint8_t read_reg(int offset);
- template <class Object> devcb_base &set_intr_A(Object &&cb) { return write_intr_A.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_intr_B(Object &&cb) { return write_intr_B.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_intr_C(Object &&cb) { return write_intr_C.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_intr_D(Object &&cb) { return write_intr_D.set_callback(std::forward<Object>(cb)); }
+ auto intr_A() { return write_intr_A.bind(); }
+ auto intr_B() { return write_intr_B.bind(); }
+ auto intr_C() { return write_intr_C.bind(); }
+ auto intr_D() { return write_intr_D.bind(); }
required_device_array<scc2698b_channel, 8> m_channel;
@@ -110,66 +108,11 @@ public:
void write_line_mpp2(int port, int value);
void write_line_mpo(int port, int value);
-
- auto tx_callback(char port) {
- switch (port) {
- case 'a': return write_a_tx.bind();
- case 'b': return write_b_tx.bind();
- case 'c': return write_c_tx.bind();
- case 'd': return write_d_tx.bind();
- case 'e': return write_e_tx.bind();
- case 'f': return write_f_tx.bind();
- case 'g': return write_g_tx.bind();
- case 'h': return write_h_tx.bind();
- default:
- fatalerror("Wrong port for tx_callback\n");
- }
- }
-
- auto mpp1_callback(char port) {
- switch (port) {
- case 'a': return write_a_mpp1.bind();
- case 'b': return write_b_mpp1.bind();
- case 'c': return write_c_mpp1.bind();
- case 'd': return write_d_mpp1.bind();
- case 'e': return write_e_mpp1.bind();
- case 'f': return write_f_mpp1.bind();
- case 'g': return write_g_mpp1.bind();
- case 'h': return write_h_mpp1.bind();
- default:
- fatalerror("Wrong port for mpp1_callback\n");
- }
- }
-
- auto mpp2_callback(char port) {
- switch (port) {
- case 'a': return write_a_mpp2.bind();
- case 'b': return write_b_mpp2.bind();
- case 'c': return write_c_mpp2.bind();
- case 'd': return write_d_mpp2.bind();
- case 'e': return write_e_mpp2.bind();
- case 'f': return write_f_mpp2.bind();
- case 'g': return write_g_mpp2.bind();
- case 'h': return write_h_mpp2.bind();
- default:
- fatalerror("Wrong port for mpp2_callback\n");
- }
- }
-
- auto mpo_callback(char port) {
- switch (port) {
- case 'a': return write_a_mpo.bind();
- case 'b': return write_b_mpo.bind();
- case 'c': return write_c_mpo.bind();
- case 'd': return write_d_mpo.bind();
- case 'e': return write_e_mpo.bind();
- case 'f': return write_f_mpo.bind();
- case 'g': return write_g_mpo.bind();
- case 'h': return write_h_mpo.bind();
- default:
- fatalerror("Wrong port for mpo_callback\n");
- }
- }
+ // assume contiguous letters - not EBCDIC-friendly
+ template <char Port> auto tx_callback() { return write_tx[Port - 'a'].bind(); }
+ template <char Port> auto mpp1_callback() { return write_mpp1[Port - 'a'].bind(); }
+ template <char Port> auto mpp2_callback() { return write_mpp2[Port - 'a'].bind(); }
+ template <char Port> auto mpo_callback() { return write_mpo[Port - 'a'].bind(); }
protected:
virtual void device_start() override;
@@ -178,12 +121,10 @@ protected:
virtual void device_add_mconfig(machine_config &config) override;
devcb_write_line write_intr_A, write_intr_B, write_intr_C, write_intr_D;
- devcb_write_line write_a_tx, write_b_tx, write_c_tx, write_d_tx, write_e_tx, write_f_tx, write_g_tx, write_h_tx;
- devcb_write_line write_a_mpp1, write_b_mpp1, write_c_mpp1, write_d_mpp1, write_e_mpp1, write_f_mpp1, write_g_mpp1, write_h_mpp1;
- devcb_write_line write_a_mpp2, write_b_mpp2, write_c_mpp2, write_d_mpp2, write_e_mpp2, write_f_mpp2, write_g_mpp2, write_h_mpp2;
- devcb_write_line write_a_mpo, write_b_mpo, write_c_mpo, write_d_mpo, write_e_mpo, write_f_mpo, write_g_mpo, write_h_mpo;
-
- void log_register_access(int offset, int value, const char* direction, const char* reg_name);
+ devcb_write_line write_tx[8];
+ devcb_write_line write_mpp1[8];
+ devcb_write_line write_mpp2[8];
+ devcb_write_line write_mpo[8];
scc2698b_channel* get_channel(int port);
diff --git a/src/devices/machine/smioc.cpp b/src/devices/machine/smioc.cpp
index d3adea99393..dee1b7d751a 100644
--- a/src/devices/machine/smioc.cpp
+++ b/src/devices/machine/smioc.cpp
@@ -20,11 +20,11 @@
* CPU - Intel N80C188 L0450591 @ ??MHz - U23
* MCU - Signetics SC87C451CCA68 220CP079109KA 97D8641 - U70
* DMA - KS82C37A - U46, U47, U48, U49, U50
- * SCC - Signetics SCC2698BC1A84 - U67
+ * SCC - Signetics SCC2698BC1A84 - U67
* Memory - NEC D43256AGU-10LL 8948A9038 SRAM 32KB - U51
* Memory - Mitsubishi M5M187AJ 046101-35 SRAM 64K X 1?? - U37
- * Memory - AT&T M79018DX-15B 2K X 9 Dual Port SRAM - U53
- * Memory - AT&T M79018DX-15B 2K X 9 Dual Port SRAM - U54
+ * Memory - AT&T M79018DX-15B 2K X 9 Dual Port SRAM - U53
+ * Memory - AT&T M79018DX-15B 2K X 9 Dual Port SRAM - U54
Logic:
* U8 - 22V10-25JC
@@ -42,21 +42,21 @@
Program Memory:
* 0x00000 - 0x07FFF : SRAM D43256AGU-10LL 32KB
* 0xF8000 - 0xFFFFF : ROM 27C256 PLCC32 32KB
- * 0xC0080 - 0xC008F : KS82C37A - Probably RAM DMA
- * 0xC0090 - 0xC009F : KS82C37A - Serial DMA (Port 1 and 2?)
- * 0xC00A0 - 0xC00AF : KS82C37A - Serial DMA (Port 3 and 4?)
- * 0xC00B0 - 0xC00BF : KS82C37A - Serial DMA (Port 5 and 6?)
- * 0xC00C0 - 0xC00CF : KS82C37A - Serial DMA (Port 7 and 8?)
+ * 0xC0080 - 0xC008F : KS82C37A - Probably RAM DMA
+ * 0xC0090 - 0xC009F : KS82C37A - Serial DMA (Port 1 and 2?)
+ * 0xC00A0 - 0xC00AF : KS82C37A - Serial DMA (Port 3 and 4?)
+ * 0xC00B0 - 0xC00BF : KS82C37A - Serial DMA (Port 5 and 6?)
+ * 0xC00C0 - 0xC00CF : KS82C37A - Serial DMA (Port 7 and 8?)
IO Memory:
* Unknown
TODO:
- * Hook up System Monitor II to RS232 port 2
- * Dump 87C451 rom data and emulate MCU
- * Dump 87C51 on SMIOC interconnect box
- * Dump all PAL chips
- * Hook up status LEDs
+ * Hook up System Monitor II to RS232 port 2
+ * Dump 87C451 rom data and emulate MCU
+ * Dump 87C51 on SMIOC interconnect box
+ * Dump all PAL chips
+ * Hook up status LEDs
*/
#include "emu.h"
@@ -156,12 +156,12 @@ void smioc_device::device_add_mconfig(machine_config &config)
/* SCC2698B */
scc2698b_device &scc2698b(SCC2698B(config, "scc2698b", XTAL(3'686'400)));
- scc2698b.tx_callback('a').set("rs232_p1", FUNC(rs232_port_device::write_txd));
- scc2698b.mpp1_callback('a').set("dma8237_2", FUNC(am9517a_device::dreq1_w)).invert();
- scc2698b.mpp2_callback('a').set("dma8237_2", FUNC(am9517a_device::dreq0_w)).invert();
- scc2698b.tx_callback('b').set("rs232_p2", FUNC(rs232_port_device::write_txd));
- scc2698b.mpp1_callback('b').set("dma8237_2", FUNC(am9517a_device::dreq3_w)).invert();
- scc2698b.mpp2_callback('b').set("dma8237_2", FUNC(am9517a_device::dreq2_w)).invert();
+ scc2698b.tx_callback<'a'>().set("rs232_p1", FUNC(rs232_port_device::write_txd));
+ scc2698b.mpp1_callback<'a'>().set("dma8237_2", FUNC(am9517a_device::dreq1_w)).invert();
+ scc2698b.mpp1_callback<'a'>().set("dma8237_2", FUNC(am9517a_device::dreq0_w)).invert();
+ scc2698b.tx_callback<'b'>().set("rs232_p2", FUNC(rs232_port_device::write_txd));
+ scc2698b.mpp1_callback<'b'>().set("dma8237_2", FUNC(am9517a_device::dreq3_w)).invert();
+ scc2698b.mpp2_callback<'b'>().set("dma8237_2", FUNC(am9517a_device::dreq2_w)).invert();
/* The first dma8237 is set up in cascade mode, and each of its four channels provides HREQ/HACK to the other 4 DMA controllers*/
m_dma8237[0]->out_dack_callback<0>().set("dma8237_2", FUNC(am9517a_device::hack_w));
@@ -171,10 +171,10 @@ void smioc_device::device_add_mconfig(machine_config &config)
m_dma8237[0]->out_hreq_callback().set("dma8237_1", FUNC(am9517a_device::hack_w));
/* Connect base DMA controller's Hold Request to its own Hold ACK
- The CPU doesn't support hold request / hold ack pins, so we will pretend that the DMA controller immediately gets what it wants every time it asks.
- This will keep things moving forward, but the CPU will continue going through DMA requests rather than halting for a few cycles each time.
- It shouldn't cause a problem though.
- */
+ The CPU doesn't support hold request / hold ack pins, so we will pretend that the DMA controller immediately gets what it wants every time it asks.
+ This will keep things moving forward, but the CPU will continue going through DMA requests rather than halting for a few cycles each time.
+ It shouldn't cause a problem though.
+ */
m_dma8237[1]->in_memr_callback().set(FUNC(smioc_device::dma8237_2_dmaread));
m_dma8237[1]->out_memw_callback().set(FUNC(smioc_device::dma8237_2_dmawrite));
@@ -276,7 +276,7 @@ void smioc_device::SendCommand(u16 command)
m_commandValue = command;
m_requestFlags_11D |= 1;
m_deviceBusy = 1;
-
+
// Invalidate status if we hit a command.
m_status = 0;
m_statusvalid = false;
@@ -284,7 +284,7 @@ void smioc_device::SendCommand(u16 command)
m_smioccpu->int2_w(CLEAR_LINE);
m_smioccpu->int2_w(HOLD_LINE);
-
+
}
void smioc_device::SendCommand2(u16 command)
@@ -365,7 +365,7 @@ void smioc_device::SetDmaParameter(smioc_dma_parameter_t param, u16 value)
{
int address = DmaParameterAddress(param);
- const char* paramNames[] = { "smiocdma_sendaddress", "smiocdma_sendlength", "smiocdma_recvaddress", "smiocdma_recvlength" };
+ static char const *const paramNames[] = { "smiocdma_sendaddress", "smiocdma_sendlength", "smiocdma_recvaddress", "smiocdma_recvlength" };
const char* paramName = "?";
if (param >= 0 && param < (sizeof(paramNames) / sizeof(*paramNames)))
{
@@ -441,7 +441,7 @@ void smioc_device::update_and_log(u16& reg, u16 newValue, const char* register_n
READ8_MEMBER(smioc_device::ram2_mmio_r)
{
- const char * description = "";
+ const char *description = "";
u8 data = m_logic_ram[offset & 0xFFF];
switch (offset)
{
@@ -458,7 +458,7 @@ READ8_MEMBER(smioc_device::ram2_mmio_r)
case 0xB86: // Command parameter 2 - C011D Bit 7
description = "(Command Parameter 2)";
break;
- case 0xB87:
+ case 0xB87:
description = "(Command Parameter 2)";
break;
@@ -499,7 +499,7 @@ READ8_MEMBER(smioc_device::ram2_mmio_r)
WRITE8_MEMBER(smioc_device::ram2_mmio_w)
{
- const char * description = "";
+ const char *description = "";
m_logic_ram[offset & 0xFFF] = data;
@@ -590,34 +590,30 @@ READ8_MEMBER(smioc_device::boardlogic_mmio_r)
u8 data = 0xFF;
switch (offset)
{
+ case 0x19: // Hardware revision?
+ // Top bit controls which set of register locations in RAM2 are polled
+ data = 0x7F;
+ break;
- case 0x19: // Hardware revision?
- // Top bit controls which set of register locations in RAM2 are polled
- data = 0x7F;
- break;
-
- case 0x1D: // C011D (HW Request flags)
- data = m_requestFlags_11D;
- LOG_REGISTER_DETAILS("%s C011D Read => %02X\n", machine().time().as_string(), data);
- // Assume this is a clear-on-read register - It is read in one location and all set bits are acted on once it is read.
- m_requestFlags_11D = 0;
-
-
- break;
-
- case 0x1F: // C011F (HW Status flags?)
- // 0x80, 0x40 seem to be HW request to cancel ongoing DMA requests, maybe related to board reset?
- // 0x01 - When this is 0, advance some state perhaps related to talking to the 8051
- data = 0xFF;
- break;
+ case 0x1D: // C011D (HW Request flags)
+ data = m_requestFlags_11D;
+ LOG_REGISTER_DETAILS("%s C011D Read => %02X\n", machine().time().as_string(), data);
+ // Assume this is a clear-on-read register - It is read in one location and all set bits are acted on once it is read.
+ m_requestFlags_11D = 0;
+ break;
- case 0x80: // C0180 - Related to talking to the 87C451 chip interfacing to the breakout box
- data = 0x05; // Hack hack
- // We need the 8051 to provide a pair of bytes with 0x05 followed by a byte with the bottom bit set.
- // For now 0x05 should work to provide this condition, and might make the required status work.
- break;
+ case 0x1F: // C011F (HW Status flags?)
+ // 0x80, 0x40 seem to be HW request to cancel ongoing DMA requests, maybe related to board reset?
+ // 0x01 - When this is 0, advance some state perhaps related to talking to the 8051
+ data = 0xFF;
+ break;
+ case 0x80: // C0180 - Related to talking to the 87C451 chip interfacing to the breakout box
+ data = 0x05; // Hack hack
+ // We need the 8051 to provide a pair of bytes with 0x05 followed by a byte with the bottom bit set.
+ // For now 0x05 should work to provide this condition, and might make the required status work.
+ break;
}
LOG_REGISTER_ACCESS("logic[%04X] => %02X\n", offset, data);
return data;
@@ -627,7 +623,7 @@ WRITE8_MEMBER(smioc_device::boardlogic_mmio_w)
{
switch (offset)
{
- case 0x10: // C0110 (Clear interrupt? This seems to happen a lot but without being related to actually completing anything.)
+ case 0x10: // C0110 (Clear interrupt? This seems to happen a lot but without being related to actually completing anything.)
LOG_REGISTER_DETAILS("%s C0110 Write, DeviceBusy = %02X, RequestFlags = %02X\n", machine().time().as_string(), m_deviceBusy, m_requestFlags_11D);
m_deviceBusy = m_requestFlags_11D;
m_smioccpu->int2_w(CLEAR_LINE);
diff --git a/src/devices/machine/smioc.h b/src/devices/machine/smioc.h
index a756bbcc738..61cfbe88f62 100644
--- a/src/devices/machine/smioc.h
+++ b/src/devices/machine/smioc.h
@@ -124,7 +124,7 @@ private:
required_device<scc2698b_device> m_scc2698b;
required_shared_ptr<uint8_t> m_smioc_ram;
-
+
u8 m_logic_ram[4096]; // 4kb of ram in the 0x4xxxx window, mainly used by the board's logic to proxy command parameters and data.
void smioc_mem(address_map &map);
diff --git a/src/devices/machine/tms9914.cpp b/src/devices/machine/tms9914.cpp
index d2a90589e53..00fedd5db0c 100644
--- a/src/devices/machine/tms9914.cpp
+++ b/src/devices/machine/tms9914.cpp
@@ -20,15 +20,14 @@
#include "tms9914.h"
// Debugging
-#include "logmacro.h"
#define LOG_NOISY_MASK (LOG_GENERAL << 1)
#define LOG_NOISY(...) LOGMASKED(LOG_NOISY_MASK, __VA_ARGS__)
#define LOG_REG_MASK (LOG_NOISY_MASK << 1)
#define LOG_REG(...) LOGMASKED(LOG_REG_MASK, __VA_ARGS__)
#define LOG_INT_MASK (LOG_REG_MASK << 1)
#define LOG_INT(...) LOGMASKED(LOG_INT_MASK, __VA_ARGS__)
-#undef VERBOSE
-#define VERBOSE 0
+//#define VERBOSE (LOG_GENERAL)
+#include "logmacro.h"
// Bit manipulation
namespace {
@@ -716,20 +715,20 @@ void tms9914_device::update_fsm()
m_sh_vsts = true;
}
if (!get_signal(IEEE_488_NDAC)) {
-#if VERBOSE
- bool iscmd = m_signals[IEEE_488_ATN];
- char cmd[16] = "";
- if (iscmd) {
- uint8_t tmp = m_dio & 0x7f;
- if (tmp >= 0x20 && tmp <= 0x3f)
- snprintf(cmd, 16, "MLA%d", tmp & 0x1f);
- else if (tmp >= 0x40 && tmp <= 0x5f)
- snprintf(cmd, 16, "MTA%d", tmp & 0x1f);
- else if (tmp >= 0x60 && tmp <= 0x7f)
- snprintf(cmd, 16, "MSA%d", tmp & 0x1f);
+ if (VERBOSE & LOG_GENERAL) {
+ bool const iscmd = m_signals[IEEE_488_ATN];
+ char cmd[16] = "";
+ if (iscmd) {
+ uint8_t tmp = m_dio & 0x7f;
+ if (tmp >= 0x20 && tmp <= 0x3f)
+ snprintf(cmd, 16, "MLA%d", tmp & 0x1f);
+ else if (tmp >= 0x40 && tmp <= 0x5f)
+ snprintf(cmd, 16, "MTA%d", tmp & 0x1f);
+ else if (tmp >= 0x60 && tmp <= 0x7f)
+ snprintf(cmd, 16, "MSA%d", tmp & 0x1f);
+ }
+ LOG("%.6f TX %s %02X/%d %s\n" , machine().time().as_double() , m_signals[IEEE_488_ATN] ? "C" : "D", m_dio , m_signals[ IEEE_488_EOI ], cmd);
}
- LOG("%.6f TX %s %02X/%d %s\n" , machine().time().as_double() , m_signals[IEEE_488_ATN] ? "C" : "D", m_dio , m_signals[ IEEE_488_EOI ], cmd);
-#endif
m_sh_state = FSM_SH_SGNS;
}
break;
diff --git a/src/devices/sound/pokey.cpp b/src/devices/sound/pokey.cpp
index 7880de562d7..53ad7f26fdf 100644
--- a/src/devices/sound/pokey.cpp
+++ b/src/devices/sound/pokey.cpp
@@ -507,7 +507,7 @@ void pokey_device::step_keyboard()
if (m_IRQEN & IRQ_KEYBD)
{
/* last interrupt not acknowledged ? */
- if(m_IRQST & IRQ_KEYBD)
+ if (m_IRQST & IRQ_KEYBD)
m_SKSTAT |= SK_KBERR;
m_IRQST |= IRQ_KEYBD;
if (!m_irq_f.isnull())
@@ -546,18 +546,16 @@ void pokey_device::step_keyboard()
void pokey_device::step_pot()
{
- int pot;
-
- if( (m_SKCTL & SK_RESET) == 0)
+ if ((m_SKCTL & SK_RESET) == 0)
return;
uint8_t upd = 0;
m_pot_counter++;
- for (pot = 0; pot < 8; pot++)
+ for (int pot = 0; pot < 8; pot++)
{
if ((m_POTx[pot]<m_pot_counter) || (m_pot_counter == 228))
{
- upd |= (1<<pot);
+ upd |= (1 << pot);
/* latching is emulated in read */
}
}
@@ -574,14 +572,13 @@ void pokey_device::step_pot()
uint32_t pokey_device::step_one_clock(void)
{
- int ch, clk;
- uint32_t sum = 0;
- int clock_triggered[3] = {0,0,0};
- int base_clock = (m_AUDCTL & CLK_15KHZ) ? CLK_114 : CLK_28;
+ int const base_clock = (m_AUDCTL & CLK_15KHZ) ? CLK_114 : CLK_28;
- if( (m_SKCTL & SK_RESET) )
+ if (m_SKCTL & SK_RESET)
{
/* Clocks only count if we are not in a reset */
+ int clock_triggered[3] = {0,0,0};
+ int clk;
for (clk = 0; clk < 3; clk++)
{
m_clock_cnt[clk]++;
@@ -625,7 +622,7 @@ uint32_t pokey_device::step_one_clock(void)
/* do CHAN2 before CHAN1 because CHAN1 may set borrow! */
if (m_channel[CHAN2].check_borrow())
{
- int isJoined = (m_AUDCTL & CH12_JOINED);
+ bool const isJoined(m_AUDCTL & CH12_JOINED);
if (isJoined)
m_channel[CHAN1].reset_channel();
m_channel[CHAN2].reset_channel();
@@ -638,7 +635,7 @@ uint32_t pokey_device::step_one_clock(void)
if (m_channel[CHAN1].check_borrow())
{
- int isJoined = (m_AUDCTL & CH12_JOINED);
+ bool const isJoined(m_AUDCTL & CH12_JOINED);
if (isJoined)
m_channel[CHAN2].inc_chan();
else
@@ -652,7 +649,7 @@ uint32_t pokey_device::step_one_clock(void)
/* do CHAN4 before CHAN3 because CHAN3 may set borrow! */
if (m_channel[CHAN4].check_borrow())
{
- int isJoined = (m_AUDCTL & CH34_JOINED);
+ bool const isJoined(m_AUDCTL & CH34_JOINED);
if (isJoined)
m_channel[CHAN3].reset_channel();
m_channel[CHAN4].reset_channel();
@@ -668,7 +665,7 @@ uint32_t pokey_device::step_one_clock(void)
if (m_channel[CHAN3].check_borrow())
{
- int isJoined = (m_AUDCTL & CH34_JOINED);
+ bool const isJoined(m_AUDCTL & CH34_JOINED);
if (isJoined)
m_channel[CHAN4].inc_chan();
else
@@ -681,7 +678,8 @@ uint32_t pokey_device::step_one_clock(void)
m_channel[CHAN1].m_filter_sample = 1;
}
- for (ch = 0; ch < 4; ch++)
+ uint32_t sum = 0;
+ for (int ch = 0; ch < 4; ch++)
{
sum |= (((((m_channel[ch].m_output ^ m_channel[ch].m_filter_sample) || (m_channel[ch].m_AUDC & VOLUME_ONLY)) ? (m_channel[ch].m_AUDC & VOLUME_MASK) : 0 )) << (ch * 4));
}
@@ -793,7 +791,7 @@ READ8_MEMBER( pokey_device::read )
case POT0_C: case POT1_C: case POT2_C: case POT3_C:
case POT4_C: case POT5_C: case POT6_C: case POT7_C:
pot = offset & 7;
- if( m_ALLPOT & (1 << pot) )
+ if (m_ALLPOT & (1 << pot))
{
/* we have a value measured */
data = m_POTx[pot];
@@ -811,12 +809,12 @@ READ8_MEMBER( pokey_device::read )
* If the 2 least significant bits of SKCTL are 0, the ALLPOTs
* are disabled (SKRESET). Thanks to MikeJ for pointing this out.
****************************************************************/
- if( (m_SKCTL & SK_RESET) == 0)
+ if ((m_SKCTL & SK_RESET) == 0)
{
data = m_ALLPOT;
LOG(("POKEY '%s' ALLPOT internal $%02x (reset)\n", tag(), data));
}
- else if( !m_allpot_r_cb.isnull() )
+ else if (!m_allpot_r_cb.isnull())
{
m_ALLPOT = data = m_allpot_r_cb(offset);
LOG(("%s: POKEY '%s' ALLPOT callback $%02x\n", machine().describe_context(), tag(), data));
@@ -833,7 +831,7 @@ READ8_MEMBER( pokey_device::read )
break;
case RANDOM_C:
- if( m_AUDCTL & POLY9 )
+ if (m_AUDCTL & POLY9)
{
data = m_poly9[m_p9] & 0xff;
LOG_RAND(("POKEY '%s' rand9[$%05x]: $%02x\n", tag(), m_p9, data));
@@ -846,7 +844,7 @@ READ8_MEMBER( pokey_device::read )
break;
case SERIN_C:
- if( !m_serin_r_cb.isnull() )
+ if (!m_serin_r_cb.isnull())
m_SERIN = m_serin_r_cb(offset);
data = m_SERIN;
LOG(("POKEY '%s' SERIN $%02x\n", tag(), data));
@@ -880,7 +878,7 @@ READ8_MEMBER( pokey_device::read )
WRITE8_MEMBER( pokey_device::write )
{
- synchronize(SYNC_WRITE, (offset<<8) | data);
+ synchronize(SYNC_WRITE, (offset << 8) | data);
}
void pokey_device::write_internal(offs_t offset, uint8_t data)
@@ -1145,7 +1143,7 @@ void pokey_device::vol_init()
rTot = 0;
for (int i=0; i<4; i++)
{
- rTot += 1.0 / r_chan[(j>>(i*4)) & 0x0f];
+ rTot += 1.0 / r_chan[(j >> (i*4)) & 0x0f];
}
rTot = 1.0 / rTot;
m_voltab[j] = rTot;
diff --git a/src/emu/dirtc.cpp b/src/emu/dirtc.cpp
index 0d5442fe6c2..20ebbbacef8 100644
--- a/src/emu/dirtc.cpp
+++ b/src/emu/dirtc.cpp
@@ -197,8 +197,8 @@ void device_rtc_interface::advance_days()
if (m_register[RTC_MONTH] > 0 && m_register[RTC_DAY] > DAYS_PER_MONTH[m_register[RTC_MONTH] - 1])
{
- if (m_register[RTC_MONTH] != 2 || m_register[RTC_DAY] != 29 || !rtc_feature_leap_year() ||
- (m_register[RTC_YEAR] % 4) != 0) {
+ if (m_register[RTC_MONTH] != 2 || m_register[RTC_DAY] != 29 || !rtc_feature_leap_year() || !(m_register[RTC_YEAR] % 4))
+ {
m_register[RTC_DAY] = 1;
m_register[RTC_MONTH]++;
}
diff --git a/src/emu/emuopts.cpp b/src/emu/emuopts.cpp
index 160398d165f..0d7c5899db5 100644
--- a/src/emu/emuopts.cpp
+++ b/src/emu/emuopts.cpp
@@ -389,7 +389,7 @@ namespace
if (!same_name)
result.push_back(image.brief_instance_name());
- if( image.instance_name() != image.cannonical_instance_name() )
+ if (image.instance_name() != image.cannonical_instance_name())
{
result.push_back(image.cannonical_instance_name());
if (!same_name)
diff --git a/src/mame/drivers/crystal.cpp b/src/mame/drivers/crystal.cpp
index 43349c843d4..13eea7fa338 100644
--- a/src/mame/drivers/crystal.cpp
+++ b/src/mame/drivers/crystal.cpp
@@ -414,9 +414,8 @@ IRQ_CALLBACK_MEMBER(crystal_state::icallback)
{
address_space &space = m_maincpu->space(AS_PROGRAM);
uint32_t IntPend = space.read_dword(0x01800c0c);
- int i;
- for (i = 0; i < 32; ++i)
+ for (int i = 0; i < 32; ++i)
{
if (BIT(IntPend, i))
{
@@ -498,15 +497,14 @@ WRITE32_MEMBER(crystal_state::DMA_w)
{
if (((data ^ m_DMActrl[Which]) & (1 << 10)) && (data & (1 << 10))) //DMAOn
{
- uint32_t CTR = data;
- uint32_t SRC = space.read_dword(0x01800804 + Which * 0x10);
- uint32_t DST = space.read_dword(0x01800808 + Which * 0x10);
- uint32_t CNT = space.read_dword(0x0180080C + Which * 0x10);
- int i;
+ uint32_t const CTR = data;
+ uint32_t const SRC = space.read_dword(0x01800804 + Which * 0x10);
+ uint32_t const DST = space.read_dword(0x01800808 + Which * 0x10);
+ uint32_t const CNT = space.read_dword(0x0180080C + Which * 0x10);
if (CTR & 0x2) //32 bits
{
- for (i = 0; i < CNT; ++i)
+ for (int i = 0; i < CNT; ++i)
{
uint32_t v = space.read_dword(SRC + i * 4);
space.write_dword(DST + i * 4, v);
@@ -514,7 +512,7 @@ WRITE32_MEMBER(crystal_state::DMA_w)
}
else if (CTR & 0x1) //16 bits
{
- for (i = 0; i < CNT; ++i)
+ for (int i = 0; i < CNT; ++i)
{
uint16_t v = space.read_word(SRC + i * 2);
space.write_word(DST + i * 2, v);
@@ -522,7 +520,7 @@ WRITE32_MEMBER(crystal_state::DMA_w)
}
else //8 bits
{
- for (i = 0; i < CNT; ++i)
+ for (int i = 0; i < CNT; ++i)
{
uint8_t v = space.read_byte(SRC + i);
space.write_byte(DST + i, v);
@@ -1067,7 +1065,6 @@ uint32_t crystal_state::screen_update(screen_device &screen, bitmap_ind16 &bitma
uint16_t *Front, *Back;
uint16_t *Visible, *DrawDest;
uint16_t *srcline;
- int y;
uint16_t head, tail;
uint32_t width = cliprect.width();
@@ -1113,9 +1110,9 @@ uint32_t crystal_state::screen_update(screen_device &screen, bitmap_ind16 &bitma
SetVidReg(space, 0x8e, GetVidReg(space, 0x8e) ^ 1);
srcline = (uint16_t *) Visible;
- uint32_t dx = cliprect.left();
- for (y = cliprect.top(); y <= cliprect.bottom(); y++)
- std::copy_n( &srcline[(y * 1024) + dx], width, &bitmap.pix16(y, dx));
+ uint32_t const dx = cliprect.left();
+ for (int y = cliprect.top(); y <= cliprect.bottom(); y++)
+ std::copy_n(&srcline[(y * 1024) + dx], width, &bitmap.pix16(y, dx));
return 0;
}
diff --git a/src/mame/drivers/r9751.cpp b/src/mame/drivers/r9751.cpp
index eca4d9004ac..3c126860703 100644
--- a/src/mame/drivers/r9751.cpp
+++ b/src/mame/drivers/r9751.cpp
@@ -170,7 +170,7 @@ private:
#if ENABLE_TRACE_ALL_DEVICES
// Device tracing
-static const char * DeviceNames[] = {
+static char const *const DeviceNames[] = {
nullptr,nullptr,nullptr,nullptr,nullptr,nullptr,nullptr,"??", // 0x00-0x07
"??","HDD",nullptr,nullptr,nullptr,nullptr,nullptr,nullptr, // 0x08-0x0F
nullptr,nullptr,nullptr,nullptr,nullptr,nullptr,nullptr,nullptr, // 0x10-0x17
@@ -180,6 +180,7 @@ static const char * DeviceNames[] = {
"??",nullptr,nullptr,nullptr,nullptr,nullptr,nullptr,nullptr, // 0x30-0x37
"SMIOCc?",nullptr,"SMIOCd?",nullptr,nullptr,nullptr,nullptr,"??" // 0x38-0x3F
};
+
struct GenericCommandRecord {
u32 AddressPattern;
const char * Name;
@@ -392,8 +393,8 @@ static const SystemRegisterInfo SystemRegisters[] = {
};
-static const int MaxSystemTables = 256; // FF00xxxx through FFFFxxxx
-static const int MaxSystemRegisters = 0x400; // FF0x0000 through FF0x0FFC
+static constexpr int MaxSystemTables = 256; // FF00xxxx through FFFFxxxx
+static constexpr int MaxSystemRegisters = 0x400; // FF0x0000 through FF0x0FFC
void r9751_state::system_trace_init()
{
const SystemRegisterInfo*** trace_context;
diff --git a/src/mame/drivers/toypop.cpp b/src/mame/drivers/toypop.cpp
index bb0df1deba2..30b26b46094 100644
--- a/src/mame/drivers/toypop.cpp
+++ b/src/mame/drivers/toypop.cpp
@@ -43,8 +43,8 @@
class namcos16_state : public driver_device
{
public:
- namcos16_state(const machine_config &mconfig, device_type type, const char *tag)
- : driver_device(mconfig, type, tag),
+ namcos16_state(const machine_config &mconfig, device_type type, const char *tag) :
+ driver_device(mconfig, type, tag),
m_master_cpu(*this,"maincpu"),
m_slave_cpu(*this, "slave"),
m_sound_cpu(*this, "audiocpu"),
@@ -59,7 +59,8 @@ public:
m_bgvram(*this, "bgvram"),
m_fgvram(*this, "fgvram"),
m_fgattr(*this, "fgattr")
- { }
+ {
+ }
void toypop(machine_config &config);
void liblrabl(machine_config &config);
@@ -123,9 +124,9 @@ private:
bool m_slave_irq_enable;
uint8_t m_pal_bank;
- void legacy_bg_draw(bitmap_ind16 &bitmap,const rectangle &cliprect,int flip);
- void legacy_fg_draw(bitmap_ind16 &bitmap,const rectangle &cliprect,int flip);
- void legacy_obj_draw(bitmap_ind16 &bitmap,const rectangle &cliprect,int flip);
+ void legacy_bg_draw(bitmap_ind16 &bitmap,const rectangle &cliprect,bool flip);
+ void legacy_fg_draw(bitmap_ind16 &bitmap,const rectangle &cliprect,bool flip);
+ void legacy_obj_draw(bitmap_ind16 &bitmap,const rectangle &cliprect,bool flip);
};
PALETTE_INIT_MEMBER(namcos16_state, toypop)
@@ -177,27 +178,22 @@ PALETTE_INIT_MEMBER(namcos16_state, toypop)
}
}
-void namcos16_state::legacy_bg_draw(bitmap_ind16 &bitmap,const rectangle &cliprect,int flip)
+void namcos16_state::legacy_bg_draw(bitmap_ind16 &bitmap,const rectangle &cliprect,bool flip)
{
- int x, y;
const uint16_t pal_base = 0x300 + (m_pal_bank << 4);
const uint32_t src_base = 0x200/2;
const uint16_t src_pitch = 288 / 2;
- for (y = cliprect.min_y; y <= cliprect.max_y; ++y)
+ for (int y = cliprect.min_y; y <= cliprect.max_y; ++y)
{
uint16_t *src = &m_bgvram[y * src_pitch + cliprect.min_x + src_base];
- uint16_t *dst;
- if(!flip)
- dst = &bitmap.pix16(y, cliprect.min_x);
- else
- dst = &bitmap.pix16(cliprect.max_y - y, cliprect.max_x);
+ uint16_t *dst = &bitmap.pix16(flip ? (cliprect.max_y - y) : y, flip ? cliprect.max_x : cliprect.min_x);
- for (x = cliprect.min_x; x <= cliprect.max_x; x += 2)
+ for (int x = cliprect.min_x; x <= cliprect.max_x; x += 2)
{
- uint32_t srcpix = *src++;
- int idx1 = ((srcpix >> 8) & 0xf) + pal_base;
- int idx2 = (srcpix & 0xf) + pal_base;
+ uint32_t const srcpix = *src++;
+ int const idx1 = ((srcpix >> 8) & 0xf) + pal_base;
+ int const idx2 = (srcpix & 0xf) + pal_base;
if (!flip)
{
*dst++ = m_palette->pen(idx1);
@@ -212,62 +208,63 @@ void namcos16_state::legacy_bg_draw(bitmap_ind16 &bitmap,const rectangle &clipre
}
}
-void namcos16_state::legacy_fg_draw(bitmap_ind16 &bitmap,const rectangle &cliprect,int flip)
+void namcos16_state::legacy_fg_draw(bitmap_ind16 &bitmap,const rectangle &cliprect,bool flip)
{
- gfx_element *gfx_0 = m_gfxdecode->gfx(0);
- int count;
+ gfx_element *const gfx_0 = m_gfxdecode->gfx(0);
- for (count=0;count<32*32;count++)
+ for (int count = 0; count < 32*32; count++)
{
+ int const xoffs(count >> 5);
+ int const yoffs(count & 0x1f);
int x;// = (count % 32);
int y; //= count / 32;
if (!flip)
{
- if(count < 64)
+ if (count < 64)
{
- x = 34 + (count / 32);
- y = (count % 32) - 2;
+ x = 34 + xoffs;
+ y = yoffs - 2;
}
- else if(count >= 32*30)
+ else if (count >= 32*30)
{
- x = (count / 32) - 30;
- y = (count % 32) - 2;
+ x = xoffs - 30;
+ y = yoffs - 2;
}
else
{
- x = 2 + (count % 32);
- y = (count / 32) - 2;
+ x = 2 + yoffs;
+ y = xoffs - 2;
}
}
else
{
- if(count < 64)
+ if (count < 64)
{
- x = 1 - (count / 32);
- y = 29 - (count % 32);
+ x = 1 - xoffs;
+ y = 29 - yoffs;
}
- else if(count >= 32*30)
+ else if (count >= 32*30)
{
- x = 65 - (count / 32);
- y = 29 - (count % 32);
+ x = 65 - xoffs;
+ y = 29 - yoffs;
}
else
{
- x = 33 - (count % 32);
- y = 29 - (count / 32);
+ x = 33 - yoffs;
+ y = 29 - xoffs;
}
}
uint16_t tile = m_fgvram[count];
- uint8_t color = (m_fgattr[count] & 0x3f) + (m_pal_bank<<6);
+ uint8_t color = (m_fgattr[count] & 0x3f) + (m_pal_bank << 6);
- gfx_0->transpen(bitmap,cliprect,tile,color,flip,flip,x*8,y*8,0);
+ gfx_0->transpen(bitmap, cliprect, tile, color, flip, flip, x*8, y*8, 0);
}
}
// TODO: this is likely to be a lot more complex, and maybe is per scanline too
-void namcos16_state::legacy_obj_draw(bitmap_ind16 &bitmap,const rectangle &cliprect,int flip)
+void namcos16_state::legacy_obj_draw(bitmap_ind16 &bitmap,const rectangle &cliprect,bool flip)
{
gfx_element *gfx_1 = m_gfxdecode->gfx(1);
int count;
@@ -309,12 +306,12 @@ void namcos16_state::legacy_obj_draw(bitmap_ind16 &bitmap,const rectangle &clipr
fy ^= 1;
}
- if(height == 2)
+ if (height == 2)
y -=16;
- for(int yi=0;yi<height;yi++)
+ for (int yi=0; yi<height; yi++)
{
- for(int xi=0;xi<width;xi++)
+ for(int xi=0; xi<width; xi++)
{
uint16_t sprite_offs = tile + gfx_offs[yi ^ ((height - 1) * fy)][xi ^ ((width - 1) * fx)];
gfx_1->transmask(bitmap,cliprect,sprite_offs,color,fx,fy,x + xi*16,y + yi *16,m_palette->transpen_mask(*gfx_1, color, 0xff));
@@ -325,7 +322,7 @@ void namcos16_state::legacy_obj_draw(bitmap_ind16 &bitmap,const rectangle &clipr
uint32_t namcos16_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect )
{
- int flip = flip_screen();
+ bool const flip = flip_screen();
legacy_bg_draw(bitmap,cliprect,flip);
legacy_fg_draw(bitmap,cliprect,flip);
legacy_obj_draw(bitmap,cliprect,flip);