diff options
| author | 2009-06-28 04:59:14 +0000 | |
|---|---|---|
| committer | 2009-06-28 04:59:14 +0000 | |
| commit | badb1141c44ef9cbbad8cb7ce44df58a5a42ac7f (patch) | |
| tree | 36c346e6ceeb2d49b8430418bad640d34c02f8cc /src | |
| parent | 8241581bf2ecc783e9076055c86d95f338ab47df (diff) | |
PPCDRC: fix flags on STWCX and fix FMULS to use the correct registers
Diffstat (limited to 'src')
| -rw-r--r-- | src/emu/cpu/powerpc/ppcdrc.c | 7 | ||||
| -rw-r--r-- | src/emu/cpu/powerpc/ppcfe.c | 9 |
2 files changed, 14 insertions, 2 deletions
diff --git a/src/emu/cpu/powerpc/ppcdrc.c b/src/emu/cpu/powerpc/ppcdrc.c index 5e332fcff0e..01fe4d4a101 100644 --- a/src/emu/cpu/powerpc/ppcdrc.c +++ b/src/emu/cpu/powerpc/ppcdrc.c @@ -3505,7 +3505,12 @@ static int generate_instruction_1f(powerpc_state *ppc, drcuml_block *block, comp UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op) UML_CALLH(block, ppc->impstate->write32align[ppc->impstate->mode]); // callh write32align generate_update_cycles(ppc, block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles> + UML_CMP(block, IREG(0), IREG(0)); // cmp i0,i0 + UML_GETFLGS(block, IREG(0), DRCUML_FLAG_Z | DRCUML_FLAG_C | DRCUML_FLAG_S); // getflgs i0,zcs + UML_LOAD(block, IREG(0), ppc->impstate->cmp_cr_table, IREG(0), BYTE); // load i0,cmp_cr_table,i0,byte + UML_OR(block, CR32(G_CRFD(op)), IREG(0), XERSO32); // or [crn],i0,[xerso] + generate_compute_flags(ppc, block, desc, TRUE, 0, FALSE); // <update flags> return TRUE; @@ -3802,7 +3807,7 @@ static int generate_instruction_3b(powerpc_state *ppc, drcuml_block *block, comp case 0x19: /* FMULSx */ if (!(ppc->impstate->drcoptions & PPCDRC_ACCURATE_SINGLES)) return generate_instruction_3f(ppc, block, compiler, desc); - UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_RB(op))); // fdmul f0,ra,rb + UML_FDMUL(block, FREG(0), F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc UML_FDRNDS(block, F64(G_RD(op)), FREG(0)); // fdrnds rd,f0 return TRUE; diff --git a/src/emu/cpu/powerpc/ppcfe.c b/src/emu/cpu/powerpc/ppcfe.c index 79c9fa7162f..84af68f4fed 100644 --- a/src/emu/cpu/powerpc/ppcfe.c +++ b/src/emu/cpu/powerpc/ppcfe.c @@ -1247,7 +1247,6 @@ static int describe_instruction_3b(powerpc_state *ppc, UINT32 op, opcode_desc *d case 0x14: /* FSUBSx */ case 0x15: /* FADDSx */ - case 0x19: /* FMULSx */ FPR_USED(desc, G_RA(op)); FPR_USED(desc, G_RB(op)); FPR_MODIFIED(desc, G_RD(op)); @@ -1255,6 +1254,14 @@ static int describe_instruction_3b(powerpc_state *ppc, UINT32 op, opcode_desc *d CR_MODIFIED(desc, 1); return TRUE; + case 0x19: /* FMULSx - not the same form as FSUB/FADD! */ + FPR_USED(desc, G_RA(op)); + FPR_USED(desc, G_REGC(op)); + FPR_MODIFIED(desc, G_RD(op)); + if (op & M_RC) + CR_MODIFIED(desc, 1); + return TRUE; + case 0x16: /* FSQRTSx */ case 0x18: /* FRESx */ FPR_USED(desc, G_RB(op)); |
