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author Aaron Giles <aaron@aarongiles.com>2008-07-03 15:34:27 +0000
committer Aaron Giles <aaron@aarongiles.com>2008-07-03 15:34:27 +0000
commitb82b111e697d9758c5b5b0911a3295db8169800b (patch)
treec073a9b296ad660a693257ccc90d81b583ea9a50 /src
parent7f1456798a266191ed2ac0adf5d47cd2d005c4d0 (diff)
Lighter weight debugger optimization for ADSP2100.
Diffstat (limited to 'src')
-rw-r--r--src/emu/cpu/adsp2100/adsp2100.c1448
1 files changed, 702 insertions, 746 deletions
diff --git a/src/emu/cpu/adsp2100/adsp2100.c b/src/emu/cpu/adsp2100/adsp2100.c
index 31daaab7b1f..02208cab7cb 100644
--- a/src/emu/cpu/adsp2100/adsp2100.c
+++ b/src/emu/cpu/adsp2100/adsp2100.c
@@ -282,7 +282,6 @@ static UINT32 pcbucket[0x4000];
static int create_tables(void);
static void check_irqs(void);
-static void execute_one(UINT32 op);
/***************************************************************************
@@ -932,6 +931,8 @@ static void adsp2100_exit(void)
/* execute instructions on this CPU until icount expires */
static int adsp2100_execute(int cycles)
{
+ int check_debugger = ((Machine->debug_flags & DEBUG_FLAG_ENABLED) != 0);
+
/* reset the core */
set_mstat(adsp2100.mstat);
@@ -940,787 +941,742 @@ static int adsp2100_execute(int cycles)
CHANGEPC();
- /* no debugger */
- if ((Machine->debug_flags & DEBUG_FLAG_ENABLED) == 0)
- {
- do
- {
- UINT32 op;
-
- /* debugging */
- adsp2100.ppc = adsp2100.pc; /* copy PC to previous PC */
- op = ROPCODE();
-
- /* advance to the next instruction */
- if (adsp2100.pc != adsp2100.loop)
- adsp2100.pc++;
-
- /* handle looping */
- else
- {
- /* condition not met, keep looping */
- if (CONDITION(adsp2100.loop_condition))
- adsp2100.pc = pc_stack_top();
-
- /* condition met; pop the PC and loop stacks and fall through */
- else
- {
- loop_stack_pop();
- pc_stack_pop_val();
- adsp2100.pc++;
- }
- }
-
- execute_one(op);
- adsp2100_icount--;
- } while (adsp2100_icount > 0);
- }
-
- /* debugger enabled */
- else
+ do
{
- do
- {
- UINT32 op;
+ UINT32 temp;
+ UINT32 op;
- /* debugging */
- adsp2100.ppc = adsp2100.pc; /* copy PC to previous PC */
+ /* debugging */
+ adsp2100.ppc = adsp2100.pc; /* copy PC to previous PC */
+ if (check_debugger)
debugger_instruction_hook(Machine, adsp2100.pc);
#if TRACK_HOTSPOTS
- pcbucket[adsp2100.pc & 0x3fff]++;
+ pcbucket[adsp2100.pc & 0x3fff]++;
#endif
- /* instruction fetch */
- op = ROPCODE();
+ /* instruction fetch */
+ op = ROPCODE();
- /* advance to the next instruction */
- if (adsp2100.pc != adsp2100.loop)
- adsp2100.pc++;
+ /* advance to the next instruction */
+ if (adsp2100.pc != adsp2100.loop)
+ adsp2100.pc++;
+
+ /* handle looping */
+ else
+ {
+ /* condition not met, keep looping */
+ if (CONDITION(adsp2100.loop_condition))
+ adsp2100.pc = pc_stack_top();
- /* handle looping */
+ /* condition met; pop the PC and loop stacks and fall through */
else
{
- /* condition not met, keep looping */
- if (CONDITION(adsp2100.loop_condition))
- adsp2100.pc = pc_stack_top();
-
- /* condition met; pop the PC and loop stacks and fall through */
+ loop_stack_pop();
+ pc_stack_pop_val();
+ adsp2100.pc++;
+ }
+ }
+
+ /* parse the instruction */
+ switch (op >> 16)
+ {
+ case 0x00:
+ /* 00000000 00000000 00000000 NOP */
+ break;
+ case 0x01:
+ /* 00000000 0xxxxxxx xxxxxxxx dst = IO(x) */
+ /* 00000000 1xxxxxxx xxxxxxxx IO(x) = dst */
+ /* ADSP-218x only */
+ if (chip_type >= CHIP_TYPE_ADSP2181)
+ {
+ if ((op & 0x008000) == 0x000000)
+ WRITE_REG(0, op & 15, RWORD_IO((op >> 4) & 0x7ff));
+ else
+ WWORD_IO((op >> 4) & 0x7ff, READ_REG(0, op & 15));
+ }
+ break;
+ case 0x02:
+ /* 00000010 0000xxxx xxxxxxxx modify flag out */
+ /* 00000010 10000000 00000000 idle */
+ /* 00000010 10000000 0000xxxx idle (n) */
+ if (op & 0x008000)
+ {
+ adsp2100.idle = 1;
+ adsp2100_icount = 0;
+ }
else
{
- loop_stack_pop();
- pc_stack_pop_val();
- adsp2100.pc++;
+ if (CONDITION(op & 15))
+ {
+ if (op & 0x020) adsp2100.flagout = 0;
+ if (op & 0x010) adsp2100.flagout ^= 1;
+ if (chip_type >= CHIP_TYPE_ADSP2101)
+ {
+ if (op & 0x080) adsp2100.fl0 = 0;
+ if (op & 0x040) adsp2100.fl0 ^= 1;
+ if (op & 0x200) adsp2100.fl1 = 0;
+ if (op & 0x100) adsp2100.fl1 ^= 1;
+ if (op & 0x800) adsp2100.fl2 = 0;
+ if (op & 0x400) adsp2100.fl2 ^= 1;
+ }
+ }
+ }
+ break;
+ case 0x03:
+ /* 00000011 xxxxxxxx xxxxxxxx call or jump on flag in */
+ if (op & 0x000002)
+ {
+ if (adsp2100.flagin)
+ {
+ if (op & 0x000001)
+ pc_stack_push();
+ adsp2100.pc = ((op >> 4) & 0x0fff) | ((op << 10) & 0x3000);
+ CHANGEPC();
+ }
}
- }
-
- execute_one(op);
- adsp2100_icount--;
- } while (adsp2100_icount > 0);
- }
-
- return cycles - adsp2100_icount;
-}
-
-
-static void execute_one(UINT32 op)
-{
- UINT32 temp;
-
- /* parse the instruction */
- switch (op >> 16)
- {
- case 0x00:
- /* 00000000 00000000 00000000 NOP */
- break;
- case 0x01:
- /* 00000000 0xxxxxxx xxxxxxxx dst = IO(x) */
- /* 00000000 1xxxxxxx xxxxxxxx IO(x) = dst */
- /* ADSP-218x only */
- if (chip_type >= CHIP_TYPE_ADSP2181)
- {
- if ((op & 0x008000) == 0x000000)
- WRITE_REG(0, op & 15, RWORD_IO((op >> 4) & 0x7ff));
else
- WWORD_IO((op >> 4) & 0x7ff, READ_REG(0, op & 15));
- }
- break;
- case 0x02:
- /* 00000010 0000xxxx xxxxxxxx modify flag out */
- /* 00000010 10000000 00000000 idle */
- /* 00000010 10000000 0000xxxx idle (n) */
- if (op & 0x008000)
- {
- adsp2100.idle = 1;
- adsp2100_icount = 0;
- }
- else
- {
- if (CONDITION(op & 15))
{
- if (op & 0x020) adsp2100.flagout = 0;
- if (op & 0x010) adsp2100.flagout ^= 1;
- if (chip_type >= CHIP_TYPE_ADSP2101)
+ if (!adsp2100.flagin)
{
- if (op & 0x080) adsp2100.fl0 = 0;
- if (op & 0x040) adsp2100.fl0 ^= 1;
- if (op & 0x200) adsp2100.fl1 = 0;
- if (op & 0x100) adsp2100.fl1 ^= 1;
- if (op & 0x800) adsp2100.fl2 = 0;
- if (op & 0x400) adsp2100.fl2 ^= 1;
+ if (op & 0x000001)
+ pc_stack_push();
+ adsp2100.pc = ((op >> 4) & 0x0fff) | ((op << 10) & 0x3000);
+ CHANGEPC();
}
}
- }
- break;
- case 0x03:
- /* 00000011 xxxxxxxx xxxxxxxx call or jump on flag in */
- if (op & 0x000002)
- {
- if (adsp2100.flagin)
+ break;
+ case 0x04:
+ /* 00000100 00000000 000xxxxx stack control */
+ if (op & 0x000010) pc_stack_pop_val();
+ if (op & 0x000008) loop_stack_pop();
+ if (op & 0x000004) cntr_stack_pop();
+ if (op & 0x000002)
{
- if (op & 0x000001)
- pc_stack_push();
- adsp2100.pc = ((op >> 4) & 0x0fff) | ((op << 10) & 0x3000);
- CHANGEPC();
+ if (op & 0x000001) stat_stack_pop();
+ else stat_stack_push();
}
- }
- else
- {
- if (!adsp2100.flagin)
+ break;
+ case 0x05:
+ /* 00000101 00000000 00000000 saturate MR */
+ if (GET_MV)
{
- if (op & 0x000001)
- pc_stack_push();
- adsp2100.pc = ((op >> 4) & 0x0fff) | ((op << 10) & 0x3000);
- CHANGEPC();
+ if (adsp2100.core.mr.mrx.mr2.u & 0x80)
+ adsp2100.core.mr.mrx.mr2.u = 0xffff, adsp2100.core.mr.mrx.mr1.u = 0x8000, adsp2100.core.mr.mrx.mr0.u = 0x0000;
+ else
+ adsp2100.core.mr.mrx.mr2.u = 0x0000, adsp2100.core.mr.mrx.mr1.u = 0x7fff, adsp2100.core.mr.mrx.mr0.u = 0xffff;
}
- }
- break;
- case 0x04:
- /* 00000100 00000000 000xxxxx stack control */
- if (op & 0x000010) pc_stack_pop_val();
- if (op & 0x000008) loop_stack_pop();
- if (op & 0x000004) cntr_stack_pop();
- if (op & 0x000002)
- {
- if (op & 0x000001) stat_stack_pop();
- else stat_stack_push();
- }
- break;
- case 0x05:
- /* 00000101 00000000 00000000 saturate MR */
- if (GET_MV)
- {
- if (adsp2100.core.mr.mrx.mr2.u & 0x80)
- adsp2100.core.mr.mrx.mr2.u = 0xffff, adsp2100.core.mr.mrx.mr1.u = 0x8000, adsp2100.core.mr.mrx.mr0.u = 0x0000;
- else
- adsp2100.core.mr.mrx.mr2.u = 0x0000, adsp2100.core.mr.mrx.mr1.u = 0x7fff, adsp2100.core.mr.mrx.mr0.u = 0xffff;
- }
- break;
- case 0x06:
- /* 00000110 000xxxxx 00000000 DIVS */
- {
- int xop = (op >> 8) & 7;
- int yop = (op >> 11) & 3;
+ break;
+ case 0x06:
+ /* 00000110 000xxxxx 00000000 DIVS */
+ {
+ int xop = (op >> 8) & 7;
+ int yop = (op >> 11) & 3;
- xop = ALU_GETXREG_UNSIGNED(xop);
- yop = ALU_GETYREG_UNSIGNED(yop);
+ xop = ALU_GETXREG_UNSIGNED(xop);
+ yop = ALU_GETYREG_UNSIGNED(yop);
- temp = xop ^ yop;
- adsp2100.astat = (adsp2100.astat & ~QFLAG) | ((temp >> 10) & QFLAG);
- adsp2100.core.af.u = (yop << 1) | (adsp2100.core.ay0.u >> 15);
- adsp2100.core.ay0.u = (adsp2100.core.ay0.u << 1) | (temp >> 15);
- }
- break;
- case 0x07:
- /* 00000111 00010xxx 00000000 DIVQ */
- {
- int xop = (op >> 8) & 7;
- int res;
+ temp = xop ^ yop;
+ adsp2100.astat = (adsp2100.astat & ~QFLAG) | ((temp >> 10) & QFLAG);
+ adsp2100.core.af.u = (yop << 1) | (adsp2100.core.ay0.u >> 15);
+ adsp2100.core.ay0.u = (adsp2100.core.ay0.u << 1) | (temp >> 15);
+ }
+ break;
+ case 0x07:
+ /* 00000111 00010xxx 00000000 DIVQ */
+ {
+ int xop = (op >> 8) & 7;
+ int res;
- xop = ALU_GETXREG_UNSIGNED(xop);
+ xop = ALU_GETXREG_UNSIGNED(xop);
- if (GET_Q)
- res = adsp2100.core.af.u + xop;
- else
- res = adsp2100.core.af.u - xop;
+ if (GET_Q)
+ res = adsp2100.core.af.u + xop;
+ else
+ res = adsp2100.core.af.u - xop;
- temp = res ^ xop;
- adsp2100.astat = (adsp2100.astat & ~QFLAG) | ((temp >> 10) & QFLAG);
- adsp2100.core.af.u = (res << 1) | (adsp2100.core.ay0.u >> 15);
- adsp2100.core.ay0.u = (adsp2100.core.ay0.u << 1) | ((~temp >> 15) & 0x0001);
- }
- break;
- case 0x08:
- /* 00001000 00000000 0000xxxx reserved */
- break;
- case 0x09:
- /* 00001001 00000000 000xxxxx modify address register */
- temp = (op >> 2) & 4;
- modify_address(temp + ((op >> 2) & 3), temp + (op & 3));
- break;
- case 0x0a:
- /* 00001010 00000000 000xxxxx conditional return */
- if (CONDITION(op & 15))
- {
- pc_stack_pop();
+ temp = res ^ xop;
+ adsp2100.astat = (adsp2100.astat & ~QFLAG) | ((temp >> 10) & QFLAG);
+ adsp2100.core.af.u = (res << 1) | (adsp2100.core.ay0.u >> 15);
+ adsp2100.core.ay0.u = (adsp2100.core.ay0.u << 1) | ((~temp >> 15) & 0x0001);
+ }
+ break;
+ case 0x08:
+ /* 00001000 00000000 0000xxxx reserved */
+ break;
+ case 0x09:
+ /* 00001001 00000000 000xxxxx modify address register */
+ temp = (op >> 2) & 4;
+ modify_address(temp + ((op >> 2) & 3), temp + (op & 3));
+ break;
+ case 0x0a:
+ /* 00001010 00000000 000xxxxx conditional return */
+ if (CONDITION(op & 15))
+ {
+ pc_stack_pop();
- /* RTI case */
- if (op & 0x000010)
- stat_stack_pop();
- }
- break;
- case 0x0b:
- /* 00001011 00000000 xxxxxxxx conditional jump (indirect address) */
- if (CONDITION(op & 15))
- {
- if (op & 0x000010)
- pc_stack_push();
- adsp2100.pc = adsp2100.i[4 + ((op >> 6) & 3)] & 0x3fff;
- CHANGEPC();
- }
- break;
- case 0x0c:
- /* 00001100 xxxxxxxx xxxxxxxx mode control */
- temp = adsp2100.mstat;
- if (chip_type >= CHIP_TYPE_ADSP2101)
- {
- if (op & 0x000008) temp = (temp & ~MSTAT_GOMODE) | ((op << 5) & MSTAT_GOMODE);
- if (op & 0x002000) temp = (temp & ~MSTAT_INTEGER) | ((op >> 8) & MSTAT_INTEGER);
- if (op & 0x008000) temp = (temp & ~MSTAT_TIMER) | ((op >> 9) & MSTAT_TIMER);
- }
- if (op & 0x000020) temp = (temp & ~MSTAT_BANK) | ((op >> 4) & MSTAT_BANK);
- if (op & 0x000080) temp = (temp & ~MSTAT_REVERSE) | ((op >> 5) & MSTAT_REVERSE);
- if (op & 0x000200) temp = (temp & ~MSTAT_STICKYV) | ((op >> 6) & MSTAT_STICKYV);
- if (op & 0x000800) temp = (temp & ~MSTAT_SATURATE) | ((op >> 7) & MSTAT_SATURATE);
- set_mstat(temp);
- break;
- case 0x0d:
- /* 00001101 0000xxxx xxxxxxxx internal data move */
- WRITE_REG((op >> 10) & 3, (op >> 4) & 15, READ_REG((op >> 8) & 3, op & 15));
- break;
- case 0x0e:
- /* 00001110 0xxxxxxx xxxxxxxx conditional shift */
- if (CONDITION(op & 15)) shift_op(op);
- break;
- case 0x0f:
- /* 00001111 0xxxxxxx xxxxxxxx shift immediate */
- shift_op_imm(op);
- break;
- case 0x10:
- /* 00010000 0xxxxxxx xxxxxxxx shift with internal data register move */
- shift_op(op);
- temp = READ_REG(0, op & 15);
- WRITE_REG(0, (op >> 4) & 15, temp);
- break;
- case 0x11:
- /* 00010001 xxxxxxxx xxxxxxxx shift with pgm memory read/write */
- if (op & 0x8000)
- {
- pgm_write_dag2(op, READ_REG(0, (op >> 4) & 15));
- shift_op(op);
- }
- else
- {
- shift_op(op);
- WRITE_REG(0, (op >> 4) & 15, pgm_read_dag2(op));
- }
- break;
- case 0x12:
- /* 00010010 xxxxxxxx xxxxxxxx shift with data memory read/write DAG1 */
- if (op & 0x8000)
- {
- data_write_dag1(op, READ_REG(0, (op >> 4) & 15));
- shift_op(op);
- }
- else
- {
- shift_op(op);
- WRITE_REG(0, (op >> 4) & 15, data_read_dag1(op));
- }
- break;
- case 0x13:
- /* 00010011 xxxxxxxx xxxxxxxx shift with data memory read/write DAG2 */
- if (op & 0x8000)
- {
- data_write_dag2(op, READ_REG(0, (op >> 4) & 15));
- shift_op(op);
- }
- else
- {
+ /* RTI case */
+ if (op & 0x000010)
+ stat_stack_pop();
+ }
+ break;
+ case 0x0b:
+ /* 00001011 00000000 xxxxxxxx conditional jump (indirect address) */
+ if (CONDITION(op & 15))
+ {
+ if (op & 0x000010)
+ pc_stack_push();
+ adsp2100.pc = adsp2100.i[4 + ((op >> 6) & 3)] & 0x3fff;
+ CHANGEPC();
+ }
+ break;
+ case 0x0c:
+ /* 00001100 xxxxxxxx xxxxxxxx mode control */
+ temp = adsp2100.mstat;
+ if (chip_type >= CHIP_TYPE_ADSP2101)
+ {
+ if (op & 0x000008) temp = (temp & ~MSTAT_GOMODE) | ((op << 5) & MSTAT_GOMODE);
+ if (op & 0x002000) temp = (temp & ~MSTAT_INTEGER) | ((op >> 8) & MSTAT_INTEGER);
+ if (op & 0x008000) temp = (temp & ~MSTAT_TIMER) | ((op >> 9) & MSTAT_TIMER);
+ }
+ if (op & 0x000020) temp = (temp & ~MSTAT_BANK) | ((op >> 4) & MSTAT_BANK);
+ if (op & 0x000080) temp = (temp & ~MSTAT_REVERSE) | ((op >> 5) & MSTAT_REVERSE);
+ if (op & 0x000200) temp = (temp & ~MSTAT_STICKYV) | ((op >> 6) & MSTAT_STICKYV);
+ if (op & 0x000800) temp = (temp & ~MSTAT_SATURATE) | ((op >> 7) & MSTAT_SATURATE);
+ set_mstat(temp);
+ break;
+ case 0x0d:
+ /* 00001101 0000xxxx xxxxxxxx internal data move */
+ WRITE_REG((op >> 10) & 3, (op >> 4) & 15, READ_REG((op >> 8) & 3, op & 15));
+ break;
+ case 0x0e:
+ /* 00001110 0xxxxxxx xxxxxxxx conditional shift */
+ if (CONDITION(op & 15)) shift_op(op);
+ break;
+ case 0x0f:
+ /* 00001111 0xxxxxxx xxxxxxxx shift immediate */
+ shift_op_imm(op);
+ break;
+ case 0x10:
+ /* 00010000 0xxxxxxx xxxxxxxx shift with internal data register move */
shift_op(op);
- WRITE_REG(0, (op >> 4) & 15, data_read_dag2(op));
- }
- break;
- case 0x14: case 0x15: case 0x16: case 0x17:
- /* 000101xx xxxxxxxx xxxxxxxx do until */
- loop_stack_push(op & 0x3ffff);
- pc_stack_push();
- break;
- case 0x18: case 0x19: case 0x1a: case 0x1b:
- /* 000110xx xxxxxxxx xxxxxxxx conditional jump (immediate addr) */
- if (CONDITION(op & 15))
- {
- adsp2100.pc = (op >> 4) & 0x3fff;
- CHANGEPC();
- }
- /* check for a busy loop */
- if (adsp2100.pc == adsp2100.ppc)
- adsp2100_icount = 0;
- break;
- case 0x1c: case 0x1d: case 0x1e: case 0x1f:
- /* 000111xx xxxxxxxx xxxxxxxx conditional call (immediate addr) */
- if (CONDITION(op & 15))
- {
- pc_stack_push();
- adsp2100.pc = (op >> 4) & 0x3fff;
- CHANGEPC();
- }
- break;
- case 0x20: case 0x21:
- /* 0010000x xxxxxxxx xxxxxxxx conditional MAC to MR */
- if (CONDITION(op & 15))
- {
- if (chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x0018f0) == 0x000010)
- mac_op_mr_xop(op);
+ temp = READ_REG(0, op & 15);
+ WRITE_REG(0, (op >> 4) & 15, temp);
+ break;
+ case 0x11:
+ /* 00010001 xxxxxxxx xxxxxxxx shift with pgm memory read/write */
+ if (op & 0x8000)
+ {
+ pgm_write_dag2(op, READ_REG(0, (op >> 4) & 15));
+ shift_op(op);
+ }
else
- mac_op_mr(op);
- }
- break;
- case 0x22: case 0x23:
- /* 0010001x xxxxxxxx xxxxxxxx conditional ALU to AR */
- if (CONDITION(op & 15))
- {
- if (chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x000010) == 0x000010)
- alu_op_ar_const(op);
+ {
+ shift_op(op);
+ WRITE_REG(0, (op >> 4) & 15, pgm_read_dag2(op));
+ }
+ break;
+ case 0x12:
+ /* 00010010 xxxxxxxx xxxxxxxx shift with data memory read/write DAG1 */
+ if (op & 0x8000)
+ {
+ data_write_dag1(op, READ_REG(0, (op >> 4) & 15));
+ shift_op(op);
+ }
else
- alu_op_ar(op);
- }
- break;
- case 0x24: case 0x25:
- /* 0010010x xxxxxxxx xxxxxxxx conditional MAC to MF */
- if (CONDITION(op & 15))
- {
- if (chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x0018f0) == 0x000010)
- mac_op_mf_xop(op);
+ {
+ shift_op(op);
+ WRITE_REG(0, (op >> 4) & 15, data_read_dag1(op));
+ }
+ break;
+ case 0x13:
+ /* 00010011 xxxxxxxx xxxxxxxx shift with data memory read/write DAG2 */
+ if (op & 0x8000)
+ {
+ data_write_dag2(op, READ_REG(0, (op >> 4) & 15));
+ shift_op(op);
+ }
else
- mac_op_mf(op);
- }
- break;
- case 0x26: case 0x27:
- /* 0010011x xxxxxxxx xxxxxxxx conditional ALU to AF */
- if (CONDITION(op & 15))
- {
- if (chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x000010) == 0x000010)
- alu_op_af_const(op);
+ {
+ shift_op(op);
+ WRITE_REG(0, (op >> 4) & 15, data_read_dag2(op));
+ }
+ break;
+ case 0x14: case 0x15: case 0x16: case 0x17:
+ /* 000101xx xxxxxxxx xxxxxxxx do until */
+ loop_stack_push(op & 0x3ffff);
+ pc_stack_push();
+ break;
+ case 0x18: case 0x19: case 0x1a: case 0x1b:
+ /* 000110xx xxxxxxxx xxxxxxxx conditional jump (immediate addr) */
+ if (CONDITION(op & 15))
+ {
+ adsp2100.pc = (op >> 4) & 0x3fff;
+ CHANGEPC();
+ /* check for a busy loop */
+ if (adsp2100.pc == adsp2100.ppc)
+ adsp2100_icount = 0;
+ }
+ break;
+ case 0x1c: case 0x1d: case 0x1e: case 0x1f:
+ /* 000111xx xxxxxxxx xxxxxxxx conditional call (immediate addr) */
+ if (CONDITION(op & 15))
+ {
+ pc_stack_push();
+ adsp2100.pc = (op >> 4) & 0x3fff;
+ CHANGEPC();
+ }
+ break;
+ case 0x20: case 0x21:
+ /* 0010000x xxxxxxxx xxxxxxxx conditional MAC to MR */
+ if (CONDITION(op & 15))
+ {
+ if (chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x0018f0) == 0x000010)
+ mac_op_mr_xop(op);
+ else
+ mac_op_mr(op);
+ }
+ break;
+ case 0x22: case 0x23:
+ /* 0010001x xxxxxxxx xxxxxxxx conditional ALU to AR */
+ if (CONDITION(op & 15))
+ {
+ if (chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x000010) == 0x000010)
+ alu_op_ar_const(op);
+ else
+ alu_op_ar(op);
+ }
+ break;
+ case 0x24: case 0x25:
+ /* 0010010x xxxxxxxx xxxxxxxx conditional MAC to MF */
+ if (CONDITION(op & 15))
+ {
+ if (chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x0018f0) == 0x000010)
+ mac_op_mf_xop(op);
+ else
+ mac_op_mf(op);
+ }
+ break;
+ case 0x26: case 0x27:
+ /* 0010011x xxxxxxxx xxxxxxxx conditional ALU to AF */
+ if (CONDITION(op & 15))
+ {
+ if (chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x000010) == 0x000010)
+ alu_op_af_const(op);
+ else
+ alu_op_af(op);
+ }
+ break;
+ case 0x28: case 0x29:
+ /* 0010100x xxxxxxxx xxxxxxxx MAC to MR with internal data register move */
+ temp = READ_REG(0, op & 15);
+ mac_op_mr(op);
+ WRITE_REG(0, (op >> 4) & 15, temp);
+ break;
+ case 0x2a: case 0x2b:
+ /* 0010101x xxxxxxxx xxxxxxxx ALU to AR with internal data register move */
+ if (chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x0000ff) == 0x0000aa)
+ alu_op_none(op);
else
- alu_op_af(op);
- }
- break;
- case 0x28: case 0x29:
- /* 0010100x xxxxxxxx xxxxxxxx MAC to MR with internal data register move */
- temp = READ_REG(0, op & 15);
- mac_op_mr(op);
- WRITE_REG(0, (op >> 4) & 15, temp);
- break;
- case 0x2a: case 0x2b:
- /* 0010101x xxxxxxxx xxxxxxxx ALU to AR with internal data register move */
- if (chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x0000ff) == 0x0000aa)
- alu_op_none(op);
- else
- {
+ {
+ temp = READ_REG(0, op & 15);
+ alu_op_ar(op);
+ WRITE_REG(0, (op >> 4) & 15, temp);
+ }
+ break;
+ case 0x2c: case 0x2d:
+ /* 0010110x xxxxxxxx xxxxxxxx MAC to MF with internal data register move */
temp = READ_REG(0, op & 15);
- alu_op_ar(op);
+ mac_op_mf(op);
WRITE_REG(0, (op >> 4) & 15, temp);
- }
- break;
- case 0x2c: case 0x2d:
- /* 0010110x xxxxxxxx xxxxxxxx MAC to MF with internal data register move */
- temp = READ_REG(0, op & 15);
- mac_op_mf(op);
- WRITE_REG(0, (op >> 4) & 15, temp);
- break;
- case 0x2e: case 0x2f:
- /* 0010111x xxxxxxxx xxxxxxxx ALU to AF with internal data register move */
- temp = READ_REG(0, op & 15);
- alu_op_af(op);
- WRITE_REG(0, (op >> 4) & 15, temp);
- break;
- case 0x30: case 0x31: case 0x32: case 0x33:
- /* 001100xx xxxxxxxx xxxxxxxx load non-data register immediate (group 0) */
- WRITE_REG(0, op & 15, (INT32)(op << 14) >> 18);
- break;
- case 0x34: case 0x35: case 0x36: case 0x37:
- /* 001101xx xxxxxxxx xxxxxxxx load non-data register immediate (group 1) */
- WRITE_REG(1, op & 15, (INT32)(op << 14) >> 18);
- break;
- case 0x38: case 0x39: case 0x3a: case 0x3b:
- /* 001110xx xxxxxxxx xxxxxxxx load non-data register immediate (group 2) */
- WRITE_REG(2, op & 15, (INT32)(op << 14) >> 18);
- break;
- case 0x3c: case 0x3d: case 0x3e: case 0x3f:
- /* 001111xx xxxxxxxx xxxxxxxx load non-data register immediate (group 3) */
- WRITE_REG(3, op & 15, (INT32)(op << 14) >> 18);
- break;
- case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
- case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
- /* 0100xxxx xxxxxxxx xxxxxxxx load data register immediate */
- WRITE_REG(0, op & 15, (op >> 4) & 0xffff);
- break;
- case 0x50: case 0x51:
- /* 0101000x xxxxxxxx xxxxxxxx MAC to MR with pgm memory read */
- mac_op_mr(op);
- WRITE_REG(0, (op >> 4) & 15, pgm_read_dag2(op));
- break;
- case 0x52: case 0x53:
- /* 0101001x xxxxxxxx xxxxxxxx ALU to AR with pgm memory read */
- alu_op_ar(op);
- WRITE_REG(0, (op >> 4) & 15, pgm_read_dag2(op));
- break;
- case 0x54: case 0x55:
- /* 0101010x xxxxxxxx xxxxxxxx MAC to MF with pgm memory read */
- mac_op_mf(op);
- WRITE_REG(0, (op >> 4) & 15, pgm_read_dag2(op));
- break;
- case 0x56: case 0x57:
- /* 0101011x xxxxxxxx xxxxxxxx ALU to AF with pgm memory read */
- alu_op_af(op);
- WRITE_REG(0, (op >> 4) & 15, pgm_read_dag2(op));
- break;
- case 0x58: case 0x59:
- /* 0101100x xxxxxxxx xxxxxxxx MAC to MR with pgm memory write */
- pgm_write_dag2(op, READ_REG(0, (op >> 4) & 15));
- mac_op_mr(op);
- break;
- case 0x5a: case 0x5b:
- /* 0101101x xxxxxxxx xxxxxxxx ALU to AR with pgm memory write */
- pgm_write_dag2(op, READ_REG(0, (op >> 4) & 15));
- alu_op_ar(op);
- break;
- case 0x5c: case 0x5d:
- /* 0101110x xxxxxxxx xxxxxxxx ALU to MR with pgm memory write */
- pgm_write_dag2(op, READ_REG(0, (op >> 4) & 15));
- mac_op_mf(op);
- break;
- case 0x5e: case 0x5f:
- /* 0101111x xxxxxxxx xxxxxxxx ALU to MF with pgm memory write */
- pgm_write_dag2(op, READ_REG(0, (op >> 4) & 15));
- alu_op_af(op);
- break;
- case 0x60: case 0x61:
- /* 0110000x xxxxxxxx xxxxxxxx MAC to MR with data memory read DAG1 */
- mac_op_mr(op);
- WRITE_REG(0, (op >> 4) & 15, data_read_dag1(op));
- break;
- case 0x62: case 0x63:
- /* 0110001x xxxxxxxx xxxxxxxx ALU to AR with data memory read DAG1 */
- alu_op_ar(op);
- WRITE_REG(0, (op >> 4) & 15, data_read_dag1(op));
- break;
- case 0x64: case 0x65:
- /* 0110010x xxxxxxxx xxxxxxxx MAC to MF with data memory read DAG1 */
- mac_op_mf(op);
- WRITE_REG(0, (op >> 4) & 15, data_read_dag1(op));
- break;
- case 0x66: case 0x67:
- /* 0110011x xxxxxxxx xxxxxxxx ALU to AF with data memory read DAG1 */
- alu_op_af(op);
- WRITE_REG(0, (op >> 4) & 15, data_read_dag1(op));
- break;
- case 0x68: case 0x69:
- /* 0110100x xxxxxxxx xxxxxxxx MAC to MR with data memory write DAG1 */
- data_write_dag1(op, READ_REG(0, (op >> 4) & 15));
- mac_op_mr(op);
- break;
- case 0x6a: case 0x6b:
- /* 0110101x xxxxxxxx xxxxxxxx ALU to AR with data memory write DAG1 */
- data_write_dag1(op, READ_REG(0, (op >> 4) & 15));
- alu_op_ar(op);
- break;
- case 0x6c: case 0x6d:
- /* 0111110x xxxxxxxx xxxxxxxx MAC to MF with data memory write DAG1 */
- data_write_dag1(op, READ_REG(0, (op >> 4) & 15));
- mac_op_mf(op);
- break;
- case 0x6e: case 0x6f:
- /* 0111111x xxxxxxxx xxxxxxxx ALU to AF with data memory write DAG1 */
- data_write_dag1(op, READ_REG(0, (op >> 4) & 15));
- alu_op_af(op);
- break;
- case 0x70: case 0x71:
- /* 0111000x xxxxxxxx xxxxxxxx MAC to MR with data memory read DAG2 */
- mac_op_mr(op);
- WRITE_REG(0, (op >> 4) & 15, data_read_dag2(op));
- break;
- case 0x72: case 0x73:
- /* 0111001x xxxxxxxx xxxxxxxx ALU to AR with data memory read DAG2 */
- alu_op_ar(op);
- WRITE_REG(0, (op >> 4) & 15, data_read_dag2(op));
- break;
- case 0x74: case 0x75:
- /* 0111010x xxxxxxxx xxxxxxxx MAC to MF with data memory read DAG2 */
- mac_op_mf(op);
- WRITE_REG(0, (op >> 4) & 15, data_read_dag2(op));
- break;
- case 0x76: case 0x77:
- /* 0111011x xxxxxxxx xxxxxxxx ALU to AF with data memory read DAG2 */
- alu_op_af(op);
- WRITE_REG(0, (op >> 4) & 15, data_read_dag2(op));
- break;
- case 0x78: case 0x79:
- /* 0111100x xxxxxxxx xxxxxxxx MAC to MR with data memory write DAG2 */
- data_write_dag2(op, READ_REG(0, (op >> 4) & 15));
- mac_op_mr(op);
- break;
- case 0x7a: case 0x7b:
- /* 0111101x xxxxxxxx xxxxxxxx ALU to AR with data memory write DAG2 */
- data_write_dag2(op, READ_REG(0, (op >> 4) & 15));
- alu_op_ar(op);
- break;
- case 0x7c: case 0x7d:
- /* 0111110x xxxxxxxx xxxxxxxx MAC to MF with data memory write DAG2 */
- data_write_dag2(op, READ_REG(0, (op >> 4) & 15));
- mac_op_mf(op);
- break;
- case 0x7e: case 0x7f:
- /* 0111111x xxxxxxxx xxxxxxxx ALU to AF with data memory write DAG2 */
- data_write_dag2(op, READ_REG(0, (op >> 4) & 15));
- alu_op_af(op);
- break;
- case 0x80: case 0x81: case 0x82: case 0x83:
- /* 100000xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 0 */
- WRITE_REG(0, op & 15, RWORD_DATA((op >> 4) & 0x3fff));
- break;
- case 0x84: case 0x85: case 0x86: case 0x87:
- /* 100001xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 1 */
- WRITE_REG(1, op & 15, RWORD_DATA((op >> 4) & 0x3fff));
- break;
- case 0x88: case 0x89: case 0x8a: case 0x8b:
- /* 100010xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 2 */
- WRITE_REG(2, op & 15, RWORD_DATA((op >> 4) & 0x3fff));
- break;
- case 0x8c: case 0x8d: case 0x8e: case 0x8f:
- /* 100011xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 3 */
- WRITE_REG(3, op & 15, RWORD_DATA((op >> 4) & 0x3fff));
- break;
- case 0x90: case 0x91: case 0x92: case 0x93:
- /* 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 0 */
- WWORD_DATA((op >> 4) & 0x3fff, READ_REG(0, op & 15));
- break;
- case 0x94: case 0x95: case 0x96: case 0x97:
- /* 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 1 */
- WWORD_DATA((op >> 4) & 0x3fff, READ_REG(1, op & 15));
- break;
- case 0x98: case 0x99: case 0x9a: case 0x9b:
- /* 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 2 */
- WWORD_DATA((op >> 4) & 0x3fff, READ_REG(2, op & 15));
- break;
- case 0x9c: case 0x9d: case 0x9e: case 0x9f:
- /* 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 3 */
- WWORD_DATA((op >> 4) & 0x3fff, READ_REG(3, op & 15));
- break;
- case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
- case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
- /* 1010xxxx xxxxxxxx xxxxxxxx data memory write (immediate) DAG1 */
- data_write_dag1(op, (op >> 4) & 0xffff);
- break;
- case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
- case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
- /* 1011xxxx xxxxxxxx xxxxxxxx data memory write (immediate) DAG2 */
- data_write_dag2(op, (op >> 4) & 0xffff);
- break;
- case 0xc0: case 0xc1:
- /* 1100000x xxxxxxxx xxxxxxxx MAC to MR with data read to AX0 & pgm read to AY0 */
- mac_op_mr(op);
- adsp2100.core.ax0.u = data_read_dag1(op);
- adsp2100.core.ay0.u = pgm_read_dag2(op >> 4);
- break;
- case 0xc2: case 0xc3:
- /* 1100001x xxxxxxxx xxxxxxxx ALU to AR with data read to AX0 & pgm read to AY0 */
- alu_op_ar(op);
- adsp2100.core.ax0.u = data_read_dag1(op);
- adsp2100.core.ay0.u = pgm_read_dag2(op >> 4);
- break;
- case 0xc4: case 0xc5:
- /* 1100010x xxxxxxxx xxxxxxxx MAC to MR with data read to AX1 & pgm read to AY0 */
- mac_op_mr(op);
- adsp2100.core.ax1.u = data_read_dag1(op);
- adsp2100.core.ay0.u = pgm_read_dag2(op >> 4);
- break;
- case 0xc6: case 0xc7:
- /* 1100011x xxxxxxxx xxxxxxxx ALU to AR with data read to AX1 & pgm read to AY0 */
- alu_op_ar(op);
- adsp2100.core.ax1.u = data_read_dag1(op);
- adsp2100.core.ay0.u = pgm_read_dag2(op >> 4);
- break;
- case 0xc8: case 0xc9:
- /* 1100100x xxxxxxxx xxxxxxxx MAC to MR with data read to MX0 & pgm read to AY0 */
- mac_op_mr(op);
- adsp2100.core.mx0.u = data_read_dag1(op);
- adsp2100.core.ay0.u = pgm_read_dag2(op >> 4);
- break;
- case 0xca: case 0xcb:
- /* 1100101x xxxxxxxx xxxxxxxx ALU to AR with data read to MX0 & pgm read to AY0 */
- alu_op_ar(op);
- adsp2100.core.mx0.u = data_read_dag1(op);
- adsp2100.core.ay0.u = pgm_read_dag2(op >> 4);
- break;
- case 0xcc: case 0xcd:
- /* 1100110x xxxxxxxx xxxxxxxx MAC to MR with data read to MX1 & pgm read to AY0 */
- mac_op_mr(op);
- adsp2100.core.mx1.u = data_read_dag1(op);
- adsp2100.core.ay0.u = pgm_read_dag2(op >> 4);
- break;
- case 0xce: case 0xcf:
- /* 1100111x xxxxxxxx xxxxxxxx ALU to AR with data read to MX1 & pgm read to AY0 */
- alu_op_ar(op);
- adsp2100.core.mx1.u = data_read_dag1(op);
- adsp2100.core.ay0.u = pgm_read_dag2(op >> 4);
- break;
- case 0xd0: case 0xd1:
- /* 1101000x xxxxxxxx xxxxxxxx MAC to MR with data read to AX0 & pgm read to AY1 */
- mac_op_mr(op);
- adsp2100.core.ax0.u = data_read_dag1(op);
- adsp2100.core.ay1.u = pgm_read_dag2(op >> 4);
- break;
- case 0xd2: case 0xd3:
- /* 1101001x xxxxxxxx xxxxxxxx ALU to AR with data read to AX0 & pgm read to AY1 */
- alu_op_ar(op);
- adsp2100.core.ax0.u = data_read_dag1(op);
- adsp2100.core.ay1.u = pgm_read_dag2(op >> 4);
- break;
- case 0xd4: case 0xd5:
- /* 1101010x xxxxxxxx xxxxxxxx MAC to MR with data read to AX1 & pgm read to AY1 */
- mac_op_mr(op);
- adsp2100.core.ax1.u = data_read_dag1(op);
- adsp2100.core.ay1.u = pgm_read_dag2(op >> 4);
- break;
- case 0xd6: case 0xd7:
- /* 1101011x xxxxxxxx xxxxxxxx ALU to AR with data read to AX1 & pgm read to AY1 */
- alu_op_ar(op);
- adsp2100.core.ax1.u = data_read_dag1(op);
- adsp2100.core.ay1.u = pgm_read_dag2(op >> 4);
- break;
- case 0xd8: case 0xd9:
- /* 1101100x xxxxxxxx xxxxxxxx MAC to MR with data read to MX0 & pgm read to AY1 */
- mac_op_mr(op);
- adsp2100.core.mx0.u = data_read_dag1(op);
- adsp2100.core.ay1.u = pgm_read_dag2(op >> 4);
- break;
- case 0xda: case 0xdb:
- /* 1101101x xxxxxxxx xxxxxxxx ALU to AR with data read to MX0 & pgm read to AY1 */
- alu_op_ar(op);
- adsp2100.core.mx0.u = data_read_dag1(op);
- adsp2100.core.ay1.u = pgm_read_dag2(op >> 4);
- break;
- case 0xdc: case 0xdd:
- /* 1101110x xxxxxxxx xxxxxxxx MAC to MR with data read to MX1 & pgm read to AY1 */
- mac_op_mr(op);
- adsp2100.core.mx1.u = data_read_dag1(op);
- adsp2100.core.ay1.u = pgm_read_dag2(op >> 4);
- break;
- case 0xde: case 0xdf:
- /* 1101111x xxxxxxxx xxxxxxxx ALU to AR with data read to MX1 & pgm read to AY1 */
- alu_op_ar(op);
- adsp2100.core.mx1.u = data_read_dag1(op);
- adsp2100.core.ay1.u = pgm_read_dag2(op >> 4);
- break;
- case 0xe0: case 0xe1:
- /* 1110000x xxxxxxxx xxxxxxxx MAC to MR with data read to AX0 & pgm read to MY0 */
- mac_op_mr(op);
- adsp2100.core.ax0.u = data_read_dag1(op);
- adsp2100.core.my0.u = pgm_read_dag2(op >> 4);
- break;
- case 0xe2: case 0xe3:
- /* 1110001x xxxxxxxx xxxxxxxx ALU to AR with data read to AX0 & pgm read to MY0 */
- alu_op_ar(op);
- adsp2100.core.ax0.u = data_read_dag1(op);
- adsp2100.core.my0.u = pgm_read_dag2(op >> 4);
- break;
- case 0xe4: case 0xe5:
- /* 1110010x xxxxxxxx xxxxxxxx MAC to MR with data read to AX1 & pgm read to MY0 */
- mac_op_mr(op);
- adsp2100.core.ax1.u = data_read_dag1(op);
- adsp2100.core.my0.u = pgm_read_dag2(op >> 4);
- break;
- case 0xe6: case 0xe7:
- /* 1110011x xxxxxxxx xxxxxxxx ALU to AR with data read to AX1 & pgm read to MY0 */
- alu_op_ar(op);
- adsp2100.core.ax1.u = data_read_dag1(op);
- adsp2100.core.my0.u = pgm_read_dag2(op >> 4);
- break;
- case 0xe8: case 0xe9:
- /* 1110100x xxxxxxxx xxxxxxxx MAC to MR with data read to MX0 & pgm read to MY0 */
- mac_op_mr(op);
- adsp2100.core.mx0.u = data_read_dag1(op);
- adsp2100.core.my0.u = pgm_read_dag2(op >> 4);
- break;
- case 0xea: case 0xeb:
- /* 1110101x xxxxxxxx xxxxxxxx ALU to AR with data read to MX0 & pgm read to MY0 */
- alu_op_ar(op);
- adsp2100.core.mx0.u = data_read_dag1(op);
- adsp2100.core.my0.u = pgm_read_dag2(op >> 4);
- break;
- case 0xec: case 0xed:
- /* 1110110x xxxxxxxx xxxxxxxx MAC to MR with data read to MX1 & pgm read to MY0 */
- mac_op_mr(op);
- adsp2100.core.mx1.u = data_read_dag1(op);
- adsp2100.core.my0.u = pgm_read_dag2(op >> 4);
- break;
- case 0xee: case 0xef:
- /* 1110111x xxxxxxxx xxxxxxxx ALU to AR with data read to MX1 & pgm read to MY0 */
- alu_op_ar(op);
- adsp2100.core.mx1.u = data_read_dag1(op);
- adsp2100.core.my0.u = pgm_read_dag2(op >> 4);
- break;
- case 0xf0: case 0xf1:
- /* 1111000x xxxxxxxx xxxxxxxx MAC to MR with data read to AX0 & pgm read to MY1 */
- mac_op_mr(op);
- adsp2100.core.ax0.u = data_read_dag1(op);
- adsp2100.core.my1.u = pgm_read_dag2(op >> 4);
- break;
- case 0xf2: case 0xf3:
- /* 1111001x xxxxxxxx xxxxxxxx ALU to AR with data read to AX0 & pgm read to MY1 */
- alu_op_ar(op);
- adsp2100.core.ax0.u = data_read_dag1(op);
- adsp2100.core.my1.u = pgm_read_dag2(op >> 4);
- break;
- case 0xf4: case 0xf5:
- /* 1111010x xxxxxxxx xxxxxxxx MAC to MR with data read to AX1 & pgm read to MY1 */
- mac_op_mr(op);
- adsp2100.core.ax1.u = data_read_dag1(op);
- adsp2100.core.my1.u = pgm_read_dag2(op >> 4);
- break;
- case 0xf6: case 0xf7:
- /* 1111011x xxxxxxxx xxxxxxxx ALU to AR with data read to AX1 & pgm read to MY1 */
- alu_op_ar(op);
- adsp2100.core.ax1.u = data_read_dag1(op);
- adsp2100.core.my1.u = pgm_read_dag2(op >> 4);
- break;
- case 0xf8: case 0xf9:
- /* 1111100x xxxxxxxx xxxxxxxx MAC to MR with data read to MX0 & pgm read to MY1 */
- mac_op_mr(op);
- adsp2100.core.mx0.u = data_read_dag1(op);
- adsp2100.core.my1.u = pgm_read_dag2(op >> 4);
- break;
- case 0xfa: case 0xfb:
- /* 1111101x xxxxxxxx xxxxxxxx ALU to AR with data read to MX0 & pgm read to MY1 */
- alu_op_ar(op);
- adsp2100.core.mx0.u = data_read_dag1(op);
- adsp2100.core.my1.u = pgm_read_dag2(op >> 4);
- break;
- case 0xfc: case 0xfd:
- /* 1111110x xxxxxxxx xxxxxxxx MAC to MR with data read to MX1 & pgm read to MY1 */
- mac_op_mr(op);
- adsp2100.core.mx1.u = data_read_dag1(op);
- adsp2100.core.my1.u = pgm_read_dag2(op >> 4);
- break;
- case 0xfe: case 0xff:
- /* 1111111x xxxxxxxx xxxxxxxx ALU to AR with data read to MX1 & pgm read to MY1 */
- alu_op_ar(op);
- adsp2100.core.mx1.u = data_read_dag1(op);
- adsp2100.core.my1.u = pgm_read_dag2(op >> 4);
- break;
- }
+ break;
+ case 0x2e: case 0x2f:
+ /* 0010111x xxxxxxxx xxxxxxxx ALU to AF with internal data register move */
+ temp = READ_REG(0, op & 15);
+ alu_op_af(op);
+ WRITE_REG(0, (op >> 4) & 15, temp);
+ break;
+ case 0x30: case 0x31: case 0x32: case 0x33:
+ /* 001100xx xxxxxxxx xxxxxxxx load non-data register immediate (group 0) */
+ WRITE_REG(0, op & 15, (INT32)(op << 14) >> 18);
+ break;
+ case 0x34: case 0x35: case 0x36: case 0x37:
+ /* 001101xx xxxxxxxx xxxxxxxx load non-data register immediate (group 1) */
+ WRITE_REG(1, op & 15, (INT32)(op << 14) >> 18);
+ break;
+ case 0x38: case 0x39: case 0x3a: case 0x3b:
+ /* 001110xx xxxxxxxx xxxxxxxx load non-data register immediate (group 2) */
+ WRITE_REG(2, op & 15, (INT32)(op << 14) >> 18);
+ break;
+ case 0x3c: case 0x3d: case 0x3e: case 0x3f:
+ /* 001111xx xxxxxxxx xxxxxxxx load non-data register immediate (group 3) */
+ WRITE_REG(3, op & 15, (INT32)(op << 14) >> 18);
+ break;
+ case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
+ case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
+ /* 0100xxxx xxxxxxxx xxxxxxxx load data register immediate */
+ WRITE_REG(0, op & 15, (op >> 4) & 0xffff);
+ break;
+ case 0x50: case 0x51:
+ /* 0101000x xxxxxxxx xxxxxxxx MAC to MR with pgm memory read */
+ mac_op_mr(op);
+ WRITE_REG(0, (op >> 4) & 15, pgm_read_dag2(op));
+ break;
+ case 0x52: case 0x53:
+ /* 0101001x xxxxxxxx xxxxxxxx ALU to AR with pgm memory read */
+ alu_op_ar(op);
+ WRITE_REG(0, (op >> 4) & 15, pgm_read_dag2(op));
+ break;
+ case 0x54: case 0x55:
+ /* 0101010x xxxxxxxx xxxxxxxx MAC to MF with pgm memory read */
+ mac_op_mf(op);
+ WRITE_REG(0, (op >> 4) & 15, pgm_read_dag2(op));
+ break;
+ case 0x56: case 0x57:
+ /* 0101011x xxxxxxxx xxxxxxxx ALU to AF with pgm memory read */
+ alu_op_af(op);
+ WRITE_REG(0, (op >> 4) & 15, pgm_read_dag2(op));
+ break;
+ case 0x58: case 0x59:
+ /* 0101100x xxxxxxxx xxxxxxxx MAC to MR with pgm memory write */
+ pgm_write_dag2(op, READ_REG(0, (op >> 4) & 15));
+ mac_op_mr(op);
+ break;
+ case 0x5a: case 0x5b:
+ /* 0101101x xxxxxxxx xxxxxxxx ALU to AR with pgm memory write */
+ pgm_write_dag2(op, READ_REG(0, (op >> 4) & 15));
+ alu_op_ar(op);
+ break;
+ case 0x5c: case 0x5d:
+ /* 0101110x xxxxxxxx xxxxxxxx ALU to MR with pgm memory write */
+ pgm_write_dag2(op, READ_REG(0, (op >> 4) & 15));
+ mac_op_mf(op);
+ break;
+ case 0x5e: case 0x5f:
+ /* 0101111x xxxxxxxx xxxxxxxx ALU to MF with pgm memory write */
+ pgm_write_dag2(op, READ_REG(0, (op >> 4) & 15));
+ alu_op_af(op);
+ break;
+ case 0x60: case 0x61:
+ /* 0110000x xxxxxxxx xxxxxxxx MAC to MR with data memory read DAG1 */
+ mac_op_mr(op);
+ WRITE_REG(0, (op >> 4) & 15, data_read_dag1(op));
+ break;
+ case 0x62: case 0x63:
+ /* 0110001x xxxxxxxx xxxxxxxx ALU to AR with data memory read DAG1 */
+ alu_op_ar(op);
+ WRITE_REG(0, (op >> 4) & 15, data_read_dag1(op));
+ break;
+ case 0x64: case 0x65:
+ /* 0110010x xxxxxxxx xxxxxxxx MAC to MF with data memory read DAG1 */
+ mac_op_mf(op);
+ WRITE_REG(0, (op >> 4) & 15, data_read_dag1(op));
+ break;
+ case 0x66: case 0x67:
+ /* 0110011x xxxxxxxx xxxxxxxx ALU to AF with data memory read DAG1 */
+ alu_op_af(op);
+ WRITE_REG(0, (op >> 4) & 15, data_read_dag1(op));
+ break;
+ case 0x68: case 0x69:
+ /* 0110100x xxxxxxxx xxxxxxxx MAC to MR with data memory write DAG1 */
+ data_write_dag1(op, READ_REG(0, (op >> 4) & 15));
+ mac_op_mr(op);
+ break;
+ case 0x6a: case 0x6b:
+ /* 0110101x xxxxxxxx xxxxxxxx ALU to AR with data memory write DAG1 */
+ data_write_dag1(op, READ_REG(0, (op >> 4) & 15));
+ alu_op_ar(op);
+ break;
+ case 0x6c: case 0x6d:
+ /* 0111110x xxxxxxxx xxxxxxxx MAC to MF with data memory write DAG1 */
+ data_write_dag1(op, READ_REG(0, (op >> 4) & 15));
+ mac_op_mf(op);
+ break;
+ case 0x6e: case 0x6f:
+ /* 0111111x xxxxxxxx xxxxxxxx ALU to AF with data memory write DAG1 */
+ data_write_dag1(op, READ_REG(0, (op >> 4) & 15));
+ alu_op_af(op);
+ break;
+ case 0x70: case 0x71:
+ /* 0111000x xxxxxxxx xxxxxxxx MAC to MR with data memory read DAG2 */
+ mac_op_mr(op);
+ WRITE_REG(0, (op >> 4) & 15, data_read_dag2(op));
+ break;
+ case 0x72: case 0x73:
+ /* 0111001x xxxxxxxx xxxxxxxx ALU to AR with data memory read DAG2 */
+ alu_op_ar(op);
+ WRITE_REG(0, (op >> 4) & 15, data_read_dag2(op));
+ break;
+ case 0x74: case 0x75:
+ /* 0111010x xxxxxxxx xxxxxxxx MAC to MF with data memory read DAG2 */
+ mac_op_mf(op);
+ WRITE_REG(0, (op >> 4) & 15, data_read_dag2(op));
+ break;
+ case 0x76: case 0x77:
+ /* 0111011x xxxxxxxx xxxxxxxx ALU to AF with data memory read DAG2 */
+ alu_op_af(op);
+ WRITE_REG(0, (op >> 4) & 15, data_read_dag2(op));
+ break;
+ case 0x78: case 0x79:
+ /* 0111100x xxxxxxxx xxxxxxxx MAC to MR with data memory write DAG2 */
+ data_write_dag2(op, READ_REG(0, (op >> 4) & 15));
+ mac_op_mr(op);
+ break;
+ case 0x7a: case 0x7b:
+ /* 0111101x xxxxxxxx xxxxxxxx ALU to AR with data memory write DAG2 */
+ data_write_dag2(op, READ_REG(0, (op >> 4) & 15));
+ alu_op_ar(op);
+ break;
+ case 0x7c: case 0x7d:
+ /* 0111110x xxxxxxxx xxxxxxxx MAC to MF with data memory write DAG2 */
+ data_write_dag2(op, READ_REG(0, (op >> 4) & 15));
+ mac_op_mf(op);
+ break;
+ case 0x7e: case 0x7f:
+ /* 0111111x xxxxxxxx xxxxxxxx ALU to AF with data memory write DAG2 */
+ data_write_dag2(op, READ_REG(0, (op >> 4) & 15));
+ alu_op_af(op);
+ break;
+ case 0x80: case 0x81: case 0x82: case 0x83:
+ /* 100000xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 0 */
+ WRITE_REG(0, op & 15, RWORD_DATA((op >> 4) & 0x3fff));
+ break;
+ case 0x84: case 0x85: case 0x86: case 0x87:
+ /* 100001xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 1 */
+ WRITE_REG(1, op & 15, RWORD_DATA((op >> 4) & 0x3fff));
+ break;
+ case 0x88: case 0x89: case 0x8a: case 0x8b:
+ /* 100010xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 2 */
+ WRITE_REG(2, op & 15, RWORD_DATA((op >> 4) & 0x3fff));
+ break;
+ case 0x8c: case 0x8d: case 0x8e: case 0x8f:
+ /* 100011xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 3 */
+ WRITE_REG(3, op & 15, RWORD_DATA((op >> 4) & 0x3fff));
+ break;
+ case 0x90: case 0x91: case 0x92: case 0x93:
+ /* 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 0 */
+ WWORD_DATA((op >> 4) & 0x3fff, READ_REG(0, op & 15));
+ break;
+ case 0x94: case 0x95: case 0x96: case 0x97:
+ /* 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 1 */
+ WWORD_DATA((op >> 4) & 0x3fff, READ_REG(1, op & 15));
+ break;
+ case 0x98: case 0x99: case 0x9a: case 0x9b:
+ /* 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 2 */
+ WWORD_DATA((op >> 4) & 0x3fff, READ_REG(2, op & 15));
+ break;
+ case 0x9c: case 0x9d: case 0x9e: case 0x9f:
+ /* 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 3 */
+ WWORD_DATA((op >> 4) & 0x3fff, READ_REG(3, op & 15));
+ break;
+ case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
+ case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
+ /* 1010xxxx xxxxxxxx xxxxxxxx data memory write (immediate) DAG1 */
+ data_write_dag1(op, (op >> 4) & 0xffff);
+ break;
+ case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
+ case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
+ /* 1011xxxx xxxxxxxx xxxxxxxx data memory write (immediate) DAG2 */
+ data_write_dag2(op, (op >> 4) & 0xffff);
+ break;
+ case 0xc0: case 0xc1:
+ /* 1100000x xxxxxxxx xxxxxxxx MAC to MR with data read to AX0 & pgm read to AY0 */
+ mac_op_mr(op);
+ adsp2100.core.ax0.u = data_read_dag1(op);
+ adsp2100.core.ay0.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xc2: case 0xc3:
+ /* 1100001x xxxxxxxx xxxxxxxx ALU to AR with data read to AX0 & pgm read to AY0 */
+ alu_op_ar(op);
+ adsp2100.core.ax0.u = data_read_dag1(op);
+ adsp2100.core.ay0.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xc4: case 0xc5:
+ /* 1100010x xxxxxxxx xxxxxxxx MAC to MR with data read to AX1 & pgm read to AY0 */
+ mac_op_mr(op);
+ adsp2100.core.ax1.u = data_read_dag1(op);
+ adsp2100.core.ay0.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xc6: case 0xc7:
+ /* 1100011x xxxxxxxx xxxxxxxx ALU to AR with data read to AX1 & pgm read to AY0 */
+ alu_op_ar(op);
+ adsp2100.core.ax1.u = data_read_dag1(op);
+ adsp2100.core.ay0.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xc8: case 0xc9:
+ /* 1100100x xxxxxxxx xxxxxxxx MAC to MR with data read to MX0 & pgm read to AY0 */
+ mac_op_mr(op);
+ adsp2100.core.mx0.u = data_read_dag1(op);
+ adsp2100.core.ay0.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xca: case 0xcb:
+ /* 1100101x xxxxxxxx xxxxxxxx ALU to AR with data read to MX0 & pgm read to AY0 */
+ alu_op_ar(op);
+ adsp2100.core.mx0.u = data_read_dag1(op);
+ adsp2100.core.ay0.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xcc: case 0xcd:
+ /* 1100110x xxxxxxxx xxxxxxxx MAC to MR with data read to MX1 & pgm read to AY0 */
+ mac_op_mr(op);
+ adsp2100.core.mx1.u = data_read_dag1(op);
+ adsp2100.core.ay0.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xce: case 0xcf:
+ /* 1100111x xxxxxxxx xxxxxxxx ALU to AR with data read to MX1 & pgm read to AY0 */
+ alu_op_ar(op);
+ adsp2100.core.mx1.u = data_read_dag1(op);
+ adsp2100.core.ay0.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xd0: case 0xd1:
+ /* 1101000x xxxxxxxx xxxxxxxx MAC to MR with data read to AX0 & pgm read to AY1 */
+ mac_op_mr(op);
+ adsp2100.core.ax0.u = data_read_dag1(op);
+ adsp2100.core.ay1.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xd2: case 0xd3:
+ /* 1101001x xxxxxxxx xxxxxxxx ALU to AR with data read to AX0 & pgm read to AY1 */
+ alu_op_ar(op);
+ adsp2100.core.ax0.u = data_read_dag1(op);
+ adsp2100.core.ay1.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xd4: case 0xd5:
+ /* 1101010x xxxxxxxx xxxxxxxx MAC to MR with data read to AX1 & pgm read to AY1 */
+ mac_op_mr(op);
+ adsp2100.core.ax1.u = data_read_dag1(op);
+ adsp2100.core.ay1.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xd6: case 0xd7:
+ /* 1101011x xxxxxxxx xxxxxxxx ALU to AR with data read to AX1 & pgm read to AY1 */
+ alu_op_ar(op);
+ adsp2100.core.ax1.u = data_read_dag1(op);
+ adsp2100.core.ay1.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xd8: case 0xd9:
+ /* 1101100x xxxxxxxx xxxxxxxx MAC to MR with data read to MX0 & pgm read to AY1 */
+ mac_op_mr(op);
+ adsp2100.core.mx0.u = data_read_dag1(op);
+ adsp2100.core.ay1.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xda: case 0xdb:
+ /* 1101101x xxxxxxxx xxxxxxxx ALU to AR with data read to MX0 & pgm read to AY1 */
+ alu_op_ar(op);
+ adsp2100.core.mx0.u = data_read_dag1(op);
+ adsp2100.core.ay1.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xdc: case 0xdd:
+ /* 1101110x xxxxxxxx xxxxxxxx MAC to MR with data read to MX1 & pgm read to AY1 */
+ mac_op_mr(op);
+ adsp2100.core.mx1.u = data_read_dag1(op);
+ adsp2100.core.ay1.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xde: case 0xdf:
+ /* 1101111x xxxxxxxx xxxxxxxx ALU to AR with data read to MX1 & pgm read to AY1 */
+ alu_op_ar(op);
+ adsp2100.core.mx1.u = data_read_dag1(op);
+ adsp2100.core.ay1.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xe0: case 0xe1:
+ /* 1110000x xxxxxxxx xxxxxxxx MAC to MR with data read to AX0 & pgm read to MY0 */
+ mac_op_mr(op);
+ adsp2100.core.ax0.u = data_read_dag1(op);
+ adsp2100.core.my0.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xe2: case 0xe3:
+ /* 1110001x xxxxxxxx xxxxxxxx ALU to AR with data read to AX0 & pgm read to MY0 */
+ alu_op_ar(op);
+ adsp2100.core.ax0.u = data_read_dag1(op);
+ adsp2100.core.my0.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xe4: case 0xe5:
+ /* 1110010x xxxxxxxx xxxxxxxx MAC to MR with data read to AX1 & pgm read to MY0 */
+ mac_op_mr(op);
+ adsp2100.core.ax1.u = data_read_dag1(op);
+ adsp2100.core.my0.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xe6: case 0xe7:
+ /* 1110011x xxxxxxxx xxxxxxxx ALU to AR with data read to AX1 & pgm read to MY0 */
+ alu_op_ar(op);
+ adsp2100.core.ax1.u = data_read_dag1(op);
+ adsp2100.core.my0.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xe8: case 0xe9:
+ /* 1110100x xxxxxxxx xxxxxxxx MAC to MR with data read to MX0 & pgm read to MY0 */
+ mac_op_mr(op);
+ adsp2100.core.mx0.u = data_read_dag1(op);
+ adsp2100.core.my0.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xea: case 0xeb:
+ /* 1110101x xxxxxxxx xxxxxxxx ALU to AR with data read to MX0 & pgm read to MY0 */
+ alu_op_ar(op);
+ adsp2100.core.mx0.u = data_read_dag1(op);
+ adsp2100.core.my0.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xec: case 0xed:
+ /* 1110110x xxxxxxxx xxxxxxxx MAC to MR with data read to MX1 & pgm read to MY0 */
+ mac_op_mr(op);
+ adsp2100.core.mx1.u = data_read_dag1(op);
+ adsp2100.core.my0.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xee: case 0xef:
+ /* 1110111x xxxxxxxx xxxxxxxx ALU to AR with data read to MX1 & pgm read to MY0 */
+ alu_op_ar(op);
+ adsp2100.core.mx1.u = data_read_dag1(op);
+ adsp2100.core.my0.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xf0: case 0xf1:
+ /* 1111000x xxxxxxxx xxxxxxxx MAC to MR with data read to AX0 & pgm read to MY1 */
+ mac_op_mr(op);
+ adsp2100.core.ax0.u = data_read_dag1(op);
+ adsp2100.core.my1.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xf2: case 0xf3:
+ /* 1111001x xxxxxxxx xxxxxxxx ALU to AR with data read to AX0 & pgm read to MY1 */
+ alu_op_ar(op);
+ adsp2100.core.ax0.u = data_read_dag1(op);
+ adsp2100.core.my1.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xf4: case 0xf5:
+ /* 1111010x xxxxxxxx xxxxxxxx MAC to MR with data read to AX1 & pgm read to MY1 */
+ mac_op_mr(op);
+ adsp2100.core.ax1.u = data_read_dag1(op);
+ adsp2100.core.my1.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xf6: case 0xf7:
+ /* 1111011x xxxxxxxx xxxxxxxx ALU to AR with data read to AX1 & pgm read to MY1 */
+ alu_op_ar(op);
+ adsp2100.core.ax1.u = data_read_dag1(op);
+ adsp2100.core.my1.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xf8: case 0xf9:
+ /* 1111100x xxxxxxxx xxxxxxxx MAC to MR with data read to MX0 & pgm read to MY1 */
+ mac_op_mr(op);
+ adsp2100.core.mx0.u = data_read_dag1(op);
+ adsp2100.core.my1.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xfa: case 0xfb:
+ /* 1111101x xxxxxxxx xxxxxxxx ALU to AR with data read to MX0 & pgm read to MY1 */
+ alu_op_ar(op);
+ adsp2100.core.mx0.u = data_read_dag1(op);
+ adsp2100.core.my1.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xfc: case 0xfd:
+ /* 1111110x xxxxxxxx xxxxxxxx MAC to MR with data read to MX1 & pgm read to MY1 */
+ mac_op_mr(op);
+ adsp2100.core.mx1.u = data_read_dag1(op);
+ adsp2100.core.my1.u = pgm_read_dag2(op >> 4);
+ break;
+ case 0xfe: case 0xff:
+ /* 1111111x xxxxxxxx xxxxxxxx ALU to AR with data read to MX1 & pgm read to MY1 */
+ alu_op_ar(op);
+ adsp2100.core.mx1.u = data_read_dag1(op);
+ adsp2100.core.my1.u = pgm_read_dag2(op >> 4);
+ break;
+ }
+
+ adsp2100_icount--;
+ } while (adsp2100_icount > 0);
+
+ return cycles - adsp2100_icount;
}