diff options
author | 2014-04-15 17:51:30 +0000 | |
---|---|---|
committer | 2014-04-15 17:51:30 +0000 | |
commit | b5610b50b121b73422bdf5f4ffc53dc2161dc1b3 (patch) | |
tree | ec9525bf9a71b0aab87b04c4020942d13f1d35c4 /src | |
parent | 1c453351846ed5f02be4d9589ed2e01ff859db7d (diff) |
sh2: converted to use delegates, so to finally remove the remaining static variables used by 32x. nw.
Diffstat (limited to 'src')
-rw-r--r-- | src/emu/cpu/sh2/sh2.c | 26 | ||||
-rw-r--r-- | src/emu/cpu/sh2/sh2.h | 43 | ||||
-rw-r--r-- | src/emu/cpu/sh2/sh2comn.c | 39 | ||||
-rw-r--r-- | src/mame/drivers/cps3.c | 28 | ||||
-rw-r--r-- | src/mame/drivers/stv.c | 8 | ||||
-rw-r--r-- | src/mame/includes/cps3.h | 1 | ||||
-rw-r--r-- | src/mess/drivers/saturn.c | 8 | ||||
-rw-r--r-- | src/mess/machine/mega32x.c | 132 | ||||
-rw-r--r-- | src/mess/machine/mega32x.h | 11 |
9 files changed, 139 insertions, 157 deletions
diff --git a/src/emu/cpu/sh2/sh2.c b/src/emu/cpu/sh2/sh2.c index e168ef3daf6..60a949efdba 100644 --- a/src/emu/cpu/sh2/sh2.c +++ b/src/emu/cpu/sh2/sh2.c @@ -166,6 +166,7 @@ ADDRESS_MAP_END sh2_device::sh2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : cpu_device(mconfig, SH2, "SH-2", tag, owner, clock, "sh2", __FILE__) , m_program_config("program", ENDIANNESS_BIG, 32, 32, 0, ADDRESS_MAP_NAME(sh2_internal_map)) + , m_is_slave(0) , m_cpu_type(CPU_TYPE_SH2) , m_cache(CACHE_SIZE + sizeof(internal_sh2_state)) , m_drcuml(NULL) @@ -201,6 +202,7 @@ void sh2_device::device_stop() sh2_device::sh2_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, int cpu_type) : cpu_device(mconfig, type, name, tag, owner, clock, shortname, source) , m_program_config("program", ENDIANNESS_BIG, 32, 32, 0, ADDRESS_MAP_NAME(sh2_internal_map)) + , m_is_slave(0) , m_cpu_type(cpu_type) , m_cache(CACHE_SIZE + sizeof(internal_sh2_state)) , m_drcuml(NULL) @@ -235,23 +237,6 @@ offs_t sh2_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *opro } -void sh2_device::device_config_complete() -{ - // inherit a copy of the static data - const sh2_cpu_core *intf = reinterpret_cast<const sh2_cpu_core *>(static_config()); - if (intf != NULL) - *static_cast<sh2_cpu_core *>(this) = *intf; - - // or initialize to defaults if none provided - else - { - memset(&dma_callback_kludge, 0, sizeof(dma_callback_kludge)); - memset(&dma_callback_fifo_data_available, 0, sizeof(dma_callback_fifo_data_available)); - is_slave = 0; - } -} - - /* speed up delay loops, bail out of tight loops */ #define BUSY_LOOP_HACKS 1 @@ -2421,9 +2406,10 @@ void sh2_device::device_start() m_dma_current_active_timer[1] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh2_device::sh2_dma_current_active_callback), this)); m_dma_current_active_timer[1]->adjust(attotime::never); - m_is_slave = is_slave; - m_dma_callback_kludge = dma_callback_kludge; - m_dma_callback_fifo_data_available = dma_callback_fifo_data_available; + /* resolve callbacks */ + m_dma_kludge_cb.bind_relative_to(*owner()); + m_dma_fifo_data_available_cb.bind_relative_to(*owner()); + m_ftcsr_read_cb.bind_relative_to(*owner()); m_program = &space(AS_PROGRAM); m_direct = &m_program->direct(); diff --git a/src/emu/cpu/sh2/sh2.h b/src/emu/cpu/sh2/sh2.h index f73ef8830d6..21e53f19a4c 100644 --- a/src/emu/cpu/sh2/sh2.h +++ b/src/emu/cpu/sh2/sh2.h @@ -60,12 +60,28 @@ enum SH2_R8, SH2_R9, SH2_R10, SH2_R11, SH2_R12, SH2_R13, SH2_R14, SH2_R15, SH2_EA }; -struct sh2_cpu_core -{ - int is_slave; - int (*dma_callback_kludge)(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size); - int (*dma_callback_fifo_data_available)(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size); -}; + +typedef device_delegate<int (UINT32 src, UINT32 dst, UINT32 data, int size)> sh2_dma_kludge_delegate; +#define SH2_DMA_KLUDGE_CB(name) int name(UINT32 src, UINT32 dst, UINT32 data, int size) + +typedef device_delegate<int (UINT32 src, UINT32 dst, UINT32 data, int size)> sh2_dma_fifo_data_available_delegate; +#define SH2_DMA_FIFO_DATA_AVAILABLE_CB(name) int name(UINT32 src, UINT32 dst, UINT32 data, int size) + +typedef device_delegate<void (UINT32 data)> sh2_ftcsr_read_delegate; +#define SH2_FTCSR_READ_CB(name) void name(UINT32 data) + + +#define MCFG_SH2_IS_SLAVE(_slave) \ + sh2_device::set_is_slave(*device, _slave); + +#define MCFG_SH2_DMA_KLUDGE_CB(_class, _method) \ + sh2_device::set_dma_kludge_callback(*device, sh2_dma_kludge_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner))); + +#define MCFG_SH2_FIFO_DATA_AVAIL_CB(_class, _method) \ + sh2_device::set_dma_fifo_data_available_callback(*device, sh2_dma_fifo_data_available_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner))); + +#define MCFG_SH2_FTCSR_READ_CB(_class, _method) \ + sh2_device::set_ftcsr_read_callback(*device, sh2_ftcsr_read_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner))); /*************************************************************************** @@ -96,7 +112,6 @@ enum class sh2_frontend; class sh2_device : public cpu_device - , public sh2_cpu_core { friend class sh2_frontend; @@ -105,11 +120,15 @@ public: sh2_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock); sh2_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, int cpu_type); + static void set_is_slave(device_t &device, int slave) { downcast<sh2_device &>(device).m_is_slave = slave; } + static void set_dma_kludge_callback(device_t &device, sh2_dma_kludge_delegate callback) { downcast<sh2_device &>(device).m_dma_kludge_cb = callback; } + static void set_dma_fifo_data_available_callback(device_t &device, sh2_dma_fifo_data_available_delegate callback) { downcast<sh2_device &>(device).m_dma_fifo_data_available_cb = callback; } + static void set_ftcsr_read_callback(device_t &device, sh2_ftcsr_read_delegate callback) { downcast<sh2_device &>(device).m_ftcsr_read_cb = callback; } + DECLARE_WRITE32_MEMBER( sh2_internal_w ); DECLARE_READ32_MEMBER( sh2_internal_r ); DECLARE_READ32_MEMBER(sh2_internal_a5); - void sh2_set_ftcsr_read_callback(void (*callback)(UINT32)); void sh2_set_frt_input(int state); void sh2drc_set_options(UINT32 options); void sh2drc_add_pcflush(offs_t address); @@ -119,7 +138,6 @@ public: protected: // device-level overrides - virtual void device_config_complete(); virtual void device_start(); virtual void device_reset(); virtual void device_stop(); @@ -221,10 +239,9 @@ private: UINT8 m_wtcsr; int m_is_slave, m_cpu_type; - int (*m_dma_callback_kludge)(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size); - int (*m_dma_callback_fifo_data_available)(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size); - - void (*m_ftcsr_read_callback)(UINT32 data); + sh2_dma_kludge_delegate m_dma_kludge_cb; + sh2_dma_fifo_data_available_delegate m_dma_fifo_data_available_cb; + sh2_ftcsr_read_delegate m_ftcsr_read_cb; drc_cache m_cache; /* pointer to the DRC code cache */ drcuml_state * m_drcuml; /* DRC UML generator state */ diff --git a/src/emu/cpu/sh2/sh2comn.c b/src/emu/cpu/sh2/sh2comn.c index 0ca03f2d788..d3ecc548db9 100644 --- a/src/emu/cpu/sh2/sh2comn.c +++ b/src/emu/cpu/sh2/sh2comn.c @@ -169,9 +169,9 @@ void sh2_device::sh2_do_dma(int dma) else tempdst = m_active_dma_dst[dma]; - if (m_dma_callback_fifo_data_available) + if (!m_dma_fifo_data_available_cb.isnull()) { - int available = m_dma_callback_fifo_data_available(this, tempsrc, tempdst, 0, m_active_dma_size[dma]); + int available = m_dma_fifo_data_available_cb(tempsrc, tempdst, 0, m_active_dma_size[dma]); if (!available) { @@ -188,7 +188,7 @@ void sh2_device::sh2_do_dma(int dma) dmadata = m_program->read_byte(tempsrc); - if (m_dma_callback_kludge) dmadata = m_dma_callback_kludge(this, tempsrc, tempdst, dmadata, m_active_dma_size[dma]); + if (!m_dma_kludge_cb.isnull()) dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dma]); m_program->write_byte(tempdst, dmadata); if(m_active_dma_incs[dma] == 2) @@ -217,9 +217,9 @@ void sh2_device::sh2_do_dma(int dma) else tempdst = m_active_dma_dst[dma]; - if (m_dma_callback_fifo_data_available) + if (!m_dma_fifo_data_available_cb.isnull()) { - int available = m_dma_callback_fifo_data_available(this, tempsrc, tempdst, 0, m_active_dma_size[dma]); + int available = m_dma_fifo_data_available_cb(tempsrc, tempdst, 0, m_active_dma_size[dma]); if (!available) { @@ -236,7 +236,7 @@ void sh2_device::sh2_do_dma(int dma) // check: should this really be using read_word_32 / write_word_32? dmadata = m_program->read_word(tempsrc); - if (m_dma_callback_kludge) dmadata = m_dma_callback_kludge(this, tempsrc, tempdst, dmadata, m_active_dma_size[dma]); + if (!m_dma_kludge_cb.isnull()) dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dma]); m_program->write_word(tempdst, dmadata); if(m_active_dma_incs[dma] == 2) @@ -264,9 +264,9 @@ void sh2_device::sh2_do_dma(int dma) else tempdst = m_active_dma_dst[dma]; - if (m_dma_callback_fifo_data_available) + if (!m_dma_fifo_data_available_cb.isnull()) { - int available = m_dma_callback_fifo_data_available(this, tempsrc, tempdst, 0, m_active_dma_size[dma]); + int available = m_dma_fifo_data_available_cb(tempsrc, tempdst, 0, m_active_dma_size[dma]); if (!available) { @@ -282,7 +282,7 @@ void sh2_device::sh2_do_dma(int dma) #endif dmadata = m_program->read_dword(tempsrc); - if (m_dma_callback_kludge) dmadata = m_dma_callback_kludge(this, tempsrc, tempdst, dmadata, m_active_dma_size[dma]); + if (!m_dma_kludge_cb.isnull()) dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dma]); m_program->write_dword(tempdst, dmadata); if(m_active_dma_incs[dma] == 2) @@ -309,9 +309,9 @@ void sh2_device::sh2_do_dma(int dma) else tempdst = m_active_dma_dst[dma]; - if (m_dma_callback_fifo_data_available) + if (!m_dma_fifo_data_available_cb.isnull()) { - int available = m_dma_callback_fifo_data_available(this, tempsrc, tempdst, 0, m_active_dma_size[dma]); + int available = m_dma_fifo_data_available_cb(tempsrc, tempdst, 0, m_active_dma_size[dma]); if (!available) { @@ -327,19 +327,19 @@ void sh2_device::sh2_do_dma(int dma) #endif dmadata = m_program->read_dword(tempsrc); - if (m_dma_callback_kludge) dmadata = m_dma_callback_kludge(this, tempsrc, tempdst, dmadata, m_active_dma_size[dma]); + if (!m_dma_kludge_cb.isnull()) dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dma]); m_program->write_dword(tempdst, dmadata); dmadata = m_program->read_dword(tempsrc+4); - if (m_dma_callback_kludge) dmadata = m_dma_callback_kludge(this, tempsrc, tempdst, dmadata, m_active_dma_size[dma]); + if (!m_dma_kludge_cb.isnull()) dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dma]); m_program->write_dword(tempdst+4, dmadata); dmadata = m_program->read_dword(tempsrc+8); - if (m_dma_callback_kludge) dmadata = m_dma_callback_kludge(this, tempsrc, tempdst, dmadata, m_active_dma_size[dma]); + if (!m_dma_kludge_cb.isnull()) dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dma]); m_program->write_dword(tempdst+8, dmadata); dmadata = m_program->read_dword(tempsrc+12); - if (m_dma_callback_kludge) dmadata = m_dma_callback_kludge(this, tempsrc, tempdst, dmadata, m_active_dma_size[dma]); + if (!m_dma_kludge_cb.isnull()) dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dma]); m_program->write_dword(tempdst+12, dmadata); if(m_active_dma_incd[dma] == 2) @@ -704,9 +704,9 @@ READ32_MEMBER( sh2_device::sh2_internal_r ) case 0x04: // TIER, FTCSR, FRC if ( mem_mask == 0x00ff0000 ) { - if ( m_ftcsr_read_callback != NULL ) + if (!m_ftcsr_read_cb.isnull()) { - m_ftcsr_read_callback( (m_m[4] & 0xffff0000) | m_frc ); + m_ftcsr_read_cb((m_m[4] & 0xffff0000) | m_frc); } } sh2_timer_resync(); @@ -741,11 +741,6 @@ READ32_MEMBER( sh2_device::sh2_internal_r ) return m_m[offset]; } -void sh2_device::sh2_set_ftcsr_read_callback(void (*callback)(UINT32)) -{ - m_ftcsr_read_callback = callback; -} - void sh2_device::sh2_set_frt_input(int state) { if(state == PULSE_LINE) diff --git a/src/mame/drivers/cps3.c b/src/mame/drivers/cps3.c index a15e9b6c30a..6068ca12319 100644 --- a/src/mame/drivers/cps3.c +++ b/src/mame/drivers/cps3.c @@ -2325,9 +2325,6 @@ INTERRUPT_GEN_MEMBER(cps3_state::cps3_other_interrupt) } -//static sh2_cpu_core sh2cp_conf_slave = { 1, NULL }; - - void cps3_state::machine_reset() { m_current_table_address = -1; @@ -2426,9 +2423,8 @@ void cps3_state::copy_from_nvram() } -static int cps3_dma_callback(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size) +SH2_DMA_KLUDGE_CB(cps3_state::dma_callback) { - cps3_state *state = device->machine().driver_data<cps3_state>(); /* on the actual CPS3 hardware the SH2 DMA bypasses the encryption. @@ -2450,22 +2446,22 @@ static int cps3_dma_callback(device_t *device, UINT32 src, UINT32 dst, UINT32 da if (src<0x80000) { - int offs = (src&0x07ffff)>>2; - data = data ^ state->cps3_mask(offs*4, state->m_key1, state->m_key2); + int offs = (src & 0x07ffff) >> 2; + data = data ^ cps3_mask(offs * 4, m_key1, m_key2); } else if (src>=0x6000000 && src<0x6800000) { - int offs = (src&0x07fffff)>>2; - if (!state->m_altEncryption) data = data ^ state->cps3_mask(0x6000000+offs*4, state->m_key1, state->m_key2); + int offs = (src & 0x07fffff) >> 2; + if (!m_altEncryption) data = data ^ cps3_mask(0x6000000 + offs * 4, m_key1, m_key2); } else if (src>=0x6800000 && src<0x7000000) { - int offs = (src&0x07fffff)>>2; - if (!state->m_altEncryption) data = data ^ state->cps3_mask(0x6800000+offs*4, state->m_key1, state->m_key2); + int offs = (src & 0x07fffff) >> 2; + if (!m_altEncryption) data = data ^ cps3_mask(0x6800000 + offs * 4, m_key1, m_key2); } else { - //printf("%s :src %08x, dst %08x, returning %08x\n", machine.describe_context(), src, dst, data); + //printf("%s :src %08x, dst %08x, returning %08x\n", machine().describe_context(), src, dst, data); } /* I doubt this is endian safe.. needs checking / fixing */ @@ -2483,12 +2479,6 @@ static int cps3_dma_callback(device_t *device, UINT32 src, UINT32 dst, UINT32 da } - -static const sh2_cpu_core sh2_conf_cps3 = { - 0, // master - cps3_dma_callback -}; - static MACHINE_CONFIG_FRAGMENT( simm1_64mbit ) MCFG_FUJITSU_29F016A_ADD("simm1.0") MCFG_FUJITSU_29F016A_ADD("simm1.1") @@ -2558,7 +2548,7 @@ static MACHINE_CONFIG_START( cps3, cps3_state ) MCFG_CPU_PROGRAM_MAP(cps3_map) MCFG_CPU_VBLANK_INT_DRIVER("screen", cps3_state, cps3_vbl_interrupt) MCFG_CPU_PERIODIC_INT_DRIVER(cps3_state, cps3_other_interrupt, 80) /* ?source? */ - MCFG_CPU_CONFIG(sh2_conf_cps3) + MCFG_SH2_DMA_KLUDGE_CB(cps3_state, dma_callback) MCFG_DEVICE_ADD("scsi", SCSI_PORT, 0) MCFG_SCSIDEV_ADD("scsi:" SCSI_PORT_DEVICE1, "cdrom", SCSICD, SCSI_ID_1) diff --git a/src/mame/drivers/stv.c b/src/mame/drivers/stv.c index 4c6d8e33d07..3404276eb63 100644 --- a/src/mame/drivers/stv.c +++ b/src/mame/drivers/stv.c @@ -921,10 +921,6 @@ DRIVER_INIT_MEMBER(stv_state,nameclv3) DRIVER_INIT_CALL(stv); } - -static const sh2_cpu_core sh2_conf_master = { 0, NULL }; -static const sh2_cpu_core sh2_conf_slave = { 1, NULL }; - static ADDRESS_MAP_START( stv_mem, AS_PROGRAM, 32, stv_state ) AM_RANGE(0x00000000, 0x0007ffff) AM_ROM AM_SHARE("share6") // bios AM_RANGE(0x00100000, 0x0010007f) AM_READWRITE8(stv_SMPC_r, stv_SMPC_w,0xffffffff) @@ -971,12 +967,12 @@ static MACHINE_CONFIG_START( stv, stv_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", SH2, MASTER_CLOCK_352/2) // 28.6364 MHz MCFG_CPU_PROGRAM_MAP(stv_mem) - MCFG_CPU_CONFIG(sh2_conf_master) + MCFG_SH2_IS_SLAVE(0) MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", stv_state, saturn_scanline, "screen", 0, 1) MCFG_CPU_ADD("slave", SH2, MASTER_CLOCK_352/2) // 28.6364 MHz MCFG_CPU_PROGRAM_MAP(stv_mem) - MCFG_CPU_CONFIG(sh2_conf_slave) + MCFG_SH2_IS_SLAVE(1) MCFG_TIMER_DRIVER_ADD_SCANLINE("slave_scantimer", stv_state, saturn_slave_scanline, "screen", 0, 1) MCFG_CPU_ADD("audiocpu", M68000, 11289600) //11.2896 MHz diff --git a/src/mame/includes/cps3.h b/src/mame/includes/cps3.h index fdea9d919ce..3caf2b16bf5 100644 --- a/src/mame/includes/cps3.h +++ b/src/mame/includes/cps3.h @@ -107,6 +107,7 @@ public: DECLARE_DRIVER_INIT(jojoba); DECLARE_DRIVER_INIT(sfiii2); DECLARE_DRIVER_INIT(cps3boot); + SH2_DMA_KLUDGE_CB(dma_callback); virtual void machine_reset(); virtual void video_start(); UINT32 screen_update_cps3(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); diff --git a/src/mess/drivers/saturn.c b/src/mess/drivers/saturn.c index ede20bde87a..7a3a2fa0e88 100644 --- a/src/mess/drivers/saturn.c +++ b/src/mess/drivers/saturn.c @@ -559,10 +559,6 @@ void sat_console_state::nvram_init(nvram_device &nvram, void *data, size_t size) } -static const sh2_cpu_core sh2_conf_master = { 0, NULL }; -static const sh2_cpu_core sh2_conf_slave = { 1, NULL }; - - MACHINE_START_MEMBER(sat_console_state, saturn) { system_time systime; @@ -711,12 +707,12 @@ static MACHINE_CONFIG_START( saturn, sat_console_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", SH2, MASTER_CLOCK_352/2) // 28.6364 MHz MCFG_CPU_PROGRAM_MAP(saturn_mem) - MCFG_CPU_CONFIG(sh2_conf_master) + MCFG_SH2_IS_SLAVE(0) MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", sat_console_state, saturn_scanline, "screen", 0, 1) MCFG_CPU_ADD("slave", SH2, MASTER_CLOCK_352/2) // 28.6364 MHz MCFG_CPU_PROGRAM_MAP(saturn_mem) - MCFG_CPU_CONFIG(sh2_conf_slave) + MCFG_SH2_IS_SLAVE(1) MCFG_TIMER_DRIVER_ADD_SCANLINE("slave_scantimer", sat_console_state, saturn_slave_scanline, "screen", 0, 1) MCFG_CPU_ADD("audiocpu", M68000, 11289600) //256 x 44100 Hz = 11.2896 MHz diff --git a/src/mess/machine/mega32x.c b/src/mess/machine/mega32x.c index 048ef718ab7..0b46e8c6f20 100644 --- a/src/mess/machine/mega32x.c +++ b/src/mess/machine/mega32x.c @@ -199,18 +199,6 @@ GFX check (these don't explicitly fails): #include "machine/mega32x.h" -/* need to make fifo callback part of device */ -static UINT16 fifo_block_a[4]; -static UINT16 fifo_block_b[4]; -static UINT16* current_fifo_block; -static UINT16* current_fifo_readblock; -int current_fifo_write_pos; -int current_fifo_read_pos; -int fifo_block_a_full; -int fifo_block_b_full; - - - const device_type SEGA_32X_NTSC = &device_creator<sega_32x_ntsc_device>; const device_type SEGA_32X_PAL = &device_creator<sega_32x_pal_device>; @@ -362,7 +350,7 @@ READ16_MEMBER( sega_32x_device::_32x_68k_a15106_r ) retval = m_a15106_reg; - if (fifo_block_a_full && fifo_block_b_full) retval |= 0x8080; + if (m_fifo_block_a_full && m_fifo_block_b_full) retval |= 0x8080; return retval; } @@ -390,12 +378,12 @@ WRITE16_MEMBER( sega_32x_device::_32x_68k_a15106_w ) if((m_a15106_reg & 4) == 0) // clears the FIFO state { - current_fifo_block = fifo_block_a; - current_fifo_readblock = fifo_block_b; - current_fifo_write_pos = 0; - current_fifo_read_pos = 0; - fifo_block_a_full = 0; - fifo_block_b_full = 0; + m_current_fifo_block = m_fifo_block_a; + m_current_fifo_readblock = m_fifo_block_b; + m_current_fifo_write_pos = 0; + m_current_fifo_read_pos = 0; + m_fifo_block_a_full = 0; + m_fifo_block_b_full = 0; } //printf("_32x_68k_a15106_w %04x\n", data); @@ -440,44 +428,44 @@ READ16_MEMBER( sega_32x_device::_32x_dreq_common_r ) return 0xffff; } - UINT16 retdat = current_fifo_readblock[current_fifo_read_pos]; + UINT16 retdat = m_current_fifo_readblock[m_current_fifo_read_pos]; - current_fifo_read_pos++; + m_current_fifo_read_pos++; // printf("reading FIFO!\n"); - if (current_fifo_readblock == fifo_block_a && !fifo_block_a_full) + if (m_current_fifo_readblock == m_fifo_block_a && !m_fifo_block_a_full) printf("Fifo block a isn't filled!\n"); - if (current_fifo_readblock == fifo_block_b && !fifo_block_b_full) + if (m_current_fifo_readblock == m_fifo_block_b && !m_fifo_block_b_full) printf("%08x Fifo block b isn't filled!\n",space.device().safe_pc()); - if (current_fifo_read_pos==4) + if (m_current_fifo_read_pos==4) { - if (current_fifo_readblock == fifo_block_a) + if (m_current_fifo_readblock == m_fifo_block_a) { - fifo_block_a_full = 0; + m_fifo_block_a_full = 0; - if (fifo_block_b_full) + if (m_fifo_block_b_full) { - current_fifo_readblock = fifo_block_b; - current_fifo_block = fifo_block_a; + m_current_fifo_readblock = m_fifo_block_b; + m_current_fifo_block = m_fifo_block_a; } - current_fifo_read_pos = 0; + m_current_fifo_read_pos = 0; } - else if (current_fifo_readblock == fifo_block_b) + else if (m_current_fifo_readblock == m_fifo_block_b) { - fifo_block_b_full = 0; + m_fifo_block_b_full = 0; - if (fifo_block_a_full) + if (m_fifo_block_a_full) { - current_fifo_readblock = fifo_block_a; - current_fifo_block = fifo_block_b; + m_current_fifo_readblock = m_fifo_block_a; + m_current_fifo_block = m_fifo_block_b; } - current_fifo_read_pos = 0; + m_current_fifo_read_pos = 0; } } @@ -544,13 +532,13 @@ WRITE16_MEMBER( sega_32x_device::_32x_dreq_common_w ) return; } - if (current_fifo_block==fifo_block_a && fifo_block_a_full) + if (m_current_fifo_block==m_fifo_block_a && m_fifo_block_a_full) { printf("attempt to write to Full Fifo block a!\n"); return; } - if (current_fifo_block==fifo_block_b && fifo_block_b_full) + if (m_current_fifo_block==m_fifo_block_b && m_fifo_block_b_full) { printf("attempt to write to Full Fifo block b!\n"); return; @@ -562,40 +550,40 @@ WRITE16_MEMBER( sega_32x_device::_32x_dreq_common_w ) return; } - current_fifo_block[current_fifo_write_pos] = data; - current_fifo_write_pos++; + m_current_fifo_block[m_current_fifo_write_pos] = data; + m_current_fifo_write_pos++; - if (current_fifo_write_pos==4) + if (m_current_fifo_write_pos==4) { - if (current_fifo_block==fifo_block_a) + if (m_current_fifo_block==m_fifo_block_a) { - fifo_block_a_full = 1; - if (!fifo_block_b_full) + m_fifo_block_a_full = 1; + if (!m_fifo_block_b_full) { - current_fifo_block = fifo_block_b; - current_fifo_readblock = fifo_block_a; + m_current_fifo_block = m_fifo_block_b; + m_current_fifo_readblock = m_fifo_block_a; // incase we have a stalled DMA in progress, let the SH2 know there is data available m_master_cpu->sh2_notify_dma_data_available(); m_slave_cpu->sh2_notify_dma_data_available(); } - current_fifo_write_pos = 0; + m_current_fifo_write_pos = 0; } else { - fifo_block_b_full = 1; + m_fifo_block_b_full = 1; - if (!fifo_block_a_full) + if (!m_fifo_block_a_full) { - current_fifo_block = fifo_block_a; - current_fifo_readblock = fifo_block_b; + m_current_fifo_block = m_fifo_block_a; + m_current_fifo_readblock = m_fifo_block_b; // incase we have a stalled DMA in progress, let the SH2 know there is data available m_master_cpu->sh2_notify_dma_data_available(); m_slave_cpu->sh2_notify_dma_data_available(); } - current_fifo_write_pos = 0; + m_current_fifo_write_pos = 0; } } @@ -1598,15 +1586,14 @@ void sega_32x_device::_32x_interrupt_cb(int scanline, int irq6) } - -int _32x_fifo_available_callback(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size) +SH2_DMA_FIFO_DATA_AVAILABLE_CB(sega_32x_device::_32x_fifo_available_callback) { if (src==0x4012) { - if (current_fifo_readblock==fifo_block_a && fifo_block_a_full) + if (m_current_fifo_readblock==m_fifo_block_a && m_fifo_block_a_full) return 1; - if (current_fifo_readblock==fifo_block_b && fifo_block_b_full) + if (m_current_fifo_readblock==m_fifo_block_b && m_fifo_block_b_full) return 1; return 0; @@ -1745,9 +1732,6 @@ void sega_32x_device::_32x_render_videobuffer_to_screenbuffer(int x, UINT32 prio } } -static const sh2_cpu_core sh2_conf_master = { 0, NULL, _32x_fifo_available_callback }; -static const sh2_cpu_core sh2_conf_slave = { 1, NULL, _32x_fifo_available_callback }; - #if 0 // for now we just use the regular loading because we have 2 different BIOS roms, and you can't use -bios within a device for obvious reasons ROM_START( 32x ) @@ -1775,17 +1759,20 @@ static MACHINE_CONFIG_FRAGMENT( _32x_ntsc ) #ifndef _32X_SWAP_MASTER_SLAVE_HACK MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_NTSC*3)/7 ) MCFG_CPU_PROGRAM_MAP(sh2_main_map) - MCFG_CPU_CONFIG(sh2_conf_master) + MCFG_SH2_IS_SLAVE(0) + MCFG_SH2_FIFO_DATA_AVAIL_CB(sega_32x_device, _32x_fifo_available_callback) #endif MCFG_CPU_ADD("32x_slave_sh2", SH2, (MASTER_CLOCK_NTSC*3)/7 ) MCFG_CPU_PROGRAM_MAP(sh2_slave_map) - MCFG_CPU_CONFIG(sh2_conf_slave) + MCFG_SH2_IS_SLAVE(1) + MCFG_SH2_FIFO_DATA_AVAIL_CB(sega_32x_device, _32x_fifo_available_callback) #ifdef _32X_SWAP_MASTER_SLAVE_HACK MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_NTSC*3)/7 ) MCFG_CPU_PROGRAM_MAP(sh2_main_map) - MCFG_CPU_CONFIG(sh2_conf_master) + MCFG_SH2_IS_SLAVE(0) + MCFG_SH2_FIFO_DATA_AVAIL_CB(sega_32x_device, _32x_fifo_available_callback) #endif MCFG_DAC_ADD("lch_pwm") @@ -1802,17 +1789,20 @@ static MACHINE_CONFIG_FRAGMENT( _32x_pal ) #ifndef _32X_SWAP_MASTER_SLAVE_HACK MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_PAL*3)/7 ) MCFG_CPU_PROGRAM_MAP(sh2_main_map) - MCFG_CPU_CONFIG(sh2_conf_master) + MCFG_SH2_IS_SLAVE(0) + MCFG_SH2_FIFO_DATA_AVAIL_CB(sega_32x_device, _32x_fifo_available_callback) #endif MCFG_CPU_ADD("32x_slave_sh2", SH2, (MASTER_CLOCK_PAL*3)/7 ) MCFG_CPU_PROGRAM_MAP(sh2_slave_map) - MCFG_CPU_CONFIG(sh2_conf_slave) + MCFG_SH2_IS_SLAVE(1) + MCFG_SH2_FIFO_DATA_AVAIL_CB(sega_32x_device, _32x_fifo_available_callback) #ifdef _32X_SWAP_MASTER_SLAVE_HACK MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_PAL*3)/7 ) MCFG_CPU_PROGRAM_MAP(sh2_main_map) - MCFG_CPU_CONFIG(sh2_conf_master) + MCFG_SH2_IS_SLAVE(0) + MCFG_SH2_FIFO_DATA_AVAIL_CB(sega_32x_device, _32x_fifo_available_callback) #endif MCFG_DAC_ADD("lch_pwm") @@ -1882,12 +1872,12 @@ void sega_32x_device::device_reset() m_32x_displaymode = 0; m_32x_240mode = 0; - current_fifo_block = fifo_block_a; - current_fifo_readblock = fifo_block_b; - current_fifo_write_pos = 0; - current_fifo_read_pos = 0; - fifo_block_a_full = 0; - fifo_block_b_full = 0; + m_current_fifo_block = m_fifo_block_a; + m_current_fifo_readblock = m_fifo_block_b; + m_current_fifo_write_pos = 0; + m_current_fifo_read_pos = 0; + m_fifo_block_a_full = 0; + m_fifo_block_b_full = 0; m_32x_hcount_compare_val = -1; m_32x_hcount_reg = 0; diff --git a/src/mess/machine/mega32x.h b/src/mess/machine/mega32x.h index 548c463195b..2cc101be954 100644 --- a/src/mess/machine/mega32x.h +++ b/src/mess/machine/mega32x.h @@ -112,6 +112,8 @@ public: DECLARE_WRITE16_MEMBER( _32x_sh2_master_401e_w ); DECLARE_WRITE16_MEMBER( _32x_sh2_slave_401e_w ); + SH2_DMA_FIFO_DATA_AVAILABLE_CB(_32x_fifo_available_callback); + void _32x_render_videobuffer_to_screenbuffer_helper(int scanline); void _32x_render_videobuffer_to_screenbuffer(int x, UINT32 priority, UINT16 &lineptr); int sh2_master_pwmint_enable, sh2_slave_pwmint_enable; @@ -193,6 +195,15 @@ private: UINT16* m_32x_palette; UINT16* m_32x_palette_lookup; + UINT16 m_fifo_block_a[4]; + UINT16 m_fifo_block_b[4]; + UINT16* m_current_fifo_block; + UINT16* m_current_fifo_readblock; + int m_current_fifo_write_pos; + int m_current_fifo_read_pos; + int m_fifo_block_a_full; + int m_fifo_block_b_full; + required_device<palette_device> m_palette; }; |