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author Aaron Giles <aaron@aarongiles.com>2008-11-22 18:38:41 +0000
committer Aaron Giles <aaron@aarongiles.com>2008-11-22 18:38:41 +0000
commit9ee2f770aa2c3f2dfbb9b6a65a689b68bc0aa4dd (patch)
tree2bfa92601a711c73c397915857962e937ccf1414 /src
parent7173ebcdba0a5ef66cf08f3ba2d155bede8111ba (diff)
Converted a bunch of CPU cores over to the new memory functions.
Diffstat (limited to 'src')
-rw-r--r--src/emu/cpu/alph8201/alph8201.c7
-rw-r--r--src/emu/cpu/alph8201/alph8201.h8
-rw-r--r--src/emu/cpu/apexc/apexc.c12
-rw-r--r--src/emu/cpu/apexc/apexc.h4
-rw-r--r--src/emu/cpu/arm/arm.c14
-rw-r--r--src/emu/cpu/arm7/arm7core.c16
-rw-r--r--src/emu/cpu/arm7/arm7exec.c4
-rw-r--r--src/emu/cpu/asap/asapdasm.c7
-rw-r--r--src/emu/cpu/ccpu/ccpu.c20
-rw-r--r--src/emu/cpu/cp1610/cp1610.c7
-rw-r--r--src/emu/cpu/cp1610/cp1610.h6
-rw-r--r--src/emu/cpu/cubeqcpu/cubeqcpu.c25
-rw-r--r--src/emu/cpu/drcfe.c5
-rw-r--r--src/emu/cpu/dsp32/dsp32.c25
-rw-r--r--src/emu/cpu/dsp32/dsp32dis.c2
-rw-r--r--src/emu/cpu/dsp56k/dsp56k.c9
-rw-r--r--src/emu/cpu/dsp56k/dsp56ops.c46
-rw-r--r--src/emu/cpu/dsp56k/dsp56pcu.c6
-rw-r--r--src/emu/cpu/e132xs/e132xs.c72
-rw-r--r--src/emu/cpu/e132xs/e132xs.h20
-rw-r--r--src/emu/cpu/f8/f8.c35
-rw-r--r--src/emu/cpu/g65816/g65816.c2
-rw-r--r--src/emu/cpu/g65816/g65816.h6
-rw-r--r--src/emu/cpu/g65816/g65816cm.h1
-rw-r--r--src/emu/cpu/h6280/h6280.c6
-rw-r--r--src/emu/cpu/h6280/h6280ops.h34
-rw-r--r--src/emu/cpu/i386/i386.c8
-rw-r--r--src/emu/cpu/i386/i386.h113
-rw-r--r--src/emu/cpu/i8085/i8085.c18
-rw-r--r--src/emu/cpu/i8085/i8085cpu.h12
-rw-r--r--src/emu/cpu/i86/i286.c5
-rw-r--r--src/emu/cpu/i86/i86.c7
-rw-r--r--src/emu/cpu/i86/i86.h24
-rw-r--r--src/emu/cpu/i86/i86mem.c60
-rw-r--r--src/emu/cpu/i86/i86mem.h13
-rw-r--r--src/emu/cpu/i8x41/i8x41.c89
-rw-r--r--src/emu/cpu/i8x41/i8x41ops.c194
-rw-r--r--src/emu/cpu/i960/i960.c1807
38 files changed, 1383 insertions, 1366 deletions
diff --git a/src/emu/cpu/alph8201/alph8201.c b/src/emu/cpu/alph8201/alph8201.c
index 00bdeb12fda..a66da3f257e 100644
--- a/src/emu/cpu/alph8201/alph8201.c
+++ b/src/emu/cpu/alph8201/alph8201.c
@@ -147,6 +147,7 @@ Timming
****************************************************************************/
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "deprecat.h"
#include "alph8201.h"
@@ -195,6 +196,9 @@ typedef struct
#if HANDLE_HALT_LINE
UINT8 halt; /* halt input line */
#endif
+
+ const device_config *device;
+ const address_space *program;
} ALPHA8201_Regs;
/* The opcode table now is a combination of cycle counts and function pointers */
@@ -664,6 +668,9 @@ static const s_opcode opcode_8301[256]=
****************************************************************************/
static CPU_INIT( ALPHA8201 )
{
+ R.device = device;
+ R.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+
state_save_register_item_array("ALPHA8201", device->tag, 0, R.RAM);
state_save_register_item("ALPHA8201", device->tag, 0, R.PREVPC);
state_save_register_item("ALPHA8201", device->tag, 0, PC);
diff --git a/src/emu/cpu/alph8201/alph8201.h b/src/emu/cpu/alph8201/alph8201.h
index 21f52072c2c..376a7d16014 100644
--- a/src/emu/cpu/alph8201/alph8201.h
+++ b/src/emu/cpu/alph8201/alph8201.h
@@ -47,26 +47,26 @@ extern CPU_GET_INFO( alpha8301 );
/*
* Read a UINT8 from given memory location
*/
-#define ALPHA8201_RDMEM(A) ((unsigned)program_read_byte_8le(A))
+#define ALPHA8201_RDMEM(A) ((unsigned)memory_read_byte_8le(R.program, A))
/*
* Write a UINT8 to given memory location
*/
-#define ALPHA8201_WRMEM(A,V) (program_write_byte_8le(A,V))
+#define ALPHA8201_WRMEM(A,V) (memory_write_byte_8le(R.program, A,V))
/*
* ALPHA8201_RDOP() is identical to ALPHA8201_RDMEM() except it is used for reading
* opcodes. In case of system with memory mapped I/O, this function can be
* used to greatly speed up emulation
*/
-#define ALPHA8201_RDOP(A) ((unsigned)program_decrypted_read_byte(A))
+#define ALPHA8201_RDOP(A) ((unsigned)memory_decrypted_read_byte(R.program, A))
/*
* ALPHA8201_RDOP_ARG() is identical to ALPHA8201_RDOP() except it is used for reading
* opcode arguments. This difference can be used to support systems that
* use different encoding mechanisms for opcodes and opcode arguments
*/
-#define ALPHA8201_RDOP_ARG(A) ((unsigned)program_raw_read_byte(A))
+#define ALPHA8201_RDOP_ARG(A) ((unsigned)memory_raw_read_byte(R.program, A))
CPU_DISASSEMBLE( ALPHA8201 );
diff --git a/src/emu/cpu/apexc/apexc.c b/src/emu/cpu/apexc/apexc.c
index 6dd70f45375..5247d9aa46c 100644
--- a/src/emu/cpu/apexc/apexc.c
+++ b/src/emu/cpu/apexc/apexc.c
@@ -323,6 +323,7 @@ field: X address D Function Y address D (part 2)
another track.
*/
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include "cpuintrf.h"
#include "debugger.h"
#include "apexc.h"
@@ -339,6 +340,10 @@ typedef struct
int running; /* 1 flag: */
/* running: flag implied by the existence of the stop instruction */
+
+ const device_config *device;
+ const address_space *program;
+ const address_space *io;
} apexc_regs;
static apexc_regs apexc;
@@ -447,12 +452,12 @@ static void word_write(int address, UINT32 data, UINT32 mask)
static int papertape_read(void)
{
- return io_read_byte_8be(0) & 0x1f;
+ return memory_read_byte_8be(apexc.io, 0) & 0x1f;
}
static void papertape_punch(int data)
{
- io_write_byte_8be(0, data);
+ memory_write_byte_8be(apexc.io, 0, data);
}
/*
@@ -769,6 +774,9 @@ special_fetch:
static CPU_INIT( apexc )
{
+ apexc.device = device;
+ apexc.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ apexc.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
}
static CPU_RESET( apexc )
diff --git a/src/emu/cpu/apexc/apexc.h b/src/emu/cpu/apexc/apexc.h
index 25f9429034d..18a03b38f9f 100644
--- a/src/emu/cpu/apexc/apexc.h
+++ b/src/emu/cpu/apexc/apexc.h
@@ -21,8 +21,8 @@ enum
CPU_GET_INFO( apexc );
#ifndef SUPPORT_ODD_WORD_SIZES
-#define apexc_readmem(address) program_read_dword_32be((address)<<2)
-#define apexc_writemem(address, data) program_write_dword_32be((address)<<2, (data))
+#define apexc_readmem(address) memory_read_dword_32be(apexc.program, (address)<<2)
+#define apexc_writemem(address, data) memory_write_dword_32be(apexc.program, (address)<<2, (data))
/* eewww ! - Fortunately, there is no memory mapped I/O, so we can simulate masked write
without danger */
#define apexc_writemem_masked(address, data, mask) \
diff --git a/src/emu/cpu/arm/arm.c b/src/emu/cpu/arm/arm.c
index 51b9216e66e..1e0f0446605 100644
--- a/src/emu/cpu/arm/arm.c
+++ b/src/emu/cpu/arm/arm.c
@@ -15,6 +15,7 @@
*/
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include "arm.h"
#include "debugger.h"
@@ -231,6 +232,7 @@ typedef struct
UINT8 pendingFiq;
cpu_irq_callback irq_callback;
const device_config *device;
+ const address_space *program;
} ARM_REGS;
static ARM_REGS arm;
@@ -252,18 +254,18 @@ static void arm_check_irq_state(void);
INLINE void cpu_write32( int addr, UINT32 data )
{
/* Unaligned writes are treated as normal writes */
- program_write_dword_32le(addr&ADDRESS_MASK,data);
+ memory_write_dword_32le(arm.program, addr&ADDRESS_MASK,data);
if (ARM_DEBUG_CORE && addr&3) logerror("%08x: Unaligned write %08x\n",R15,addr);
}
INLINE void cpu_write8( int addr, UINT8 data )
{
- program_write_byte_32le(addr,data);
+ memory_write_byte_32le(arm.program,addr,data);
}
INLINE UINT32 cpu_read32( int addr )
{
- UINT32 result = program_read_dword_32le(addr&ADDRESS_MASK);
+ UINT32 result = memory_read_dword_32le(arm.program,addr&ADDRESS_MASK);
/* Unaligned reads rotate the word, they never combine words */
if (addr&3) {
@@ -283,7 +285,7 @@ INLINE UINT32 cpu_read32( int addr )
INLINE UINT8 cpu_read8( int addr )
{
- return program_read_byte_32le(addr);
+ return memory_read_byte_32le(arm.program, addr);
}
INLINE UINT32 GetRegister( int rIndex )
@@ -306,6 +308,7 @@ static CPU_RESET( arm )
memset(&arm, 0, sizeof(arm));
arm.irq_callback = save_irqcallback;
arm.device = device;
+ arm.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
/* start up in SVC mode with interrupts disabled. */
R15 = eARM_MODE_SVC|I_MASK|F_MASK;
@@ -329,7 +332,7 @@ static CPU_EXECUTE( arm )
/* load instruction */
pc = R15;
- insn = program_decrypted_read_dword( pc & ADDRESS_MASK );
+ insn = memory_decrypted_read_dword( arm.program, pc & ADDRESS_MASK );
switch (insn >> INSN_COND_SHIFT)
{
@@ -514,6 +517,7 @@ static CPU_INIT( arm )
{
arm.irq_callback = irqcallback;
arm.device = device;
+ arm.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
state_save_register_item_array("arm", device->tag, 0, arm.sArmRegister);
state_save_register_item_array("arm", device->tag, 0, arm.coproRegister);
diff --git a/src/emu/cpu/arm7/arm7core.c b/src/emu/cpu/arm7/arm7core.c
index 6a9a32aa173..4da7777b41c 100644
--- a/src/emu/cpu/arm7/arm7core.c
+++ b/src/emu/cpu/arm7/arm7core.c
@@ -77,6 +77,7 @@
By Bryan McPhail (bmcphail@tendril.co.uk) and Phil Stroffolino
*****************************************************************************/
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include <stdarg.h>
#include "deprecat.h"
@@ -139,19 +140,19 @@ char *(*arm7_dasm_cop_do_callback)(char *pBuf, UINT32 opcode, char *pConditionCo
INLINE void arm7_cpu_write32(UINT32 addr, UINT32 data)
{
addr &= ~3;
- program_write_dword_32le(addr, data);
+ memory_write_dword_32le(ARM7.program, addr, data);
}
INLINE void arm7_cpu_write16(UINT32 addr, UINT16 data)
{
addr &= ~1;
- program_write_word_32le(addr, data);
+ memory_write_word_32le(ARM7.program, addr, data);
}
INLINE void arm7_cpu_write8(UINT32 addr, UINT8 data)
{
- program_write_byte_32le(addr, data);
+ memory_write_byte_32le(ARM7.program, addr, data);
}
INLINE UINT32 arm7_cpu_read32(offs_t addr)
@@ -160,12 +161,12 @@ INLINE UINT32 arm7_cpu_read32(offs_t addr)
if (addr & 3)
{
- result = program_read_dword_32le(addr & ~3);
+ result = memory_read_dword_32le(ARM7.program, addr & ~3);
result = (result >> (8 * (addr & 3))) | (result << (32 - (8 * (addr & 3))));
}
else
{
- result = program_read_dword_32le(addr);
+ result = memory_read_dword_32le(ARM7.program, addr);
}
return result;
@@ -175,7 +176,7 @@ INLINE UINT16 arm7_cpu_read16(offs_t addr)
{
UINT16 result;
- result = program_read_word_32le(addr & ~1);
+ result = memory_read_word_32le(ARM7.program, addr & ~1);
if (addr & 1)
{
@@ -188,7 +189,7 @@ INLINE UINT16 arm7_cpu_read16(offs_t addr)
INLINE UINT8 arm7_cpu_read8(offs_t addr)
{
// Handle through normal 8 bit handler (for 32 bit cpu)
- return program_read_byte_32le(addr);
+ return memory_read_byte_32le(ARM7.program, addr);
}
/***************
@@ -527,6 +528,7 @@ static void arm7_core_reset(const device_config *device)
memset(&ARM7, 0, sizeof(ARM7));
ARM7.irq_callback = save_irqcallback;
ARM7.device = device;
+ ARM7.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
/* start up in SVC mode with interrupts disabled. */
SwitchMode(eARM7_MODE_SVC);
diff --git a/src/emu/cpu/arm7/arm7exec.c b/src/emu/cpu/arm7/arm7exec.c
index d854ea22241..a712b980956 100644
--- a/src/emu/cpu/arm7/arm7exec.c
+++ b/src/emu/cpu/arm7/arm7exec.c
@@ -58,7 +58,7 @@
INT32 offs;
pc = R15;
- insn = program_decrypted_read_word(pc & (~1));
+ insn = memory_decrypted_read_word(ARM7.program, pc & (~1));
ARM7_ICOUNT -= (3 - thumbCycles[insn >> 8]);
switch ((insn & THUMB_INSN_TYPE) >> THUMB_INSN_TYPE_SHIFT)
{
@@ -1168,7 +1168,7 @@
/* load 32 bit instruction */
pc = R15;
- insn = program_decrypted_read_dword(pc);
+ insn = memory_decrypted_read_dword(ARM7.program, pc);
/* process condition codes for this instruction */
switch (insn >> INSN_COND_SHIFT)
diff --git a/src/emu/cpu/asap/asapdasm.c b/src/emu/cpu/asap/asapdasm.c
index 85aba5d7d22..6b6a677653a 100644
--- a/src/emu/cpu/asap/asapdasm.c
+++ b/src/emu/cpu/asap/asapdasm.c
@@ -29,13 +29,6 @@ static const char *const condition[16] =
/***************************************************************************
- MEMORY ACCESSORS
-***************************************************************************/
-
-#define ROPCODE(pc) program_decrypted_read_dword(pc)
-
-
-/***************************************************************************
CODE CODE
***************************************************************************/
diff --git a/src/emu/cpu/ccpu/ccpu.c b/src/emu/cpu/ccpu/ccpu.c
index 1eb4d25ad27..c26a2f60751 100644
--- a/src/emu/cpu/ccpu/ccpu.c
+++ b/src/emu/cpu/ccpu/ccpu.c
@@ -8,6 +8,7 @@
***************************************************************************/
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "ccpu.h"
@@ -38,6 +39,11 @@ typedef struct
UINT8 waiting;
UINT8 watchdog;
+
+ const device_config *device;
+ const address_space *program;
+ const address_space *data;
+ const address_space *io;
} ccpuRegs;
@@ -55,13 +61,13 @@ static int ccpu_icount;
MACROS
***************************************************************************/
-#define READOP(a) (program_decrypted_read_byte(a))
+#define READOP(a) (memory_decrypted_read_byte(ccpu.program, a))
-#define RDMEM(a) (data_read_word_16be((a) * 2) & 0xfff)
-#define WRMEM(a,v) (data_write_word_16be((a) * 2, (v)))
+#define RDMEM(a) (memory_read_word_16be(ccpu.data, (a) * 2) & 0xfff)
+#define WRMEM(a,v) (memory_write_word_16be(ccpu.data, (a) * 2, (v)))
-#define READPORT(a) (io_read_byte_8be(a))
-#define WRITEPORT(a,v) (io_write_byte_8be((a), (v)))
+#define READPORT(a) (memory_read_byte_8be(ccpu.io, a))
+#define WRITEPORT(a,v) (memory_write_byte_8be(ccpu.io, (a), (v)))
#define SET_A0() do { ccpu.a0flag = ccpu.A; } while (0)
#define SET_CMP_VAL(x) do { ccpu.cmpacc = *ccpu.acc; ccpu.cmpval = (x) & 0xfff; } while (0)
@@ -140,6 +146,10 @@ static CPU_INIT( ccpu )
/* copy input params */
ccpu.external_input = configdata->external_input ? configdata->external_input : read_jmi;
ccpu.vector_callback = configdata->vector_callback;
+ ccpu.device = device;
+ ccpu.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ ccpu.data = memory_find_address_space(device, ADDRESS_SPACE_DATA);
+ ccpu.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
state_save_register_item("ccpu", device->tag, 0, ccpu.PC);
state_save_register_item("ccpu", device->tag, 0, ccpu.A);
diff --git a/src/emu/cpu/cp1610/cp1610.c b/src/emu/cpu/cp1610/cp1610.c
index 895c0efaf98..26456f10c1a 100644
--- a/src/emu/cpu/cp1610/cp1610.c
+++ b/src/emu/cpu/cp1610/cp1610.c
@@ -21,6 +21,7 @@
*
*****************************************************************************/
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include "cpuexec.h"
#include "debugger.h"
#include "cp1610.h"
@@ -36,7 +37,6 @@ typedef struct {
int intr_enabled;
//int (*reset_callback)(void);
cpu_irq_callback irq_callback;
- const device_config *device;
UINT16 intr_vector;
int reset_state;
int intr_state;
@@ -45,6 +45,8 @@ typedef struct {
int intr_pending;
int intrm_pending;
int mask_interrupts;
+ const device_config *device;
+ const address_space *program;
} cp1610_Regs;
static int cp1610_icount;
@@ -1550,7 +1552,7 @@ static void cp1610_xori(int d)
static CPU_RESET( cp1610 )
{
/* This is how we set the reset vector */
- cpu_set_input_line(device->machine->activecpu, CP1610_RESET, PULSE_LINE);
+ cpu_set_input_line(device, CP1610_RESET, PULSE_LINE);
}
/***************************************************
@@ -3392,6 +3394,7 @@ static CPU_INIT( cp1610 )
cp1610.intrm_pending = 0;
cp1610.irq_callback = irqcallback;
cp1610.device = device;
+ cp1610.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
}
static void cp1610_set_irq_line(UINT32 irqline, int state)
diff --git a/src/emu/cpu/cp1610/cp1610.h b/src/emu/cpu/cp1610/cp1610.h
index cc1d86eb5f7..4ce5def761e 100644
--- a/src/emu/cpu/cp1610/cp1610.h
+++ b/src/emu/cpu/cp1610/cp1610.h
@@ -41,8 +41,8 @@ CPU_GET_INFO( cp1610 );
CPU_DISASSEMBLE( cp1610 );
// Temporary
-#define cp1610_readop(A) program_read_word_16be((A)<<1)
-#define cp1610_readmem16(A) program_read_word_16be((A)<<1)
-#define cp1610_writemem16(A,B) program_write_word_16be((A)<<1,B)
+#define cp1610_readop(A) memory_read_word_16be(cp1610.program, (A)<<1)
+#define cp1610_readmem16(A) memory_read_word_16be(cp1610.program, (A)<<1)
+#define cp1610_writemem16(A,B) memory_write_word_16be(cp1610.program, (A)<<1,B)
#endif /* __CP1610_H__ */
diff --git a/src/emu/cpu/cubeqcpu/cubeqcpu.c b/src/emu/cpu/cubeqcpu/cubeqcpu.c
index 6c07e58ae33..a32ad4cae86 100644
--- a/src/emu/cpu/cubeqcpu/cubeqcpu.c
+++ b/src/emu/cpu/cubeqcpu/cubeqcpu.c
@@ -10,6 +10,7 @@
***************************************************************************/
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "deprecat.h"
#include "cubeqcpu.h"
@@ -127,6 +128,9 @@ typedef struct
void (*dac_w)(UINT16 data);
UINT16 *sound_data;
+
+ const device_config *device;
+ const address_space *program;
} cquestsnd_state;
@@ -163,6 +167,9 @@ typedef struct
UINT8 wc;
UINT8 rc;
UINT8 clkcnt;
+
+ const device_config *device;
+ const address_space *program;
} cquestrot_state;
@@ -204,6 +211,9 @@ typedef struct
UINT8 *ptr_ram;
UINT32 *e_stack;
UINT32 *o_stack;
+
+ const device_config *device;
+ const address_space *program;
} cquestlin_state;
@@ -343,6 +353,9 @@ static CPU_INIT( cquestsnd )
cquestsnd.dac_w = _config->dac_w;
cquestsnd.sound_data = (UINT16*)memory_region(device->machine, _config->sound_data_region);
+
+ cquestsnd.device = device;
+ cquestsnd.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
/* Allocate RAM shared with 68000 */
cquestsnd.sram = malloc(4096);
@@ -411,6 +424,9 @@ static CPU_INIT( cquestrot )
cquestrot.dram = malloc(16384 * sizeof(UINT16)); /* Shared with 68000 */
cquestrot.sram = malloc(2048 * sizeof(UINT16)); /* Private */
+ cquestrot.device = device;
+ cquestrot.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+
cquestrot_state_register(device, "cquestrot");
}
@@ -489,6 +505,9 @@ static CPU_INIT( cquestlin )
cquestlin.e_stack = malloc(32768 * sizeof(UINT32)); /* Stack DRAM: 32kx20 */
cquestlin.o_stack = malloc(32768 * sizeof(UINT32)); /* Stack DRAM: 32kx20 */
+ cquestlin.device = device;
+ cquestlin.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+
cquestlin_state_register(device, "cquestlin");
}
@@ -549,7 +568,7 @@ static CPU_EXECUTE( cquestsnd )
do
{
/* Decode the instruction */
- UINT64 inst = program_decrypted_read_qword(SND_PC << 3);
+ UINT64 inst = memory_decrypted_read_qword(cquestsnd.program, SND_PC << 3);
UINT32 inslow = inst & 0xffffffff;
UINT32 inshig = inst >> 32;
@@ -883,7 +902,7 @@ static CPU_EXECUTE( cquestrot )
do
{
/* Decode the instruction */
- UINT64 inst = program_decrypted_read_qword(ROT_PC << 3);
+ UINT64 inst = memory_decrypted_read_qword(cquestrot.program, ROT_PC << 3);
UINT32 inslow = inst & 0xffffffff;
UINT32 inshig = inst >> 32;
@@ -1405,7 +1424,7 @@ static CPU_EXECUTE( cquestlin )
/* Are we executing the foreground or backgroud program? */
int prog = (cquestlin.clkcnt & 3) ? BACKGROUND : FOREGROUND;
- UINT64 inst = program_decrypted_read_qword(LINE_PC << 3);
+ UINT64 inst = memory_decrypted_read_qword(cquestlin.program, LINE_PC << 3);
UINT32 inslow = inst & 0xffffffff;
UINT32 inshig = inst >> 32;
diff --git a/src/emu/cpu/drcfe.c b/src/emu/cpu/drcfe.c
index f54c5d41505..6a39a461711 100644
--- a/src/emu/cpu/drcfe.c
+++ b/src/emu/cpu/drcfe.c
@@ -17,6 +17,7 @@
***************************************************************************/
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include <stddef.h>
#include "cpuintrf.h"
#include "mame.h"
@@ -145,7 +146,7 @@ drcfe_state *drcfe_init(const device_config *cpu, const drcfe_config *config, vo
/* initialize the state */
drcfe->device = cpu;
- drcfe->program = cpu_get_address_space(cpu, ADDRESS_SPACE_PROGRAM);
+ drcfe->program = memory_find_address_space(cpu, ADDRESS_SPACE_PROGRAM);
drcfe->pageshift = cpu_get_page_shift(cpu, ADDRESS_SPACE_PROGRAM);
drcfe->translate = (cpu_translate_func)cpu_get_info_fct(cpu, CPUINFO_PTR_TRANSLATE);
#ifdef LSB_FIRST
@@ -302,7 +303,7 @@ static opcode_desc *describe_one(drcfe_state *drcfe, offs_t curpc, const opcode_
/* get a pointer to the physical address */
change_pc(desc->physpc);
- desc->opptr.v = program_decrypted_read_ptr(desc->physpc ^ drcfe->codexor);
+ desc->opptr.v = memory_decrypted_read_ptr(drcfe->program, desc->physpc ^ drcfe->codexor);
assert(desc->opptr.v != NULL);
if (desc->opptr.v == NULL)
{
diff --git a/src/emu/cpu/dsp32/dsp32.c b/src/emu/cpu/dsp32/dsp32.c
index 3eb7301d708..584ed04c84e 100644
--- a/src/emu/cpu/dsp32/dsp32.c
+++ b/src/emu/cpu/dsp32/dsp32.c
@@ -27,6 +27,7 @@
***************************************************************************/
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "deprecat.h"
#include "dsp32.h"
@@ -212,17 +213,17 @@ static int dsp32_icount;
MEMORY ACCESSORS
***************************************************************************/
-#define ROPCODE(pc) program_decrypted_read_dword(pc)
+#define ROPCODE(pc) memory_decrypted_read_dword(dsp32.program, pc)
-#define RBYTE(addr) program_read_byte_32le(addr)
-#define WBYTE(addr,data) program_write_byte_32le((addr), data)
+#define RBYTE(addr) memory_read_byte_32le(dsp32.program, addr)
+#define WBYTE(addr,data) memory_write_byte_32le(dsp32.program, (addr), data)
#if (!DETECT_MISALIGNED_MEMORY)
-#define RWORD(addr) program_read_word_32le(addr)
-#define WWORD(addr,data) program_write_word_32le((addr), data)
-#define RLONG(addr) program_read_dword_32le(addr)
-#define WLONG(addr,data) program_write_dword_32le((addr), data)
+#define RWORD(addr) memory_read_word_32le(dsp32.program, addr)
+#define WWORD(addr,data) memory_write_word_32le(dsp32.program, (addr), data)
+#define RLONG(addr) memory_read_dword_32le(dsp32.program, addr)
+#define WLONG(addr,data) memory_write_dword_32le(dsp32.program, (addr), data)
#else
@@ -230,7 +231,7 @@ INLINE UINT16 RWORD(offs_t addr)
{
UINT16 data;
if (addr & 1) fprintf(stderr, "Unaligned word read @ %06X, PC=%06X\n", addr, dsp32.PC);
- data = program_read_word_32le(addr);
+ data = memory_read_word_32le(dsp32.program, addr);
return data;
}
@@ -238,20 +239,20 @@ INLINE UINT32 RLONG(offs_t addr)
{
UINT32 data;
if (addr & 3) fprintf(stderr, "Unaligned long read @ %06X, PC=%06X\n", addr, dsp32.PC);
- data = program_write_word_32le(addr);
+ data = memory_write_word_32le(dsp32.program, addr);
return data;
}
INLINE void WWORD(offs_t addr, UINT16 data)
{
if (addr & 1) fprintf(stderr, "Unaligned word write @ %06X, PC=%06X\n", addr, dsp32.PC);
- program_read_dword_32le((addr), data);
+ memory_read_dword_32le(dsp32.program, (addr), data);
}
INLINE void WLONG(offs_t addr, UINT32 data)
{
if (addr & 3) fprintf(stderr, "Unaligned long write @ %06X, PC=%06X\n", addr, dsp32.PC);
- program_write_dword_32le((addr), data);
+ memory_write_dword_32le(dsp32.program, (addr), data);
}
#endif
@@ -357,7 +358,7 @@ static CPU_INIT( dsp32c )
dsp32.output_pins_changed = configdata->output_pins_changed;
dsp32.device = device;
- dsp32.program = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM);
+ dsp32.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
}
diff --git a/src/emu/cpu/dsp32/dsp32dis.c b/src/emu/cpu/dsp32/dsp32dis.c
index db612939929..47084fcf221 100644
--- a/src/emu/cpu/dsp32/dsp32dis.c
+++ b/src/emu/cpu/dsp32/dsp32dis.c
@@ -13,8 +13,6 @@
MEMORY ACCESSORS
***************************************************************************/
-#define ROPCODE(pc) program_decrypted_read_dword(pc)
-
#define ABS(x) (((x) >= 0) ? (x) : -(x))
diff --git a/src/emu/cpu/dsp56k/dsp56k.c b/src/emu/cpu/dsp56k/dsp56k.c
index 5a9768b6c21..5f1b310f653 100644
--- a/src/emu/cpu/dsp56k/dsp56k.c
+++ b/src/emu/cpu/dsp56k/dsp56k.c
@@ -29,6 +29,7 @@
- 1-21 Vectored exception requests on the Host Interface!
***************************************************************************/
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "deprecat.h"
#include "dsp56k.h"
@@ -209,6 +210,8 @@ typedef struct
int interrupt_cycles;
void (*output_pins_changed)(UINT32 pins);
const device_config *device;
+ const address_space *program;
+ const address_space *data;
} dsp56k_core;
@@ -249,7 +252,7 @@ static int dsp56k_icount;
/***************************************************************************
MEMORY ACCESSORS
***************************************************************************/
-#define ROPCODE(pc) program_decrypted_read_word(pc)
+#define ROPCODE(pc) memory_decrypted_read_word(core.program, pc)
/***************************************************************************
@@ -401,6 +404,8 @@ static CPU_INIT( dsp56k )
//core.config = device->static_config;
//core.irq_callback = irqcallback;
core.device = device;
+ core.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ core.data = memory_find_address_space(device, ADDRESS_SPACE_DATA);
}
static void agu_reset(void)
@@ -449,7 +454,7 @@ static CPU_RESET( dsp56k )
alu_reset();
/* HACK - Put a jump to 0x0000 at 0x0000 - this keeps the CPU put in MAME */
- program_write_word_16le(0x0000, 0x0124);
+ memory_write_word_16le(core.program, 0x0000, 0x0124);
}
diff --git a/src/emu/cpu/dsp56k/dsp56ops.c b/src/emu/cpu/dsp56k/dsp56ops.c
index f07455bdf53..6cba8a2cf62 100644
--- a/src/emu/cpu/dsp56k/dsp56ops.c
+++ b/src/emu/cpu/dsp56k/dsp56ops.c
@@ -2188,7 +2188,7 @@ static size_t dsp56k_op_bfop(const UINT16 op, const UINT16 op2, UINT8* cycles)
decode_BBB_bitmask(BITS(op2,0xe000), &iVal);
workAddr = assemble_address_from_Pppppp_table(BITS(OP,0x0020), BITS(OP,0x001f));
- previousValue = data_read_word_16le(WORD(workAddr));
+ previousValue = memory_read_word_16le(core.data, WORD(workAddr));
workingWord = previousValue;
switch(BITS(op2, 0x1f00))
@@ -2254,7 +2254,7 @@ static size_t dsp56k_op_bfop_1(const UINT16 op, const UINT16 op2, UINT8* cycles)
decode_RR_table(BITS(op,0x0003), &R);
workAddr = *((UINT16*)R.addr);
- previousValue = data_read_word_16le(WORD(workAddr));
+ previousValue = memory_read_word_16le(core.data, WORD(workAddr));
workingWord = previousValue;
switch(BITS(op2, 0x1f00))
@@ -3030,7 +3030,7 @@ static size_t dsp56k_op_movec(const UINT16 op, UINT8* cycles)
if (W)
{
/* Write D */
- UINT16 value = data_read_word_16le(WORD(*((UINT16*)R.addr))) ;
+ UINT16 value = memory_read_word_16le(core.data, WORD(*((UINT16*)R.addr))) ;
typed_pointer temp_src = { &value, DT_WORD };
SetDestinationValue(temp_src, SD);
}
@@ -3072,7 +3072,7 @@ static size_t dsp56k_op_movec_1(const UINT16 op, UINT8* cycles)
if (W)
{
/* Write D */
- UINT16 tempData = data_read_word_16le(WORD(memOffset));
+ UINT16 tempData = memory_read_word_16le(core.data, WORD(memOffset));
typed_pointer temp_src = { (void*)&tempData, DT_WORD };
SetDestinationValue(temp_src, SD);
}
@@ -3116,7 +3116,7 @@ static size_t dsp56k_op_movec_2(const UINT16 op, UINT8* cycles)
if (W)
{
/* Write D */
- UINT16 tempData = data_read_word_16le(WORD(memOffset));
+ UINT16 tempData = memory_read_word_16le(core.data, WORD(memOffset));
typed_pointer temp_src = { (void*)&tempData, DT_WORD };
SetDestinationValue(temp_src, SD);
}
@@ -3167,7 +3167,7 @@ static size_t dsp56k_op_movec_3(const UINT16 op, const UINT16 op2, UINT8* cycles
else
{
/* 16-bit long address */
- UINT16 tempD = data_read_word_16le(WORD(op2));
+ UINT16 tempD = memory_read_word_16le(core.data, WORD(op2));
typed_pointer tempTP = {&tempD, DT_WORD};
SetDestinationValue(tempTP, SD);
}
@@ -3245,7 +3245,7 @@ static size_t dsp56k_op_movec_5(const UINT16 op, const UINT16 op2, UINT8* cycles
if (W)
{
/* Write D */
- UINT16 tempData = data_read_word_16le(WORD(memOffset));
+ UINT16 tempData = memory_read_word_16le(core.data, WORD(memOffset));
typed_pointer temp_src = { (void*)&tempData, DT_WORD };
SetDestinationValue(temp_src, SD);
}
@@ -3308,7 +3308,7 @@ static size_t dsp56k_op_movem(const UINT16 op, UINT8* cycles)
{
/* Read from Program Memory */
typed_pointer data;
- UINT16 ldata = program_read_word_16le(WORD(*((UINT16*)R.addr)));
+ UINT16 ldata = memory_read_word_16le(core.program, WORD(*((UINT16*)R.addr)));
data.addr = &ldata;
data.data_type = DT_WORD;
@@ -3362,7 +3362,7 @@ static size_t dsp56k_op_movep(const UINT16 op, UINT8* cycles)
if (W)
{
- UINT16 data = data_read_word_16le(WORD(pp));
+ UINT16 data = memory_read_word_16le(core.data, WORD(pp));
typed_pointer tempTP;
tempTP.addr = &data;
@@ -3401,7 +3401,7 @@ static size_t dsp56k_op_movep_1(const UINT16 op, UINT8* cycles)
/* A little different than most W if's - opposite read and write */
if (W)
{
- UINT16 data = data_read_word_16le(WORD(*((UINT16*)SD.addr)));
+ UINT16 data = memory_read_word_16le(core.data, WORD(*((UINT16*)SD.addr)));
typed_pointer tempTP;
tempTP.addr = &data;
@@ -4352,7 +4352,7 @@ static void execute_x_memory_data_move(const UINT16 op, typed_pointer* d_registe
if (W)
{
/* From X:<ea> to SD */
- UINT16 data = data_read_word_16le(WORD(*((UINT16*)R.addr)));
+ UINT16 data = memory_read_word_16le(core.data, WORD(*((UINT16*)R.addr)));
typed_pointer tempTP;
tempTP.addr = &data;
@@ -4400,7 +4400,7 @@ static void execute_x_memory_data_move2(const UINT16 op, typed_pointer* d_regist
if (W)
{
/* Write D */
- UINT16 value = data_read_word_16le(WORD(*mem_offset));
+ UINT16 value = memory_read_word_16le(core.data, WORD(*mem_offset));
typed_pointer tempV = {&value, DT_WORD};
SetDestinationValue(tempV, SD);
}
@@ -4428,7 +4428,7 @@ static void execute_x_memory_data_move_with_short_displacement(const UINT16 op,
if (W)
{
/* Write D */
- UINT16 tempData = data_read_word_16le(WORD(memOffset));
+ UINT16 tempData = memory_read_word_16le(core.data, WORD(memOffset));
typed_pointer temp_src = { (void*)&tempData, DT_WORD };
SetDestinationValue(temp_src, SD);
}
@@ -4464,13 +4464,13 @@ static void execute_dual_x_memory_data_read(const UINT16 op, typed_pointer* d_re
fatalerror("Dsp56k: Unimplemented access to external X Data Memory >= 0xffc0 in Dual X Memory Data Read.");
/* First memmove */
- srcVal1 = data_read_word_16le(WORD(*((UINT16*)R.addr)));
+ srcVal1 = memory_read_word_16le(core.data, WORD(*((UINT16*)R.addr)));
tempV.addr = &srcVal1;
tempV.data_type = DT_WORD;
SetDestinationValue(tempV, D1);
/* Second memmove */
- srcVal2 = data_read_word_16le(WORD(R3));
+ srcVal2 = memory_read_word_16le(core.data, WORD(R3));
tempV.addr = &srcVal2;
tempV.data_type = DT_WORD;
SetDestinationValue(tempV, D2);
@@ -4565,13 +4565,13 @@ static void SetDataMemoryValue(typed_pointer source, UINT32 destinationAddr)
{
switch(source.data_type)
{
- case DT_BYTE: data_write_word_16le(destinationAddr, (UINT16)( (*((UINT8*) source.addr) & 0xff) ) ) ; break ;
- case DT_WORD: data_write_word_16le(destinationAddr, (UINT16)( (*((UINT16*)source.addr) & 0xffff) ) ) ; break ;
- case DT_DOUBLE_WORD: data_write_word_16le(destinationAddr, (UINT16)( (*((UINT32*)source.addr) & 0x0000ffff) ) ) ; break ;
+ case DT_BYTE: memory_write_word_16le(core.data, destinationAddr, (UINT16)( (*((UINT8*) source.addr) & 0xff) ) ) ; break ;
+ case DT_WORD: memory_write_word_16le(core.data, destinationAddr, (UINT16)( (*((UINT16*)source.addr) & 0xffff) ) ) ; break ;
+ case DT_DOUBLE_WORD: memory_write_word_16le(core.data, destinationAddr, (UINT16)( (*((UINT32*)source.addr) & 0x0000ffff) ) ) ; break ;
// !!! Is this universal ???
// !!! Forget not, yon shift-limiter !!!
- case DT_LONG_WORD: data_write_word_16le(destinationAddr, (UINT16)( ((*((UINT64*)source.addr)) & U64(0x00000000ffff0000)) >> 16) ) ; break ;
+ case DT_LONG_WORD: memory_write_word_16le(core.data, destinationAddr, (UINT16)( ((*((UINT64*)source.addr)) & U64(0x00000000ffff0000)) >> 16) ) ; break ;
}
}
@@ -4580,13 +4580,13 @@ static void SetProgramMemoryValue(typed_pointer source, UINT32 destinationAddr)
{
switch(source.data_type)
{
- case DT_BYTE: program_write_word_16le(destinationAddr, (UINT16)( (*((UINT8*) source.addr) & 0xff) ) ) ; break ;
- case DT_WORD: program_write_word_16le(destinationAddr, (UINT16)( (*((UINT16*)source.addr) & 0xffff) ) ) ; break ;
- case DT_DOUBLE_WORD: program_write_word_16le(destinationAddr, (UINT16)( (*((UINT32*)source.addr) & 0x0000ffff) ) ) ; break ;
+ case DT_BYTE: memory_write_word_16le(core.program, destinationAddr, (UINT16)( (*((UINT8*) source.addr) & 0xff) ) ) ; break ;
+ case DT_WORD: memory_write_word_16le(core.program, destinationAddr, (UINT16)( (*((UINT16*)source.addr) & 0xffff) ) ) ; break ;
+ case DT_DOUBLE_WORD: memory_write_word_16le(core.program, destinationAddr, (UINT16)( (*((UINT32*)source.addr) & 0x0000ffff) ) ) ; break ;
// !!! Is this universal ???
// !!! Forget not, yon shift-limiter !!!
- case DT_LONG_WORD: program_write_word_16le(destinationAddr, (UINT16)( ((*((UINT64*)source.addr)) & U64(0x00000000ffff0000)) >> 16) ) ; break ;
+ case DT_LONG_WORD: memory_write_word_16le(core.program, destinationAddr, (UINT16)( ((*((UINT64*)source.addr)) & U64(0x00000000ffff0000)) >> 16) ) ; break ;
}
}
diff --git a/src/emu/cpu/dsp56k/dsp56pcu.c b/src/emu/cpu/dsp56k/dsp56pcu.c
index a43188c5b50..07766f8ae39 100644
--- a/src/emu/cpu/dsp56k/dsp56pcu.c
+++ b/src/emu/cpu/dsp56k/dsp56pcu.c
@@ -150,8 +150,8 @@ static void pcu_reset(void)
// ...
// P:$cffe -> Internal P:$07ff low byte
// P:$cfff -> Internal P:$07ff high byte
- UINT8 mem_value_low = program_read_byte_16le(mem_offset); /* TODO: IS THIS READING RIGHT? */
- UINT8 mem_value_high = program_read_byte_16be(mem_offset);
+ UINT8 mem_value_low = memory_read_byte_16le(core.program, mem_offset); /* TODO: IS THIS READING RIGHT? */
+ UINT8 mem_value_high = memory_read_byte_16be(core.program, mem_offset);
dsp56k_program_ram[i] = (mem_value_high << 8) || mem_value_low;
}
@@ -172,7 +172,7 @@ static void pcu_reset(void)
// they need. Once they've had their fill, they turn bootstrap mode off
// and the CPU begins execution at 0x0000;
// HACK - Read bit 15 at 0xc000 to see if we're working with the SSIO or host interface.
- if (program_read_word_16le(0xc000<<1) & 0x8000)
+ if (memory_read_word_16le(core.program, 0xc000<<1) & 0x8000)
{
core.bootstrap_mode = BOOTSTRAP_SSIX;
logerror("DSP56k : Currently in (hacked) bootstrap mode - reading from SSIx.\n");
diff --git a/src/emu/cpu/e132xs/e132xs.c b/src/emu/cpu/e132xs/e132xs.c
index dfbcc620a5c..830a3703a92 100644
--- a/src/emu/cpu/e132xs/e132xs.c
+++ b/src/emu/cpu/e132xs/e132xs.c
@@ -211,6 +211,7 @@
*********************************************************************/
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "deprecat.h"
#include "cpuexec.h"
@@ -224,16 +225,6 @@
#define DEBUG_PRINTF(x) do { } while (0)
#endif
-static UINT8 (*hyp_cpu_read_byte)(offs_t address);
-static UINT16 (*hyp_cpu_read_half_word)(offs_t address);
-static UINT32 (*hyp_cpu_read_word)(offs_t address);
-static UINT32 (*hyp_cpu_read_io_word)(offs_t address);
-static void (*hyp_cpu_write_byte)(offs_t address, UINT8 data);
-static void (*hyp_cpu_write_half_word)(offs_t address, UINT16 data);
-static void (*hyp_cpu_write_word)(offs_t address, UINT32 data);
-static void (*hyp_cpu_write_io_word)(offs_t address, UINT32 data);
-int hyp_type_16bit;
-
// set C in adds/addsi/subs/sums
#define SETCARRYS 0
#define MISSIONCRAFT_FLAGS 1
@@ -334,6 +325,9 @@ typedef struct
cpu_irq_callback irq_callback;
const device_config *device;
+ const address_space *program;
+ const address_space *io;
+ UINT32 opcodexor;
INT32 instruction_length;
INT32 intblock;
@@ -386,31 +380,6 @@ static void check_interrupts(void);
#define SAME_SRC_DSTF (decode)->same_src_dstf
#define SAME_SRCF_DST (decode)->same_srcf_dst
-#if (HAS_E116T || HAS_E116XT || HAS_E116XS || HAS_E116XSR || HAS_GMS30C2116 || HAS_GMS30C2216)
-static UINT32 internal_program_read_dword_16be(offs_t address)
-{
- return (program_read_word_16be(address & ~1) << 16) | program_read_word_16be((address & ~1) + 2);
-}
-
-static void internal_program_write_dword_16be(offs_t address, UINT32 data)
-{
- program_write_word_16be(address & ~1, (data & 0xffff0000)>>16);
- program_write_word_16be((address & ~1)+2, data & 0xffff);
-}
-
-static UINT32 internal_io_read_dword_16be(offs_t address)
-{
- return (io_read_word_16be(address & ~1)<< 16) | io_read_word_16be((address & ~1) + 2);
-}
-
-static void internal_io_write_dword_16be(offs_t address, UINT32 data)
-{
- io_write_word_16be(address & ~1, (data & 0xffff0000)>>16);
- io_write_word_16be((address & ~1)+2, data & 0xffff);
-}
-#endif
-
-
// 4Kb IRAM (On-Chip Memory)
#if (HAS_E116T || HAS_GMS30C2116)
@@ -1580,6 +1549,8 @@ static void hyperstone_init(const device_config *device, int index, int clock, c
hyperstone.irq_callback = irqcallback;
hyperstone.device = device;
+ hyperstone.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ hyperstone.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
hyperstone.timer = timer_alloc(e132xs_timer_callback, NULL);
hyperstone.clock_scale_mask = scale_mask;
}
@@ -1587,19 +1558,8 @@ static void hyperstone_init(const device_config *device, int index, int clock, c
#if (HAS_E116T || HAS_E116XT || HAS_E116XS || HAS_E116XSR || HAS_GMS30C2116 || HAS_GMS30C2216)
static void e116_init(const device_config *device, int index, int clock, cpu_irq_callback irqcallback, int scale_mask)
{
- hyp_cpu_read_byte = program_read_byte_16be;
- hyp_cpu_read_half_word = program_read_word_16be;
- hyp_cpu_read_word = internal_program_read_dword_16be;
- hyp_cpu_read_io_word = internal_io_read_dword_16be;
-
- hyp_cpu_write_byte = program_write_byte_16be;
- hyp_cpu_write_half_word = program_write_word_16be;
- hyp_cpu_write_word = internal_program_write_dword_16be;
- hyp_cpu_write_io_word = internal_io_write_dword_16be;
-
- hyp_type_16bit = 1;
-
hyperstone_init(device, index, clock, irqcallback, scale_mask);
+ hyperstone.opcodexor = 0;
}
#endif
@@ -1648,19 +1608,8 @@ static CPU_INIT( gms30c2216 )
#if (HAS_E132N || HAS_E132T || HAS_E132XN || HAS_E132XT || HAS_E132XS || HAS_E132XSR || HAS_GMS30C2132 || HAS_GMS30C2232)
static void e132_init(const device_config *device, int index, int clock, cpu_irq_callback irqcallback, int scale_mask)
{
- hyp_cpu_read_byte = program_read_byte_32be;
- hyp_cpu_read_half_word = program_read_word_32be;
- hyp_cpu_read_word = program_read_dword_32be;
- hyp_cpu_read_io_word = io_read_dword_32be;
-
- hyp_cpu_write_byte = program_write_byte_32be;
- hyp_cpu_write_half_word = program_write_word_32be;
- hyp_cpu_write_word = program_write_dword_32be;
- hyp_cpu_write_io_word = io_write_dword_32be;
-
- hyp_type_16bit = 0;
-
hyperstone_init(device, index, clock, irqcallback, scale_mask);
+ hyperstone.opcodexor = WORD_XOR_BE(0);
}
#endif
@@ -1726,12 +1675,17 @@ static CPU_RESET( hyperstone )
emu_timer *save_timer;
cpu_irq_callback save_irqcallback;
+ UINT32 save_opcodexor;
save_timer = hyperstone.timer;
save_irqcallback = hyperstone.irq_callback;
+ save_opcodexor = hyperstone.opcodexor;
memset(&hyperstone, 0, sizeof(hyperstone_regs));
hyperstone.irq_callback = save_irqcallback;
+ hyperstone.opcodexor = save_opcodexor;
hyperstone.device = device;
+ hyperstone.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ hyperstone.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
hyperstone.timer = save_timer;
hyperstone.tr_clocks_per_tick = 2;
diff --git a/src/emu/cpu/e132xs/e132xs.h b/src/emu/cpu/e132xs/e132xs.h
index 2dedbf065b7..5859640a493 100644
--- a/src/emu/cpu/e132xs/e132xs.h
+++ b/src/emu/cpu/e132xs/e132xs.h
@@ -81,32 +81,30 @@ CPU_GET_INFO( gms30c2232 );
extern unsigned dasm_hyperstone(char *buffer, unsigned pc, const UINT8 *oprom, unsigned h_flag, int private_fp);
-extern int hyp_type_16bit;
-
/* Memory access */
/* read byte */
-#define READ_B(addr) ((*hyp_cpu_read_byte)(addr))
+#define READ_B(addr) memory_read_byte(hyperstone.program, (addr))
/* read half-word */
-#define READ_HW(addr) ((*hyp_cpu_read_half_word)((addr) & ~1))
+#define READ_HW(addr) memory_read_word(hyperstone.program, (addr) & ~1)
/* read word */
-#define READ_W(addr) ((*hyp_cpu_read_word)((addr) & ~3))
+#define READ_W(addr) memory_read_dword(hyperstone.program, (addr) & ~3)
/* write byte */
-#define WRITE_B(addr, data) ((*hyp_cpu_write_byte)(addr, data))
+#define WRITE_B(addr, data) memory_write_byte(hyperstone.program, addr, data)
/* write half-word */
-#define WRITE_HW(addr, data) ((*hyp_cpu_write_half_word)((addr) & ~1, data))
+#define WRITE_HW(addr, data) memory_write_word(hyperstone.program, (addr) & ~1, data)
/* write word */
-#define WRITE_W(addr, data) ((*hyp_cpu_write_word)((addr) & ~3, data))
+#define WRITE_W(addr, data) memory_write_dword(hyperstone.program, (addr) & ~3, data)
/* I/O access */
/* read word */
-#define IO_READ_W(addr) ((*hyp_cpu_read_io_word)(((addr) >> 11) & 0x7ffc))
+#define IO_READ_W(addr) memory_read_dword(hyperstone.io, ((addr) >> 11) & 0x7ffc)
/* write word */
-#define IO_WRITE_W(addr, data) ((*hyp_cpu_write_io_word)(((addr) >> 11) & 0x7ffc, data))
+#define IO_WRITE_W(addr, data) memory_write_dword(hyperstone.io, ((addr) >> 11) & 0x7ffc, data)
-#define READ_OP(addr) (program_decrypted_read_word(hyp_type_16bit ? addr: WORD_XOR_BE(addr)))
+#define READ_OP(addr) memory_decrypted_read_word(hyperstone.program, (addr) ^ hyperstone.opcodexor)
/* Registers Number */
diff --git a/src/emu/cpu/f8/f8.c b/src/emu/cpu/f8/f8.c
index 1121f4bd9e2..8c4bf382f0a 100644
--- a/src/emu/cpu/f8/f8.c
+++ b/src/emu/cpu/f8/f8.c
@@ -26,6 +26,7 @@
added interrupt functionality
*/
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "f8.h"
@@ -51,6 +52,8 @@ typedef struct {
UINT16 irq_vector;
cpu_irq_callback irq_callback;
const device_config *device;
+ const address_space *program;
+ const address_space *iospace;
UINT8 r[64]; /* scratchpad RAM */
int irq_request;
} f8_Regs;
@@ -109,7 +112,7 @@ static void ROMC_00(int insttim) /* SKR - added parameter to tell if */
* of PC0.
*/
- f8.dbus = program_decrypted_read_byte(f8.pc0);
+ f8.dbus = memory_decrypted_read_byte(f8.program, f8.pc0);
f8.pc0 += 1;
f8_icount -= insttim; /* SKR - ROMC00 is usually short, not short+long, */
/* but DS is long */
@@ -123,7 +126,7 @@ static void ROMC_01(void)
* location addressed by PC0; then all devices add the 8-bit value
* on the data bus as signed binary number to PC0.
*/
- f8.dbus = program_raw_read_byte(f8.pc0);
+ f8.dbus = memory_raw_read_byte(f8.program, f8.pc0);
f8.pc0 += (INT8)f8.dbus;
f8_icount -= cL;
}
@@ -136,7 +139,7 @@ static void ROMC_02(void)
* the memory location addressed by DC0; then all devices increment
* DC0.
*/
- f8.dbus = program_read_byte_8be(f8.dc0);
+ f8.dbus = memory_read_byte_8be(f8.program, f8.dc0);
f8.dc0 += 1;
f8_icount -= cL;
}
@@ -147,7 +150,7 @@ static void ROMC_03(int insttim) /* SKR - added parameter to tell if */
* Similiar to 0x00, except that it is used for immediate operands
* fetches (using PC0) instead of instruction fetches.
*/
- f8.dbus = f8.io = program_raw_read_byte(f8.pc0);
+ f8.dbus = f8.io = memory_raw_read_byte(f8.program, f8.pc0);
f8.pc0 += 1;
f8_icount -= insttim;
}
@@ -167,7 +170,7 @@ static void ROMC_05(void)
* Store the data bus contents into the memory location pointed
* to by DC0; increment DC0.
*/
- program_write_byte_8be(f8.dc0, f8.dbus);
+ memory_write_byte_8be(f8.program, f8.dc0, f8.dbus);
f8.dc0 += 1;
f8_icount -= cL;
}
@@ -241,7 +244,7 @@ static void ROMC_0C(void)
* by PC0 into the data bus; then all devices move the value that
* has just been placed on the data bus into the low order byte of PC0.
*/
- f8.dbus = program_raw_read_byte(f8.pc0);
+ f8.dbus = memory_raw_read_byte(f8.program, f8.pc0);
f8.pc0 = (f8.pc0 & 0xff00) | f8.dbus;
f8_icount -= cL;
}
@@ -264,7 +267,7 @@ static void ROMC_0E(void)
* The value on the data bus is then moved to the low order byte
* of DC0 by all devices.
*/
- f8.dbus = program_raw_read_byte(f8.pc0);
+ f8.dbus = memory_raw_read_byte(f8.program, f8.pc0);
f8.dc0 = (f8.dc0 & 0xff00) | f8.dbus;
f8_icount -= cL;
}
@@ -304,7 +307,7 @@ static void ROMC_11(void)
* data bus. All devices must then move the contents of the
* data bus to the upper byte of DC0.
*/
- f8.dbus = program_raw_read_byte(f8.pc0);
+ f8.dbus = memory_raw_read_byte(f8.program, f8.pc0);
f8.dc0 = (f8.dc0 & 0x00ff) | (f8.dbus << 8);
f8_icount -= cL;
}
@@ -403,7 +406,7 @@ static void ROMC_1A(void)
* register was addressed; the device containing the addressed port
* must place the contents of the data bus into the address port.
*/
- io_write_byte_8be(f8.io, f8.dbus);
+ memory_write_byte_8be(f8.iospace, f8.io, f8.dbus);
f8_icount -= cL;
}
@@ -416,7 +419,7 @@ static void ROMC_1B(void)
* contents of timer and interrupt control registers cannot be read
* back onto the data bus).
*/
- f8.dbus = io_read_byte_8be(f8.io);
+ f8.dbus = memory_read_byte_8be(f8.iospace, f8.io);
f8_icount -= cL;
}
@@ -1258,7 +1261,7 @@ static void f8_ins_0(int n)
{
ROMC_1C(cS);
CLR_OZCS;
- f8.a = io_read_byte_8be(n);
+ f8.a = memory_read_byte_8be(f8.iospace, n);
SET_SZ(f8.a);
}
@@ -1283,7 +1286,7 @@ static void f8_ins_1(int n)
static void f8_outs_0(int n)
{
ROMC_1C(cS);
- io_write_byte_8be(n, f8.a);
+ memory_write_byte_8be(f8.iospace, n, f8.a);
}
/***************************************************
@@ -1540,6 +1543,8 @@ static CPU_RESET( f8 )
memset(&f8, 0, sizeof(f8_Regs));
f8.irq_callback = save_callback;
f8.device = device;
+ f8.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ f8.iospace = memory_find_address_space(device, ADDRESS_SPACE_IO);
f8.w&=~I;
/* save PC0 to PC1 and reset PC0 */
@@ -1898,6 +1903,8 @@ static CPU_INIT( f8 )
{
f8.irq_callback = irqcallback;
f8.device = device;
+ f8.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ f8.iospace = memory_find_address_space(device, ADDRESS_SPACE_IO);
}
static CPU_SET_INFO( f8 )
@@ -1908,14 +1915,14 @@ static CPU_SET_INFO( f8 )
case CPUINFO_INT_SP: f8.pc1 = info->i; break;
case CPUINFO_INT_PC:
f8.pc0 = info->i;
- f8.dbus = program_decrypted_read_byte(f8.pc0);
+ f8.dbus = memory_decrypted_read_byte(f8.program, f8.pc0);
f8.pc0 += 1;
break;
case CPUINFO_INT_PREVIOUSPC: break; /* TODO? */
case CPUINFO_INT_INPUT_STATE: f8.irq_request = info->i; break;
case CPUINFO_INT_REGISTER + F8_PC0:
f8.pc0 = info->i;
- f8.dbus = program_decrypted_read_byte(f8.pc0);
+ f8.dbus = memory_decrypted_read_byte(f8.program, f8.pc0);
f8.pc0 += 1;
break;
case CPUINFO_INT_REGISTER + F8_PC1: f8.pc1 = info->i; break;
diff --git a/src/emu/cpu/g65816/g65816.c b/src/emu/cpu/g65816/g65816.c
index b4b94d535d9..f3a59757060 100644
--- a/src/emu/cpu/g65816/g65816.c
+++ b/src/emu/cpu/g65816/g65816.c
@@ -84,6 +84,7 @@ TODO general:
/* ================================= DATA ================================= */
/* ======================================================================== */
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include "g65816cm.h"
/* Our CPU structure */
@@ -330,6 +331,7 @@ static CPU_INIT( g65816 )
{
g65816_set_irq_callback(irqcallback);
g65816i_cpu.device = device;
+ g65816i_cpu.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
state_save_register_item("G65816", device->tag, 0, g65816i_cpu.a);
state_save_register_item("G65816", device->tag, 0, g65816i_cpu.b);
diff --git a/src/emu/cpu/g65816/g65816.h b/src/emu/cpu/g65816/g65816.h
index 50bd4d335ba..cc12e672d3f 100644
--- a/src/emu/cpu/g65816/g65816.h
+++ b/src/emu/cpu/g65816/g65816.h
@@ -94,9 +94,9 @@ CPU_GET_INFO( g65816 );
#undef G65816_CALL_DEBUGGER
#define G65816_CALL_DEBUGGER(x) debugger_instruction_hook(g65816i_cpu.device, x)
-#define g65816_read_8(addr) program_read_byte_8be(addr)
-#define g65816_write_8(addr,data) program_write_byte_8be(addr,data)
-#define g65816_read_8_immediate(A) program_read_byte_8be(A)
+#define g65816_read_8(addr) memory_read_byte_8be(g65816i_cpu.program, addr)
+#define g65816_write_8(addr,data) memory_write_byte_8be(g65816i_cpu.program, addr,data)
+#define g65816_read_8_immediate(A) memory_read_byte_8be(g65816i_cpu.program, A)
#define g65816_jumping(A) change_pc(A)
#define g65816_branching(A)
diff --git a/src/emu/cpu/g65816/g65816cm.h b/src/emu/cpu/g65816/g65816cm.h
index 363a6c6c693..d675cb43733 100644
--- a/src/emu/cpu/g65816/g65816cm.h
+++ b/src/emu/cpu/g65816/g65816cm.h
@@ -90,6 +90,7 @@ struct _g65816i_cpu_struct
uint irq_delay; /* delay 1 instruction before checking irq */
cpu_irq_callback int_ack; /* Interrupt Acknowledge */
const device_config *device;
+ const address_space *program;
read8_space_func read_vector; /* Read vector override */
uint stopped; /* Sets how the CPU is stopped */
void (*const *opcodes)(void);
diff --git a/src/emu/cpu/h6280/h6280.c b/src/emu/cpu/h6280/h6280.c
index 2030e9f0f0d..837f85bf024 100644
--- a/src/emu/cpu/h6280/h6280.c
+++ b/src/emu/cpu/h6280/h6280.c
@@ -107,6 +107,7 @@
- Improvements to the handling of taking of delayed interrupts.
******************************************************************************/
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "deprecat.h"
#include "h6280.h"
@@ -139,6 +140,8 @@ typedef struct
UINT8 irq_pending;
cpu_irq_callback irq_callback;
const device_config *device;
+ const address_space *program;
+ const address_space *io;
#if LAZY_FLAGS
INT32 NZ; /* last value (lazy N and Z flag) */
@@ -188,6 +191,8 @@ static CPU_INIT( h6280 )
h6280.irq_callback = irqcallback;
h6280.device = device;
+ h6280.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ h6280.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
}
static CPU_RESET( h6280 )
@@ -200,6 +205,7 @@ static CPU_RESET( h6280 )
memset(&h6280, 0, sizeof(h6280_Regs));
h6280.irq_callback = save_irqcallback;
h6280.device = device;
+ h6280.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
/* set I and B flags */
P = _fI | _fB;
diff --git a/src/emu/cpu/h6280/h6280ops.h b/src/emu/cpu/h6280/h6280ops.h
index bf12f4c31c7..ec3970217c5 100644
--- a/src/emu/cpu/h6280/h6280ops.h
+++ b/src/emu/cpu/h6280/h6280ops.h
@@ -128,7 +128,7 @@
***************************************************************/
INLINE UINT8 RDMEM(offs_t addr) {
CHECK_VDC_VCE_PENALTY(addr);
- return program_read_byte_8le(TRANSLATED(addr));
+ return memory_read_byte_8le(h6280.program, TRANSLATED(addr));
}
/***************************************************************
@@ -136,60 +136,60 @@ INLINE UINT8 RDMEM(offs_t addr) {
***************************************************************/
INLINE void WRMEM(offs_t addr, UINT8 data) {
CHECK_VDC_VCE_PENALTY(addr);
- program_write_byte_8le(TRANSLATED(addr),data);
+ memory_write_byte_8le(h6280.program, TRANSLATED(addr),data);
}
/***************************************************************
* RDMEMZ read memory - zero page
***************************************************************/
#define RDMEMZ(addr) \
- program_read_byte_8le( (h6280.mmr[1] << 13) | ((addr)&0x1fff));
+ memory_read_byte_8le(h6280.program, (h6280.mmr[1] << 13) | ((addr)&0x1fff));
/***************************************************************
* WRMEMZ write memory - zero page
***************************************************************/
#define WRMEMZ(addr,data) \
- program_write_byte_8le( (h6280.mmr[1] << 13) | ((addr)&0x1fff),data);
+ memory_write_byte_8le(h6280.program, (h6280.mmr[1] << 13) | ((addr)&0x1fff),data);
/***************************************************************
* RDMEMW read word from memory
***************************************************************/
#define RDMEMW(addr) \
- program_read_byte_8le(TRANSLATED(addr)) \
-| ( program_read_byte_8le(TRANSLATED(addr+1)) << 8 )
+ memory_read_byte_8le(h6280.program, TRANSLATED(addr)) \
+| ( memory_read_byte_8le(h6280.program, TRANSLATED(addr+1)) << 8 )
/***************************************************************
* RDZPWORD read a word from a zero page address
***************************************************************/
#define RDZPWORD(addr) \
((addr&0xff)==0xff) ? \
- program_read_byte_8le( (h6280.mmr[1] << 13) | ((addr)&0x1fff)) \
- +(program_read_byte_8le( (h6280.mmr[1] << 13) | ((addr-0xff)&0x1fff))<<8) : \
- program_read_byte_8le( (h6280.mmr[1] << 13) | ((addr)&0x1fff)) \
- +(program_read_byte_8le( (h6280.mmr[1] << 13) | ((addr+1)&0x1fff))<<8)
+ memory_read_byte_8le(h6280.program, (h6280.mmr[1] << 13) | ((addr)&0x1fff)) \
+ +(memory_read_byte_8le(h6280.program, (h6280.mmr[1] << 13) | ((addr-0xff)&0x1fff))<<8) : \
+ memory_read_byte_8le(h6280.program, (h6280.mmr[1] << 13) | ((addr)&0x1fff)) \
+ +(memory_read_byte_8le(h6280.program, (h6280.mmr[1] << 13) | ((addr+1)&0x1fff))<<8)
/***************************************************************
* push a register onto the stack
***************************************************************/
-#define PUSH(Rg) program_write_byte_8le( (h6280.mmr[1] << 13) | h6280.sp.d,Rg); S--
+#define PUSH(Rg) memory_write_byte_8le(h6280.program, (h6280.mmr[1] << 13) | h6280.sp.d,Rg); S--
/***************************************************************
* pull a register from the stack
***************************************************************/
-#define PULL(Rg) S++; Rg = program_read_byte_8le( (h6280.mmr[1] << 13) | h6280.sp.d)
+#define PULL(Rg) S++; Rg = memory_read_byte_8le(h6280.program, (h6280.mmr[1] << 13) | h6280.sp.d)
/***************************************************************
* RDOP read an opcode
***************************************************************/
#define RDOP() \
- program_decrypted_read_byte(TRANSLATED(PCW))
+ memory_decrypted_read_byte(h6280.program, TRANSLATED(PCW))
/***************************************************************
* RDOPARG read an opcode argument
***************************************************************/
#define RDOPARG() \
- program_raw_read_byte(TRANSLATED(PCW))
+ memory_raw_read_byte(h6280.program, TRANSLATED(PCW))
/***************************************************************
* BRA branch relative
@@ -1121,21 +1121,21 @@ INLINE void WRMEM(offs_t addr, UINT8 data) {
***************************************************************/
#define ST0 \
CLEAR_T; \
- io_write_byte_8le(0x0000,tmp)
+ memory_write_byte_8le(h6280.io,0x0000,tmp)
/* 6280 ********************************************************
* ST1 Store at hardware address 2
***************************************************************/
#define ST1 \
CLEAR_T; \
- io_write_byte_8le(0x0002,tmp)
+ memory_write_byte_8le(h6280.io,0x0002,tmp)
/* 6280 ********************************************************
* ST2 Store at hardware address 3
***************************************************************/
#define ST2 \
CLEAR_T; \
- io_write_byte_8le(0x0003,tmp)
+ memory_write_byte_8le(h6280.io,0x0003,tmp)
/* 6280 ********************************************************
* STA Store accumulator
diff --git a/src/emu/cpu/i386/i386.c b/src/emu/cpu/i386/i386.c
index 19d498481e0..b882eaedc86 100644
--- a/src/emu/cpu/i386/i386.c
+++ b/src/emu/cpu/i386/i386.c
@@ -443,7 +443,7 @@ static void I386OP(decode_two_byte)(void)
/*************************************************************************/
-static UINT64 i386_debug_segbase(void *ref, UINT32 params, const UINT64 *param)
+static UINT64 i386_debug_segbase(void *globalref, void *ref, UINT32 params, const UINT64 *param)
{
UINT32 result;
I386_SREG seg;
@@ -462,7 +462,7 @@ static UINT64 i386_debug_segbase(void *ref, UINT32 params, const UINT64 *param)
return result;
}
-static UINT64 i386_debug_seglimit(void *ref, UINT32 params, const UINT64 *param)
+static UINT64 i386_debug_seglimit(void *globalref, void *ref, UINT32 params, const UINT64 *param)
{
UINT32 result = 0;
I386_SREG seg;
@@ -524,6 +524,8 @@ static CPU_INIT( i386 )
I.irq_callback = irqcallback;
I.device = device;
+ I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
state_save_register_item_array(state_type, device->tag, 0, I.reg.d);
state_save_register_item(state_type, device->tag, 0, I.sreg[ES].selector);
@@ -620,6 +622,8 @@ static CPU_RESET( i386 )
memset( &I, 0, sizeof(I386_REGS) );
I.irq_callback = save_irqcallback;
I.device = device;
+ I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
I.sreg[CS].selector = 0xf000;
I.sreg[CS].base = 0xffff0000;
diff --git a/src/emu/cpu/i386/i386.h b/src/emu/cpu/i386/i386.h
index 3cb3c34743f..a06b4853559 100644
--- a/src/emu/cpu/i386/i386.h
+++ b/src/emu/cpu/i386/i386.h
@@ -3,6 +3,7 @@
#ifndef __I386_H__
#define __I386_H__
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include "cpuintrf.h"
#define I386OP(XX) i386_##XX
@@ -251,6 +252,8 @@ typedef struct {
UINT8 irq_state;
cpu_irq_callback irq_callback;
const device_config *device;
+ const address_space *program;
+ const address_space *io;
UINT32 a20_mask;
int cpuid_max_input_value_eax;
@@ -361,8 +364,8 @@ INLINE int translate_address(UINT32 *address)
UINT32 offset = a & 0xfff;
// TODO: 4MB pages
- UINT32 page_dir = program_read_dword_32le(pdbr + directory * 4);
- UINT32 page_entry = program_read_dword_32le((page_dir & 0xfffff000) + (table * 4));
+ UINT32 page_dir = memory_read_dword_32le(I.program, pdbr + directory * 4);
+ UINT32 page_entry = memory_read_dword_32le(I.program, (page_dir & 0xfffff000) + (table * 4));
*address = (page_entry & 0xfffff000) | offset;
return 1;
@@ -410,7 +413,7 @@ INLINE UINT8 FETCH(void)
translate_address(&address);
}
- value = program_decrypted_read_byte(address & I.a20_mask);
+ value = memory_decrypted_read_byte(I.program, address & I.a20_mask);
I.eip++;
I.pc++;
return value;
@@ -427,11 +430,11 @@ INLINE UINT16 FETCH16(void)
if( address & 0x1 ) { /* Unaligned read */
address &= I.a20_mask;
- value = (program_decrypted_read_byte(address+0) << 0) |
- (program_decrypted_read_byte(address+1) << 8);
+ value = (memory_decrypted_read_byte(I.program, address+0) << 0) |
+ (memory_decrypted_read_byte(I.program, address+1) << 8);
} else {
address &= I.a20_mask;
- value = program_decrypted_read_word(address);
+ value = memory_decrypted_read_word(I.program, address);
}
I.eip += 2;
I.pc += 2;
@@ -449,13 +452,13 @@ INLINE UINT32 FETCH32(void)
if( I.pc & 0x3 ) { /* Unaligned read */
address &= I.a20_mask;
- value = (program_decrypted_read_byte(address+0) << 0) |
- (program_decrypted_read_byte(address+1) << 8) |
- (program_decrypted_read_byte(address+2) << 16) |
- (program_decrypted_read_byte(address+3) << 24);
+ value = (memory_decrypted_read_byte(I.program, address+0) << 0) |
+ (memory_decrypted_read_byte(I.program, address+1) << 8) |
+ (memory_decrypted_read_byte(I.program, address+2) << 16) |
+ (memory_decrypted_read_byte(I.program, address+3) << 24);
} else {
address &= I.a20_mask;
- value = program_decrypted_read_dword(address);
+ value = memory_decrypted_read_dword(I.program, address);
}
I.eip += 4;
I.pc += 4;
@@ -472,7 +475,7 @@ INLINE UINT8 READ8(UINT32 ea)
}
address &= I.a20_mask;
- return program_read_byte_32le(address);
+ return memory_read_byte_32le(I.program, address);
}
INLINE UINT16 READ16(UINT32 ea)
{
@@ -486,10 +489,10 @@ INLINE UINT16 READ16(UINT32 ea)
address &= I.a20_mask;
if( ea & 0x1 ) { /* Unaligned read */
- value = (program_read_byte_32le( address+0 ) << 0) |
- (program_read_byte_32le( address+1 ) << 8);
+ value = (memory_read_byte_32le( I.program, address+0 ) << 0) |
+ (memory_read_byte_32le( I.program, address+1 ) << 8);
} else {
- value = program_read_word_32le( address );
+ value = memory_read_word_32le( I.program, address );
}
return value;
}
@@ -505,12 +508,12 @@ INLINE UINT32 READ32(UINT32 ea)
address &= I.a20_mask;
if( ea & 0x3 ) { /* Unaligned read */
- value = (program_read_byte_32le( address+0 ) << 0) |
- (program_read_byte_32le( address+1 ) << 8) |
- (program_read_byte_32le( address+2 ) << 16) |
- (program_read_byte_32le( address+3 ) << 24);
+ value = (memory_read_byte_32le( I.program, address+0 ) << 0) |
+ (memory_read_byte_32le( I.program, address+1 ) << 8) |
+ (memory_read_byte_32le( I.program, address+2 ) << 16) |
+ (memory_read_byte_32le( I.program, address+3 ) << 24);
} else {
- value = program_read_dword_32le( address );
+ value = memory_read_dword_32le( I.program, address );
}
return value;
}
@@ -527,17 +530,17 @@ INLINE UINT64 READ64(UINT32 ea)
address &= I.a20_mask;
if( ea & 0x7 ) { /* Unaligned read */
- value = (((UINT64) program_read_byte_32le( address+0 )) << 0) |
- (((UINT64) program_read_byte_32le( address+1 )) << 8) |
- (((UINT64) program_read_byte_32le( address+2 )) << 16) |
- (((UINT64) program_read_byte_32le( address+3 )) << 24) |
- (((UINT64) program_read_byte_32le( address+4 )) << 32) |
- (((UINT64) program_read_byte_32le( address+5 )) << 40) |
- (((UINT64) program_read_byte_32le( address+6 )) << 48) |
- (((UINT64) program_read_byte_32le( address+7 )) << 56);
+ value = (((UINT64) memory_read_byte_32le( I.program, address+0 )) << 0) |
+ (((UINT64) memory_read_byte_32le( I.program, address+1 )) << 8) |
+ (((UINT64) memory_read_byte_32le( I.program, address+2 )) << 16) |
+ (((UINT64) memory_read_byte_32le( I.program, address+3 )) << 24) |
+ (((UINT64) memory_read_byte_32le( I.program, address+4 )) << 32) |
+ (((UINT64) memory_read_byte_32le( I.program, address+5 )) << 40) |
+ (((UINT64) memory_read_byte_32le( I.program, address+6 )) << 48) |
+ (((UINT64) memory_read_byte_32le( I.program, address+7 )) << 56);
} else {
- value = (((UINT64) program_read_dword_32le( address+0 )) << 0) |
- (((UINT64) program_read_dword_32le( address+4 )) << 32);
+ value = (((UINT64) memory_read_dword_32le( I.program, address+0 )) << 0) |
+ (((UINT64) memory_read_dword_32le( I.program, address+4 )) << 32);
}
return value;
}
@@ -552,7 +555,7 @@ INLINE void WRITE8(UINT32 ea, UINT8 value)
}
address &= I.a20_mask;
- program_write_byte_32le(address, value);
+ memory_write_byte_32le(I.program, address, value);
}
INLINE void WRITE16(UINT32 ea, UINT16 value)
{
@@ -565,10 +568,10 @@ INLINE void WRITE16(UINT32 ea, UINT16 value)
address &= I.a20_mask;
if( ea & 0x1 ) { /* Unaligned write */
- program_write_byte_32le( address+0, value & 0xff );
- program_write_byte_32le( address+1, (value >> 8) & 0xff );
+ memory_write_byte_32le( I.program, address+0, value & 0xff );
+ memory_write_byte_32le( I.program, address+1, (value >> 8) & 0xff );
} else {
- program_write_word_32le(address, value);
+ memory_write_word_32le(I.program, address, value);
}
}
INLINE void WRITE32(UINT32 ea, UINT32 value)
@@ -582,12 +585,12 @@ INLINE void WRITE32(UINT32 ea, UINT32 value)
ea &= I.a20_mask;
if( ea & 0x3 ) { /* Unaligned write */
- program_write_byte_32le( address+0, value & 0xff );
- program_write_byte_32le( address+1, (value >> 8) & 0xff );
- program_write_byte_32le( address+2, (value >> 16) & 0xff );
- program_write_byte_32le( address+3, (value >> 24) & 0xff );
+ memory_write_byte_32le( I.program, address+0, value & 0xff );
+ memory_write_byte_32le( I.program, address+1, (value >> 8) & 0xff );
+ memory_write_byte_32le( I.program, address+2, (value >> 16) & 0xff );
+ memory_write_byte_32le( I.program, address+3, (value >> 24) & 0xff );
} else {
- program_write_dword_32le(address, value);
+ memory_write_dword_32le(I.program, address, value);
}
}
@@ -602,17 +605,17 @@ INLINE void WRITE64(UINT32 ea, UINT64 value)
ea &= I.a20_mask;
if( ea & 0x7 ) { /* Unaligned write */
- program_write_byte_32le( address+0, value & 0xff );
- program_write_byte_32le( address+1, (value >> 8) & 0xff );
- program_write_byte_32le( address+2, (value >> 16) & 0xff );
- program_write_byte_32le( address+3, (value >> 24) & 0xff );
- program_write_byte_32le( address+4, (value >> 32) & 0xff );
- program_write_byte_32le( address+5, (value >> 40) & 0xff );
- program_write_byte_32le( address+6, (value >> 48) & 0xff );
- program_write_byte_32le( address+7, (value >> 56) & 0xff );
+ memory_write_byte_32le( I.program, address+0, value & 0xff );
+ memory_write_byte_32le( I.program, address+1, (value >> 8) & 0xff );
+ memory_write_byte_32le( I.program, address+2, (value >> 16) & 0xff );
+ memory_write_byte_32le( I.program, address+3, (value >> 24) & 0xff );
+ memory_write_byte_32le( I.program, address+4, (value >> 32) & 0xff );
+ memory_write_byte_32le( I.program, address+5, (value >> 40) & 0xff );
+ memory_write_byte_32le( I.program, address+6, (value >> 48) & 0xff );
+ memory_write_byte_32le( I.program, address+7, (value >> 56) & 0xff );
} else {
- program_write_dword_32le(address+0, value & 0xffffffff);
- program_write_dword_32le(address+4, (value >> 32) & 0xffffffff);
+ memory_write_dword_32le(I.program, address+0, value & 0xffffffff);
+ memory_write_dword_32le(I.program, address+4, (value >> 32) & 0xffffffff);
}
}
@@ -893,11 +896,11 @@ INLINE void BUMP_DI(int adjustment)
/***********************************************************************************/
-#define READPORT8(port) (io_read_byte_32le(port))
-#define READPORT16(port) (io_read_word_32le(port))
-#define READPORT32(port) (io_read_dword_32le(port))
-#define WRITEPORT8(port, value) (io_write_byte_32le(port, value))
-#define WRITEPORT16(port, value) (io_write_word_32le(port, value))
-#define WRITEPORT32(port, value) (io_write_dword_32le(port, value))
+#define READPORT8(port) (memory_read_byte_32le(I.io, port))
+#define READPORT16(port) (memory_read_word_32le(I.io, port))
+#define READPORT32(port) (memory_read_dword_32le(I.io, port))
+#define WRITEPORT8(port, value) (memory_write_byte_32le(I.io, port, value))
+#define WRITEPORT16(port, value) (memory_write_word_32le(I.io, port, value))
+#define WRITEPORT32(port, value) (memory_write_dword_32le(I.io, port, value))
#endif /* __I386_H__ */
diff --git a/src/emu/cpu/i8085/i8085.c b/src/emu/cpu/i8085/i8085.c
index 00f2a3375fa..46e91839f9b 100644
--- a/src/emu/cpu/i8085/i8085.c
+++ b/src/emu/cpu/i8085/i8085.c
@@ -124,6 +124,7 @@
/*int survival_prot = 0; */
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "i8085.h"
#include "i8085cpu.h"
@@ -149,6 +150,8 @@ typedef struct {
INT8 irq_state[4];
cpu_irq_callback irq_callback;
const device_config *device;
+ const address_space *program;
+ const address_space *io;
void (*sod_callback)(int state);
int (*sid_callback)(void);
} i8085_Regs;
@@ -162,20 +165,20 @@ static UINT8 RIM_IEN = 0; //AT: IEN status latch used by the RIM instruction
static UINT8 ROP(void)
{
I.STATUS = 0xa2; // instruction fetch
- return program_decrypted_read_byte(I.PC.w.l++);
+ return memory_decrypted_read_byte(I.program, I.PC.w.l++);
}
static UINT8 ARG(void)
{
- return program_raw_read_byte(I.PC.w.l++);
+ return memory_raw_read_byte(I.program, I.PC.w.l++);
}
static UINT16 ARG16(void)
{
UINT16 w;
- w = program_raw_read_byte(I.PC.d);
+ w = memory_raw_read_byte(I.program, I.PC.d);
I.PC.w.l++;
- w += program_raw_read_byte(I.PC.d) << 8;
+ w += memory_raw_read_byte(I.program, I.PC.d) << 8;
I.PC.w.l++;
return w;
}
@@ -183,13 +186,13 @@ static UINT16 ARG16(void)
static UINT8 RM(UINT32 a)
{
I.STATUS = 0x82; // memory read
- return program_read_byte_8le(a);
+ return memory_read_byte_8le(I.program, a);
}
static void WM(UINT32 a, UINT8 v)
{
I.STATUS = 0x00; // memory write
- program_write_byte_8le(a, v);
+ memory_write_byte_8le(I.program, a, v);
}
INLINE void execute_one(int opcode)
@@ -1362,6 +1365,8 @@ static CPU_INIT( i8085 )
I.cputype = 1;
I.irq_callback = irqcallback;
I.device = device;
+ I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
state_save_register_item("i8085", device->tag, 0, I.AF.w.l);
state_save_register_item("i8085", device->tag, 0, I.BC.w.l);
@@ -1399,6 +1404,7 @@ static CPU_RESET( i8085 )
I.sod_callback = save_sodcallback;
I.sid_callback = save_sidcallback;
I.device = device;
+ I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
change_pc(I.PC.d);
I.cputype = cputype_bak;
diff --git a/src/emu/cpu/i8085/i8085cpu.h b/src/emu/cpu/i8085/i8085cpu.h
index 4947bd97dee..27919a1b42a 100644
--- a/src/emu/cpu/i8085/i8085cpu.h
+++ b/src/emu/cpu/i8085/i8085cpu.h
@@ -109,12 +109,12 @@ int q = I.AF.b.h+R; \
#define M_IN \
I.STATUS = 0x42; \
I.XX.d=ARG(); \
- I.AF.b.h=io_read_byte_8le(I.XX.d);
+ I.AF.b.h=memory_read_byte_8le(I.io, I.XX.d);
#define M_OUT \
I.STATUS = 0x10; \
I.XX.d=ARG(); \
- io_write_byte_8le(I.XX.d,I.AF.b.h)
+ memory_write_byte_8le(I.io, I.XX.d,I.AF.b.h)
#define M_DAD(R) { \
int q = I.HL.d + I.R.d; \
@@ -126,14 +126,14 @@ int q = I.AF.b.h+R; \
#define M_PUSH(R) { \
I.STATUS = 0x04; \
- program_write_byte_8le(--I.SP.w.l, I.R.b.h); \
- program_write_byte_8le(--I.SP.w.l, I.R.b.l); \
+ memory_write_byte_8le(I.program, --I.SP.w.l, I.R.b.h); \
+ memory_write_byte_8le(I.program, --I.SP.w.l, I.R.b.l); \
}
#define M_POP(R) { \
I.STATUS = 0x86; \
- I.R.b.l = program_read_byte_8le(I.SP.w.l++); \
- I.R.b.h = program_read_byte_8le(I.SP.w.l++); \
+ I.R.b.l = memory_read_byte_8le(I.program, I.SP.w.l++); \
+ I.R.b.h = memory_read_byte_8le(I.program, I.SP.w.l++); \
}
#define M_RET(cc) \
diff --git a/src/emu/cpu/i86/i286.c b/src/emu/cpu/i86/i286.c
index 70782d671a3..e4a779b01e0 100644
--- a/src/emu/cpu/i86/i286.c
+++ b/src/emu/cpu/i86/i286.c
@@ -3,6 +3,7 @@
* (initial work based on David Hedley's pcemu) *
****************************************************************************/
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "host.h"
@@ -59,6 +60,8 @@ typedef struct
} ldtr, tr;
cpu_irq_callback irq_callback;
const device_config *device;
+ const address_space *program;
+ const address_space *io;
INT32 AuxVal, OverVal, SignVal, ZeroVal, CarryVal, DirVal; /* 0 or non-0 valued flags */
UINT8 ParityVal;
UINT8 TF, IF; /* 0 or 1 valued flags */
@@ -288,6 +291,8 @@ static CPU_INIT( i80286 )
I.irq_callback = irqcallback;
I.device = device;
+ I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
/* If a reset parameter is given, take it as pointer to an address mask */
if( device->static_config )
diff --git a/src/emu/cpu/i86/i86.c b/src/emu/cpu/i86/i86.c
index 0d37fc6e387..b1740ce0e19 100644
--- a/src/emu/cpu/i86/i86.c
+++ b/src/emu/cpu/i86/i86.c
@@ -4,6 +4,7 @@
****************************************************************************/
/* 26.March 2000 PeT changed set_irq_line */
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "cpuintrf.h"
@@ -41,6 +42,8 @@ typedef struct
UINT16 flags;
cpu_irq_callback irq_callback;
const device_config *device;
+ const address_space *program;
+ const address_space *io;
INT32 AuxVal, OverVal, SignVal, ZeroVal, CarryVal, DirVal; /* 0 or non-0 valued flags */
UINT8 ParityVal;
UINT8 TF, IF; /* 0 or 1 valued flags */
@@ -143,6 +146,8 @@ static CPU_INIT( i8086 )
I.irq_callback = irqcallback;
I.device = device;
+ I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
i8086_state_register(device);
configure_memory_16bit();
@@ -167,6 +172,8 @@ static CPU_RESET( i8086 )
I.irq_callback = save_irqcallback;
I.mem = save_mem;
I.device = device;
+ I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
I.sregs[CS] = 0xf000;
I.base[CS] = SegBase(CS);
diff --git a/src/emu/cpu/i86/i86.h b/src/emu/cpu/i86/i86.h
index a13081431c3..3c7ff29861f 100644
--- a/src/emu/cpu/i86/i86.h
+++ b/src/emu/cpu/i86/i86.h
@@ -71,15 +71,15 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,SIH,SIL,DIH,DIL } BREGS;
/************************************************************************/
-#define read_byte(a) (*I.mem.rbyte)(a)
-#define read_word(a) (*I.mem.rword)(a)
-#define write_byte(a,d) (*I.mem.wbyte)((a),(d))
-#define write_word(a,d) (*I.mem.wword)((a),(d))
+#define read_byte(a) (*I.mem.rbyte)(I.program, a)
+#define read_word(a) (*I.mem.rword)(I.program, a)
+#define write_byte(a,d) (*I.mem.wbyte)(I.program, (a),(d))
+#define write_word(a,d) (*I.mem.wword)(I.program, (a),(d))
-#define read_port_byte(a) (*I.mem.rbyte_port)(a)
-#define read_port_word(a) (*I.mem.rword_port)(a)
-#define write_port_byte(a,d) (*I.mem.wbyte_port)((a),(d))
-#define write_port_word(a,d) (*I.mem.wword_port)((a),(d))
+#define read_port_byte(a) (*I.mem.rbyte)(I.io, a)
+#define read_port_word(a) (*I.mem.rword)(I.io, a)
+#define write_port_byte(a,d) (*I.mem.wbyte)(I.io, (a),(d))
+#define write_port_word(a,d) (*I.mem.wword)(I.io, (a),(d))
/************************************************************************/
@@ -99,10 +99,10 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,SIH,SIL,DIH,DIL } BREGS;
#define WriteWord(ea,val) write_word((ea) & AMASK, val);
#define FETCH_XOR(a) ((a) ^ I.mem.fetch_xor)
-#define FETCH (program_raw_read_byte(FETCH_XOR(I.pc++)))
-#define FETCHOP (program_decrypted_read_byte(FETCH_XOR(I.pc++)))
-#define PEEKOP(addr) (program_decrypted_read_byte(FETCH_XOR(addr)))
-#define FETCHWORD(var) { var = program_raw_read_byte(FETCH_XOR(I.pc)); var += (program_raw_read_byte(FETCH_XOR(I.pc + 1)) << 8); I.pc += 2; }
+#define FETCH (memory_raw_read_byte(I.program, FETCH_XOR(I.pc++)))
+#define FETCHOP (memory_decrypted_read_byte(I.program, FETCH_XOR(I.pc++)))
+#define PEEKOP(addr) (memory_decrypted_read_byte(I.program, FETCH_XOR(addr)))
+#define FETCHWORD(var) { var = memory_raw_read_byte(I.program, FETCH_XOR(I.pc)); var += (memory_raw_read_byte(I.program, FETCH_XOR(I.pc + 1)) << 8); I.pc += 2; }
#define CHANGE_PC(addr) change_pc(addr)
#define PUSH(val) { I.regs.w[SP] -= 2; WriteWord(((I.base[SS] + I.regs.w[SP]) & AMASK), val); }
#define POP(var) { var = ReadWord(((I.base[SS] + I.regs.w[SP]) & AMASK)); I.regs.w[SP] += 2; }
diff --git a/src/emu/cpu/i86/i86mem.c b/src/emu/cpu/i86/i86mem.c
index 47dbdc7d4c2..003627d16ad 100644
--- a/src/emu/cpu/i86/i86mem.c
+++ b/src/emu/cpu/i86/i86mem.c
@@ -8,15 +8,10 @@ static void configure_memory_8bit(void)
{
I.mem.fetch_xor = 0;
- I.mem.rbyte = program_read_byte_8le;
- I.mem.rword = program_read_word_8le;
- I.mem.wbyte = program_write_byte_8le;
- I.mem.wword = program_write_word_8le;
-
- I.mem.rbyte_port = io_read_byte_8le;
- I.mem.rword_port = io_read_word_8le;
- I.mem.wbyte_port = io_write_byte_8le;
- I.mem.wword_port = io_write_word_8le;
+ I.mem.rbyte = memory_read_byte_8le;
+ I.mem.rword = memory_read_word_8le;
+ I.mem.wbyte = memory_write_byte_8le;
+ I.mem.wword = memory_write_word_8le;
}
#endif
#endif
@@ -26,47 +21,25 @@ static void configure_memory_8bit(void)
16-bit memory accessors
*****************************************************************************/
-static UINT16 read_word_16le(offs_t addr)
-{
- if (!(addr & 1))
- return program_read_word_16le(addr);
- else
- {
- UINT16 result = program_read_byte_16le(addr);
- return result | (program_read_byte_16le(addr + 1) << 8);
- }
-}
-
-static void write_word_16le(offs_t addr, UINT16 data)
+static UINT16 read_word_16le(const address_space *space, offs_t addr)
{
if (!(addr & 1))
- program_write_word_16le(addr, data);
+ return memory_read_word_16le(space, addr);
else
{
- program_write_byte_16le(addr, data);
- program_write_byte_16le(addr + 1, data >> 8);
+ UINT16 result = memory_read_byte_16le(space, addr);
+ return result | (memory_read_byte_16le(space, addr + 1) << 8);
}
}
-static UINT16 read_port_word_16le(offs_t addr)
+static void write_word_16le(const address_space *space, offs_t addr, UINT16 data)
{
if (!(addr & 1))
- return io_read_word_16le(addr);
+ memory_write_word_16le(space, addr, data);
else
{
- UINT16 result = io_read_byte_16le(addr);
- return result | (io_read_byte_16le(addr + 1) << 8);
- }
-}
-
-static void write_port_word_16le(offs_t addr, UINT16 data)
-{
- if (!(addr & 1))
- io_write_word_16le(addr, data);
- else
- {
- io_write_byte_16le(addr, data);
- io_write_byte_16le(addr + 1, data >> 8);
+ memory_write_byte_16le(space, addr, data);
+ memory_write_byte_16le(space, addr + 1, data >> 8);
}
}
@@ -74,13 +47,8 @@ static void configure_memory_16bit(void)
{
I.mem.fetch_xor = BYTE_XOR_LE(0);
- I.mem.rbyte = program_read_byte_16le;
+ I.mem.rbyte = memory_read_byte_16le;
I.mem.rword = read_word_16le;
- I.mem.wbyte = program_write_byte_16le;
+ I.mem.wbyte = memory_write_byte_16le;
I.mem.wword = write_word_16le;
-
- I.mem.rbyte_port = io_read_byte_16le;
- I.mem.rword_port = read_port_word_16le;
- I.mem.wbyte_port = io_write_byte_16le;
- I.mem.wword_port = write_port_word_16le;
}
diff --git a/src/emu/cpu/i86/i86mem.h b/src/emu/cpu/i86/i86mem.h
index 55eaf874c62..9bccd2a2342 100644
--- a/src/emu/cpu/i86/i86mem.h
+++ b/src/emu/cpu/i86/i86mem.h
@@ -3,13 +3,8 @@ struct _memory_interface
{
offs_t fetch_xor;
- UINT8 (*rbyte)(offs_t);
- UINT16 (*rword)(offs_t);
- void (*wbyte)(offs_t, UINT8);
- void (*wword)(offs_t, UINT16);
-
- UINT8 (*rbyte_port)(offs_t);
- UINT16 (*rword_port)(offs_t);
- void (*wbyte_port)(offs_t, UINT8);
- void (*wword_port)(offs_t, UINT16);
+ UINT8 (*rbyte)(const address_space *, offs_t);
+ UINT16 (*rword)(const address_space *, offs_t);
+ void (*wbyte)(const address_space *, offs_t, UINT8);
+ void (*wword)(const address_space *, offs_t, UINT16);
};
diff --git a/src/emu/cpu/i8x41/i8x41.c b/src/emu/cpu/i8x41/i8x41.c
index 27be9f939fe..ce5c9206697 100644
--- a/src/emu/cpu/i8x41/i8x41.c
+++ b/src/emu/cpu/i8x41/i8x41.c
@@ -114,6 +114,7 @@
*/
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "i8x41.h"
@@ -137,19 +138,22 @@ struct _upi41_state_t {
UINT8 ram_mask;
cpu_irq_callback irq_callback;
const device_config *device;
+ const address_space *program;
+ const address_space *data;
+ const address_space *io;
int icount;
};
-#define RM(a) program_read_byte_8le(a)
+#define RM(s,a) memory_read_byte_8le((s)->program, a)
-#define IRAM_R(a) data_read_byte_8le((a) & upi41_state->ram_mask)
-#define IRAM_W(a,v) data_write_byte_8le((a) & upi41_state->ram_mask, v)
+#define IRAM_R(s,a) memory_read_byte_8le((s)->data, (a) & upi41_state->ram_mask)
+#define IRAM_W(s,a,v) memory_write_byte_8le((s)->data, (a) & upi41_state->ram_mask, v)
-#define RP(a) io_read_byte_8le(a)
-#define WP(a,v) io_write_byte_8le(a,v)
+#define RP(s,a) memory_read_byte_8le((s)->io, a)
+#define WP(s,a,v) memory_write_byte_8le((s)->io, a,v)
-#define ROP(pc) program_decrypted_read_byte(pc)
-#define ROP_ARG(pc) program_raw_read_byte(pc)
+#define ROP(s,pc) memory_decrypted_read_byte((s)->program, pc)
+#define ROP_ARG(s,pc) memory_raw_read_byte((s)->program, pc)
/* PC vectors */
#define V_RESET 0x000 /* power on address */
@@ -218,8 +222,8 @@ struct _upi41_state_t {
#define CONTROL upi41_state->control
-#define GETR(n) (IRAM_R(((PSW & BS) ? M_BANK1:M_BANK0)+(n)))
-#define SETR(n,v) (IRAM_W(((PSW & BS) ? M_BANK1:M_BANK0)+(n), (v)))
+#define GETR(s,n) (IRAM_R((s), ((PSW & BS) ? M_BANK1:M_BANK0)+(n)))
+#define SETR(s,n,v) (IRAM_W((s), ((PSW & BS) ? M_BANK1:M_BANK0)+(n), (v)))
static void set_irq_line(upi41_state_t *upi41_state, int irqline, int state);
@@ -229,8 +233,8 @@ static void set_irq_line(upi41_state_t *upi41_state, int irqline, int state);
INLINE void push_pc_to_stack(upi41_state_t *upi41_state)
{
- IRAM_W( M_STACK + (PSW&SP) * 2 + 0, PC & 0xff);
- IRAM_W( M_STACK + (PSW&SP) * 2 + 1, ((PC >> 8) & 0x0f) | (PSW & 0xf0) );
+ IRAM_W( upi41_state, M_STACK + (PSW&SP) * 2 + 0, PC & 0xff);
+ IRAM_W( upi41_state, M_STACK + (PSW&SP) * 2 + 1, ((PC >> 8) & 0x0f) | (PSW & 0xf0) );
PSW = (PSW & ~SP) | ((PSW + 1) & SP);
}
@@ -839,6 +843,9 @@ static CPU_INIT( i8x41 )
upi41_state->irq_callback = irqcallback;
upi41_state->device = device;
+ upi41_state->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ upi41_state->data = memory_find_address_space(device, ADDRESS_SPACE_DATA);
+ upi41_state->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
upi41_state->subtype = 8041;
upi41_state->ram_mask = I8X41_intRAM_MASK;
@@ -919,7 +926,7 @@ static CPU_EXECUTE( i8x41 )
do
{
- UINT8 op = program_decrypted_read_byte(PC);
+ UINT8 op = memory_decrypted_read_byte(upi41_state->program, PC);
PPC = PC;
@@ -935,7 +942,7 @@ static CPU_EXECUTE( i8x41 )
inst_cycles = i8x41_cycles[op];
for ( ; inst_cycles > 0; inst_cycles-- )
{
- T1_level = RP(I8X41_t1);
+ T1_level = RP(upi41_state, I8X41_t1);
if( (CONTROL & TEST1) && (T1_level == 0) ) /* Negative Edge */
{
upi41_state->timer++;
@@ -1112,15 +1119,15 @@ static CPU_SET_INFO( i8x41 )
case CPUINFO_INT_REGISTER + I8X41_PSW: PSW = info->i; break;
case CPUINFO_INT_REGISTER + I8X41_A: A = info->i; break;
- case CPUINFO_INT_REGISTER + I8X41_T: upi41_state->timer = info->i & 0x1fff; break;
- case CPUINFO_INT_REGISTER + I8X41_R0: SETR(0, info->i); break;
- case CPUINFO_INT_REGISTER + I8X41_R1: SETR(1, info->i); break;
- case CPUINFO_INT_REGISTER + I8X41_R2: SETR(2, info->i); break;
- case CPUINFO_INT_REGISTER + I8X41_R3: SETR(3, info->i); break;
- case CPUINFO_INT_REGISTER + I8X41_R4: SETR(4, info->i); break;
- case CPUINFO_INT_REGISTER + I8X41_R5: SETR(5, info->i); break;
- case CPUINFO_INT_REGISTER + I8X41_R6: SETR(6, info->i); break;
- case CPUINFO_INT_REGISTER + I8X41_R7: SETR(7, info->i); break;
+ case CPUINFO_INT_REGISTER + I8X41_T: upi41_state->timer = info->i & 0x1fff; break;
+ case CPUINFO_INT_REGISTER + I8X41_R0: SETR(upi41_state, 0, info->i); break;
+ case CPUINFO_INT_REGISTER + I8X41_R1: SETR(upi41_state, 1, info->i); break;
+ case CPUINFO_INT_REGISTER + I8X41_R2: SETR(upi41_state, 2, info->i); break;
+ case CPUINFO_INT_REGISTER + I8X41_R3: SETR(upi41_state, 3, info->i); break;
+ case CPUINFO_INT_REGISTER + I8X41_R4: SETR(upi41_state, 4, info->i); break;
+ case CPUINFO_INT_REGISTER + I8X41_R5: SETR(upi41_state, 5, info->i); break;
+ case CPUINFO_INT_REGISTER + I8X41_R6: SETR(upi41_state, 6, info->i); break;
+ case CPUINFO_INT_REGISTER + I8X41_R7: SETR(upi41_state, 7, info->i); break;
case CPUINFO_INT_REGISTER + I8X41_DATA:
DBBI = info->i;
@@ -1135,7 +1142,7 @@ static CPU_SET_INFO( i8x41 )
P2_HS |= 0x20;
if( 0 == (STATE & OBF) ) P2_HS |= 0x10;
else P2_HS &= 0xef;
- WP(0x02, (P2 & P2_HS) ); /* Assert the DBBI IRQ out on P25 */
+ WP(upi41_state, 0x02, (P2 & P2_HS) ); /* Assert the DBBI IRQ out on P25 */
}
break;
@@ -1160,7 +1167,7 @@ static CPU_SET_INFO( i8x41 )
P2_HS |= 0x20;
if( 0 == (STATE & OBF) ) P2_HS |= 0x10;
else P2_HS &= 0xef;
- WP(0x02, (P2 & P2_HS) ); /* Assert the DBBI IRQ out on P25 */
+ WP(upi41_state, 0x02, (P2 & P2_HS) ); /* Assert the DBBI IRQ out on P25 */
}
break;
@@ -1231,14 +1238,14 @@ CPU_GET_INFO( i8041 )
case CPUINFO_INT_REGISTER + I8X41_PSW: info->i = PSW; break;
case CPUINFO_INT_REGISTER + I8X41_A: info->i = A; break;
case CPUINFO_INT_REGISTER + I8X41_T: info->i = upi41_state->timer; break;
- case CPUINFO_INT_REGISTER + I8X41_R0: info->i = GETR(0); break;
- case CPUINFO_INT_REGISTER + I8X41_R1: info->i = GETR(1); break;
- case CPUINFO_INT_REGISTER + I8X41_R2: info->i = GETR(2); break;
- case CPUINFO_INT_REGISTER + I8X41_R3: info->i = GETR(3); break;
- case CPUINFO_INT_REGISTER + I8X41_R4: info->i = GETR(4); break;
- case CPUINFO_INT_REGISTER + I8X41_R5: info->i = GETR(5); break;
- case CPUINFO_INT_REGISTER + I8X41_R6: info->i = GETR(6); break;
- case CPUINFO_INT_REGISTER + I8X41_R7: info->i = GETR(7); break;
+ case CPUINFO_INT_REGISTER + I8X41_R0: info->i = GETR(upi41_state, 0); break;
+ case CPUINFO_INT_REGISTER + I8X41_R1: info->i = GETR(upi41_state, 1); break;
+ case CPUINFO_INT_REGISTER + I8X41_R2: info->i = GETR(upi41_state, 2); break;
+ case CPUINFO_INT_REGISTER + I8X41_R3: info->i = GETR(upi41_state, 3); break;
+ case CPUINFO_INT_REGISTER + I8X41_R4: info->i = GETR(upi41_state, 4); break;
+ case CPUINFO_INT_REGISTER + I8X41_R5: info->i = GETR(upi41_state, 5); break;
+ case CPUINFO_INT_REGISTER + I8X41_R6: info->i = GETR(upi41_state, 6); break;
+ case CPUINFO_INT_REGISTER + I8X41_R7: info->i = GETR(upi41_state, 7); break;
case CPUINFO_INT_REGISTER + I8X41_DATA:
STATE &= ~OBF; /* reset the output buffer full flag */
@@ -1247,7 +1254,7 @@ CPU_GET_INFO( i8041 )
P2_HS &= 0xef;
if( STATE & IBF ) P2_HS |= 0x20;
else P2_HS &= 0xdf;
- WP(0x02, (P2 & P2_HS) ); /* Clear the DBBO IRQ out on P24 */
+ WP(upi41_state, 0x02, (P2 & P2_HS) ); /* Clear the DBBO IRQ out on P24 */
}
info->i = DBBO;
break;
@@ -1299,14 +1306,14 @@ CPU_GET_INFO( i8041 )
case CPUINFO_STR_REGISTER + I8X41_PSW: sprintf(info->s, "PSW:%02X", upi41_state->psw); break;
case CPUINFO_STR_REGISTER + I8X41_A: sprintf(info->s, "A:%02X", upi41_state->a); break;
case CPUINFO_STR_REGISTER + I8X41_T: sprintf(info->s, "T:%02X.%02X", upi41_state->timer, (upi41_state->prescaler & 0x1f) ); break;
- case CPUINFO_STR_REGISTER + I8X41_R0: sprintf(info->s, "R0:%02X", GETR(0)); break;
- case CPUINFO_STR_REGISTER + I8X41_R1: sprintf(info->s, "R1:%02X", GETR(1)); break;
- case CPUINFO_STR_REGISTER + I8X41_R2: sprintf(info->s, "R2:%02X", GETR(2)); break;
- case CPUINFO_STR_REGISTER + I8X41_R3: sprintf(info->s, "R3:%02X", GETR(3)); break;
- case CPUINFO_STR_REGISTER + I8X41_R4: sprintf(info->s, "R4:%02X", GETR(4)); break;
- case CPUINFO_STR_REGISTER + I8X41_R5: sprintf(info->s, "R5:%02X", GETR(5)); break;
- case CPUINFO_STR_REGISTER + I8X41_R6: sprintf(info->s, "R6:%02X", GETR(6)); break;
- case CPUINFO_STR_REGISTER + I8X41_R7: sprintf(info->s, "R7:%02X", GETR(7)); break;
+ case CPUINFO_STR_REGISTER + I8X41_R0: sprintf(info->s, "R0:%02X", GETR(upi41_state, 0));break;
+ case CPUINFO_STR_REGISTER + I8X41_R1: sprintf(info->s, "R1:%02X", GETR(upi41_state, 1));break;
+ case CPUINFO_STR_REGISTER + I8X41_R2: sprintf(info->s, "R2:%02X", GETR(upi41_state, 2));break;
+ case CPUINFO_STR_REGISTER + I8X41_R3: sprintf(info->s, "R3:%02X", GETR(upi41_state, 3));break;
+ case CPUINFO_STR_REGISTER + I8X41_R4: sprintf(info->s, "R4:%02X", GETR(upi41_state, 4));break;
+ case CPUINFO_STR_REGISTER + I8X41_R5: sprintf(info->s, "R5:%02X", GETR(upi41_state, 5));break;
+ case CPUINFO_STR_REGISTER + I8X41_R6: sprintf(info->s, "R6:%02X", GETR(upi41_state, 6));break;
+ case CPUINFO_STR_REGISTER + I8X41_R7: sprintf(info->s, "R7:%02X", GETR(upi41_state, 7));break;
case CPUINFO_STR_REGISTER + I8X41_P1: sprintf(info->s, "P1:%02X", upi41_state->p1); break;
case CPUINFO_STR_REGISTER + I8X41_P2: sprintf(info->s, "P2:%02X", upi41_state->p2); break;
case CPUINFO_STR_REGISTER + I8X41_DATA_DASM: sprintf(info->s, "DBBI:%02X", upi41_state->dbbi); break;
diff --git a/src/emu/cpu/i8x41/i8x41ops.c b/src/emu/cpu/i8x41/i8x41ops.c
index 53086936542..78d02c5ed1d 100644
--- a/src/emu/cpu/i8x41/i8x41ops.c
+++ b/src/emu/cpu/i8x41/i8x41ops.c
@@ -10,7 +10,7 @@
***********************************/
OP_HANDLER( illegal )
{
- logerror("i8x41 #%d: illegal opcode at 0x%03x: %02x\n", cpunum_get_active(), PC, ROP(PC));
+ logerror("i8x41 #%d: illegal opcode at 0x%03x: %02x\n", cpunum_get_active(), PC, ROP(upi41_state, PC));
}
/***********************************
@@ -18,7 +18,7 @@ OP_HANDLER( illegal )
***********************************/
OP_HANDLER( add_r )
{
- UINT8 res = A + GETR(r);
+ UINT8 res = A + GETR(upi41_state, r);
if( res < A ) PSW |= FC;
if( (res & 0x0f) < (A & 0x0f) ) PSW |= FA;
A = res;
@@ -30,7 +30,7 @@ OP_HANDLER( add_r )
***********************************/
OP_HANDLER( add_rm )
{
- UINT8 res = A + IRAM_R(GETR(r));
+ UINT8 res = A + IRAM_R(upi41_state, GETR(upi41_state, r));
if( res < A ) PSW |= FC;
if( (res & 0x0f) < (A & 0x0f) ) PSW |= FA;
A = res;
@@ -42,7 +42,7 @@ OP_HANDLER( add_rm )
***********************************/
OP_HANDLER( add_i )
{
- UINT8 res = A + ROP_ARG(PC);
+ UINT8 res = A + ROP_ARG(upi41_state, PC);
PC++;
if( res < A ) PSW |= FC;
if( (res & 0x0f) < (A & 0x0f) ) PSW |= FA;
@@ -55,7 +55,7 @@ OP_HANDLER( add_i )
***********************************/
OP_HANDLER( addc_r )
{
- UINT8 res = A + GETR(r) + (PSW >> 7);
+ UINT8 res = A + GETR(upi41_state, r) + (PSW >> 7);
if( res <= A ) PSW |= FC;
if( (res & 0x0f) <= (A & 0x0f) ) PSW |= FA;
A = res;
@@ -67,7 +67,7 @@ OP_HANDLER( addc_r )
***********************************/
OP_HANDLER( addc_rm )
{
- UINT8 res = A + IRAM_R(GETR(r)) + (PSW >> 7);
+ UINT8 res = A + IRAM_R(upi41_state, GETR(upi41_state, r)) + (PSW >> 7);
if( res <= A ) PSW |= FC;
if( (res & 0x0f) <= (A & 0x0f) ) PSW |= FA;
A = res;
@@ -79,7 +79,7 @@ OP_HANDLER( addc_rm )
***********************************/
OP_HANDLER( addc_i )
{
- UINT8 res = A + ROP_ARG(PC) + (PSW >> 7);
+ UINT8 res = A + ROP_ARG(upi41_state, PC) + (PSW >> 7);
PC++;
if( res <= A ) PSW |= FC;
if( (res & 0x0f) < (A & 0x0f) ) PSW |= FA;
@@ -92,7 +92,7 @@ OP_HANDLER( addc_i )
***********************************/
OP_HANDLER( anl_r )
{
- A = A & GETR(r);
+ A = A & GETR(upi41_state, r);
}
/***********************************
@@ -101,7 +101,7 @@ OP_HANDLER( anl_r )
***********************************/
OP_HANDLER( anl_rm )
{
- A = A & IRAM_R(GETR(r));
+ A = A & IRAM_R(upi41_state, GETR(upi41_state, r));
}
/***********************************
@@ -110,7 +110,7 @@ OP_HANDLER( anl_rm )
***********************************/
OP_HANDLER( anl_i )
{
- A = A & ROP_ARG(PC);
+ A = A & ROP_ARG(upi41_state, PC);
PC++;
}
@@ -121,14 +121,14 @@ OP_HANDLER( anl_i )
OP_HANDLER( anl_p_i )
{
UINT8 p = r;
- UINT8 val = ROP_ARG(PC);
+ UINT8 val = ROP_ARG(upi41_state, PC);
PC++;
/* changed to latched port scheme */
switch (p)
{
case 00: break; /* invalid port */
- case 01: P1 &= val; WP(p, P1); break;
- case 02: P2 &= val; WP(p, (P2 & P2_HS) ); break;
+ case 01: P1 &= val; WP(upi41_state, p, P1); break;
+ case 02: P2 &= val; WP(upi41_state, p, (P2 & P2_HS) ); break;
case 03: break; /* invalid port */
default: break;
}
@@ -142,10 +142,10 @@ OP_HANDLER( anld_p_a )
{
UINT8 p = r;
/* added proper expanded port setup */
- WP(2, (P2 & 0xf0) | 0x0c | p); /* AND mode */
- WP(I8X41_ps, 0); /* activate command strobe */
- WP(2, (A & 0x0f)); /* Expander to take care of AND function */
- WP(I8X41_ps, 1); /* release command strobe */
+ WP(upi41_state, 2, (P2 & 0xf0) | 0x0c | p); /* AND mode */
+ WP(upi41_state, I8X41_ps, 0); /* activate command strobe */
+ WP(upi41_state, 2, (A & 0x0f)); /* Expander to take care of AND function */
+ WP(upi41_state, I8X41_ps, 1); /* release command strobe */
}
/***********************************
@@ -155,7 +155,7 @@ OP_HANDLER( anld_p_a )
OP_HANDLER( call_i )
{
UINT16 page = (r & 0xe0) << 3;
- UINT8 adr = ROP_ARG(PC);
+ UINT8 adr = ROP_ARG(upi41_state, PC);
PC++;
PUSH_PC_TO_STACK();
PC = page | adr;
@@ -266,7 +266,7 @@ OP_HANDLER( dec_a )
***********************************/
OP_HANDLER( dec_r )
{
- SETR(r, GETR(r) - 1);
+ SETR(upi41_state, r, GETR(upi41_state, r) - 1);
}
/***********************************
@@ -293,10 +293,10 @@ OP_HANDLER( dis_tcnti )
***********************************/
OP_HANDLER( djnz_r_i )
{
- UINT8 adr = ROP_ARG(PC);
+ UINT8 adr = ROP_ARG(upi41_state, PC);
PC++;
- SETR(r, GETR(r) - 1);
- if( GETR(r) )
+ SETR(upi41_state, r, GETR(upi41_state, r) - 1);
+ if( GETR(upi41_state, r) )
PC = (PC & 0x700) | adr;
}
@@ -308,7 +308,7 @@ OP_HANDLER( en_dma )
{
ENABLE |= DMA; /* enable DMA handshake lines */
P2_HS &= 0xbf;
- WP(0x02, (P2 & P2_HS) );
+ WP(upi41_state, 0x02, (P2 & P2_HS) );
}
/***********************************
@@ -326,7 +326,7 @@ OP_HANDLER( en_flags )
else P2_HS &= 0xef;
if( STATE & IBF ) P2_HS |= 0x20;
else P2_HS &= 0xdf;
- WP(0x02, (P2 & P2_HS) );
+ WP(upi41_state, 0x02, (P2 & P2_HS) );
}
}
@@ -370,7 +370,7 @@ OP_HANDLER( in_a_dbb )
P2_HS &= 0xdf;
if( STATE & OBF ) P2_HS |= 0x10;
else P2_HS &= 0xef;
- WP(0x02, (P2 & P2_HS) ); /* Clear the DBBI IRQ out on P25 */
+ WP(upi41_state, 0x02, (P2 & P2_HS) ); /* Clear the DBBI IRQ out on P25 */
}
A = DBBI;
}
@@ -386,8 +386,8 @@ OP_HANDLER( in_a_p )
switch( p )
{
case 00: break; /* invalid port */
- case 01: A = (RP(p) & P1); break;
- case 02: A = (RP(p) & P2); break;
+ case 01: A = (RP(upi41_state, p) & P1); break;
+ case 02: A = (RP(upi41_state, p) & P2); break;
case 03: break; /* invalid port */
default: break;
}
@@ -408,7 +408,7 @@ OP_HANDLER( inc_a )
***********************************/
OP_HANDLER( inc_r )
{
- SETR(r, GETR(r) + 1);
+ SETR(upi41_state, r, GETR(upi41_state, r) + 1);
}
/***********************************
@@ -417,8 +417,8 @@ OP_HANDLER( inc_r )
***********************************/
OP_HANDLER( inc_rm )
{
- UINT16 addr = GETR(r);
- IRAM_W( addr, IRAM_R(addr) + 1 );
+ UINT16 addr = GETR(upi41_state, r);
+ IRAM_W(upi41_state, addr, IRAM_R(upi41_state, addr) + 1 );
}
/***********************************
@@ -428,7 +428,7 @@ OP_HANDLER( inc_rm )
OP_HANDLER( jbb_i )
{
UINT8 bit = r;
- UINT8 adr = ROP_ARG(PC);
+ UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( A & (1 << bit) )
PC = (PC & 0x700) | adr;
@@ -440,7 +440,7 @@ OP_HANDLER( jbb_i )
***********************************/
OP_HANDLER( jc_i )
{
- UINT8 adr = ROP_ARG(PC);
+ UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( PSW & FC )
PC = (PC & 0x700) | adr;
@@ -452,7 +452,7 @@ OP_HANDLER( jc_i )
***********************************/
OP_HANDLER( jf0_i )
{
- UINT8 adr = ROP_ARG(PC);
+ UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( STATE & F0 )
PC = (PC & 0x700) | adr;
@@ -464,7 +464,7 @@ OP_HANDLER( jf0_i )
***********************************/
OP_HANDLER( jf1_i )
{
- UINT8 adr = ROP_ARG(PC);
+ UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( STATE & F1 )
PC = (PC & 0x700) | adr;
@@ -481,7 +481,7 @@ OP_HANDLER( jmp_i )
* JMP is said to use aaa0 (8 pages)
*/
UINT16 page = ((r & 0xe0) << 3);
- UINT8 adr = ROP_ARG(PC);
+ UINT8 adr = ROP_ARG(upi41_state, PC);
PC = page | adr;
}
@@ -492,7 +492,7 @@ OP_HANDLER( jmp_i )
OP_HANDLER( jmpp_a )
{
UINT16 adr = (PC & 0x700) | A;
- PC = (PC & 0x700) | RM(adr);
+ PC = (PC & 0x700) | RM(upi41_state, adr);
}
/***********************************
@@ -501,7 +501,7 @@ OP_HANDLER( jmpp_a )
***********************************/
OP_HANDLER( jnc_i )
{
- UINT8 adr = ROP_ARG(PC);
+ UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( !(PSW & FC) )
PC = (PC & 0x700) | adr;
@@ -513,7 +513,7 @@ OP_HANDLER( jnc_i )
***********************************/
OP_HANDLER( jnibf_i )
{
- UINT8 adr = ROP_ARG(PC);
+ UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( 0 == (STATE & IBF) )
PC = (PC & 0x700) | adr;
@@ -525,9 +525,9 @@ OP_HANDLER( jnibf_i )
***********************************/
OP_HANDLER( jnt0_i )
{
- UINT8 adr = ROP_ARG(PC);
+ UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
- if( 0 == RP(I8X41_t0) )
+ if( 0 == RP(upi41_state, I8X41_t0) )
PC = (PC & 0x700) | adr;
}
@@ -537,11 +537,11 @@ OP_HANDLER( jnt0_i )
***********************************/
OP_HANDLER( jnt1_i )
{
- UINT8 adr = ROP_ARG(PC);
+ UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( !(ENABLE & CNT) )
{
- UINT8 level = RP(I8X41_t1);
+ UINT8 level = RP(upi41_state, I8X41_t1);
if( level ) CONTROL |= TEST1;
else CONTROL &= ~TEST1;
}
@@ -555,7 +555,7 @@ OP_HANDLER( jnt1_i )
***********************************/
OP_HANDLER( jnz_i )
{
- UINT8 adr = ROP_ARG(PC);
+ UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( A )
PC = (PC & 0x700) | adr;
@@ -567,7 +567,7 @@ OP_HANDLER( jnz_i )
***********************************/
OP_HANDLER( jobf_i )
{
- UINT8 adr = ROP_ARG(PC);
+ UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( STATE & OBF )
PC = (PC & 0x700) | adr;
@@ -579,7 +579,7 @@ OP_HANDLER( jobf_i )
***********************************/
OP_HANDLER( jtf_i )
{
- UINT8 adr = ROP_ARG(PC);
+ UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( CONTROL & TOVF )
PC = (PC & 0x700) | adr;
@@ -592,9 +592,9 @@ OP_HANDLER( jtf_i )
***********************************/
OP_HANDLER( jt0_i )
{
- UINT8 adr = ROP_ARG(PC);
+ UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
- if( RP(I8X41_t0) )
+ if( RP(upi41_state, I8X41_t0) )
PC = (PC & 0x700) | adr;
}
@@ -604,11 +604,11 @@ OP_HANDLER( jt0_i )
***********************************/
OP_HANDLER( jt1_i )
{
- UINT8 adr = ROP_ARG(PC);
+ UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( !(ENABLE & CNT) )
{
- UINT8 level = RP(I8X41_t1);
+ UINT8 level = RP(upi41_state, I8X41_t1);
if( level ) CONTROL |= TEST1;
else CONTROL &= ~TEST1;
}
@@ -622,7 +622,7 @@ OP_HANDLER( jt1_i )
***********************************/
OP_HANDLER( jz_i )
{
- UINT8 adr = ROP_ARG(PC);
+ UINT8 adr = ROP_ARG(upi41_state, PC);
PC += 1;
if( !A )
PC = (PC & 0x700) | adr;
@@ -634,7 +634,7 @@ OP_HANDLER( jz_i )
***********************************/
OP_HANDLER( mov_a_i )
{
- A = ROP(PC);
+ A = ROP(upi41_state, PC);
PC += 1;
}
@@ -653,7 +653,7 @@ OP_HANDLER( mov_a_psw )
***********************************/
OP_HANDLER( mov_a_r )
{
- A = GETR(r);
+ A = GETR(upi41_state, r);
}
/***********************************
@@ -662,7 +662,7 @@ OP_HANDLER( mov_a_r )
***********************************/
OP_HANDLER( mov_a_rm )
{
- A = IRAM_R(GETR(r));
+ A = IRAM_R(upi41_state, GETR(upi41_state, r));
}
/***********************************
@@ -689,7 +689,7 @@ OP_HANDLER( mov_psw_a )
***********************************/
OP_HANDLER( mov_r_a )
{
- SETR(r, A);
+ SETR(upi41_state, r, A);
}
/***********************************
@@ -698,9 +698,9 @@ OP_HANDLER( mov_r_a )
***********************************/
OP_HANDLER( mov_r_i )
{
- UINT8 val = ROP_ARG(PC);
+ UINT8 val = ROP_ARG(upi41_state, PC);
PC += 1;
- SETR(r, val);
+ SETR(upi41_state, r, val);
}
/***********************************
@@ -709,7 +709,7 @@ OP_HANDLER( mov_r_i )
***********************************/
OP_HANDLER( mov_rm_a )
{
- IRAM_W(GETR(r), A );
+ IRAM_W(upi41_state, GETR(upi41_state, r), A );
}
/***********************************
@@ -718,9 +718,9 @@ OP_HANDLER( mov_rm_a )
***********************************/
OP_HANDLER( mov_rm_i )
{
- UINT8 val = ROP_ARG(PC);
+ UINT8 val = ROP_ARG(upi41_state, PC);
PC += 1;
- IRAM_W(GETR(r), val );
+ IRAM_W(upi41_state, GETR(upi41_state, r), val );
}
/***********************************
@@ -749,10 +749,10 @@ OP_HANDLER( movd_a_p )
{
UINT8 p = r;
/* added proper expanded port setup */
- WP(2, (P2 & 0xf0) | 0x00 | p); /* READ mode */
- WP(I8X41_ps, 0); /* activate command strobe */
- A = RP(2) & 0xf;
- WP(I8X41_ps, 1); /* release command strobe */
+ WP(upi41_state, 2, (P2 & 0xf0) | 0x00 | p); /* READ mode */
+ WP(upi41_state, I8X41_ps, 0); /* activate command strobe */
+ A = RP(upi41_state, 2) & 0xf;
+ WP(upi41_state, I8X41_ps, 1); /* release command strobe */
}
/***********************************
@@ -763,10 +763,10 @@ OP_HANDLER( movd_p_a )
{
UINT8 p = r;
/* added proper expanded port setup */
- WP(2, (P2 & 0xf0) | 0x04 | p); /* WRITE mode */
- WP(I8X41_ps, 0); /* activate command strobe */
- WP(2, A & 0x0f);
- WP(I8X41_ps, 1); /* release command strobe */
+ WP(upi41_state, 2, (P2 & 0xf0) | 0x04 | p); /* WRITE mode */
+ WP(upi41_state, I8X41_ps, 0); /* activate command strobe */
+ WP(upi41_state, 2, A & 0x0f);
+ WP(upi41_state, I8X41_ps, 1); /* release command strobe */
}
/***********************************
@@ -776,7 +776,7 @@ OP_HANDLER( movd_p_a )
OP_HANDLER( movp_a_am )
{
UINT16 addr = (PC & 0x700) | A;
- A = RM(addr);
+ A = RM(upi41_state, addr);
}
/***********************************
@@ -786,7 +786,7 @@ OP_HANDLER( movp_a_am )
OP_HANDLER( movp3_a_am )
{
UINT16 addr = 0x300 | A;
- A = RM(addr);
+ A = RM(upi41_state, addr);
}
/***********************************
@@ -803,7 +803,7 @@ OP_HANDLER( nop )
***********************************/
OP_HANDLER( orl_r )
{
- A = A | GETR(r);
+ A = A | GETR(upi41_state, r);
}
/***********************************
@@ -812,7 +812,7 @@ OP_HANDLER( orl_r )
***********************************/
OP_HANDLER( orl_rm )
{
- A = A | IRAM_R(GETR(r));
+ A = A | IRAM_R(upi41_state, GETR(upi41_state, r));
}
/***********************************
@@ -821,7 +821,7 @@ OP_HANDLER( orl_rm )
***********************************/
OP_HANDLER( orl_i )
{
- UINT8 val = ROP_ARG(PC);
+ UINT8 val = ROP_ARG(upi41_state, PC);
PC++;
A = A | val;
}
@@ -833,14 +833,14 @@ OP_HANDLER( orl_i )
OP_HANDLER( orl_p_i )
{
UINT8 p = r;
- UINT8 val = ROP_ARG(PC);
+ UINT8 val = ROP_ARG(upi41_state, PC);
PC++;
/* changed to latched port scheme */
switch (p)
{
case 00: break; /* invalid port */
- case 01: P1 |= val; WP(p, P1); break;
- case 02: P2 |= val; WP(p, P2); break;
+ case 01: P1 |= val; WP(upi41_state, p, P1); break;
+ case 02: P2 |= val; WP(upi41_state, p, P2); break;
case 03: break; /* invalid port */
default: break;
}
@@ -854,10 +854,10 @@ OP_HANDLER( orld_p_a )
{
UINT8 p = r;
/* added proper expanded port setup */
- WP(2, (P2 & 0xf0) | 0x08 | p); /* OR mode */
- WP(I8X41_ps, 0); /* activate command strobe */
- WP(2, A & 0x0f); /* Expander to take care of OR function */
- WP(I8X41_ps, 1); /* release command strobe */
+ WP(upi41_state, 2, (P2 & 0xf0) | 0x08 | p); /* OR mode */
+ WP(upi41_state, I8X41_ps, 0); /* activate command strobe */
+ WP(upi41_state, 2, A & 0x0f); /* Expander to take care of OR function */
+ WP(upi41_state, I8X41_ps, 1); /* release command strobe */
}
/***********************************
@@ -873,7 +873,7 @@ OP_HANDLER( out_dbb_a )
P2_HS |= 0x10;
if( STATE & IBF ) P2_HS |= 0x20;
else P2_HS &= 0xdf;
- WP(0x02, (P2 & P2_HS) ); /* Assert the DBBO IRQ out on P24 */
+ WP(upi41_state, 0x02, (P2 & P2_HS) ); /* Assert the DBBO IRQ out on P24 */
}
}
@@ -888,8 +888,8 @@ OP_HANDLER( out_p_a )
switch (p)
{
case 00: break; /* invalid port */
- case 01: WP(p, A); P1 = A; break;
- case 02: WP(p, A); P2 = A; break;
+ case 01: WP(upi41_state, p, A); P1 = A; break;
+ case 02: WP(upi41_state, p, A); P2 = A; break;
case 03: break; /* invalid port */
default: break;
}
@@ -903,8 +903,8 @@ OP_HANDLER( ret )
{
UINT8 msb;
PSW = (PSW & ~SP) | ((PSW - 1) & SP);
- msb = IRAM_R(M_STACK + (PSW&SP) * 2 + 1);
- PC = IRAM_R(M_STACK + (PSW&SP) * 2 + 0);
+ msb = IRAM_R(upi41_state, M_STACK + (PSW&SP) * 2 + 1);
+ PC = IRAM_R(upi41_state, M_STACK + (PSW&SP) * 2 + 0);
PC |= (msb << 8) & 0x700;
}
@@ -916,8 +916,8 @@ OP_HANDLER( retr )
{
UINT8 msb;
PSW = (PSW & ~SP) | ((PSW - 1) & SP);
- msb = IRAM_R(M_STACK + (PSW&SP) * 2 + 1);
- PC = IRAM_R(M_STACK + (PSW&SP) * 2 + 0);
+ msb = IRAM_R(upi41_state, M_STACK + (PSW&SP) * 2 + 1);
+ PC = IRAM_R(upi41_state, M_STACK + (PSW&SP) * 2 + 0);
PC |= (msb << 8) & 0x700;
PSW = (PSW & 0x0f) | (msb & 0xf0);
CONTROL &= ~IRQ_IGNR;
@@ -1025,8 +1025,8 @@ OP_HANDLER( swap_a )
***********************************/
OP_HANDLER( xch_a_r )
{
- UINT8 tmp = GETR(r);
- SETR(r, A);
+ UINT8 tmp = GETR(upi41_state, r);
+ SETR(upi41_state, r, A);
A = tmp;
}
@@ -1036,9 +1036,9 @@ OP_HANDLER( xch_a_r )
***********************************/
OP_HANDLER( xch_a_rm )
{
- UINT16 addr = GETR(r);
- UINT8 tmp = IRAM_R(addr);
- IRAM_W( addr, A );
+ UINT16 addr = GETR(upi41_state, r);
+ UINT8 tmp = IRAM_R(upi41_state, addr);
+ IRAM_W(upi41_state, addr, A );
A = tmp;
}
@@ -1048,9 +1048,9 @@ OP_HANDLER( xch_a_rm )
***********************************/
OP_HANDLER( xchd_a_rm )
{
- UINT16 addr = GETR(r);
- UINT8 tmp = IRAM_R(addr);
- IRAM_W( addr, (tmp & 0xf0) | (A & 0x0f) );
+ UINT16 addr = GETR(upi41_state, r);
+ UINT8 tmp = IRAM_R(upi41_state, addr);
+ IRAM_W(upi41_state, addr, (tmp & 0xf0) | (A & 0x0f) );
A = (A & 0xf0) | (tmp & 0x0f);
}
@@ -1060,7 +1060,7 @@ OP_HANDLER( xchd_a_rm )
***********************************/
OP_HANDLER( xrl_r )
{
- A = A ^ GETR(r);
+ A = A ^ GETR(upi41_state, r);
}
/***********************************
@@ -1069,7 +1069,7 @@ OP_HANDLER( xrl_r )
***********************************/
OP_HANDLER( xrl_rm )
{
- A = A ^ IRAM_R(GETR(r));
+ A = A ^ IRAM_R(upi41_state, GETR(upi41_state, r));
}
/***********************************
@@ -1078,7 +1078,7 @@ OP_HANDLER( xrl_rm )
***********************************/
OP_HANDLER( xrl_i )
{
- UINT8 val = ROP_ARG(PC);
+ UINT8 val = ROP_ARG(upi41_state, PC);
PC++;
A = A ^ val;
}
diff --git a/src/emu/cpu/i960/i960.c b/src/emu/cpu/i960/i960.c
index e62913e7cdc..e4fe8b20501 100644
--- a/src/emu/cpu/i960/i960.c
+++ b/src/emu/cpu/i960/i960.c
@@ -1,3 +1,4 @@
+#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "i960.h"
#include "i960dis.h"
@@ -34,78 +35,79 @@ struct _i960_state_t {
cpu_irq_callback irq_cb;
const device_config *device;
+ const address_space *program;
int icount;
};
-static void do_call(i960_state_t *i960_state, UINT32 adr, int type, UINT32 stack);
+static void do_call(i960_state_t *i960, UINT32 adr, int type, UINT32 stack);
-INLINE UINT32 i960_read_dword_unaligned(UINT32 address)
+INLINE UINT32 i960_read_dword_unaligned(i960_state_t *i960, UINT32 address)
{
if (address & 3)
- return program_read_byte_32le(address) | program_read_byte_32le(address+1)<<8 | program_read_byte_32le(address+2)<<16 | program_read_byte_32le(address+3)<<24;
+ return memory_read_byte_32le(i960->program, address) | memory_read_byte_32le(i960->program, address+1)<<8 | memory_read_byte_32le(i960->program, address+2)<<16 | memory_read_byte_32le(i960->program, address+3)<<24;
else
- return program_read_dword_32le(address);
+ return memory_read_dword_32le(i960->program, address);
}
-INLINE UINT16 i960_read_word_unaligned(UINT32 address)
+INLINE UINT16 i960_read_word_unaligned(i960_state_t *i960, UINT32 address)
{
if (address & 1)
- return program_read_byte_32le(address) | program_read_byte_32le(address+1)<<8;
+ return memory_read_byte_32le(i960->program, address) | memory_read_byte_32le(i960->program, address+1)<<8;
else
- return program_read_word_32le(address);
+ return memory_read_word_32le(i960->program, address);
}
-INLINE void i960_write_dword_unaligned(UINT32 address, UINT32 data)
+INLINE void i960_write_dword_unaligned(i960_state_t *i960, UINT32 address, UINT32 data)
{
if (address & 3)
{
- program_write_byte_32le(address, data & 0xff);
- program_write_byte_32le(address+1, (data>>8)&0xff);
- program_write_byte_32le(address+2, (data>>16)&0xff);
- program_write_byte_32le(address+3, (data>>24)&0xff);
+ memory_write_byte_32le(i960->program, address, data & 0xff);
+ memory_write_byte_32le(i960->program, address+1, (data>>8)&0xff);
+ memory_write_byte_32le(i960->program, address+2, (data>>16)&0xff);
+ memory_write_byte_32le(i960->program, address+3, (data>>24)&0xff);
}
else
{
- program_write_dword_32le(address, data);
+ memory_write_dword_32le(i960->program, address, data);
}
}
-INLINE void i960_write_word_unaligned(UINT32 address, UINT16 data)
+INLINE void i960_write_word_unaligned(i960_state_t *i960, UINT32 address, UINT16 data)
{
if (address & 1)
{
- program_write_byte_32le(address, data & 0xff);
- program_write_byte_32le(address+1, (data>>8)&0xff);
+ memory_write_byte_32le(i960->program, address, data & 0xff);
+ memory_write_byte_32le(i960->program, address+1, (data>>8)&0xff);
}
else
{
- program_write_word_32le(address, data);
+ memory_write_word_32le(i960->program, address, data);
}
}
-INLINE void send_iac(i960_state_t *i960_state, UINT32 adr)
+INLINE void send_iac(i960_state_t *i960, UINT32 adr)
{
UINT32 iac[4];
- iac[0] = program_read_dword_32le(adr);
- iac[1] = program_read_dword_32le(adr+4);
- iac[2] = program_read_dword_32le(adr+8);
- iac[3] = program_read_dword_32le(adr+12);
+ iac[0] = memory_read_dword_32le(i960->program, adr);
+ iac[1] = memory_read_dword_32le(i960->program, adr+4);
+ iac[2] = memory_read_dword_32le(i960->program, adr+8);
+ iac[3] = memory_read_dword_32le(i960->program, adr+12);
switch(iac[0]>>24) {
case 0x93: // reinit
- i960_state->SAT = iac[1];
- i960_state->PRCB = iac[2];
- i960_state->IP = iac[3];
- change_pc(i960_state->IP);
+ i960->SAT = iac[1];
+ i960->PRCB = iac[2];
+ i960->IP = iac[3];
+ change_pc(i960->IP);
break;
default:
- fatalerror("I960: %x: IAC %08x %08x %08x %08x", i960_state->PIP, iac[0], iac[1], iac[2], iac[3]);
+ fatalerror("I960: %x: IAC %08x %08x %08x %08x", i960->PIP, iac[0], iac[1], iac[2], iac[3]);
break;
}
}
-INLINE UINT32 get_ea(i960_state_t *i960_state, UINT32 opcode)
+INLINE UINT32 get_ea(i960_state_t *i960, UINT32 opcode)
{
int abase = (opcode >> 14) & 0x1f;
if(!(opcode & 0x00001000)) { // MEMA
@@ -113,7 +115,7 @@ INLINE UINT32 get_ea(i960_state_t *i960_state, UINT32 opcode)
if(!(opcode & 0x2000))
return offset;
else
- return i960_state->r[abase]+offset;
+ return i960->r[abase]+offset;
} else { // MEMB
int index = opcode & 0x1f;
int scale = (opcode >> 7) & 0x7;
@@ -122,188 +124,188 @@ INLINE UINT32 get_ea(i960_state_t *i960_state, UINT32 opcode)
switch(mode) {
case 0x4:
- return i960_state->r[abase];
+ return i960->r[abase];
case 0x7:
- return i960_state->r[abase] + (i960_state->r[index] << scale);
+ return i960->r[abase] + (i960->r[index] << scale);
case 0xc:
- ret = program_decrypted_read_dword(i960_state->IP);
- i960_state->IP += 4;
+ ret = memory_decrypted_read_dword(i960->program, i960->IP);
+ i960->IP += 4;
return ret;
case 0xd:
- ret = program_decrypted_read_dword(i960_state->IP) + i960_state->r[abase];
- i960_state->IP += 4;
+ ret = memory_decrypted_read_dword(i960->program, i960->IP) + i960->r[abase];
+ i960->IP += 4;
return ret;
case 0xe:
- ret = program_decrypted_read_dword(i960_state->IP) + (i960_state->r[index] << scale);
- i960_state->IP += 4;
+ ret = memory_decrypted_read_dword(i960->program, i960->IP) + (i960->r[index] << scale);
+ i960->IP += 4;
return ret;
case 0xf:
- ret = program_decrypted_read_dword(i960_state->IP) + i960_state->r[abase] + (i960_state->r[index] << scale);
- i960_state->IP += 4;
+ ret = memory_decrypted_read_dword(i960->program, i960->IP) + i960->r[abase] + (i960->r[index] << scale);
+ i960->IP += 4;
return ret;
default:
- fatalerror("I960: %x: unhandled MEMB mode %x", i960_state->PIP, mode);
+ fatalerror("I960: %x: unhandled MEMB mode %x", i960->PIP, mode);
return 0;
}
}
}
-INLINE UINT32 get_1_ri(i960_state_t *i960_state, UINT32 opcode)
+INLINE UINT32 get_1_ri(i960_state_t *i960, UINT32 opcode)
{
if(!(opcode & 0x00000800))
- return i960_state->r[opcode & 0x1f];
+ return i960->r[opcode & 0x1f];
else
return opcode & 0x1f;
}
-INLINE UINT32 get_2_ri(i960_state_t *i960_state, UINT32 opcode)
+INLINE UINT32 get_2_ri(i960_state_t *i960, UINT32 opcode)
{
if(!(opcode & 0x00001000))
- return i960_state->r[(opcode>>14) & 0x1f];
+ return i960->r[(opcode>>14) & 0x1f];
else
return (opcode>>14) & 0x1f;
}
-INLINE UINT64 get_2_ri64(i960_state_t *i960_state, UINT32 opcode)
+INLINE UINT64 get_2_ri64(i960_state_t *i960, UINT32 opcode)
{
if(!(opcode & 0x00001000))
- return i960_state->r[(opcode>>14) & 0x1f] | ((UINT64)i960_state->r[((opcode>>14) & 0x1f)+1]<<32);
+ return i960->r[(opcode>>14) & 0x1f] | ((UINT64)i960->r[((opcode>>14) & 0x1f)+1]<<32);
else
return (opcode>>14) & 0x1f;
}
-INLINE void set_ri(i960_state_t *i960_state, UINT32 opcode, UINT32 val)
+INLINE void set_ri(i960_state_t *i960, UINT32 opcode, UINT32 val)
{
if(!(opcode & 0x00002000))
- i960_state->r[(opcode>>19) & 0x1f] = val;
+ i960->r[(opcode>>19) & 0x1f] = val;
else {
- fatalerror("I960: %x: set_ri on literal?", i960_state->PIP);
+ fatalerror("I960: %x: set_ri on literal?", i960->PIP);
}
}
-INLINE void set_ri2(i960_state_t *i960_state, UINT32 opcode, UINT32 val, UINT32 val2)
+INLINE void set_ri2(i960_state_t *i960, UINT32 opcode, UINT32 val, UINT32 val2)
{
if(!(opcode & 0x00002000))
{
- i960_state->r[(opcode>>19) & 0x1f] = val;
- i960_state->r[((opcode>>19) & 0x1f)+1] = val2;
+ i960->r[(opcode>>19) & 0x1f] = val;
+ i960->r[((opcode>>19) & 0x1f)+1] = val2;
}
else {
- fatalerror("I960: %x: set_ri2 on literal?", i960_state->PIP);
+ fatalerror("I960: %x: set_ri2 on literal?", i960->PIP);
}
}
-INLINE void set_ri64(i960_state_t *i960_state, UINT32 opcode, UINT64 val)
+INLINE void set_ri64(i960_state_t *i960, UINT32 opcode, UINT64 val)
{
if(!(opcode & 0x00002000)) {
- i960_state->r[(opcode>>19) & 0x1f] = val;
- i960_state->r[((opcode>>19) & 0x1f)+1] = val >> 32;
+ i960->r[(opcode>>19) & 0x1f] = val;
+ i960->r[((opcode>>19) & 0x1f)+1] = val >> 32;
} else
- fatalerror("I960: %x: set_ri64 on literal?", i960_state->PIP);
+ fatalerror("I960: %x: set_ri64 on literal?", i960->PIP);
}
-INLINE double get_1_rif(i960_state_t *i960_state, UINT32 opcode)
+INLINE double get_1_rif(i960_state_t *i960, UINT32 opcode)
{
if(!(opcode & 0x00000800))
- return u2f(i960_state->r[opcode & 0x1f]);
+ return u2f(i960->r[opcode & 0x1f]);
else {
int idx = opcode & 0x1f;
if(idx < 4)
- return i960_state->fp[idx];
+ return i960->fp[idx];
if(idx == 0x16)
return 1.0;
return 0.0;
}
}
-INLINE double get_2_rif(i960_state_t *i960_state, UINT32 opcode)
+INLINE double get_2_rif(i960_state_t *i960, UINT32 opcode)
{
if(!(opcode & 0x00001000))
- return u2f(i960_state->r[(opcode>>14) & 0x1f]);
+ return u2f(i960->r[(opcode>>14) & 0x1f]);
else {
int idx = (opcode>>14) & 0x1f;
if(idx < 4)
- return i960_state->fp[idx];
+ return i960->fp[idx];
if(idx == 0x16)
return 1.0;
return 0.0;
}
}
-INLINE void set_rif(i960_state_t *i960_state, UINT32 opcode, double val)
+INLINE void set_rif(i960_state_t *i960, UINT32 opcode, double val)
{
if(!(opcode & 0x00002000))
- i960_state->r[(opcode>>19) & 0x1f] = f2u(val);
+ i960->r[(opcode>>19) & 0x1f] = f2u(val);
else if(!(opcode & 0x00e00000))
- i960_state->fp[(opcode>>19) & 3] = val;
+ i960->fp[(opcode>>19) & 3] = val;
else
- fatalerror("I960: %x: set_rif on literal?", i960_state->PIP);
+ fatalerror("I960: %x: set_rif on literal?", i960->PIP);
}
-INLINE double get_1_rifl(i960_state_t *i960_state, UINT32 opcode)
+INLINE double get_1_rifl(i960_state_t *i960, UINT32 opcode)
{
if(!(opcode & 0x00000800)) {
- UINT64 v = i960_state->r[opcode & 0x1e];
- v |= ((UINT64)(i960_state->r[(opcode & 0x1e)+1]))<<32;
+ UINT64 v = i960->r[opcode & 0x1e];
+ v |= ((UINT64)(i960->r[(opcode & 0x1e)+1]))<<32;
return u2d(v);
} else {
int idx = opcode & 0x1f;
if(idx < 4)
- return i960_state->fp[idx];
+ return i960->fp[idx];
if(idx == 0x16)
return 1.0;
return 0.0;
}
}
-INLINE double get_2_rifl(i960_state_t *i960_state, UINT32 opcode)
+INLINE double get_2_rifl(i960_state_t *i960, UINT32 opcode)
{
if(!(opcode & 0x00001000)) {
- UINT64 v = i960_state->r[(opcode >> 14) & 0x1e];
- v |= ((UINT64)(i960_state->r[((opcode>>14) & 0x1e)+1]))<<32;
+ UINT64 v = i960->r[(opcode >> 14) & 0x1e];
+ v |= ((UINT64)(i960->r[((opcode>>14) & 0x1e)+1]))<<32;
return u2d(v);
} else {
int idx = (opcode>>14) & 0x1f;
if(idx < 4)
- return i960_state->fp[idx];
+ return i960->fp[idx];
if(idx == 0x16)
return 1.0;
return 0.0;
}
}
-INLINE void set_rifl(i960_state_t *i960_state, UINT32 opcode, double val)
+INLINE void set_rifl(i960_state_t *i960, UINT32 opcode, double val)
{
if(!(opcode & 0x00002000)) {
UINT64 v = d2u(val);
- i960_state->r[(opcode>>19) & 0x1e] = v;
- i960_state->r[((opcode>>19) & 0x1e)+1] = v>>32;
+ i960->r[(opcode>>19) & 0x1e] = v;
+ i960->r[((opcode>>19) & 0x1e)+1] = v>>32;
} else if(!(opcode & 0x00e00000))
- i960_state->fp[(opcode>>19) & 3] = val;
+ i960->fp[(opcode>>19) & 3] = val;
else
- fatalerror("I960: %x: set_rifl on literal?", i960_state->PIP);
+ fatalerror("I960: %x: set_rifl on literal?", i960->PIP);
}
-INLINE UINT32 get_1_ci(i960_state_t *i960_state, UINT32 opcode)
+INLINE UINT32 get_1_ci(i960_state_t *i960, UINT32 opcode)
{
if(!(opcode & 0x00002000))
- return i960_state->r[(opcode >> 19) & 0x1f];
+ return i960->r[(opcode >> 19) & 0x1f];
else
return (opcode >> 19) & 0x1f;
}
-INLINE UINT32 get_2_ci(i960_state_t *i960_state, UINT32 opcode)
+INLINE UINT32 get_2_ci(i960_state_t *i960, UINT32 opcode)
{
- return i960_state->r[(opcode >> 14) & 0x1f];
+ return i960->r[(opcode >> 14) & 0x1f];
}
-INLINE UINT32 get_disp(i960_state_t *i960_state, UINT32 opcode)
+INLINE UINT32 get_disp(i960_state_t *i960, UINT32 opcode)
{
UINT32 disp;
disp = opcode & 0xffffff;
@@ -312,7 +314,7 @@ INLINE UINT32 get_disp(i960_state_t *i960_state, UINT32 opcode)
return disp-4;
}
-INLINE UINT32 get_disp_s(i960_state_t *i960_state, UINT32 opcode)
+INLINE UINT32 get_disp_s(i960_state_t *i960, UINT32 opcode)
{
UINT32 disp;
disp = opcode & 0x1fff;
@@ -321,142 +323,142 @@ INLINE UINT32 get_disp_s(i960_state_t *i960_state, UINT32 opcode)
return disp-4;
}
-INLINE void cmp_s(i960_state_t *i960_state, INT32 v1, INT32 v2)
+INLINE void cmp_s(i960_state_t *i960, INT32 v1, INT32 v2)
{
- i960_state->AC &= ~7;
+ i960->AC &= ~7;
if(v1<v2)
- i960_state->AC |= 4;
+ i960->AC |= 4;
else if(v1 == v2)
- i960_state->AC |= 2;
+ i960->AC |= 2;
else
- i960_state->AC |= 1;
+ i960->AC |= 1;
}
-INLINE void cmp_u(i960_state_t *i960_state, UINT32 v1, UINT32 v2)
+INLINE void cmp_u(i960_state_t *i960, UINT32 v1, UINT32 v2)
{
- i960_state->AC &= ~7;
+ i960->AC &= ~7;
if(v1<v2)
- i960_state->AC |= 4;
+ i960->AC |= 4;
else if(v1 == v2)
- i960_state->AC |= 2;
+ i960->AC |= 2;
else
- i960_state->AC |= 1;
+ i960->AC |= 1;
}
-INLINE void concmp_s(i960_state_t *i960_state, INT32 v1, INT32 v2)
+INLINE void concmp_s(i960_state_t *i960, INT32 v1, INT32 v2)
{
- i960_state->AC &= ~7;
+ i960->AC &= ~7;
if(v1 <= v2)
- i960_state->AC |= 2;
+ i960->AC |= 2;
else
- i960_state->AC |= 1;
+ i960->AC |= 1;
}
-INLINE void concmp_u(i960_state_t *i960_state, UINT32 v1, UINT32 v2)
+INLINE void concmp_u(i960_state_t *i960, UINT32 v1, UINT32 v2)
{
- i960_state->AC &= ~7;
+ i960->AC &= ~7;
if(v1 <= v2)
- i960_state->AC |= 2;
+ i960->AC |= 2;
else
- i960_state->AC |= 1;
+ i960->AC |= 1;
}
-INLINE void cmp_d(i960_state_t *i960_state, double v1, double v2)
+INLINE void cmp_d(i960_state_t *i960, double v1, double v2)
{
- i960_state->AC &= ~7;
+ i960->AC &= ~7;
if(v1<v2)
- i960_state->AC |= 4;
+ i960->AC |= 4;
else if(v1 == v2)
- i960_state->AC |= 2;
+ i960->AC |= 2;
else if(v1 > v2)
- i960_state->AC |= 1;
+ i960->AC |= 1;
}
-INLINE void bxx(i960_state_t *i960_state, UINT32 opcode, int mask)
+INLINE void bxx(i960_state_t *i960, UINT32 opcode, int mask)
{
- if(i960_state->AC & mask) {
- i960_state->IP += get_disp(i960_state, opcode);
- change_pc(i960_state->IP);
+ if(i960->AC & mask) {
+ i960->IP += get_disp(i960, opcode);
+ change_pc(i960->IP);
}
}
-INLINE void bxx_s(i960_state_t *i960_state, UINT32 opcode, int mask)
+INLINE void bxx_s(i960_state_t *i960, UINT32 opcode, int mask)
{
- if(i960_state->AC & mask) {
- i960_state->IP += get_disp_s(i960_state, opcode);
- change_pc(i960_state->IP);
+ if(i960->AC & mask) {
+ i960->IP += get_disp_s(i960, opcode);
+ change_pc(i960->IP);
}
}
-INLINE void test(i960_state_t *i960_state, UINT32 opcode, int mask)
+INLINE void test(i960_state_t *i960, UINT32 opcode, int mask)
{
- if(i960_state->AC & mask)
- i960_state->r[(opcode>>19) & 0x1f] = 1;
+ if(i960->AC & mask)
+ i960->r[(opcode>>19) & 0x1f] = 1;
else
- i960_state->r[(opcode>>19) & 0x1f] = 0;
+ i960->r[(opcode>>19) & 0x1f] = 0;
}
-INLINE const char *i960_get_strflags(i960_state_t *i960_state)
+INLINE const char *i960_get_strflags(i960_state_t *i960)
{
static const char *const conditions[8] =
{
"no", "g", "e", "ge", "l", "ne", "le", "o"
};
- return (conditions[i960_state->AC & 7]);
+ return (conditions[i960->AC & 7]);
}
// interrupt dispatch
-static void take_interrupt(i960_state_t *i960_state, int vector, int lvl)
+static void take_interrupt(i960_state_t *i960, int vector, int lvl)
{
- int int_tab = program_read_dword_32le(i960_state->PRCB+20); // interrupt table
- int int_SP = program_read_dword_32le(i960_state->PRCB+24); // interrupt stack
+ int int_tab = memory_read_dword_32le(i960->program, i960->PRCB+20); // interrupt table
+ int int_SP = memory_read_dword_32le(i960->program, i960->PRCB+24); // interrupt stack
int SP;
UINT32 IRQV;
- IRQV = program_read_dword_32le(int_tab + 36 + (vector-8)*4);
+ IRQV = memory_read_dword_32le(i960->program, int_tab + 36 + (vector-8)*4);
// start the process
- if(!(i960_state->PC & 0x2000)) // if this is a nested interrupt, don't re-get int_SP
+ if(!(i960->PC & 0x2000)) // if this is a nested interrupt, don't re-get int_SP
{
SP = int_SP;
}
else
{
- SP = i960_state->r[I960_SP];
+ SP = i960->r[I960_SP];
}
SP = (SP + 63) & ~63;
SP += 128; // emulate ElSemi's core, this fixes the crash in sonic the fighters
- do_call(i960_state, IRQV, 7, SP);
+ do_call(i960, IRQV, 7, SP);
// save the processor state
- program_write_dword_32le(i960_state->r[I960_FP]-16, i960_state->PC);
- program_write_dword_32le(i960_state->r[I960_FP]-12, i960_state->AC);
+ memory_write_dword_32le(i960->program, i960->r[I960_FP]-16, i960->PC);
+ memory_write_dword_32le(i960->program, i960->r[I960_FP]-12, i960->AC);
// store the vector
- program_write_dword_32le(i960_state->r[I960_FP]-8, vector-8);
+ memory_write_dword_32le(i960->program, i960->r[I960_FP]-8, vector-8);
- i960_state->PC &= ~0x1f00; // clear priority, state, trace-fault pending, and trace enable
- i960_state->PC |= (lvl<<16); // set CPU level to current IRQ level
- i960_state->PC |= 0x2002; // set supervisor mode & interrupt flag
+ i960->PC &= ~0x1f00; // clear priority, state, trace-fault pending, and trace enable
+ i960->PC |= (lvl<<16); // set CPU level to current IRQ level
+ i960->PC |= 0x2002; // set supervisor mode & interrupt flag
}
-static void check_irqs(i960_state_t *i960_state)
+static void check_irqs(i960_state_t *i960)
{
- int int_tab = program_read_dword_32le(i960_state->PRCB+20); // interrupt table
- int cpu_pri = (i960_state->PC>>16)&0x1f;
+ int int_tab = memory_read_dword_32le(i960->program, i960->PRCB+20); // interrupt table
+ int cpu_pri = (i960->PC>>16)&0x1f;
int pending_pri;
int lvl, irq, take = -1;
int vword;
static const UINT32 lvlmask[4] = { 0x000000ff, 0x0000ff00, 0x00ff0000, 0xff000000 };
- pending_pri = program_read_dword_32le(int_tab); // read pending priorities
+ pending_pri = memory_read_dword_32le(i960->program, int_tab); // read pending priorities
- if ((i960_state->immediate_irq) && ((cpu_pri < i960_state->immediate_pri) || (i960_state->immediate_pri == 31)))
+ if ((i960->immediate_irq) && ((cpu_pri < i960->immediate_pri) || (i960->immediate_pri == 31)))
{
- take_interrupt(i960_state, i960_state->immediate_vector, i960_state->immediate_pri);
- i960_state->immediate_irq = 0;
+ take_interrupt(i960, i960->immediate_vector, i960->immediate_pri);
+ i960->immediate_irq = 0;
}
else
{
@@ -469,14 +471,14 @@ static void check_irqs(i960_state_t *i960_state)
wordl = (lvl % 4) * 8;
wordh = (wordl + 8) - 1;
- vword = program_read_dword_32le(int_tab + word);
+ vword = memory_read_dword_32le(i960->program, int_tab + word);
// take the first vector we find for this level
for (irq = wordh; irq >= wordl; irq--) {
if(vword & (1 << irq)) {
// clear pending bit
vword &= ~(1 << irq);
- program_write_dword_32le(int_tab + word, vword);
+ memory_write_dword_32le(i960->program, int_tab + word, vword);
take = irq;
break;
}
@@ -488,630 +490,630 @@ static void check_irqs(i960_state_t *i960_state)
// try to recover...
pending_pri &= ~(1 << lvl);
- program_write_dword_32le(int_tab, pending_pri);
+ memory_write_dword_32le(i960->program, int_tab, pending_pri);
return;
}
// if no vectors are waiting for this level, clear the level bit
if(!(vword & lvlmask[lvl % 4])) {
pending_pri &= ~(1 << lvl);
- program_write_dword_32le(int_tab, pending_pri);
+ memory_write_dword_32le(i960->program, int_tab, pending_pri);
}
take += ((lvl/4) * 32);
- take_interrupt(i960_state, take, lvl);
+ take_interrupt(i960, take, lvl);
return;
}
}
}
}
-static void do_call(i960_state_t *i960_state, UINT32 adr, int type, UINT32 stack)
+static void do_call(i960_state_t *i960, UINT32 adr, int type, UINT32 stack)
{
int i;
UINT32 FP;
// call and callx take 9 cycles base
- i960_state->icount -= 9;
+ i960->icount -= 9;
// set the new RIP
- i960_state->r[I960_RIP] = i960_state->IP;
-// mame_printf_debug("CALL (type %d): FP %x, %x => %x, stack %x, rcache_pos %d\n", type, i960_state->r[I960_FP], i960_state->r[I960_RIP], adr, stack, i960_state->rcache_pos);
+ i960->r[I960_RIP] = i960->IP;
+// mame_printf_debug("CALL (type %d): FP %x, %x => %x, stack %x, rcache_pos %d\n", type, i960->r[I960_FP], i960->r[I960_RIP], adr, stack, i960->rcache_pos);
// are we out of cache entries?
- if (i960_state->rcache_pos >= RCACHE_SIZE) {
+ if (i960->rcache_pos >= RCACHE_SIZE) {
// flush the current register set to the current frame
- FP = i960_state->r[I960_FP] & ~0x3f;
+ FP = i960->r[I960_FP] & ~0x3f;
for (i = 0; i < 16; i++) {
- program_write_dword_32le(FP + (i*4), i960_state->r[i]);
+ memory_write_dword_32le(i960->program, FP + (i*4), i960->r[i]);
}
}
else // a cache entry is available, use it
{
- memcpy(&i960_state->rcache[i960_state->rcache_pos][0], i960_state->r, 0x10 * sizeof(UINT32));
- i960_state->rcache_frame_addr[i960_state->rcache_pos] = i960_state->r[I960_FP] & ~0x3f;
+ memcpy(&i960->rcache[i960->rcache_pos][0], i960->r, 0x10 * sizeof(UINT32));
+ i960->rcache_frame_addr[i960->rcache_pos] = i960->r[I960_FP] & ~0x3f;
}
- i960_state->rcache_pos++;
+ i960->rcache_pos++;
- i960_state->IP = adr;
- i960_state->r[I960_PFP] = i960_state->r[I960_FP] & ~7;
- i960_state->r[I960_PFP] |= type;
+ i960->IP = adr;
+ i960->r[I960_PFP] = i960->r[I960_FP] & ~7;
+ i960->r[I960_PFP] |= type;
if(type == 7) { // interrupts need special handling
// set the stack to the passed-in value to properly handle nested interrupts
// (can't set it externally or the original program's SP will be lost)
- i960_state->r[I960_SP] = stack;
+ i960->r[I960_SP] = stack;
}
- i960_state->r[I960_FP] = (i960_state->r[I960_SP] + 63) & ~63;
- i960_state->r[I960_SP] = i960_state->r[I960_FP] + 64;
+ i960->r[I960_FP] = (i960->r[I960_SP] + 63) & ~63;
+ i960->r[I960_SP] = i960->r[I960_FP] + 64;
- change_pc(i960_state->IP);
+ change_pc(i960->IP);
}
-static void do_ret_0(i960_state_t *i960_state)
+static void do_ret_0(i960_state_t *i960)
{
-// int type = i960_state->r[I960_PFP] & 7;
+// int type = i960->r[I960_PFP] & 7;
- i960_state->r[I960_FP] = i960_state->r[I960_PFP] & ~0x3f;
+ i960->r[I960_FP] = i960->r[I960_PFP] & ~0x3f;
- i960_state->rcache_pos--;
+ i960->rcache_pos--;
// normal situation: if we're still above rcache size, we're not in cache.
// abnormal situation (after the app does a FLUSHREG): rcache_pos will be 0
// coming in, but we must still treat it as a not-in-cache situation.
- if ((i960_state->rcache_pos >= RCACHE_SIZE) || (i960_state->rcache_pos < 0))
+ if ((i960->rcache_pos >= RCACHE_SIZE) || (i960->rcache_pos < 0))
{
int i;
for(i=0; i<0x10; i++)
- i960_state->r[i] = program_read_dword_32le(i960_state->r[I960_FP]+4*i);
+ i960->r[i] = memory_read_dword_32le(i960->program, i960->r[I960_FP]+4*i);
- if (i960_state->rcache_pos < 0)
+ if (i960->rcache_pos < 0)
{
- i960_state->rcache_pos = 0;
+ i960->rcache_pos = 0;
}
}
else
{
- memcpy(i960_state->r, i960_state->rcache[i960_state->rcache_pos], 0x10*sizeof(UINT32));
+ memcpy(i960->r, i960->rcache[i960->rcache_pos], 0x10*sizeof(UINT32));
}
-// mame_printf_debug("RET (type %d): FP %x, %x => %x, rcache_pos %d\n", type, i960_state->r[I960_FP], i960_state->IP, i960_state->r[I960_RIP], i960_state->rcache_pos);
- i960_state->IP = i960_state->r[I960_RIP];
- change_pc(i960_state->IP);
+// mame_printf_debug("RET (type %d): FP %x, %x => %x, rcache_pos %d\n", type, i960->r[I960_FP], i960->IP, i960->r[I960_RIP], i960->rcache_pos);
+ i960->IP = i960->r[I960_RIP];
+ change_pc(i960->IP);
}
-static void do_ret(i960_state_t *i960_state)
+static void do_ret(i960_state_t *i960)
{
UINT32 x, y;
- i960_state->icount -= 7;
- switch(i960_state->r[I960_PFP] & 7) {
+ i960->icount -= 7;
+ switch(i960->r[I960_PFP] & 7) {
case 0:
- do_ret_0(i960_state);
+ do_ret_0(i960);
break;
case 7:
- x = program_read_dword(i960_state->r[I960_FP]-16);
- y = program_read_dword(i960_state->r[I960_FP]-12);
- do_ret_0(i960_state);
- i960_state->AC = y;
+ x = memory_read_dword(i960->program, i960->r[I960_FP]-16);
+ y = memory_read_dword(i960->program, i960->r[I960_FP]-12);
+ do_ret_0(i960);
+ i960->AC = y;
// #### test supervisor
- i960_state->PC = x;
+ i960->PC = x;
// check for another IRQ now that we're back
- check_irqs(i960_state);
+ check_irqs(i960);
break;
default:
- fatalerror("I960: %x: Unsupported return mode %d", i960_state->PIP, i960_state->r[I960_PFP] & 7);
+ fatalerror("I960: %x: Unsupported return mode %d", i960->PIP, i960->r[I960_PFP] & 7);
}
}
-INLINE void execute_op(i960_state_t *i960_state, UINT32 opcode)
+INLINE void execute_op(i960_state_t *i960, UINT32 opcode)
{
UINT32 t1, t2;
double t1f, t2f;
switch(opcode >> 24) {
case 0x08: // b
- i960_state->icount--;
- i960_state->IP += get_disp(i960_state, opcode);
- change_pc(i960_state->IP);
+ i960->icount--;
+ i960->IP += get_disp(i960, opcode);
+ change_pc(i960->IP);
break;
case 0x09: // call
- do_call(i960_state, i960_state->IP+get_disp(i960_state, opcode), 0, i960_state->r[I960_SP]);
+ do_call(i960, i960->IP+get_disp(i960, opcode), 0, i960->r[I960_SP]);
break;
case 0x0a: // ret
- do_ret(i960_state);
+ do_ret(i960);
break;
case 0x0b: // bal
- i960_state->icount -= 5;
- i960_state->r[0x1e] = i960_state->IP;
- i960_state->IP += get_disp(i960_state, opcode);
- change_pc(i960_state->IP);
+ i960->icount -= 5;
+ i960->r[0x1e] = i960->IP;
+ i960->IP += get_disp(i960, opcode);
+ change_pc(i960->IP);
break;
case 0x10: // bno
- i960_state->icount--;
- if(!(i960_state->AC & 7)) {
- i960_state->IP += get_disp(i960_state, opcode);
- change_pc(i960_state->IP);
+ i960->icount--;
+ if(!(i960->AC & 7)) {
+ i960->IP += get_disp(i960, opcode);
+ change_pc(i960->IP);
}
break;
case 0x11: // bg
- i960_state->icount--;
- bxx(i960_state, opcode, 1);
+ i960->icount--;
+ bxx(i960, opcode, 1);
break;
case 0x12: // be
- i960_state->icount--;
- bxx(i960_state, opcode, 2);
+ i960->icount--;
+ bxx(i960, opcode, 2);
break;
case 0x13: // bge
- i960_state->icount--;
- bxx(i960_state, opcode, 3);
+ i960->icount--;
+ bxx(i960, opcode, 3);
break;
case 0x14: // bl
- i960_state->icount--;
- bxx(i960_state, opcode, 4);
+ i960->icount--;
+ bxx(i960, opcode, 4);
break;
case 0x15: // bne
- i960_state->icount--;
- bxx(i960_state, opcode, 5);
+ i960->icount--;
+ bxx(i960, opcode, 5);
break;
case 0x16: // ble
- i960_state->icount--;
- bxx(i960_state, opcode, 6);
+ i960->icount--;
+ bxx(i960, opcode, 6);
break;
case 0x17: // bo
- i960_state->icount--;
- bxx(i960_state, opcode, 7);
+ i960->icount--;
+ bxx(i960, opcode, 7);
break;
case 0x20: // testno
- i960_state->icount--;
- if(!(i960_state->AC & 7))
- i960_state->r[(opcode>>19) & 0x1f] = 1;
+ i960->icount--;
+ if(!(i960->AC & 7))
+ i960->r[(opcode>>19) & 0x1f] = 1;
else
- i960_state->r[(opcode>>19) & 0x1f] = 0;
+ i960->r[(opcode>>19) & 0x1f] = 0;
break;
case 0x21: // testg
- i960_state->icount--;
- test(i960_state, opcode, 1);
+ i960->icount--;
+ test(i960, opcode, 1);
break;
case 0x22: // teste
- i960_state->icount--;
- test(i960_state, opcode, 2);
+ i960->icount--;
+ test(i960, opcode, 2);
break;
case 0x23: // testge
- i960_state->icount--;
- test(i960_state, opcode, 3);
+ i960->icount--;
+ test(i960, opcode, 3);
break;
case 0x24: // testl
- i960_state->icount--;
- test(i960_state, opcode, 4);
+ i960->icount--;
+ test(i960, opcode, 4);
break;
case 0x25: // testne
- i960_state->icount--;
- test(i960_state, opcode, 5);
+ i960->icount--;
+ test(i960, opcode, 5);
break;
case 0x26: // testle
- i960_state->icount--;
- test(i960_state, opcode, 6);
+ i960->icount--;
+ test(i960, opcode, 6);
break;
case 0x27: // testo
- i960_state->icount--;
- test(i960_state, opcode, 7);
+ i960->icount--;
+ test(i960, opcode, 7);
break;
case 0x30: // bbc
- i960_state->icount -= 4;
- t1 = get_1_ci(i960_state, opcode) & 0x1f;
- t2 = get_2_ci(i960_state, opcode);
+ i960->icount -= 4;
+ t1 = get_1_ci(i960, opcode) & 0x1f;
+ t2 = get_2_ci(i960, opcode);
if(!(t2 & (1<<t1))) {
- i960_state->AC = (i960_state->AC & ~7) | 2;
- i960_state->IP += get_disp_s(i960_state, opcode);
- change_pc(i960_state->IP);
+ i960->AC = (i960->AC & ~7) | 2;
+ i960->IP += get_disp_s(i960, opcode);
+ change_pc(i960->IP);
} else
- i960_state->AC &= ~7;
+ i960->AC &= ~7;
break;
case 0x31: // cmp0bg
- i960_state->icount -= 4;
- t1 = get_1_ci(i960_state, opcode);
- t2 = get_2_ci(i960_state, opcode);
- cmp_u(i960_state, t1, t2);
- bxx_s(i960_state, opcode, 1);
+ i960->icount -= 4;
+ t1 = get_1_ci(i960, opcode);
+ t2 = get_2_ci(i960, opcode);
+ cmp_u(i960, t1, t2);
+ bxx_s(i960, opcode, 1);
break;
case 0x32: // cmpobe
- i960_state->icount -= 4;
- t1 = get_1_ci(i960_state, opcode);
- t2 = get_2_ci(i960_state, opcode);
- cmp_u(i960_state, t1, t2);
- bxx_s(i960_state, opcode, 2);
+ i960->icount -= 4;
+ t1 = get_1_ci(i960, opcode);
+ t2 = get_2_ci(i960, opcode);
+ cmp_u(i960, t1, t2);
+ bxx_s(i960, opcode, 2);
break;
case 0x33: // cmpobge
- i960_state->icount -= 4;
- t1 = get_1_ci(i960_state, opcode);
- t2 = get_2_ci(i960_state, opcode);
- cmp_u(i960_state, t1, t2);
- bxx_s(i960_state, opcode, 3);
+ i960->icount -= 4;
+ t1 = get_1_ci(i960, opcode);
+ t2 = get_2_ci(i960, opcode);
+ cmp_u(i960, t1, t2);
+ bxx_s(i960, opcode, 3);
break;
case 0x34: // cmpobl
- i960_state->icount -= 4;
- t1 = get_1_ci(i960_state, opcode);
- t2 = get_2_ci(i960_state, opcode);
- cmp_u(i960_state, t1, t2);
- bxx_s(i960_state, opcode, 4);
+ i960->icount -= 4;
+ t1 = get_1_ci(i960, opcode);
+ t2 = get_2_ci(i960, opcode);
+ cmp_u(i960, t1, t2);
+ bxx_s(i960, opcode, 4);
break;
case 0x35: // cmpobne
- i960_state->icount -= 4;
- t1 = get_1_ci(i960_state, opcode);
- t2 = get_2_ci(i960_state, opcode);
- cmp_u(i960_state, t1, t2);
- bxx_s(i960_state, opcode, 5);
+ i960->icount -= 4;
+ t1 = get_1_ci(i960, opcode);
+ t2 = get_2_ci(i960, opcode);
+ cmp_u(i960, t1, t2);
+ bxx_s(i960, opcode, 5);
break;
case 0x36: // cmpoble
- i960_state->icount -= 4;
- t1 = get_1_ci(i960_state, opcode);
- t2 = get_2_ci(i960_state, opcode);
- cmp_u(i960_state, t1, t2);
- bxx_s(i960_state, opcode, 6);
+ i960->icount -= 4;
+ t1 = get_1_ci(i960, opcode);
+ t2 = get_2_ci(i960, opcode);
+ cmp_u(i960, t1, t2);
+ bxx_s(i960, opcode, 6);
break;
case 0x37: // bbs
- i960_state->icount -= 4;
- t1 = get_1_ci(i960_state, opcode) & 0x1f;
- t2 = get_2_ci(i960_state, opcode);
+ i960->icount -= 4;
+ t1 = get_1_ci(i960, opcode) & 0x1f;
+ t2 = get_2_ci(i960, opcode);
if(t2 & (1<<t1)) {
- i960_state->AC = (i960_state->AC & ~7) | 2;
- i960_state->IP += get_disp_s(i960_state, opcode);
- change_pc(i960_state->IP);
+ i960->AC = (i960->AC & ~7) | 2;
+ i960->IP += get_disp_s(i960, opcode);
+ change_pc(i960->IP);
} else
- i960_state->AC &= ~7;
+ i960->AC &= ~7;
break;
case 0x39: // cmpibg
- i960_state->icount -= 4;
- t1 = get_1_ci(i960_state, opcode);
- t2 = get_2_ci(i960_state, opcode);
- cmp_s(i960_state, t1, t2);
- bxx_s(i960_state, opcode, 1);
+ i960->icount -= 4;
+ t1 = get_1_ci(i960, opcode);
+ t2 = get_2_ci(i960, opcode);
+ cmp_s(i960, t1, t2);
+ bxx_s(i960, opcode, 1);
break;
case 0x3a: // cmpibe
- i960_state->icount -= 4;
- t1 = get_1_ci(i960_state, opcode);
- t2 = get_2_ci(i960_state, opcode);
- cmp_s(i960_state, t1, t2);
- bxx_s(i960_state, opcode, 2);
+ i960->icount -= 4;
+ t1 = get_1_ci(i960, opcode);
+ t2 = get_2_ci(i960, opcode);
+ cmp_s(i960, t1, t2);
+ bxx_s(i960, opcode, 2);
break;
case 0x3b: // cmpibge
- i960_state->icount -= 4;
- t1 = get_1_ci(i960_state, opcode);
- t2 = get_2_ci(i960_state, opcode);
- cmp_s(i960_state, t1, t2);
- bxx_s(i960_state, opcode, 3);
+ i960->icount -= 4;
+ t1 = get_1_ci(i960, opcode);
+ t2 = get_2_ci(i960, opcode);
+ cmp_s(i960, t1, t2);
+ bxx_s(i960, opcode, 3);
break;
case 0x3c: // cmpibl
- i960_state->icount -= 4;
- t1 = get_1_ci(i960_state, opcode);
- t2 = get_2_ci(i960_state, opcode);
- cmp_s(i960_state, t1, t2);
- bxx_s(i960_state, opcode, 4);
+ i960->icount -= 4;
+ t1 = get_1_ci(i960, opcode);
+ t2 = get_2_ci(i960, opcode);
+ cmp_s(i960, t1, t2);
+ bxx_s(i960, opcode, 4);
break;
case 0x3d: // cmpibne
- i960_state->icount -= 4;
- t1 = get_1_ci(i960_state, opcode);
- t2 = get_2_ci(i960_state, opcode);
- cmp_s(i960_state, t1, t2);
- bxx_s(i960_state, opcode, 5);
+ i960->icount -= 4;
+ t1 = get_1_ci(i960, opcode);
+ t2 = get_2_ci(i960, opcode);
+ cmp_s(i960, t1, t2);
+ bxx_s(i960, opcode, 5);
break;
case 0x3e: // cmpible
- i960_state->icount -= 4;
- t1 = get_1_ci(i960_state, opcode);
- t2 = get_2_ci(i960_state, opcode);
- cmp_s(i960_state, t1, t2);
- bxx_s(i960_state, opcode, 6);
+ i960->icount -= 4;
+ t1 = get_1_ci(i960, opcode);
+ t2 = get_2_ci(i960, opcode);
+ cmp_s(i960, t1, t2);
+ bxx_s(i960, opcode, 6);
break;
case 0x58:
switch((opcode >> 7) & 0xf) {
case 0x0: // notbit
- i960_state->icount -= 2;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, t2 ^ (1<<(t1 & 31)));
+ i960->icount -= 2;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, t2 ^ (1<<(t1 & 31)));
break;
case 0x1: // and
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, t2 & t1);
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, t2 & t1);
break;
case 0x2: // andnot
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, t2 & ~t1);
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, t2 & ~t1);
break;
case 0x3: // setbit
- i960_state->icount -= 2;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, t2 | (1<<(t1 & 31)));
+ i960->icount -= 2;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, t2 | (1<<(t1 & 31)));
break;
case 0x4: // notand
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, (~t2) & t1);
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, (~t2) & t1);
break;
case 0x6: // xor
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, t2 ^ t1);
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, t2 ^ t1);
break;
case 0x7: // or
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, t2 | t1);
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, t2 | t1);
break;
case 0x8: // nor
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, ((~t2) ^ (~t1)));
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, ((~t2) ^ (~t1)));
break;
case 0x9: // xnor
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, ~(t2 ^ t1));
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, ~(t2 ^ t1));
break;
case 0xa: // not
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- set_ri(i960_state, opcode, ~t1);
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ set_ri(i960, opcode, ~t1);
break;
case 0xb: // ornot
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, t2 | ~t1);
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, t2 | ~t1);
break;
case 0xc: // clrbit
- i960_state->icount -= 2;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, t2 & ~(1<<(t1 & 31)));
+ i960->icount -= 2;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, t2 & ~(1<<(t1 & 31)));
break;
case 0xe: // nand
- i960_state->icount -= 2;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, ~t2 | ~t1);
+ i960->icount -= 2;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, ~t2 | ~t1);
break;
case 0xf: // alterbit
- i960_state->icount -= 2;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- if(i960_state->AC & 2)
- set_ri(i960_state, opcode, t2 | (1<<(t1 & 31)));
+ i960->icount -= 2;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ if(i960->AC & 2)
+ set_ri(i960, opcode, t2 | (1<<(t1 & 31)));
else
- set_ri(i960_state, opcode, t2 & ~(1<<(t1 & 31)));
+ set_ri(i960, opcode, t2 & ~(1<<(t1 & 31)));
break;
default:
- fatalerror("I960: %x: Unhandled 58.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 58.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x59:
switch((opcode >> 7) & 0xf) {
case 0x0: // addo
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, t2+t1);
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, t2+t1);
break;
case 0x1: // addi
// #### overflow
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, t2+t1);
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, t2+t1);
break;
case 0x2: // subo
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, t2-t1);
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, t2-t1);
break;
case 0x3: // subi
// #### overflow
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, t2-t1);
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, t2-t1);
break;
case 0x8: // shro
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, t2>>t1);
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, t2>>t1);
break;
case 0xa: // shrdi
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
if(((INT32)t2) < 0) {
if(t2 & ((1<<t1)-1))
- set_ri(i960_state, opcode, (((INT32)t2)>>t1)+1);
+ set_ri(i960, opcode, (((INT32)t2)>>t1)+1);
else
- set_ri(i960_state, opcode, ((INT32)t2)>>t1);
+ set_ri(i960, opcode, ((INT32)t2)>>t1);
} else
- set_ri(i960_state, opcode, t2>>t1);
+ set_ri(i960, opcode, t2>>t1);
break;
case 0xb: // shri
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, ((INT32)t2)>>t1);
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, ((INT32)t2)>>t1);
break;
case 0xc: // shlo
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, t2<<t1);
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, t2<<t1);
break;
case 0xd: // rotate
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode) & 0x1f;
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, (t2<<t1)|(t2>>(32-t1)));
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode) & 0x1f;
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, (t2<<t1)|(t2>>(32-t1)));
break;
case 0xe: // shli
// missing overflow
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, t2<<t1);
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, t2<<t1);
break;
default:
- fatalerror("I960: %x: Unhandled 59.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 59.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x5a:
switch((opcode >> 7) & 0xf) {
case 0x0: // cmpo
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- cmp_u(i960_state, t1, t2);
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ cmp_u(i960, t1, t2);
break;
case 0x1: // cmpi
- i960_state->icount--;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- cmp_s(i960_state, t1, t2);
+ i960->icount--;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ cmp_s(i960, t1, t2);
break;
case 0x2: // concmpo
- i960_state->icount--;
- if(!(i960_state->AC & 0x4)) {
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- concmp_u(i960_state, t1, t2);
+ i960->icount--;
+ if(!(i960->AC & 0x4)) {
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ concmp_u(i960, t1, t2);
}
break;
case 0x3: // concmpi
- i960_state->icount--;
- if(!(i960_state->AC & 0x4)) {
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- concmp_s(i960_state, t1, t2);
+ i960->icount--;
+ if(!(i960->AC & 0x4)) {
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ concmp_s(i960, t1, t2);
}
break;
case 0x4: // cmpinco
- i960_state->icount -= 2;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- cmp_u(i960_state, t1, t2);
- set_ri(i960_state, opcode, t2+1);
+ i960->icount -= 2;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ cmp_u(i960, t1, t2);
+ set_ri(i960, opcode, t2+1);
break;
case 0x5: // cmpinci
- i960_state->icount -= 2;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- cmp_s(i960_state, t1, t2);
- set_ri(i960_state, opcode, t2+1);
+ i960->icount -= 2;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ cmp_s(i960, t1, t2);
+ set_ri(i960, opcode, t2+1);
break;
case 0x6: // cmpdeco
- i960_state->icount -= 2;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- cmp_u(i960_state, t1, t2);
- set_ri(i960_state, opcode, t2-1);
+ i960->icount -= 2;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ cmp_u(i960, t1, t2);
+ set_ri(i960, opcode, t2-1);
break;
case 0x7: // cmpdeci
- i960_state->icount -= 2;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- cmp_s(i960_state, t1, t2);
- set_ri(i960_state, opcode, t2-1);
+ i960->icount -= 2;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ cmp_s(i960, t1, t2);
+ set_ri(i960, opcode, t2-1);
break;
case 0xe: // chkbit
- i960_state->icount -= 2;
- t1 = get_1_ri(i960_state, opcode) & 0x1f;
- t2 = get_2_ri(i960_state, opcode);
+ i960->icount -= 2;
+ t1 = get_1_ri(i960, opcode) & 0x1f;
+ t2 = get_2_ri(i960, opcode);
if(t2 & (1<<t1))
- i960_state->AC = (i960_state->AC & ~7) | 2;
+ i960->AC = (i960->AC & ~7) | 2;
else
- i960_state->AC &= ~7;
+ i960->AC &= ~7;
break;
default:
- fatalerror("I960: %x: Unhandled 5a.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 5a.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
@@ -1121,17 +1123,17 @@ INLINE void execute_op(i960_state_t *i960_state, UINT32 opcode)
{
UINT64 res;
- i960_state->icount -= 2;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- res = t2+(t1+((i960_state->AC>>1)&1));
- set_ri(i960_state, opcode, res&0xffffffff);
+ i960->icount -= 2;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ res = t2+(t1+((i960->AC>>1)&1));
+ set_ri(i960, opcode, res&0xffffffff);
- i960_state->AC &= ~0x3; // clear C and V
+ i960->AC &= ~0x3; // clear C and V
// set carry
- i960_state->AC |= ((res) & (((UINT64)1) << 32)) ? 0x2 : 0;
+ i960->AC |= ((res) & (((UINT64)1) << 32)) ? 0x2 : 0;
// set overflow
- i960_state->AC |= (((res) ^ (t1)) & ((res) ^ (t2)) & 0x80000000) ? 1: 0;
+ i960->AC |= (((res) ^ (t1)) & ((res) ^ (t2)) & 0x80000000) ? 1: 0;
}
break;
@@ -1139,120 +1141,120 @@ INLINE void execute_op(i960_state_t *i960_state, UINT32 opcode)
{
UINT64 res;
- i960_state->icount -= 2;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- res = t2-(t1+((i960_state->AC>>1)&1));
- set_ri(i960_state, opcode, res&0xffffffff);
+ i960->icount -= 2;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ res = t2-(t1+((i960->AC>>1)&1));
+ set_ri(i960, opcode, res&0xffffffff);
- i960_state->AC &= ~0x3; // clear C and V
+ i960->AC &= ~0x3; // clear C and V
// set carry
- i960_state->AC |= ((res) & (((UINT64)1) << 32)) ? 0x2 : 0;
+ i960->AC |= ((res) & (((UINT64)1) << 32)) ? 0x2 : 0;
// set overflow
- i960_state->AC |= (((t2) ^ (t1)) & ((t2) ^ (res)) & 0x80000000) ? 1 : 0;
+ i960->AC |= (((t2) ^ (t1)) & ((t2) ^ (res)) & 0x80000000) ? 1 : 0;
}
break;
default:
- fatalerror("I960: %x: Unhandled 5b.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 5b.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x5c:
switch((opcode >> 7) & 0xf) {
case 0xc: // mov
- i960_state->icount -= 2;
- t1 = get_1_ri(i960_state, opcode);
- set_ri(i960_state, opcode, t1);
+ i960->icount -= 2;
+ t1 = get_1_ri(i960, opcode);
+ set_ri(i960, opcode, t1);
break;
default:
- fatalerror("I960: %x: Unhandled 5c.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 5c.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x5d:
switch((opcode >> 7) & 0xf) {
case 0xc: // movl
- i960_state->icount -= 2;
+ i960->icount -= 2;
t2 = (opcode>>19) & 0x1e;
if(opcode & 0x00000800) { // litteral
t1 = opcode & 0x1f;
- i960_state->r[t2] = i960_state->r[t2+1] = t1;
+ i960->r[t2] = i960->r[t2+1] = t1;
} else
- memcpy(i960_state->r+t2, i960_state->r+(opcode & 0x1f), 2*sizeof(UINT32));
+ memcpy(i960->r+t2, i960->r+(opcode & 0x1f), 2*sizeof(UINT32));
break;
default:
- fatalerror("I960: %x: Unhandled 5d.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 5d.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x5e:
switch((opcode >> 7) & 0xf) {
case 0xc: // movt
- i960_state->icount -= 3;
+ i960->icount -= 3;
t2 = (opcode>>19) & 0x1c;
if(opcode & 0x00000800) { // litteral
t1 = opcode & 0x1f;
- i960_state->r[t2] = i960_state->r[t2+1] = i960_state->r[t2+2]= t1;
+ i960->r[t2] = i960->r[t2+1] = i960->r[t2+2]= t1;
} else
- memcpy(i960_state->r+t2, i960_state->r+(opcode & 0x1f), 3*sizeof(UINT32));
+ memcpy(i960->r+t2, i960->r+(opcode & 0x1f), 3*sizeof(UINT32));
break;
default:
- fatalerror("I960: %x: Unhandled 5e.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 5e.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x5f:
switch((opcode >> 7) & 0xf) {
case 0xc: // movq
- i960_state->icount -= 4;
+ i960->icount -= 4;
t2 = (opcode>>19) & 0x1c;
if(opcode & 0x00000800) { // litteral
t1 = opcode & 0x1f;
- i960_state->r[t2] = i960_state->r[t2+1] = i960_state->r[t2+2] = i960_state->r[t2+3] = t1;
+ i960->r[t2] = i960->r[t2+1] = i960->r[t2+2] = i960->r[t2+3] = t1;
} else
- memcpy(i960_state->r+t2, i960_state->r+(opcode & 0x1f), 4*sizeof(UINT32));
+ memcpy(i960->r+t2, i960->r+(opcode & 0x1f), 4*sizeof(UINT32));
break;
default:
- fatalerror("I960: %x: Unhandled 5f.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 5f.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x60:
switch((opcode >> 7) & 0xf) {
case 0x0: // synmov
- i960_state->icount -= 6;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
+ i960->icount -= 6;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
// interrupt control register
if(t1 == 0xff000004)
- i960_state->ICR = program_read_dword_32le(t2);
+ i960->ICR = memory_read_dword_32le(i960->program, t2);
else
- program_write_dword_32le(t1, program_read_dword_32le(t2));
- i960_state->AC = (i960_state->AC & ~7) | 2;
+ memory_write_dword_32le(i960->program, t1, memory_read_dword_32le(i960->program, t2));
+ i960->AC = (i960->AC & ~7) | 2;
break;
case 0x2: // synmovq
- i960_state->icount -= 12;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
+ i960->icount -= 12;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
if(t1 == 0xff000010)
- send_iac(i960_state, t2);
+ send_iac(i960, t2);
else {
- program_write_dword_32le(t1, program_read_dword_32le(t2));
- program_write_dword_32le(t1+4, program_read_dword_32le(t2+4));
- program_write_dword_32le(t1+8, program_read_dword_32le(t2+8));
- program_write_dword_32le(t1+12, program_read_dword_32le(t2+12));
+ memory_write_dword_32le(i960->program, t1, memory_read_dword_32le(i960->program, t2));
+ memory_write_dword_32le(i960->program, t1+4, memory_read_dword_32le(i960->program, t2+4));
+ memory_write_dword_32le(i960->program, t1+8, memory_read_dword_32le(i960->program, t2+8));
+ memory_write_dword_32le(i960->program, t1+12, memory_read_dword_32le(i960->program, t2+12));
}
- i960_state->AC = (i960_state->AC & ~7) | 2;
+ i960->AC = (i960->AC & ~7) | 2;
break;
default:
- fatalerror("I960: %x: Unhandled 60.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 60.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
@@ -1263,22 +1265,22 @@ INLINE void execute_op(i960_state_t *i960_state, UINT32 opcode)
UINT32 res = 0xffffffff;
int i;
- i960_state->icount -= 10;
+ i960->icount -= 10;
- t1 = get_1_ri(i960_state, opcode);
- i960_state->AC &= ~7;
+ t1 = get_1_ri(i960, opcode);
+ i960->AC &= ~7;
for (i = 31; i >= 0; i--)
{
if (!(t1 & (1<<i)))
{
- i960_state->AC |= 2;
+ i960->AC |= 2;
res = i;
break;
}
}
- set_ri(i960_state, opcode, res);
+ set_ri(i960, opcode, res);
}
break;
@@ -1287,319 +1289,319 @@ INLINE void execute_op(i960_state_t *i960_state, UINT32 opcode)
UINT32 res = 0xffffffff;
int i;
- i960_state->icount -= 10;
+ i960->icount -= 10;
- t1 = get_1_ri(i960_state, opcode);
- i960_state->AC &= ~7;
+ t1 = get_1_ri(i960, opcode);
+ i960->AC &= ~7;
for (i = 31; i >= 0; i--)
{
if (t1 & (1<<i))
{
- i960_state->AC |= 2;
+ i960->AC |= 2;
res = i;
break;
}
}
- set_ri(i960_state, opcode, res);
+ set_ri(i960, opcode, res);
}
break;
case 0x5: // modac
- i960_state->icount -= 10;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, i960_state->AC);
- i960_state->AC = (i960_state->AC & ~t1) | (t2 & t1);
+ i960->icount -= 10;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, i960->AC);
+ i960->AC = (i960->AC & ~t1) | (t2 & t1);
break;
default:
- fatalerror("I960: %x: Unhandled 64.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 64.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x65:
switch((opcode >> 7) & 0xf) {
case 0x5: // modpc
- i960_state->icount -= 10;
- t1 = i960_state->PC;
- t2 = get_2_ri(i960_state, opcode);
- i960_state->PC = (i960_state->PC & ~t2) | (i960_state->r[(opcode>>19) & 0x1f] & t2);
- set_ri(i960_state, opcode, t1);
+ i960->icount -= 10;
+ t1 = i960->PC;
+ t2 = get_2_ri(i960, opcode);
+ i960->PC = (i960->PC & ~t2) | (i960->r[(opcode>>19) & 0x1f] & t2);
+ set_ri(i960, opcode, t1);
break;
default:
- fatalerror("I960: %x: Unhandled 65.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 65.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x66:
switch((opcode >> 7) & 0xf) {
case 0xd: // flushreg
- if (i960_state->rcache_pos > 4)
+ if (i960->rcache_pos > 4)
{
- i960_state->rcache_pos = 4;
+ i960->rcache_pos = 4;
}
- for(t1=0; t1 < i960_state->rcache_pos; t1++)
+ for(t1=0; t1 < i960->rcache_pos; t1++)
{
int i;
for (i = 0; i < 0x10; i++)
{
- program_write_dword_32le(i960_state->rcache_frame_addr[t1] + (i * sizeof(UINT32)), i960_state->rcache[t1][i]);
+ memory_write_dword_32le(i960->program, i960->rcache_frame_addr[t1] + (i * sizeof(UINT32)), i960->rcache[t1][i]);
}
}
- i960_state->rcache_pos = 0;
+ i960->rcache_pos = 0;
break;
default:
- fatalerror("I960: %x: Unhandled 66.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 66.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x67:
switch((opcode >> 7) & 0xf) {
case 0x0: // emul
- i960_state->icount -= 37;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
+ i960->icount -= 37;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
- set_ri64(i960_state, opcode, (INT64)t1 * (INT64)t2);
+ set_ri64(i960, opcode, (INT64)t1 * (INT64)t2);
break;
case 0x1: // ediv
- i960_state->icount -= 37;
+ i960->icount -= 37;
{
UINT64 src1, src2;
- src1 = get_1_ri(i960_state, opcode);
- src2 = get_2_ri64(i960_state, opcode);
+ src1 = get_1_ri(i960, opcode);
+ src2 = get_2_ri64(i960, opcode);
- set_ri2(i960_state, opcode, src2 % src1, src2 / src1);
+ set_ri2(i960, opcode, src2 % src1, src2 / src1);
}
break;
case 0x4: // cvtir
- i960_state->icount -= 30;
- t1 = get_1_ri(i960_state, opcode);
- set_rif(i960_state, opcode, (double)(INT32)t1);
+ i960->icount -= 30;
+ t1 = get_1_ri(i960, opcode);
+ set_rif(i960, opcode, (double)(INT32)t1);
break;
case 0x6: // scalerl
- i960_state->icount -= 30;
- t1 = get_1_ri(i960_state, opcode);
- t2f = get_2_rifl(i960_state, opcode);
- set_rifl(i960_state, opcode, t2f * pow(2.0, (double)(INT32)t1));
+ i960->icount -= 30;
+ t1 = get_1_ri(i960, opcode);
+ t2f = get_2_rifl(i960, opcode);
+ set_rifl(i960, opcode, t2f * pow(2.0, (double)(INT32)t1));
break;
case 0x7: // scaler
- i960_state->icount -= 30;
- t1 = get_1_ri(i960_state, opcode);
- t2f = get_2_rif(i960_state, opcode);
- set_rif(i960_state, opcode, t2f * pow(2.0, (double)(INT32)t1));
+ i960->icount -= 30;
+ t1 = get_1_ri(i960, opcode);
+ t2f = get_2_rif(i960, opcode);
+ set_rif(i960, opcode, t2f * pow(2.0, (double)(INT32)t1));
break;
default:
- fatalerror("I960: %x: Unhandled 67.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 67.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x68:
switch((opcode >> 7) & 0xf) {
case 0x0: // atanr
- i960_state->icount -= 267;
- t1f = get_1_rif(i960_state, opcode);
- t2f = get_2_rif(i960_state, opcode);
- set_rif(i960_state, opcode, atan2(t2f, t1f));
+ i960->icount -= 267;
+ t1f = get_1_rif(i960, opcode);
+ t2f = get_2_rif(i960, opcode);
+ set_rif(i960, opcode, atan2(t2f, t1f));
break;
case 0x1: // logepr
- i960_state->icount -= 400;
- t1f = get_1_rif(i960_state, opcode);
- t2f = get_2_rif(i960_state, opcode);
- set_rif(i960_state, opcode, t2f*log(t1f+1.0)/log(2.0));
+ i960->icount -= 400;
+ t1f = get_1_rif(i960, opcode);
+ t2f = get_2_rif(i960, opcode);
+ set_rif(i960, opcode, t2f*log(t1f+1.0)/log(2.0));
break;
case 0x3: // remr
- i960_state->icount -= 67; // (67 to 75878 depending on opcodes!!!)
- t1f = get_1_rif(i960_state, opcode);
- t2f = get_2_rif(i960_state, opcode);
- set_rif(i960_state, opcode, fmod(t2f, t1f));
+ i960->icount -= 67; // (67 to 75878 depending on opcodes!!!)
+ t1f = get_1_rif(i960, opcode);
+ t2f = get_2_rif(i960, opcode);
+ set_rif(i960, opcode, fmod(t2f, t1f));
break;
case 0x5: // cmpr
- i960_state->icount -= 10;
- t1f = get_1_rif(i960_state, opcode);
- t2f = get_2_rif(i960_state, opcode);
- cmp_d(i960_state, t1f, t2f);
+ i960->icount -= 10;
+ t1f = get_1_rif(i960, opcode);
+ t2f = get_2_rif(i960, opcode);
+ cmp_d(i960, t1f, t2f);
break;
case 0x8: // sqrtr
- i960_state->icount -= 104;
- t1f = get_1_rif(i960_state, opcode);
- set_rif(i960_state, opcode, sqrt(t1f));
+ i960->icount -= 104;
+ t1f = get_1_rif(i960, opcode);
+ set_rif(i960, opcode, sqrt(t1f));
break;
case 0xa: // logbnr
- i960_state->icount -= 37;
- t1f = get_1_rif(i960_state, opcode);
- set_rif(i960_state, opcode, logb(t1f));
+ i960->icount -= 37;
+ t1f = get_1_rif(i960, opcode);
+ set_rif(i960, opcode, logb(t1f));
break;
case 0xb: // roundr
{
- INT32 st1 = get_1_rif(i960_state, opcode);
- i960_state->icount -= 69;
- set_rif(i960_state, opcode, (double)st1);
+ INT32 st1 = get_1_rif(i960, opcode);
+ i960->icount -= 69;
+ set_rif(i960, opcode, (double)st1);
}
break;
case 0xc: // sinr
- i960_state->icount -= 406;
- t1f = get_1_rif(i960_state, opcode);
- set_rif(i960_state, opcode, sin(t1f));
+ i960->icount -= 406;
+ t1f = get_1_rif(i960, opcode);
+ set_rif(i960, opcode, sin(t1f));
break;
case 0xd: // cosr
- i960_state->icount -= 406;
- t1f = get_1_rif(i960_state, opcode);
- set_rif(i960_state, opcode, sin(t1f));
+ i960->icount -= 406;
+ t1f = get_1_rif(i960, opcode);
+ set_rif(i960, opcode, sin(t1f));
break;
case 0xe: // tanr
- i960_state->icount -= 293;
- t1f = get_1_rif(i960_state, opcode);
- set_rif(i960_state, opcode, tan(t1f));
+ i960->icount -= 293;
+ t1f = get_1_rif(i960, opcode);
+ set_rif(i960, opcode, tan(t1f));
break;
default:
- fatalerror("I960: %x: Unhandled 68.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 68.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x69:
switch((opcode >> 7) & 0xf) {
case 0x0: // atanrl
- i960_state->icount -= 350;
- t1f = get_1_rifl(i960_state, opcode);
- t2f = get_2_rifl(i960_state, opcode);
- set_rifl(i960_state, opcode, atan2(t2f, t1f));
+ i960->icount -= 350;
+ t1f = get_1_rifl(i960, opcode);
+ t2f = get_2_rifl(i960, opcode);
+ set_rifl(i960, opcode, atan2(t2f, t1f));
break;
case 0x2: // logrl
- i960_state->icount -= 438;
- t1f = get_1_rifl(i960_state, opcode);
- set_rifl(i960_state, opcode, log(t1f));
+ i960->icount -= 438;
+ t1f = get_1_rifl(i960, opcode);
+ set_rifl(i960, opcode, log(t1f));
break;
case 0x5: // cmprl
- i960_state->icount -= 12;
- t1f = get_1_rifl(i960_state, opcode);
- t2f = get_2_rifl(i960_state, opcode);
- cmp_d(i960_state, t1f, t2f);
+ i960->icount -= 12;
+ t1f = get_1_rifl(i960, opcode);
+ t2f = get_2_rifl(i960, opcode);
+ cmp_d(i960, t1f, t2f);
break;
case 0x8: // sqrtrl
- i960_state->icount -= 104;
- t1f = get_1_rifl(i960_state, opcode);
- set_rifl(i960_state, opcode, sqrt(t1f));
+ i960->icount -= 104;
+ t1f = get_1_rifl(i960, opcode);
+ set_rifl(i960, opcode, sqrt(t1f));
break;
case 0x9: // exprl
- i960_state->icount -= 334;
- t1f = get_1_rifl(i960_state, opcode);
- set_rifl(i960_state, opcode, pow(2.0, t1f)-1.0);
+ i960->icount -= 334;
+ t1f = get_1_rifl(i960, opcode);
+ set_rifl(i960, opcode, pow(2.0, t1f)-1.0);
break;
case 0xa: // logbnrl
- i960_state->icount -= 37;
- t1f = get_1_rifl(i960_state, opcode);
- set_rifl(i960_state, opcode, logb(t1f));
+ i960->icount -= 37;
+ t1f = get_1_rifl(i960, opcode);
+ set_rifl(i960, opcode, logb(t1f));
break;
case 0xb: // roundrl
{
- INT32 st1 = get_1_rifl(i960_state, opcode);
- i960_state->icount -= 70;
- set_rifl(i960_state, opcode, (double)st1);
+ INT32 st1 = get_1_rifl(i960, opcode);
+ i960->icount -= 70;
+ set_rifl(i960, opcode, (double)st1);
}
break;
case 0xc: // sinrl
- i960_state->icount -= 441;
- t1f = get_1_rifl(i960_state, opcode);
- set_rifl(i960_state, opcode, sin(t1f));
+ i960->icount -= 441;
+ t1f = get_1_rifl(i960, opcode);
+ set_rifl(i960, opcode, sin(t1f));
break;
case 0xd: // cosrl
- i960_state->icount -= 441;
- t1f = get_1_rifl(i960_state, opcode);
- set_rifl(i960_state, opcode, cos(t1f));
+ i960->icount -= 441;
+ t1f = get_1_rifl(i960, opcode);
+ set_rifl(i960, opcode, cos(t1f));
break;
case 0xe: // tanrl
- i960_state->icount -= 323;
- t1f = get_1_rifl(i960_state, opcode);
- set_rifl(i960_state, opcode, tan(t1f));
+ i960->icount -= 323;
+ t1f = get_1_rifl(i960, opcode);
+ set_rifl(i960, opcode, tan(t1f));
break;
default:
- fatalerror("I960: %x: Unhandled 69.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 69.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x6c:
switch((opcode >> 7) & 0xf) {
case 0x0: // cvtri
- i960_state->icount -= 33;
- t1f = get_1_rif(i960_state, opcode);
+ i960->icount -= 33;
+ t1f = get_1_rif(i960, opcode);
// apply rounding mode
// we do this a little indirectly to avoid some odd GCC warnings
t2f = 0.0;
- switch((i960_state->AC>>30)&3)
+ switch((i960->AC>>30)&3)
{
case 0: t2f = floor(t1f+0.5); break;
case 1: t2f = floor(t1f); break;
case 2: t2f = ceil(t1f); break;
case 3: t2f = t1f; break;
}
- set_ri(i960_state, opcode, (INT32)t2f);
+ set_ri(i960, opcode, (INT32)t2f);
break;
case 0x2: // cvtzri
- i960_state->icount -= 43;
- t1f = get_1_rif(i960_state, opcode);
- set_ri(i960_state, opcode, (INT32)t1f);
+ i960->icount -= 43;
+ t1f = get_1_rif(i960, opcode);
+ set_ri(i960, opcode, (INT32)t1f);
break;
case 0x3: // cvtzril
- i960_state->icount -= 44;
- t1f = get_1_rif(i960_state, opcode);
- set_ri64(i960_state, opcode, (INT64)t1f);
+ i960->icount -= 44;
+ t1f = get_1_rif(i960, opcode);
+ set_ri64(i960, opcode, (INT64)t1f);
break;
case 0x9: // movr
- i960_state->icount -= 5;
- t1f = get_1_rif(i960_state, opcode);
- set_rif(i960_state, opcode, t1f);
+ i960->icount -= 5;
+ t1f = get_1_rif(i960, opcode);
+ set_rif(i960, opcode, t1f);
break;
default:
- fatalerror("I960: %x: Unhandled 6c.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 6c.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x6d:
switch((opcode >> 7) & 0xf) {
case 0x9: // movrl
- i960_state->icount -= 6;
- t1f = get_1_rifl(i960_state, opcode);
- set_rifl(i960_state, opcode, t1f);
+ i960->icount -= 6;
+ t1f = get_1_rifl(i960, opcode);
+ set_rifl(i960, opcode, t1f);
break;
default:
- fatalerror("I960: %x: Unhandled 6d.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 6d.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
@@ -1609,20 +1611,20 @@ INLINE void execute_op(i960_state_t *i960_state, UINT32 opcode)
{
UINT32 *src=0, *dst=0;
- i960_state->icount -= 8;
+ i960->icount -= 8;
if(!(opcode & 0x00000800)) {
- src = (UINT32 *)&i960_state->r[opcode & 0x1e];
+ src = (UINT32 *)&i960->r[opcode & 0x1e];
} else {
int idx = opcode & 0x1f;
if(idx < 4)
- src = (UINT32 *)&i960_state->fp[idx];
+ src = (UINT32 *)&i960->fp[idx];
}
if(!(opcode & 0x00002000)) {
- dst = (UINT32 *)&i960_state->r[(opcode>>19) & 0x1e];
+ dst = (UINT32 *)&i960->r[(opcode>>19) & 0x1e];
} else if(!(opcode & 0x00e00000))
- dst = (UINT32 *)&i960_state->fp[(opcode>>19) & 3];
+ dst = (UINT32 *)&i960->fp[(opcode>>19) & 3];
dst[0] = src[0];
dst[1] = src[1];
@@ -1630,224 +1632,224 @@ INLINE void execute_op(i960_state_t *i960_state, UINT32 opcode)
}
break;
case 0x2: // cpysre
- i960_state->icount -= 8;
- t1f = get_1_rifl(i960_state, opcode);
- t2f = get_2_rifl(i960_state, opcode);
+ i960->icount -= 8;
+ t1f = get_1_rifl(i960, opcode);
+ t2f = get_2_rifl(i960, opcode);
if (t2f >= 0.0)
- set_rifl(i960_state, opcode, fabs(t1f));
+ set_rifl(i960, opcode, fabs(t1f));
else
- set_rifl(i960_state, opcode, -fabs(t1f));
+ set_rifl(i960, opcode, -fabs(t1f));
break;
default:
- fatalerror("I960: %x: Unhandled 6e.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 6e.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x70:
switch((opcode >> 7) & 0xf) {
case 0x1: // mulo
- i960_state->icount -= 18;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, t2*t1);
+ i960->icount -= 18;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, t2*t1);
break;
case 0x8: // remo
- i960_state->icount -= 37;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, t2%t1);
+ i960->icount -= 37;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, t2%t1);
break;
case 0xb: // divo
- i960_state->icount -= 37;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
+ i960->icount -= 37;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
if (t1 == 0) // HACK!
- set_ri(i960_state, opcode, 0);
+ set_ri(i960, opcode, 0);
else
- set_ri(i960_state, opcode, t2/t1);
+ set_ri(i960, opcode, t2/t1);
break;
default:
- fatalerror("I960: %x: Unhandled 70.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 70.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x74:
switch((opcode >> 7) & 0xf) {
case 0x1: // muli
- i960_state->icount -= 18;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, ((INT32)t2)*((INT32)t1));
+ i960->icount -= 18;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, ((INT32)t2)*((INT32)t1));
break;
case 0x8: // remi
- i960_state->icount -= 37;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, ((INT32)t2)%((INT32)t1));
+ i960->icount -= 37;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, ((INT32)t2)%((INT32)t1));
break;
case 0x9:{// modi
INT32 src1, src2, dst;
- i960_state->icount -= 37;
- src1 = (INT32)get_1_ri(i960_state, opcode);
- src2 = (INT32)get_2_ri(i960_state, opcode);
+ i960->icount -= 37;
+ src1 = (INT32)get_1_ri(i960, opcode);
+ src2 = (INT32)get_2_ri(i960, opcode);
dst = src2 - ((src2/src1)*src1);
if(((src2*src1) < 0) && (dst != 0))
dst += src1;
- set_ri(i960_state, opcode, dst);
+ set_ri(i960, opcode, dst);
break;
}
case 0xb: // divi
- i960_state->icount -= 37;
- t1 = get_1_ri(i960_state, opcode);
- t2 = get_2_ri(i960_state, opcode);
- set_ri(i960_state, opcode, ((INT32)t2)/((INT32)t1));
+ i960->icount -= 37;
+ t1 = get_1_ri(i960, opcode);
+ t2 = get_2_ri(i960, opcode);
+ set_ri(i960, opcode, ((INT32)t2)/((INT32)t1));
break;
default:
- fatalerror("I960: %x: Unhandled 74.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 74.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x78:
switch((opcode >> 7) & 0xf) {
case 0xb: // divr
- i960_state->icount -= 35;
- t1f = get_1_rif(i960_state, opcode);
- t2f = get_2_rif(i960_state, opcode);
- set_rif(i960_state, opcode, t2f/t1f);
+ i960->icount -= 35;
+ t1f = get_1_rif(i960, opcode);
+ t2f = get_2_rif(i960, opcode);
+ set_rif(i960, opcode, t2f/t1f);
break;
case 0xc: // mulr
- i960_state->icount -= 18;
- t1f = get_1_rif(i960_state, opcode);
- t2f = get_2_rif(i960_state, opcode);
- set_rif(i960_state, opcode, t2f*t1f);
+ i960->icount -= 18;
+ t1f = get_1_rif(i960, opcode);
+ t2f = get_2_rif(i960, opcode);
+ set_rif(i960, opcode, t2f*t1f);
break;
case 0xd: // subr
- i960_state->icount -= 10;
- t1f = get_1_rif(i960_state, opcode);
- t2f = get_2_rif(i960_state, opcode);
- set_rif(i960_state, opcode, t2f-t1f);
+ i960->icount -= 10;
+ t1f = get_1_rif(i960, opcode);
+ t2f = get_2_rif(i960, opcode);
+ set_rif(i960, opcode, t2f-t1f);
break;
case 0xf: // addr
- i960_state->icount -= 10;
- t1f = get_1_rif(i960_state, opcode);
- t2f = get_2_rif(i960_state, opcode);
- set_rif(i960_state, opcode, t2f+t1f);
+ i960->icount -= 10;
+ t1f = get_1_rif(i960, opcode);
+ t2f = get_2_rif(i960, opcode);
+ set_rif(i960, opcode, t2f+t1f);
break;
default:
- fatalerror("I960: %x: Unhandled 78.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 78.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x79:
switch((opcode >> 7) & 0xf) {
case 0xb: // divrl
- i960_state->icount -= 77;
- t1f = get_1_rifl(i960_state, opcode);
- t2f = get_2_rifl(i960_state, opcode);
- set_rifl(i960_state, opcode, t2f/t1f);
+ i960->icount -= 77;
+ t1f = get_1_rifl(i960, opcode);
+ t2f = get_2_rifl(i960, opcode);
+ set_rifl(i960, opcode, t2f/t1f);
break;
case 0xc: // mulrl
- i960_state->icount -= 36;
- t1f = get_1_rifl(i960_state, opcode);
- t2f = get_2_rifl(i960_state, opcode);
- set_rifl(i960_state, opcode, t2f*t1f);
+ i960->icount -= 36;
+ t1f = get_1_rifl(i960, opcode);
+ t2f = get_2_rifl(i960, opcode);
+ set_rifl(i960, opcode, t2f*t1f);
break;
case 0xd: // subrl
- i960_state->icount -= 13;
- t1f = get_1_rifl(i960_state, opcode);
- t2f = get_2_rifl(i960_state, opcode);
- set_rifl(i960_state, opcode, t2f-t1f);
+ i960->icount -= 13;
+ t1f = get_1_rifl(i960, opcode);
+ t2f = get_2_rifl(i960, opcode);
+ set_rifl(i960, opcode, t2f-t1f);
break;
case 0xf: // addrl
- i960_state->icount -= 13;
- t1f = get_1_rifl(i960_state, opcode);
- t2f = get_2_rifl(i960_state, opcode);
- set_rifl(i960_state, opcode, t2f+t1f);
+ i960->icount -= 13;
+ t1f = get_1_rifl(i960, opcode);
+ t2f = get_2_rifl(i960, opcode);
+ set_rifl(i960, opcode, t2f+t1f);
break;
default:
- fatalerror("I960: %x: Unhandled 79.%x", i960_state->PIP, (opcode >> 7) & 0xf);
+ fatalerror("I960: %x: Unhandled 79.%x", i960->PIP, (opcode >> 7) & 0xf);
}
break;
case 0x80: // ldob
- i960_state->icount -= 4;
- i960_state->r[(opcode>>19)&0x1f] = program_read_byte_32le(get_ea(i960_state, opcode));
+ i960->icount -= 4;
+ i960->r[(opcode>>19)&0x1f] = memory_read_byte_32le(i960->program, get_ea(i960, opcode));
break;
case 0x82: // stob
- i960_state->icount -= 2;
- program_write_byte_32le(get_ea(i960_state, opcode), i960_state->r[(opcode>>19)&0x1f]);
+ i960->icount -= 2;
+ memory_write_byte_32le(i960->program, get_ea(i960, opcode), i960->r[(opcode>>19)&0x1f]);
break;
case 0x84: // bx
- i960_state->icount -= 3;
- i960_state->IP = get_ea(i960_state, opcode);
- change_pc(i960_state->IP);
+ i960->icount -= 3;
+ i960->IP = get_ea(i960, opcode);
+ change_pc(i960->IP);
break;
case 0x85: // balx
- i960_state->icount -= 5;
- t1 = get_ea(i960_state, opcode);
- i960_state->r[(opcode>>19)&0x1f] = i960_state->IP;
- i960_state->IP = t1;
- change_pc(i960_state->IP);
+ i960->icount -= 5;
+ t1 = get_ea(i960, opcode);
+ i960->r[(opcode>>19)&0x1f] = i960->IP;
+ i960->IP = t1;
+ change_pc(i960->IP);
break;
case 0x86: // callx
- t1 = get_ea(i960_state, opcode);
- do_call(i960_state, t1, 0, i960_state->r[I960_SP]);
+ t1 = get_ea(i960, opcode);
+ do_call(i960, t1, 0, i960->r[I960_SP]);
break;
case 0x88: // ldos
- i960_state->icount -= 4;
- i960_state->r[(opcode>>19)&0x1f] = i960_read_word_unaligned(get_ea(i960_state, opcode));
+ i960->icount -= 4;
+ i960->r[(opcode>>19)&0x1f] = i960_read_word_unaligned(i960, get_ea(i960, opcode));
break;
case 0x8a: // stos
- i960_state->icount -= 2;
- i960_write_word_unaligned(get_ea(i960_state, opcode), i960_state->r[(opcode>>19)&0x1f]);
+ i960->icount -= 2;
+ i960_write_word_unaligned(i960, get_ea(i960, opcode), i960->r[(opcode>>19)&0x1f]);
break;
case 0x8c: // lda
- i960_state->icount--;
- i960_state->r[(opcode>>19)&0x1f] = get_ea(i960_state, opcode);
+ i960->icount--;
+ i960->r[(opcode>>19)&0x1f] = get_ea(i960, opcode);
break;
case 0x90: // ld
- i960_state->icount -= 4;
- i960_state->r[(opcode>>19)&0x1f] = i960_read_dword_unaligned(get_ea(i960_state, opcode));
+ i960->icount -= 4;
+ i960->r[(opcode>>19)&0x1f] = i960_read_dword_unaligned(i960, get_ea(i960, opcode));
break;
case 0x92: // st
- i960_state->icount -= 2;
- i960_write_dword_unaligned(get_ea(i960_state, opcode), i960_state->r[(opcode>>19)&0x1f]);
+ i960->icount -= 2;
+ i960_write_dword_unaligned(i960, get_ea(i960, opcode), i960->r[(opcode>>19)&0x1f]);
break;
case 0x98:{// ldl
int i;
- i960_state->icount -= 5;
- t1 = get_ea(i960_state, opcode);
+ i960->icount -= 5;
+ t1 = get_ea(i960, opcode);
t2 = (opcode>>19)&0x1e;
- i960_state->bursting = 1;
+ i960->bursting = 1;
for(i=0; i<2; i++) {
- i960_state->r[t2+i] = i960_read_dword_unaligned(t1);
- if(i960_state->bursting)
+ i960->r[t2+i] = i960_read_dword_unaligned(i960, t1);
+ if(i960->bursting)
t1 += 4;
}
break;
@@ -1855,13 +1857,13 @@ INLINE void execute_op(i960_state_t *i960_state, UINT32 opcode)
case 0x9a:{// stl
int i;
- i960_state->icount -= 3;
- t1 = get_ea(i960_state, opcode);
+ i960->icount -= 3;
+ t1 = get_ea(i960, opcode);
t2 = (opcode>>19)&0x1e;
- i960_state->bursting = 1;
+ i960->bursting = 1;
for(i=0; i<2; i++) {
- i960_write_dword_unaligned(t1, i960_state->r[t2+i]);
- if(i960_state->bursting)
+ i960_write_dword_unaligned(i960, t1, i960->r[t2+i]);
+ if(i960->bursting)
t1 += 4;
}
break;
@@ -1869,13 +1871,13 @@ INLINE void execute_op(i960_state_t *i960_state, UINT32 opcode)
case 0xa0:{// ldt
int i;
- i960_state->icount -= 6;
- t1 = get_ea(i960_state, opcode);
+ i960->icount -= 6;
+ t1 = get_ea(i960, opcode);
t2 = (opcode>>19)&0x1c;
- i960_state->bursting = 1;
+ i960->bursting = 1;
for(i=0; i<3; i++) {
- i960_state->r[t2+i] = i960_read_dword_unaligned(t1);
- if(i960_state->bursting)
+ i960->r[t2+i] = i960_read_dword_unaligned(i960, t1);
+ if(i960->bursting)
t1 += 4;
}
break;
@@ -1883,13 +1885,13 @@ INLINE void execute_op(i960_state_t *i960_state, UINT32 opcode)
case 0xa2:{// stt
int i;
- i960_state->icount -= 4;
- t1 = get_ea(i960_state, opcode);
+ i960->icount -= 4;
+ t1 = get_ea(i960, opcode);
t2 = (opcode>>19)&0x1c;
- i960_state->bursting = 1;
+ i960->bursting = 1;
for(i=0; i<3; i++) {
- i960_write_dword_unaligned(t1, i960_state->r[t2+i]);
- if(i960_state->bursting)
+ i960_write_dword_unaligned(i960, t1, i960->r[t2+i]);
+ if(i960->bursting)
t1 += 4;
}
break;
@@ -1897,13 +1899,13 @@ INLINE void execute_op(i960_state_t *i960_state, UINT32 opcode)
case 0xb0:{// ldq
int i;
- i960_state->icount -= 7;
- t1 = get_ea(i960_state, opcode);
+ i960->icount -= 7;
+ t1 = get_ea(i960, opcode);
t2 = (opcode>>19)&0x1c;
- i960_state->bursting = 1;
+ i960->bursting = 1;
for(i=0; i<4; i++) {
- i960_state->r[t2+i] = i960_read_dword_unaligned(t1);
- if(i960_state->bursting)
+ i960->r[t2+i] = i960_read_dword_unaligned(i960, t1);
+ if(i960->bursting)
t1 += 4;
}
break;
@@ -1911,63 +1913,63 @@ INLINE void execute_op(i960_state_t *i960_state, UINT32 opcode)
case 0xb2:{// stq
int i;
- i960_state->icount -= 5;
- t1 = get_ea(i960_state, opcode);
+ i960->icount -= 5;
+ t1 = get_ea(i960, opcode);
t2 = (opcode>>19)&0x1c;
- i960_state->bursting = 1;
+ i960->bursting = 1;
for(i=0; i<4; i++) {
- i960_write_dword_unaligned(t1, i960_state->r[t2+i]);
- if(i960_state->bursting)
+ i960_write_dword_unaligned(i960, t1, i960->r[t2+i]);
+ if(i960->bursting)
t1 += 4;
}
break;
}
case 0xc0: // ldib
- i960_state->icount -= 4;
- i960_state->r[(opcode>>19)&0x1f] = (INT8)program_read_byte_32le(get_ea(i960_state, opcode));
+ i960->icount -= 4;
+ i960->r[(opcode>>19)&0x1f] = (INT8)memory_read_byte_32le(i960->program, get_ea(i960, opcode));
break;
case 0xc2: // stib
- i960_state->icount -= 2;
- program_write_byte_32le(get_ea(i960_state, opcode), i960_state->r[(opcode>>19)&0x1f]);
+ i960->icount -= 2;
+ memory_write_byte_32le(i960->program, get_ea(i960, opcode), i960->r[(opcode>>19)&0x1f]);
break;
case 0xc8: // ldis
- i960_state->icount -= 4;
- i960_state->r[(opcode>>19)&0x1f] = (INT16)i960_read_word_unaligned(get_ea(i960_state, opcode));
+ i960->icount -= 4;
+ i960->r[(opcode>>19)&0x1f] = (INT16)i960_read_word_unaligned(i960, get_ea(i960, opcode));
break;
case 0xca: // stis
- i960_state->icount -= 2;
- i960_write_word_unaligned(get_ea(i960_state, opcode), i960_state->r[(opcode>>19)&0x1f]);
+ i960->icount -= 2;
+ i960_write_word_unaligned(i960, get_ea(i960, opcode), i960->r[(opcode>>19)&0x1f]);
break;
default:
- fatalerror("I960: %x: Unhandled %02x", i960_state->PIP, opcode >> 24);
+ fatalerror("I960: %x: Unhandled %02x", i960->PIP, opcode >> 24);
}
}
static CPU_EXECUTE( i960 )
{
- i960_state_t *i960_state = device->token;
+ i960_state_t *i960 = device->token;
UINT32 opcode;
- i960_state->icount = cycles;
- check_irqs(i960_state);
- while(i960_state->icount >= 0) {
- i960_state->PIP = i960_state->IP;
- debugger_instruction_hook(device, i960_state->IP);
+ i960->icount = cycles;
+ check_irqs(i960);
+ while(i960->icount >= 0) {
+ i960->PIP = i960->IP;
+ debugger_instruction_hook(device, i960->IP);
- i960_state->bursting = 0;
+ i960->bursting = 0;
- opcode = program_decrypted_read_dword(i960_state->IP);
- i960_state->IP += 4;
+ opcode = memory_decrypted_read_dword(i960->program, i960->IP);
+ i960->IP += 4;
- execute_op(i960_state, opcode);
+ execute_op(i960, opcode);
}
- return cycles - i960_state->icount;
+ return cycles - i960->icount;
}
static CPU_GET_CONTEXT( i960 )
@@ -1978,10 +1980,10 @@ static CPU_SET_CONTEXT( i960 )
{
}
-static void set_irq_line(i960_state_t *i960_state, int irqline, int state)
+static void set_irq_line(i960_state_t *i960, int irqline, int state)
{
- int int_tab = program_read_dword_32le(i960_state->PRCB+20); // interrupt table
- int cpu_pri = (i960_state->PC>>16)&0x1f;
+ int int_tab = memory_read_dword_32le(i960->program, i960->PRCB+20); // interrupt table
+ int cpu_pri = (i960->PC>>16)&0x1f;
int vector =0;
int priority;
UINT32 pend, word, wordofs;
@@ -1993,19 +1995,19 @@ static void set_irq_line(i960_state_t *i960_state, int irqline, int state)
switch (irqline)
{
case I960_IRQ0:
- vector = i960_state->ICR & 0xff;
+ vector = i960->ICR & 0xff;
break;
case I960_IRQ1:
- vector = (i960_state->ICR>>8)&0xff;
+ vector = (i960->ICR>>8)&0xff;
break;
case I960_IRQ2:
- vector = (i960_state->ICR>>16)&0xff;
+ vector = (i960->ICR>>16)&0xff;
break;
case I960_IRQ3:
- vector = (i960_state->ICR>>24)&0xff;
+ vector = (i960->ICR>>24)&0xff;
break;
}
@@ -2020,48 +2022,48 @@ static void set_irq_line(i960_state_t *i960_state, int irqline, int state)
if(state) {
// check if we can take this "right now"
- if (((cpu_pri < priority) || (priority == 31)) && (i960_state->immediate_irq == 0))
+ if (((cpu_pri < priority) || (priority == 31)) && (i960->immediate_irq == 0))
{
- i960_state->immediate_irq = 1;
- i960_state->immediate_vector = vector;
- i960_state->immediate_pri = priority;
+ i960->immediate_irq = 1;
+ i960->immediate_vector = vector;
+ i960->immediate_pri = priority;
}
else
{
// store the interrupt in the "pending" table
- pend = program_read_dword_32le(int_tab);
+ pend = memory_read_dword_32le(i960->program, int_tab);
pend |= (1 << priority);
- program_write_dword_32le(int_tab, pend);
+ memory_write_dword_32le(i960->program, int_tab, pend);
// now bitfield-ize the vector
word = ((vector / 32) * 4) + 4;
wordofs = vector % 32;
- pend = program_read_dword_32le(int_tab + word);
+ pend = memory_read_dword_32le(i960->program, int_tab + word);
pend |= (1 << wordofs);
- program_write_dword_32le(int_tab + word, pend);
+ memory_write_dword_32le(i960->program, int_tab + word, pend);
}
// and ack it to the core now that it's queued
- (*i960_state->irq_cb)(i960_state->device, irqline);
+ (*i960->irq_cb)(i960->device, irqline);
}
}
static CPU_SET_INFO( i960 )
{
- i960_state_t *i960_state = device->token;
+ i960_state_t *i960 = device->token;
if(state >= CPUINFO_INT_REGISTER+I960_R0 && state <= CPUINFO_INT_REGISTER + I960_G15) {
- i960_state->r[state - (CPUINFO_INT_REGISTER + I960_R0)] = info->i;
+ i960->r[state - (CPUINFO_INT_REGISTER + I960_R0)] = info->i;
return;
}
switch(state) {
// Interfacing
- case CPUINFO_INT_REGISTER + I960_IP: i960_state->IP = info->i; change_pc(i960_state->IP); break;
- case CPUINFO_INT_INPUT_STATE + I960_IRQ0: set_irq_line(i960_state, I960_IRQ0, info->i); break;
- case CPUINFO_INT_INPUT_STATE + I960_IRQ1: set_irq_line(i960_state, I960_IRQ1, info->i); break;
- case CPUINFO_INT_INPUT_STATE + I960_IRQ2: set_irq_line(i960_state, I960_IRQ2, info->i); break;
- case CPUINFO_INT_INPUT_STATE + I960_IRQ3: set_irq_line(i960_state, I960_IRQ3, info->i); break;
+ case CPUINFO_INT_REGISTER + I960_IP: i960->IP = info->i; change_pc(i960->IP); break;
+ case CPUINFO_INT_INPUT_STATE + I960_IRQ0: set_irq_line(i960, I960_IRQ0, info->i); break;
+ case CPUINFO_INT_INPUT_STATE + I960_IRQ1: set_irq_line(i960, I960_IRQ1, info->i); break;
+ case CPUINFO_INT_INPUT_STATE + I960_IRQ2: set_irq_line(i960, I960_IRQ2, info->i); break;
+ case CPUINFO_INT_INPUT_STATE + I960_IRQ3: set_irq_line(i960, I960_IRQ3, info->i); break;
default:
fatalerror("i960_set_info %x", state);
@@ -2070,21 +2072,22 @@ static CPU_SET_INFO( i960 )
static CPU_INIT( i960 )
{
- i960_state_t *i960_state = device->token;
-
- i960_state->irq_cb = irqcallback;
- i960_state->device = device;
-
- state_save_register_item("i960", device->tag, 0, i960_state->PIP);
- state_save_register_item("i960", device->tag, 0, i960_state->SAT);
- state_save_register_item("i960", device->tag, 0, i960_state->PRCB);
- state_save_register_item("i960", device->tag, 0, i960_state->PC);
- state_save_register_item("i960", device->tag, 0, i960_state->AC);
- state_save_register_item("i960", device->tag, 0, i960_state->ICR);
- state_save_register_item_array("i960", device->tag, 0, i960_state->r);
- state_save_register_item_array("i960", device->tag, 0, i960_state->fp);
- state_save_register_item_2d_array("i960", device->tag, 0, i960_state->rcache);
- state_save_register_item_array("i960", device->tag, 0, i960_state->rcache_frame_addr);
+ i960_state_t *i960 = device->token;
+
+ i960->irq_cb = irqcallback;
+ i960->device = device;
+ i960->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+
+ state_save_register_item("i960", device->tag, 0, i960->PIP);
+ state_save_register_item("i960", device->tag, 0, i960->SAT);
+ state_save_register_item("i960", device->tag, 0, i960->PRCB);
+ state_save_register_item("i960", device->tag, 0, i960->PC);
+ state_save_register_item("i960", device->tag, 0, i960->AC);
+ state_save_register_item("i960", device->tag, 0, i960->ICR);
+ state_save_register_item_array("i960", device->tag, 0, i960->r);
+ state_save_register_item_array("i960", device->tag, 0, i960->fp);
+ state_save_register_item_2d_array("i960", device->tag, 0, i960->rcache);
+ state_save_register_item_array("i960", device->tag, 0, i960->rcache_frame_addr);
}
static CPU_DISASSEMBLE( i960 )
@@ -2102,31 +2105,31 @@ static CPU_DISASSEMBLE( i960 )
static CPU_RESET( i960 )
{
- i960_state_t *i960_state = device->token;
-
- i960_state->SAT = program_read_dword_32le(0);
- i960_state->PRCB = program_read_dword_32le(4);
- i960_state->IP = program_read_dword_32le(12);
- i960_state->PC = 0x001f2002;
- i960_state->AC = 0;
- i960_state->ICR = 0xff000000;
- i960_state->bursting = 0;
- i960_state->immediate_irq = 0;
-
- memset(i960_state->r, 0, sizeof(i960_state->r));
- memset(i960_state->rcache, 0, sizeof(i960_state->rcache));
-
- i960_state->r[I960_FP] = program_read_dword_32le(i960_state->PRCB+24);
- i960_state->r[I960_SP] = i960_state->r[I960_FP] + 64;
- i960_state->rcache_pos = 0;
+ i960_state_t *i960 = device->token;
+
+ i960->SAT = memory_read_dword_32le(i960->program, 0);
+ i960->PRCB = memory_read_dword_32le(i960->program, 4);
+ i960->IP = memory_read_dword_32le(i960->program, 12);
+ i960->PC = 0x001f2002;
+ i960->AC = 0;
+ i960->ICR = 0xff000000;
+ i960->bursting = 0;
+ i960->immediate_irq = 0;
+
+ memset(i960->r, 0, sizeof(i960->r));
+ memset(i960->rcache, 0, sizeof(i960->rcache));
+
+ i960->r[I960_FP] = memory_read_dword_32le(i960->program, i960->PRCB+24);
+ i960->r[I960_SP] = i960->r[I960_FP] + 64;
+ i960->rcache_pos = 0;
}
CPU_GET_INFO( i960 )
{
- i960_state_t *i960_state = (device != NULL) ? device->token : NULL;
+ i960_state_t *i960 = (device != NULL) ? device->token : NULL;
if(state >= CPUINFO_INT_REGISTER+I960_R0 && state <= CPUINFO_INT_REGISTER + I960_G15) {
- info->i = i960_state->r[state - (CPUINFO_INT_REGISTER + I960_R0)];
+ info->i = i960->r[state - (CPUINFO_INT_REGISTER + I960_R0)];
return;
}
@@ -2141,8 +2144,8 @@ CPU_GET_INFO( i960 )
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(i960); break;
case CPUINFO_PTR_BURN: info->burn = 0; break;
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i960); break;
- case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &i960_state->icount; break;
- case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(i960_state_t); break;
+ case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &i960->icount; break;
+ case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(i960_state_t); break;
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 4; break;
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 8; break;
@@ -2161,14 +2164,14 @@ CPU_GET_INFO( i960 )
case CPUINFO_INT_LOGADDR_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
// Internal maps
- case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map32 = NULL; break;
- case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_DATA: info->internal_map32 = NULL; break;
- case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_IO: info->internal_map32 = NULL; break;
+ case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map32 = NULL;break;
+ case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_DATA: info->internal_map32 = NULL;break;
+ case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_IO: info->internal_map32 = NULL;break;
// CPU misc parameters
case CPUINFO_STR_NAME: strcpy(info->s, "i960KB"); break;
case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
- case CPUINFO_STR_FLAGS: strcpy(info->s, i960_get_strflags(i960_state)); break;
+ case CPUINFO_STR_FLAGS: strcpy(info->s, i960_get_strflags(i960)); break;
case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break;
case CPUINFO_INT_INPUT_LINES: info->i = 4; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = -1; break;
@@ -2176,58 +2179,58 @@ CPU_GET_INFO( i960 )
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
// CPU main state
- case CPUINFO_INT_PC: info->i = i960_state->IP; break;
- case CPUINFO_INT_SP: info->i = i960_state->r[I960_SP]; break;
- case CPUINFO_INT_PREVIOUSPC: info->i = i960_state->PIP; break;
+ case CPUINFO_INT_PC: info->i = i960->IP; break;
+ case CPUINFO_INT_SP: info->i = i960->r[I960_SP]; break;
+ case CPUINFO_INT_PREVIOUSPC: info->i = i960->PIP; break;
- case CPUINFO_INT_REGISTER + I960_SAT: info->i = i960_state->SAT; break;
- case CPUINFO_INT_REGISTER + I960_PRCB: info->i = i960_state->PRCB; break;
- case CPUINFO_INT_REGISTER + I960_PC: info->i = i960_state->PC; break;
- case CPUINFO_INT_REGISTER + I960_AC: info->i = i960_state->AC; break;
- case CPUINFO_INT_REGISTER + I960_IP: info->i = i960_state->IP; break;
- case CPUINFO_INT_REGISTER + I960_PIP: info->i = i960_state->PIP; break;
+ case CPUINFO_INT_REGISTER + I960_SAT: info->i = i960->SAT; break;
+ case CPUINFO_INT_REGISTER + I960_PRCB: info->i = i960->PRCB; break;
+ case CPUINFO_INT_REGISTER + I960_PC: info->i = i960->PC; break;
+ case CPUINFO_INT_REGISTER + I960_AC: info->i = i960->AC; break;
+ case CPUINFO_INT_REGISTER + I960_IP: info->i = i960->IP; break;
+ case CPUINFO_INT_REGISTER + I960_PIP: info->i = i960->PIP; break;
// CPU debug stuff
- case CPUINFO_STR_REGISTER + I960_SAT: sprintf(info->s, "sat :%08x", i960_state->SAT); break;
- case CPUINFO_STR_REGISTER + I960_PRCB: sprintf(info->s, "prcb :%08x", i960_state->PRCB); break;
- case CPUINFO_STR_REGISTER + I960_PC: sprintf(info->s, "pc :%08x", i960_state->PC); break;
- case CPUINFO_STR_REGISTER + I960_AC: sprintf(info->s, "ac :%08x", i960_state->AC); break;
- case CPUINFO_STR_REGISTER + I960_IP: sprintf(info->s, "ip :%08x", i960_state->IP); break;
- case CPUINFO_STR_REGISTER + I960_PIP: sprintf(info->s, "pip :%08x", i960_state->PIP); break;
-
- case CPUINFO_STR_REGISTER + I960_R0: sprintf(info->s, "pfp :%08x", i960_state->r[ 0]); break;
- case CPUINFO_STR_REGISTER + I960_R1: sprintf(info->s, "sp :%08x", i960_state->r[ 1]); break;
- case CPUINFO_STR_REGISTER + I960_R2: sprintf(info->s, "rip :%08x", i960_state->r[ 2]); break;
- case CPUINFO_STR_REGISTER + I960_R3: sprintf(info->s, "r3 :%08x", i960_state->r[ 3]); break;
- case CPUINFO_STR_REGISTER + I960_R4: sprintf(info->s, "r4 :%08x", i960_state->r[ 4]); break;
- case CPUINFO_STR_REGISTER + I960_R5: sprintf(info->s, "r5 :%08x", i960_state->r[ 5]); break;
- case CPUINFO_STR_REGISTER + I960_R6: sprintf(info->s, "r6 :%08x", i960_state->r[ 6]); break;
- case CPUINFO_STR_REGISTER + I960_R7: sprintf(info->s, "r7 :%08x", i960_state->r[ 7]); break;
- case CPUINFO_STR_REGISTER + I960_R8: sprintf(info->s, "r8 :%08x", i960_state->r[ 8]); break;
- case CPUINFO_STR_REGISTER + I960_R9: sprintf(info->s, "r9 :%08x", i960_state->r[ 9]); break;
- case CPUINFO_STR_REGISTER + I960_R10: sprintf(info->s, "r10 :%08x", i960_state->r[10]); break;
- case CPUINFO_STR_REGISTER + I960_R11: sprintf(info->s, "r11 :%08x", i960_state->r[11]); break;
- case CPUINFO_STR_REGISTER + I960_R12: sprintf(info->s, "r12 :%08x", i960_state->r[12]); break;
- case CPUINFO_STR_REGISTER + I960_R13: sprintf(info->s, "r13 :%08x", i960_state->r[13]); break;
- case CPUINFO_STR_REGISTER + I960_R14: sprintf(info->s, "r14 :%08x", i960_state->r[14]); break;
- case CPUINFO_STR_REGISTER + I960_R15: sprintf(info->s, "r15 :%08x", i960_state->r[15]); break;
-
- case CPUINFO_STR_REGISTER + I960_G0: sprintf(info->s, "g0 :%08x", i960_state->r[16]); break;
- case CPUINFO_STR_REGISTER + I960_G1: sprintf(info->s, "g1 :%08x", i960_state->r[17]); break;
- case CPUINFO_STR_REGISTER + I960_G2: sprintf(info->s, "g2 :%08x", i960_state->r[18]); break;
- case CPUINFO_STR_REGISTER + I960_G3: sprintf(info->s, "g3 :%08x", i960_state->r[19]); break;
- case CPUINFO_STR_REGISTER + I960_G4: sprintf(info->s, "g4 :%08x", i960_state->r[20]); break;
- case CPUINFO_STR_REGISTER + I960_G5: sprintf(info->s, "g5 :%08x", i960_state->r[21]); break;
- case CPUINFO_STR_REGISTER + I960_G6: sprintf(info->s, "g6 :%08x", i960_state->r[22]); break;
- case CPUINFO_STR_REGISTER + I960_G7: sprintf(info->s, "g7 :%08x", i960_state->r[23]); break;
- case CPUINFO_STR_REGISTER + I960_G8: sprintf(info->s, "g8 :%08x", i960_state->r[24]); break;
- case CPUINFO_STR_REGISTER + I960_G9: sprintf(info->s, "g9 :%08x", i960_state->r[25]); break;
- case CPUINFO_STR_REGISTER + I960_G10: sprintf(info->s, "g10 :%08x", i960_state->r[26]); break;
- case CPUINFO_STR_REGISTER + I960_G11: sprintf(info->s, "g11 :%08x", i960_state->r[27]); break;
- case CPUINFO_STR_REGISTER + I960_G12: sprintf(info->s, "g12 :%08x", i960_state->r[28]); break;
- case CPUINFO_STR_REGISTER + I960_G13: sprintf(info->s, "g13 :%08x", i960_state->r[29]); break;
- case CPUINFO_STR_REGISTER + I960_G14: sprintf(info->s, "g14 :%08x", i960_state->r[30]); break;
- case CPUINFO_STR_REGISTER + I960_G15: sprintf(info->s, "fp :%08x", i960_state->r[31]); break;
+ case CPUINFO_STR_REGISTER + I960_SAT: sprintf(info->s, "sat :%08x", i960->SAT); break;
+ case CPUINFO_STR_REGISTER + I960_PRCB: sprintf(info->s, "prcb :%08x", i960->PRCB); break;
+ case CPUINFO_STR_REGISTER + I960_PC: sprintf(info->s, "pc :%08x", i960->PC); break;
+ case CPUINFO_STR_REGISTER + I960_AC: sprintf(info->s, "ac :%08x", i960->AC); break;
+ case CPUINFO_STR_REGISTER + I960_IP: sprintf(info->s, "ip :%08x", i960->IP); break;
+ case CPUINFO_STR_REGISTER + I960_PIP: sprintf(info->s, "pip :%08x", i960->PIP); break;
+
+ case CPUINFO_STR_REGISTER + I960_R0: sprintf(info->s, "pfp :%08x", i960->r[ 0]); break;
+ case CPUINFO_STR_REGISTER + I960_R1: sprintf(info->s, "sp :%08x", i960->r[ 1]); break;
+ case CPUINFO_STR_REGISTER + I960_R2: sprintf(info->s, "rip :%08x", i960->r[ 2]); break;
+ case CPUINFO_STR_REGISTER + I960_R3: sprintf(info->s, "r3 :%08x", i960->r[ 3]); break;
+ case CPUINFO_STR_REGISTER + I960_R4: sprintf(info->s, "r4 :%08x", i960->r[ 4]); break;
+ case CPUINFO_STR_REGISTER + I960_R5: sprintf(info->s, "r5 :%08x", i960->r[ 5]); break;
+ case CPUINFO_STR_REGISTER + I960_R6: sprintf(info->s, "r6 :%08x", i960->r[ 6]); break;
+ case CPUINFO_STR_REGISTER + I960_R7: sprintf(info->s, "r7 :%08x", i960->r[ 7]); break;
+ case CPUINFO_STR_REGISTER + I960_R8: sprintf(info->s, "r8 :%08x", i960->r[ 8]); break;
+ case CPUINFO_STR_REGISTER + I960_R9: sprintf(info->s, "r9 :%08x", i960->r[ 9]); break;
+ case CPUINFO_STR_REGISTER + I960_R10: sprintf(info->s, "r10 :%08x", i960->r[10]); break;
+ case CPUINFO_STR_REGISTER + I960_R11: sprintf(info->s, "r11 :%08x", i960->r[11]); break;
+ case CPUINFO_STR_REGISTER + I960_R12: sprintf(info->s, "r12 :%08x", i960->r[12]); break;
+ case CPUINFO_STR_REGISTER + I960_R13: sprintf(info->s, "r13 :%08x", i960->r[13]); break;
+ case CPUINFO_STR_REGISTER + I960_R14: sprintf(info->s, "r14 :%08x", i960->r[14]); break;
+ case CPUINFO_STR_REGISTER + I960_R15: sprintf(info->s, "r15 :%08x", i960->r[15]); break;
+
+ case CPUINFO_STR_REGISTER + I960_G0: sprintf(info->s, "g0 :%08x", i960->r[16]); break;
+ case CPUINFO_STR_REGISTER + I960_G1: sprintf(info->s, "g1 :%08x", i960->r[17]); break;
+ case CPUINFO_STR_REGISTER + I960_G2: sprintf(info->s, "g2 :%08x", i960->r[18]); break;
+ case CPUINFO_STR_REGISTER + I960_G3: sprintf(info->s, "g3 :%08x", i960->r[19]); break;
+ case CPUINFO_STR_REGISTER + I960_G4: sprintf(info->s, "g4 :%08x", i960->r[20]); break;
+ case CPUINFO_STR_REGISTER + I960_G5: sprintf(info->s, "g5 :%08x", i960->r[21]); break;
+ case CPUINFO_STR_REGISTER + I960_G6: sprintf(info->s, "g6 :%08x", i960->r[22]); break;
+ case CPUINFO_STR_REGISTER + I960_G7: sprintf(info->s, "g7 :%08x", i960->r[23]); break;
+ case CPUINFO_STR_REGISTER + I960_G8: sprintf(info->s, "g8 :%08x", i960->r[24]); break;
+ case CPUINFO_STR_REGISTER + I960_G9: sprintf(info->s, "g9 :%08x", i960->r[25]); break;
+ case CPUINFO_STR_REGISTER + I960_G10: sprintf(info->s, "g10 :%08x", i960->r[26]); break;
+ case CPUINFO_STR_REGISTER + I960_G11: sprintf(info->s, "g11 :%08x", i960->r[27]); break;
+ case CPUINFO_STR_REGISTER + I960_G12: sprintf(info->s, "g12 :%08x", i960->r[28]); break;
+ case CPUINFO_STR_REGISTER + I960_G13: sprintf(info->s, "g13 :%08x", i960->r[29]); break;
+ case CPUINFO_STR_REGISTER + I960_G14: sprintf(info->s, "g14 :%08x", i960->r[30]); break;
+ case CPUINFO_STR_REGISTER + I960_G15: sprintf(info->s, "fp :%08x", i960->r[31]); break;
// default:
// fatalerror("i960_get_info %x ", state);
@@ -2238,12 +2241,12 @@ CPU_GET_INFO( i960 )
// on the real hardware (e.g. Model 2's interrupt control registers)
void i960_noburst(const device_config *device)
{
- i960_state_t *i960_state = device->token;
- i960_state->bursting = 0;
+ i960_state_t *i960 = device->token;
+ i960->bursting = 0;
}
void i960_stall(const device_config *device)
{
- i960_state_t *i960_state = device->token;
- i960_state->IP = i960_state->PIP;
+ i960_state_t *i960 = device->token;
+ i960->IP = i960->PIP;
}