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author Vas Crabb <vas@vastheman.com>2024-05-20 19:46:53 +1000
committer Vas Crabb <vas@vastheman.com>2024-05-20 19:47:08 +1000
commit835e7e4462e2f38ff34ea420d57e882dcdb98140 (patch)
tree0079e247f7c99fa5afb6ac16821230d2e82ded41 /src
parente20dc1f93b320ea373adda35b3ca87bbad3f27e9 (diff)
bus/kim1: Added pinouts for the main variants of the "6502 local bus" to comment.
Diffstat (limited to 'src')
-rw-r--r--src/devices/bus/kim1/kim1bus.h77
1 files changed, 77 insertions, 0 deletions
diff --git a/src/devices/bus/kim1/kim1bus.h b/src/devices/bus/kim1/kim1bus.h
index 2512654c196..2fa57a2096d 100644
--- a/src/devices/bus/kim1/kim1bus.h
+++ b/src/devices/bus/kim1/kim1bus.h
@@ -4,6 +4,83 @@
kim1bus.h - KIM-1 expansion bus
+ Basically 6502 bus brought out to a connector.
+
+ 44-pin edge connector, 1-22 on top, A-Z on bottom
+
+ SYNC 1 A AB0
+ /RDY 2 B AB1
+ clock phase 1 3 C AB2
+ /IRQ 4 D AB3
+ RO 5 E AB4
+ /NMI 6 F AB5
+ /RES 7 H AB6
+ DB7 8 J AB7
+ DB6 9 K AB8
+ DB5 10 L AB9
+ DB4 11 M AB10
+ DB3 12 N AB11
+ DB2 13 P AB12
+ DB1 14 R AB13
+ DB0 15 S AB14
+ K6 16 T AB15
+ SST out 17 U clock phase 2
+ N/C 18 V R/W
+ N/C 19 W inverted R/W
+ N/C 20 X PLL test
+ VCC 21 Y inverted clock phase 2
+ GND 22 Z RAM R/W
+
+ * RO is connected to 6502 SO pin
+ * K6 is asserted (low) when accessing 0x1800-0x1bff (mirror 0xe000)
+
+ Rockwell AIM65 expansion only differs in five pins:
+
+ -12V 16
+ +12V 17
+ /CS8 18
+ /CS9 19
+ /CSA 20
+
+ Comelta DRAC-1 expansion modules use a 64-pin edge connector with an
+ external manual reset input and more power rails, but without some
+ control signals:
+
+ +25V a 1 c +25V
+ external manual reset a 2 c reserved
+ reserved a 3 c +5V battery
+ +12V a 4 c +15V
+ -5V a 5 c -15V/-12V
+ +5V a 6 c +5V
+ GND a 7 c GND
+ GND a 8 c GND
+ N/C a 9 c N/C
+ N/C a 10 c N/C
+ N/C a 11 c N/C
+ N/C a 12 c N/C
+ reserved a 13 c SYNC
+ reserved a 14 c reserved
+ R/W a 15 c /RDY
+ clock phase 2 a 16 c clock phase 1
+ /IRQ a 17 c reserved
+ /NMI a 18 c /RES
+ reserved a 19 c reserved
+ DB7 a 20 c DB6
+ DB5 a 21 c DB4
+ DB3 a 22 c DB2
+ DB1 a 23 c DB0
+ reserved a 24 c reserved
+ AB15 a 25 c AB14
+ AB13 a 26 c AB12
+ AB11 a 27 c AB10
+ AB9 a 28 c AB8
+ AB7 a 29 c AB6
+ AB5 a 30 c AB4
+ AB3 a 31 c AB2
+ AB1 a 32 c AB0
+
+ * No RO, RAM R/W, inverted clock phase 2 and R/W, K6 or SST out
+
***************************************************************************/
#ifndef MAME_BUS_KIM1_KIM1BUS_H