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author Couriersud <couriersud@users.noreply.github.com>2008-11-23 16:58:41 +0000
committer Couriersud <couriersud@users.noreply.github.com>2008-11-23 16:58:41 +0000
commit80991da900a3a92c38539bdaa3a0098a224ee9c8 (patch)
treebf5293d23b16437184e83101c7a9a1860b96977e /src
parent12e44c67c4a6ca8006fbb4a9b54e8990972c7310 (diff)
Pointer-"ified" the s2650 core
* Used s2650c to identify the state variable. This is unique within the 2650 core and may be renamed using simple replace.
Diffstat (limited to 'src')
-rw-r--r--src/emu/cpu/s2650/s2650.c922
-rw-r--r--src/emu/cpu/s2650/s2650cpu.h8
2 files changed, 468 insertions, 462 deletions
diff --git a/src/emu/cpu/s2650/s2650.c b/src/emu/cpu/s2650/s2650.c
index 314f125d945..56c63fa90ce 100644
--- a/src/emu/cpu/s2650/s2650.c
+++ b/src/emu/cpu/s2650/s2650.c
@@ -25,9 +25,8 @@
/* define this to expand all EA calculations inline */
#define INLINE_EA 1
-static int s2650_ICount = 0;
-
-typedef struct {
+typedef struct _s2650_regs s2650_regs;
+struct _s2650_regs {
UINT16 ppc; /* previous program counter (page + iar) */
UINT16 page; /* 8K page select register (A14..A13) */
UINT16 iar; /* instruction address register (A12..A0) */
@@ -40,13 +39,13 @@ typedef struct {
UINT8 ir; /* instruction register */
UINT16 ras[8]; /* 8 return address stack entries */
UINT8 irq_state;
+
+ int icount;
cpu_irq_callback irq_callback;
const device_config *device;
const address_space *program;
const address_space *io;
-} s2650_Regs;
-
-static s2650_Regs S;
+};
/* condition code changes for a byte */
static const UINT8 ccc[0x200] = {
@@ -116,37 +115,37 @@ static const UINT8 ccc[0x200] = {
0x84,0x84,0x84,0x84,0x84,0x84,0x84,0x84
};
-static void s2650_set_sense(int state);
+static void s2650_set_sense(s2650_regs *s2650c, int state);
#define CHECK_IRQ_LINE \
- if (S.irq_state != CLEAR_LINE) \
+ if (s2650c->irq_state != CLEAR_LINE) \
{ \
- if( (S.psu & II) == 0 ) \
+ if( (s2650c->psu & II) == 0 ) \
{ \
int vector; \
- if (S.halt) \
+ if (s2650c->halt) \
{ \
- S.halt = 0; \
- S.iar = (S.iar + 1) & PMSK; \
+ s2650c->halt = 0; \
+ s2650c->iar = (s2650c->iar + 1) & PMSK; \
} \
- vector = (*S.irq_callback)(S.device, 0) & 0xff; \
+ vector = (*s2650c->irq_callback)(s2650c->device, 0) & 0xff; \
/* build effective address within first 8K page */ \
- S.ea = S2650_relative[vector] & PMSK; \
+ s2650c->ea = S2650_relative[vector] & PMSK; \
if (vector & 0x80) /* indirect bit set ? */ \
{ \
- int addr = S.ea; \
- s2650_ICount -= 6; \
+ int addr = s2650c->ea; \
+ s2650c->icount -= 6; \
/* build indirect 32K address */ \
- S.ea = RDMEM(addr) << 8; \
+ s2650c->ea = RDMEM(addr) << 8; \
if (!(++addr & PMSK)) addr -= PLEN; \
- S.ea = (S.ea + RDMEM(addr)) & AMSK; \
+ s2650c->ea = (s2650c->ea + RDMEM(addr)) & AMSK; \
} \
- LOG(("S2650 interrupt to $%04x\n", S.ea));\
- S.psu = (S.psu & ~SP) | ((S.psu + 1) & SP) | II; \
- S.ras[S.psu & SP] = S.page + S.iar; \
- S.page = S.ea & PAGE; \
- S.iar = S.ea & PMSK; \
+ LOG(("S2650 interrupt to $%04x\n", s2650c->ea));\
+ s2650c->psu = (s2650c->psu & ~SP) | ((s2650c->psu + 1) & SP) | II; \
+ s2650c->ras[s2650c->psu & SP] = s2650c->page + s2650c->iar; \
+ s2650c->page = s2650c->ea & PAGE; \
+ s2650c->iar = s2650c->ea & PMSK; \
} \
}
@@ -155,14 +154,14 @@ static void s2650_set_sense(int state);
* set condition code (zero,plus,minus) from result
***************************************************************/
#define SET_CC(result) \
- S.psl = (S.psl & ~CC) | ccc[result]
+ s2650c->psl = (s2650c->psl & ~CC) | ccc[result]
/***************************************************************
*
* set condition code (zero,plus,minus) and overflow
***************************************************************/
#define SET_CC_OVF(result,value) \
- S.psl = (S.psl & ~(OVF+CC)) | \
+ s2650c->psl = (s2650c->psl & ~(OVF+CC)) | \
ccc[result + (((value) & 0x80) << 1)]
#define SET_CC_OVF_ADD(result,value1,value2) SET_CC_OVF(result,~((value1) ^ (value2)) & ((value1) ^ (result)))
@@ -172,10 +171,10 @@ static void s2650_set_sense(int state);
* ROP
* read next opcode
***************************************************************/
-INLINE UINT8 ROP(void)
+INLINE UINT8 ROP(s2650_regs *s2650c)
{
- UINT8 result = memory_decrypted_read_byte(S.program, S.page + S.iar);
- S.iar = (S.iar + 1) & PMSK;
+ UINT8 result = memory_decrypted_read_byte(s2650c->program, s2650c->page + s2650c->iar);
+ s2650c->iar = (s2650c->iar + 1) & PMSK;
return result;
}
@@ -183,10 +182,10 @@ INLINE UINT8 ROP(void)
* ARG
* read next opcode argument
***************************************************************/
-INLINE UINT8 ARG(void)
+INLINE UINT8 ARG(s2650_regs *s2650c)
{
- UINT8 result = memory_raw_read_byte(S.program, S.page + S.iar);
- S.iar = (S.iar + 1) & PMSK;
+ UINT8 result = memory_raw_read_byte(s2650c->program, s2650c->page + s2650c->iar);
+ s2650c->iar = (s2650c->iar + 1) & PMSK;
return result;
}
@@ -194,7 +193,7 @@ INLINE UINT8 ARG(void)
* RDMEM
* read memory byte from addr
***************************************************************/
-#define RDMEM(addr) memory_read_byte_8le(S.program, addr)
+#define RDMEM(addr) memory_read_byte_8le(s2650c->program, addr)
/***************************************************************
* handy table to build PC relative offsets
@@ -226,16 +225,16 @@ static const int S2650_relative[0x100] =
***************************************************************/
#define _REL_EA(page) \
{ \
- UINT8 hr = ARG(); /* get 'holding register' */ \
+ UINT8 hr = ARG(s2650c); /* get 'holding register' */ \
/* build effective address within current 8K page */ \
- S.ea = page + ((S.iar + S2650_relative[hr]) & PMSK); \
+ s2650c->ea = page + ((s2650c->iar + S2650_relative[hr]) & PMSK); \
if (hr & 0x80) { /* indirect bit set ? */ \
- int addr = S.ea; \
- s2650_ICount -= 6; \
+ int addr = s2650c->ea; \
+ s2650c->icount -= 6; \
/* build indirect 32K address */ \
- S.ea = RDMEM(addr) << 8; \
+ s2650c->ea = RDMEM(addr) << 8; \
if( (++addr & PMSK) == 0 ) addr -= PLEN; /* page wrap */\
- S.ea = (S.ea + RDMEM(addr)) & AMSK; \
+ s2650c->ea = (s2650c->ea + RDMEM(addr)) & AMSK; \
} \
}
@@ -245,16 +244,16 @@ static const int S2650_relative[0x100] =
***************************************************************/
#define _REL_ZERO(page) \
{ \
- UINT8 hr = ARG(); /* get 'holding register' */ \
+ UINT8 hr = ARG(s2650c); /* get 'holding register' */ \
/* build effective address from 0 */ \
- S.ea = (S2650_relative[hr] & PMSK); \
+ s2650c->ea = (S2650_relative[hr] & PMSK); \
if (hr & 0x80) { /* indirect bit set ? */ \
- int addr = S.ea; \
- s2650_ICount -= 6; \
+ int addr = s2650c->ea; \
+ s2650c->icount -= 6; \
/* build indirect 32K address */ \
- S.ea = RDMEM(addr) << 8; \
+ s2650c->ea = RDMEM(addr) << 8; \
if( (++addr & PMSK) == 0 ) addr -= PLEN; /* page wrap */\
- S.ea = (S.ea + RDMEM(addr)) & AMSK; \
+ s2650c->ea = (s2650c->ea + RDMEM(addr)) & AMSK; \
} \
}
@@ -265,37 +264,37 @@ static const int S2650_relative[0x100] =
#define _ABS_EA() \
{ \
UINT8 hr, dr; \
- hr = ARG(); /* get 'holding register' */ \
- dr = ARG(); /* get 'data bus register' */ \
+ hr = ARG(s2650c); /* get 'holding register' */ \
+ dr = ARG(s2650c); /* get 'data bus register' */ \
/* build effective address within current 8K page */ \
- S.ea = S.page + (((hr << 8) + dr) & PMSK); \
+ s2650c->ea = s2650c->page + (((hr << 8) + dr) & PMSK); \
/* indirect addressing ? */ \
if (hr & 0x80) { \
- int addr = S.ea; \
- s2650_ICount -= 6; \
+ int addr = s2650c->ea; \
+ s2650c->icount -= 6; \
/* build indirect 32K address */ \
/* build indirect 32K address */ \
- S.ea = RDMEM(addr) << 8; \
+ s2650c->ea = RDMEM(addr) << 8; \
if( (++addr & PMSK) == 0 ) addr -= PLEN; /* page wrap */\
- S.ea = (S.ea + RDMEM(addr)) & AMSK; \
+ s2650c->ea = (s2650c->ea + RDMEM(addr)) & AMSK; \
} \
/* check indexed addressing modes */ \
switch (hr & 0x60) { \
case 0x00: /* not indexed */ \
break; \
case 0x20: /* auto increment indexed */ \
- S.reg[S.r] += 1; \
- S.ea = (S.ea & PAGE)+((S.ea+S.reg[S.r]) & PMSK); \
- S.r = 0; /* absolute addressing reg is R0 */ \
+ s2650c->reg[s2650c->r] += 1; \
+ s2650c->ea = (s2650c->ea & PAGE)+((s2650c->ea+s2650c->reg[s2650c->r]) & PMSK); \
+ s2650c->r = 0; /* absolute addressing reg is R0 */ \
break; \
case 0x40: /* auto decrement indexed */ \
- S.reg[S.r] -= 1; \
- S.ea = (S.ea & PAGE)+((S.ea+S.reg[S.r]) & PMSK); \
- S.r = 0; /* absolute addressing reg is R0 */ \
+ s2650c->reg[s2650c->r] -= 1; \
+ s2650c->ea = (s2650c->ea & PAGE)+((s2650c->ea+s2650c->reg[s2650c->r]) & PMSK); \
+ s2650c->r = 0; /* absolute addressing reg is R0 */ \
break; \
case 0x60: /* indexed */ \
- S.ea = (S.ea & PAGE)+((S.ea+S.reg[S.r]) & PMSK); \
- S.r = 0; /* absolute addressing reg is R0 */ \
+ s2650c->ea = (s2650c->ea & PAGE)+((s2650c->ea+s2650c->reg[s2650c->r]) & PMSK); \
+ s2650c->r = 0; /* absolute addressing reg is R0 */ \
break; \
} \
}
@@ -307,18 +306,18 @@ static const int S2650_relative[0x100] =
#define _BRA_EA() \
{ \
UINT8 hr, dr; \
- hr = ARG(); /* get 'holding register' */ \
- dr = ARG(); /* get 'data bus register' */ \
+ hr = ARG(s2650c); /* get 'holding register' */ \
+ dr = ARG(s2650c); /* get 'data bus register' */ \
/* build address in 32K address space */ \
- S.ea = ((hr << 8) + dr) & AMSK; \
+ s2650c->ea = ((hr << 8) + dr) & AMSK; \
/* indirect addressing ? */ \
if (hr & 0x80) { \
- int addr = S.ea; \
- s2650_ICount -= 6; \
+ int addr = s2650c->ea; \
+ s2650c->icount -= 6; \
/* build indirect 32K address */ \
- S.ea = RDMEM(addr) << 8; \
+ s2650c->ea = RDMEM(addr) << 8; \
if( (++addr & PMSK) == 0 ) addr -= PLEN; /* page wrap */\
- S.ea = (S.ea + RDMEM(addr)) & AMSK; \
+ s2650c->ea = (s2650c->ea + RDMEM(addr)) & AMSK; \
} \
}
@@ -330,15 +329,15 @@ static const int S2650_relative[0x100] =
#define SWAP_REGS \
{ \
UINT8 tmp; \
- tmp = S.reg[1]; \
- S.reg[1] = S.reg[4]; \
- S.reg[4] = tmp; \
- tmp = S.reg[2]; \
- S.reg[2] = S.reg[5]; \
- S.reg[5] = tmp; \
- tmp = S.reg[3]; \
- S.reg[3] = S.reg[6]; \
- S.reg[6] = tmp; \
+ tmp = s2650c->reg[1]; \
+ s2650c->reg[1] = s2650c->reg[4]; \
+ s2650c->reg[4] = tmp; \
+ tmp = s2650c->reg[2]; \
+ s2650c->reg[2] = s2650c->reg[5]; \
+ s2650c->reg[5] = tmp; \
+ tmp = s2650c->reg[3]; \
+ s2650c->reg[3] = s2650c->reg[6]; \
+ s2650c->reg[6] = tmp; \
}
/***************************************************************
@@ -349,11 +348,11 @@ static const int S2650_relative[0x100] =
{ \
if (cond) \
{ \
- REL_EA( S.page ); \
- S.page = S.ea & PAGE; \
- S.iar = S.ea & PMSK; \
- change_pc(S.ea); \
- } else S.iar = (S.iar + 1) & PMSK; \
+ REL_EA( s2650c->page ); \
+ s2650c->page = s2650c->ea & PAGE; \
+ s2650c->iar = s2650c->ea & PMSK; \
+ change_pc(s2650c->ea); \
+ } else s2650c->iar = (s2650c->iar + 1) & PMSK; \
}
/***************************************************************
@@ -363,9 +362,9 @@ static const int S2650_relative[0x100] =
#define M_ZBRR() \
{ \
REL_ZERO( 0 ); \
- S.page = S.ea & PAGE; \
- S.iar = S.ea & PMSK; \
- change_pc(S.ea); \
+ s2650c->page = s2650c->ea & PAGE; \
+ s2650c->iar = s2650c->ea & PMSK; \
+ change_pc(s2650c->ea); \
}
/***************************************************************
@@ -377,10 +376,10 @@ static const int S2650_relative[0x100] =
if( cond ) \
{ \
BRA_EA(); \
- S.page = S.ea & PAGE; \
- S.iar = S.ea & PMSK; \
- change_pc(S.ea); \
- } else S.iar = (S.iar + 2) & PMSK; \
+ s2650c->page = s2650c->ea & PAGE; \
+ s2650c->iar = s2650c->ea & PMSK; \
+ change_pc(s2650c->ea); \
+ } else s2650c->iar = (s2650c->iar + 2) & PMSK; \
}
/***************************************************************
@@ -390,10 +389,10 @@ static const int S2650_relative[0x100] =
#define M_BXA() \
{ \
BRA_EA(); \
- S.ea = (S.ea + S.reg[3]) & AMSK; \
- S.page = S.ea & PAGE; \
- S.iar = S.ea & PMSK; \
- change_pc(S.ea); \
+ s2650c->ea = (s2650c->ea + s2650c->reg[3]) & AMSK; \
+ s2650c->page = s2650c->ea & PAGE; \
+ s2650c->iar = s2650c->ea & PMSK; \
+ change_pc(s2650c->ea); \
}
/***************************************************************
@@ -404,13 +403,13 @@ static const int S2650_relative[0x100] =
{ \
if( cond ) \
{ \
- REL_EA(S.page); \
- S.psu = (S.psu & ~SP) | ((S.psu + 1) & SP); \
- S.ras[S.psu & SP] = S.page + S.iar; \
- S.page = S.ea & PAGE; \
- S.iar = S.ea & PMSK; \
- change_pc(S.ea); \
- } else S.iar = (S.iar + 1) & PMSK; \
+ REL_EA(s2650c->page); \
+ s2650c->psu = (s2650c->psu & ~SP) | ((s2650c->psu + 1) & SP); \
+ s2650c->ras[s2650c->psu & SP] = s2650c->page + s2650c->iar; \
+ s2650c->page = s2650c->ea & PAGE; \
+ s2650c->iar = s2650c->ea & PMSK; \
+ change_pc(s2650c->ea); \
+ } else s2650c->iar = (s2650c->iar + 1) & PMSK; \
}
/***************************************************************
@@ -420,11 +419,11 @@ static const int S2650_relative[0x100] =
#define M_ZBSR() \
{ \
REL_ZERO(0); \
- S.psu = (S.psu & ~SP) | ((S.psu + 1) & SP); \
- S.ras[S.psu & SP] = S.page + S.iar; \
- S.page = S.ea & PAGE; \
- S.iar = S.ea & PMSK; \
- change_pc(S.ea); \
+ s2650c->psu = (s2650c->psu & ~SP) | ((s2650c->psu + 1) & SP); \
+ s2650c->ras[s2650c->psu & SP] = s2650c->page + s2650c->iar; \
+ s2650c->page = s2650c->ea & PAGE; \
+ s2650c->iar = s2650c->ea & PMSK; \
+ change_pc(s2650c->ea); \
}
/***************************************************************
@@ -436,12 +435,12 @@ static const int S2650_relative[0x100] =
if( cond ) \
{ \
BRA_EA(); \
- S.psu = (S.psu & ~SP) | ((S.psu + 1) & SP); \
- S.ras[S.psu & SP] = S.page + S.iar; \
- S.page = S.ea & PAGE; \
- S.iar = S.ea & PMSK; \
- change_pc(S.ea); \
- } else S.iar = (S.iar + 2) & PMSK; \
+ s2650c->psu = (s2650c->psu & ~SP) | ((s2650c->psu + 1) & SP); \
+ s2650c->ras[s2650c->psu & SP] = s2650c->page + s2650c->iar; \
+ s2650c->page = s2650c->ea & PAGE; \
+ s2650c->iar = s2650c->ea & PMSK; \
+ change_pc(s2650c->ea); \
+ } else s2650c->iar = (s2650c->iar + 2) & PMSK; \
}
/***************************************************************
@@ -451,12 +450,12 @@ static const int S2650_relative[0x100] =
#define M_BSXA() \
{ \
BRA_EA(); \
- S.ea = (S.ea + S.reg[3]) & AMSK; \
- S.psu = (S.psu & ~SP) | ((S.psu + 1) & SP); \
- S.ras[S.psu & SP] = S.page + S.iar; \
- S.page = S.ea & PAGE; \
- S.iar = S.ea & PMSK; \
- change_pc(S.ea); \
+ s2650c->ea = (s2650c->ea + s2650c->reg[3]) & AMSK; \
+ s2650c->psu = (s2650c->psu & ~SP) | ((s2650c->psu + 1) & SP); \
+ s2650c->ras[s2650c->psu & SP] = s2650c->page + s2650c->iar; \
+ s2650c->page = s2650c->ea & PAGE; \
+ s2650c->iar = s2650c->ea & PMSK; \
+ change_pc(s2650c->ea); \
}
/***************************************************************
@@ -467,12 +466,12 @@ static const int S2650_relative[0x100] =
{ \
if( cond ) \
{ \
- s2650_ICount -= 6; \
- S.ea = S.ras[S.psu & SP]; \
- S.psu = (S.psu & ~SP) | ((S.psu - 1) & SP); \
- S.page = S.ea & PAGE; \
- S.iar = S.ea & PMSK; \
- change_pc(S.ea); \
+ s2650c->icount -= 6; \
+ s2650c->ea = s2650c->ras[s2650c->psu & SP]; \
+ s2650c->psu = (s2650c->psu & ~SP) | ((s2650c->psu - 1) & SP); \
+ s2650c->page = s2650c->ea & PAGE; \
+ s2650c->iar = s2650c->ea & PMSK; \
+ change_pc(s2650c->ea); \
} \
}
@@ -486,12 +485,12 @@ static const int S2650_relative[0x100] =
{ \
if( cond ) \
{ \
- S.ea = S.ras[S.psu & SP]; \
- S.psu = (S.psu & ~SP) | ((S.psu - 1) & SP); \
- S.page = S.ea & PAGE; \
- S.iar = S.ea & PMSK; \
- change_pc(S.ea); \
- S.psu &= ~II; \
+ s2650c->ea = s2650c->ras[s2650c->psu & SP]; \
+ s2650c->psu = (s2650c->psu & ~SP) | ((s2650c->psu - 1) & SP); \
+ s2650c->page = s2650c->ea & PAGE; \
+ s2650c->iar = s2650c->ea & PMSK; \
+ change_pc(s2650c->ea); \
+ s2650c->psu &= ~II; \
CHECK_IRQ_LINE; \
} \
}
@@ -511,7 +510,7 @@ static const int S2650_relative[0x100] =
* Store source register to memory addr (CC unchanged)
***************************************************************/
#define M_STR(address,source) \
- memory_write_byte_8le(S.program, address, source)
+ memory_write_byte_8le(s2650c->program, address, source)
/***************************************************************
* M_AND
@@ -553,11 +552,11 @@ static const int S2650_relative[0x100] =
UINT8 source = _source; \
UINT8 before = dest; \
/* add source; carry only if WC is set */ \
- UINT16 res = dest + source + ((S.psl >> 3) & S.psl & C); \
- S.psl &= ~(C | OVF | IDC); \
- if(res & 0x100) S.psl |= C; \
+ UINT16 res = dest + source + ((s2650c->psl >> 3) & s2650c->psl & C); \
+ s2650c->psl &= ~(C | OVF | IDC); \
+ if(res & 0x100) s2650c->psl |= C; \
dest = res & 0xff; \
- if( (dest & 15) < (before & 15) ) S.psl |= IDC; \
+ if( (dest & 15) < (before & 15) ) s2650c->psl |= IDC; \
SET_CC_OVF_ADD(dest,before,source); \
}
@@ -571,11 +570,11 @@ static const int S2650_relative[0x100] =
UINT8 source = _source; \
UINT8 before = dest; \
/* subtract source; borrow only if WC is set */ \
- UINT16 res = dest - source - ((S.psl >> 3) & (S.psl ^ C) & C); \
- S.psl &= ~(C | OVF | IDC); \
- if((res & 0x100)==0) S.psl |= C; \
+ UINT16 res = dest - source - ((s2650c->psl >> 3) & (s2650c->psl ^ C) & C); \
+ s2650c->psl &= ~(C | OVF | IDC); \
+ if((res & 0x100)==0) s2650c->psl |= C; \
dest = res & 0xff; \
- if( (dest & 15) <= (before & 15) ) S.psl |= IDC; \
+ if( (dest & 15) <= (before & 15) ) s2650c->psl |= IDC; \
SET_CC_OVF_SUB(dest,before,source); \
}
@@ -587,12 +586,12 @@ static const int S2650_relative[0x100] =
#define M_COM(reg,val) \
{ \
int d; \
- S.psl &= ~CC; \
- if (S.psl & COM) d = (UINT8)reg - (UINT8)val; \
+ s2650c->psl &= ~CC; \
+ if (s2650c->psl & COM) d = (UINT8)reg - (UINT8)val; \
else d = (INT8)reg - (INT8)val; \
- if( d < 0 ) S.psl |= 0x80; \
+ if( d < 0 ) s2650c->psl |= 0x80; \
else \
- if( d > 0 ) S.psl |= 0x40; \
+ if( d > 0 ) s2650c->psl |= 0x40; \
}
/***************************************************************
@@ -601,8 +600,8 @@ static const int S2650_relative[0x100] =
***************************************************************/
#define M_DAR(dest) \
{ \
- if ((S.psl & C) == 0) dest += 0xA0; \
- if ((S.psl & IDC) == 0) dest = (dest & 0xF0) | ((dest + 0x0A) & 0x0F);\
+ if ((s2650c->psl & C) == 0) dest += 0xA0; \
+ if ((s2650c->psl & IDC) == 0) dest = (dest & 0xF0) | ((dest + 0x0A) & 0x0F);\
}
/***************************************************************
@@ -613,19 +612,19 @@ static const int S2650_relative[0x100] =
#define M_RRL(dest) \
{ \
UINT8 before = dest; \
- if( S.psl & WC ) \
+ if( s2650c->psl & WC ) \
{ \
- UINT8 c = S.psl & C; \
- S.psl &= ~(C + IDC); \
+ UINT8 c = s2650c->psl & C; \
+ s2650c->psl &= ~(C + IDC); \
dest = (before << 1) | c; \
- S.psl |= (before >> 7) + (dest & IDC); \
+ s2650c->psl |= (before >> 7) + (dest & IDC); \
} \
else \
{ \
dest = (before << 1) | (before >> 7); \
} \
SET_CC(dest); \
- S.psl = (S.psl & ~OVF) | (((dest ^ before) >> 5) & OVF); \
+ s2650c->psl = (s2650c->psl & ~OVF) | (((dest ^ before) >> 5) & OVF); \
}
/***************************************************************
@@ -636,15 +635,15 @@ static const int S2650_relative[0x100] =
#define M_RRR(dest) \
{ \
UINT8 before = dest; \
- if (S.psl & WC) \
+ if (s2650c->psl & WC) \
{ \
- UINT8 c = S.psl & C; \
- S.psl &= ~(C + IDC); \
+ UINT8 c = s2650c->psl & C; \
+ s2650c->psl &= ~(C + IDC); \
dest = (before >> 1) | (c << 7); \
- S.psl |= (before & C) + (dest & IDC); \
+ s2650c->psl |= (before & C) + (dest & IDC); \
} else dest = (before >> 1) | (before << 7); \
SET_CC(dest); \
- S.psl = (S.psl & ~OVF) | (((dest ^ before) >> 5) & OVF); \
+ s2650c->psl = (s2650c->psl & ~OVF) | (((dest ^ before) >> 5) & OVF); \
}
// bxd() not necessary
@@ -656,7 +655,7 @@ static const int S2650_relative[0x100] =
***************************************************************/
#define M_SPSU() \
{ \
- R0 = ((S.psu & ~PSU34) | (memory_read_byte_8le(S.io, S2650_SENSE_PORT) & SI)); \
+ R0 = ((s2650c->psu & ~PSU34) | (memory_read_byte_8le(s2650c->io, S2650_SENSE_PORT) & SI)); \
SET_CC(R0); \
}
@@ -666,7 +665,7 @@ static const int S2650_relative[0x100] =
***************************************************************/
#define M_SPSL() \
{ \
- R0 = S.psl; \
+ R0 = s2650c->psl; \
SET_CC(R0); \
}
@@ -676,8 +675,8 @@ static const int S2650_relative[0x100] =
***************************************************************/
#define M_CPSU() \
{ \
- UINT8 cpsu = ARG(); \
- S.psu = S.psu & ~cpsu; \
+ UINT8 cpsu = ARG(s2650c); \
+ s2650c->psu = s2650c->psu & ~cpsu; \
CHECK_IRQ_LINE; \
}
@@ -687,11 +686,11 @@ static const int S2650_relative[0x100] =
***************************************************************/
#define M_CPSL() \
{ \
- UINT8 cpsl = ARG(); \
+ UINT8 cpsl = ARG(s2650c); \
/* select other register set now ? */ \
- if( (cpsl & RS) && (S.psl & RS) ) \
+ if( (cpsl & RS) && (s2650c->psl & RS) ) \
SWAP_REGS; \
- S.psl = S.psl & ~cpsl; \
+ s2650c->psl = s2650c->psl & ~cpsl; \
CHECK_IRQ_LINE; \
}
@@ -702,8 +701,8 @@ static const int S2650_relative[0x100] =
***************************************************************/
#define M_PPSU() \
{ \
- UINT8 ppsu = (ARG() & ~PSU34) & ~SI; \
- S.psu = S.psu | ppsu; \
+ UINT8 ppsu = (ARG(s2650c) & ~PSU34) & ~SI; \
+ s2650c->psu = s2650c->psu | ppsu; \
}
/***************************************************************
@@ -712,11 +711,11 @@ static const int S2650_relative[0x100] =
***************************************************************/
#define M_PPSL() \
{ \
- UINT8 ppsl = ARG(); \
+ UINT8 ppsl = ARG(s2650c); \
/* select 2nd register set now ? */ \
- if ((ppsl & RS) && !(S.psl & RS)) \
+ if ((ppsl & RS) && !(s2650c->psl & RS)) \
SWAP_REGS; \
- S.psl = S.psl | ppsl; \
+ s2650c->psl = s2650c->psl | ppsl; \
}
/***************************************************************
@@ -725,11 +724,11 @@ static const int S2650_relative[0x100] =
***************************************************************/
#define M_TPSU() \
{ \
- UINT8 tpsu = ARG(); \
- UINT8 rpsu = (S.psu | (memory_read_byte_8le(S.io, S2650_SENSE_PORT) & SI)); \
- S.psl &= ~CC; \
+ UINT8 tpsu = ARG(s2650c); \
+ UINT8 rpsu = (s2650c->psu | (memory_read_byte_8le(s2650c->io, S2650_SENSE_PORT) & SI)); \
+ s2650c->psl &= ~CC; \
if( (rpsu & tpsu) != tpsu ) \
- S.psl |= 0x80; \
+ s2650c->psl |= 0x80; \
}
/***************************************************************
@@ -738,11 +737,11 @@ static const int S2650_relative[0x100] =
***************************************************************/
#define M_TPSL() \
{ \
- UINT8 tpsl = ARG(); \
- if( (S.psl & tpsl) != tpsl ) \
- S.psl = (S.psl & ~CC) | 0x80; \
+ UINT8 tpsl = ARG(s2650c); \
+ if( (s2650c->psl & tpsl) != tpsl ) \
+ s2650c->psl = (s2650c->psl & ~CC) | 0x80; \
else \
- S.psl &= ~CC; \
+ s2650c->psl &= ~CC; \
}
/***************************************************************
@@ -751,10 +750,10 @@ static const int S2650_relative[0x100] =
***************************************************************/
#define M_TMI(value) \
{ \
- UINT8 tmi = ARG(); \
- S.psl &= ~CC; \
+ UINT8 tmi = ARG(s2650c); \
+ s2650c->psl &= ~CC; \
if( (value & tmi) != tmi ) \
- S.psl |= 0x80; \
+ s2650c->psl |= 0x80; \
}
#if INLINE_EA
@@ -771,35 +770,46 @@ static void BRA_EA(void) _BRA_EA()
static CPU_INIT( s2650 )
{
- S.irq_callback = irqcallback;
- S.device = device;
- S.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
- S.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
-
- state_save_register_item("s2650", device->tag, 0, S.ppc);
- state_save_register_item("s2650", device->tag, 0, S.page);
- state_save_register_item("s2650", device->tag, 0, S.iar);
- state_save_register_item("s2650", device->tag, 0, S.ea);
- state_save_register_item("s2650", device->tag, 0, S.psl);
- state_save_register_item("s2650", device->tag, 0, S.psu);
- state_save_register_item("s2650", device->tag, 0, S.r);
- state_save_register_item_array("s2650", device->tag, 0, S.reg);
- state_save_register_item("s2650", device->tag, 0, S.halt);
- state_save_register_item("s2650", device->tag, 0, S.ir);
- state_save_register_item_array("s2650", device->tag, 0, S.ras);
- state_save_register_item("s2650", device->tag, 0, S.irq_state);
+ s2650_regs *s2650c = device->token;
+
+ s2650c->irq_callback = irqcallback;
+ s2650c->device = device;
+ s2650c->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ s2650c->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
+
+ state_save_register_item("s2650", device->tag, 0, s2650c->ppc);
+ state_save_register_item("s2650", device->tag, 0, s2650c->page);
+ state_save_register_item("s2650", device->tag, 0, s2650c->iar);
+ state_save_register_item("s2650", device->tag, 0, s2650c->ea);
+ state_save_register_item("s2650", device->tag, 0, s2650c->psl);
+ state_save_register_item("s2650", device->tag, 0, s2650c->psu);
+ state_save_register_item("s2650", device->tag, 0, s2650c->r);
+ state_save_register_item_array("s2650", device->tag, 0, s2650c->reg);
+ state_save_register_item("s2650", device->tag, 0, s2650c->halt);
+ state_save_register_item("s2650", device->tag, 0, s2650c->ir);
+ state_save_register_item_array("s2650", device->tag, 0, s2650c->ras);
+ state_save_register_item("s2650", device->tag, 0, s2650c->irq_state);
}
static CPU_RESET( s2650 )
{
- cpu_irq_callback save_irqcallback = S.irq_callback;
- memset(&S, 0, sizeof(S));
- S.irq_callback = save_irqcallback;
- S.device = device;
- S.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
- S.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
- S.psl = COM | WC;
- S.psu = 0;
+ s2650_regs *s2650c = device->token;
+
+ s2650c->ppc = 0;
+ s2650c->page = 0,
+ s2650c->iar = 0;
+ s2650c->ea = 0;
+ s2650c->r = 0;
+ s2650c->halt = 0;
+ s2650c->ir = 0;
+ memset(s2650c->reg, 0, sizeof(s2650c->reg));
+ memset(s2650c->ras, 0, sizeof(s2650c->ras));
+
+ s2650c->device = device;
+ s2650c->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+ s2650c->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
+ s2650c->psl = COM | WC;
+ s2650c->psu = 0;
}
static CPU_EXIT( s2650 )
@@ -809,153 +819,146 @@ static CPU_EXIT( s2650 )
static CPU_GET_CONTEXT( s2650 )
{
- if( dst )
- *(s2650_Regs*)dst = S;
}
static CPU_SET_CONTEXT( s2650 )
{
- if( src )
- {
- S = *(s2650_Regs*)src;
- S.page = S.page & PAGE;
- S.iar = S.iar & PMSK;
- change_pc(S.page + S.iar);
- }
}
-static void set_irq_line(int irqline, int state)
+static void set_irq_line(s2650_regs *s2650c, int irqline, int state)
{
if (irqline == 1)
{
if (state == CLEAR_LINE)
- s2650_set_sense(0);
+ s2650_set_sense(s2650c, 0);
else
- s2650_set_sense(1);
+ s2650_set_sense(s2650c, 1);
return;
}
- S.irq_state = state;
+ s2650c->irq_state = state;
CHECK_IRQ_LINE;
}
-static void s2650_set_flag(int state)
+static void s2650_set_flag(s2650_regs *s2650c, int state)
{
if (state)
- S.psu |= FO;
+ s2650c->psu |= FO;
else
- S.psu &= ~FO;
+ s2650c->psu &= ~FO;
}
-static int s2650_get_flag(void)
+static int s2650_get_flag(s2650_regs *s2650c)
{
- return (S.psu & FO) ? 1 : 0;
+ return (s2650c->psu & FO) ? 1 : 0;
}
-static void s2650_set_sense(int state)
+static void s2650_set_sense(s2650_regs *s2650c, int state)
{
if (state)
- S.psu |= SI;
+ s2650c->psu |= SI;
else
- S.psu &= ~SI;
+ s2650c->psu &= ~SI;
}
-static int s2650_get_sense(void)
+static int s2650_get_sense(s2650_regs *s2650c)
{
/* OR'd with Input to allow for external connections */
- return (((S.psu & SI) ? 1 : 0) | ((memory_read_byte_8le(S.io, S2650_SENSE_PORT) & SI) ? 1 : 0));
+ return (((s2650c->psu & SI) ? 1 : 0) | ((memory_read_byte_8le(s2650c->io, S2650_SENSE_PORT) & SI) ? 1 : 0));
}
static CPU_EXECUTE( s2650 )
{
- s2650_ICount = cycles;
+ s2650_regs *s2650c = device->token;
+
+ s2650c->icount = cycles;
do
{
- S.ppc = S.page + S.iar;
+ s2650c->ppc = s2650c->page + s2650c->iar;
- debugger_instruction_hook(device, S.page + S.iar);
+ debugger_instruction_hook(device, s2650c->page + s2650c->iar);
- S.ir = ROP();
- S.r = S.ir & 3; /* register / value */
- switch (S.ir) {
+ s2650c->ir = ROP(s2650c);
+ s2650c->r = s2650c->ir & 3; /* register / value */
+ switch (s2650c->ir) {
case 0x00: /* LODZ,0 */
case 0x01: /* LODZ,1 */
case 0x02: /* LODZ,2 */
case 0x03: /* LODZ,3 */
- s2650_ICount -= 6;
- M_LOD( R0, S.reg[S.r] );
+ s2650c->icount -= 6;
+ M_LOD( R0, s2650c->reg[s2650c->r] );
break;
case 0x04: /* LODI,0 v */
case 0x05: /* LODI,1 v */
case 0x06: /* LODI,2 v */
case 0x07: /* LODI,3 v */
- s2650_ICount -= 6;
- M_LOD( S.reg[S.r], ARG() );
+ s2650c->icount -= 6;
+ M_LOD( s2650c->reg[s2650c->r], ARG(s2650c) );
break;
case 0x08: /* LODR,0 (*)a */
case 0x09: /* LODR,1 (*)a */
case 0x0a: /* LODR,2 (*)a */
case 0x0b: /* LODR,3 (*)a */
- s2650_ICount -= 9;
- REL_EA( S.page );
- M_LOD( S.reg[S.r], RDMEM(S.ea) );
+ s2650c->icount -= 9;
+ REL_EA( s2650c->page );
+ M_LOD( s2650c->reg[s2650c->r], RDMEM(s2650c->ea) );
break;
case 0x0c: /* LODA,0 (*)a(,X) */
case 0x0d: /* LODA,1 (*)a(,X) */
case 0x0e: /* LODA,2 (*)a(,X) */
case 0x0f: /* LODA,3 (*)a(,X) */
- s2650_ICount -= 12;
+ s2650c->icount -= 12;
ABS_EA();
- M_LOD( S.reg[S.r], RDMEM(S.ea) );
+ M_LOD( s2650c->reg[s2650c->r], RDMEM(s2650c->ea) );
break;
case 0x10: /* illegal */
case 0x11: /* illegal */
- s2650_ICount -= 7;
+ s2650c->icount -= 7;
break;
case 0x12: /* SPSU */
- s2650_ICount -= 6;
+ s2650c->icount -= 6;
M_SPSU();
break;
case 0x13: /* SPSL */
- s2650_ICount -= 6;
+ s2650c->icount -= 6;
M_SPSL();
break;
case 0x14: /* RETC,0 (zero) */
case 0x15: /* RETC,1 (plus) */
case 0x16: /* RETC,2 (minus) */
- s2650_ICount -= 9; /* +2 cycles if condition is true */
- M_RET( (S.psl >> 6) == S.r );
+ s2650c->icount -= 9; /* +2 cycles if condition is true */
+ M_RET( (s2650c->psl >> 6) == s2650c->r );
break;
case 0x17: /* RETC,3 (always) */
- s2650_ICount -= 9; /* +2 cycles if condition is true */
+ s2650c->icount -= 9; /* +2 cycles if condition is true */
M_RET( 1 );
break;
case 0x18: /* BCTR,0 (*)a */
case 0x19: /* BCTR,1 (*)a */
case 0x1a: /* BCTR,2 (*)a */
- s2650_ICount -= 9;
- M_BRR( (S.psl >> 6) == S.r );
+ s2650c->icount -= 9;
+ M_BRR( (s2650c->psl >> 6) == s2650c->r );
break;
case 0x1b: /* BCTR,3 (*)a */
- s2650_ICount -= 9;
+ s2650c->icount -= 9;
M_BRR( 1 );
break;
case 0x1c: /* BCTA,0 (*)a */
case 0x1d: /* BCTA,1 (*)a */
case 0x1e: /* BCTA,2 (*)a */
- s2650_ICount -= 9;
- M_BRA( (S.psl >> 6) == S.r );
+ s2650c->icount -= 9;
+ M_BRA( (s2650c->psl >> 6) == s2650c->r );
break;
case 0x1f: /* BCTA,3 (*)a */
- s2650_ICount -= 9;
+ s2650c->icount -= 9;
M_BRA( 1 );
break;
@@ -963,208 +966,208 @@ static CPU_EXECUTE( s2650 )
case 0x21: /* EORZ,1 */
case 0x22: /* EORZ,2 */
case 0x23: /* EORZ,3 */
- s2650_ICount -= 6;
- M_EOR( R0, S.reg[S.r] );
+ s2650c->icount -= 6;
+ M_EOR( R0, s2650c->reg[s2650c->r] );
break;
case 0x24: /* EORI,0 v */
case 0x25: /* EORI,1 v */
case 0x26: /* EORI,2 v */
case 0x27: /* EORI,3 v */
- s2650_ICount -= 6;
- M_EOR( S.reg[S.r], ARG() );
+ s2650c->icount -= 6;
+ M_EOR( s2650c->reg[s2650c->r], ARG(s2650c) );
break;
case 0x28: /* EORR,0 (*)a */
case 0x29: /* EORR,1 (*)a */
case 0x2a: /* EORR,2 (*)a */
case 0x2b: /* EORR,3 (*)a */
- s2650_ICount -= 9;
- REL_EA( S.page );
- M_EOR( S.reg[S.r], RDMEM(S.ea) );
+ s2650c->icount -= 9;
+ REL_EA( s2650c->page );
+ M_EOR( s2650c->reg[s2650c->r], RDMEM(s2650c->ea) );
break;
case 0x2c: /* EORA,0 (*)a(,X) */
case 0x2d: /* EORA,1 (*)a(,X) */
case 0x2e: /* EORA,2 (*)a(,X) */
case 0x2f: /* EORA,3 (*)a(,X) */
- s2650_ICount -= 12;
+ s2650c->icount -= 12;
ABS_EA();
- M_EOR( S.reg[S.r], RDMEM(S.ea) );
+ M_EOR( s2650c->reg[s2650c->r], RDMEM(s2650c->ea) );
break;
case 0x30: /* REDC,0 */
case 0x31: /* REDC,1 */
case 0x32: /* REDC,2 */
case 0x33: /* REDC,3 */
- s2650_ICount -= 6;
- S.reg[S.r] = memory_read_byte_8le(S.io, S2650_CTRL_PORT);
- SET_CC( S.reg[S.r] );
+ s2650c->icount -= 6;
+ s2650c->reg[s2650c->r] = memory_read_byte_8le(s2650c->io, S2650_CTRL_PORT);
+ SET_CC( s2650c->reg[s2650c->r] );
break;
case 0x34: /* RETE,0 */
case 0x35: /* RETE,1 */
case 0x36: /* RETE,2 */
- s2650_ICount -= 9;
- M_RETE( (S.psl >> 6) == S.r );
+ s2650c->icount -= 9;
+ M_RETE( (s2650c->psl >> 6) == s2650c->r );
break;
case 0x37: /* RETE,3 */
- s2650_ICount -= 9;
+ s2650c->icount -= 9;
M_RETE( 1 );
break;
case 0x38: /* BSTR,0 (*)a */
case 0x39: /* BSTR,1 (*)a */
case 0x3a: /* BSTR,2 (*)a */
- s2650_ICount -= 9;
- M_BSR( (S.psl >> 6) == S.r );
+ s2650c->icount -= 9;
+ M_BSR( (s2650c->psl >> 6) == s2650c->r );
break;
case 0x3b: /* BSTR,R3 (*)a */
- s2650_ICount -= 9;
+ s2650c->icount -= 9;
M_BSR( 1 );
break;
case 0x3c: /* BSTA,0 (*)a */
case 0x3d: /* BSTA,1 (*)a */
case 0x3e: /* BSTA,2 (*)a */
- s2650_ICount -= 9;
- M_BSA( (S.psl >> 6) == S.r );
+ s2650c->icount -= 9;
+ M_BSA( (s2650c->psl >> 6) == s2650c->r );
break;
case 0x3f: /* BSTA,3 (*)a */
- s2650_ICount -= 9;
+ s2650c->icount -= 9;
M_BSA( 1 );
break;
case 0x40: /* HALT */
- s2650_ICount -= 6;
- S.iar = (S.iar - 1) & PMSK;
- S.halt = 1;
- if (s2650_ICount > 0)
- s2650_ICount = 0;
+ s2650c->icount -= 6;
+ s2650c->iar = (s2650c->iar - 1) & PMSK;
+ s2650c->halt = 1;
+ if (s2650c->icount > 0)
+ s2650c->icount = 0;
break;
case 0x41: /* ANDZ,1 */
case 0x42: /* ANDZ,2 */
case 0x43: /* ANDZ,3 */
- s2650_ICount -= 6;
- M_AND( R0, S.reg[S.r] );
+ s2650c->icount -= 6;
+ M_AND( R0, s2650c->reg[s2650c->r] );
break;
case 0x44: /* ANDI,0 v */
case 0x45: /* ANDI,1 v */
case 0x46: /* ANDI,2 v */
case 0x47: /* ANDI,3 v */
- s2650_ICount -= 6;
- M_AND( S.reg[S.r], ARG() );
+ s2650c->icount -= 6;
+ M_AND( s2650c->reg[s2650c->r], ARG(s2650c) );
break;
case 0x48: /* ANDR,0 (*)a */
case 0x49: /* ANDR,1 (*)a */
case 0x4a: /* ANDR,2 (*)a */
case 0x4b: /* ANDR,3 (*)a */
- s2650_ICount -= 9;
- REL_EA( S.page );
- M_AND( S.reg[S.r], RDMEM(S.ea) );
+ s2650c->icount -= 9;
+ REL_EA( s2650c->page );
+ M_AND( s2650c->reg[s2650c->r], RDMEM(s2650c->ea) );
break;
case 0x4c: /* ANDA,0 (*)a(,X) */
case 0x4d: /* ANDA,1 (*)a(,X) */
case 0x4e: /* ANDA,2 (*)a(,X) */
case 0x4f: /* ANDA,3 (*)a(,X) */
- s2650_ICount -= 12;
+ s2650c->icount -= 12;
ABS_EA();
- M_AND( S.reg[S.r], RDMEM(S.ea) );
+ M_AND( s2650c->reg[s2650c->r], RDMEM(s2650c->ea) );
break;
case 0x50: /* RRR,0 */
case 0x51: /* RRR,1 */
case 0x52: /* RRR,2 */
case 0x53: /* RRR,3 */
- s2650_ICount -= 6;
- M_RRR( S.reg[S.r] );
+ s2650c->icount -= 6;
+ M_RRR( s2650c->reg[s2650c->r] );
break;
case 0x54: /* REDE,0 v */
case 0x55: /* REDE,1 v */
case 0x56: /* REDE,2 v */
case 0x57: /* REDE,3 v */
- s2650_ICount -= 9;
- S.reg[S.r] = memory_read_byte_8le( S.io, ARG() );
- SET_CC(S.reg[S.r]);
+ s2650c->icount -= 9;
+ s2650c->reg[s2650c->r] = memory_read_byte_8le( s2650c->io, ARG(s2650c) );
+ SET_CC(s2650c->reg[s2650c->r]);
break;
case 0x58: /* BRNR,0 (*)a */
case 0x59: /* BRNR,1 (*)a */
case 0x5a: /* BRNR,2 (*)a */
case 0x5b: /* BRNR,3 (*)a */
- s2650_ICount -= 9;
- M_BRR( S.reg[S.r] );
+ s2650c->icount -= 9;
+ M_BRR( s2650c->reg[s2650c->r] );
break;
case 0x5c: /* BRNA,0 (*)a */
case 0x5d: /* BRNA,1 (*)a */
case 0x5e: /* BRNA,2 (*)a */
case 0x5f: /* BRNA,3 (*)a */
- s2650_ICount -= 9;
- M_BRA( S.reg[S.r] );
+ s2650c->icount -= 9;
+ M_BRA( s2650c->reg[s2650c->r] );
break;
case 0x60: /* IORZ,0 */
case 0x61: /* IORZ,1 */
case 0x62: /* IORZ,2 */
case 0x63: /* IORZ,3 */
- s2650_ICount -= 6;
- M_IOR( R0, S.reg[S.r] );
+ s2650c->icount -= 6;
+ M_IOR( R0, s2650c->reg[s2650c->r] );
break;
case 0x64: /* IORI,0 v */
case 0x65: /* IORI,1 v */
case 0x66: /* IORI,2 v */
case 0x67: /* IORI,3 v */
- s2650_ICount -= 6;
- M_IOR( S.reg[S.r], ARG() );
+ s2650c->icount -= 6;
+ M_IOR( s2650c->reg[s2650c->r], ARG(s2650c) );
break;
case 0x68: /* IORR,0 (*)a */
case 0x69: /* IORR,1 (*)a */
case 0x6a: /* IORR,2 (*)a */
case 0x6b: /* IORR,3 (*)a */
- s2650_ICount -= 9;
- REL_EA( S.page );
- M_IOR( S.reg[S. r],RDMEM(S.ea) );
+ s2650c->icount -= 9;
+ REL_EA( s2650c->page );
+ M_IOR( s2650c->reg[s2650c-> r],RDMEM(s2650c->ea) );
break;
case 0x6c: /* IORA,0 (*)a(,X) */
case 0x6d: /* IORA,1 (*)a(,X) */
case 0x6e: /* IORA,2 (*)a(,X) */
case 0x6f: /* IORA,3 (*)a(,X) */
- s2650_ICount -= 12;
+ s2650c->icount -= 12;
ABS_EA();
- M_IOR( S.reg[S.r], RDMEM(S.ea) );
+ M_IOR( s2650c->reg[s2650c->r], RDMEM(s2650c->ea) );
break;
case 0x70: /* REDD,0 */
case 0x71: /* REDD,1 */
case 0x72: /* REDD,2 */
case 0x73: /* REDD,3 */
- s2650_ICount -= 6;
- S.reg[S.r] = memory_read_byte_8le(S.io, S2650_DATA_PORT);
- SET_CC(S.reg[S.r]);
+ s2650c->icount -= 6;
+ s2650c->reg[s2650c->r] = memory_read_byte_8le(s2650c->io, S2650_DATA_PORT);
+ SET_CC(s2650c->reg[s2650c->r]);
break;
case 0x74: /* CPSU */
- s2650_ICount -= 9;
+ s2650c->icount -= 9;
M_CPSU();
break;
case 0x75: /* CPSL */
- s2650_ICount -= 9;
+ s2650c->icount -= 9;
M_CPSL();
break;
case 0x76: /* PPSU */
- s2650_ICount -= 9;
+ s2650c->icount -= 9;
M_PPSU();
break;
case 0x77: /* PPSL */
- s2650_ICount -= 9;
+ s2650c->icount -= 9;
M_PPSL();
break;
@@ -1172,95 +1175,95 @@ static CPU_EXECUTE( s2650 )
case 0x79: /* BSNR,1 (*)a */
case 0x7a: /* BSNR,2 (*)a */
case 0x7b: /* BSNR,3 (*)a */
- s2650_ICount -= 9;
- M_BSR( S.reg[S.r] );
+ s2650c->icount -= 9;
+ M_BSR( s2650c->reg[s2650c->r] );
break;
case 0x7c: /* BSNA,0 (*)a */
case 0x7d: /* BSNA,1 (*)a */
case 0x7e: /* BSNA,2 (*)a */
case 0x7f: /* BSNA,3 (*)a */
- s2650_ICount -= 9;
- M_BSA( S.reg[S.r] );
+ s2650c->icount -= 9;
+ M_BSA( s2650c->reg[s2650c->r] );
break;
case 0x80: /* ADDZ,0 */
case 0x81: /* ADDZ,1 */
case 0x82: /* ADDZ,2 */
case 0x83: /* ADDZ,3 */
- s2650_ICount -= 6;
- M_ADD( R0,S.reg[S.r] );
+ s2650c->icount -= 6;
+ M_ADD( R0,s2650c->reg[s2650c->r] );
break;
case 0x84: /* ADDI,0 v */
case 0x85: /* ADDI,1 v */
case 0x86: /* ADDI,2 v */
case 0x87: /* ADDI,3 v */
- s2650_ICount -= 6;
- M_ADD( S.reg[S.r], ARG() );
+ s2650c->icount -= 6;
+ M_ADD( s2650c->reg[s2650c->r], ARG(s2650c) );
break;
case 0x88: /* ADDR,0 (*)a */
case 0x89: /* ADDR,1 (*)a */
case 0x8a: /* ADDR,2 (*)a */
case 0x8b: /* ADDR,3 (*)a */
- s2650_ICount -= 9;
- REL_EA(S.page);
- M_ADD( S.reg[S.r], RDMEM(S.ea) );
+ s2650c->icount -= 9;
+ REL_EA(s2650c->page);
+ M_ADD( s2650c->reg[s2650c->r], RDMEM(s2650c->ea) );
break;
case 0x8c: /* ADDA,0 (*)a(,X) */
case 0x8d: /* ADDA,1 (*)a(,X) */
case 0x8e: /* ADDA,2 (*)a(,X) */
case 0x8f: /* ADDA,3 (*)a(,X) */
- s2650_ICount -= 12;
+ s2650c->icount -= 12;
ABS_EA();
- M_ADD( S.reg[S.r], RDMEM(S.ea) );
+ M_ADD( s2650c->reg[s2650c->r], RDMEM(s2650c->ea) );
break;
case 0x90: /* illegal */
case 0x91: /* illegal */
- s2650_ICount -= 7;
+ s2650c->icount -= 7;
break;
case 0x92: /* LPSU */
- s2650_ICount -= 6;
- S.psu = (R0 & ~PSU34) & ~SI;
+ s2650c->icount -= 6;
+ s2650c->psu = (R0 & ~PSU34) & ~SI;
break;
case 0x93: /* LPSL */
- s2650_ICount -= 6;
+ s2650c->icount -= 6;
/* change register set ? */
- if ((S.psl ^ R0) & RS)
+ if ((s2650c->psl ^ R0) & RS)
SWAP_REGS;
- S.psl = R0;
+ s2650c->psl = R0;
break;
case 0x94: /* DAR,0 */
case 0x95: /* DAR,1 */
case 0x96: /* DAR,2 */
case 0x97: /* DAR,3 */
- s2650_ICount -= 9;
- M_DAR( S.reg[S.r] );
+ s2650c->icount -= 9;
+ M_DAR( s2650c->reg[s2650c->r] );
break;
case 0x98: /* BCFR,0 (*)a */
case 0x99: /* BCFR,1 (*)a */
case 0x9a: /* BCFR,2 (*)a */
- s2650_ICount -= 9;
- M_BRR( (S.psl >> 6) != S.r );
+ s2650c->icount -= 9;
+ M_BRR( (s2650c->psl >> 6) != s2650c->r );
break;
case 0x9b: /* ZBRR (*)a */
- s2650_ICount -= 9;
+ s2650c->icount -= 9;
M_ZBRR();
break;
case 0x9c: /* BCFA,0 (*)a */
case 0x9d: /* BCFA,1 (*)a */
case 0x9e: /* BCFA,2 (*)a */
- s2650_ICount -= 9;
- M_BRA( (S.psl >> 6) != S.r );
+ s2650c->icount -= 9;
+ M_BRA( (s2650c->psl >> 6) != s2650c->r );
break;
case 0x9f: /* BXA (*)a */
- s2650_ICount -= 9;
+ s2650c->icount -= 9;
M_BXA();
break;
@@ -1268,215 +1271,215 @@ static CPU_EXECUTE( s2650 )
case 0xa1: /* SUBZ,1 */
case 0xa2: /* SUBZ,2 */
case 0xa3: /* SUBZ,3 */
- s2650_ICount -= 6;
- M_SUB( R0, S.reg[S.r] );
+ s2650c->icount -= 6;
+ M_SUB( R0, s2650c->reg[s2650c->r] );
break;
case 0xa4: /* SUBI,0 v */
case 0xa5: /* SUBI,1 v */
case 0xa6: /* SUBI,2 v */
case 0xa7: /* SUBI,3 v */
- s2650_ICount -= 6;
- M_SUB( S.reg[S.r], ARG() );
+ s2650c->icount -= 6;
+ M_SUB( s2650c->reg[s2650c->r], ARG(s2650c) );
break;
case 0xa8: /* SUBR,0 (*)a */
case 0xa9: /* SUBR,1 (*)a */
case 0xaa: /* SUBR,2 (*)a */
case 0xab: /* SUBR,3 (*)a */
- s2650_ICount -= 9;
- REL_EA(S.page);
- M_SUB( S.reg[S.r], RDMEM(S.ea) );
+ s2650c->icount -= 9;
+ REL_EA(s2650c->page);
+ M_SUB( s2650c->reg[s2650c->r], RDMEM(s2650c->ea) );
break;
case 0xac: /* SUBA,0 (*)a(,X) */
case 0xad: /* SUBA,1 (*)a(,X) */
case 0xae: /* SUBA,2 (*)a(,X) */
case 0xaf: /* SUBA,3 (*)a(,X) */
- s2650_ICount -= 12;
+ s2650c->icount -= 12;
ABS_EA();
- M_SUB( S.reg[S.r], RDMEM(S.ea) );
+ M_SUB( s2650c->reg[s2650c->r], RDMEM(s2650c->ea) );
break;
case 0xb0: /* WRTC,0 */
case 0xb1: /* WRTC,1 */
case 0xb2: /* WRTC,2 */
case 0xb3: /* WRTC,3 */
- s2650_ICount -= 6;
- memory_write_byte_8le(S.io, S2650_CTRL_PORT,S.reg[S.r]);
+ s2650c->icount -= 6;
+ memory_write_byte_8le(s2650c->io, S2650_CTRL_PORT,s2650c->reg[s2650c->r]);
break;
case 0xb4: /* TPSU */
- s2650_ICount -= 9;
+ s2650c->icount -= 9;
M_TPSU();
break;
case 0xb5: /* TPSL */
- s2650_ICount -= 9;
+ s2650c->icount -= 9;
M_TPSL();
break;
case 0xb6: /* illegal */
case 0xb7: /* illegal */
- s2650_ICount -= 7;
+ s2650c->icount -= 7;
break;
case 0xb8: /* BSFR,0 (*)a */
case 0xb9: /* BSFR,1 (*)a */
case 0xba: /* BSFR,2 (*)a */
- s2650_ICount -= 9;
- M_BSR( (S.psl >> 6) != S.r );
+ s2650c->icount -= 9;
+ M_BSR( (s2650c->psl >> 6) != s2650c->r );
break;
case 0xbb: /* ZBSR (*)a */
- s2650_ICount -= 9;
+ s2650c->icount -= 9;
M_ZBSR();
break;
case 0xbc: /* BSFA,0 (*)a */
case 0xbd: /* BSFA,1 (*)a */
case 0xbe: /* BSFA,2 (*)a */
- s2650_ICount -= 9;
- M_BSA( (S.psl >> 6) != S.r );
+ s2650c->icount -= 9;
+ M_BSA( (s2650c->psl >> 6) != s2650c->r );
break;
case 0xbf: /* BSXA (*)a */
- s2650_ICount -= 9;
+ s2650c->icount -= 9;
M_BSXA();
break;
case 0xc0: /* NOP */
- s2650_ICount -= 6;
+ s2650c->icount -= 6;
break;
case 0xc1: /* STRZ,1 */
case 0xc2: /* STRZ,2 */
case 0xc3: /* STRZ,3 */
- s2650_ICount -= 6;
- M_LOD( S.reg[S.r], R0 );
+ s2650c->icount -= 6;
+ M_LOD( s2650c->reg[s2650c->r], R0 );
break;
case 0xc4: /* illegal */
case 0xc5: /* illegal */
case 0xc6: /* illegal */
case 0xc7: /* illegal */
- s2650_ICount -= 7;
+ s2650c->icount -= 7;
break;
case 0xc8: /* STRR,0 (*)a */
case 0xc9: /* STRR,1 (*)a */
case 0xca: /* STRR,2 (*)a */
case 0xcb: /* STRR,3 (*)a */
- s2650_ICount -= 9;
- REL_EA(S.page);
- M_STR( S.ea, S.reg[S.r] );
+ s2650c->icount -= 9;
+ REL_EA(s2650c->page);
+ M_STR( s2650c->ea, s2650c->reg[s2650c->r] );
break;
case 0xcc: /* STRA,0 (*)a(,X) */
case 0xcd: /* STRA,1 (*)a(,X) */
case 0xce: /* STRA,2 (*)a(,X) */
case 0xcf: /* STRA,3 (*)a(,X) */
- s2650_ICount -= 12;
+ s2650c->icount -= 12;
ABS_EA();
- M_STR( S.ea, S.reg[S.r] );
+ M_STR( s2650c->ea, s2650c->reg[s2650c->r] );
break;
case 0xd0: /* RRL,0 */
case 0xd1: /* RRL,1 */
case 0xd2: /* RRL,2 */
case 0xd3: /* RRL,3 */
- s2650_ICount -= 6;
- M_RRL( S.reg[S.r] );
+ s2650c->icount -= 6;
+ M_RRL( s2650c->reg[s2650c->r] );
break;
case 0xd4: /* WRTE,0 v */
case 0xd5: /* WRTE,1 v */
case 0xd6: /* WRTE,2 v */
case 0xd7: /* WRTE,3 v */
- s2650_ICount -= 9;
- memory_write_byte_8le( S.io, ARG(), S.reg[S.r] );
+ s2650c->icount -= 9;
+ memory_write_byte_8le( s2650c->io, ARG(s2650c), s2650c->reg[s2650c->r] );
break;
case 0xd8: /* BIRR,0 (*)a */
case 0xd9: /* BIRR,1 (*)a */
case 0xda: /* BIRR,2 (*)a */
case 0xdb: /* BIRR,3 (*)a */
- s2650_ICount -= 9;
- M_BRR( ++S.reg[S.r] );
+ s2650c->icount -= 9;
+ M_BRR( ++s2650c->reg[s2650c->r] );
break;
case 0xdc: /* BIRA,0 (*)a */
case 0xdd: /* BIRA,1 (*)a */
case 0xde: /* BIRA,2 (*)a */
case 0xdf: /* BIRA,3 (*)a */
- s2650_ICount -= 9;
- M_BRA( ++S.reg[S.r] );
+ s2650c->icount -= 9;
+ M_BRA( ++s2650c->reg[s2650c->r] );
break;
case 0xe0: /* COMZ,0 */
case 0xe1: /* COMZ,1 */
case 0xe2: /* COMZ,2 */
case 0xe3: /* COMZ,3 */
- s2650_ICount -= 6;
- M_COM( R0, S.reg[S.r] );
+ s2650c->icount -= 6;
+ M_COM( R0, s2650c->reg[s2650c->r] );
break;
case 0xe4: /* COMI,0 v */
case 0xe5: /* COMI,1 v */
case 0xe6: /* COMI,2 v */
case 0xe7: /* COMI,3 v */
- s2650_ICount -= 6;
- M_COM( S.reg[S.r], ARG() );
+ s2650c->icount -= 6;
+ M_COM( s2650c->reg[s2650c->r], ARG(s2650c) );
break;
case 0xe8: /* COMR,0 (*)a */
case 0xe9: /* COMR,1 (*)a */
case 0xea: /* COMR,2 (*)a */
case 0xeb: /* COMR,3 (*)a */
- s2650_ICount -= 9;
- REL_EA(S.page);
- M_COM( S.reg[S.r], RDMEM(S.ea) );
+ s2650c->icount -= 9;
+ REL_EA(s2650c->page);
+ M_COM( s2650c->reg[s2650c->r], RDMEM(s2650c->ea) );
break;
case 0xec: /* COMA,0 (*)a(,X) */
case 0xed: /* COMA,1 (*)a(,X) */
case 0xee: /* COMA,2 (*)a(,X) */
case 0xef: /* COMA,3 (*)a(,X) */
- s2650_ICount -= 12;
+ s2650c->icount -= 12;
ABS_EA();
- M_COM( S.reg[S.r], RDMEM(S.ea) );
+ M_COM( s2650c->reg[s2650c->r], RDMEM(s2650c->ea) );
break;
case 0xf0: /* WRTD,0 */
case 0xf1: /* WRTD,1 */
case 0xf2: /* WRTD,2 */
case 0xf3: /* WRTD,3 */
- s2650_ICount -= 6;
- memory_write_byte_8le(S.io, S2650_DATA_PORT, S.reg[S.r]);
+ s2650c->icount -= 6;
+ memory_write_byte_8le(s2650c->io, S2650_DATA_PORT, s2650c->reg[s2650c->r]);
break;
case 0xf4: /* TMI,0 v */
case 0xf5: /* TMI,1 v */
case 0xf6: /* TMI,2 v */
case 0xf7: /* TMI,3 v */
- s2650_ICount -= 9;
- M_TMI( S.reg[S.r] );
+ s2650c->icount -= 9;
+ M_TMI( s2650c->reg[s2650c->r] );
break;
case 0xf8: /* BDRR,0 (*)a */
case 0xf9: /* BDRR,1 (*)a */
case 0xfa: /* BDRR,2 (*)a */
case 0xfb: /* BDRR,3 (*)a */
- s2650_ICount -= 9;
- M_BRR( --S.reg[S.r] );
+ s2650c->icount -= 9;
+ M_BRR( --s2650c->reg[s2650c->r] );
break;
case 0xfc: /* BDRA,0 (*)a */
case 0xfd: /* BDRA,1 (*)a */
case 0xfe: /* BDRA,2 (*)a */
case 0xff: /* BDRA,3 (*)a */
- s2650_ICount -= 9;
- M_BRA( --S.reg[S.r] );
+ s2650c->icount -= 9;
+ M_BRA( --s2650c->reg[s2650c->r] );
break;
}
- } while( s2650_ICount > 0 );
+ } while( s2650c->icount > 0 );
- return cycles - s2650_ICount;
+ return cycles - s2650c->icount;
}
@@ -1486,31 +1489,33 @@ static CPU_EXECUTE( s2650 )
static CPU_SET_INFO( s2650 )
{
+ s2650_regs *s2650c = device->token;
+
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
- case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(0, info->i); break;
- case CPUINFO_INT_INPUT_STATE + 1: set_irq_line(1, info->i); break;
+ case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(s2650c, 0, info->i); break;
+ case CPUINFO_INT_INPUT_STATE + 1: set_irq_line(s2650c, 1, info->i); break;
case CPUINFO_INT_PC:
- S.page = info->i & PAGE;
- S.iar = info->i & PMSK;
- change_pc(S.page + S.iar);
+ s2650c->page = info->i & PAGE;
+ s2650c->iar = info->i & PMSK;
+ change_pc(s2650c->page + s2650c->iar);
break;
- case CPUINFO_INT_REGISTER + S2650_PC: S.page = info->i & PAGE; S.iar = info->i & PMSK; break;
- case CPUINFO_INT_SP: S.psu = (S.psu & ~SP) | (info->i & SP); break;
- case CPUINFO_INT_REGISTER + S2650_PS: S.psl = info->i & 0xff; S.psu = info->i >> 8; break;
- case CPUINFO_INT_REGISTER + S2650_R0: S.reg[0] = info->i; break;
- case CPUINFO_INT_REGISTER + S2650_R1: S.reg[1] = info->i; break;
- case CPUINFO_INT_REGISTER + S2650_R2: S.reg[2] = info->i; break;
- case CPUINFO_INT_REGISTER + S2650_R3: S.reg[3] = info->i; break;
- case CPUINFO_INT_REGISTER + S2650_R1A: S.reg[4] = info->i; break;
- case CPUINFO_INT_REGISTER + S2650_R2A: S.reg[5] = info->i; break;
- case CPUINFO_INT_REGISTER + S2650_R3A: S.reg[6] = info->i; break;
- case CPUINFO_INT_REGISTER + S2650_HALT: S.halt = info->i; break;
- case CPUINFO_INT_REGISTER + S2650_SI: s2650_set_sense(info->i); break;
- case CPUINFO_INT_REGISTER + S2650_FO: s2650_set_flag(info->i); break;
+ case CPUINFO_INT_REGISTER + S2650_PC: s2650c->page = info->i & PAGE; s2650c->iar = info->i & PMSK; break;
+ case CPUINFO_INT_SP: s2650c->psu = (s2650c->psu & ~SP) | (info->i & SP); break;
+ case CPUINFO_INT_REGISTER + S2650_PS: s2650c->psl = info->i & 0xff; s2650c->psu = info->i >> 8; break;
+ case CPUINFO_INT_REGISTER + S2650_R0: s2650c->reg[0] = info->i; break;
+ case CPUINFO_INT_REGISTER + S2650_R1: s2650c->reg[1] = info->i; break;
+ case CPUINFO_INT_REGISTER + S2650_R2: s2650c->reg[2] = info->i; break;
+ case CPUINFO_INT_REGISTER + S2650_R3: s2650c->reg[3] = info->i; break;
+ case CPUINFO_INT_REGISTER + S2650_R1A: s2650c->reg[4] = info->i; break;
+ case CPUINFO_INT_REGISTER + S2650_R2A: s2650c->reg[5] = info->i; break;
+ case CPUINFO_INT_REGISTER + S2650_R3A: s2650c->reg[6] = info->i; break;
+ case CPUINFO_INT_REGISTER + S2650_HALT: s2650c->halt = info->i; break;
+ case CPUINFO_INT_REGISTER + S2650_SI: s2650_set_sense(s2650c, info->i); break;
+ case CPUINFO_INT_REGISTER + S2650_FO: s2650_set_flag(s2650c, info->i); break;
}
}
@@ -1522,10 +1527,11 @@ static CPU_SET_INFO( s2650 )
CPU_GET_INFO( s2650 )
{
+ s2650_regs *s2650c = device ? device->token : NULL;
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
- case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(S); break;
+ case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(s2650_regs); break;
case CPUINFO_INT_INPUT_LINES: info->i = 2; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break;
@@ -1548,26 +1554,26 @@ CPU_GET_INFO( s2650 )
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 9; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
- case CPUINFO_INT_INPUT_STATE + 0: info->i = S.irq_state; break;
- case CPUINFO_INT_INPUT_STATE + 1: info->i = s2650_get_sense() ? ASSERT_LINE : CLEAR_LINE; break;
+ case CPUINFO_INT_INPUT_STATE + 0: info->i = s2650c->irq_state; break;
+ case CPUINFO_INT_INPUT_STATE + 1: info->i = s2650_get_sense(s2650c) ? ASSERT_LINE : CLEAR_LINE; break;
- case CPUINFO_INT_PREVIOUSPC: info->i = S.ppc; break;
+ case CPUINFO_INT_PREVIOUSPC: info->i = s2650c->ppc; break;
case CPUINFO_INT_PC:
- case CPUINFO_INT_REGISTER + S2650_PC: info->i = S.page + S.iar; break;
-
- case CPUINFO_INT_SP: info->i = S.psu & SP; break;
- case CPUINFO_INT_REGISTER + S2650_PS: info->i = (S.psu << 8) | S.psl; break;
- case CPUINFO_INT_REGISTER + S2650_R0: info->i = S.reg[0]; break;
- case CPUINFO_INT_REGISTER + S2650_R1: info->i = S.reg[1]; break;
- case CPUINFO_INT_REGISTER + S2650_R2: info->i = S.reg[2]; break;
- case CPUINFO_INT_REGISTER + S2650_R3: info->i = S.reg[3]; break;
- case CPUINFO_INT_REGISTER + S2650_R1A: info->i = S.reg[4]; break;
- case CPUINFO_INT_REGISTER + S2650_R2A: info->i = S.reg[5]; break;
- case CPUINFO_INT_REGISTER + S2650_R3A: info->i = S.reg[6]; break;
- case CPUINFO_INT_REGISTER + S2650_HALT: info->i = S.halt; break;
- case CPUINFO_INT_REGISTER + S2650_SI: info->i = s2650_get_sense(); break;
- case CPUINFO_INT_REGISTER + S2650_FO: info->i = s2650_get_flag(); break;
+ case CPUINFO_INT_REGISTER + S2650_PC: info->i = s2650c->page + s2650c->iar; break;
+
+ case CPUINFO_INT_SP: info->i = s2650c->psu & SP; break;
+ case CPUINFO_INT_REGISTER + S2650_PS: info->i = (s2650c->psu << 8) | s2650c->psl; break;
+ case CPUINFO_INT_REGISTER + S2650_R0: info->i = s2650c->reg[0]; break;
+ case CPUINFO_INT_REGISTER + S2650_R1: info->i = s2650c->reg[1]; break;
+ case CPUINFO_INT_REGISTER + S2650_R2: info->i = s2650c->reg[2]; break;
+ case CPUINFO_INT_REGISTER + S2650_R3: info->i = s2650c->reg[3]; break;
+ case CPUINFO_INT_REGISTER + S2650_R1A: info->i = s2650c->reg[4]; break;
+ case CPUINFO_INT_REGISTER + S2650_R2A: info->i = s2650c->reg[5]; break;
+ case CPUINFO_INT_REGISTER + S2650_R3A: info->i = s2650c->reg[6]; break;
+ case CPUINFO_INT_REGISTER + S2650_HALT: info->i = s2650c->halt; break;
+ case CPUINFO_INT_REGISTER + S2650_SI: info->i = s2650_get_sense(s2650c); break;
+ case CPUINFO_INT_REGISTER + S2650_FO: info->i = s2650_get_flag(s2650c); break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(s2650); break;
@@ -1579,7 +1585,7 @@ CPU_GET_INFO( s2650 )
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(s2650); break;
case CPUINFO_PTR_BURN: info->burn = NULL; break;
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(s2650); break;
- case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &s2650_ICount; break;
+ case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &s2650c->icount; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "S2650"); break;
@@ -1590,35 +1596,35 @@ CPU_GET_INFO( s2650 )
case CPUINFO_STR_FLAGS:
sprintf(info->s, "%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
- S.psu & 0x80 ? 'S':'.',
- S.psu & 0x40 ? 'O':'.',
- S.psu & 0x20 ? 'I':'.',
- S.psu & 0x10 ? '?':'.',
- S.psu & 0x08 ? '?':'.',
- S.psu & 0x04 ? 's':'.',
- S.psu & 0x02 ? 's':'.',
- S.psu & 0x01 ? 's':'.',
- S.psl & 0x80 ? 'M':'.',
- S.psl & 0x40 ? 'P':'.',
- S.psl & 0x20 ? 'H':'.',
- S.psl & 0x10 ? 'R':'.',
- S.psl & 0x08 ? 'W':'.',
- S.psl & 0x04 ? 'V':'.',
- S.psl & 0x02 ? '2':'.',
- S.psl & 0x01 ? 'C':'.');
+ s2650c->psu & 0x80 ? 'S':'.',
+ s2650c->psu & 0x40 ? 'O':'.',
+ s2650c->psu & 0x20 ? 'I':'.',
+ s2650c->psu & 0x10 ? '?':'.',
+ s2650c->psu & 0x08 ? '?':'.',
+ s2650c->psu & 0x04 ? 's':'.',
+ s2650c->psu & 0x02 ? 's':'.',
+ s2650c->psu & 0x01 ? 's':'.',
+ s2650c->psl & 0x80 ? 'M':'.',
+ s2650c->psl & 0x40 ? 'P':'.',
+ s2650c->psl & 0x20 ? 'H':'.',
+ s2650c->psl & 0x10 ? 'R':'.',
+ s2650c->psl & 0x08 ? 'W':'.',
+ s2650c->psl & 0x04 ? 'V':'.',
+ s2650c->psl & 0x02 ? '2':'.',
+ s2650c->psl & 0x01 ? 'C':'.');
break;
- case CPUINFO_STR_REGISTER + S2650_PC: sprintf(info->s, "PC:%04X", S.page + S.iar); break;
- case CPUINFO_STR_REGISTER + S2650_PS: sprintf(info->s, "PS:%02X%02X", S.psu, S.psl); break;
- case CPUINFO_STR_REGISTER + S2650_R0: sprintf(info->s, "R0:%02X", S.reg[0]); break;
- case CPUINFO_STR_REGISTER + S2650_R1: sprintf(info->s, "R1:%02X", S.reg[1]); break;
- case CPUINFO_STR_REGISTER + S2650_R2: sprintf(info->s, "R2:%02X", S.reg[2]); break;
- case CPUINFO_STR_REGISTER + S2650_R3: sprintf(info->s, "R3:%02X", S.reg[3]); break;
- case CPUINFO_STR_REGISTER + S2650_R1A: sprintf(info->s, "R1':%02X", S.reg[4]); break;
- case CPUINFO_STR_REGISTER + S2650_R2A: sprintf(info->s, "R2':%02X", S.reg[5]); break;
- case CPUINFO_STR_REGISTER + S2650_R3A: sprintf(info->s, "R3':%02X", S.reg[6]); break;
- case CPUINFO_STR_REGISTER + S2650_HALT: sprintf(info->s, "HALT:%X", S.halt); break;
- case CPUINFO_STR_REGISTER + S2650_SI: sprintf(info->s, "SI:%X", (S.psu & SI) ? 1 : 0); break;
- case CPUINFO_STR_REGISTER + S2650_FO: sprintf(info->s, "FO:%X", (S.psu & FO) ? 1 : 0); break;
+ case CPUINFO_STR_REGISTER + S2650_PC: sprintf(info->s, "PC:%04X", s2650c->page + s2650c->iar); break;
+ case CPUINFO_STR_REGISTER + S2650_PS: sprintf(info->s, "PS:%02X%02X", s2650c->psu, s2650c->psl); break;
+ case CPUINFO_STR_REGISTER + S2650_R0: sprintf(info->s, "R0:%02X", s2650c->reg[0]); break;
+ case CPUINFO_STR_REGISTER + S2650_R1: sprintf(info->s, "R1:%02X", s2650c->reg[1]); break;
+ case CPUINFO_STR_REGISTER + S2650_R2: sprintf(info->s, "R2:%02X", s2650c->reg[2]); break;
+ case CPUINFO_STR_REGISTER + S2650_R3: sprintf(info->s, "R3:%02X", s2650c->reg[3]); break;
+ case CPUINFO_STR_REGISTER + S2650_R1A: sprintf(info->s, "R1':%02X", s2650c->reg[4]); break;
+ case CPUINFO_STR_REGISTER + S2650_R2A: sprintf(info->s, "R2':%02X", s2650c->reg[5]); break;
+ case CPUINFO_STR_REGISTER + S2650_R3A: sprintf(info->s, "R3':%02X", s2650c->reg[6]); break;
+ case CPUINFO_STR_REGISTER + S2650_HALT: sprintf(info->s, "HALT:%X", s2650c->halt); break;
+ case CPUINFO_STR_REGISTER + S2650_SI: sprintf(info->s, "SI:%X", (s2650c->psu & SI) ? 1 : 0); break;
+ case CPUINFO_STR_REGISTER + S2650_FO: sprintf(info->s, "FO:%X", (s2650c->psu & FO) ? 1 : 0); break;
}
}
diff --git a/src/emu/cpu/s2650/s2650cpu.h b/src/emu/cpu/s2650/s2650cpu.h
index edd2c5f922c..e0158390e67 100644
--- a/src/emu/cpu/s2650/s2650cpu.h
+++ b/src/emu/cpu/s2650/s2650cpu.h
@@ -27,7 +27,7 @@
#define FO 0x40 /* flag output */
#define SI 0x80 /* sense input */
-#define R0 S.reg[0]
-#define R1 S.reg[1]
-#define R2 S.reg[2]
-#define R3 S.reg[3]
+#define R0 s2650c->reg[0]
+#define R1 s2650c->reg[1]
+#define R2 s2650c->reg[2]
+#define R3 s2650c->reg[3]