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author Michaël Banaan Ananas <happppp@users.noreply.github.com>2009-08-24 11:57:26 +0000
committer Michaël Banaan Ananas <happppp@users.noreply.github.com>2009-08-24 11:57:26 +0000
commit7e2794ad210e9c6e2019d513ba676a6496c61383 (patch)
tree748182b32c3bcd4c4e9508039be83e7b9856d36b /src
parentc269fb3d3227b24f62e01219ecaf6bb93fd074bc (diff)
Fixed IM2 interrupt cycles [eke]
http://www.mameworld.info/ubbthreads/showthreaded.php?Cat=&Number=199853&page=0&view=expanded&sb=5&o=&fpart=1&vc=1 I don't know this z80 emulator well enough to look into his first two points. Juergen? 1/ In the cc_xy[] table which lists instructions with DD or FD prefixes, "illegal" combos are returning 4 cycles when they should return 4 + cc_op (the normal instruction being executed). Another way to handle this correctly is to call EXEC(z80,fd,xx) or EXEC(z80,dd,xx) instead of op_xx(z80) when such pair of opcode is detected, to be sure the correct amount of cycles is used. 2/ According to Sean Young, R register is NOT incremented when chaining multiple DD or FD prefixes: [...] This one was already fixed, dunno when: 2/ In the cc_ed[] table, INI (ED A2) and IND (ED AA) should return 16 cycles, like other instructions from this group, not 12. This seems to be a typo error.
Diffstat (limited to 'src')
-rw-r--r--src/emu/cpu/z80/z80.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/emu/cpu/z80/z80.c b/src/emu/cpu/z80/z80.c
index 7f0b952e26a..e7ae5876243 100644
--- a/src/emu/cpu/z80/z80.c
+++ b/src/emu/cpu/z80/z80.c
@@ -34,6 +34,7 @@
* - Fixed cycle counts for LD IYL/IXL/IYH/IXH,n [Marshmellow]
* - Fixed X/Y flags in CCF/SCF/BIT, ZEXALL is happy now [hap]
* - Simplified DAA, renamed MEMPTR (3.8) to WZ, added TODO [hap]
+ * - Fixed IM2 interrupt cycles [eke]
* Changes in 3.8 [Miodrag Milanovic]:
* - Added MEMPTR register (according to informations provided
* by Vladimir Kladov
@@ -3296,8 +3297,8 @@ static void take_interrupt(z80_state *z80)
PUSH(z80, pc);
RM16(z80, irq_vector, &z80->pc);
LOG(("Z80 '%s' IM2 [$%04x] = $%04x\n", z80->device->tag, irq_vector, z80->PCD));
- /* CALL opcode timing */
- z80->icount -= z80->cc_op[0xcd];
+ /* CALL opcode timing + 'interrupt latency' cycles */
+ z80->icount -= z80->cc_op[0xcd] + z80->cc_ex[0xff];
}
else
/* Interrupt mode 1. RST 38h */