diff options
| author | 2009-06-20 19:48:16 +0000 | |
|---|---|---|
| committer | 2009-06-20 19:48:16 +0000 | |
| commit | 70cb45d062664b78a8fa153626c769de87971119 (patch) | |
| tree | 4ea9340831a12955de3178f26997bb6087f16f17 /src | |
| parent | 8a3509b1256abf2f07097244442f603a35c6fa6b (diff) | |
mc68hc11: Fixed a CPY IMM DASM bug, added BRCLR INDX, BRSET INDX, BCLR INDX, BSET INDX, CLC, NOP, SUBB DIR, SUBA DIR, SUBA INDX, SUBB INDX, SUBD IMM
Diffstat (limited to 'src')
| -rw-r--r-- | src/emu/cpu/mc68hc11/hc11dasm.c | 2 | ||||
| -rw-r--r-- | src/emu/cpu/mc68hc11/hc11ops.c | 161 | ||||
| -rw-r--r-- | src/emu/cpu/mc68hc11/hc11ops.h | 11 | ||||
| -rw-r--r-- | src/mame/drivers/hitpoker.c | 17 |
4 files changed, 181 insertions, 10 deletions
diff --git a/src/emu/cpu/mc68hc11/hc11dasm.c b/src/emu/cpu/mc68hc11/hc11dasm.c index 6fbf4bfb819..d46c82e304c 100644 --- a/src/emu/cpu/mc68hc11/hc11dasm.c +++ b/src/emu/cpu/mc68hc11/hc11dasm.c @@ -463,7 +463,7 @@ static const M68HC11_OPCODE opcode_table_page2[256] = { "?", 0, }, { "?", 0, }, { "?", 0, }, - { "cpy", EA_IMM8, }, + { "cpy", EA_IMM16, }, { "?", 0, }, { "?", 0, }, { "xgdy", 0, }, diff --git a/src/emu/cpu/mc68hc11/hc11ops.c b/src/emu/cpu/mc68hc11/hc11ops.c index 5783cf1c10d..313dcde658f 100644 --- a/src/emu/cpu/mc68hc11/hc11ops.c +++ b/src/emu/cpu/mc68hc11/hc11ops.c @@ -785,6 +785,21 @@ static void HC11OP(bcc)(hc11_state *cpustate) CYCLES(cpustate, 3); } +/* BCLR INDX 0x1d */ +static void HC11OP(bclr_indx)(hc11_state *cpustate) +{ + UINT8 offset = FETCH(cpustate); + UINT8 mask = FETCH(cpustate); + UINT8 r = READ8(cpustate, cpustate->ix + offset); + r = r & ~mask; + WRITE8(cpustate, cpustate->ix + offset, r); + CLEAR_NZV(cpustate); + SET_N8(r); + SET_Z8(r); + + CYCLES(cpustate, 7); +} + /* BCS 0x25 */ static void HC11OP(bcs)(hc11_state *cpustate) { @@ -865,14 +880,62 @@ static void HC11OP(bra)(hc11_state *cpustate) CYCLES(cpustate, 3); } +/* BRCLR INDX 0x1F */ +static void HC11OP(brclr_indx)(hc11_state *cpustate) +{ + UINT8 offset = FETCH(cpustate); + UINT8 mask = FETCH(cpustate); + INT8 rel = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + offset); + + if(!(i & mask)) + { + SET_PC(cpustate, cpustate->ppc + rel + 4); + } + + CYCLES(cpustate, 7); +} + +/* BRSET INDX 0x1E */ +static void HC11OP(brset_indx)(hc11_state *cpustate) +{ + UINT8 offset = FETCH(cpustate); + UINT8 mask = FETCH(cpustate); + INT8 rel = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + offset); + + if(i & mask) + { + SET_PC(cpustate, cpustate->ppc + rel + 4); + } + + CYCLES(cpustate, 7); +} + + /* BRN 0x21 */ static void HC11OP(brn)(hc11_state *cpustate) { - /* with this opcode, the branch condition is always false. */ + /* with this opcode the branch condition is always false. */ SET_PC(cpustate, cpustate->ppc + 2); CYCLES(cpustate, 3); } +/* BSET INDX 0x1c */ +static void HC11OP(bset_indx)(hc11_state *cpustate) +{ + UINT8 offset = FETCH(cpustate); + UINT8 mask = FETCH(cpustate); + UINT8 r = READ8(cpustate, cpustate->ix + offset); + r = (r & ~mask) | mask; + WRITE8(cpustate, cpustate->ix + offset, r); + CLEAR_NZV(cpustate); + SET_N8(r); + SET_Z8(r); + + CYCLES(cpustate, 7); +} + /* BSR 0x8D */ static void HC11OP(bsr)(hc11_state *cpustate) { @@ -917,6 +980,14 @@ static void HC11OP(cba)(hc11_state *cpustate) CYCLES(cpustate, 2); } +/* CLC 0x0C */ +static void HC11OP(clc)(hc11_state *cpustate) +{ + cpustate->ccr &= ~CC_C; + CYCLES(cpustate, 2); +} + + /* CLI 0x0E */ static void HC11OP(cli)(hc11_state *cpustate) { @@ -2009,6 +2080,12 @@ static void HC11OP(mul)(hc11_state *cpustate) CYCLES(cpustate, 10); } +/* NOP 0x01 */ +static void HC11OP(nop)(hc11_state *cpustate) +{ + CYCLES(cpustate, 2); +} + /* PSHA 0x36 */ static void HC11OP(psha)(hc11_state *cpustate) { @@ -2016,7 +2093,6 @@ static void HC11OP(psha)(hc11_state *cpustate) CYCLES(cpustate, 3); } - /* ORAA IMM 0x8A */ static void HC11OP(oraa_imm)(hc11_state *cpustate) { @@ -2394,6 +2470,22 @@ static void HC11OP(sty_indx)(hc11_state *cpustate) CYCLES(cpustate, 6); } +/* SUBA DIR 0xd0 */ +static void HC11OP(suba_dir)(hc11_state *cpustate) +{ + UINT8 d = FETCH(cpustate); + UINT8 i = READ8(cpustate, d); + UINT16 r = REG_A - i; + CLEAR_HNZVC(cpustate); + SET_H(r, i, REG_A); + SET_N8(r); + SET_Z8(r); + SET_V_SUB8(r, i, REG_A); + SET_C8(r); + REG_B = (UINT8)r; + CYCLES(cpustate, 3); +} + /* SUBA IMM 0x80 */ static void HC11OP(suba_imm)(hc11_state *cpustate) { @@ -2409,7 +2501,39 @@ static void HC11OP(suba_imm)(hc11_state *cpustate) CYCLES(cpustate, 2); } -/* SUBB IMM 0xc0 */ +/* SUBA INDX 0xA0 */ +static void HC11OP(suba_indx)(hc11_state *cpustate) +{ + UINT16 adr = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + adr); + UINT16 r = REG_A - i; + CLEAR_HNZVC(cpustate); + SET_H(r, i, REG_A); + SET_N8(r); + SET_Z8(r); + SET_V_SUB8(r, i, REG_A); + SET_C8(r); + REG_B = (UINT8)r; + CYCLES(cpustate, 4); +} + +/* SUBB DIR 0xD0 */ +static void HC11OP(subb_dir)(hc11_state *cpustate) +{ + UINT8 d = FETCH(cpustate); + UINT8 i = READ8(cpustate, d); + UINT16 r = REG_B - i; + CLEAR_HNZVC(cpustate); + SET_H(r, i, REG_B); + SET_N8(r); + SET_Z8(r); + SET_V_SUB8(r, i, REG_B); + SET_C8(r); + REG_B = (UINT8)r; + CYCLES(cpustate, 3); +} + +/* SUBB IMM 0xC0 */ static void HC11OP(subb_imm)(hc11_state *cpustate) { UINT8 i = FETCH(cpustate); @@ -2424,6 +2548,36 @@ static void HC11OP(subb_imm)(hc11_state *cpustate) CYCLES(cpustate, 2); } +/* SUBB INDX 0xE0 */ +static void HC11OP(subb_indx)(hc11_state *cpustate) +{ + UINT16 adr = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + adr); + UINT16 r = REG_B - i; + CLEAR_HNZVC(cpustate); + SET_H(r, i, REG_B); + SET_N8(r); + SET_Z8(r); + SET_V_SUB8(r, i, REG_B); + SET_C8(r); + REG_B = (UINT8)r; + CYCLES(cpustate, 4); +} + +/* SUBD IMM 0x83 */ +static void HC11OP(subd_imm)(hc11_state *cpustate) +{ + UINT16 i = FETCH16(cpustate); + UINT32 r = REG_D - i; + CLEAR_NZVC(cpustate); + SET_N16(r); + SET_Z16(r); + SET_V_SUB16(r, i, REG_D); + SET_C16(r); + REG_D = (UINT16)r; + CYCLES(cpustate, 4); +} + /* TAB 0x16 */ static void HC11OP(tab)(hc11_state *cpustate) { @@ -2434,7 +2588,6 @@ static void HC11OP(tab)(hc11_state *cpustate) CYCLES(cpustate, 2); } - /* TAP 0x06 */ static void HC11OP(tap)(hc11_state *cpustate) { diff --git a/src/emu/cpu/mc68hc11/hc11ops.h b/src/emu/cpu/mc68hc11/hc11ops.h index 8cf937f007a..680a486e7e4 100644 --- a/src/emu/cpu/mc68hc11/hc11ops.h +++ b/src/emu/cpu/mc68hc11/hc11ops.h @@ -60,6 +60,7 @@ static const hc11_opcode_list_struct hc11_opcode_list[] = { 0, 0xe5, HC11OP(bitb_indx) }, { 0x18, 0xe5, HC11OP(bitb_indy) }, { 0, 0x24, HC11OP(bcc) }, + { 0, 0x1d, HC11OP(bclr_indx) }, { 0, 0x25, HC11OP(bcs) }, { 0, 0x27, HC11OP(beq) }, { 0, 0x26, HC11OP(bne) }, @@ -67,11 +68,15 @@ static const hc11_opcode_list_struct hc11_opcode_list[] = { 0, 0x2b, HC11OP(bmi) }, { 0, 0x2a, HC11OP(bpl) }, { 0, 0x20, HC11OP(bra) }, + { 0, 0x1f, HC11OP(brclr_indx) }, + { 0, 0x1e, HC11OP(brset_indx) }, { 0, 0x21, HC11OP(brn) }, + { 0, 0x1c, HC11OP(bset_indx) }, { 0, 0x8d, HC11OP(bsr) }, { 0, 0x28, HC11OP(bvc) }, { 0, 0x29, HC11OP(bvs) }, { 0, 0x11, HC11OP(cba) }, + { 0, 0x0c, HC11OP(clc) }, { 0, 0x0e, HC11OP(cli) }, { 0, 0x4f, HC11OP(clra) }, { 0, 0x5f, HC11OP(clrb) }, @@ -163,6 +168,7 @@ static const hc11_opcode_list_struct hc11_opcode_list[] = { 0, 0x05, HC11OP(lsld) }, { 0, 0x04, HC11OP(lsrd) }, { 0, 0x3d, HC11OP(mul) }, + { 0, 0x01, HC11OP(nop) }, { 0, 0x8a, HC11OP(oraa_imm) }, { 0, 0x9a, HC11OP(oraa_dir) }, { 0, 0xba, HC11OP(oraa_ext) }, @@ -200,8 +206,13 @@ static const hc11_opcode_list_struct hc11_opcode_list[] = { 0, 0xff, HC11OP(stx_ext) }, { 0x18, 0xff, HC11OP(sty_ext) }, { 0x1a, 0xef, HC11OP(sty_indx) }, + { 0, 0x90, HC11OP(suba_dir) }, { 0, 0x80, HC11OP(suba_imm) }, + { 0, 0xa0, HC11OP(suba_indx) }, + { 0, 0xd0, HC11OP(subb_dir) }, { 0, 0xc0, HC11OP(subb_imm) }, + { 0, 0xe0, HC11OP(subb_indx) }, + { 0, 0x83, HC11OP(subd_imm) }, { 0, 0x16, HC11OP(tab) }, { 0, 0x06, HC11OP(tap) }, { 0, 0x17, HC11OP(tba) }, diff --git a/src/mame/drivers/hitpoker.c b/src/mame/drivers/hitpoker.c index 45bd1197877..5cc5c96a60a 100644 --- a/src/mame/drivers/hitpoker.c +++ b/src/mame/drivers/hitpoker.c @@ -20,12 +20,16 @@ Skeleton driver, just the main CPU has been identified (a MC68HC11). This one requires some mods to the cpu core in order to start to work... Many thanks to Olivier Galibert for the identify effort ;-) -How to initialize this: -- let it run then soft reset (it wants that ram at 0-0xff is equal to 0xff, - nvram maybe?); +Some debug tricks (let's test this CPU as more as possible): +- let it run then soft reset (it wants that ram at 0-0xff is equal to 0xff); - set a bp 10c5 then pc=10c8, it currently fails the rom checksum for whatever reason (should be 0 and it returns 0x89), note that area 0xf00-0xfff isn't tested at all, maybe that belongs to somewhere else? +- set a bp 1119 then pc=11a8 for more testing, then jump the tight loop with + a direct pc += 2; + +* Bugs are caused by a weird I/O setting, maybe this one isn't actually + MC68HC11 but something without the I/O stuff? ***************************************************************************/ @@ -49,7 +53,7 @@ VIDEO_UPDATE(hitpoker) bitmap_fill(bitmap, cliprect, 0); - for (x=0;x<64;x++) + for (x=0;x<42;x++) { for (y=0;y<42;y+=2) { @@ -102,6 +106,9 @@ static ADDRESS_MAP_START( main_map, ADDRESS_SPACE_PROGRAM, 8 ) AM_RANGE(0x0000, 0xffff) AM_ROM ADDRESS_MAP_END +static ADDRESS_MAP_START( main_io, ADDRESS_SPACE_IO, 8 ) +ADDRESS_MAP_END + static INPUT_PORTS_START( hitpoker ) INPUT_PORTS_END @@ -144,6 +151,7 @@ GFXDECODE_END static MACHINE_DRIVER_START( hitpoker ) MDRV_CPU_ADD("maincpu", MC68HC11,2000000) MDRV_CPU_PROGRAM_MAP(main_map) + MDRV_CPU_IO_MAP(main_io) MDRV_CPU_VBLANK_INT("screen", irq0_line_hold) /* video hardware */ @@ -171,7 +179,6 @@ ROM_START( hitpoker ) ROM_REGION( 0x1000, "cram", ROMREGION_ERASE00 ) - ROM_REGION( 0x100000, "gfx1", 0 ) // tile 0x4c8 seems to contain something non-gfx related, could be tilemap / colour data, check! ROM_LOAD16_BYTE( "u42.bin", 0x00001, 0x40000, CRC(cbe56fec) SHA1(129bfd10243eaa7fb6a087f96de90228e6030353) ) ROM_LOAD16_BYTE( "u43.bin", 0x00000, 0x40000, CRC(6c0d4283) SHA1(04a4fd82f5cc0ed9f548e490ac67d287227073c3) ) |
