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author Olivier Galibert <galibert@pobox.com>2021-03-26 22:24:12 +0100
committer Olivier Galibert <galibert@pobox.com>2021-03-26 22:26:55 +0100
commit6ceb297bfc52802afa0d001e310d54557e83ff86 (patch)
tree9d23b487ed55a9c868b94d20a8d6e8d509357a98 /src
parent6195c1d6e1208a68383ea06589cb92e4b72b8369 (diff)
ppc: Fix uml for stswx, lswx
Diffstat (limited to 'src')
-rw-r--r--src/devices/cpu/powerpc/ppcdrc.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/devices/cpu/powerpc/ppcdrc.cpp b/src/devices/cpu/powerpc/ppcdrc.cpp
index e93adcdda26..c81915d2cf9 100644
--- a/src/devices/cpu/powerpc/ppcdrc.cpp
+++ b/src/devices/cpu/powerpc/ppcdrc.cpp
@@ -3077,7 +3077,7 @@ bool ppc_device::generate_instruction_1f(drcuml_block &block, compiler_state *co
UML_ADD(block, mem(&m_core->updateaddr), R32Z(G_RA(op)), R32(G_RB(op))); // add [updateaddr],ra,rb
UML_AND(block, mem(&m_core->swcount), SPR32(SPR_XER), 0x7f); // and [swcount],[xer],0x7f
UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), mem(&m_core->swcount));// sub icount,icount,[swcount]
- UML_CALLHc(block, COND_NZ, *m_lsw[m_core->mode][G_RD(op)]); // call lsw[rd],nz
+ UML_CALLH(block, *m_lsw[m_core->mode][G_RD(op)]); // call lsw[rd],nz
generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
return true;
@@ -3229,7 +3229,7 @@ bool ppc_device::generate_instruction_1f(drcuml_block &block, compiler_state *co
UML_ADD(block, mem(&m_core->updateaddr), R32Z(G_RA(op)), R32(G_RB(op))); // add [updateaddr],ra,rb
UML_AND(block, mem(&m_core->swcount), SPR32(SPR_XER), 0x7f); // and [swcount],[xer],0x7f
UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), mem(&m_core->swcount));// sub icount,icount,[swcount]
- UML_CALLHc(block, COND_NZ, *m_stsw[m_core->mode][G_RD(op)]); // call stsw[rd]
+ UML_CALLH(block, *m_stsw[m_core->mode][G_RD(op)]); // call stsw[rd]
generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
return true;