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author Vas Crabb <vas@vastheman.com>2016-06-24 02:59:35 +1000
committer Vas Crabb <vas@vastheman.com>2016-06-24 03:00:01 +1000
commit64f9a674d1bceec375bfa2881fe99568f64f9819 (patch)
treeaf04e54f50e15b5771a9f554d84d7e11c7baff67 /src
parentb07e498b11353c7b35f462ac6402315845019438 (diff)
SPARC VIS 2+, VIS 3 and VIS 3B disassembler support [Vas Crabb]
* Note that this omits non-VIS OSA 2007/2011 features * VIS 2+ ldtxa/ldtwa/sttwa still uses ldda/stda, using new mnemonics requires special-casing this instruction and checking ASI
Diffstat (limited to 'src')
-rw-r--r--src/devices/cpu/sparc/sparcdasm.cpp243
-rw-r--r--src/devices/cpu/sparc/sparcdasm.h14
-rw-r--r--src/tools/unidasm.cpp368
3 files changed, 379 insertions, 246 deletions
diff --git a/src/devices/cpu/sparc/sparcdasm.cpp b/src/devices/cpu/sparc/sparcdasm.cpp
index 0b7bb50e110..06f68082330 100644
--- a/src/devices/cpu/sparc/sparcdasm.cpp
+++ b/src/devices/cpu/sparc/sparcdasm.cpp
@@ -292,27 +292,27 @@ const sparc_disassembler::prftch_desc_map::value_type sparc_disassembler::V9_PRF
};
const sparc_disassembler::vis_op_desc_map::value_type sparc_disassembler::VIS1_OP_DESC[] = {
- { 0x000, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge8" } },
- { 0x002, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge8l" } },
- { 0x004, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge16" } },
- { 0x006, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge16l" } },
- { 0x008, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge32" } },
- { 0x00a, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge32l" } },
-
- { 0x010, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "array8" } },
- { 0x012, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "array16" } },
- { 0x014, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "array32" } },
- { 0x018, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, true, "alignaddr" } },
- { 0x01a, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, true, "alignaddrl" } },
-
- { 0x020, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::I, false, "fcmple16" } },
- { 0x022, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::I, false, "fcmpne16" } },
- { 0x024, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::I, false, "fcmple32" } },
- { 0x026, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::I, false, "fcmpne32" } },
- { 0x028, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::I, false, "fcmpgt16" } },
- { 0x02a, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::I, false, "fcmpeq16" } },
- { 0x02c, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::I, false, "fcmpgt32" } },
- { 0x02e, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::I, false, "fcmpeq32" } },
+ { 0x000, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "edge8" } },
+ { 0x002, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "edge8l" } },
+ { 0x004, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "edge16" } },
+ { 0x006, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "edge16l" } },
+ { 0x008, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "edge32" } },
+ { 0x00a, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "edge32l" } },
+
+ { 0x010, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "array8" } },
+ { 0x012, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "array16" } },
+ { 0x014, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "array32" } },
+ { 0x018, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, true, "alignaddr" } },
+ { 0x01a, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, true, "alignaddrl" } },
+
+ { 0x020, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::R, false, "fcmple16" } },
+ { 0x022, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::R, false, "fcmpne16" } },
+ { 0x024, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::R, false, "fcmple32" } },
+ { 0x026, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::R, false, "fcmpne32" } },
+ { 0x028, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::R, false, "fcmpgt16" } },
+ { 0x02a, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::R, false, "fcmpeq16" } },
+ { 0x02c, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::R, false, "fcmpgt32" } },
+ { 0x02e, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::R, false, "fcmpeq32" } },
{ 0x031, { vis_op_desc::Fs, vis_op_desc::Fd, vis_op_desc::Fd, false, "fmul8x16" } },
{ 0x033, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fd, false, "fmul8x16au" } },
@@ -406,27 +406,101 @@ const sparc_disassembler::asi_desc_map::value_type sparc_disassembler::VIS1_ASI_
{ 0xd9, { "#ASI_FL8_SL", nullptr } },
{ 0xda, { "#ASI_FL16_PL", nullptr } },
{ 0xdb, { "#ASI_FL16_SL", nullptr } },
- { 0xe0, { "#ASI_BLOCK_COMMIT_P", nullptr } },
- { 0xe1, { "#ASI_BLOCK_COMMIT_S", nullptr } },
- { 0xf0, { "#ASI_BLOCK_P", nullptr } },
- { 0xf1, { "#ASI_BLOCK_S", nullptr } },
- { 0xf8, { "#ASI_BLOCK_PL", nullptr } },
- { 0xf9, { "#ASI_BLOCK_SL", nullptr } }
+ { 0xe0, { "#ASI_BLK_COMMIT_P", nullptr } },
+ { 0xe1, { "#ASI_BLK_COMMIT_S", nullptr } },
+ { 0xf0, { "#ASI_BLK_P", nullptr } },
+ { 0xf1, { "#ASI_BLK_S", nullptr } },
+ { 0xf8, { "#ASI_BLK_PL", nullptr } },
+ { 0xf9, { "#ASI_BLK_SL", nullptr } }
};
const sparc_disassembler::vis_op_desc_map::value_type sparc_disassembler::VIS2_OP_DESC[] = {
- { 0x001, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge8n" } },
- { 0x003, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge8ln" } },
- { 0x005, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge16n" } },
- { 0x007, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge16ln" } },
- { 0x009, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge32n" } },
- { 0x00b, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge32ln" } },
+ { 0x001, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "edge8n" } },
+ { 0x003, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "edge8ln" } },
+ { 0x005, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "edge16n" } },
+ { 0x007, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "edge16ln" } },
+ { 0x009, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "edge32n" } },
+ { 0x00b, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "edge32ln" } },
- { 0x019, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, true, "bmask" } },
+ { 0x019, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, true, "bmask" } },
{ 0x04c, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "bshuffle" } }
};
+const sparc_disassembler::asi_desc_map::value_type sparc_disassembler::VIS2P_ASI_DESC[] = {
+ { 0x22, { "#ASI_TWINX_AIUP", nullptr } },
+ { 0x23, { "#ASI_TWINX_AIUS", nullptr } },
+ { 0x26, { "#ASI_TWINX_REAL", nullptr } },
+ { 0x27, { "#ASI_TWINX_N", nullptr } },
+ { 0x2a, { "#ASI_TWINX_AIUP_L", nullptr } },
+ { 0x2b, { "#ASI_TWINX_AIUS_L", nullptr } },
+ { 0x2e, { "#ASI_TWINX_REAL_L", nullptr } },
+ { 0x2f, { "#ASI_TWINX_NL", nullptr } },
+ { 0xe2, { "#ASI_TWINX_P", nullptr } },
+ { 0xe3, { "#ASI_TWINX_S", nullptr } },
+ { 0xea, { "#ASI_TWINX_PL", nullptr } },
+ { 0xeb, { "#ASI_TWINX_SL", nullptr } }
+};
+
+const sparc_disassembler::fpop1_desc_map::value_type sparc_disassembler::VIS3_FPOP1_DESC[] = {
+ { 0x051, { true, false, false, false, "fnadds" } },
+ { 0x052, { true, true, true, true, "fnaddd" } },
+ { 0x059, { true, false, false, false, "fnmuls" } },
+ { 0x05a, { true, true, true, true, "fnmuld" } },
+
+ { 0x061, { true, false, false, false, "fhadds" } },
+ { 0x062, { true, true, true, true, "fhaddd" } },
+ { 0x065, { true, false, false, false, "fhsubs" } },
+ { 0x066, { true, true, true, true, "fhsubd" } },
+
+ { 0x071, { true, false, false, false, "fnhadds" } },
+ { 0x072, { true, true, true, true, "fnhaddd" } },
+ { 0x079, { true, false, false, true, "fnsmuld" } }
+};
+
+const sparc_disassembler::vis_op_desc_map::value_type sparc_disassembler::VIS3_OP_DESC[] = {
+ { 0x011, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "addxc" } },
+ { 0x013, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "addxccc" } },
+ { 0x016, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "umulxhi" } },
+ { 0x017, { vis_op_desc::X, vis_op_desc::R, vis_op_desc::R, false, "lzcnt" } },
+ { 0x01b, { vis_op_desc::X, vis_op_desc::R, vis_op_desc::X, false, "cmask8" } },
+ { 0x01d, { vis_op_desc::X, vis_op_desc::R, vis_op_desc::X, false, "cmask16" } },
+ { 0x01f, { vis_op_desc::X, vis_op_desc::R, vis_op_desc::X, false, "cmask32" } },
+
+ { 0x021, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fsll16" } },
+ { 0x023, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fsrl16" } },
+ { 0x025, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fsll32" } },
+ { 0x027, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fsrl32" } },
+ { 0x029, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fslas16" } },
+ { 0x02b, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fsra16" } },
+ { 0x02d, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fslas32" } },
+ { 0x02f, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fsra32" } },
+
+ { 0x03f, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::R, false, "pdistn" } },
+
+ { 0x040, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fmean16" } },
+ { 0x044, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fchksm16" } },
+
+ { 0x115, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "xmulx" } },
+ { 0x116, { vis_op_desc::R, vis_op_desc::R, vis_op_desc::R, false, "xmulxhi" } }
+};
+
+const sparc_disassembler::vis_op_desc_map::value_type sparc_disassembler::VIS3B_OP_DESC[] = {
+ { 0x042, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fpadd64" } },
+ { 0x046, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fpsub64" } },
+
+ { 0x110, { vis_op_desc::X, vis_op_desc::Fd, vis_op_desc::R, false, "movdtox" } },
+ { 0x111, { vis_op_desc::X, vis_op_desc::Fs, vis_op_desc::R, false, "movstouw" } },
+ { 0x113, { vis_op_desc::X, vis_op_desc::Fs, vis_op_desc::R, false, "movstosw" } },
+ { 0x118, { vis_op_desc::X, vis_op_desc::R, vis_op_desc::Fd, false, "movxtod" } },
+ { 0x119, { vis_op_desc::X, vis_op_desc::R, vis_op_desc::Fs, false, "movwtos" } },
+
+ { 0x120, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::R, false, "fpcmpule8" } },
+ { 0x122, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::R, false, "fpcmpune8" } },
+ { 0x128, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::R, false, "fpcmpugt8" } },
+ { 0x12a, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::R, false, "fpcmpueq8" } }
+};
+
inline UINT32 sparc_disassembler::freg(UINT32 val, bool shift) const
{
@@ -478,8 +552,13 @@ inline void sparc_disassembler::print(char *&output, const char *fmt, ...)
sparc_disassembler::sparc_disassembler(unsigned version)
+ : sparc_disassembler(version, vis_none)
+{
+}
+
+sparc_disassembler::sparc_disassembler(unsigned version, vis_level vis)
: m_version(version)
- , m_vis_level(0)
+ , m_vis_level(vis)
, m_op_field_width(9)
, m_branch_desc{
EMPTY_BRANCH_DESC,
@@ -533,24 +612,55 @@ sparc_disassembler::sparc_disassembler(unsigned version)
add_prftch_desc(V9_PRFTCH_DESC);
}
-}
-
-
-void sparc_disassembler::enable_vis1()
-{
- m_vis_level = std::max(m_vis_level, 1U);
- m_op_field_width = std::max(m_op_field_width, 12);
- add_vis_op_desc(VIS1_OP_DESC);
- add_state_reg_desc(VIS1_STATE_REG_DESC);
- add_asi_desc(VIS1_ASI_DESC);
-}
-
-void sparc_disassembler::enable_vis2()
-{
- enable_vis1();
- m_vis_level = std::max(m_vis_level, 2U);
- add_vis_op_desc(VIS2_OP_DESC);
+ switch (m_vis_level)
+ {
+ case vis_3b:
+ add_vis_op_desc(VIS3B_OP_DESC);
+ case vis_3:
+ add_fpop1_desc(VIS3_FPOP1_DESC);
+ add_vis_op_desc(VIS3_OP_DESC);
+ case vis_2p:
+ add_asi_desc(VIS2P_ASI_DESC);
+ case vis_2:
+ add_vis_op_desc(VIS2_OP_DESC);
+ case vis_1:
+ m_op_field_width = std::max(m_op_field_width, 12);
+ add_vis_op_desc(VIS1_OP_DESC);
+ add_state_reg_desc(VIS1_STATE_REG_DESC);
+ add_asi_desc(VIS1_ASI_DESC);
+ if (m_vis_level >= vis_3)
+ {
+ m_vis_op_desc.find(0x020)->second.mnemonic = "fpcmple16";
+ m_vis_op_desc.find(0x022)->second.mnemonic = "fpcmpne16";
+ m_vis_op_desc.find(0x024)->second.mnemonic = "fpcmple32";
+ m_vis_op_desc.find(0x026)->second.mnemonic = "fpcmpne32";
+ m_vis_op_desc.find(0x028)->second.mnemonic = "fpcmpgt16";
+ m_vis_op_desc.find(0x02a)->second.mnemonic = "fpcmpeq16";
+ m_vis_op_desc.find(0x02c)->second.mnemonic = "fpcmpgt32";
+ m_vis_op_desc.find(0x02e)->second.mnemonic = "fpcmpeq32";
+
+ m_vis_op_desc.find(0x060)->second.mnemonic = "fzerod";
+ m_vis_op_desc.find(0x062)->second.mnemonic = "fnord";
+ m_vis_op_desc.find(0x064)->second.mnemonic = "fandnot2d";
+ m_vis_op_desc.find(0x066)->second.mnemonic = "fnot2d";
+ m_vis_op_desc.find(0x068)->second.mnemonic = "fandnot1d";
+ m_vis_op_desc.find(0x06a)->second.mnemonic = "fnot1d";
+ m_vis_op_desc.find(0x06c)->second.mnemonic = "fxord";
+ m_vis_op_desc.find(0x06e)->second.mnemonic = "fnandd";
+
+ m_vis_op_desc.find(0x070)->second.mnemonic = "fandd";
+ m_vis_op_desc.find(0x072)->second.mnemonic = "fxnord";
+ m_vis_op_desc.find(0x074)->second.mnemonic = "fsrc1d";
+ m_vis_op_desc.find(0x076)->second.mnemonic = "fornot2d";
+ m_vis_op_desc.find(0x078)->second.mnemonic = "fsrc2d";
+ m_vis_op_desc.find(0x07a)->second.mnemonic = "fornot1d";
+ m_vis_op_desc.find(0x07c)->second.mnemonic = "ford";
+ m_vis_op_desc.find(0x07e)->second.mnemonic = "foned";
+ }
+ case vis_none:
+ break;
+ }
}
@@ -1117,10 +1227,25 @@ offs_t sparc_disassembler::dasm_impdep1(char *buf, offs_t pc, UINT32 op) const
dasm_vis_arg(buf, args, it->second.rd, RD);
return 4 | DASMFLAG_SUPPORTED;
}
- else if ((m_vis_level >= 2) && (OPF == 0x081))
+
+ switch (OPF)
{
- print(buf, "%-*s0x%x", m_op_field_width, "siam", IAMODE);
- return 4 | DASMFLAG_SUPPORTED;
+ case 0x081:
+ if (m_vis_level >= vis_2)
+ {
+ print(buf, "%-*s0x%x", m_op_field_width, "siam", IAMODE);
+ return 4 | DASMFLAG_SUPPORTED;
+ }
+ break;
+ case 0x151:
+ case 0x152:
+ if (m_vis_level >= vis_3)
+ {
+ const bool shift(OPF == 0x152);
+ print(buf, "%-*s%%fcc%d,%%f%d,%%f%d", m_op_field_width, (shift) ? "flcmpd" : "flcmps", RD & 3, freg(RS1, shift), freg(RS2, shift));
+ return 4 | DASMFLAG_SUPPORTED;
+ }
+ break;
}
// TODO: driver hook for other kinds of coprocessor?
@@ -1201,6 +1326,12 @@ offs_t sparc_disassembler::dasm_ldst(char *buf, offs_t pc, UINT32 op) const
print(buf, "],%%fsr");
return 4 | DASMFLAG_SUPPORTED;
}
+ else if ((RD == 3) && (m_vis_level >= vis_3b))
+ {
+ print(buf, "%-*s[", m_op_field_width, "ldx");
+ dasm_address(buf, op);
+ print(buf, "],%%efsr");
+ }
break;
case 0x25: // Store floating-point state register
if ((RD == 0) || (RD == 1))
@@ -1371,7 +1502,7 @@ void sparc_disassembler::dasm_vis_arg(char *&output, bool &args, vis_op_desc::ar
{
case vis_op_desc::X:
break;
- case vis_op_desc::I:
+ case vis_op_desc::R:
print(output, args ? ",%s" : "%s", REG_NAMES[reg]);
args = true;
break;
diff --git a/src/devices/cpu/sparc/sparcdasm.h b/src/devices/cpu/sparc/sparcdasm.h
index 986eedacdb7..c292d0c6b23 100644
--- a/src/devices/cpu/sparc/sparcdasm.h
+++ b/src/devices/cpu/sparc/sparcdasm.h
@@ -15,6 +15,8 @@
class sparc_disassembler
{
public:
+ enum vis_level { vis_none, vis_1, vis_2, vis_2p, vis_3, vis_3b };
+
struct asi_desc
{
asi_desc() { }
@@ -43,9 +45,7 @@ public:
typedef std::map<UINT8, prftch_desc> prftch_desc_map;
sparc_disassembler(unsigned version);
-
- void enable_vis1();
- void enable_vis2();
+ sparc_disassembler(unsigned version, vis_level vis);
template <typename T> void add_state_reg_desc(const T &desc)
{
@@ -148,7 +148,7 @@ private:
struct vis_op_desc
{
- enum arg { X, I, Fs, Fd };
+ enum arg { X, R, Fs, Fd };
vis_op_desc() { }
vis_op_desc(arg rs1_, arg rs2_, arg rd_, bool collapse_, const char *mnemonic_) : rs1(rs1_), rs2(rs2_), rd(rd_), collapse(collapse_), mnemonic(mnemonic_) { }
arg rs1 = X;
@@ -218,9 +218,13 @@ private:
static const state_reg_desc_map::value_type VIS1_STATE_REG_DESC[];
static const asi_desc_map::value_type VIS1_ASI_DESC[];
static const vis_op_desc_map::value_type VIS2_OP_DESC[];
+ static const asi_desc_map::value_type VIS2P_ASI_DESC[];
+ static const fpop1_desc_map::value_type VIS3_FPOP1_DESC[];
+ static const vis_op_desc_map::value_type VIS3_OP_DESC[];
+ static const vis_op_desc_map::value_type VIS3B_OP_DESC[];
unsigned m_version;
- unsigned m_vis_level;
+ vis_level m_vis_level;
int m_op_field_width;
branch_desc m_branch_desc[8];
int_op_desc_map m_int_op_desc;
diff --git a/src/tools/unidasm.cpp b/src/tools/unidasm.cpp
index aefde45d1c9..4c5bb0e9cbb 100644
--- a/src/tools/unidasm.cpp
+++ b/src/tools/unidasm.cpp
@@ -10,8 +10,13 @@
#include "emu.h"
#include "cpu/sparc/sparcdasm.h"
+
+#include <algorithm>
+#include <cstring>
+
#include <ctype.h>
+
enum display_type
{
_8bit,
@@ -207,185 +212,178 @@ CPU_DISASSEMBLE( z8 );
CPU_DISASSEMBLE( z80 );
CPU_DISASSEMBLE( z8000 );
-static sparc_disassembler sparcv7_dasm(7);
-static sparc_disassembler sparcv8_dasm(8);
-static sparc_disassembler sparcv9_dasm(9);
-static sparc_disassembler sparcv9vis1_dasm(9);
-static sparc_disassembler sparcv9vis2_dasm(9);
-struct sparc_helper_c
-{
- sparc_helper_c()
- {
- sparcv9vis1_dasm.enable_vis1();
- sparcv9vis2_dasm.enable_vis2();
- }
-} sparc_helper;
-CPU_DISASSEMBLE( sparcv7 ) { return sparcv7_dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
-CPU_DISASSEMBLE( sparcv8 ) { return sparcv8_dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
-CPU_DISASSEMBLE( sparcv9 ) { return sparcv9_dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
-CPU_DISASSEMBLE( sparcv9vis1 ) { return sparcv9vis1_dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
-CPU_DISASSEMBLE( sparcv9vis2 ) { return sparcv9vis2_dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
+CPU_DISASSEMBLE( sparcv7 ) { static sparc_disassembler dasm(7); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
+CPU_DISASSEMBLE(sparcv8) { static sparc_disassembler dasm(8); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
+CPU_DISASSEMBLE(sparcv9) { static sparc_disassembler dasm(9); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
+CPU_DISASSEMBLE(sparcv9vis1) { static sparc_disassembler dasm(9, sparc_disassembler::vis_1); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
+CPU_DISASSEMBLE(sparcv9vis2) { static sparc_disassembler dasm(9, sparc_disassembler::vis_2); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
+CPU_DISASSEMBLE(sparcv9vis2p) { static sparc_disassembler dasm(9, sparc_disassembler::vis_2p); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
+CPU_DISASSEMBLE(sparcv9vis3) { static sparc_disassembler dasm(9, sparc_disassembler::vis_3); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
+CPU_DISASSEMBLE(sparcv9vis3b) { static sparc_disassembler dasm(9, sparc_disassembler::vis_3b); return dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); }
static const dasm_table_entry dasm_table[] =
{
- { "8x300", _16be, 0, CPU_DISASSEMBLE_NAME(n8x300) },
- { "adsp21xx", _24le, -2, CPU_DISASSEMBLE_NAME(adsp21xx) },
- { "alpha8201", _8bit, 0, CPU_DISASSEMBLE_NAME(alpha8201) },
- { "am29000", _32be, 0, CPU_DISASSEMBLE_NAME(am29000) },
- { "amis2000", _8bit, 0, CPU_DISASSEMBLE_NAME(amis2000) },
- { "apexc", _32be, 0, CPU_DISASSEMBLE_NAME(apexc) },
- { "arm", _32le, 0, CPU_DISASSEMBLE_NAME(arm) },
- { "arm_be", _32be, 0, CPU_DISASSEMBLE_NAME(arm_be) },
- { "arm7", _32le, 0, CPU_DISASSEMBLE_NAME(arm7arm) },
- { "arm7_be", _32be, 0, CPU_DISASSEMBLE_NAME(arm7arm_be) },
- { "arm7thumb", _16le, 0, CPU_DISASSEMBLE_NAME(arm7thumb) },
- { "arm7thumbb", _16be, 0, CPU_DISASSEMBLE_NAME(arm7thumb_be) },
- { "asap", _32le, 0, CPU_DISASSEMBLE_NAME(asap) },
- { "avr8", _16le, 0, CPU_DISASSEMBLE_NAME(avr8) },
- { "ccpu", _8bit, 0, CPU_DISASSEMBLE_NAME(ccpu) },
- { "cdp1801", _8bit, 0, CPU_DISASSEMBLE_NAME(cdp1801) },
- { "cdp1802", _8bit, 0, CPU_DISASSEMBLE_NAME(cdp1802) },
- { "coldfire", _16be, 0, CPU_DISASSEMBLE_NAME(coldfire) },
- { "cop410", _8bit, 0, CPU_DISASSEMBLE_NAME(cop410) },
- { "cop420", _8bit, 0, CPU_DISASSEMBLE_NAME(cop420) },
- { "cop444", _8bit, 0, CPU_DISASSEMBLE_NAME(cop444) },
- { "cp1610", _16be, -1, CPU_DISASSEMBLE_NAME(cp1610) },
- { "cquestlin", _64be, -3, CPU_DISASSEMBLE_NAME(cquestlin) },
- { "cquestrot", _64be, -3, CPU_DISASSEMBLE_NAME(cquestrot) },
- { "cquestsnd", _64be, -3, CPU_DISASSEMBLE_NAME(cquestsnd) },
- { "ds5002fp", _8bit, 0, CPU_DISASSEMBLE_NAME(ds5002fp) },
- { "dsp16a", _16le, -1, CPU_DISASSEMBLE_NAME(dsp16a) },
- { "dsp32c", _32le, 0, CPU_DISASSEMBLE_NAME(dsp32c) },
- { "dsp56k", _16le, -1, CPU_DISASSEMBLE_NAME(dsp56k) },
- { "e0c6200", _16be, -1, CPU_DISASSEMBLE_NAME(e0c6200) },
- { "esrip", _64be, 0, CPU_DISASSEMBLE_NAME(esrip) },
- { "f8", _8bit, 0, CPU_DISASSEMBLE_NAME(f8) },
- { "g65816", _8bit, 0, CPU_DISASSEMBLE_NAME(g65816_generic) },
- { "h6280", _8bit, 0, CPU_DISASSEMBLE_NAME(h6280) },
-// { "h8", _16be, 0, CPU_DISASSEMBLE_NAME(h8) },
-// { "h8_24", _16be, 0, CPU_DISASSEMBLE_NAME(h8_24) },
-// { "h8_32", _16be, 0, CPU_DISASSEMBLE_NAME(h8_32) },
- { "hc11", _8bit, 0, CPU_DISASSEMBLE_NAME(mb88) },
- { "hcd62121", _16be, 0, CPU_DISASSEMBLE_NAME(hcd62121) },
- { "hd61700", _8bit, 0, CPU_DISASSEMBLE_NAME(hd61700) },
- { "hd6301", _8bit, 0, CPU_DISASSEMBLE_NAME(hd6301) },
- { "hd6309", _8bit, 0, CPU_DISASSEMBLE_NAME(hd6309) },
- { "hd63701", _8bit, 0, CPU_DISASSEMBLE_NAME(hd63701) },
- { "hmcs40", _16le, -1, CPU_DISASSEMBLE_NAME(hmcs40) },
- { "hyperstone", _16be, 0, CPU_DISASSEMBLE_NAME(hyperstone_generic) },
- { "i4004", _8bit, 0, CPU_DISASSEMBLE_NAME(i4004) },
- { "i8008", _8bit, 0, CPU_DISASSEMBLE_NAME(i8008) },
- { "i8051", _8bit, 0, CPU_DISASSEMBLE_NAME(i8051) },
- { "i8052", _8bit, 0, CPU_DISASSEMBLE_NAME(i8052) },
- { "i8085", _8bit, 0, CPU_DISASSEMBLE_NAME(i8085) },
- { "i8089", _8bit, 0, CPU_DISASSEMBLE_NAME(i8089) },
- { "i80c51", _8bit, 0, CPU_DISASSEMBLE_NAME(i80c51) },
- { "i80c52", _8bit, 0, CPU_DISASSEMBLE_NAME(i80c52) },
- { "i860", _64le, 0, CPU_DISASSEMBLE_NAME(i860) },
- { "i960", _32le, 0, CPU_DISASSEMBLE_NAME(i960) },
- { "ie15", _8bit, 0, CPU_DISASSEMBLE_NAME(ie15) },
- { "jaguardsp", _16be, 0, CPU_DISASSEMBLE_NAME(jaguardsp) },
- { "jaguargpu", _16be, 0, CPU_DISASSEMBLE_NAME(jaguargpu) },
- { "kb1013vk12", _8bit, 0, CPU_DISASSEMBLE_NAME(kb1013vk12) },
- { "konami", _8bit, 0, CPU_DISASSEMBLE_NAME(konami) },
- { "lh5801", _8bit, 0, CPU_DISASSEMBLE_NAME(lh5801) },
- { "lr35902", _8bit, 0, CPU_DISASSEMBLE_NAME(lr35902) },
- { "m58846", _16le, -1, CPU_DISASSEMBLE_NAME(m58846) },
- { "m37710", _8bit, 0, CPU_DISASSEMBLE_NAME(m37710_generic) },
- { "m6800", _8bit, 0, CPU_DISASSEMBLE_NAME(m6800) },
- { "m68000", _16be, 0, CPU_DISASSEMBLE_NAME(m68000) },
- { "m68008", _16be, 0, CPU_DISASSEMBLE_NAME(m68008) },
- { "m6801", _8bit, 0, CPU_DISASSEMBLE_NAME(m6801) },
- { "m68010", _16be, 0, CPU_DISASSEMBLE_NAME(m68010) },
- { "m6802", _8bit, 0, CPU_DISASSEMBLE_NAME(m6802) },
- { "m68020", _16be, 0, CPU_DISASSEMBLE_NAME(m68020) },
- { "m6803", _8bit, 0, CPU_DISASSEMBLE_NAME(m6803) },
- { "m68030", _16be, 0, CPU_DISASSEMBLE_NAME(m68030) },
- { "m68040", _16be, 0, CPU_DISASSEMBLE_NAME(m68040) },
- { "m6805", _8bit, 0, CPU_DISASSEMBLE_NAME(m6805) },
- { "m6808", _8bit, 0, CPU_DISASSEMBLE_NAME(m6808) },
- { "m6809", _8bit, 0, CPU_DISASSEMBLE_NAME(m6809) },
- { "m68340", _16be, 0, CPU_DISASSEMBLE_NAME(m68340) },
- { "mb86233", _32le, -2, CPU_DISASSEMBLE_NAME(mb86233) },
- { "mb88", _8bit, 0, CPU_DISASSEMBLE_NAME(mb88) },
- { "mcs48", _8bit, 0, CPU_DISASSEMBLE_NAME(mcs48) },
- { "minx", _8bit, 0, CPU_DISASSEMBLE_NAME(minx) },
- { "mips3be", _32be, 0, CPU_DISASSEMBLE_NAME(mips3be) },
- { "mips3le", _32le, 0, CPU_DISASSEMBLE_NAME(mips3le) },
- { "mn10200", _16le, 0, CPU_DISASSEMBLE_NAME(mn10200) },
- { "nec", _8bit, 0, CPU_DISASSEMBLE_NAME(nec) },
- { "nsc8105", _8bit, 0, CPU_DISASSEMBLE_NAME(nsc8105) },
- { "pdp1", _32be, 0, CPU_DISASSEMBLE_NAME(pdp1) },
- { "pic16c5x", _16le, -1, CPU_DISASSEMBLE_NAME(pic16c5x) },
- { "pic16c62x", _16le, -1, CPU_DISASSEMBLE_NAME(pic16c62x) },
- { "powerpc", _32be, 0, CPU_DISASSEMBLE_NAME(powerpc) },
- { "pps4", _8bit, 0, CPU_DISASSEMBLE_NAME(pps4) },
- { "psxcpu", _32le, 0, CPU_DISASSEMBLE_NAME(psxcpu_generic) },
- { "r3000be", _32be, 0, CPU_DISASSEMBLE_NAME(r3000be) },
- { "r3000le", _32le, 0, CPU_DISASSEMBLE_NAME(r3000le) },
- { "rsp", _32le, 0, CPU_DISASSEMBLE_NAME(rsp) },
- { "s2650", _8bit, 0, CPU_DISASSEMBLE_NAME(s2650) },
- { "saturn", _8bit, 0, CPU_DISASSEMBLE_NAME(saturn) },
- { "sc61860", _8bit, 0, CPU_DISASSEMBLE_NAME(sc61860) },
- { "scmp", _8bit, 0, CPU_DISASSEMBLE_NAME(scmp) },
- { "scudsp", _32be, 0, CPU_DISASSEMBLE_NAME(scudsp) },
- { "se3208", _16le, 0, CPU_DISASSEMBLE_NAME(se3208) },
- { "sh2", _16be, 0, CPU_DISASSEMBLE_NAME(sh2) },
- { "sh4", _16le, 0, CPU_DISASSEMBLE_NAME(sh4) },
- { "sh4be", _16be, 0, CPU_DISASSEMBLE_NAME(sh4be) },
- { "sharc", _48le, -2, CPU_DISASSEMBLE_NAME(sharc) },
- { "sm500", _8bit, 0, CPU_DISASSEMBLE_NAME(sm500) },
- { "sm510", _8bit, 0, CPU_DISASSEMBLE_NAME(sm510) },
- { "sm511", _8bit, 0, CPU_DISASSEMBLE_NAME(sm511) },
- { "sm8500", _8bit, 0, CPU_DISASSEMBLE_NAME(sm8500) },
- { "sparcv7", _32be, 0, CPU_DISASSEMBLE_NAME(sparcv7) },
- { "sparcv8", _32be, 0, CPU_DISASSEMBLE_NAME(sparcv8) },
- { "sparcv9", _32be, 0, CPU_DISASSEMBLE_NAME(sparcv9) },
- { "sparcv9vis1",_32be, 0, CPU_DISASSEMBLE_NAME(sparcv9vis1) },
- { "sparcv9vis2",_32be, 0, CPU_DISASSEMBLE_NAME(sparcv9vis2) },
- { "spc700", _8bit, 0, CPU_DISASSEMBLE_NAME(spc700) },
- { "ssem", _32le, 0, CPU_DISASSEMBLE_NAME(ssem) },
- { "ssp1601", _16be, -1, CPU_DISASSEMBLE_NAME(ssp1601) },
-// { "superfx", _8bit, 0, CPU_DISASSEMBLE_NAME(superfx) },
- { "t11", _16le, 0, CPU_DISASSEMBLE_NAME(t11) },
-// { "t90", _8bit, 0, CPU_DISASSEMBLE_NAME(t90) },
- { "tlcs900", _8bit, 0, CPU_DISASSEMBLE_NAME(tlcs900) },
- { "tms0980", _16be, 0, CPU_DISASSEMBLE_NAME(tms0980) },
- { "tms1000", _8bit, 0, CPU_DISASSEMBLE_NAME(tms1000) },
- { "tms1100", _8bit, 0, CPU_DISASSEMBLE_NAME(tms1100) },
- { "tms32010", _16be, -1, CPU_DISASSEMBLE_NAME(tms32010) },
- { "tms32025", _16be, -1, CPU_DISASSEMBLE_NAME(tms32025) },
- { "tms3203x", _32le, -2, CPU_DISASSEMBLE_NAME(tms3203x) },
- { "tms32051", _16le, -1, CPU_DISASSEMBLE_NAME(tms32051) },
- { "tms34010", _8bit, 3, CPU_DISASSEMBLE_NAME(tms34010) },
- { "tms34020", _8bit, 3, CPU_DISASSEMBLE_NAME(tms34020) },
- { "tms57002", _32le, -2, CPU_DISASSEMBLE_NAME(tms57002) },
- { "tms7000", _8bit, 0, CPU_DISASSEMBLE_NAME(tms7000) },
- { "tms9900", _16be, 0, CPU_DISASSEMBLE_NAME(tms9900) },
- { "tms9980", _8bit, 0, CPU_DISASSEMBLE_NAME(tms9980) },
- { "tms9995", _8bit, 0, CPU_DISASSEMBLE_NAME(tms9995) },
- { "tp0320", _16be, 0, CPU_DISASSEMBLE_NAME(tp0320) },
- { "tx0_64kw", _32be, -2, CPU_DISASSEMBLE_NAME(tx0_64kw) },
- { "tx0_8kw", _32be, -2, CPU_DISASSEMBLE_NAME(tx0_8kw) },
- { "ucom4", _8bit, 0, CPU_DISASSEMBLE_NAME(ucom4) },
- { "unsp", _16be, 0, CPU_DISASSEMBLE_NAME(unsp) },
- { "upd7725", _32be, 0, CPU_DISASSEMBLE_NAME(unsp) },
- { "upd7801", _8bit, 0, CPU_DISASSEMBLE_NAME(upd7801) },
- { "upd7807", _8bit, 0, CPU_DISASSEMBLE_NAME(upd7807) },
- { "upd7810", _8bit, 0, CPU_DISASSEMBLE_NAME(upd7810) },
- { "upd78c05", _8bit, 0, CPU_DISASSEMBLE_NAME(upd78c05) },
- { "upi41", _8bit, 0, CPU_DISASSEMBLE_NAME(upi41) },
- { "v60", _8bit, 0, CPU_DISASSEMBLE_NAME(v60) },
- { "v70", _8bit, 0, CPU_DISASSEMBLE_NAME(v70) },
- { "v810", _16le, 0, CPU_DISASSEMBLE_NAME(v810) },
- { "x86_16", _8bit, 0, CPU_DISASSEMBLE_NAME(x86_16) },
- { "x86_32", _8bit, 0, CPU_DISASSEMBLE_NAME(x86_32) },
- { "x86_64", _8bit, 0, CPU_DISASSEMBLE_NAME(x86_64) },
- { "z180", _8bit, 0, CPU_DISASSEMBLE_NAME(z180) },
- { "z8", _8bit, 0, CPU_DISASSEMBLE_NAME(z8) },
- { "z80", _8bit, 0, CPU_DISASSEMBLE_NAME(z80) },
-// { "z8000", _16be, 0, CPU_DISASSEMBLE_NAME(z8000) },
+ { "8x300", _16be, 0, CPU_DISASSEMBLE_NAME(n8x300) },
+ { "adsp21xx", _24le, -2, CPU_DISASSEMBLE_NAME(adsp21xx) },
+ { "alpha8201", _8bit, 0, CPU_DISASSEMBLE_NAME(alpha8201) },
+ { "am29000", _32be, 0, CPU_DISASSEMBLE_NAME(am29000) },
+ { "amis2000", _8bit, 0, CPU_DISASSEMBLE_NAME(amis2000) },
+ { "apexc", _32be, 0, CPU_DISASSEMBLE_NAME(apexc) },
+ { "arm", _32le, 0, CPU_DISASSEMBLE_NAME(arm) },
+ { "arm_be", _32be, 0, CPU_DISASSEMBLE_NAME(arm_be) },
+ { "arm7", _32le, 0, CPU_DISASSEMBLE_NAME(arm7arm) },
+ { "arm7_be", _32be, 0, CPU_DISASSEMBLE_NAME(arm7arm_be) },
+ { "arm7thumb", _16le, 0, CPU_DISASSEMBLE_NAME(arm7thumb) },
+ { "arm7thumbb", _16be, 0, CPU_DISASSEMBLE_NAME(arm7thumb_be) },
+ { "asap", _32le, 0, CPU_DISASSEMBLE_NAME(asap) },
+ { "avr8", _16le, 0, CPU_DISASSEMBLE_NAME(avr8) },
+ { "ccpu", _8bit, 0, CPU_DISASSEMBLE_NAME(ccpu) },
+ { "cdp1801", _8bit, 0, CPU_DISASSEMBLE_NAME(cdp1801) },
+ { "cdp1802", _8bit, 0, CPU_DISASSEMBLE_NAME(cdp1802) },
+ { "coldfire", _16be, 0, CPU_DISASSEMBLE_NAME(coldfire) },
+ { "cop410", _8bit, 0, CPU_DISASSEMBLE_NAME(cop410) },
+ { "cop420", _8bit, 0, CPU_DISASSEMBLE_NAME(cop420) },
+ { "cop444", _8bit, 0, CPU_DISASSEMBLE_NAME(cop444) },
+ { "cp1610", _16be, -1, CPU_DISASSEMBLE_NAME(cp1610) },
+ { "cquestlin", _64be, -3, CPU_DISASSEMBLE_NAME(cquestlin) },
+ { "cquestrot", _64be, -3, CPU_DISASSEMBLE_NAME(cquestrot) },
+ { "cquestsnd", _64be, -3, CPU_DISASSEMBLE_NAME(cquestsnd) },
+ { "ds5002fp", _8bit, 0, CPU_DISASSEMBLE_NAME(ds5002fp) },
+ { "dsp16a", _16le, -1, CPU_DISASSEMBLE_NAME(dsp16a) },
+ { "dsp32c", _32le, 0, CPU_DISASSEMBLE_NAME(dsp32c) },
+ { "dsp56k", _16le, -1, CPU_DISASSEMBLE_NAME(dsp56k) },
+ { "e0c6200", _16be, -1, CPU_DISASSEMBLE_NAME(e0c6200) },
+ { "esrip", _64be, 0, CPU_DISASSEMBLE_NAME(esrip) },
+ { "f8", _8bit, 0, CPU_DISASSEMBLE_NAME(f8) },
+ { "g65816", _8bit, 0, CPU_DISASSEMBLE_NAME(g65816_generic) },
+ { "h6280", _8bit, 0, CPU_DISASSEMBLE_NAME(h6280) },
+// { "h8", _16be, 0, CPU_DISASSEMBLE_NAME(h8) },
+// { "h8_24", _16be, 0, CPU_DISASSEMBLE_NAME(h8_24) },
+// { "h8_32", _16be, 0, CPU_DISASSEMBLE_NAME(h8_32) },
+ { "hc11", _8bit, 0, CPU_DISASSEMBLE_NAME(mb88) },
+ { "hcd62121", _16be, 0, CPU_DISASSEMBLE_NAME(hcd62121) },
+ { "hd61700", _8bit, 0, CPU_DISASSEMBLE_NAME(hd61700) },
+ { "hd6301", _8bit, 0, CPU_DISASSEMBLE_NAME(hd6301) },
+ { "hd6309", _8bit, 0, CPU_DISASSEMBLE_NAME(hd6309) },
+ { "hd63701", _8bit, 0, CPU_DISASSEMBLE_NAME(hd63701) },
+ { "hmcs40", _16le, -1, CPU_DISASSEMBLE_NAME(hmcs40) },
+ { "hyperstone", _16be, 0, CPU_DISASSEMBLE_NAME(hyperstone_generic) },
+ { "i4004", _8bit, 0, CPU_DISASSEMBLE_NAME(i4004) },
+ { "i8008", _8bit, 0, CPU_DISASSEMBLE_NAME(i8008) },
+ { "i8051", _8bit, 0, CPU_DISASSEMBLE_NAME(i8051) },
+ { "i8052", _8bit, 0, CPU_DISASSEMBLE_NAME(i8052) },
+ { "i8085", _8bit, 0, CPU_DISASSEMBLE_NAME(i8085) },
+ { "i8089", _8bit, 0, CPU_DISASSEMBLE_NAME(i8089) },
+ { "i80c51", _8bit, 0, CPU_DISASSEMBLE_NAME(i80c51) },
+ { "i80c52", _8bit, 0, CPU_DISASSEMBLE_NAME(i80c52) },
+ { "i860", _64le, 0, CPU_DISASSEMBLE_NAME(i860) },
+ { "i960", _32le, 0, CPU_DISASSEMBLE_NAME(i960) },
+ { "ie15", _8bit, 0, CPU_DISASSEMBLE_NAME(ie15) },
+ { "jaguardsp", _16be, 0, CPU_DISASSEMBLE_NAME(jaguardsp) },
+ { "jaguargpu", _16be, 0, CPU_DISASSEMBLE_NAME(jaguargpu) },
+ { "kb1013vk12", _8bit, 0, CPU_DISASSEMBLE_NAME(kb1013vk12) },
+ { "konami", _8bit, 0, CPU_DISASSEMBLE_NAME(konami) },
+ { "lh5801", _8bit, 0, CPU_DISASSEMBLE_NAME(lh5801) },
+ { "lr35902", _8bit, 0, CPU_DISASSEMBLE_NAME(lr35902) },
+ { "m58846", _16le, -1, CPU_DISASSEMBLE_NAME(m58846) },
+ { "m37710", _8bit, 0, CPU_DISASSEMBLE_NAME(m37710_generic) },
+ { "m6800", _8bit, 0, CPU_DISASSEMBLE_NAME(m6800) },
+ { "m68000", _16be, 0, CPU_DISASSEMBLE_NAME(m68000) },
+ { "m68008", _16be, 0, CPU_DISASSEMBLE_NAME(m68008) },
+ { "m6801", _8bit, 0, CPU_DISASSEMBLE_NAME(m6801) },
+ { "m68010", _16be, 0, CPU_DISASSEMBLE_NAME(m68010) },
+ { "m6802", _8bit, 0, CPU_DISASSEMBLE_NAME(m6802) },
+ { "m68020", _16be, 0, CPU_DISASSEMBLE_NAME(m68020) },
+ { "m6803", _8bit, 0, CPU_DISASSEMBLE_NAME(m6803) },
+ { "m68030", _16be, 0, CPU_DISASSEMBLE_NAME(m68030) },
+ { "m68040", _16be, 0, CPU_DISASSEMBLE_NAME(m68040) },
+ { "m6805", _8bit, 0, CPU_DISASSEMBLE_NAME(m6805) },
+ { "m6808", _8bit, 0, CPU_DISASSEMBLE_NAME(m6808) },
+ { "m6809", _8bit, 0, CPU_DISASSEMBLE_NAME(m6809) },
+ { "m68340", _16be, 0, CPU_DISASSEMBLE_NAME(m68340) },
+ { "mb86233", _32le, -2, CPU_DISASSEMBLE_NAME(mb86233) },
+ { "mb88", _8bit, 0, CPU_DISASSEMBLE_NAME(mb88) },
+ { "mcs48", _8bit, 0, CPU_DISASSEMBLE_NAME(mcs48) },
+ { "minx", _8bit, 0, CPU_DISASSEMBLE_NAME(minx) },
+ { "mips3be", _32be, 0, CPU_DISASSEMBLE_NAME(mips3be) },
+ { "mips3le", _32le, 0, CPU_DISASSEMBLE_NAME(mips3le) },
+ { "mn10200", _16le, 0, CPU_DISASSEMBLE_NAME(mn10200) },
+ { "nec", _8bit, 0, CPU_DISASSEMBLE_NAME(nec) },
+ { "nsc8105", _8bit, 0, CPU_DISASSEMBLE_NAME(nsc8105) },
+ { "pdp1", _32be, 0, CPU_DISASSEMBLE_NAME(pdp1) },
+ { "pic16c5x", _16le, -1, CPU_DISASSEMBLE_NAME(pic16c5x) },
+ { "pic16c62x", _16le, -1, CPU_DISASSEMBLE_NAME(pic16c62x) },
+ { "powerpc", _32be, 0, CPU_DISASSEMBLE_NAME(powerpc) },
+ { "pps4", _8bit, 0, CPU_DISASSEMBLE_NAME(pps4) },
+ { "psxcpu", _32le, 0, CPU_DISASSEMBLE_NAME(psxcpu_generic) },
+ { "r3000be", _32be, 0, CPU_DISASSEMBLE_NAME(r3000be) },
+ { "r3000le", _32le, 0, CPU_DISASSEMBLE_NAME(r3000le) },
+ { "rsp", _32le, 0, CPU_DISASSEMBLE_NAME(rsp) },
+ { "s2650", _8bit, 0, CPU_DISASSEMBLE_NAME(s2650) },
+ { "saturn", _8bit, 0, CPU_DISASSEMBLE_NAME(saturn) },
+ { "sc61860", _8bit, 0, CPU_DISASSEMBLE_NAME(sc61860) },
+ { "scmp", _8bit, 0, CPU_DISASSEMBLE_NAME(scmp) },
+ { "scudsp", _32be, 0, CPU_DISASSEMBLE_NAME(scudsp) },
+ { "se3208", _16le, 0, CPU_DISASSEMBLE_NAME(se3208) },
+ { "sh2", _16be, 0, CPU_DISASSEMBLE_NAME(sh2) },
+ { "sh4", _16le, 0, CPU_DISASSEMBLE_NAME(sh4) },
+ { "sh4be", _16be, 0, CPU_DISASSEMBLE_NAME(sh4be) },
+ { "sharc", _48le, -2, CPU_DISASSEMBLE_NAME(sharc) },
+ { "sm500", _8bit, 0, CPU_DISASSEMBLE_NAME(sm500) },
+ { "sm510", _8bit, 0, CPU_DISASSEMBLE_NAME(sm510) },
+ { "sm511", _8bit, 0, CPU_DISASSEMBLE_NAME(sm511) },
+ { "sm8500", _8bit, 0, CPU_DISASSEMBLE_NAME(sm8500) },
+ { "sparcv7", _32be, 0, CPU_DISASSEMBLE_NAME(sparcv7) },
+ { "sparcv8", _32be, 0, CPU_DISASSEMBLE_NAME(sparcv8) },
+ { "sparcv9", _32be, 0, CPU_DISASSEMBLE_NAME(sparcv9) },
+ { "sparcv9vis1", _32be, 0, CPU_DISASSEMBLE_NAME(sparcv9vis1) },
+ { "sparcv9vis2", _32be, 0, CPU_DISASSEMBLE_NAME(sparcv9vis2) },
+ { "sparcv9vis2p",_32be, 0, CPU_DISASSEMBLE_NAME(sparcv9vis2p) },
+ { "sparcv9vis3", _32be, 0, CPU_DISASSEMBLE_NAME(sparcv9vis3) },
+ { "sparcv9vis3b",_32be, 0, CPU_DISASSEMBLE_NAME(sparcv9vis3b) },
+ { "spc700", _8bit, 0, CPU_DISASSEMBLE_NAME(spc700) },
+ { "ssem", _32le, 0, CPU_DISASSEMBLE_NAME(ssem) },
+ { "ssp1601", _16be, -1, CPU_DISASSEMBLE_NAME(ssp1601) },
+// { "superfx", _8bit, 0, CPU_DISASSEMBLE_NAME(superfx) },
+ { "t11", _16le, 0, CPU_DISASSEMBLE_NAME(t11) },
+// { "t90", _8bit, 0, CPU_DISASSEMBLE_NAME(t90) },
+ { "tlcs900", _8bit, 0, CPU_DISASSEMBLE_NAME(tlcs900) },
+ { "tms0980", _16be, 0, CPU_DISASSEMBLE_NAME(tms0980) },
+ { "tms1000", _8bit, 0, CPU_DISASSEMBLE_NAME(tms1000) },
+ { "tms1100", _8bit, 0, CPU_DISASSEMBLE_NAME(tms1100) },
+ { "tms32010", _16be, -1, CPU_DISASSEMBLE_NAME(tms32010) },
+ { "tms32025", _16be, -1, CPU_DISASSEMBLE_NAME(tms32025) },
+ { "tms3203x", _32le, -2, CPU_DISASSEMBLE_NAME(tms3203x) },
+ { "tms32051", _16le, -1, CPU_DISASSEMBLE_NAME(tms32051) },
+ { "tms34010", _8bit, 3, CPU_DISASSEMBLE_NAME(tms34010) },
+ { "tms34020", _8bit, 3, CPU_DISASSEMBLE_NAME(tms34020) },
+ { "tms57002", _32le, -2, CPU_DISASSEMBLE_NAME(tms57002) },
+ { "tms7000", _8bit, 0, CPU_DISASSEMBLE_NAME(tms7000) },
+ { "tms9900", _16be, 0, CPU_DISASSEMBLE_NAME(tms9900) },
+ { "tms9980", _8bit, 0, CPU_DISASSEMBLE_NAME(tms9980) },
+ { "tms9995", _8bit, 0, CPU_DISASSEMBLE_NAME(tms9995) },
+ { "tp0320", _16be, 0, CPU_DISASSEMBLE_NAME(tp0320) },
+ { "tx0_64kw", _32be, -2, CPU_DISASSEMBLE_NAME(tx0_64kw) },
+ { "tx0_8kw", _32be, -2, CPU_DISASSEMBLE_NAME(tx0_8kw) },
+ { "ucom4", _8bit, 0, CPU_DISASSEMBLE_NAME(ucom4) },
+ { "unsp", _16be, 0, CPU_DISASSEMBLE_NAME(unsp) },
+ { "upd7725", _32be, 0, CPU_DISASSEMBLE_NAME(unsp) },
+ { "upd7801", _8bit, 0, CPU_DISASSEMBLE_NAME(upd7801) },
+ { "upd7807", _8bit, 0, CPU_DISASSEMBLE_NAME(upd7807) },
+ { "upd7810", _8bit, 0, CPU_DISASSEMBLE_NAME(upd7810) },
+ { "upd78c05", _8bit, 0, CPU_DISASSEMBLE_NAME(upd78c05) },
+ { "upi41", _8bit, 0, CPU_DISASSEMBLE_NAME(upi41) },
+ { "v60", _8bit, 0, CPU_DISASSEMBLE_NAME(v60) },
+ { "v70", _8bit, 0, CPU_DISASSEMBLE_NAME(v70) },
+ { "v810", _16le, 0, CPU_DISASSEMBLE_NAME(v810) },
+ { "x86_16", _8bit, 0, CPU_DISASSEMBLE_NAME(x86_16) },
+ { "x86_32", _8bit, 0, CPU_DISASSEMBLE_NAME(x86_32) },
+ { "x86_64", _8bit, 0, CPU_DISASSEMBLE_NAME(x86_64) },
+ { "z180", _8bit, 0, CPU_DISASSEMBLE_NAME(z180) },
+ { "z8", _8bit, 0, CPU_DISASSEMBLE_NAME(z8) },
+ { "z80", _8bit, 0, CPU_DISASSEMBLE_NAME(z80) },
+// { "z8000", _16be, 0, CPU_DISASSEMBLE_NAME(z8000) },
};
@@ -396,14 +394,11 @@ static int parse_options(int argc, char *argv[], options *opts)
int pending_mode = FALSE;
int pending_skip = FALSE;
int pending_count = FALSE;
- int curarch;
- int numrows;
- int arg;
memset(opts, 0, sizeof(*opts));
// loop through arguments
- for (arg = 1; arg < argc; arg++)
+ for (unsigned arg = 1; arg < argc; arg++)
{
char *curarg = argv[arg];
@@ -461,6 +456,7 @@ static int parse_options(int argc, char *argv[], options *opts)
// architecture
else if (pending_arch)
{
+ int curarch;
for (curarch = 0; curarch < ARRAY_LENGTH(dasm_table); curarch++)
if (core_stricmp(curarg, dasm_table[curarch].name) == 0)
break;
@@ -510,15 +506,17 @@ usage:
printf(" [-skip <n>] [-count <n>]\n");
printf("\n");
printf("Supported architectures:");
- numrows = (ARRAY_LENGTH(dasm_table) + 5) / 6;
- for (curarch = 0; curarch < numrows * 6; curarch++)
+ const int colwidth = 1 + std::strlen(std::max_element(std::begin(dasm_table), std::end(dasm_table), [](const dasm_table_entry &a, const dasm_table_entry &b) { return std::strlen(a.name) < std::strlen(b.name); })->name);
+ const int columns = std::max(1, 80 / colwidth);
+ const int numrows = (ARRAY_LENGTH(dasm_table) + columns - 1) / columns;
+ for (unsigned curarch = 0; curarch < numrows * columns; curarch++)
{
- int row = curarch / 6;
- int col = curarch % 6;
- int index = col * numrows + row;
+ const int row = curarch / columns;
+ const int col = curarch % columns;
+ const int index = col * numrows + row;
if (col == 0)
printf("\n ");
- printf("%-12s", (index < ARRAY_LENGTH(dasm_table)) ? dasm_table[index].name : "");
+ printf("%-*s", colwidth, (index < ARRAY_LENGTH(dasm_table)) ? dasm_table[index].name : "");
}
printf("\n");
return 1;