diff options
| author | 2021-11-21 14:14:44 +1100 | |
|---|---|---|
| committer | 2021-11-21 14:14:44 +1100 | |
| commit | 637eaca7a4ee0f7ca01162931806ac4d65e56630 (patch) | |
| tree | 43a8bd97b49d54f8de086dd76e9c82036c629f69 /src | |
| parent | 7a68283de7f328af7bae232a41947c4d760c5dd3 (diff) | |
srcclean in preparation for release of MAME 0.238.
Patched up positron.cpp input ports - you shouldn’t use PORT_NAME when
the key cap label is just the characters it produces anyway, and you’re
supposed to use the actual character a key produces for PORT_CHAR or
"natural" keyboard mode/paste will be unnatural.
Diffstat (limited to 'src')
25 files changed, 475 insertions, 472 deletions
diff --git a/src/devices/bus/nes/mmc3_clones.cpp b/src/devices/bus/nes/mmc3_clones.cpp index 2021976a97f..b7b9bb6d5a2 100644 --- a/src/devices/bus/nes/mmc3_clones.cpp +++ b/src/devices/bus/nes/mmc3_clones.cpp @@ -1089,7 +1089,7 @@ void nes_bmw8544_device::set_prg(int prg_base, int prg_mask) u8 nes_bmw8544_device::read_m(offs_t offset) { -// LOG_MMC(("bmw8544 read_m, offset: %04x\n", offset)); +// LOG_MMC(("bmw8544 read_m, offset: %04x\n", offset)); // CHR banking may be done by reads in this address range diff --git a/src/devices/bus/snes/sa1.cpp b/src/devices/bus/snes/sa1.cpp index dffdba37ca8..dc2307d7a14 100644 --- a/src/devices/bus/snes/sa1.cpp +++ b/src/devices/bus/snes/sa1.cpp @@ -1136,7 +1136,7 @@ u8 sns_sa1_device::rom_r(offs_t offset) else // when HiROM mapping is enabled, we mirror [(cx,dx,ex,fx)][0000-ffff] bank bank = BIT(offset, 16, 5) | (m_bank_rom[slot] << 5); - ret = m_rom[(rom_bank_map[bank] << 15) | (offset & 0x7fff)]; + ret = m_rom[(rom_bank_map[bank] << 15) | (offset & 0x7fff)]; } return ret; } diff --git a/src/devices/bus/snes/sa1.h b/src/devices/bus/snes/sa1.h index 8126e11c247..ccb6affc2fa 100644 --- a/src/devices/bus/snes/sa1.h +++ b/src/devices/bus/snes/sa1.h @@ -120,10 +120,10 @@ private: /* enum super_mmc_t { - CXB = 0, - DXB = 1, - EXB = 2, - FXB = 3 + CXB = 0, + DXB = 1, + EXB = 2, + FXB = 3 }; */ bool m_bank_hi[4]; @@ -144,7 +144,7 @@ private: // DMA Control (DCNT) inline const bool DCNT_DMAEN() { return BIT(m_dma_ctrl, 7); } // DMA Enable control //inline const bool DCNT_DPRIO() { return BIT(m_dma_ctrl, 6); } // Processing priority between SA-1 CPU and DMA; Not emulated currently - inline const bool DCNT_CDEN() { return BIT(m_dma_ctrl, 5); } // DMA mode selection (Normal/Character conversion) + inline const bool DCNT_CDEN() { return BIT(m_dma_ctrl, 5); } // DMA mode selection (Normal/Character conversion) inline const bool DCNT_CDSEL() { return BIT(m_dma_ctrl, 4); } // Character conversion DMA type inline const bool DCNT_DD() { return BIT(m_dma_ctrl, 2); } // Destination device (IRAM, BWRAM) inline const u8 DCNT_SD() { return BIT(m_dma_ctrl, 0, 1); } // Source device (ROM, IRAM, BWRAM) diff --git a/src/devices/bus/vme/vme_hcpu30.cpp b/src/devices/bus/vme/vme_hcpu30.cpp index 13c840dbbdb..8c90410b21c 100644 --- a/src/devices/bus/vme/vme_hcpu30.cpp +++ b/src/devices/bus/vme/vme_hcpu30.cpp @@ -189,14 +189,14 @@ void vme_hcpu30_card_device::device_add_mconfig(machine_config &config) m_dusccterm->out_txda_callback().set(RS232P1_TAG, FUNC(rs232_port_device::write_txd)); m_dusccterm->out_dtra_callback().set(RS232P1_TAG, FUNC(rs232_port_device::write_dtr)); m_dusccterm->out_rtsa_callback().set(RS232P1_TAG, FUNC(rs232_port_device::write_rts)); -// m_dusccterm->out_dtra_callback().set(m_dusccterm, FUNC(duscc68562_device::dcda_w)); -// m_dusccterm->out_rtsa_callback().set(m_dusccterm, FUNC(duscc68562_device::ctsa_w)); +// m_dusccterm->out_dtra_callback().set(m_dusccterm, FUNC(duscc68562_device::dcda_w)); +// m_dusccterm->out_rtsa_callback().set(m_dusccterm, FUNC(duscc68562_device::ctsa_w)); m_dusccterm->out_txdb_callback().set(RS232P2_TAG, FUNC(rs232_port_device::write_txd)); m_dusccterm->out_dtrb_callback().set(RS232P2_TAG, FUNC(rs232_port_device::write_dtr)); m_dusccterm->out_rtsb_callback().set(RS232P2_TAG, FUNC(rs232_port_device::write_rts)); -// m_dusccterm->out_txdb_callback().set(m_dusccterm, FUNC(duscc68562_device::rxb_w)); -// m_dusccterm->out_dtrb_callback().set(m_dusccterm, FUNC(duscc68562_device::dcdb_w)); -// m_dusccterm->out_rtsb_callback().set(m_dusccterm, FUNC(duscc68562_device::ctsb_w)); +// m_dusccterm->out_txdb_callback().set(m_dusccterm, FUNC(duscc68562_device::rxb_w)); +// m_dusccterm->out_dtrb_callback().set(m_dusccterm, FUNC(duscc68562_device::dcdb_w)); +// m_dusccterm->out_rtsb_callback().set(m_dusccterm, FUNC(duscc68562_device::ctsb_w)); m_dusccterm->out_int_callback().set(FUNC(vme_hcpu30_card_device::dusirq_callback)); rs232_port_device &rs232p1(RS232_PORT(config, RS232P1_TAG, default_rs232_devices, "terminal")); @@ -397,23 +397,23 @@ WRITE_LINE_MEMBER(vme_hcpu30_card_device::fdcdrq_callback) // D69 translates to DI0-7, D67 to DL24-31 // // == f101.w == -// 0 - SYSFAIL* -// 1 - ACFAIL* -// 2 - TERMRES* -// 3 - nc -// 4 - FPSENSE* -// 5 - RST* -// 6 - IRQ30* D119 PLM output (CLRINT* and VECT20 inputs) -// 7 - SDMRQ* +// 0 - SYSFAIL* +// 1 - ACFAIL* +// 2 - TERMRES* +// 3 - nc +// 4 - FPSENSE* +// 5 - RST* +// 6 - IRQ30* D119 PLM output (CLRINT* and VECT20 inputs) +// 7 - SDMRQ* // == f100.w == -// 8 - SCSIIRQ -// 9 - CENTIRQ* -// 10 - FDCIRQ* -// 11 - ABORT* -// 12 - DUSIRQ* -// 13 - LANIRQ -// 14 - IPEND* from 030 -// 15 - LDMARQ* +// 8 - SCSIIRQ +// 9 - CENTIRQ* +// 10 - FDCIRQ* +// 11 - ABORT* +// 12 - DUSIRQ* +// 13 - LANIRQ +// 14 - IPEND* from 030 +// 15 - LDMARQ* uint32_t vme_hcpu30_card_device::irq_state_r(offs_t offset) { return m_irq_state << 16; @@ -438,21 +438,21 @@ void vme_hcpu30_card_device::update_030_irq(int irq, line_state state) // D60 translates from DI0-7 (DL24-31) // D61 translates from DL16-21 -// 0 - INTL0 -// 1 - INTL1 -// 2 - INTL2 -// 3 - VME16 -// 4 - CLRINT* D119 PLM input -// 5 - LPBK* (loopback?) -// 6-7 - nc -// 8 - SCSIRES* -// 9 - ROR -// 10 - CENTDS (strobe) -// 11 - RESET* -// 12 - HALT* -// 13 - SRLOCL* -// 14 - PWRDOWN -// 15 - INTENA* "enable input" pin of LS148 priority encoder +// 0 - INTL0 +// 1 - INTL1 +// 2 - INTL2 +// 3 - VME16 +// 4 - CLRINT* D119 PLM input +// 5 - LPBK* (loopback?) +// 6-7 - nc +// 8 - SCSIRES* +// 9 - ROR +// 10 - CENTDS (strobe) +// 11 - RESET* +// 12 - HALT* +// 13 - SRLOCL* +// 14 - PWRDOWN +// 15 - INTENA* "enable input" pin of LS148 priority encoder void vme_hcpu30_card_device::irq_mask_w(offs_t offset, uint32_t data, uint32_t mem_mask) { uint16_t diff; diff --git a/src/devices/bus/vme/vme_mvme120.cpp b/src/devices/bus/vme/vme_mvme120.cpp index 3558d6af13a..0be106f460e 100644 --- a/src/devices/bus/vme/vme_mvme120.cpp +++ b/src/devices/bus/vme/vme_mvme120.cpp @@ -1,11 +1,11 @@ // license:BSD-3-Clause // copyright-holders:Katherine Rohl /* - * Motorola MVME120 CPU board. + * Motorola MVME120 CPU board. * This is an early MVME system from 1984, using standard Motorola parts * instead of the many ASICs of later boards. * - * The following configurations were available: + * The following configurations were available: * MVME120 - 10MHz 68010, 128KB RAM, 4KB SRAM cache, 68451 MMU * MVME121 - 10MHz 68010, 512KB RAM, 4KB SRAM cache, 68451 MMU * MVME122 - 12.5MHz 68010, 128KB RAM, no cache, no MMU @@ -29,25 +29,25 @@ #endif #define LOG_PRINTF (1U << 1) -#define LOG_SETUP (1U << 2) +#define LOG_SETUP (1U << 2) #define LOG_GENERAL (1U << 3) #define VERBOSE (LOG_PRINTF | LOG_SETUP | LOG_GENERAL) - + #include "logmacro.h" -#define LOGPRINTF(...) LOGMASKED(LOG_PRINTF, __VA_ARGS__) -#define LOGSETUP(...) LOGMASKED(LOG_SETUP, __VA_ARGS__) -#define LOGGENERAL(...) LOGMASKED(LOG_GENERAL, __VA_ARGS__) +#define LOGPRINTF(...) LOGMASKED(LOG_PRINTF, __VA_ARGS__) +#define LOGSETUP(...) LOGMASKED(LOG_SETUP, __VA_ARGS__) +#define LOGGENERAL(...) LOGMASKED(LOG_GENERAL, __VA_ARGS__) // Clocks -#define MVME120_MASTER_CLOCK 20_MHz_XTAL -#define MVME120_CPU_CLOCK ( MVME120_MASTER_CLOCK / 2 ) -#define MVME120_MFP_CLOCK ( MVME120_CPU_CLOCK / 4 ) +#define MVME120_MASTER_CLOCK 20_MHz_XTAL +#define MVME120_CPU_CLOCK ( MVME120_MASTER_CLOCK / 2 ) +#define MVME120_MFP_CLOCK ( MVME120_CPU_CLOCK / 4 ) -#define MVME122_MASTER_CLOCK 25_MHz_XTAL -#define MVME122_CPU_CLOCK ( MVME122_MASTER_CLOCK / 2 ) -#define MVME122_MFP_CLOCK ( MVME122_CPU_CLOCK / 4 ) +#define MVME122_MASTER_CLOCK 25_MHz_XTAL +#define MVME122_CPU_CLOCK ( MVME122_MASTER_CLOCK / 2 ) +#define MVME122_MFP_CLOCK ( MVME122_CPU_CLOCK / 4 ) // The four MVME12x card variants. DEFINE_DEVICE_TYPE(VME_MVME120, vme_mvme120_card_device, "mvme120", "Motorola MVME-120") @@ -58,66 +58,66 @@ DEFINE_DEVICE_TYPE(VME_MVME123, vme_mvme123_card_device, "mvme123", "Motor static INPUT_PORTS_START(mvme120) PORT_START("S3") // described as "autoboot" and "cache disable" in the manual - PORT_DIPNAME(0x01, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("S3:1") PORT_CHANGED_MEMBER(DEVICE_SELF, vme_mvme120_device, s3_autoboot, 0) + PORT_DIPNAME(0x01, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("S3:1") PORT_CHANGED_MEMBER(DEVICE_SELF, vme_mvme120_device, s3_autoboot, 0) PORT_DIPSETTING( 0x01, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) - - PORT_DIPNAME(0x02, 0x00, "Baud Rate Select") PORT_DIPLOCATION("S3:2") PORT_CHANGED_MEMBER(DEVICE_SELF, vme_mvme120_device, s3_baudrate, 0) + + PORT_DIPNAME(0x02, 0x00, "Baud Rate Select") PORT_DIPLOCATION("S3:2") PORT_CHANGED_MEMBER(DEVICE_SELF, vme_mvme120_device, s3_baudrate, 0) PORT_DIPSETTING( 0x02, "10.0MHz CPU") PORT_DIPSETTING( 0x00, "12.5MHz CPU") - - PORT_DIPNAME(0x0C, 0x08, "Reset Vector Source") PORT_DIPLOCATION("S3:3,4") + + PORT_DIPNAME(0x0C, 0x08, "Reset Vector Source") PORT_DIPLOCATION("S3:3,4") PORT_DIPSETTING( 0x08, "Onboard ROM") PORT_DIPSETTING( 0x04, "VMEbus") - + // Select whether MSR bit 7 monitors ACFAIL* or SYSFAIL* on the VME bus. PORT_START("J2") PORT_DIPNAME(0x01, 0x01, "ACFAIL*/SYSFAIL* Select") PORT_DIPSETTING( 0x00, "ACFAIL*") PORT_DIPSETTING( 0x01, "SYSFAIL*") - - PORT_START("J3-J4") // Different configurations of jumpers in J3 and J4. + + PORT_START("J3-J4") // Different configurations of jumpers in J3 and J4. PORT_DIPNAME(0x03, 0x03, "VMEbus Request Level") PORT_DIPSETTING( 0x00, "Level 0") PORT_DIPSETTING( 0x01, "Level 1") PORT_DIPSETTING( 0x02, "Level 2") PORT_DIPSETTING( 0x03, "Level 3") - + PORT_START("J5") PORT_DIPNAME(0x01, 0x01, "Abort Switch Enable") PORT_DIPSETTING( 0x00, DEF_STR( Off )) PORT_DIPSETTING( 0x01, DEF_STR( On )) - + PORT_START("J6") PORT_DIPNAME(0x01, 0x01, "Reset Switch Enable") PORT_DIPSETTING( 0x00, DEF_STR( Off )) PORT_DIPSETTING( 0x01, DEF_STR( On )) - - PORT_START("J7") // Enable/disable VME IRQs reaching the MFP. - PORT_DIPNAME(0x01, 0x01, "VME IRQ1") PORT_DIPLOCATION("J7:1") + + PORT_START("J7") // Enable/disable VME IRQs reaching the MFP. + PORT_DIPNAME(0x01, 0x01, "VME IRQ1") PORT_DIPLOCATION("J7:1") PORT_DIPSETTING( 0x00, DEF_STR( Off )) PORT_DIPSETTING( 0x01, DEF_STR( On )) - PORT_DIPNAME(0x02, 0x02, "VME IRQ2") PORT_DIPLOCATION("J7:2") + PORT_DIPNAME(0x02, 0x02, "VME IRQ2") PORT_DIPLOCATION("J7:2") PORT_DIPSETTING( 0x00, DEF_STR( Off )) PORT_DIPSETTING( 0x02, DEF_STR( On )) - PORT_DIPNAME(0x04, 0x04, "VME IRQ3") PORT_DIPLOCATION("J7:3") + PORT_DIPNAME(0x04, 0x04, "VME IRQ3") PORT_DIPLOCATION("J7:3") PORT_DIPSETTING( 0x00, DEF_STR( Off )) PORT_DIPSETTING( 0x04, DEF_STR( On )) - PORT_DIPNAME(0x08, 0x08, "VME IRQ4") PORT_DIPLOCATION("J7:4") + PORT_DIPNAME(0x08, 0x08, "VME IRQ4") PORT_DIPLOCATION("J7:4") PORT_DIPSETTING( 0x00, DEF_STR( Off )) PORT_DIPSETTING( 0x08, DEF_STR( On )) - PORT_DIPNAME(0x10, 0x10, "VME IRQ5") PORT_DIPLOCATION("J7:5") + PORT_DIPNAME(0x10, 0x10, "VME IRQ5") PORT_DIPLOCATION("J7:5") PORT_DIPSETTING( 0x00, DEF_STR( Off )) PORT_DIPSETTING( 0x10, DEF_STR( On )) - PORT_DIPNAME(0x20, 0x20, "VME IRQ6") PORT_DIPLOCATION("J7:6") + PORT_DIPNAME(0x20, 0x20, "VME IRQ6") PORT_DIPLOCATION("J7:6") PORT_DIPSETTING( 0x00, DEF_STR( Off )) PORT_DIPSETTING( 0x20, DEF_STR( On )) - PORT_DIPNAME(0x40, 0x40, "VME IRQ7") PORT_DIPLOCATION("J7:7") + PORT_DIPNAME(0x40, 0x40, "VME IRQ7") PORT_DIPLOCATION("J7:7") PORT_DIPSETTING( 0x00, DEF_STR( Off )) PORT_DIPSETTING( 0x40, DEF_STR( On )) - + // EPROM configuration is J8 - // Cache configuration is J9/J17 + // Cache configuration is J9/J17 INPUT_PORTS_END ioport_constructor vme_mvme120_device::device_input_ports() const @@ -159,20 +159,20 @@ vme_mvme122_card_device::vme_mvme122_card_device(const machine_config &mconfig, vme_mvme123_card_device::vme_mvme123_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : vme_mvme123_card_device(mconfig, VME_MVME123, tag, owner, clock) { - + } void vme_mvme120_device::mvme12x_base_mem(address_map &map) { - map(0xf00000, 0xf0ffff).rom().region("maincpu", 0x00000); // ROM/EEPROM bank 1 - 120bug - map(0xf10000, 0xf1ffff).rom().region("maincpu", 0x10000); // ROM/EEPROM bank 2 - unpopulated + map(0xf00000, 0xf0ffff).rom().region("maincpu", 0x00000); // ROM/EEPROM bank 1 - 120bug + map(0xf10000, 0xf1ffff).rom().region("maincpu", 0x10000); // ROM/EEPROM bank 2 - unpopulated map(0xf20000, 0xf2003f).mirror(0x1ffc0).umask16(0x00ff).rw(m_mfp, FUNC(mc68901_device::read), FUNC(mc68901_device::write)); map(0xf40000, 0xf40000).mirror(0x1fffc).rw(FUNC(vme_mvme120_card_device::ctrlreg_r), FUNC(vme_mvme120_card_device::ctrlreg_w)); // $F60000-F6003F 68451 MMU, mirrored to $F7FFFF map(0xfa0000, 0xfeffff).rw(FUNC(vme_mvme120_card_device::vme_a24_r), FUNC(vme_mvme120_card_device::vme_a24_w)); // VMEbus 24-bit addresses map(0xff0000, 0xffffff).rw(FUNC(vme_mvme120_card_device::vme_a16_r), FUNC(vme_mvme120_card_device::vme_a16_w)); // VMEbus 16-bit addresses - - // $F80002-F80003 clear cache bank 2 + + // $F80002-F80003 clear cache bank 2 // $F80004-F80005 clear cache bank 1 // $F80006-F80007 clear cache bank 1+2 // (above mirrored to $F9FFFF) @@ -184,7 +184,7 @@ void vme_mvme120_device::mvme120_mem(address_map &map) map(0x000000, 0x01ffff).ram().share(m_localram); map(0x020000, 0xefffff).rw(FUNC(vme_mvme120_card_device::vme_a24_r), FUNC(vme_mvme120_card_device::vme_a24_w)); // VMEbus 24-bit addresses // $F60000-F6003F 68451 MMU, mirrored to $F7FFFF - // $F80002-F80003 clear cache bank 2 + // $F80002-F80003 clear cache bank 2 // $F80004-F80005 clear cache bank 1 // $F80006-F80007 clear cache bank 1+2 // (above mirrored to $F9FFFF) @@ -196,7 +196,7 @@ void vme_mvme120_device::mvme121_mem(address_map &map) map(0x000000, 0x07ffff).ram().share(m_localram); map(0x080000, 0xefffff).rw(FUNC(vme_mvme120_card_device::vme_a24_r), FUNC(vme_mvme120_card_device::vme_a24_w)); // VMEbus 24-bit addresses // $F60000-F6003F 68451 MMU, mirrored to $F7FFFF - // $F80002-F80003 clear cache bank 2 + // $F80002-F80003 clear cache bank 2 // $F80004-F80005 clear cache bank 1 // $F80006-F80007 clear cache bank 1+2 // (above mirrored to $F9FFFF) @@ -215,7 +215,7 @@ void vme_mvme120_device::mvme123_mem(address_map &map) mvme12x_base_mem(map); map(0x000000, 0x07ffff).ram().share(m_localram); map(0x020000, 0xefffff).rw(FUNC(vme_mvme120_card_device::vme_a24_r), FUNC(vme_mvme120_card_device::vme_a24_w)); // VMEbus 24-bit addresses - // $F80002-F80003 clear cache bank 2 + // $F80002-F80003 clear cache bank 2 // $F80004-F80005 clear cache bank 1 // $F80006-F80007 clear cache bank 1+2 // (above mirrored to $F9FFFF) @@ -229,7 +229,7 @@ void vme_mvme120_device::device_start() void vme_mvme120_device::device_reset() { LOG("%s\n", FUNCNAME); - + // First 4 machine cycles, ROM is mapped to the reset vector. address_space &program = m_maincpu->space(AS_PROGRAM); program.install_rom(0x000000, 0x000007, m_sysrom); @@ -240,7 +240,7 @@ void vme_mvme120_device::device_reset() rom_shadow_tap(offset, data, mem_mask); }); - ctrlreg_w(0, 0xFF); // /RESET flips the latch bits to $FF + ctrlreg_w(0, 0xFF); // /RESET flips the latch bits to $FF } uint16_t vme_mvme120_device::rom_shadow_tap(offs_t address, u16 data, u16 mem_mask) @@ -256,7 +256,7 @@ uint16_t vme_mvme120_device::rom_shadow_tap(offs_t address, u16 data, u16 mem_ma m_maincpu->space(AS_PROGRAM).install_ram(0x000000, 0x000007, m_localram); } m_memory_read_count++; - } + } return data; } @@ -273,7 +273,7 @@ WRITE_LINE_MEMBER(vme_mvme120_device::watchdog_reset) WRITE_LINE_MEMBER(vme_mvme120_device::mfp_interrupt) { LOG("%s: MFP asserting interrupt\n", FUNCNAME); - + // MFP interrupts are gated by bit 2 of the control register. if(state && !BIT(m_ctrlreg, 2)) { @@ -290,7 +290,7 @@ void vme_mvme120_device::vme_bus_timeout() { m_mfp->i2_w(ASSERT_LINE); m_mfp->i2_w(CLEAR_LINE); - + m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE); m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE); } @@ -306,7 +306,7 @@ uint16_t vme_mvme120_device::vme_a24_r() } void vme_mvme120_device::vme_a24_w(uint16_t data) -{ +{ vme_bus_timeout(); } @@ -327,15 +327,15 @@ void vme_mvme120_device::vme_a16_w(uint16_t data) uint8_t vme_mvme120_device::ctrlreg_r(offs_t offset) { // Control Register - // b0 - BRDFAIL - Controls FAIL LED - // b1 - /CTS - Asserts RTS on serial port 1 - // b2 - /IE - When asserted, MFP interrupts reach the CPU - // b3 - /PAREN - When asserted, parity errors do not cause /BERR. - // b4 - CACHEN - Enable SRAM cache - // b5 - FREEZE - Cache cannot be updated (but can be invalidated) - // b6 - /ALTCLR - "Allows bus error to start alternate interrupt mode" (?) - // b7 - /WWP - When asserted, bad parity is written to RAM. - + // b0 - BRDFAIL - Controls FAIL LED + // b1 - /CTS - Asserts RTS on serial port 1 + // b2 - /IE - When asserted, MFP interrupts reach the CPU + // b3 - /PAREN - When asserted, parity errors do not cause /BERR. + // b4 - CACHEN - Enable SRAM cache + // b5 - FREEZE - Cache cannot be updated (but can be invalidated) + // b6 - /ALTCLR - "Allows bus error to start alternate interrupt mode" (?) + // b7 - /WWP - When asserted, bad parity is written to RAM. + return m_ctrlreg; } @@ -343,7 +343,7 @@ void vme_mvme120_device::ctrlreg_w(offs_t offset, uint8_t data) { LOG("%s: vme120 control register set to $%02X\n", FUNCNAME, data); m_ctrlreg = data; - + // Set lines according to the new ctrlreg status. m_rs232->write_rts(!BIT(m_ctrlreg, 1)); } @@ -367,7 +367,7 @@ void vme_mvme120_device::device_add_mconfig(machine_config &config) M68010(config, m_maincpu, MVME120_CPU_CLOCK); m_maincpu->set_addrmap(AS_PROGRAM, &vme_mvme120_card_device::mvme120_mem); m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &vme_mvme120_card_device::mvme120_mem); - + MC68901(config, m_mfp, MVME120_MFP_CLOCK); m_mfp->set_timer_clock(MVME120_MFP_CLOCK); m_mfp->out_so_cb().set("rs232", FUNC(rs232_port_device::write_txd)); @@ -382,15 +382,15 @@ void vme_mvme120_device::device_add_mconfig(machine_config &config) m_rs232->set_option_device_input_defaults("terminal", terminal_defaults); // Missing: MMU, VMEbus - + VME(config, "vme", 0); /* // Onboard RAM is always visible to VMEbus. (Decoding controlled by U28.) m_vme->install_device(vme_device::A24_SC, 0, 0x1FFFF, - read16_delegate(*this, FUNC(vme_mvme120_device::vme_to_ram_r)), - write16_delegate(*this, FUNC(vme_mvme120_device::vme_to_ram_w)), - 0xFFFF); + read16_delegate(*this, FUNC(vme_mvme120_device::vme_to_ram_r)), + write16_delegate(*this, FUNC(vme_mvme120_device::vme_to_ram_w)), + 0xFFFF); */ } @@ -403,7 +403,7 @@ void vme_mvme120_device::vme_to_ram_w(address_space &space, offs_t address, uint { m_localram[address] = data; } - + void vme_mvme120_card_device::device_add_mconfig(machine_config &config) { vme_mvme120_device::device_add_mconfig(config); @@ -421,11 +421,11 @@ void vme_mvme121_card_device::device_add_mconfig(machine_config &config) void vme_mvme122_card_device::device_add_mconfig(machine_config &config) { vme_mvme120_device::device_add_mconfig(config); - + m_maincpu->set_addrmap(AS_PROGRAM, &vme_mvme122_card_device::mvme122_mem); m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &vme_mvme122_card_device::mvme122_mem); m_maincpu->set_clock(MVME122_CPU_CLOCK); - + m_mfp->set_clock(MVME122_MFP_CLOCK); m_mfp->set_timer_clock(MVME122_MFP_CLOCK); } @@ -435,9 +435,9 @@ void vme_mvme123_card_device::device_add_mconfig(machine_config &config) vme_mvme120_device::device_add_mconfig(config); m_maincpu->set_addrmap(AS_PROGRAM, &vme_mvme123_card_device::mvme123_mem); m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &vme_mvme123_card_device::mvme123_mem); - + m_maincpu->set_clock(MVME122_CPU_CLOCK); - + m_mfp->set_clock(MVME122_MFP_CLOCK); m_mfp->set_timer_clock(MVME122_MFP_CLOCK); } @@ -463,7 +463,7 @@ ROM_START(mvme120) ROM_SYSTEM_BIOS(0, "12xbug-v2.0", "MVME120 12xbug v2.0") ROMX_LOAD("12xbug-2.0-u44.bin", 0x0000, 0x4000, CRC(87d62dac) SHA1(c57eb9f8aefe29794b8fc5f0afbaff9b59d38c73), ROM_SKIP(1) | ROM_BIOS(0)) ROMX_LOAD("12xbug-2.0-u52.bin", 0x0001, 0x4000, CRC(5651b61d) SHA1(0d0004dff3c88b2f0b18951b4f2acd7f65f701b1), ROM_SKIP(1) | ROM_BIOS(0)) - + ROM_SYSTEM_BIOS(1, "12xbug-v1.1", "MVME120 12xbug v1.1") ROMX_LOAD("12xbug-1.1-u44.bin", 0x0000, 0x4000, CRC(bf4d6cf1) SHA1(371bb55611eddeb6231a92af7c1e34d4ec0321b5), ROM_SKIP(1) | ROM_BIOS(1)) ROMX_LOAD("12xbug-1.1-u52.bin", 0x0001, 0x4000, CRC(76fabe32) SHA1(2f933d0eb46d00db0051ce23c3e53ccef75a2c69), ROM_SKIP(1) | ROM_BIOS(1)) diff --git a/src/devices/bus/vme/vme_mvme120.h b/src/devices/bus/vme/vme_mvme120.h index c19eb2313f4..1f39456370b 100644 --- a/src/devices/bus/vme/vme_mvme120.h +++ b/src/devices/bus/vme/vme_mvme120.h @@ -23,56 +23,56 @@ class vme_mvme120_device : public device_t, public device_vme_card_interface { public: /* Board types */ - enum mvme12x_variant + enum mvme12x_variant { mvme120_board, mvme121_board, mvme122_board, mvme123_board }; - + vme_mvme120_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, mvme12x_variant board_id); // Switch and jumper handlers DECLARE_INPUT_CHANGED_MEMBER(s3_autoboot); DECLARE_INPUT_CHANGED_MEMBER(s3_baudrate); - + uint16_t vme_to_ram_r(address_space &space, offs_t offset, uint16_t mem_mask); void vme_to_ram_w(address_space &space, offs_t address, uint16_t data, uint16_t mem_mask); - + protected: void device_add_mconfig(machine_config &config) override; virtual const tiny_rom_entry *device_rom_region() const override; virtual ioport_constructor device_input_ports() const override; - + virtual void device_start() override; virtual void device_reset() override; - + void mvme12x_base_mem(address_map &map); void mvme120_mem(address_map &map); void mvme121_mem(address_map &map); void mvme122_mem(address_map &map); void mvme123_mem(address_map &map); - + required_device<cpu_device> m_maincpu; - + required_device<mc68901_device> m_mfp; required_device<rs232_port_device> m_rs232; - + required_ioport m_input_s3; - + memory_passthrough_handler *m_rom_shadow_tap; memory_passthrough_handler *m_ram_wwp_tap; required_region_ptr<uint16_t> m_sysrom; required_shared_ptr<uint16_t> m_localram; - uint8_t m_ctrlreg; // "VME120 Control Register" - uint8_t m_memory_read_count; // For boot ROM shadowing $000000 + uint8_t m_ctrlreg; // "VME120 Control Register" + uint8_t m_memory_read_count; // For boot ROM shadowing $000000 + + uint8_t ctrlreg_r(offs_t offset); + void ctrlreg_w(offs_t offset, uint8_t data); - uint8_t ctrlreg_r(offs_t offset); - void ctrlreg_w(offs_t offset, uint8_t data); - // VMEbus dummy lines void vme_bus_timeout(); uint16_t vme_a24_r(); @@ -81,8 +81,8 @@ protected: void vme_a16_w(uint16_t data); uint16_t rom_shadow_tap(offs_t address, u16 data, u16 mem_mask); - - DECLARE_WRITE_LINE_MEMBER(watchdog_reset); + + DECLARE_WRITE_LINE_MEMBER(watchdog_reset); DECLARE_WRITE_LINE_MEMBER(mfp_interrupt); const mvme12x_variant m_board_id; diff --git a/src/devices/cpu/arm7/upd800468.cpp b/src/devices/cpu/arm7/upd800468.cpp index 471e16098f4..6a3869c4bd3 100644 --- a/src/devices/cpu/arm7/upd800468.cpp +++ b/src/devices/cpu/arm7/upd800468.cpp @@ -212,7 +212,7 @@ u8 upd800468_device::port_ddr_r(offs_t num) void upd800468_device::port_ddr_w(offs_t num, u8 data) { m_port_ddr[num] = data; -// logerror("port %u ddr_w: %02x\n", num, data); +// logerror("port %u ddr_w: %02x\n", num, data); port_update(num); } @@ -232,7 +232,7 @@ void upd800468_device::port_w(offs_t num, u8 data) void upd800468_device::port_update(offs_t num) { -// logerror("port %u out: %02x\n", num, m_port_data[num] & m_port_ddr[num]); +// logerror("port %u out: %02x\n", num, m_port_data[num] & m_port_ddr[num]); m_out_cb[num](m_port_data[num] & m_port_ddr[num]); } diff --git a/src/devices/cpu/arm7/upd800468.h b/src/devices/cpu/arm7/upd800468.h index afd47d9bab9..3d78560ab9b 100644 --- a/src/devices/cpu/arm7/upd800468.h +++ b/src/devices/cpu/arm7/upd800468.h @@ -12,7 +12,7 @@ #include "machine/vic_pl192.h" /*************************************************************************** - TYPE DEFINITIONS + TYPE DEFINITIONS ***************************************************************************/ class upd800468_timer_device : public device_t @@ -46,7 +46,7 @@ class upd800468_device : public arm7_cpu_device { public: upd800468_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t); - + void upd800468_map(address_map &map); template<offs_t i> auto adc_cb() { return m_adc_cb[i].bind(); } @@ -96,7 +96,7 @@ private: u32 m_ram_enable; }; -// device type +// device type DECLARE_DEVICE_TYPE(UPD800468_TIMER, upd800468_timer_device) DECLARE_DEVICE_TYPE(UPD800468, upd800468_device) diff --git a/src/devices/machine/mc68328.cpp b/src/devices/machine/mc68328.cpp index 9ecce201f66..4699054dae9 100644 --- a/src/devices/machine/mc68328.cpp +++ b/src/devices/machine/mc68328.cpp @@ -11,34 +11,34 @@ #include "emu.h" #include "machine/mc68328.h" -#define LOG_SCR (1U << 1) -#define LOG_CS_GRP (1U << 2) -#define LOG_CS_SEL (1U << 3) -#define LOG_PLL (1U << 4) -#define LOG_INTS (1U << 5) -#define LOG_GPIO_A (1U << 6) -#define LOG_GPIO_B (1U << 7) -#define LOG_GPIO_C (1U << 8) -#define LOG_GPIO_D (1U << 9) -#define LOG_GPIO_E (1U << 10) -#define LOG_GPIO_F (1U << 11) -#define LOG_GPIO_G (1U << 12) -#define LOG_GPIO_J (1U << 13) -#define LOG_GPIO_K (1U << 14) -#define LOG_GPIO_M (1U << 15) -#define LOG_PWM (1U << 16) -#define LOG_TIMERS (1U << 17) -#define LOG_TSTAT (1U << 18) -#define LOG_WATCHDOG (1U << 19) -#define LOG_SPIS (1U << 20) -#define LOG_SPIM (1U << 21) -#define LOG_UART (1U << 22) -#define LOG_LCD (1U << 23) -#define LOG_RTC (1U << 24) -#define LOG_ALL (LOG_SCR | LOG_CS_GRP | LOG_CS_SEL | LOG_PLL | LOG_INTS | LOG_GPIO_A | LOG_GPIO_B | LOG_GPIO_C | LOG_GPIO_D | LOG_GPIO_E \ +#define LOG_SCR (1U << 1) +#define LOG_CS_GRP (1U << 2) +#define LOG_CS_SEL (1U << 3) +#define LOG_PLL (1U << 4) +#define LOG_INTS (1U << 5) +#define LOG_GPIO_A (1U << 6) +#define LOG_GPIO_B (1U << 7) +#define LOG_GPIO_C (1U << 8) +#define LOG_GPIO_D (1U << 9) +#define LOG_GPIO_E (1U << 10) +#define LOG_GPIO_F (1U << 11) +#define LOG_GPIO_G (1U << 12) +#define LOG_GPIO_J (1U << 13) +#define LOG_GPIO_K (1U << 14) +#define LOG_GPIO_M (1U << 15) +#define LOG_PWM (1U << 16) +#define LOG_TIMERS (1U << 17) +#define LOG_TSTAT (1U << 18) +#define LOG_WATCHDOG (1U << 19) +#define LOG_SPIS (1U << 20) +#define LOG_SPIM (1U << 21) +#define LOG_UART (1U << 22) +#define LOG_LCD (1U << 23) +#define LOG_RTC (1U << 24) +#define LOG_ALL (LOG_SCR | LOG_CS_GRP | LOG_CS_SEL | LOG_PLL | LOG_INTS | LOG_GPIO_A | LOG_GPIO_B | LOG_GPIO_C | LOG_GPIO_D | LOG_GPIO_E \ | LOG_GPIO_F | LOG_GPIO_G | LOG_GPIO_J | LOG_GPIO_K | LOG_GPIO_M | LOG_PWM | LOG_TIMERS | LOG_TSTAT | LOG_WATCHDOG | LOG_SPIS \ | LOG_SPIM | LOG_UART | LOG_LCD | LOG_RTC) -#define VERBOSE (0) +#define VERBOSE (0) #include "logmacro.h" diff --git a/src/devices/machine/wd_fdc.cpp b/src/devices/machine/wd_fdc.cpp index aa478bdbf21..082a706bad3 100644 --- a/src/devices/machine/wd_fdc.cpp +++ b/src/devices/machine/wd_fdc.cpp @@ -22,7 +22,7 @@ #define LOG_STATE (1U << 12) // Show state machine #define LOG_LIVE (1U << 13) // Live states #define LOG_FUNC (1U << 14) // Function calls -#define LOG_CRC (1U << 15) // CRC errors +#define LOG_CRC (1U << 15) // CRC errors #define VERBOSE (LOG_DESC) //#define VERBOSE (LOG_DESC | LOG_COMMAND | LOG_MATCH | LOG_WRITE | LOG_STATE | LOG_LINES | LOG_COMP | LOG_CRC ) @@ -82,11 +82,11 @@ DEFINE_DEVICE_TYPE(WD1770, wd1770_device, "wd1770", "Western Digital DEFINE_DEVICE_TYPE(WD1772, wd1772_device, "wd1772", "Western Digital WD1772 FDC") DEFINE_DEVICE_TYPE(WD1773, wd1773_device, "wd1773", "Western Digital WD1773 FDC") -static const char *const states[] = +static const char *const states[] = { - "IDLE", - "RESTORE", - "SEEK", + "IDLE", + "RESTORE", + "SEEK", "STEP", "READ_SECTOR", "READ_TRACK", @@ -186,7 +186,7 @@ void wd_fdc_device_base::device_start() data = 0x00; track = 0x00; mr = true; - + delay_int = false; save_item(NAME(status)); @@ -1022,14 +1022,14 @@ void wd_fdc_device_base::interrupt_start() // If writing a byte to a sector, then wait until it's written before terminating // This behavior is required by the RM nimbus driver, otherwise the forced interrupt - // at the end of a multiple sector write occasionally prevents the CRC byte being + // at the end of a multiple sector write occasionally prevents the CRC byte being // written, causing the disk to be corrupted. if (/*((main_state == READ_SECTOR) && (cur_live.state == READ_SECTOR_DATA)) ||*/ - ((main_state == WRITE_SECTOR) && (cur_live.state == WRITE_BYTE))) + ((main_state == WRITE_SECTOR) && (cur_live.state == WRITE_BYTE))) { delay_int = true; return; - } + } else { delay_int = false; @@ -1984,15 +1984,15 @@ void wd_fdc_device_base::live_run(attotime limit) } else if(slot < sector_size+2) { // CRC - if(slot == sector_size+1) + if(slot == sector_size+1) { // act on delayed interrupt if active -/* if (delay_int) - { - interrupt_start(); - return; - } -*/ live_delay(IDLE); +/* if (delay_int) + { + interrupt_start(); + return; + } +*/ live_delay(IDLE); return; } } @@ -2243,11 +2243,11 @@ void wd_fdc_device_base::live_run(attotime limit) live_write_mfm(cur_live.crc >> 8); else if(cur_live.byte_counter < sector_size + 16+3) live_write_mfm(0xff); -// live_write_mfm(0x4e); +// live_write_mfm(0x4e); else { pll_stop_writing(floppy, cur_live.tm); cur_live.state = IDLE; - + // Act on delayed interrupt if set. if (delay_int) { diff --git a/src/devices/machine/wd_fdc.h b/src/devices/machine/wd_fdc.h index 7f7f28ddee1..6d9ee3a8d55 100644 --- a/src/devices/machine/wd_fdc.h +++ b/src/devices/machine/wd_fdc.h @@ -91,7 +91,7 @@ public: DECLARE_WRITE_LINE_MEMBER(mr_w); - void index_callback(floppy_image_device *floppy, int state); + void index_callback(floppy_image_device *floppy, int state); protected: wd_fdc_device_base(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); @@ -176,11 +176,11 @@ private: enum { // General "doing nothing" state - IDLE, + IDLE, // Main states - the commands - RESTORE, - SEEK, + RESTORE, + SEEK, STEP, READ_SECTOR, READ_TRACK, @@ -241,7 +241,7 @@ private: WRITE_SECTOR_PRE_BYTE }; - + struct live_info { enum { PT_NONE, PT_CRC_1, PT_CRC_2 }; diff --git a/src/lib/formats/acorn_dsk.cpp b/src/lib/formats/acorn_dsk.cpp index 8c7d094799c..e33f95a53f3 100644 --- a/src/lib/formats/acorn_dsk.cpp +++ b/src/lib/formats/acorn_dsk.cpp @@ -99,7 +99,7 @@ int acorn_ssd_format::find_size(util::random_read &io, uint32_t form_factor, con { sectors2 = sectors0; } - + if (sectors0 > 0 && sectors0 % 10 == 0 && sectors2 > 0 && sectors2 % 10 == 0 && size <= (sectors0 + sectors2) * 256) return i; } diff --git a/src/mame/drivers/aa310.cpp b/src/mame/drivers/aa310.cpp index 25114684952..93079648c96 100644 --- a/src/mame/drivers/aa310.cpp +++ b/src/mame/drivers/aa310.cpp @@ -693,9 +693,9 @@ u8 aa4000_state::ioeb_r(offs_t offset) case 0x70: // MID register (monitor) //if (BIT(m_ioeb_control, 2)) - // hs = !vidc_get_hs(); + // hs = !vidc_get_hs(); //else - // hs = vidc_get_hs(); + // hs = vidc_get_hs(); if (hs) data = 0xf0 | mid[1].id | mid[1].hs; @@ -964,12 +964,12 @@ void aa4_state::memc_map(address_map &map) //static INPUT_PORTS_START( aa4 ) -// PORT_START("MONITOR") -// PORT_CONFNAME( 0x07, 0x07, "Monitor Type" ) -// PORT_CONFSETTING( 0x02, "Colour SVGA" ) -// PORT_CONFSETTING( 0x05, "Mono VGA" ) -// PORT_CONFSETTING( 0x06, "Colour VGA" ) -// PORT_CONFSETTING( 0x07, "LCD" ) +// PORT_START("MONITOR") +// PORT_CONFNAME( 0x07, 0x07, "Monitor Type" ) +// PORT_CONFSETTING( 0x02, "Colour SVGA" ) +// PORT_CONFSETTING( 0x05, "Mono VGA" ) +// PORT_CONFSETTING( 0x06, "Colour VGA" ) +// PORT_CONFSETTING( 0x07, "LCD" ) //INPUT_PORTS_END diff --git a/src/mame/drivers/ctk2000.cpp b/src/mame/drivers/ctk2000.cpp index 64aba38114c..d92908a9637 100644 --- a/src/mame/drivers/ctk2000.cpp +++ b/src/mame/drivers/ctk2000.cpp @@ -1,29 +1,29 @@ // license:BSD-3-Clause // copyright-holders:Devin Acker /* - Casio CTK-2000 keyboard (and related models) + Casio CTK-2000 keyboard (and related models) - - CTK-2000 (2008) - Basic 61-key model - - CTK-3000 - Adds velocity-sensitive keys and pitch wheel - - CTK-2100 (2009) - More flexible sampling feature, lesson buttons double as voice/drum pads - (based on CTK-2000, not 3000) + - CTK-2000 (2008) + Basic 61-key model + - CTK-3000 + Adds velocity-sensitive keys and pitch wheel + - CTK-2100 (2009) + More flexible sampling feature, lesson buttons double as voice/drum pads + (based on CTK-2000, not 3000) - Main board (M800-MDA1): + Main board (M800-MDA1): - IC1: CPU (NEC uPD800468) - Custom chip (ARM-based), built in peripheral controllers & sound generator + IC1: CPU (NEC uPD800468) + Custom chip (ARM-based), built in peripheral controllers & sound generator - LSI2: 16Mbit ROM (OKI MR27T1602L) + LSI2: 16Mbit ROM (OKI MR27T1602L) - Console PCB (M800-CNA): + Console PCB (M800-CNA): - IC401: LCD controller (Sitronix ST7066U-0A, HD44780 compatible) + IC401: LCD controller (Sitronix ST7066U-0A, HD44780 compatible) - CTK-2000 service manual with schematics, pinouts, etc.: - https://www.manualslib.com/manual/933451/Casio-Ctk-2000.html + CTK-2000 service manual with schematics, pinouts, etc.: + https://www.manualslib.com/manual/933451/Casio-Ctk-2000.html */ @@ -211,7 +211,7 @@ INPUT_PORTS_START(ctk2100) PORT_START("maincpu:kbd:FI8") PORT_BIT( 0xff, IP_ACTIVE_HIGH, IPT_UNUSED ) - + PORT_START("maincpu:kbd:FI9") PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYPAD ) PORT_NAME("Keypad 0") PORT_CODE(KEYCODE_0_PAD) PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYPAD ) PORT_NAME("Keypad 1") PORT_CODE(KEYCODE_1_PAD) diff --git a/src/mame/drivers/g627.cpp b/src/mame/drivers/g627.cpp index 3a2a2e9a841..c18e82ffb5f 100644 --- a/src/mame/drivers/g627.cpp +++ b/src/mame/drivers/g627.cpp @@ -126,7 +126,7 @@ static INPUT_PORTS_START( g627 ) PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_F) PORT_NAME("3/11 Target") PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_G) PORT_NAME("1/9 Target") PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_0) PORT_NAME("North Slam") - PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_7) PORT_NAME("North Test") + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_7) PORT_NAME("North Test") PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_COIN1) PORT_NAME("North Coin") PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_9) PORT_NAME("North Tilt") PORT_START("SWITCH.3") diff --git a/src/mame/drivers/imolagp.cpp b/src/mame/drivers/imolagp.cpp index 3cda22030ab..d1be2a24cc1 100644 --- a/src/mame/drivers/imolagp.cpp +++ b/src/mame/drivers/imolagp.cpp @@ -95,7 +95,7 @@ p2-1.bin [4/4] 07.bin IDENTICAL p2-2.bin [4/4] 05.bin IDENTICAL p1-1.bin [4/4] 02.bin IDENTICAL -The only xtal on this PCB is 16.00000 MHz. +The only xtal on this PCB is 16.00000 MHz. This "Ferrari 1" was legally registered by Videotronic on Spain on 1985. The PCB is silkscreened by Falgas and the cab contains Falgas logos with a small note that reads "Manufactured by Videotronic for Falgas" (in Spanish). diff --git a/src/mame/drivers/macp.cpp b/src/mame/drivers/macp.cpp index 17c35b56454..bd3bb908d3d 100644 --- a/src/mame/drivers/macp.cpp +++ b/src/mame/drivers/macp.cpp @@ -354,7 +354,7 @@ void macp_state::mac16k(machine_config &config) kbdc.out_sl_callback().set(FUNC(macp_state::scanlines_w)); // scan SL lines kbdc.out_disp_callback().set(FUNC(macp_state::digit_w)); // display A&B kbdc.in_rl_callback().set(FUNC(macp_state::kbd_r)); // kbd RL lines - kbdc.out_irq_callback().set(FUNC(macp_state::irq_w)); + kbdc.out_irq_callback().set(FUNC(macp_state::irq_w)); /* sound hardware */ genpin_audio(config); diff --git a/src/mame/drivers/positron.cpp b/src/mame/drivers/positron.cpp index c6f281a0a45..78535d35fab 100644 --- a/src/mame/drivers/positron.cpp +++ b/src/mame/drivers/positron.cpp @@ -46,6 +46,8 @@ #include "logmacro.h" +namespace { + class positron_state : public driver_device { public: @@ -408,63 +410,63 @@ static INPUT_PORTS_START(positron) PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_UNUSED) PORT_START("COL2") - PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("0 #") PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR('#') - PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("1 !") PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!') - PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("2 \"") PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('\"') - PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("3 £") PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR(0xA3) - PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("4 $") PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$') - PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("5 %") PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%') - PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("6 &") PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&') - PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("7 '") PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'') + PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR('#') + PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!') + PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('\"') + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR(0xA3) + PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$') + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%') + PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&') + PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'') PORT_START("COL3") - PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("8 (") PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(') - PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("9 )") PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')') - PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME(": *") PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(':') PORT_CHAR('*') - PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("; +") PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR('+') - PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME(", <") PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<') - PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("= -") PORT_CODE(KEYCODE_MINUS) PORT_CHAR('=') PORT_CHAR('-') - PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME(". >") PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>') - PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("/ ?") PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?') + PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(') + PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')') + PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(':') PORT_CHAR('*') + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR('+') + PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<') + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('=') PORT_CHAR('-') + PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>') + PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?') PORT_START("COL4") - PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("@ _") PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('@') PORT_CHAR('_') - PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("A") PORT_CODE(KEYCODE_A) PORT_CHAR('A') - PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("B") PORT_CODE(KEYCODE_B) PORT_CHAR('B') - PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("C") PORT_CODE(KEYCODE_C) PORT_CHAR('C') - PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("D") PORT_CODE(KEYCODE_D) PORT_CHAR('D') - PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("E") PORT_CODE(KEYCODE_E) PORT_CHAR('E') - PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("F") PORT_CODE(KEYCODE_F) PORT_CHAR('F') - PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("G") PORT_CODE(KEYCODE_G) PORT_CHAR('G') + PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('@') PORT_CHAR('_') + PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_A) PORT_CHAR('A') + PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_B) PORT_CHAR('B') + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_C) PORT_CHAR('C') + PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_D) PORT_CHAR('D') + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_E) PORT_CHAR('E') + PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_F) PORT_CHAR('F') + PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_G) PORT_CHAR('G') PORT_START("COL5") - PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("H") PORT_CODE(KEYCODE_H) PORT_CHAR('H') - PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("I") PORT_CODE(KEYCODE_I) PORT_CHAR('I') - PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("J") PORT_CODE(KEYCODE_J) PORT_CHAR('J') - PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("K") PORT_CODE(KEYCODE_K) PORT_CHAR('K') - PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("L") PORT_CODE(KEYCODE_L) PORT_CHAR('L') - PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("M") PORT_CODE(KEYCODE_M) PORT_CHAR('M') - PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("N") PORT_CODE(KEYCODE_N) PORT_CHAR('N') - PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("O") PORT_CODE(KEYCODE_O) PORT_CHAR('O') + PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_H) PORT_CHAR('H') + PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_I) PORT_CHAR('I') + PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_J) PORT_CHAR('J') + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_K) PORT_CHAR('K') + PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_L) PORT_CHAR('L') + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_M) PORT_CHAR('M') + PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_N) PORT_CHAR('N') + PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_O) PORT_CHAR('O') PORT_START("COL6") - PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("P") PORT_CODE(KEYCODE_P) PORT_CHAR('P') - PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Q") PORT_CODE(KEYCODE_Q) PORT_CHAR('Q') - PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("R") PORT_CODE(KEYCODE_R) PORT_CHAR('R') - PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("S") PORT_CODE(KEYCODE_S) PORT_CHAR('S') - PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("T") PORT_CODE(KEYCODE_T) PORT_CHAR('T') - PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("U") PORT_CODE(KEYCODE_U) PORT_CHAR('U') - PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("V") PORT_CODE(KEYCODE_V) PORT_CHAR('V') - PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("W") PORT_CODE(KEYCODE_W) PORT_CHAR('W') + PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_P) PORT_CHAR('P') + PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Q) PORT_CHAR('Q') + PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_R) PORT_CHAR('R') + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_S) PORT_CHAR('S') + PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_T) PORT_CHAR('T') + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_U) PORT_CHAR('U') + PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_V) PORT_CHAR('V') + PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_W) PORT_CHAR('W') PORT_START("COL7") - PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("X") PORT_CODE(KEYCODE_X) PORT_CHAR('X') - PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Y") PORT_CODE(KEYCODE_Y) PORT_CHAR('Y') - PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Z") PORT_CODE(KEYCODE_Z) PORT_CHAR('Z') - PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME(u8"← ¼") PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR('{') - PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME(u8"½ ‖") PORT_CODE(KEYCODE_BACKSLASH2) PORT_CHAR('\\') PORT_CHAR('|') - PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME(u8"→ ¾") PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR(']') PORT_CHAR('}') - PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME(u8"^ ÷") PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('^') PORT_CHAR('~') + PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_X) PORT_CHAR('X') + PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Y) PORT_CHAR('Y') + PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Z) PORT_CHAR('Z') + PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR(0x2190) PORT_CHAR(0xbc) // ← ¼ + PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH2) PORT_CHAR(0xbd) PORT_CHAR(0x2016) // ½ ‖ + PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR(0x2192) PORT_CHAR(0xbe) // → ¾ + PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('^') PORT_CHAR(0xf7) // ÷ PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("SPACE") PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ') PORT_START("COL8") // Video Attributes @@ -967,7 +969,8 @@ ROM_START(positron) ROM_LOAD("os9_1_0007.bin", 0x1e000, 0x2000, CRC(63f0fb57) SHA1(7c50c0cbc7c0dbaf8da186ccb474d263f71416ea)) ROM_END +} // anonymous namespace + // YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS COMP( 1982, positron, 0, 0, positron, positron, positron_state, empty_init, "Positron Computers Ltd", "Positron 9000", MACHINE_NOT_WORKING ) - diff --git a/src/mame/drivers/rawthrillspc.cpp b/src/mame/drivers/rawthrillspc.cpp index e5003b89241..fcac5099cee 100644 --- a/src/mame/drivers/rawthrillspc.cpp +++ b/src/mame/drivers/rawthrillspc.cpp @@ -112,7 +112,7 @@ ROM_END /* Two I/O boards on "The Fast and The Furious": - 1. With Xilinx XC95144XL (labeled "FAST & FURIOUS U4 REV 1.0 (c)2004 RightHand Tech, Inc"), + 1. With Xilinx XC95144XL (labeled "FAST & FURIOUS U4 REV 1.0 (c)2004 RightHand Tech, Inc"), ST72F63BK4M1 (labeled "U6 FAST&FURIOUS Release 3 3311h (c)2004 RightHand Tech, Inc") and a bank of 8 dipswitches. 2- With Xilinx XC9536XL (labeled "r1.0 (c)2004 RightHand Tech, Inc") Parallel port HASP4 1.5 dongle (MCU Marvin2) diff --git a/src/mame/drivers/rmnimbus.cpp b/src/mame/drivers/rmnimbus.cpp index aefa1add81b..dfd855bdf31 100644 --- a/src/mame/drivers/rmnimbus.cpp +++ b/src/mame/drivers/rmnimbus.cpp @@ -211,7 +211,7 @@ void rmnimbus_state::nimbus(machine_config &config) msm5205.add_route(ALL_OUTPUTS, MONO_TAG, 0.75); SOFTWARE_LIST(config, "disk_list").set_original("nimbus"); - + m_maincpu->set_dasm_override(FUNC(rmnimbus_state::dasm_override)); } diff --git a/src/mame/drivers/sys1121.cpp b/src/mame/drivers/sys1121.cpp index 122a0ab65c0..e43dcb8374e 100644 --- a/src/mame/drivers/sys1121.cpp +++ b/src/mame/drivers/sys1121.cpp @@ -1,18 +1,18 @@ // license:BSD-3-Clause // copyright-holders:Katherine Rohl /* - * Motorola SYS1121 VME chassis. + * Motorola SYS1121 VME chassis. * * The basic configuration was an MVME12x MPU, * an MVME050 system controller, and an MVME320 disk * controller. */ - + #include "emu.h" #include "bus/vme/vme_mvme120.h" #include "logmacro.h" -namespace +namespace { class sys1121_state : public driver_device { @@ -51,7 +51,7 @@ namespace } // This is a VME chassis so any ROMs are contained in the cards. - ROM_START(sys1121) + ROM_START(sys1121) ROM_END } diff --git a/src/mame/includes/rmnimbus.h b/src/mame/includes/rmnimbus.h index 7f2090fbbcf..10eb6441659 100644 --- a/src/mame/includes/rmnimbus.h +++ b/src/mame/includes/rmnimbus.h @@ -93,7 +93,7 @@ public: void decode_subbios(device_t *device, offs_t pc); void decode_subbios_return(device_t *device, offs_t pc); void decode_dos21(device_t *device, offs_t pc); - + private: required_device<i80186_cpu_device> m_maincpu; required_device<i8031_device> m_iocpu; @@ -148,7 +148,7 @@ private: void nimbus_pc8031_port3_w(uint8_t data); uint8_t nimbus_iou_r(offs_t offset); void nimbus_iou_w(offs_t offset, uint8_t data); - + uint8_t nimbus_rompack_r(offs_t offset); void nimbus_rompack_w(offs_t offset, uint8_t data); void nimbus_sound_ay8910_porta_w(uint8_t data); @@ -166,7 +166,7 @@ private: DECLARE_WRITE_LINE_MEMBER(nimbus_fdc_intrq_w); DECLARE_WRITE_LINE_MEMBER(nimbus_fdc_drq_w); DECLARE_READ_LINE_MEMBER(nimbus_fdc_enmf_r); - + void nimbus_via_write_portb(uint8_t data); DECLARE_WRITE_LINE_MEMBER(write_scsi_bsy); DECLARE_WRITE_LINE_MEMBER(write_scsi_cd); @@ -200,8 +200,8 @@ private: void rmni_sound_reset(); void mouse_js_reset(); void check_scsi_irq(); - void set_scsi_drqlat(bool clock, bool clear); - + void set_scsi_drqlat(bool clock, bool clear); + int m_scsi_iena; int m_scsi_msg; int m_scsi_bsy; @@ -235,20 +235,20 @@ private: /* Mouse/Joystick */ struct { - int8_t m_mouse_x; - int8_t m_mouse_y; + int8_t m_mouse_x; + int8_t m_mouse_y; - uint8_t m_mouse_pcx; - uint8_t m_mouse_pcy; + uint8_t m_mouse_pcx; + uint8_t m_mouse_pcy; - uint8_t m_intstate_x; - uint8_t m_intstate_y; + uint8_t m_intstate_x; + uint8_t m_intstate_y; - uint8_t m_reg0a4; + uint8_t m_reg0a4; emu_timer *m_mouse_timer; } m_nimbus_mouse; - + bool m_voice_enabled; void nimbus_io(address_map &map); @@ -263,7 +263,7 @@ private: void decode_dssi_f_set_new_clt(uint16_t ds, uint16_t si); void decode_dssi_f_plonk_char(uint16_t ds, uint16_t si); void decode_dssi_f_rw_sectors(uint16_t ds, uint16_t si); - + void debug_command(const std::vector<std::string> ¶ms); void video_debug(const std::vector<std::string> ¶ms); offs_t dasm_override(std::ostream &stream, offs_t pc, const util::disasm_interface::data_buffer &opcodes, const util::disasm_interface::data_buffer ¶ms); diff --git a/src/mame/machine/macadb.cpp b/src/mame/machine/macadb.cpp index 16fed4443e3..28debf54c4b 100644 --- a/src/mame/machine/macadb.cpp +++ b/src/mame/machine/macadb.cpp @@ -396,10 +396,10 @@ int macadb_device::adb_pollkbd(int update) } } -// if ((codes[0] != 0xff) || (codes[1] != 0xff)) -// { -// printf("ADB keyboard: update %d keys %02x %02x\n", update, codes[0], codes[1]); -// } +// if ((codes[0] != 0xff) || (codes[1] != 0xff)) +// { +// printf("ADB keyboard: update %d keys %02x %02x\n", update, codes[0], codes[1]); +// } // figure out if there was a change if ((m_adb_currentkeys[0] != codes[0]) || (m_adb_currentkeys[1] != codes[1])) @@ -454,7 +454,7 @@ void macadb_device::adb_accummouse( uint8_t *MouseX, uint8_t *MouseY ) NewX = m_mouse2->read(); NewY = m_mouse1->read(); -// printf("pollmouse: X %d Y %d\n", NewX, NewY); +// printf("pollmouse: X %d Y %d\n", NewX, NewY); /* see if it moved in the x coord */ if (NewX != m_adb_lastmousex) @@ -499,7 +499,7 @@ void macadb_device::adb_talk() addr = (m_adb_command>>4); reg = (m_adb_command & 3); -// printf("Mac sent %x (cmd %d addr %d reg %d mr %d kr %d)\n", m_adb_command, (m_adb_command>>2)&3, addr, reg, m_adb_mouseaddr, m_adb_keybaddr); +// printf("Mac sent %x (cmd %d addr %d reg %d mr %d kr %d)\n", m_adb_command, (m_adb_command>>2)&3, addr, reg, m_adb_mouseaddr, m_adb_keybaddr); if (m_adb_waiting_cmd) { diff --git a/src/mame/machine/rmnimbus.cpp b/src/mame/machine/rmnimbus.cpp index f6f12e59fc5..7d7c62da454 100644 --- a/src/mame/machine/rmnimbus.cpp +++ b/src/mame/machine/rmnimbus.cpp @@ -109,16 +109,16 @@ chdman createhd -o ST125N.chd -chs 41921,1,1 -ss 512 #define MOUSE_INT_ENABLE 0x08 #define PC8031_INT_ENABLE 0x10 -#define MOUSE_NONE 0x00 -#define MOUSE_LEFT 0x01 -#define MOUSE_RIGHT 0x02 -#define MOUSE_DOWN 0x04 -#define MOUSE_UP 0x08 -#define MOUSE_LBUTTON 0x10 -#define MOUSE_RBUTTON 0x20 +#define MOUSE_NONE 0x00 +#define MOUSE_LEFT 0x01 +#define MOUSE_RIGHT 0x02 +#define MOUSE_DOWN 0x04 +#define MOUSE_UP 0x08 +#define MOUSE_LBUTTON 0x10 +#define MOUSE_RBUTTON 0x20 // Frequency in Hz to poll for mouse movement. -#define MOUSE_POLL_FREQUENCY 500 +#define MOUSE_POLL_FREQUENCY 500 #define MOUSE_INT_ENABLED(state) (((state)->m_iou_reg092 & MOUSE_INT_ENABLE) ? 1 : 0) @@ -137,7 +137,7 @@ chdman createhd -o ST125N.chd -chs 41921,1,1 -ss 512 /* Debugging */ -#define DEBUG_SET(flags) ((m_debug_machine & (flags))==(flags)) +#define DEBUG_SET(flags) ((m_debug_machine & (flags))==(flags)) #define DEBUG_SET_STATE(flags) ((state->m_debug_machine & (flags))==(flags)) #define DEBUG_NONE 0x0000000 @@ -216,7 +216,7 @@ void rmnimbus_state::machine_reset() void rmnimbus_state::machine_start() { m_nimbus_mouse.m_mouse_timer=timer_alloc(TIMER_MOUSE); - + /* setup debug commands */ if (machine().debug_flags & DEBUG_FLAG_ENABLED) { @@ -231,7 +231,7 @@ void rmnimbus_state::machine_start() m_debug_trap=0; m_voice_enabled=false; m_fdc->dden_w(0); - //m_fdc->overide_delays(64,m_fdc->get_cmd_delay()); + //m_fdc->overide_delays(64,m_fdc->get_cmd_delay()); } void rmnimbus_state::debug_command(const std::vector<std::string> ¶ms) @@ -258,8 +258,8 @@ static int instruction_hook(device_t &device, offs_t curpc) rmnimbus_state *state = device.machine().driver_data<rmnimbus_state>(); address_space &space = device.memory().space(AS_PROGRAM); uint8_t *addr_ptr; - uint8_t first; - + uint8_t first; + addr_ptr = (uint8_t*)space.get_read_ptr(curpc); first = (curpc & 0x01) ? 1 : 0; @@ -273,7 +273,7 @@ static int instruction_hook(device_t &device, offs_t curpc) { if(DEBUG_SET_STATE(DECODE_BIOS) && (addr_ptr[first+1]==0xF0)) state->decode_subbios(&device,curpc); - + if(DEBUG_SET_STATE(DECODE_DOS21) && (addr_ptr[first+1]==0x21)) state->decode_dos21(&device,curpc); } @@ -799,13 +799,13 @@ void rmnimbus_state::decode_dssi_f_rw_sectors(uint16_t ds, uint16_t si) params=(uint16_t *)get_regpair_ptr(space,ds,si); logerror("unitno=%04X, count=%02X, first_sector=%08X buffer=%04X:%04X (%05X)\n", - params[0], + params[0], params[1], ((params[3] * 65536)+params[2]), params[5],params[4], ((params[5]*16)+params[4]) ); - + for(param_no=0;param_no<16;param_no++) logerror("%04X ",params[param_no]); @@ -816,8 +816,8 @@ void rmnimbus_state::decode_dos21(device_t *device,offs_t pc) { address_space &space = m_maincpu->space(AS_PROGRAM); //uint16_t *params; - char *path; - + char *path; + uint16_t ax = m_maincpu->state_int(I8086_AX); uint16_t bx = m_maincpu->state_int(I8086_BX); uint16_t cx = m_maincpu->state_int(I8086_CX); @@ -830,8 +830,8 @@ void rmnimbus_state::decode_dos21(device_t *device,offs_t pc) uint16_t si = m_maincpu->state_int(I8086_SI); uint16_t di = m_maincpu->state_int(I8086_DI); uint16_t bp = m_maincpu->state_int(I8086_BP); - - uint8_t dosfn = ax >> 8; // Dos function is AH, upper half of AX. + + uint8_t dosfn = ax >> 8; // Dos function is AH, upper half of AX. logerror("=======================================================================\n"); logerror("DOS Int 0x21 call at %05X\n",pc); @@ -839,16 +839,16 @@ void rmnimbus_state::decode_dos21(device_t *device,offs_t pc) logerror("CS=%04X, DS=%04X, ES=%04X, SS=%04X\n",cs,ds,es,ss); logerror("SI=%04X, DI=%04X, BP=%04X\n",si,di,bp); logerror("=======================================================================\n"); - - if (((dosfn >= 0x39) && (dosfn <= 0x3d)) - || (0x43 == dosfn) - || (0x4e == dosfn) + + if (((dosfn >= 0x39) && (dosfn <= 0x3d)) + || (0x43 == dosfn) + || (0x4e == dosfn) || (0x56 == dosfn) - || ((dosfn >= 0x5a) && (dosfn <= 0x5b)) ) + || ((dosfn >= 0x5a) && (dosfn <= 0x5b)) ) { path=(char *)get_regpair_ptr(space,ds,dx); logerror("Path at DS:DX=%s\n",path); - + if (0x56 == dosfn) { path=(char *)get_regpair_ptr(space,es,di); @@ -858,44 +858,44 @@ void rmnimbus_state::decode_dos21(device_t *device,offs_t pc) } } -#define CBUFLEN 32 +#define CBUFLEN 32 offs_t rmnimbus_state::dasm_override(std::ostream &stream, offs_t pc, const util::disasm_interface::data_buffer &opcodes, const util::disasm_interface::data_buffer ¶ms) { unsigned call; - char callname[CBUFLEN]; + char callname[CBUFLEN]; offs_t result = 0; // decode and document (some) INT XX calls if (opcodes.r8(pc) == 0xCD) { call = opcodes.r8(pc+1); - switch (call) + switch (call) { case 0x20 : - strcpy(callname, "(dos terminate)"); + strcpy(callname, "(dos terminate)"); break; - + case 0x21 : - strcpy(callname, "(dos function)"); + strcpy(callname, "(dos function)"); break; - + case 0xf0 : - strcpy(callname, "(sub_bios)"); + strcpy(callname, "(sub_bios)"); break; - + case 0xf3 : - strcpy(callname, "(dispatch handler)"); + strcpy(callname, "(dispatch handler)"); break; - + case 0xf5 : - strcpy(callname, "(event handler)"); + strcpy(callname, "(event handler)"); break; case 0xf6 : - strcpy(callname, "(resource message)"); + strcpy(callname, "(resource message)"); break; - + default : strcpy(callname, ""); } @@ -1216,7 +1216,7 @@ void rmnimbus_state::fdc_ctl_w(uint8_t data) uint8_t old_drq = m_nimbus_drives.reg400 & HDC_DRQ_MASK; char drive[5]; floppy_image_device *floppy; - + m_nimbus_drives.reg400 = data; sprintf(drive, "%d", FDC_DRIVE()); @@ -1272,14 +1272,14 @@ void rmnimbus_state::hdc_reset() m_scsi_req = 0; // Latched req, IC11b - m_scsi_reqlat = 0; + m_scsi_reqlat = 0; } -/* - The SCSI code outputs a 1 to indicate an active line, even though it is active low - The inputs on the RM schematic are fed through inverters, but because of the above - we don't need to invert them, unless the schematic uses the signal directly - For consistency we will invert msg before latching. +/* + The SCSI code outputs a 1 to indicate an active line, even though it is active low + The inputs on the RM schematic are fed through inverters, but because of the above + we don't need to invert them, unless the schematic uses the signal directly + For consistency we will invert msg before latching. */ void rmnimbus_state::check_scsi_irq() @@ -1294,13 +1294,13 @@ WRITE_LINE_MEMBER(rmnimbus_state::write_scsi_iena) } // This emulates the 74LS74 latched version of req -void rmnimbus_state::set_scsi_drqlat(bool clock, bool clear) -{ +void rmnimbus_state::set_scsi_drqlat(bool clock, bool clear) +{ if (clear) m_scsi_reqlat = 0; else if (clock) m_scsi_reqlat = 1; - + if(m_scsi_reqlat) hdc_drq(true); else @@ -1311,9 +1311,9 @@ void rmnimbus_state::hdc_post_rw() { if(m_scsi_req) m_scsibus->write_ack(1); - + // IC17A, IC17B, latched req cleared by SCSI data read or write, or C/D= command - set_scsi_drqlat(false, true); + set_scsi_drqlat(false, true); } void rmnimbus_state::hdc_drq(bool state) @@ -1329,10 +1329,10 @@ WRITE_LINE_MEMBER( rmnimbus_state::write_scsi_bsy ) WRITE_LINE_MEMBER( rmnimbus_state::write_scsi_cd ) { m_scsi_cd = state; - + // IC17A, IC17B, latched req cleared by SCSI data read or write, or C/D= command set_scsi_drqlat(false, !m_scsi_cd); - + check_scsi_irq(); } @@ -1356,22 +1356,22 @@ WRITE_LINE_MEMBER( rmnimbus_state::write_scsi_req ) { // Detect rising edge on req, IC11b, clock int rising = ((m_scsi_req == 0) && (state == 1)); - + // This is the state of the actual line from the SCSI m_scsi_req = state; - + // Latched req, is forced low by C/D being set to command set_scsi_drqlat(rising, m_scsi_cd); - + if (!m_scsi_reqlat) m_scsibus->write_ack(0); - + check_scsi_irq(); } void rmnimbus_state::nimbus_voice_w(offs_t offset, uint8_t data) { - if (offset == 0xB0) + if (offset == 0xB0) m_voice_enabled = true; else if (offset == 0xB2) m_voice_enabled = false; @@ -1607,7 +1607,7 @@ void rmnimbus_state::iou_reset() uint8_t rmnimbus_state::nimbus_rompack_r(offs_t offset) { logerror("Rompack read offset %02X, rompack address=%04X\n",offset,(m_ay8910_b*256)+m_ay8910_a); - + return 0; } @@ -1658,7 +1658,7 @@ void rmnimbus_state::nimbus_sound_ay8910_portb_w(uint8_t data) m_last_playmode = (data & 0x07); m_msm->playmode_w(m_last_playmode); } - + // ROMpack upper address lines m_ay8910_b=data; } @@ -1673,7 +1673,7 @@ void rmnimbus_state::device_timer(emu_timer &timer, device_timer_id id, int para { switch(id) { - case TIMER_MOUSE : do_mouse(); break; + case TIMER_MOUSE : do_mouse(); break; } } @@ -1682,41 +1682,41 @@ static const int MOUSE_XYB[4] = { 0, 1, 1, 0 }; void rmnimbus_state::do_mouse() { - int mouse_x = 0; // Current mouse X and Y - int mouse_y = 0; - int xdiff = 0; // Difference from previous X and Y - int ydiff = 0; - - uint8_t intstate_x; // Used to calculate if we should trigger interrupt - uint8_t intstate_y; - int xint; // X and Y interrupts to trigger + int mouse_x = 0; // Current mouse X and Y + int mouse_y = 0; + int xdiff = 0; // Difference from previous X and Y + int ydiff = 0; + + uint8_t intstate_x; // Used to calculate if we should trigger interrupt + uint8_t intstate_y; + int xint; // X and Y interrupts to trigger int yint; - uint8_t mxa; // Values of quadrature encoders for X and Y + uint8_t mxa; // Values of quadrature encoders for X and Y uint8_t mxb; uint8_t mya; uint8_t myb; // Read mouse buttons m_nimbus_mouse.m_reg0a4 = m_io_mouse_button->read(); - + // Read mose positions and calculate difference from previous value mouse_x = m_io_mousex->read(); mouse_y = m_io_mousey->read(); xdiff = m_nimbus_mouse.m_mouse_x - mouse_x; ydiff = m_nimbus_mouse.m_mouse_y - mouse_y; - + // check and compensate for wrap..... - if (xdiff > 0x80) + if (xdiff > 0x80) xdiff -= 0x100; else if (xdiff < -0x80) xdiff += 0x100; - if (ydiff > 0x80) + if (ydiff > 0x80) ydiff -= 0x100; else if (ydiff < -0x80) - ydiff += 0x100; + ydiff += 0x100; // convert movement into emulated movement of quadrature encoder in mouse. if (xdiff < 0) @@ -1728,7 +1728,7 @@ void rmnimbus_state::do_mouse() m_nimbus_mouse.m_mouse_pcy++; else if (ydiff > 0) m_nimbus_mouse.m_mouse_pcy--; - + // Compensate for quadrature wrap. m_nimbus_mouse.m_mouse_pcx &= 0x03; m_nimbus_mouse.m_mouse_pcy &= 0x03; diff --git a/src/mame/video/rmnimbus.cpp b/src/mame/video/rmnimbus.cpp index b9e7e8ded69..244a2e2c4a0 100644 --- a/src/mame/video/rmnimbus.cpp +++ b/src/mame/video/rmnimbus.cpp @@ -22,10 +22,10 @@ operation by disassembling the Nimbus bios and by writing experemental code on the real machine. - 2021-09-29, P.Harvey-Smith. - - I now have access to the service manual for the Nimbus, this documents to facilities provided - by the video chip, which will hopefully allow a much more accurate implementation. + 2021-09-29, P.Harvey-Smith. + + I now have access to the service manual for the Nimbus, this documents to facilities provided + by the video chip, which will hopefully allow a much more accurate implementation. */ #include "emu.h" @@ -36,92 +36,92 @@ #include <functional> -/* - Acording to the service manual the Nimbus should be capable of the following modes : - - 320 x 200 4bpp - 640 x 200 2bpp - 400 x 200 4bpp - 800 x 200 2bpp - 320 x 250 4bpp - 640 x 250 2bpp - 400 x 250 4bpp - 800 x 250 2bpp -*/ - -/* - From the service manual the registers are defined as follows : - +/* + Acording to the service manual the Nimbus should be capable of the following modes : + + 320 x 200 4bpp + 640 x 200 2bpp + 400 x 200 4bpp + 800 x 200 2bpp + 320 x 250 4bpp + 640 x 250 2bpp + 400 x 250 4bpp + 800 x 250 2bpp +*/ + +/* + From the service manual the registers are defined as follows : + Ports 0x00-0x1E are the registers used to update the display RAM thus : -Addr m_x m_y Update memory on write? -0x00 nop nop no -0x02 load nop no -0x04 nop inc no -0x06 load inc no -0x08 nop nop no -0x0A inc nop no -0x0C nop load no -0x0E inc load no -0x10 nop nop yes -0x12 load nop yes -0x14 nop inc yes -0x16 load inc yes -0x18 nop nop yes -0x1A inc nop yes -0x1C nop load yes -0x1E inc load yes - -0x20 scroll port, contains 8 bit scroll address - -0x22 Update mode control port (up_mode), controls how data is written to display ram. - see UPMODE_ constants below - -0x24h Intensity port, provides current logical intensities for update operations - bits 0..3 Foreground - bits 4..7 Background - -0x26 Display mode (m_mode) current display mode and border colour. - see MODE_ constants below +Addr m_x m_y Update memory on write? +0x00 nop nop no +0x02 load nop no +0x04 nop inc no +0x06 load inc no +0x08 nop nop no +0x0A inc nop no +0x0C nop load no +0x0E inc load no +0x10 nop nop yes +0x12 load nop yes +0x14 nop inc yes +0x16 load inc yes +0x18 nop nop yes +0x1A inc nop yes +0x1C nop load yes +0x1E inc load yes + +0x20 scroll port, contains 8 bit scroll address + +0x22 Update mode control port (up_mode), controls how data is written to display ram. + see UPMODE_ constants below + +0x24h Intensity port, provides current logical intensities for update operations + bits 0..3 Foreground + bits 4..7 Background + +0x26 Display mode (m_mode) current display mode and border colour. + see MODE_ constants below For READ. Ports 0x28, 0x2A, 0x2C and 0x2E have different read and write functions : -0x28 Timing / status, all bits active high - bit 0 line blank - bit 1 line display - bit 2 frame blank - bit 3 frame display - -0x2A X address status, returns current value of X counter (m_x) +0x28 Timing / status, all bits active high + bit 0 line blank + bit 1 line display + bit 2 frame blank + bit 3 frame display -0x2C Y address status, returns current value of Y counter (m_y) +0x2A X address status, returns current value of X counter (m_x) + +0x2C Y address status, returns current value of Y counter (m_y) For Write 0x28, 0x2A, 0x2C, 0x2E Colour look up table : - Logic colour -Port Bits Low res High Res -0x28 0..3 0 0 -0x28 4..7 1 0 -0x28 8..11 2 0 -0x28 12..15 3 0 + Logic colour +Port Bits Low res High Res +0x28 0..3 0 0 +0x28 4..7 1 0 +0x28 8..11 2 0 +0x28 12..15 3 0 -0x2A 0..3 3 1 -0x2A 4..7 5 1 -0x2A 8..11 6 1 -0x2A 12..15 7 1 +0x2A 0..3 3 1 +0x2A 4..7 5 1 +0x2A 8..11 6 1 +0x2A 12..15 7 1 -0x2C 0..3 8 2 -0x2C 4..7 9 2 -0x2C 8..11 10 2 -0x2C 12..15 11 2 +0x2C 0..3 8 2 +0x2C 4..7 9 2 +0x2C 8..11 10 2 +0x2C 12..15 11 2 -0x2E 0..3 12 3 -0x2E 4..7 13 3 -0x2E 8..11 14 3 -0x2E 12..15 15 3 +0x2E 0..3 12 3 +0x2E 4..7 13 3 +0x2E 8..11 14 3 +0x2E 12..15 15 3 */ @@ -129,47 +129,47 @@ Port Bits Low res High Res // In following definitions ports are the WORD offset, the RM manual // lists them by the byte offset so they are 2* the value -#define P_SCROLL 0x10 -#define P_UPDATE_MODE 0x11 -#define P_INTENSITY 0x12 -#define P_MODE 0x13 -#define P_STATUS 0x14 -#define P_X_COUNT 0x15 -#define P_Y_COUNT 0x16 +#define P_SCROLL 0x10 +#define P_UPDATE_MODE 0x11 +#define P_INTENSITY 0x12 +#define P_MODE 0x13 +#define P_STATUS 0x14 +#define P_X_COUNT 0x15 +#define P_Y_COUNT 0x16 -#define P_COLOUR03 0x14 -#define P_COLOUR47 0x15 -#define P_COLOUR8B 0x16 -#define P_COLOURCF 0x17 +#define P_COLOUR03 0x14 +#define P_COLOUR47 0x15 +#define P_COLOUR8B 0x16 +#define P_COLOURCF 0x17 // From the service manual, Reg022 update mode constants : // The first 8 are NON XOR writes -#define UPMODE_40_TEXT 0x00 // 40 character text -#define UPMODE_80_TEXT 0x01 // 80 character text -#define UPMODE_LO_PIXEL 0x02 // Low res pixel -#define UPMODE_HI_PIXEL 0x03 // Hi res pixel -#define UPMODE_ANIMATION 0x04 // Animation (mask + data) -#define UPMODE_SCROLL 0x05 // Scroll mode -#define UPMODE_DIRECT 0x06 // Direct write to video ram -#define UPMODE_ILLEGAL7 0x07 +#define UPMODE_40_TEXT 0x00 // 40 character text +#define UPMODE_80_TEXT 0x01 // 80 character text +#define UPMODE_LO_PIXEL 0x02 // Low res pixel +#define UPMODE_HI_PIXEL 0x03 // Hi res pixel +#define UPMODE_ANIMATION 0x04 // Animation (mask + data) +#define UPMODE_SCROLL 0x05 // Scroll mode +#define UPMODE_DIRECT 0x06 // Direct write to video ram +#define UPMODE_ILLEGAL7 0x07 // The second 8 are XOR writes -#define UPMODE_40_TEXT_X 0x08 -#define UPMODE_80_TEXT_X 0x09 -#define UPMODE_LO_PIXEL_X 0x0A -#define UPMODE_HI_PIXEL_X 0x0B -#define UPMODE_ANIMATION_X 0x0C -#define UPMODE_SCROLL_X 0x0D -#define UPMODE_DIRECT_X 0x0E -#define UPMODE_ILLEGALF 0x0F +#define UPMODE_40_TEXT_X 0x08 +#define UPMODE_80_TEXT_X 0x09 +#define UPMODE_LO_PIXEL_X 0x0A +#define UPMODE_HI_PIXEL_X 0x0B +#define UPMODE_ANIMATION_X 0x0C +#define UPMODE_SCROLL_X 0x0D +#define UPMODE_DIRECT_X 0x0E +#define UPMODE_ILLEGALF 0x0F -#define UP_XOR_MASK 0x08 +#define UP_XOR_MASK 0x08 // port 026, display mode (m_mode) -#define MODE_BORDER 0x0F // bits 0..3, Border colour number -#define MODE_RESOLUTION 0x10 // bit 4, 0=low res (40 col), high = high res (80 col) -#define MODE_WIDTH 0x20 // bit 5, 0=narrow, 1=wide -#define MODE_HEIGHT 0x40 // bit 6, 0=625 lines, 1=562 +#define MODE_BORDER 0x0F // bits 0..3, Border colour number +#define MODE_RESOLUTION 0x10 // bit 4, 0=low res (40 col), high = high res (80 col) +#define MODE_WIDTH 0x20 // bit 5, 0=narrow, 1=wide +#define MODE_HEIGHT 0x40 // bit 6, 0=625 lines, 1=562 #define WIDTH_MASK 0x07 @@ -427,7 +427,7 @@ void rmnimbus_state::nimbus_video_io_w(offs_t offset, uint16_t data, uint16_t me // This register doesn't appear to be documented, but is written regually in setpc ibm mode case 0x18 : break; - + default: logerror("nimbus: unknown video reg write %02x %04x\n", offset, data); return; @@ -608,7 +608,7 @@ void rmnimbus_state::write_pixel_data(uint16_t x, uint16_t y, uint16_t data) // Colours are encoded as follows : // Each nibble contains a colour encoded as igrb // so we shift through the specified colours and extract the bits, to set the palette. -// +// void rmnimbus_state::change_palette(uint8_t bank, uint16_t colours) { // loop over changing colours |
