diff options
author | 2016-06-22 20:25:23 +0200 | |
---|---|---|
committer | 2016-06-22 20:25:23 +0200 | |
commit | 48e5f590bff8fb6cd491aebe66b9679284d02cd1 (patch) | |
tree | a5dccf06f1b21d3f27002629e992486e4b398e75 /src | |
parent | 23c5c02d5abcdfff6034d2104247406f61973abf (diff) | |
parent | 32a75e7ae44c148a08b464f327b3549c95e388d0 (diff) |
Merge remote-tracking branch 'origin/master' into netlist_dev
Diffstat (limited to 'src')
49 files changed, 673 insertions, 335 deletions
diff --git a/src/devices/cpu/sparc/mb86901.cpp b/src/devices/cpu/sparc/mb86901.cpp index 04e41e94e60..f2e737b7265 100644 --- a/src/devices/cpu/sparc/mb86901.cpp +++ b/src/devices/cpu/sparc/mb86901.cpp @@ -24,8 +24,6 @@ #define SPARCV8 (0) -CPU_DISASSEMBLE( sparc ); - const device_type MB86901 = &device_creator<mb86901_device>; const int mb86901_device::WINDOW_COUNT = 7; @@ -552,7 +550,7 @@ bool mb86901_device::execute_group2(UINT32 op) { UINT32 result = arg1 - arg2; TEST_ICC_NZ(result); - if ((arg1 & 0x80000000) == (arg2 & 0x80000000) && (arg2 & 0x80000000) != (result & 0x80000000)) + if ((arg1 & 0x80000000) != (arg2 & 0x80000000) && (arg2 & 0x80000000) != (result & 0x80000000)) SET_ICC_V_FLAG; if (result > arg1) SET_ICC_C_FLAG; @@ -614,10 +612,10 @@ bool mb86901_device::execute_group2(UINT32 op) case 28: // subxcc { UINT32 c = (ICC_C_SET ? 1 : 0); - UINT32 argt = arg2 - c; + UINT32 argt = arg2 + c; UINT32 result = arg1 - argt; TEST_ICC_NZ(result); - if (((arg1 & 0x80000000) == (argt & 0x80000000) && (arg1 & 0x80000000) != (result & 0x80000000)) || (c != 0 && arg2 == 0x80000000)) + if (((arg1 & 0x80000000) != (argt & 0x80000000) && (arg1 & 0x80000000) != (result & 0x80000000)) || (c != 0 && arg2 == 0x80000000)) SET_ICC_V_FLAG; if (result > arg1 || (result == arg1 && arg2 != 0)) SET_ICC_C_FLAG; @@ -1113,7 +1111,7 @@ void mb86901_device::execute_group3(UINT32 op) write_word(m_data_asi, ADDRESS, RDREG); if (MAE || HOLD_BUS) break; - write_word(m_data_asi, ADDRESS, REG(RD+1)); + write_word(m_data_asi, ADDRESS+4, REG(RD+1)); break; case 9: // ldsb { diff --git a/src/devices/cpu/sparc/sparc.h b/src/devices/cpu/sparc/sparc.h index a646a80040c..a5e31751ed2 100644 --- a/src/devices/cpu/sparc/sparc.h +++ b/src/devices/cpu/sparc/sparc.h @@ -40,6 +40,10 @@ #define SPARC_INT15 31 #define SPARC_TRAP_INSTRUCTION 128 +// TODO: when there are more SPARC CPUs, move setter to a base class +#define MCFG_SPARC_ADD_ASI_DESC(desc) \ + mb86901_device::add_asi_desc(*device, desc); + class mb86901_device : public cpu_device { public: @@ -76,7 +80,11 @@ public: void hold_bus() { m_hold_bus = true; } void release_bus() { m_hold_bus = false; } + template<typename T> static void add_asi_desc(device_t &device, const T &desc) { return downcast<mb86901_device &>(device).add_asi_desc(desc); } + protected: + template<typename T> void add_asi_desc(const T &desc) { m_dasm.add_asi_desc(desc); } + bool invoke_queued_traps(); bool check_main_traps(UINT32 op, bool privileged, UINT32 alignment, UINT8 registeralign, bool noimmediate); diff --git a/src/devices/cpu/sparc/sparcdasm.cpp b/src/devices/cpu/sparc/sparcdasm.cpp index 357e391702d..6422c0a567f 100644 --- a/src/devices/cpu/sparc/sparcdasm.cpp +++ b/src/devices/cpu/sparc/sparcdasm.cpp @@ -8,12 +8,14 @@ #include "sparcdasm.h" #include "sparcdefs.h" +#include <algorithm> #include <cstdio> + namespace { - const sparc_disassembler DASM_V7(7); - const sparc_disassembler DASM_V8(8); - const sparc_disassembler DASM_V9(9); + INT32 get_disp16(UINT32 op) { return DISP19; } + INT32 get_disp19(UINT32 op) { return DISP19; } + INT32 get_disp22(UINT32 op) { return DISP19; } } const char * const sparc_disassembler::REG_NAMES[32] = { @@ -33,7 +35,7 @@ const sparc_disassembler::branch_desc sparc_disassembler::EMPTY_BRANCH_DESC = { }; const sparc_disassembler::branch_desc sparc_disassembler::BPCC_DESC = { - [](UINT32 op) { return DISP19; }, 6, true, true, + &get_disp19, 6, true, true, { "%icc", nullptr, "%xcc", nullptr }, { "bn", "be", "ble", "bl", "bleu", "bcs", "bneg", "bvs", @@ -42,7 +44,7 @@ const sparc_disassembler::branch_desc sparc_disassembler::BPCC_DESC = { }; const sparc_disassembler::branch_desc sparc_disassembler::BICC_DESC = { - [](UINT32 op) { return DISP22; }, 6, false, false, + &get_disp22, 6, false, false, { nullptr, nullptr, nullptr, nullptr }, { "bn", "be", "ble", "bl", "bleu", "bcs", "bneg", "bvs", @@ -51,7 +53,7 @@ const sparc_disassembler::branch_desc sparc_disassembler::BICC_DESC = { }; const sparc_disassembler::branch_desc sparc_disassembler::BPR_DESC = { - [](UINT32 op) { return DISP16; }, 5, true, false, + &get_disp16, 5, true, false, { nullptr, nullptr, nullptr, nullptr }, { nullptr, "brz", "brlez", "brlz", nullptr, "brnz", "brgz", "brgez", @@ -60,7 +62,7 @@ const sparc_disassembler::branch_desc sparc_disassembler::BPR_DESC = { }; const sparc_disassembler::branch_desc sparc_disassembler::FBPFCC_DESC = { - [](UINT32 op) { return DISP19; }, 6, true, true, + &get_disp19, 6, true, true, { "%fcc0", "%fcc1", "%fcc2", "%fcc3" }, { "fbn", "fbne", "fblg", "fbul", "fbl", "fbug", "fbg", "fbu", @@ -69,7 +71,7 @@ const sparc_disassembler::branch_desc sparc_disassembler::FBPFCC_DESC = { }; const sparc_disassembler::branch_desc sparc_disassembler::FBFCC_DESC = { - [](UINT32 op) { return DISP22; }, 6, false, false, + &get_disp22, 6, false, false, { nullptr, nullptr, nullptr, nullptr }, { "fbn", "fbne", "fblg", "fbul", "fbl", "fbug", "fbg", "fbu", @@ -78,7 +80,7 @@ const sparc_disassembler::branch_desc sparc_disassembler::FBFCC_DESC = { }; const sparc_disassembler::branch_desc sparc_disassembler::CBCCC_DESC = { - [](UINT32 op) { return DISP22; }, 6, false, false, + &get_disp22, 6, false, false, { nullptr, nullptr, nullptr, nullptr }, { "cbn", "cb123", "cb12", "cb13", "cb1", "cb23", "cb2", "cb3", @@ -86,54 +88,49 @@ const sparc_disassembler::branch_desc sparc_disassembler::CBCCC_DESC = { } }; -const sparc_disassembler::int_op_desc_map::value_type sparc_disassembler::SIMPLE_INT_OP_DESC[] = { - { 0x00, { 7, false, "add" } }, - { 0x01, { 7, true, "and" } }, - { 0x02, { 7, true, "or" } }, - { 0x03, { 7, true, "xor" } }, - { 0x04, { 7, false, "sub" } }, - { 0x05, { 7, true, "andn" } }, - { 0x06, { 7, true, "orn" } }, - { 0x07, { 7, true, "xnor" } }, - { 0x08, { 7, false, "addx" } }, - { 0x09, { 9, false, "mulx" } }, - { 0x0a, { 8, false, "umul" } }, - { 0x0b, { 8, false, "smul" } }, - { 0x0c, { 7, false, "subx" } }, - { 0x0d, { 9, false, "udivx" } }, - { 0x0e, { 8, false, "udiv" } }, - { 0x0f, { 8, false, "sdiv" } }, - { 0x10, { 8, false, "addcc" } }, - { 0x11, { 8, true, "andcc" } }, - { 0x12, { 7, true, "orcc" } }, - { 0x13, { 7, true, "xorcc" } }, - { 0x14, { 7, false, "subcc" } }, - { 0x15, { 7, true, "andncc" } }, - { 0x16, { 7, true, "orncc" } }, - { 0x17, { 7, true, "xnorcc" } }, - { 0x18, { 7, false, "addxcc" } }, - { 0x1a, { 8, false, "umulcc" } }, - { 0x1b, { 8, false, "smulcc" } }, - { 0x1c, { 7, false, "subxcc" } }, - { 0x1e, { 8, false, "udivcc" } }, - { 0x1f, { 8, false, "sdivcc" } }, - { 0x20, { 7, false, "taddcc" } }, - { 0x21, { 7, false, "tsubcc" } }, - { 0x22, { 7, false, "taddcctv" } }, - { 0x23, { 7, false, "tsubcctv" } }, - { 0x24, { 7, false, "mulscc" } }, - { 0x2d, { 9, false, "sdivx" } }, - { 0x3c, { 7, false, "save" } }, - { 0x3d, { 7, false, "restore" } } +const sparc_disassembler::int_op_desc_map::value_type sparc_disassembler::V7_INT_OP_DESC[] = { + { 0x00, { false, "add" } }, { 0x10, { false, "addcc" } }, + { 0x01, { true, "and" } }, { 0x11, { true, "andcc" } }, + { 0x02, { true, "or" } }, { 0x12, { true, "orcc" } }, + { 0x03, { true, "xor" } }, { 0x13, { true, "xorcc" } }, + { 0x04, { false, "sub" } }, { 0x14, { false, "subcc" } }, + { 0x05, { true, "andn" } }, { 0x15, { true, "andncc" } }, + { 0x06, { true, "orn" } }, { 0x16, { true, "orncc" } }, + { 0x07, { true, "xnor" } }, { 0x17, { true, "xnorcc" } }, + { 0x08, { false, "addx" } }, { 0x18, { false, "addxcc" } }, + { 0x0c, { false, "subx" } }, { 0x1c, { false, "subxcc" } }, + + { 0x20, { false, "taddcc" } }, + { 0x21, { false, "tsubcc" } }, + { 0x22, { false, "taddcctv" } }, + { 0x23, { false, "tsubcctv" } }, + { 0x24, { false, "mulscc" } }, + + { 0x3c, { false, "save" } }, + { 0x3d, { false, "restore" } } +}; + +const sparc_disassembler::int_op_desc_map::value_type sparc_disassembler::V8_INT_OP_DESC[] = { + { 0x0a, { false, "umul" } }, { 0x1a, { false, "umulcc" } }, + { 0x0b, { false, "smul" } }, { 0x1b, { false, "smulcc" } }, + { 0x0e, { false, "udiv" } }, { 0x1e, { false, "udivcc" } }, + { 0x0f, { false, "sdiv" } }, { 0x1f, { false, "sdivcc" } } +}; + +const sparc_disassembler::int_op_desc_map::value_type sparc_disassembler::V9_INT_OP_DESC[] = { + { 0x09, { false, "mulx" } }, + { 0x0d, { false, "udivx" } }, + + { 0x2d, { false, "sdivx" } } }; const sparc_disassembler::state_reg_desc_map::value_type sparc_disassembler::V9_STATE_REG_DESC[] = { - { 1, { true, nullptr, nullptr } }, - { 2, { false, "%ccr", "%ccr" } }, - { 3, { false, "%asi", "%asi" } }, - { 4, { false, "%tick", nullptr } }, - { 5, { false, "%pc", nullptr } }, - { 6, { false, "%fprs", "%fprs" } } + { 1, { true, nullptr, nullptr } }, + { 2, { false, "%ccr", "%ccr" } }, + { 3, { false, "%asi", "%asi" } }, + { 4, { false, "%tick", nullptr } }, + { 5, { false, "%pc", nullptr } }, + { 6, { false, "%fprs", "%fprs" } } }; const char * const sparc_disassembler::MOVCC_CC_NAMES[8] = { @@ -286,8 +283,7 @@ const sparc_disassembler::asi_desc_map::value_type sparc_disassembler::V9_ASI_DE { 0x8b, { "#ASI_SNF_L", nullptr } } }; -const sparc_disassembler::prftch_desc_map::value_type sparc_disassembler::V9_PRFTCH_DESC[] = -{ +const sparc_disassembler::prftch_desc_map::value_type sparc_disassembler::V9_PRFTCH_DESC[] = { { 0x00, { "#n_reads" } }, { 0x01, { "#one_read" } }, { 0x02, { "#n_writes" } }, @@ -295,12 +291,154 @@ const sparc_disassembler::prftch_desc_map::value_type sparc_disassembler::V9_PRF { 0x04, { "#page" } } }; +const sparc_disassembler::vis_op_desc_map::value_type sparc_disassembler::VIS1_OP_DESC[] = { + { 0x000, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge8" } }, + { 0x002, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge8l" } }, + { 0x004, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge16" } }, + { 0x006, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge16l" } }, + { 0x008, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge32" } }, + { 0x00a, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge32l" } }, + + { 0x010, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "array8" } }, + { 0x012, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "array16" } }, + { 0x014, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "array32" } }, + { 0x018, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, true, "alignaddr" } }, + { 0x01a, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, true, "alignaddrl" } }, + + { 0x020, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::I, false, "fcmple16" } }, + { 0x022, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::I, false, "fcmpne16" } }, + { 0x024, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::I, false, "fcmple32" } }, + { 0x026, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::I, false, "fcmpne32" } }, + { 0x028, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::I, false, "fcmpgt16" } }, + { 0x02a, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::I, false, "fcmpeq16" } }, + { 0x02c, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::I, false, "fcmpgt32" } }, + { 0x02e, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::I, false, "fcmpeq32" } }, + + { 0x031, { vis_op_desc::Fs, vis_op_desc::Fd, vis_op_desc::Fd, false, "fmul8x16" } }, + { 0x033, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fd, false, "fmul8x16au" } }, + { 0x035, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fd, false, "fmul8x16al" } }, + { 0x036, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fmul8sux16" } }, + { 0x037, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fmul8ulx16" } }, + { 0x038, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fd, false, "fmuld8sux16" } }, + { 0x039, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fd, false, "fmuld8ulx16" } }, + { 0x03a, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fpack32" } }, + { 0x03b, { vis_op_desc::X, vis_op_desc::Fd, vis_op_desc::Fs, false, "fpack16" } }, + { 0x03d, { vis_op_desc::X, vis_op_desc::Fd, vis_op_desc::Fs, false, "fpackfix" } }, + { 0x03e, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "pdist" } }, + + { 0x048, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "faligndata" } }, + { 0x04b, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fd, false, "fpmerge" } }, + { 0x04d, { vis_op_desc::X, vis_op_desc::Fs, vis_op_desc::Fd, false, "fexpand" } }, + + { 0x050, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fpadd16" } }, + { 0x051, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fs, false, "fpadd16s" } }, + { 0x052, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fpadd32" } }, + { 0x053, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fs, false, "fpadd32s" } }, + { 0x054, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fpsub16" } }, + { 0x055, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fs, false, "fpsub16s" } }, + { 0x056, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fpsub32" } }, + { 0x057, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fs, false, "fpsub32s" } }, + + { 0x060, { vis_op_desc::X, vis_op_desc::X, vis_op_desc::Fd, false, "fzero" } }, + { 0x061, { vis_op_desc::X, vis_op_desc::X, vis_op_desc::Fs, false, "fzeros" } }, + { 0x062, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fnor" } }, + { 0x063, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fs, false, "fnors" } }, + { 0x064, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fandnot2" } }, + { 0x065, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fs, false, "fandnot2s" } }, + { 0x066, { vis_op_desc::X, vis_op_desc::Fd, vis_op_desc::Fd, false, "fnot2" } }, + { 0x067, { vis_op_desc::X, vis_op_desc::Fs, vis_op_desc::Fs, false, "fnot2s" } }, + { 0x068, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fandnot1" } }, + { 0x069, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fs, false, "fandnot1s" } }, + { 0x06a, { vis_op_desc::Fd, vis_op_desc::X, vis_op_desc::Fd, false, "fnot1" } }, + { 0x06b, { vis_op_desc::Fs, vis_op_desc::X, vis_op_desc::Fs, false, "fnot1s" } }, + { 0x06c, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fxor" } }, + { 0x06d, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fs, false, "fxors" } }, + { 0x06e, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fnand" } }, + { 0x06f, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fs, false, "fnands" } }, + + { 0x070, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fand" } }, + { 0x071, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fs, false, "fands" } }, + { 0x072, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fxnor" } }, + { 0x073, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fs, false, "fxnors" } }, + { 0x074, { vis_op_desc::Fd, vis_op_desc::X, vis_op_desc::Fd, false, "fsrc1" } }, + { 0x075, { vis_op_desc::Fs, vis_op_desc::X, vis_op_desc::Fs, false, "fsrc1s" } }, + { 0x076, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fornot2" } }, + { 0x077, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fs, false, "fornot2s" } }, + { 0x078, { vis_op_desc::X, vis_op_desc::Fd, vis_op_desc::Fd, false, "fsrc2" } }, + { 0x079, { vis_op_desc::X, vis_op_desc::Fs, vis_op_desc::Fs, false, "fsrc2s" } }, + { 0x07a, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "fornot1" } }, + { 0x07b, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fs, false, "fornot1s" } }, + { 0x07c, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "for" } }, + { 0x07d, { vis_op_desc::Fs, vis_op_desc::Fs, vis_op_desc::Fs, false, "fors" } }, + { 0x07e, { vis_op_desc::X, vis_op_desc::X, vis_op_desc::Fd, false, "fone" } }, + { 0x07f, { vis_op_desc::X, vis_op_desc::X, vis_op_desc::Fs, false, "fones" } }, + + { 0x080, { vis_op_desc::X, vis_op_desc::X, vis_op_desc::X, false, "shutdown" } } +}; + +const sparc_disassembler::state_reg_desc_map::value_type sparc_disassembler::VIS1_STATE_REG_DESC[] = { + { 19, { false, "%gsr", "%gsr" } } +}; + +const sparc_disassembler::asi_desc_map::value_type sparc_disassembler::VIS1_ASI_DESC[] = { + { 0x2c, { "#ASI_NUCLEUS_QUAD_LDD_L", nullptr } }, + { 0x70, { "#ASI_BLK_AIUP", nullptr } }, + { 0x71, { "#ASI_BLK_AIUS", nullptr } }, + { 0x78, { "#ASI_BLK_AIUPL", nullptr } }, + { 0x79, { "#ASI_BLK_AIUSL", nullptr } }, + { 0xc0, { "#ASI_PST8_P", nullptr } }, + { 0xc1, { "#ASI_PST8_S", nullptr } }, + { 0xc2, { "#ASI_PST16_P", nullptr } }, + { 0xc3, { "#ASI_PST16_S", nullptr } }, + { 0xc4, { "#ASI_PST32_P", nullptr } }, + { 0xc5, { "#ASI_PST32_S", nullptr } }, + { 0xc8, { "#ASI_PST8_PL", nullptr } }, + { 0xc9, { "#ASI_PST8_SL", nullptr } }, + { 0xca, { "#ASI_PST16_PL", nullptr } }, + { 0xcb, { "#ASI_PST16_SL", nullptr } }, + { 0xcc, { "#ASI_PST32_PL", nullptr } }, + { 0xcd, { "#ASI_PST32_SL", nullptr } }, + { 0xd0, { "#ASI_FL8_P", nullptr } }, + { 0xd1, { "#ASI_FL8_S", nullptr } }, + { 0xd2, { "#ASI_FL16_P", nullptr } }, + { 0xd3, { "#ASI_FL16_S", nullptr } }, + { 0xd8, { "#ASI_FL8_PL", nullptr } }, + { 0xd9, { "#ASI_FL8_SL", nullptr } }, + { 0xda, { "#ASI_FL16_PL", nullptr } }, + { 0xdb, { "#ASI_FL16_SL", nullptr } }, + { 0xe0, { "#ASI_BLOCK_COMMIT_P", nullptr } }, + { 0xe1, { "#ASI_BLOCK_COMMIT_S", nullptr } }, + { 0xf0, { "#ASI_BLOCK_P", nullptr } }, + { 0xf1, { "#ASI_BLOCK_S", nullptr } }, + { 0xf8, { "#ASI_BLOCK_PL", nullptr } }, + { 0xf9, { "#ASI_BLOCK_SL", nullptr } } +}; + +const sparc_disassembler::vis_op_desc_map::value_type sparc_disassembler::VIS2_OP_DESC[] = { + { 0x001, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge8n" } }, + { 0x003, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge8ln" } }, + { 0x005, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge16n" } }, + { 0x007, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge16ln" } }, + { 0x009, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge32n" } }, + { 0x00b, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, false, "edge32ln" } }, + + { 0x019, { vis_op_desc::I, vis_op_desc::I, vis_op_desc::I, true, "bmask" } }, + + { 0x04c, { vis_op_desc::Fd, vis_op_desc::Fd, vis_op_desc::Fd, false, "bshuffle" } } +}; + inline UINT32 sparc_disassembler::freg(UINT32 val, bool shift) const { return (shift && (m_version >= 9)) ? ((val & 0x1e) | ((val << 5) & 0x20)) : val; } +template <typename T> inline void sparc_disassembler::add_int_op_desc(const T &desc) +{ + for (const auto &it : desc) + m_int_op_desc.insert(it); +} + template <typename T> inline void sparc_disassembler::add_fpop1_desc(const T &desc) { for (const auto &it : desc) @@ -319,6 +457,12 @@ template <typename T> inline void sparc_disassembler::add_ldst_desc(const T &des m_ldst_desc.insert(it); } +template <typename T> inline void sparc_disassembler::add_vis_op_desc(const T &desc) +{ + for (const auto &it : desc) + m_vis_op_desc.insert(it); +} + inline void sparc_disassembler::pad_op_field(char *buf, char *&output) const { while ((output - buf) < m_op_field_width) *output++ = ' '; @@ -346,22 +490,29 @@ sparc_disassembler::sparc_disassembler(unsigned version) FBFCC_DESC, // branch on floating-point condition codes (version == 8) ? CBCCC_DESC : EMPTY_BRANCH_DESC // branch on coprocessor condition codes, SPARCv8 } - , m_simple_int_op_desc(std::begin(SIMPLE_INT_OP_DESC), std::end(SIMPLE_INT_OP_DESC)) + , m_int_op_desc(std::begin(V7_INT_OP_DESC), std::end(V7_INT_OP_DESC)) , m_state_reg_desc() , m_fpop1_desc(std::begin(V7_FPOP1_DESC), std::end(V7_FPOP1_DESC)) , m_fpop2_desc(std::begin(V7_FPOP2_DESC), std::end(V7_FPOP2_DESC)) , m_ldst_desc(std::begin(V7_LDST_DESC), std::end(V7_LDST_DESC)) , m_asi_desc() , m_prftch_desc() + , m_vis_op_desc() { + if (m_version >= 8) + { + add_int_op_desc(V8_INT_OP_DESC); + } + if (m_version >= 9) { m_op_field_width = 11; - m_simple_int_op_desc.find(0x08)->second.mnemonic = "addc"; - m_simple_int_op_desc.find(0x0c)->second.mnemonic = "subc"; - m_simple_int_op_desc.find(0x18)->second.mnemonic = "addccc"; - m_simple_int_op_desc.find(0x1c)->second.mnemonic = "subccc"; + m_int_op_desc.find(0x08)->second.mnemonic = "addc"; + m_int_op_desc.find(0x0c)->second.mnemonic = "subc"; + m_int_op_desc.find(0x18)->second.mnemonic = "addccc"; + m_int_op_desc.find(0x1c)->second.mnemonic = "subccc"; + add_int_op_desc(V9_INT_OP_DESC); add_state_reg_desc(V9_STATE_REG_DESC), add_fpop1_desc(V9_FPOP1_DESC); @@ -384,6 +535,22 @@ sparc_disassembler::sparc_disassembler(unsigned version) } +void sparc_disassembler::enable_vis1() +{ + m_op_field_width = std::max(m_op_field_width, 12); + add_vis_op_desc(VIS1_OP_DESC); + add_state_reg_desc(VIS1_STATE_REG_DESC); + add_asi_desc(VIS1_ASI_DESC); +} + + +void sparc_disassembler::enable_vis2() +{ + enable_vis1(); + add_vis_op_desc(VIS2_OP_DESC); +} + + offs_t sparc_disassembler::dasm(char *buf, offs_t pc, UINT32 op) const { switch (OP) @@ -405,7 +572,7 @@ offs_t sparc_disassembler::dasm(char *buf, offs_t pc, UINT32 op) const } return 4 | DASMFLAG_SUPPORTED; case 1: - print(buf, "%-*s%%pc%c0x%08x ! %08x", m_op_field_width, "call", (DISP30 < 0) ? '-' : '+', std::abs(DISP30), pc + DISP30); + print(buf, "%-*s%%pc%c0x%08x ! 0x%08x", m_op_field_width, "call", (DISP30 < 0) ? '-' : '+', std::abs(DISP30), pc + DISP30); return 4 | DASMFLAG_SUPPORTED; case 2: switch (OP3) @@ -609,8 +776,7 @@ offs_t sparc_disassembler::dasm(char *buf, offs_t pc, UINT32 op) const case 0x35: return dasm_fpop2(buf, pc, op); case 0x36: - // TODO: hooks for IMPDEP1/CPop1 - break; + return dasm_impdep1(buf, pc, op); case 0x37: // TODO: hooks for IMPDEP2/CPop2 break; @@ -654,8 +820,8 @@ offs_t sparc_disassembler::dasm(char *buf, offs_t pc, UINT32 op) const break; } { - const auto it(m_simple_int_op_desc.find(OP3)); - if ((it != m_simple_int_op_desc.end()) && (m_version >= it->second.min_version)) + const auto it(m_int_op_desc.find(OP3)); + if (it != m_int_op_desc.end()) { if (!USEIMM) print(buf, "%-*s%s,%s,%s", m_op_field_width, it->second.mnemonic, REG_NAMES[RS1], REG_NAMES[RS2], REG_NAMES[RD]); @@ -821,7 +987,7 @@ offs_t sparc_disassembler::dasm_write_state_reg(char *buf, offs_t pc, UINT32 op) } else { - const char *const comment((RD < 16) ? "reserved" : "implementation-dependent"); + const char * const comment((RD < 16) ? "reserved" : "implementation-dependent"); if (USEIMM) print(buf, "%-*s%s,%d,%%asr%d ! %s", m_op_field_width, "wr", REG_NAMES[RS1], SIMM13, RD, comment); else print(buf, "%-*s%s,%s,%%asr%d ! %s", m_op_field_width, "wr", REG_NAMES[RS1], REG_NAMES[RS2], RD, comment); } @@ -925,6 +1091,36 @@ offs_t sparc_disassembler::dasm_fpop2(char *buf, offs_t pc, UINT32 op) const } +offs_t sparc_disassembler::dasm_impdep1(char *buf, offs_t pc, UINT32 op) const +{ + const auto it(m_vis_op_desc.find(OPF)); + if (it != m_vis_op_desc.end()) + { + print(buf, "%-*s", m_op_field_width, it->second.mnemonic); + bool args(false); + if (it->second.collapse && !RS1) + { + dasm_vis_arg(buf, args, it->second.rs2, RS2); + } + else if (it->second.collapse && !RS2) + { + dasm_vis_arg(buf, args, it->second.rs1, RS1); + } + else + { + dasm_vis_arg(buf, args, it->second.rs1, RS1); + dasm_vis_arg(buf, args, it->second.rs2, RS2); + } + dasm_vis_arg(buf, args, it->second.rd, RD); + return 4 | DASMFLAG_SUPPORTED; + } + + // TODO: driver hook for other kinds of coprocessor? + + return dasm_invalid(buf, pc, op); +} + + offs_t sparc_disassembler::dasm_jmpl(char *buf, offs_t pc, UINT32 op) const { if (USEIMM && (RD == 0) && ((RS1 == 15) || (RS1 == 31)) && (SIMM13 == 8)) @@ -1156,20 +1352,20 @@ void sparc_disassembler::dasm_asi_comment(char *&output, UINT32 op) const } -CPU_DISASSEMBLE( sparcv7 ) -{ - UINT32 op = *reinterpret_cast<const UINT32 *>(oprom); - return DASM_V7.dasm(buffer, pc, BIG_ENDIANIZE_INT32(op)); -} - -CPU_DISASSEMBLE( sparcv8 ) -{ - UINT32 op = *reinterpret_cast<const UINT32 *>(oprom); - return DASM_V8.dasm(buffer, pc, BIG_ENDIANIZE_INT32(op)); -} - -CPU_DISASSEMBLE( sparcv9 ) +void sparc_disassembler::dasm_vis_arg(char *&output, bool &args, vis_op_desc::arg fmt, UINT32 reg) const { - UINT32 op = *reinterpret_cast<const UINT32 *>(oprom); - return DASM_V9.dasm(buffer, pc, BIG_ENDIANIZE_INT32(op)); + switch (fmt) + { + case vis_op_desc::X: + break; + case vis_op_desc::I: + print(output, args ? ",%s" : "%s", REG_NAMES[reg]); + args = true; + break; + case vis_op_desc::Fs: + case vis_op_desc::Fd: + print(output, args ? ",%%f%d" : "%%f%d", freg(reg, (fmt == vis_op_desc::Fd))); + args = true; + break; + }; } diff --git a/src/devices/cpu/sparc/sparcdasm.h b/src/devices/cpu/sparc/sparcdasm.h index e745de4721d..77e39eda177 100644 --- a/src/devices/cpu/sparc/sparcdasm.h +++ b/src/devices/cpu/sparc/sparcdasm.h @@ -38,6 +38,9 @@ public: sparc_disassembler(unsigned version); + void enable_vis1(); + void enable_vis2(); + template <typename T> void add_state_reg_desc(const T &desc) { for (const auto &it : desc) @@ -97,7 +100,6 @@ private: struct int_op_desc { - unsigned min_version; bool hex_imm; const char *mnemonic; }; @@ -132,6 +134,17 @@ private: }; typedef std::map<UINT8, ldst_desc> ldst_desc_map; + struct vis_op_desc + { + enum arg { X, I, Fs, Fd }; + arg rs1 = X; + arg rs2 = X; + arg rd = X; + bool collapse = false; + const char *mnemonic = nullptr; + }; + typedef std::map<UINT16, vis_op_desc> vis_op_desc_map; + offs_t dasm_invalid(char *buf, offs_t pc, UINT32 op) const; offs_t dasm_branch(char *buf, offs_t pc, UINT32 op) const; offs_t dasm_shift(char *buf, offs_t pc, UINT32 op, const char *mnemonic, const char *mnemonicx, const char *mnemonicx0) const; @@ -141,6 +154,7 @@ private: offs_t dasm_move_reg_cond(char *buf, offs_t pc, UINT32 op) const; offs_t dasm_fpop1(char *buf, offs_t pc, UINT32 op) const; offs_t dasm_fpop2(char *buf, offs_t pc, UINT32 op) const; + offs_t dasm_impdep1(char *buf, offs_t pc, UINT32 op) const; offs_t dasm_jmpl(char *buf, offs_t pc, UINT32 op) const; offs_t dasm_return(char *buf, offs_t pc, UINT32 op) const; offs_t dasm_tcc(char *buf, offs_t pc, UINT32 op) const; @@ -149,12 +163,15 @@ private: void dasm_address(char *&output, UINT32 op) const; void dasm_asi(char *&output, UINT32 op) const; void dasm_asi_comment(char *&output, UINT32 op) const; + void dasm_vis_arg(char *&output, bool &args, vis_op_desc::arg fmt, UINT32 reg) const; UINT32 freg(UINT32 val, bool shift) const; + template <typename T> void add_int_op_desc(const T &desc); template <typename T> void add_fpop1_desc(const T &desc); template <typename T> void add_fpop2_desc(const T &desc); template <typename T> void add_ldst_desc(const T &desc); + template <typename T> void add_vis_op_desc(const T &desc); void pad_op_field(char *buf, char *&output) const; ATTR_PRINTF(2, 3) static void print(char *&output, const char *fmt, ...); @@ -167,7 +184,9 @@ private: static const branch_desc FBPFCC_DESC; static const branch_desc FBFCC_DESC; static const branch_desc CBCCC_DESC; - static const int_op_desc_map::value_type SIMPLE_INT_OP_DESC[]; + static const int_op_desc_map::value_type V7_INT_OP_DESC[]; + static const int_op_desc_map::value_type V8_INT_OP_DESC[]; + static const int_op_desc_map::value_type V9_INT_OP_DESC[]; static const state_reg_desc_map::value_type V9_STATE_REG_DESC[]; static const char * const MOVCC_CC_NAMES[8]; static const char * const MOVCC_COND_NAMES[32]; @@ -181,17 +200,22 @@ private: static const ldst_desc_map::value_type V9_LDST_DESC[]; static const asi_desc_map::value_type V9_ASI_DESC[]; static const prftch_desc_map::value_type V9_PRFTCH_DESC[]; + static const vis_op_desc_map::value_type VIS1_OP_DESC[]; + static const state_reg_desc_map::value_type VIS1_STATE_REG_DESC[]; + static const asi_desc_map::value_type VIS1_ASI_DESC[]; + static const vis_op_desc_map::value_type VIS2_OP_DESC[]; unsigned m_version; int m_op_field_width; branch_desc m_branch_desc[8]; - int_op_desc_map m_simple_int_op_desc; + int_op_desc_map m_int_op_desc; state_reg_desc_map m_state_reg_desc; fpop1_desc_map m_fpop1_desc; fpop2_desc_map m_fpop2_desc; ldst_desc_map m_ldst_desc; asi_desc_map m_asi_desc; prftch_desc_map m_prftch_desc; + vis_op_desc_map m_vis_op_desc; }; CPU_DISASSEMBLE( sparcv7 ); diff --git a/src/devices/cpu/t11/t11.cpp b/src/devices/cpu/t11/t11.cpp index 4930b956ea5..5db830866ee 100644 --- a/src/devices/cpu/t11/t11.cpp +++ b/src/devices/cpu/t11/t11.cpp @@ -285,7 +285,7 @@ void t11_device::device_start() state_add( T11_R5, "R5", m_reg[5].w.l).formatstr("%04X"); state_add(STATE_GENPC, "curpc", m_reg[7].w.l).noshow(); - state_add(STATE_GENFLAGS, "GENFLAGS", m_psw.b.l).noshow(); + state_add(STATE_GENFLAGS, "GENFLAGS", m_psw.b.l).formatstr("%8s").noshow(); state_add(STATE_GENPCBASE, "GENPCBASE", m_ppc.w.l).noshow(); m_icountptr = &m_icount; diff --git a/src/devices/cpu/tms32025/tms32025.cpp b/src/devices/cpu/tms32025/tms32025.cpp index c202c243ea2..a73ec8f21da 100644 --- a/src/devices/cpu/tms32025/tms32025.cpp +++ b/src/devices/cpu/tms32025/tms32025.cpp @@ -131,8 +131,6 @@ Table 3-2. TMS32025/26 Memory Blocks #define P_IN(A) (m_io->read_word((A)<<1)) #define P_OUT(A,V) (m_io->write_word(((A)<<1),(V))) -#define S_IN(A) (m_io->read_word((A)<<1)) -#define S_OUT(A,V) (m_io->write_word(((A)<<1),(V))) #define M_RDOP(A) ((m_pgmmap[(A) >> 7]) ? (m_pgmmap[(A) >> 7][(A) & 0x7f]) : m_direct->read_word((A)<<1)) #define M_RDOP_ARG(A) ((m_pgmmap[(A) >> 7]) ? (m_pgmmap[(A) >> 7][(A) & 0x7f]) : m_direct->read_word((A)<<1)) @@ -212,7 +210,13 @@ tms32025_device::tms32025_device(const machine_config &mconfig, const char *tag, : cpu_device(mconfig, TMS32025, "TMS32025", tag, owner, clock, "tms32025", __FILE__) , m_program_config("program", ENDIANNESS_BIG, 16, 16, -1) , m_data_config("data", ENDIANNESS_BIG, 16, 16, -1) - , m_io_config("io", ENDIANNESS_BIG, 16, 16+1, -1) + , m_io_config("io", ENDIANNESS_BIG, 16, 16, -1) + , m_bio_in(*this) + , m_hold_in(*this) + , m_hold_ack_out(*this) + , m_xf_out(*this) + , m_dr_in(*this) + , m_dx_out(*this) { } @@ -221,7 +225,13 @@ tms32025_device::tms32025_device(const machine_config &mconfig, device_type type : cpu_device(mconfig, type, name, tag, owner, clock, shortname, source) , m_program_config("program", ENDIANNESS_BIG, 16, 16, -1) , m_data_config("data", ENDIANNESS_BIG, 16, 16, -1) - , m_io_config("io", ENDIANNESS_BIG, 16, 16+1, -1) + , m_io_config("io", ENDIANNESS_BIG, 16, 16, -1) + , m_bio_in(*this) + , m_hold_in(*this) + , m_hold_ack_out(*this) + , m_xf_out(*this) + , m_dr_in(*this) + , m_dx_out(*this) { } @@ -674,7 +684,7 @@ void tms32025_device::bgz() } void tms32025_device::bioz() { - if (S_IN(TMS32025_BIO) != CLEAR_LINE) SET_PC(M_RDOP_ARG(m_PC)); + if (m_bio_in() != CLEAR_LINE) SET_PC(M_RDOP_ARG(m_PC)); else m_PC++ ; MODIFY_AR_ARP(); } @@ -1276,7 +1286,7 @@ void tms32025_device::rtxm() /** Serial port stuff */ void tms32025_device::rxf() { CLR1(XF_FLAG); - S_OUT(TMS32025_XF,CLEAR_LINE); + m_xf_out(CLEAR_LINE); } void tms32025_device::sach() { @@ -1485,7 +1495,7 @@ void tms32025_device::subt() void tms32025_device::sxf() { SET1(XF_FLAG); - S_OUT(TMS32025_XF,ASSERT_LINE); + m_xf_out(ASSERT_LINE); } void tms32025_device::tblr() { @@ -1639,6 +1649,13 @@ void tms32025_device::device_start() m_data = &space(AS_DATA); m_io = &space(AS_IO); + m_bio_in.resolve_safe(0xffff); + m_hold_in.resolve_safe(0xffff); + m_hold_ack_out.resolve_safe(); + m_xf_out.resolve_safe(); + m_dr_in.resolve_safe(0xffff); + m_dx_out.resolve_safe(); + m_PREVPC = 0; m_PFC = 0; m_STR0 = 0; @@ -1846,7 +1863,7 @@ void tms32025_device::device_reset() m_RPTC = 0; /* Reset repeat counter to 0 */ m_IFR = 0; /* IRQ pending flags */ - S_OUT(TMS32025_XF,ASSERT_LINE); /* XF flag is high. Must set the pin */ + m_xf_out(ASSERT_LINE); /* XF flag is high. Must set the pin */ /* Set the internal memory mapped registers */ GREG = 0; @@ -1941,7 +1958,7 @@ int tms32025_device::process_IRQs() } if ((m_IFR & 0x10) && (IMR & 0x10)) { /* Serial port receive IRQ (internal) */ // logerror("TMS32025: Active RINT (Serial receive)\n"); - DRR = S_IN(TMS32025_DR); + DRR = m_dr_in(); SET_PC(0x001A); m_idle = 0; m_IFR &= (~0x10); @@ -1950,7 +1967,7 @@ int tms32025_device::process_IRQs() } if ((m_IFR & 0x20) && (IMR & 0x20)) { /* Serial port transmit IRQ (internal) */ // logerror("TMS32025: Active XINT (Serial transmit)\n"); - S_OUT(TMS32025_DX,DXR); + m_dx_out(DXR); SET_PC(0x001C); m_idle = 0; m_IFR &= (~0x20); @@ -2005,9 +2022,9 @@ again: void tms32025_device::execute_run() { /**** Respond to external hold signal */ - if (S_IN(TMS32025_HOLD) == ASSERT_LINE) { + if (m_hold_in() == ASSERT_LINE) { if (m_hold == 0) { - S_OUT(TMS32025_HOLDA,ASSERT_LINE); /* Hold-Ack (active low) */ + m_hold_ack_out(ASSERT_LINE); /* Hold-Ack (active low) */ } m_hold = 1; if (HM) { @@ -2021,7 +2038,7 @@ void tms32025_device::execute_run() } else { if (m_hold == 1) { - S_OUT(TMS32025_HOLDA,CLEAR_LINE); /* Hold-Ack (active low) */ + m_hold_ack_out(CLEAR_LINE); /* Hold-Ack (active low) */ process_timer(3); } m_hold = 0; diff --git a/src/devices/cpu/tms32025/tms32025.h b/src/devices/cpu/tms32025/tms32025.h index daac81c8314..0d414c1cb4f 100644 --- a/src/devices/cpu/tms32025/tms32025.h +++ b/src/devices/cpu/tms32025/tms32025.h @@ -23,17 +23,25 @@ #define __TMS32025_H__ +#define MCFG_TMS32025_BIO_IN_CB(_devcb) \ + devcb = &tms32025_device::set_bio_in_cb(*device, DEVCB_##_devcb); /* BIO input */ +#define MCFG_TMS32025_HOLD_IN_CB(_devcb) \ + devcb = &tms32025_device::set_hold_in_cb(*device, DEVCB_##_devcb); /* HOLD input */ -#define TMS32025_BIO 0x10000 /* BIO input */ -#define TMS32025_HOLD 0x10001 /* HOLD input */ -#define TMS32025_HOLDA 0x10001 /* HOLD Acknowledge output */ -#define TMS32025_XF 0x10002 /* XF output */ -#define TMS32025_DR 0x10003 /* Serial Data Receive input */ -#define TMS32025_DX 0x10003 /* Serial Data Transmit output */ +#define MCFG_TMS32025_HOLD_ACK_OUT_CB(_devcb) \ + devcb = &tms32025_device::set_hold_ack_out_cb(*device, DEVCB_##_devcb); /* HOLD Acknowledge output */ + +#define MCFG_TMS32025_XF_OUT_CB(_devcb) \ + devcb = &tms32025_device::set_xf_out_cb(*device, DEVCB_##_devcb); /* XF output */ +#define MCFG_TMS32025_DR_IN_CB(_devcb) \ + devcb = &tms32025_device::set_dr_in_cb(*device, DEVCB_##_devcb); /* Serial Data Receive input */ +#define MCFG_TMS32025_DX_OUT_CB(_devcb) \ + devcb = &tms32025_device::set_dx_out_cb(*device, DEVCB_##_devcb); /* Serial Data Transmit output */ + /**************************************************************************** * Interrupt constants */ @@ -75,6 +83,14 @@ public: // construction/destruction tms32025_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); tms32025_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source); + + // static configuration helpers + template<class _Object> static devcb_base & set_bio_in_cb(device_t &device, _Object object) { return downcast<tms32025_device &>(device).m_bio_in.set_callback(object); } + template<class _Object> static devcb_base & set_hold_in_cb(device_t &device, _Object object) { return downcast<tms32025_device &>(device).m_hold_in.set_callback(object); } + template<class _Object> static devcb_base & set_hold_ack_out_cb(device_t &device, _Object object) { return downcast<tms32025_device &>(device).m_hold_ack_out.set_callback(object); } + template<class _Object> static devcb_base & set_xf_out_cb(device_t &device, _Object object) { return downcast<tms32025_device &>(device).m_xf_out.set_callback(object); } + template<class _Object> static devcb_base & set_dr_in_cb(device_t &device, _Object object) { return downcast<tms32025_device &>(device).m_dr_in.set_callback(object); } + template<class _Object> static devcb_base & set_dx_out_cb(device_t &device, _Object object) { return downcast<tms32025_device &>(device).m_dx_out.set_callback(object); } protected: // device-level overrides @@ -119,6 +135,13 @@ private: static const tms32025_opcode s_opcode_CE_subset[256]; static const tms32025_opcode s_opcode_Dx_subset[8]; + devcb_read16 m_bio_in; + devcb_read16 m_hold_in; + devcb_write16 m_hold_ack_out; + devcb_write16 m_xf_out; + devcb_read16 m_dr_in; + devcb_write16 m_dx_out; + /******************** CPU Internal Registers *******************/ UINT16 m_PREVPC; /* previous program counter */ diff --git a/src/devices/cpu/tms9900/ti990_10.cpp b/src/devices/cpu/tms9900/ti990_10.cpp index c336d5e689a..97510d1f610 100644 --- a/src/devices/cpu/tms9900/ti990_10.cpp +++ b/src/devices/cpu/tms9900/ti990_10.cpp @@ -43,7 +43,7 @@ ti990_10_device::ti990_10_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : cpu_device(mconfig, TI990_10, "TI990/10 CPU", tag, owner, clock, "ti990_10_cpu", __FILE__), - m_program_config("program", ENDIANNESS_BIG, 16, 16), + m_program_config("program", ENDIANNESS_BIG, 16, 21), m_io_config("cru", ENDIANNESS_BIG, 8, 12), m_prgspace(nullptr), m_cru(nullptr) diff --git a/src/devices/video/zeus2.cpp b/src/devices/video/zeus2.cpp index cb35cf501c6..59c68e4129a 100644 --- a/src/devices/video/zeus2.cpp +++ b/src/devices/video/zeus2.cpp @@ -221,10 +221,10 @@ if (machine().input().code_pressed(KEYCODE_DOWN)) { zbase -= 1.0f; popmessage("Z if (machine().input().code_pressed(KEYCODE_RIGHT) && texel_width < 512) { texel_width <<= 1; while (machine().input().code_pressed(KEYCODE_RIGHT)) ; } if (yoffs < 0) yoffs = 0; - if (0) + if (1) base = waveram0_ptr_from_expanded_addr(yoffs << 16); else - base = (void *)&m_frameColor[yoffs<<9]; + base = (void *)&m_frameColor[yoffs << 6]; int xoffs = screen.visible_area().min_x; for (y = cliprect.min_y; y <= cliprect.max_y; y++) @@ -232,7 +232,7 @@ if (machine().input().code_pressed(KEYCODE_DOWN)) { zbase -= 1.0f; popmessage("Z UINT32 *dest = &bitmap.pix32(y); for (x = cliprect.min_x; x <= cliprect.max_x; x++) { - if (0) { + if (1) { UINT8 tex = get_texel_8bit((UINT64 *)base, y, x, texel_width); dest[x] = (tex << 16) | (tex << 8) | tex; } @@ -241,7 +241,7 @@ if (machine().input().code_pressed(KEYCODE_DOWN)) { zbase -= 1.0f; popmessage("Z } } } - popmessage("offs = %06X base = %08X", yoffs, yoffs<<9); + popmessage("offs = %06X base = %08X", yoffs, yoffs<<16); } return 0; @@ -776,7 +776,7 @@ int zeus2_device::zeus2_fifo_process(const UINT32 *data, int numwords) return FALSE; if (log_fifo) { - log_fifo_command(data, numwords, " -- unknown control + hack clear screen\n"); + log_fifo_command(data, numwords, " -- unknown control + happens after clear screen\n"); logerror("\t\tvector %8.2f %8.2f %8.5f\n", (double) convert_float(data[1]), (double) convert_float(data[2]), @@ -816,7 +816,7 @@ int zeus2_device::zeus2_fifo_process(const UINT32 *data, int numwords) case 0x25: if (log_fifo) log_fifo_command(data, numwords, "\n"); - //zeus_quad_size = 10; + zeus_quad_size = 14; break; /* 0x31: sync pipeline? (thegrid) */ @@ -864,7 +864,7 @@ void zeus2_device::zeus2_draw_model(UINT32 baseaddr, UINT16 count, int logit) UINT32 databuffer[32]; int databufcount = 0; int model_done = FALSE; - UINT32 texoffs = 0; + UINT32 texdata = 0; int quadsize = zeus_quad_size; if (logit) @@ -914,9 +914,9 @@ void zeus2_device::zeus2_draw_model(UINT32 baseaddr, UINT16 count, int logit) case 0x22: /* crusnexo */ if (((databuffer[0] >> 16) & 0xff) == 0x9b) { - texoffs = databuffer[1]; + texdata = databuffer[1]; if (logit) - logerror("texture offset\n"); + logerror("texdata\n"); } else if (logit) logerror("unknown offset\n"); @@ -936,12 +936,14 @@ void zeus2_device::zeus2_draw_model(UINT32 baseaddr, UINT16 count, int logit) break; case 0x2d: // atlantis - texoffs = databuffer[1]; - poly->zeus2_draw_quad(&databuffer[1], texoffs, logit); + texdata = databuffer[1]; + databuffer[1] = m_renderRegs[0x6]; + //poly->zeus2_draw_quad(&databuffer[1], texoffs, logit); + poly->zeus2_draw_quad(databuffer, texdata, logit); break; case 0x38: /* crusnexo/thegrid */ - poly->zeus2_draw_quad(databuffer, texoffs, logit); + poly->zeus2_draw_quad(databuffer, texdata, logit); break; default: @@ -965,7 +967,7 @@ void zeus2_device::zeus2_draw_model(UINT32 baseaddr, UINT16 count, int logit) /************************************* * Draw a quad *************************************/ -void zeus2_renderer::zeus2_draw_quad(const UINT32 *databuffer, UINT32 texoffs, int logit) +void zeus2_renderer::zeus2_draw_quad(const UINT32 *databuffer, UINT32 texdata, int logit) { z2_poly_vertex clipvert[8]; z2_poly_vertex vert[4]; @@ -976,20 +978,20 @@ void zeus2_renderer::zeus2_draw_quad(const UINT32 *databuffer, UINT32 texoffs, i int i; // INT16 normal[3]; // INT32 rotnormal[3]; - int texmode = texoffs & 0xffff; + int texmode = texdata & 0xffff; if (logit) m_state->logerror("quad\n"); - if (machine().input().code_pressed(KEYCODE_Q) && (texoffs & 0xffff) == 0x119) return; - if (machine().input().code_pressed(KEYCODE_E) && (texoffs & 0xffff) == 0x01d) return; - if (machine().input().code_pressed(KEYCODE_R) && (texoffs & 0xffff) == 0x11d) return; - if (machine().input().code_pressed(KEYCODE_T) && (texoffs & 0xffff) == 0x05d) return; - if (machine().input().code_pressed(KEYCODE_Y) && (texoffs & 0xffff) == 0x0dd) return; - //if (machine().input().code_pressed(KEYCODE_U) && (texoffs & 0xffff) == 0x119) return; - //if (machine().input().code_pressed(KEYCODE_I) && (texoffs & 0xffff) == 0x119) return; - //if (machine().input().code_pressed(KEYCODE_O) && (texoffs & 0xffff) == 0x119) return; - //if (machine().input().code_pressed(KEYCODE_L) && (texoffs & 0x100)) return; + if (machine().input().code_pressed(KEYCODE_Q) && (texdata & 0xffff) == 0x119) return; + if (machine().input().code_pressed(KEYCODE_E) && (texdata & 0xffff) == 0x01d) return; + if (machine().input().code_pressed(KEYCODE_R) && (texdata & 0xffff) == 0x11d) return; + if (machine().input().code_pressed(KEYCODE_T) && (texdata & 0xffff) == 0x05d) return; + if (machine().input().code_pressed(KEYCODE_Y) && (texdata & 0xffff) == 0x0dd) return; + //if (machine().input().code_pressed(KEYCODE_U) && (texdata & 0xffff) == 0x119) return; + //if (machine().input().code_pressed(KEYCODE_I) && (texdata & 0xffff) == 0x119) return; + //if (machine().input().code_pressed(KEYCODE_O) && (texdata & 0xffff) == 0x119) return; + //if (machine().input().code_pressed(KEYCODE_L) && (texdata & 0x100)) return; /* 0 38800000 @@ -1092,7 +1094,7 @@ void zeus2_renderer::zeus2_draw_quad(const UINT32 *databuffer, UINT32 texoffs, i vert[i].y = x * m_state->zeus_matrix[1][0] + y * m_state->zeus_matrix[1][1] + z * m_state->zeus_matrix[1][2] + m_state->zeus_point[1]; vert[i].p[0] = x * m_state->zeus_matrix[2][0] + y * m_state->zeus_matrix[2][1] + z * m_state->zeus_matrix[2][2] + m_state->zeus_point[2]; vert[i].p[0] += m_state->zbase; - vert[i].p[2] += texoffs >> 16; + vert[i].p[2] += texdata >> 16; vert[i].p[1] *= 256.0f; vert[i].p[2] *= 256.0f; @@ -1138,17 +1140,21 @@ void zeus2_renderer::zeus2_draw_quad(const UINT32 *databuffer, UINT32 texoffs, i zeus2_poly_extra_data& extra = this->object_data_alloc(); switch (texmode) { + //case 0x18e: // atlantis + // extra.texwidth = 512; + // break; + case 0x01d: /* crusnexo: RHS of score bar */ case 0x05d: /* crusnexo: background, road */ case 0x0dd: /* crusnexo: license plate letters */ case 0x11d: /* crusnexo: LHS of score bar */ case 0x14d: // atlantis + case 0x18e: // atlantis case 0x15d: /* crusnexo */ case 0x85d: /* crusnexo */ case 0x95d: /* crusnexo */ case 0xc1d: /* crusnexo */ case 0xc5d: /* crusnexo */ - case 0x18e: // atlantis extra.texwidth = 256; break; @@ -1176,10 +1182,10 @@ void zeus2_renderer::zeus2_draw_quad(const UINT32 *databuffer, UINT32 texoffs, i default: { static UINT8 hits[0x10000]; - if (!hits[(texoffs & 0xffff)]) + if (!hits[(texdata & 0xffff)]) { - hits[(texoffs & 0xffff)] = 1; - printf("format = %04X\n", (texoffs & 0xffff)); + hits[(texdata & 0xffff)] = 1; + printf("texMode = %04X\n", (texdata & 0xffff)); } break; } diff --git a/src/devices/video/zeus2.h b/src/devices/video/zeus2.h index b89fe1f82e4..86b1cc3d089 100644 --- a/src/devices/video/zeus2.h +++ b/src/devices/video/zeus2.h @@ -89,7 +89,7 @@ public: void render_poly_8bit(INT32 scanline, const extent_t& extent, const zeus2_poly_extra_data& object, int threadid); - void zeus2_draw_quad(const UINT32 *databuffer, UINT32 texoffs, int logit); + void zeus2_draw_quad(const UINT32 *databuffer, UINT32 texdata, int logit); private: zeus2_device* m_state; diff --git a/src/frontend/mame/luaengine.cpp b/src/frontend/mame/luaengine.cpp index b5c698c0eb5..1b72336eb2f 100644 --- a/src/frontend/mame/luaengine.cpp +++ b/src/frontend/mame/luaengine.cpp @@ -1629,6 +1629,17 @@ int lua_engine::lua_ui_input::l_ui_input_find_mouse(lua_State *L) return 4; } +int lua_engine::lua_render_target::l_render_view_bounds(lua_State *L) +{ + render_target *target = luabridge::Stack<render_target *>::get(L, 1); + const render_bounds &bounds = target->current_view()->bounds(); + lua_pushnumber(L, bounds.x0); + lua_pushnumber(L, bounds.x1); + lua_pushnumber(L, bounds.y0); + lua_pushnumber(L, bounds.y1); + return 4; +} + void *lua_engine::checkparam(lua_State *L, int idx, const char *tname) { const char *name; @@ -2391,7 +2402,10 @@ void lua_engine::initialize() .deriveClass <ui_input_manager, lua_ui_input> ("input") .addFunction ("pressed", &ui_input_manager::pressed) .endClass() - .beginClass <render_target> ("target") + .beginClass <lua_render_target> ("lua_target") + .addCFunction ("view_bounds", &lua_render_target::l_render_view_bounds) + .endClass() + .deriveClass <render_target, lua_render_target> ("target") .addFunction ("width", &render_target::width) .addFunction ("height", &render_target::height) .addFunction ("pixel_aspect", &render_target::pixel_aspect) diff --git a/src/frontend/mame/luaengine.h b/src/frontend/mame/luaengine.h index a616fa1292f..fed95d05f26 100644 --- a/src/frontend/mame/luaengine.h +++ b/src/frontend/mame/luaengine.h @@ -213,6 +213,10 @@ private: int l_ui_input_find_mouse(lua_State *L); }; + struct lua_render_target { + int l_render_view_bounds(lua_State *L); + }; + struct lua_emu_file { lua_emu_file(const char *searchpath, UINT32 openflags) : path(searchpath), diff --git a/src/mame/drivers/comquest.cpp b/src/mame/drivers/comquest.cpp index e03a04c456e..fc018fab425 100644 --- a/src/mame/drivers/comquest.cpp +++ b/src/mame/drivers/comquest.cpp @@ -61,7 +61,7 @@ WRITE8_MEMBER(comquest_state::comquest_write) static ADDRESS_MAP_START( comquest_mem , AS_PROGRAM, 8, comquest_state ) // { 0x0000, 0x7fff, SMH_BANK(1) }, - AM_RANGE(0x0000, 0x7fff) AM_ROM + AM_RANGE(0x0000, 0xfff) AM_ROM ADDRESS_MAP_END static INPUT_PORTS_START( comquest ) diff --git a/src/mame/drivers/coolpool.cpp b/src/mame/drivers/coolpool.cpp index cfdc7f36027..a4d0209c6aa 100644 --- a/src/mame/drivers/coolpool.cpp +++ b/src/mame/drivers/coolpool.cpp @@ -681,9 +681,6 @@ static ADDRESS_MAP_START( coolpool_dsp_io_map, AS_IO, 16, coolpool_state ) AM_RANGE(0x04, 0x04) AM_READ(dsp_rom_r) AM_RANGE(0x05, 0x05) AM_READ_PORT("IN0") AM_RANGE(0x07, 0x07) AM_READ_PORT("IN1") - AM_RANGE(TMS32025_BIO, TMS32025_BIO) AM_READ(dsp_bio_line_r) - AM_RANGE(TMS32025_HOLD, TMS32025_HOLD) AM_READ(dsp_hold_line_r) -// AM_RANGE(TMS32025_HOLDA, TMS32025_HOLDA) AM_WRITE(dsp_HOLDA_signal_w) ADDRESS_MAP_END @@ -837,6 +834,9 @@ static MACHINE_CONFIG_START( coolpool, coolpool_state ) MCFG_CPU_ADD("dsp", TMS32026,XTAL_40MHz) MCFG_CPU_PROGRAM_MAP(coolpool_dsp_pgm_map) MCFG_CPU_IO_MAP(coolpool_dsp_io_map) + MCFG_TMS32025_BIO_IN_CB(READ16(coolpool_state, dsp_bio_line_r)) + MCFG_TMS32025_HOLD_IN_CB(READ16(coolpool_state, dsp_hold_line_r)) +// MCFG_TMS32025_HOLD_ACK_OUT_CB(WRITE16(coolpool_state, dsp_HOLDA_signal_w)) MCFG_MACHINE_RESET_OVERRIDE(coolpool_state,coolpool) MCFG_NVRAM_ADD_0FILL("nvram") diff --git a/src/mame/drivers/cxhumax.cpp b/src/mame/drivers/cxhumax.cpp index 936d33b62db..18cb23c4f3e 100644 --- a/src/mame/drivers/cxhumax.cpp +++ b/src/mame/drivers/cxhumax.cpp @@ -1077,7 +1077,7 @@ ROM_START( hxhdci2k ) ROM_SYSTEM_BIOS( 0, "FW10005", "HDCI REV 1.0 RHDXSCI 1.00.05" ) /* 19 AUG 2008 */ ROM_LOAD16_WORD_SWAP( "28f320j3d.bin", 0x000000, 0x400000, BAD_DUMP CRC(63d98942) SHA1(c5b8d701677a3edc25f203854f44953b19c9158d) ) - ROM_REGION16_BE( 0x2000, "eeprom", 0 ) + ROM_REGION( 0x2000, "eeprom", 0 ) ROM_LOAD( "24lc64.bin", 0x0000, 0x2000, NO_DUMP) ROM_END diff --git a/src/mame/drivers/ddragon.cpp b/src/mame/drivers/ddragon.cpp index 57b827c85dd..7fcb26fb459 100644 --- a/src/mame/drivers/ddragon.cpp +++ b/src/mame/drivers/ddragon.cpp @@ -569,7 +569,7 @@ ADDRESS_MAP_END static ADDRESS_MAP_START( ddragonba_sub_portmap, AS_IO, 8, ddragon_state ) - AM_RANGE(0x0000, 0xffff) AM_WRITE(ddragonba_port_w) + AM_RANGE(0x0000, 0x01ff) AM_WRITE(ddragonba_port_w) ADDRESS_MAP_END diff --git a/src/mame/drivers/esd16.cpp b/src/mame/drivers/esd16.cpp index 10ded704940..3b366429bc9 100644 --- a/src/mame/drivers/esd16.cpp +++ b/src/mame/drivers/esd16.cpp @@ -1088,7 +1088,7 @@ ROM_START( hedpanic ) /* Story line & game instructions in English */ ROM_REGION( 0x40000, "oki", 0 ) /* Samples */ ROM_LOAD( "esd4.su10", 0x000000, 0x020000, CRC(3c11c590) SHA1(cb33845c3dc0501fff8055c2d66f412881089df1) ) /* AT27010 mask rom */ - ROM_REGION( 0x80, "eeprom", 0 ) + ROM_REGION16_BE( 0x80, "eeprom", 0 ) ROM_LOAD( "hedpanic.nv", 0x0000, 0x0080, CRC(e91f4038) SHA1(f492de71170900f87912a272ab4f4a3a37ba31fe) ) ROM_END @@ -1115,7 +1115,7 @@ ROM_START( hedpanicf ) /* Story line in Japanese, game instructions in English * ROM_REGION( 0x40000, "oki", 0 ) /* Samples */ ROM_LOAD( "esd4.su10", 0x000000, 0x020000, CRC(3c11c590) SHA1(cb33845c3dc0501fff8055c2d66f412881089df1) ) /* AT27010 mask rom */ - ROM_REGION( 0x80, "eeprom", 0 ) + ROM_REGION16_BE( 0x80, "eeprom", 0 ) ROM_LOAD( "hedpanic.nv", 0x0000, 0x0080, CRC(e91f4038) SHA1(f492de71170900f87912a272ab4f4a3a37ba31fe) ) ROM_END @@ -1142,7 +1142,7 @@ ROM_START( hedpanico ) /* Story line & game instructions in English, copyright y ROM_REGION( 0x40000, "oki", 0 ) /* Samples */ ROM_LOAD( "esd4.rom", 0x000000, 0x020000, CRC(d7ca6806) SHA1(8ad668bfb5b7561cc0f3e36dfc3c936b136a4274) ) /* SU10 */ - ROM_REGION( 0x80, "eeprom", 0 ) + ROM_REGION16_BE( 0x80, "eeprom", 0 ) ROM_LOAD( "hedpanic.nv", 0x0000, 0x0080, CRC(e91f4038) SHA1(f492de71170900f87912a272ab4f4a3a37ba31fe) ) ROM_END diff --git a/src/mame/drivers/fireball.cpp b/src/mame/drivers/fireball.cpp index eb73ab3ad37..51c03c08b6c 100644 --- a/src/mame/drivers/fireball.cpp +++ b/src/mame/drivers/fireball.cpp @@ -516,7 +516,7 @@ ROM_START(fireball) ROM_REGION(0x10000, "maincpu", 0) ROM_LOAD("euroball-89-07-13-c026.bin", 0x0000, 0x2000, CRC(cab3fc1c) SHA1(bcf0d17e26f2d9f5e20bda258728c989ea138702)) - ROM_REGION( 0x20, "eeprom", 0 ) // default eeprom must have some specific value at 0x03 at least + ROM_REGION16_BE( 0x20, "eeprom", 0 ) // default eeprom must have some specific value at 0x03 at least ROM_LOAD( "fireball.nv", 0x0000, 0x020, CRC(1d0f5f0f) SHA1(8e68fcd8782f39ed3b1df6162db9be83cb3335e4) ) //default setting ROM_END diff --git a/src/mame/drivers/fortecar.cpp b/src/mame/drivers/fortecar.cpp index 5ae79558571..3597caa1ad9 100644 --- a/src/mame/drivers/fortecar.cpp +++ b/src/mame/drivers/fortecar.cpp @@ -702,7 +702,7 @@ ROM_START( fortecar ) ROM_REGION( 0x0800, "nvram", 0 ) /* default NVRAM */ ROM_LOAD( "fortecrd_nvram.u6", 0x0000, 0x0800, BAD_DUMP CRC(7d3e7eb5) SHA1(788fe7adc381bcc6eaefed33f5aa1081340608a0) ) - ROM_REGION( 0x0100, "eeprom", 0 ) /* default serial EEPROM */ + ROM_REGION16_BE( 0x0100, "eeprom", 0 ) /* default serial EEPROM */ ROM_LOAD16_WORD_SWAP( "forte_card_93cs56_serial_12345678.u13", 0x0000, 0x0100, BAD_DUMP CRC(2fc5961d) SHA1(f958c8b2b4e48cc6e5a607a6751acde5592bd27f) ) ROM_REGION( 0x200, "proms", 0 ) @@ -721,7 +721,7 @@ ROM_START( fortecrd ) ROM_REGION( 0x0800, "nvram", 0 ) /* default NVRAM */ ROM_LOAD( "fortecrd_nvram.u6", 0x0000, 0x0800, CRC(7d3e7eb5) SHA1(788fe7adc381bcc6eaefed33f5aa1081340608a0) ) - ROM_REGION( 0x0100, "eeprom", 0 ) /* default serial EEPROM */ + ROM_REGION16_BE( 0x0100, "eeprom", 0 ) /* default serial EEPROM */ ROM_LOAD16_WORD_SWAP( "forte_card_93cs56_serial_12345678.u13", 0x0000, 0x0100, CRC(2fc5961d) SHA1(f958c8b2b4e48cc6e5a607a6751acde5592bd27f) ) ROM_REGION( 0x0200, "proms", 0 ) diff --git a/src/mame/drivers/hornet.cpp b/src/mame/drivers/hornet.cpp index 2753b3fa849..3a15506a5a4 100644 --- a/src/mame/drivers/hornet.cpp +++ b/src/mame/drivers/hornet.cpp @@ -1447,7 +1447,7 @@ ROM_START(sscope2) ROM_REGION(0x8, "lan_serial_id", 0) /* LAN Board DS2401 */ ROM_LOAD( "ds2401.8b", 0x000000, 0x000008, BAD_DUMP CRC(bae36d0b) SHA1(4dd5915888d5718356b40bbe897f2470e410176a) ) // hand built - ROM_REGION(0x80, "lan_eeprom", 0) /* LAN Board AT93C46 */ + ROM_REGION16_BE(0x80, "lan_eeprom", 0) /* LAN Board AT93C46 */ ROM_LOAD( "at93c46.16g", 0x000000, 0x000080, BAD_DUMP CRC(cc63c213) SHA1(fb20e56fb73a887dc7b6db49efd1f8a18b959152) ) // hand built ROM_END diff --git a/src/mame/drivers/ibm3153.cpp b/src/mame/drivers/ibm3153.cpp index b98556bd3b2..df8befae1dd 100644 --- a/src/mame/drivers/ibm3153.cpp +++ b/src/mame/drivers/ibm3153.cpp @@ -59,7 +59,7 @@ private: static ADDRESS_MAP_START(ibm3153_mem, AS_PROGRAM, 8, ibm3153_state) ADDRESS_MAP_UNMAP_HIGH - AM_RANGE(0x00000,0x3ffff) AM_ROM AM_REGION("user1", 0) + AM_RANGE(0x00000,0x0ffff) AM_ROM AM_REGION("user1", 0) ADDRESS_MAP_END static ADDRESS_MAP_START(ibm3153_io, AS_IO, 8, ibm3153_state) diff --git a/src/mame/drivers/indigo.cpp b/src/mame/drivers/indigo.cpp index c901247032d..5fe06760c67 100644 --- a/src/mame/drivers/indigo.cpp +++ b/src/mame/drivers/indigo.cpp @@ -468,31 +468,17 @@ static ADDRESS_MAP_START( indigo_map, AS_PROGRAM, 32, indigo_state ) AM_RANGE( 0x18000000, 0x187fffff ) AM_RAM AM_SHARE("share1") AM_RANGE( 0x1fb80000, 0x1fb8ffff ) AM_READWRITE(hpc_r, hpc_w ) AM_RANGE( 0x1fbd9000, 0x1fbd903f ) AM_READWRITE(int_r, int_w ) - AM_RANGE( 0x80000000, 0x801fffff ) AM_RAM AM_SHARE("share10") - AM_RANGE( 0x88000000, 0x88ffffff ) AM_RAM AM_SHARE("share5") - AM_RANGE( 0xa0000000, 0xa01fffff ) AM_RAM AM_SHARE("share10") - AM_RANGE( 0xa8000000, 0xa8ffffff ) AM_RAM AM_SHARE("share5") - AM_RANGE( 0xa9000000, 0xa97fffff ) AM_RAM AM_SHARE("share6") - AM_RANGE( 0xaa000000, 0xaa7fffff ) AM_RAM AM_SHARE("share7") - AM_RANGE( 0xac000000, 0xac7fffff ) AM_RAM AM_SHARE("share8") - AM_RANGE( 0xb0000000, 0xb07fffff ) AM_RAM AM_SHARE("share9") - AM_RANGE( 0xb8000000, 0xb87fffff ) AM_RAM AM_SHARE("share1") - AM_RANGE( 0xbfb80000, 0xbfb8ffff ) AM_READWRITE(hpc_r, hpc_w ) - AM_RANGE( 0xbfbd9000, 0xbfbd903f ) AM_READWRITE(int_r, int_w ) ADDRESS_MAP_END static ADDRESS_MAP_START( indigo3k_map, AS_PROGRAM, 32, indigo_state ) AM_IMPORT_FROM( indigo_map ) AM_RANGE( 0x1fc00000, 0x1fc3ffff ) AM_ROM AM_SHARE("share2") AM_REGION( "user1", 0 ) - AM_RANGE( 0xbfc00000, 0xbfc3ffff ) AM_ROM AM_SHARE("share2") /* BIOS Mirror */ ADDRESS_MAP_END static ADDRESS_MAP_START( indigo4k_map, AS_PROGRAM, 32, indigo_state ) AM_IMPORT_FROM( indigo_map ) AM_RANGE( 0x1fa00000, 0x1fa1ffff ) AM_DEVREADWRITE("sgi_mc", sgi_mc_device, read, write ) AM_RANGE( 0x1fc00000, 0x1fc7ffff ) AM_ROM AM_SHARE("share2") AM_REGION( "user1", 0 ) - AM_RANGE( 0xbfa00000, 0xbfa1ffff ) AM_DEVREADWRITE("sgi_mc", sgi_mc_device, read, write ) - AM_RANGE( 0xbfc00000, 0xbfc7ffff ) AM_ROM AM_SHARE("share2") /* BIOS Mirror */ ADDRESS_MAP_END WRITE_LINE_MEMBER(indigo_state::scsi_irq) diff --git a/src/mame/drivers/jclub2.cpp b/src/mame/drivers/jclub2.cpp index fe83f2ad7a5..169cab5c1c8 100644 --- a/src/mame/drivers/jclub2.cpp +++ b/src/mame/drivers/jclub2.cpp @@ -1262,7 +1262,7 @@ ROM_START( jclub2o ) ROM_REGION( 0x80000, "maincpu", 0 ) // z80 core (used for sound?) ROM_LOAD( "sx006-04.u87", 0x00000, 0x80000, CRC(a87adedd) SHA1(1cd5af2d03738fff2230b46241659179467c828c) ) - ROM_REGION( 0x100, "eeprom", 0 ) // eeprom 16 bit one!!! + ROM_REGION16_BE( 0x100, "eeprom", 0 ) // eeprom 16 bit one!!! ROM_LOAD( "eeprom-jclub2o.bin", 0x0000, 0x100, CRC(dd1c88ec) SHA1(acb67e41e832f203361e0f93afcd4eaf963fd13e) ) //jclub2ob ones ROM_END @@ -1283,7 +1283,7 @@ ROM_START( jclub2ob ) ROM_REGION( 0x80000, "maincpu", 0 ) // z80 core (used for sound?) ROM_LOAD( "sx006-04.u87", 0x00000, 0x80000, CRC(a87adedd) SHA1(1cd5af2d03738fff2230b46241659179467c828c) ) - ROM_REGION( 0x100, "eeprom", 0 ) // eeprom 16 bit one!!! + ROM_REGION16_BE( 0x100, "eeprom", 0 ) // eeprom 16 bit one!!! ROM_LOAD( "eeprom-jclub2o.bin", 0x0000, 0x100, CRC(dd1c88ec) SHA1(acb67e41e832f203361e0f93afcd4eaf963fd13e) ) ROM_END diff --git a/src/mame/drivers/jubilee.cpp b/src/mame/drivers/jubilee.cpp index 3634918336a..222a43a02e2 100644 --- a/src/mame/drivers/jubilee.cpp +++ b/src/mame/drivers/jubilee.cpp @@ -566,7 +566,7 @@ READ8_MEMBER(jubilee_state::mux_port_r) static ADDRESS_MAP_START( jubileep_cru_map, AS_IO, 8, jubilee_state ) AM_RANGE(0x00c8, 0x00c8) AM_READ(mux_port_r) /* multiplexed input port */ - AM_RANGE(0x0000, 0x0fff) AM_WRITE(unk_w) + AM_RANGE(0x0000, 0x07ff) AM_WRITE(unk_w) ADDRESS_MAP_END /* I/O byte R/W diff --git a/src/mame/drivers/konamigx.cpp b/src/mame/drivers/konamigx.cpp index c3d73611293..5138f3a9f62 100644 --- a/src/mame/drivers/konamigx.cpp +++ b/src/mame/drivers/konamigx.cpp @@ -2002,7 +2002,7 @@ ROM_START( gokuparo ) ROM_LOAD( "321b17.9g", 0x000000, 2*1024*1024, CRC(b3e8d5d8) SHA1(6644a414e7f0e69ded9aa1bf892566002cebae26) ) ROM_LOAD( "321b18.7g", 0x200000, 2*1024*1024, CRC(2c561ad0) SHA1(6265054072ba1c2837dd96e0259b20bc50457160) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "gokuparo.nv", 0x0000, 0x080, CRC(15c0f2d9) SHA1(57c7462e3b1e15652ec5d682a1be3786926ddecd) ) ROM_END @@ -2035,7 +2035,7 @@ ROM_START( fantjour ) ROM_LOAD( "321b17.9g", 0x000000, 2*1024*1024, CRC(b3e8d5d8) SHA1(6644a414e7f0e69ded9aa1bf892566002cebae26) ) ROM_LOAD( "321b18.7g", 0x200000, 2*1024*1024, CRC(2c561ad0) SHA1(6265054072ba1c2837dd96e0259b20bc50457160) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "fantjour.nv", 0x0000, 0x080, CRC(35b7d8e1) SHA1(5f0e3799ff9c63af3e55b040cc52b2a9e7a76168) ) ROM_END @@ -2068,7 +2068,7 @@ ROM_START( fantjoura ) ROM_LOAD( "321b17.9g", 0x000000, 2*1024*1024, CRC(b3e8d5d8) SHA1(6644a414e7f0e69ded9aa1bf892566002cebae26) ) ROM_LOAD( "321b18.7g", 0x200000, 2*1024*1024, CRC(2c561ad0) SHA1(6265054072ba1c2837dd96e0259b20bc50457160) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "fantjoura.nv", 0x0000, 0x080, CRC(d13b1ec1) SHA1(0f4aedd0aa9682b0b68b9f7745946a3bc1e76714) ) ROM_END @@ -2102,7 +2102,7 @@ ROM_START( salmndr2 ) ROM_LOAD( "521-a12.9g", 0x000000, 2*1024*1024, CRC(66614d3b) SHA1(e1e5ebe546bced6ab74b0af500acf0f3308902a4) ) ROM_LOAD( "521-a13.7g", 0x200000, 1*1024*1024, CRC(c3322475) SHA1(1774524ff031e0c4a7f3432810e968d37f9c6331) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "salmndr2.nv", 0x0000, 0x080, CRC(60cdea03) SHA1(6aa597d391b5d7db67e599ec54d98600983966fc) ) ROM_END @@ -2136,7 +2136,7 @@ ROM_START( salmndr2a ) ROM_LOAD( "521-a12.9g", 0x000000, 2*1024*1024, CRC(66614d3b) SHA1(e1e5ebe546bced6ab74b0af500acf0f3308902a4) ) ROM_LOAD( "521-a13.7g", 0x200000, 1*1024*1024, CRC(c3322475) SHA1(1774524ff031e0c4a7f3432810e968d37f9c6331) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "salmndr2a.nv", 0x0000, 0x080, CRC(3a98a8f9) SHA1(08c2d164620a4d8ad902d502acea8ad621931198) ) ROM_END @@ -2169,7 +2169,7 @@ ROM_START( tbyahhoo ) ROM_LOAD( "424a17.9g", 0x000000, 2*1024*1024, CRC(e9dd9692) SHA1(c289019c8d1dd71b3cec26479c39b649de804707) ) ROM_LOAD( "424a18.7g", 0x200000, 2*1024*1024, CRC(0f0d9f3a) SHA1(57f6b113b80f06964b7e672ad517c1654c5569c5) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "tbyahhoo.nv", 0x0000, 0x080, CRC(1e6fa2f8) SHA1(fceb6617a4e02babfc1678bae9f6a131c1d759f5) ) ROM_END @@ -2434,7 +2434,7 @@ ROM_START( tokkae ) ROM_LOAD( "615a22.9g", 0x000000, 2*1024*1024, CRC(ea7e47dd) SHA1(5bf5bad9427b083757c400eaf58c63a6267c1caf) ) ROM_LOAD( "615a23.7g", 0x200000, 2*1024*1024, CRC(22d71f36) SHA1(3f24bb4cd8e1d693b42219e05960ad0c756b08cb) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "tokkae.nv", 0x0000, 0x080, CRC(5a6f8da6) SHA1(f68c67c98e99669904e23d5eac7e13a9c57bc394) ) ROM_END @@ -2469,7 +2469,7 @@ ROM_START( tkmmpzdm ) ROM_LOAD( "515a13.9g", 0x000000, 2*1024*1024, CRC(4b066b00) SHA1(874dd49847b10e6d9c39decb81557534baa36d79) ) ROM_LOAD( "515a14.7g", 0x200000, 2*1024*1024, CRC(128cc944) SHA1(b0cd2ec1b9a2ac936d57b6d6c2a70f9c13dc97a5) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "tkmmpzdm.nv", 0x0000, 0x080, CRC(850ab8c4) SHA1(fea5ceb3f2cea61fb19bdb1b8f1496d1c06bfff1) ) ROM_END @@ -2592,7 +2592,7 @@ ROM_START( crzcross ) ROM_LOAD( "315a17.9g", 0x000000, 2*1024*1024, CRC(ea763d61) SHA1(2a7dcb2a2a23c9fea62fb82ffc18949bf15b9f6f) ) ROM_LOAD( "315a18.7g", 0x200000, 2*1024*1024, CRC(6e416cee) SHA1(145a766ad2fa2b692692053dd36e0caf51d67a56) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting upside down with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting upside down with error ROM_LOAD( "crzcross.nv", 0x0000, 0x080, CRC(446f178c) SHA1(84b02192c26459c1b798f07b96768e1013b57666) ) ROM_END @@ -2625,7 +2625,7 @@ ROM_START( puzldama ) ROM_LOAD( "315a17.9g", 0x000000, 2*1024*1024, CRC(ea763d61) SHA1(2a7dcb2a2a23c9fea62fb82ffc18949bf15b9f6f) ) ROM_LOAD( "315a18.7g", 0x200000, 2*1024*1024, CRC(6e416cee) SHA1(145a766ad2fa2b692692053dd36e0caf51d67a56) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting upside down with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting upside down with error ROM_LOAD( "puzldama.nv", 0x0000, 0x080, CRC(bda98b84) SHA1(f4b03130bdc2a5bc6f0fc9ca21603109d82703b4) ) ROM_END @@ -2665,7 +2665,7 @@ ROM_START( dragoonj ) ROM_REGION( 0x200000, "shared", 0 ) ROM_LOAD( "417a17.9g", 0x000000, 2*1024*1024, CRC(88d47dfd) SHA1(b5d6dd7ee9ac0c427dc3e714a97945c954260913) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "dragoonj.nv", 0x0000, 0x080, CRC(cbe16082) SHA1(da48893f3584ae2e034c73d4338b220107a884da) ) ROM_END @@ -2705,7 +2705,7 @@ ROM_START( dragoona ) ROM_REGION( 0x200000, "shared", 0 ) ROM_LOAD( "417a17.9g", 0x000000, 2*1024*1024, CRC(88d47dfd) SHA1(b5d6dd7ee9ac0c427dc3e714a97945c954260913) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "dragoona.nv", 0x0000, 0x080, CRC(7980ad2b) SHA1(dccaab02d23edbd81ae13441fbac0dbd7112c258) ) ROM_END @@ -2764,7 +2764,7 @@ ROM_START( soccerss ) ROM_REGION( 0x400000, "shared", 0 ) ROM_LOAD( "427a16.9r", 0x000000, 2*1024*1024, CRC(39547265) SHA1(c0efd68c0c1ea59141045150842f36d43e1f01d8) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "soccerss.nv", 0x0000, 0x080, CRC(f222dae4) SHA1(fede48a4e1fe91cf2b17ff3f3996bca4816fc283) ) ROM_END @@ -2823,7 +2823,7 @@ ROM_START( soccerssu ) ROM_REGION( 0x400000, "shared", 0 ) ROM_LOAD( "427a16.9r", 0x000000, 2*1024*1024, CRC(39547265) SHA1(c0efd68c0c1ea59141045150842f36d43e1f01d8) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "soccerssu.nv", 0x0000, 0x080, CRC(812f6878) SHA1(fc4975211720a7eb413bceda8109231cb1c00834) ) ROM_END @@ -2870,7 +2870,7 @@ ROM_START( soccerssj ) ROM_REGION( 0x400000, "shared", 0 ) ROM_LOAD( "427a16.9r", 0x000000, 2*1024*1024, CRC(39547265) SHA1(c0efd68c0c1ea59141045150842f36d43e1f01d8) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "soccerssj.nv", 0x0000, 0x080, CRC(7440255e) SHA1(af379b5b1f765f9050f18fbd41c5031c5ad4918b) ) ROM_END @@ -2917,7 +2917,7 @@ ROM_START( soccerssja ) ROM_REGION( 0x400000, "shared", 0 ) ROM_LOAD( "427a16.9r", 0x000000, 2*1024*1024, CRC(39547265) SHA1(c0efd68c0c1ea59141045150842f36d43e1f01d8) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "soccerssja.nv", 0x0000, 0x080, CRC(60dba700) SHA1(087b086b29748727b41fdd4c154ff9b4bef42959) ) ROM_END @@ -2964,7 +2964,7 @@ ROM_START( soccerssa ) ROM_REGION( 0x400000, "shared", 0 ) ROM_LOAD( "427a16.9r", 0x000000, 2*1024*1024, CRC(39547265) SHA1(c0efd68c0c1ea59141045150842f36d43e1f01d8) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "soccerssa.nv", 0x0000, 0x080, CRC(e3a3f3d5) SHA1(374cf5bbcc459c56ebbba5068406f6d767bcb608) ) ROM_END @@ -3320,7 +3320,7 @@ ROM_START( le2 ) ROM_LOAD( "312a17.9g", 0x000000, 2*1024*1024, CRC(ed101448) SHA1(ef1342f37fbbb092eddee0c237b40989ad42cf26) ) ROM_LOAD( "312a18.7g", 0x200000, 1*1024*1024, CRC(5717abd7) SHA1(d304d733e7fca0363ea6b3872c2d3bbe4edf1179) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting upside down with invisible error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting upside down with invisible error ROM_LOAD( "le2.nv", 0x0000, 0x080, CRC(fec3bc2e) SHA1(64040364d7db12f54e5c11f28a28e030bcf9a0f7) ) ROM_END @@ -3358,7 +3358,7 @@ ROM_START( le2u ) ROM_LOAD( "312a17.9g", 0x000000, 2*1024*1024, CRC(ed101448) SHA1(ef1342f37fbbb092eddee0c237b40989ad42cf26) ) ROM_LOAD( "312a18.7g", 0x200000, 1*1024*1024, CRC(5717abd7) SHA1(d304d733e7fca0363ea6b3872c2d3bbe4edf1179) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting upside down with invisible error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting upside down with invisible error ROM_LOAD( "le2u.nv", 0x0000, 0x080, CRC(d46b3878) SHA1(81bf4331547ce977eaa185f7281625fb695f6deb) ) ROM_END @@ -3397,7 +3397,7 @@ ROM_START( le2j ) ROM_LOAD( "312a17.9g", 0x000000, 2*1024*1024, CRC(ed101448) SHA1(ef1342f37fbbb092eddee0c237b40989ad42cf26) ) ROM_LOAD( "312a18.7g", 0x200000, 1*1024*1024, CRC(5717abd7) SHA1(d304d733e7fca0363ea6b3872c2d3bbe4edf1179) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting upside down with invisible error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting upside down with invisible error ROM_LOAD( "le2j.nv", 0x0000, 0x080, CRC(f6790425) SHA1(f233f3c09c4cdbd1c6e5204fc6554a4826b44c59) ) ROM_END @@ -3448,7 +3448,7 @@ ROM_START( racinfrc ) ROM_LOAD( "250a18.12y", 0x200000, 2*1024*1024, CRC(8014a2eb) SHA1(d82f0a7d559340ae05a78ecc8bb69bb35b9c0658) ) // note, it seems impossible to calibrate the controls (again!), this has nothing to do with the default eeprom! - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "racinfrc.nv", 0x0000, 0x080, CRC(dc88c693) SHA1(a7967f390db043570803c79edf984a3e6bdbd172) ) ROM_END @@ -3500,7 +3500,7 @@ ROM_START( racinfrcu ) ROM_LOAD( "250a18.12y", 0x200000, 2*1024*1024, CRC(8014a2eb) SHA1(d82f0a7d559340ae05a78ecc8bb69bb35b9c0658) ) // note, it seems impossible to calibrate the controls (again!), this has nothing to do with the default eeprom! - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "racinfrcu.nv", 0x0000, 0x080, CRC(369e1a84) SHA1(bfed0145d89550b1a1661f3ccc612505053063f8) ) ROM_END @@ -3586,7 +3586,7 @@ ROM_START( opengolf ) ROM_LOAD( "218a17.14y", 0x000000, 2*1024*1024, CRC(0b525127) SHA1(218b306c12e1094a676815b7dddaf13bf19be2d5) ) ROM_LOAD( "218a18.12y", 0x200000, 1*1024*1024, CRC(98ec4cfb) SHA1(638753f9d9269719a37133b9c39c242507fdd8ac) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "opengolf.nv", 0x0000, 0x080, CRC(d49bf7c3) SHA1(294c772a2f562c01e7c4d15068ba4e80e9522f9f) ) ROM_END @@ -3641,7 +3641,7 @@ ROM_START( opengolf2 ) ROM_LOAD( "218a17.14y", 0x000000, 2*1024*1024, CRC(0b525127) SHA1(218b306c12e1094a676815b7dddaf13bf19be2d5) ) ROM_LOAD( "218a18.12y", 0x200000, 1*1024*1024, CRC(98ec4cfb) SHA1(638753f9d9269719a37133b9c39c242507fdd8ac) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "opengolf2.nv", 0x0000, 0x080, CRC(c09fc0e6) SHA1(32807752344763613440bee46da24d605e62eace) ) ROM_END @@ -3695,7 +3695,7 @@ ROM_START( ggreats2 ) ROM_LOAD( "218a17.14y", 0x000000, 2*1024*1024, CRC(0b525127) SHA1(218b306c12e1094a676815b7dddaf13bf19be2d5) ) ROM_LOAD( "218a18.12y", 0x200000, 1*1024*1024, CRC(98ec4cfb) SHA1(638753f9d9269719a37133b9c39c242507fdd8ac) ) - ROM_REGION( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error + ROM_REGION16_BE( 0x80, "eeprom", 0 ) // default eeprom to prevent game booting with error ROM_LOAD( "ggreats2.nv", 0x0000, 0x080, CRC(4db10b5c) SHA1(29e3a59e4101349ace33d49b5fe59f0c785979b3) ) ROM_END diff --git a/src/mame/drivers/konendev.cpp b/src/mame/drivers/konendev.cpp index 9e8f542eb65..801789a7df5 100644 --- a/src/mame/drivers/konendev.cpp +++ b/src/mame/drivers/konendev.cpp @@ -341,7 +341,7 @@ ROM_START( enchlamp ) ROM_REGION32_BE( 0x1800000, "flash", ROMREGION_ERASE00 ) ROM_LOAD( "enl5r211.fmu.bin", 0x0000, 0x1800000, CRC(592c3c7f) SHA1(119b3c6223d656981c399c399d7edccfdbb50dc7) ) - ROM_REGION32_BE( 0x100, "eeprom", 0 ) + ROM_REGION16_BE( 0x100, "eeprom", 0 ) ROM_LOAD( "93c56.u98", 0x00, 0x100, CRC(b2521a6a) SHA1(f44711545bee7e9c772a3dc23b79f0ea8059ec50) ) // empty eeprom with Konami header ROM_END @@ -471,7 +471,7 @@ ROM_START( konzero ) ROM_REGION32_BE( 0x1800000, "flash", ROMREGION_ERASE00 ) - ROM_REGION32_BE( 0x100, "eeprom", 0 ) + ROM_REGION16_BE( 0x100, "eeprom", 0 ) ROM_LOAD( "93c56.u98", 0x00, 0x100, CRC(b2521a6a) SHA1(f44711545bee7e9c772a3dc23b79f0ea8059ec50) ) // empty eeprom with Konami header ROM_END diff --git a/src/mame/drivers/mlanding.cpp b/src/mame/drivers/mlanding.cpp index a4cb4078ec7..07d37c9cff9 100644 --- a/src/mame/drivers/mlanding.cpp +++ b/src/mame/drivers/mlanding.cpp @@ -780,13 +780,6 @@ static ADDRESS_MAP_START( dsp_map_data, AS_DATA, 16, mlanding_state ) AM_RANGE(0x0000, 0x1fff) AM_RAM AM_SHARE("dot_ram") ADDRESS_MAP_END -static ADDRESS_MAP_START( dsp_map_io, AS_IO, 16, mlanding_state ) - AM_RANGE(TMS32025_HOLD, TMS32025_HOLD) AM_READ(dsp_hold_signal_r) - AM_RANGE(TMS32025_HOLDA, TMS32025_HOLDA) AM_WRITENOP -ADDRESS_MAP_END - - - /************************************* * * Audio CPU memory handlers @@ -945,7 +938,8 @@ static MACHINE_CONFIG_START( mlanding, mlanding_state ) MCFG_CPU_ADD("dsp", TMS32025, 32000000) // ? MCFG_CPU_PROGRAM_MAP(dsp_map_prog) MCFG_CPU_DATA_MAP(dsp_map_data) - MCFG_CPU_IO_MAP(dsp_map_io) + MCFG_TMS32025_HOLD_IN_CB(READ16(mlanding_state, dsp_hold_signal_r)) + MCFG_TMS32025_HOLD_ACK_OUT_CB(NOOP) MCFG_DEVICE_ADD("ctc", Z80CTC, 4000000) MCFG_Z80CTC_ZC0_CB(WRITELINE(mlanding_state, z80ctc_to0)) diff --git a/src/mame/drivers/namcos21.cpp b/src/mame/drivers/namcos21.cpp index e8b629340da..a6ccb0f8875 100644 --- a/src/mame/drivers/namcos21.cpp +++ b/src/mame/drivers/namcos21.cpp @@ -993,9 +993,6 @@ static ADDRESS_MAP_START( master_dsp_io, AS_IO, 16, namcos21_state ) AM_RANGE(0x0b,0x0b) AM_READWRITE(dsp_portb_r,dsp_portb_w) AM_RANGE(0x0c,0x0c) AM_WRITE(dsp_portc_w) AM_RANGE(0x0f,0x0f) AM_READ(dsp_portf_r) - AM_RANGE(TMS32025_HOLD, TMS32025_HOLD) AM_READNOP - AM_RANGE(TMS32025_HOLDA, TMS32025_HOLDA) AM_WRITENOP - AM_RANGE(TMS32025_XF, TMS32025_XF) AM_WRITE(dsp_xf_w ) ADDRESS_MAP_END /************************************************************************************/ @@ -1111,9 +1108,6 @@ static ADDRESS_MAP_START( slave_dsp_io, AS_IO, 16, namcos21_state ) AM_RANGE(0x02,0x02) AM_READ(slave_port2_r) AM_RANGE(0x03,0x03) AM_READWRITE(slave_port3_r,slave_port3_w) AM_RANGE(0x0f,0x0f) AM_READ(slave_portf_r) - AM_RANGE(TMS32025_HOLD, TMS32025_HOLD) AM_READNOP - AM_RANGE(TMS32025_HOLDA, TMS32025_HOLDA) AM_WRITENOP - AM_RANGE(TMS32025_XF, TMS32025_XF) AM_WRITE(slave_XF_output_w) ADDRESS_MAP_END /************************************************************************************/ @@ -1424,21 +1418,8 @@ static ADDRESS_MAP_START( winrun_dsp_io, AS_IO, 16, namcos21_state ) AM_RANGE(0x0a,0x0a) AM_WRITE(winrun_dsp_render_w) AM_RANGE(0x0b,0x0b) AM_WRITENOP AM_RANGE(0x0c,0x0c) AM_WRITE(winrun_dsp_complete_w) - AM_RANGE(TMS32025_BIO, TMS32025_BIO) AM_READ(winrun_poly_reset_r ) - AM_RANGE(TMS32025_HOLD, TMS32025_HOLD) AM_READNOP - AM_RANGE(TMS32025_HOLDA, TMS32025_HOLDA) AM_WRITENOP - AM_RANGE(TMS32025_XF, TMS32025_XF) AM_WRITENOP ADDRESS_MAP_END -READ16_MEMBER(namcos21_state::winrun_gpucomram_r) -{ - return m_winrun_gpucomram[offset]; -} -WRITE16_MEMBER(namcos21_state::winrun_gpucomram_w) -{ - COMBINE_DATA( &m_winrun_gpucomram[offset] ); -} - WRITE16_MEMBER(namcos21_state::winrun_dspbios_w) { COMBINE_DATA( &m_winrun_dspbios[offset] ); @@ -1491,7 +1472,7 @@ static ADDRESS_MAP_START( am_master_winrun, AS_PROGRAM, 16, namcos21_state ) AM_RANGE(0x3c0000, 0x3c1fff) AM_READWRITE(winrun_68k_dspcomram_r,winrun_68k_dspcomram_w) AM_RANGE(0x400000, 0x400001) AM_WRITE(pointram_control_w) AM_RANGE(0x440000, 0x440001) AM_READWRITE(pointram_data_r,pointram_data_w) - AM_RANGE(0x600000, 0x60ffff) AM_READWRITE(winrun_gpucomram_r,winrun_gpucomram_w) + AM_RANGE(0x600000, 0x60ffff) AM_RAM AM_SHARE("gpu_comram") AM_RANGE(0x800000, 0x87ffff) AM_ROM AM_REGION("data", 0) AM_RANGE(0x900000, 0x90ffff) AM_RAM AM_SHARE("sharedram") AM_RANGE(0xa00000, 0xa00fff) AM_READWRITE(namcos2_68k_dualportram_word_r,namcos2_68k_dualportram_word_w) @@ -1503,7 +1484,7 @@ static ADDRESS_MAP_START( am_slave_winrun, AS_PROGRAM, 16, namcos21_state ) AM_RANGE(0x000000, 0x03ffff) AM_ROM AM_RANGE(0x100000, 0x13ffff) AM_RAM AM_RANGE(0x1c0000, 0x1fffff) AM_READWRITE(namcos2_68k_slave_C148_r,namcos2_68k_slave_C148_w) - AM_RANGE(0x600000, 0x60ffff) AM_READWRITE(winrun_gpucomram_r,winrun_gpucomram_w) + AM_RANGE(0x600000, 0x60ffff) AM_RAM AM_SHARE("gpu_comram") AM_RANGE(0x800000, 0x87ffff) AM_ROM AM_REGION("data", 0) AM_RANGE(0x900000, 0x90ffff) AM_RAM AM_SHARE("sharedram") AM_RANGE(0xa00000, 0xa00fff) AM_READWRITE(namcos2_68k_dualportram_word_r,namcos2_68k_dualportram_word_w) @@ -1516,7 +1497,7 @@ static ADDRESS_MAP_START( am_gpu_winrun, AS_PROGRAM, 16, namcos21_state ) AM_RANGE(0x100000, 0x100001) AM_READWRITE(winrun_gpu_color_r,winrun_gpu_color_w) /* ? */ AM_RANGE(0x180000, 0x19ffff) AM_RAM /* work RAM */ AM_RANGE(0x1c0000, 0x1fffff) AM_READWRITE(namcos21_68k_gpu_C148_r,namcos21_68k_gpu_C148_w) - AM_RANGE(0x200000, 0x20ffff) AM_RAM AM_SHARE("winrun_comram") + AM_RANGE(0x200000, 0x20ffff) AM_RAM AM_SHARE("gpu_comram") AM_RANGE(0x400000, 0x40ffff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette") AM_RANGE(0x410000, 0x41ffff) AM_RAM_DEVWRITE("palette", palette_device, write_ext) AM_SHARE("palette_ext") AM_RANGE(0x600000, 0x6fffff) AM_ROM AM_REGION("gdata", 0) @@ -1667,11 +1648,17 @@ static MACHINE_CONFIG_START( namcos21, namcos21_state ) MCFG_CPU_PROGRAM_MAP(master_dsp_program) MCFG_CPU_DATA_MAP(master_dsp_data) MCFG_CPU_IO_MAP(master_dsp_io) + MCFG_TMS32025_HOLD_IN_CB(NOOP) + MCFG_TMS32025_HOLD_ACK_OUT_CB(NOOP) + MCFG_TMS32025_XF_OUT_CB(WRITE16(namcos21_state, dsp_xf_w)) MCFG_CPU_ADD("dspslave", TMS32025,24000000*4) /* 24 MHz?; overclocked */ MCFG_CPU_PROGRAM_MAP(slave_dsp_program) MCFG_CPU_DATA_MAP(slave_dsp_data) MCFG_CPU_IO_MAP(slave_dsp_io) + MCFG_TMS32025_HOLD_IN_CB(NOOP) + MCFG_TMS32025_HOLD_ACK_OUT_CB(NOOP) + MCFG_TMS32025_XF_OUT_CB(WRITE16(namcos21_state, slave_XF_output_w)) MCFG_QUANTUM_TIME(attotime::from_hz(12000)) @@ -1729,6 +1716,10 @@ static MACHINE_CONFIG_START( driveyes, namcos21_state ) MCFG_CPU_PROGRAM_MAP(winrun_dsp_program) MCFG_CPU_DATA_MAP(winrun_dsp_data) MCFG_CPU_IO_MAP(winrun_dsp_io) + MCFG_TMS32025_BIO_IN_CB(READ16(namcos21_state, winrun_poly_reset_r)) + MCFG_TMS32025_HOLD_IN_CB(NOOP) + MCFG_TMS32025_HOLD_ACK_OUT_CB(NOOP) + MCFG_TMS32025_XF_OUT_CB(NOOP) MCFG_QUANTUM_TIME(attotime::from_hz(6000)) /* 100 CPU slices per frame */ @@ -1786,6 +1777,10 @@ static MACHINE_CONFIG_START( winrun, namcos21_state ) MCFG_CPU_PROGRAM_MAP(winrun_dsp_program) MCFG_CPU_DATA_MAP(winrun_dsp_data) MCFG_CPU_IO_MAP(winrun_dsp_io) + MCFG_TMS32025_BIO_IN_CB(READ16(namcos21_state, winrun_poly_reset_r)) + MCFG_TMS32025_HOLD_IN_CB(NOOP) + MCFG_TMS32025_HOLD_ACK_OUT_CB(NOOP) + MCFG_TMS32025_XF_OUT_CB(NOOP) MCFG_CPU_ADD("gpu", M68000,12288000) /* graphics coprocessor */ MCFG_CPU_PROGRAM_MAP(am_gpu_winrun) diff --git a/src/mame/drivers/namcos22.cpp b/src/mame/drivers/namcos22.cpp index c361e74a74d..e0617229634 100644 --- a/src/mame/drivers/namcos22.cpp +++ b/src/mame/drivers/namcos22.cpp @@ -162,7 +162,7 @@ *the video board as these are known to run hot and commonly fail, especially now the system is many years old. * *CPU PCB - There are four known revisions of this PCB. Three of them have an extra connector for an - * auxillary PCB. One of the others doesn't have that connector but is are otherwise identical. + * auxiliary PCB. One of the others doesn't have that connector but is are otherwise identical. * All PCBs can be swapped to any game and it will work. However, ALL required IC's must be swapped. * This includes Program ROM PCB, socketed Keycus IC, socketed DATA ROM and socketed WAVE ROM(s). * On most games the EEPROM will re-init itself on bootup. On the others, the EEPROM can re-init itself @@ -242,7 +242,7 @@ *Notes: * J6 : Custom Namco connector for plug-in program ROM PCB * J11 : Custom Namco connector for optional plug-in WAVE ROM PCB (holds some SOP44 MASKROMs) - * JC410 : Custom Namco connector for Optional plug-in Auxillary PCB (e.g. Gun Control PCB used in Time Crisis + * JC410 : Custom Namco connector for Optional plug-in Auxiliary PCB (e.g. Gun Control PCB used in Time Crisis * etc) * The connector is populated only on the 2nd revision CPU (B) PCB 8646962600 (8646972600) * and 3rd Revision CPU (B) PCB 8646962600 (8646972601) @@ -963,7 +963,7 @@ * C407 : Namco custom C407 (QFP64) NOTE! On Revision A & B, this position is populated by an * Altera EPM7064 PLCC84 FPGA labelled 'SS22V1B' * The Altera chip runs very hot and fails quite often. - * Even if a heaksink is added to the chip it still fails. + * Even if a heatsink is added to the chip it still fails. * The failure of this chip is the primary cause of * video faults on Namco Super System 22 PCBs. * (Second reason for video faults is generally attributed @@ -2562,11 +2562,6 @@ static ADDRESS_MAP_START( master_dsp_io, AS_IO, 16, namcos22_state ) AM_RANGE(0xd, 0xd) AM_WRITE(namcos22_dspram16_bank_w) AM_RANGE(0xe, 0xe) AM_WRITE(dsp_led_w) AM_RANGE(0xf, 0xf) AM_READ(dsp_upload_status_r) AM_WRITENOP - AM_RANGE(TMS32025_HOLD, TMS32025_HOLD) AM_READ(dsp_hold_signal_r) - AM_RANGE(TMS32025_HOLDA, TMS32025_HOLDA) AM_WRITE(dsp_hold_ack_w) - AM_RANGE(TMS32025_XF, TMS32025_XF) AM_WRITE(dsp_xf_output_w) - AM_RANGE(TMS32025_BIO, TMS32025_BIO) AM_READ(pdp_status_r) - AM_RANGE(TMS32025_DR, TMS32025_DR) AM_READ(master_serial_io_r) ADDRESS_MAP_END @@ -2651,12 +2646,6 @@ static ADDRESS_MAP_START( slave_dsp_io, AS_IO, 16, namcos22_state ) AM_RANGE(0xb, 0xb) AM_READWRITE(dsp_slave_portb_r, dsp_slave_portb_w) AM_RANGE(0xc, 0xc) AM_WRITE(dsp_slave_portc_w) - - AM_RANGE(TMS32025_HOLD, TMS32025_HOLD) AM_READ(dsp_hold_signal_r) - AM_RANGE(TMS32025_HOLDA, TMS32025_HOLDA) AM_WRITE(dsp_hold_ack_w) - AM_RANGE(TMS32025_XF, TMS32025_XF) AM_WRITE(dsp_xf_output_w) - AM_RANGE(TMS32025_BIO, TMS32025_BIO) AM_READ(dsp_bioz_r) - AM_RANGE(TMS32025_DX, TMS32025_DX) AM_WRITE(slave_serial_io_w) ADDRESS_MAP_END @@ -3751,12 +3740,22 @@ static MACHINE_CONFIG_START( namcos22, namcos22_state ) MCFG_CPU_PROGRAM_MAP(master_dsp_program) MCFG_CPU_DATA_MAP(master_dsp_data) MCFG_CPU_IO_MAP(master_dsp_io) + MCFG_TMS32025_BIO_IN_CB(READ16(namcos22_state, pdp_status_r)) + MCFG_TMS32025_HOLD_IN_CB(READ16(namcos22_state, dsp_hold_signal_r)) + MCFG_TMS32025_HOLD_ACK_OUT_CB(WRITE16(namcos22_state, dsp_hold_ack_w)) + MCFG_TMS32025_XF_OUT_CB(WRITE16(namcos22_state, dsp_xf_output_w)) + MCFG_TMS32025_DR_IN_CB(READ16(namcos22_state, master_serial_io_r)) MCFG_TIMER_DRIVER_ADD_SCANLINE("master_st", namcos22_state, dsp_master_serial_irq, "screen", 0, 1) MCFG_CPU_ADD("slave", TMS32025,SS22_MASTER_CLOCK) /* ? */ MCFG_CPU_PROGRAM_MAP(slave_dsp_program) MCFG_CPU_DATA_MAP(slave_dsp_data) MCFG_CPU_IO_MAP(slave_dsp_io) + MCFG_TMS32025_BIO_IN_CB(READ16(namcos22_state, dsp_bioz_r)) + MCFG_TMS32025_HOLD_IN_CB(READ16(namcos22_state, dsp_hold_signal_r)) + MCFG_TMS32025_HOLD_ACK_OUT_CB(WRITE16(namcos22_state, dsp_hold_ack_w)) + MCFG_TMS32025_XF_OUT_CB(WRITE16(namcos22_state, dsp_xf_output_w)) + MCFG_TMS32025_DX_OUT_CB(WRITE16(namcos22_state, slave_serial_io_w)) MCFG_TIMER_DRIVER_ADD_SCANLINE("slave_st", namcos22_state, dsp_slave_serial_irq, "screen", 0, 1) MCFG_CPU_ADD("mcu", NAMCO_C74, SS22_MASTER_CLOCK/3) // C74 on the CPU board has no periodic interrupts, it runs entirely off Timer A0 @@ -3801,12 +3800,22 @@ static MACHINE_CONFIG_START( namcos22s, namcos22_state ) MCFG_CPU_PROGRAM_MAP(master_dsp_program) MCFG_CPU_DATA_MAP(master_dsp_data) MCFG_CPU_IO_MAP(master_dsp_io) + MCFG_TMS32025_BIO_IN_CB(READ16(namcos22_state, pdp_status_r)) + MCFG_TMS32025_HOLD_IN_CB(READ16(namcos22_state, dsp_hold_signal_r)) + MCFG_TMS32025_HOLD_ACK_OUT_CB(WRITE16(namcos22_state, dsp_hold_ack_w)) + MCFG_TMS32025_XF_OUT_CB(WRITE16(namcos22_state, dsp_xf_output_w)) + MCFG_TMS32025_DR_IN_CB(READ16(namcos22_state, master_serial_io_r)) MCFG_TIMER_DRIVER_ADD_SCANLINE("master_st", namcos22_state, dsp_master_serial_irq, "screen", 0, 1) MCFG_CPU_ADD("slave", TMS32025,SS22_MASTER_CLOCK) MCFG_CPU_PROGRAM_MAP(slave_dsp_program) MCFG_CPU_DATA_MAP(slave_dsp_data) MCFG_CPU_IO_MAP(slave_dsp_io) + MCFG_TMS32025_BIO_IN_CB(READ16(namcos22_state, dsp_bioz_r)) + MCFG_TMS32025_HOLD_IN_CB(READ16(namcos22_state, dsp_hold_signal_r)) + MCFG_TMS32025_HOLD_ACK_OUT_CB(WRITE16(namcos22_state, dsp_hold_ack_w)) + MCFG_TMS32025_XF_OUT_CB(WRITE16(namcos22_state, dsp_xf_output_w)) + MCFG_TMS32025_DX_OUT_CB(WRITE16(namcos22_state, slave_serial_io_w)) MCFG_TIMER_DRIVER_ADD_SCANLINE("slave_st", namcos22_state, dsp_slave_serial_irq, "screen", 0, 1) MCFG_CPU_ADD("mcu", M37710S4, SS22_MASTER_CLOCK/3) diff --git a/src/mame/drivers/pandoras.cpp b/src/mame/drivers/pandoras.cpp index 7836ad8662d..aa7f68bb076 100644 --- a/src/mame/drivers/pandoras.cpp +++ b/src/mame/drivers/pandoras.cpp @@ -170,7 +170,7 @@ static ADDRESS_MAP_START( pandoras_sound_map, AS_PROGRAM, 8, pandoras_state ) ADDRESS_MAP_END static ADDRESS_MAP_START( pandoras_i8039_map, AS_PROGRAM, 8, pandoras_state ) - AM_RANGE(0x0000, 0x1fff) AM_ROM + AM_RANGE(0x0000, 0x0fff) AM_ROM ADDRESS_MAP_END static ADDRESS_MAP_START( pandoras_i8039_io_map, AS_IO, 8, pandoras_state ) diff --git a/src/mame/drivers/sealy.cpp b/src/mame/drivers/sealy.cpp index 0dedecb8feb..fbdc2ed03cd 100644 --- a/src/mame/drivers/sealy.cpp +++ b/src/mame/drivers/sealy.cpp @@ -67,7 +67,6 @@ UINT32 sealy_state::screen_update_sealy(screen_device &screen, bitmap_rgb32 &bit static ADDRESS_MAP_START( sealy_map, AS_PROGRAM, 16, sealy_state ) - ADDRESS_MAP_GLOBAL_MASK(0x3ffff) AM_RANGE(0x00000, 0x3ffff) AM_ROM ADDRESS_MAP_END diff --git a/src/mame/drivers/speglsht.cpp b/src/mame/drivers/speglsht.cpp index a91684053bf..2c681d9d34e 100644 --- a/src/mame/drivers/speglsht.cpp +++ b/src/mame/drivers/speglsht.cpp @@ -262,10 +262,9 @@ static ADDRESS_MAP_START( speglsht_mem, AS_PROGRAM, 32, speglsht_state ) AM_RANGE(0x01b00000, 0x01b07fff) AM_RAM //cleared ... video related ? AM_RANGE(0x01c00000, 0x01dfffff) AM_ROM AM_REGION("user2", 0) AM_RANGE(0x0a000000, 0x0a003fff) AM_READWRITE(shared_r, shared_w) + AM_RANGE(0x0fc00000, 0x0fdfffff) AM_ROM AM_MIRROR(0x10000000) AM_REGION("user1", 0) AM_RANGE(0x1eff0000, 0x1eff001f) AM_RAM AM_RANGE(0x1eff003c, 0x1eff003f) AM_READ(irq_ack_clear) - AM_RANGE(0x1fc00000, 0x1fdfffff) AM_ROM AM_REGION("user1", 0) - AM_RANGE(0x2fc00000, 0x2fdfffff) AM_ROM AM_REGION("user1", 0) // mirror for interrupts ADDRESS_MAP_END static INPUT_PORTS_START( speglsht ) diff --git a/src/mame/drivers/srmp5.cpp b/src/mame/drivers/srmp5.cpp index 260f01fbcf2..0f792f7337e 100644 --- a/src/mame/drivers/srmp5.cpp +++ b/src/mame/drivers/srmp5.cpp @@ -377,11 +377,10 @@ static ADDRESS_MAP_START( srmp5_mem, AS_PROGRAM, 32, srmp5_state ) AM_RANGE(0x0a180000, 0x0a180003) AM_READNOP // write 0x00000400 AM_RANGE(0x0a180000, 0x0a18011f) AM_READWRITE(srmp5_vidregs_r, srmp5_vidregs_w) AM_RANGE(0x0a200000, 0x0a3fffff) AM_READWRITE(tileram_r, tileram_w) + AM_RANGE(0x0fc00000, 0x0fdfffff) AM_MIRROR(0x10000000) AM_ROM AM_REGION("sub", 0) AM_RANGE(0x1eff0000, 0x1eff001f) AM_WRITEONLY AM_RANGE(0x1eff003c, 0x1eff003f) AM_READ(irq_ack_clear) - AM_RANGE(0x1fc00000, 0x1fdfffff) AM_ROM AM_REGION("sub", 0) - AM_RANGE(0x2fc00000, 0x2fdfffff) AM_ROM AM_REGION("sub", 0) ADDRESS_MAP_END static ADDRESS_MAP_START( st0016_mem, AS_PROGRAM, 8, srmp5_state ) diff --git a/src/mame/drivers/sumt8035.cpp b/src/mame/drivers/sumt8035.cpp index 9de2d25a847..457c7dbe006 100644 --- a/src/mame/drivers/sumt8035.cpp +++ b/src/mame/drivers/sumt8035.cpp @@ -32,8 +32,7 @@ protected: static ADDRESS_MAP_START( sumt_map, AS_PROGRAM, 8, sumt8035_state ) - AM_RANGE(0x0000, 0x1fff) AM_ROM - AM_RANGE(0x2000, 0x23ff) AM_RAM//poss wrong + AM_RANGE(0x0000, 0x0fff) AM_ROM ADDRESS_MAP_END diff --git a/src/mame/drivers/sun4.cpp b/src/mame/drivers/sun4.cpp index ba95e54f0d8..dd4eb577f74 100644 --- a/src/mame/drivers/sun4.cpp +++ b/src/mame/drivers/sun4.cpp @@ -382,20 +382,13 @@ 21/11/2011 Skeleton driver. 20/06/2016 Much less skeletony. - 4/60 memory test notes: + 4/60 ROM notes: ffe809fc: call to print "Sizing Memory" to the UART - ffe80a04: set o0 to 0xf0000000, a valid PTE that points to absolute zero in main RAM - ffe80a08: call to set that PTE in the page table (routine also reads back the written value and verifies that the unused bits are all 0) - ffe80a0c: stash g0, the current memory base testing, to o2, which the CALL above uses as the virtual address to set the PTE for - ffe80a10: set o0 to 0xf0000400, a valid PTE that points to the 4 MB mark (0x400000) in main RAM - ffe80a14: call to set that PTE in the page table - ffe80a18: set o2 to 0x00001000, so virtual address 0x1000 now points to physical 0x400000 - ffe80a1c: set i7 to 0x01000000, which indicates the memory size is 64MB if everything passes - ffe80a20: store i7 at g0, which is currently 0 - ffe80a24: SRL i7 by 2, now 0x00400000, so if the next store fails on a bus error memory size is 4 MB - ffe80a28: store the new i7 at o2, which is 0x400000 - ffe80a2c: store succeeded! load [g0] to i7, ta-da, 64 MB RAM sized + ffe80a70: call to "Setting up RAM for monitor" that goes wrong + ffe80210: testing memory + ffe80274: loop that goes wobbly and fails + ffe80dc4: switch off boot mode, MMU maps ROM to copy in RAM from here on ****************************************************************************/ @@ -429,6 +422,42 @@ #define PM_ACCESSED (0x02000000) // accessed flag #define PM_MODIFIED (0x01000000) // modified flag +namespace +{ +const sparc_disassembler::asi_desc_map::value_type sun4_asi_desc[] = { + { 0x10, { nullptr, "Flush I-Cache (Segment)" } }, + { 0x11, { nullptr, "Flush I-Cache (Page)" } }, + { 0x02, { nullptr, "System Space" } }, { 0x12, { nullptr, "Flush I-Cache (Context)" } }, + { 0x03, { nullptr, "Segment Map" } }, { 0x13, { nullptr, "Flush I-Cache (User)" } }, + { 0x04, { nullptr, "Page Map" } }, { 0x14, { nullptr, "Flush D-Cache (Segment)" } }, + { 0x05, { nullptr, "Block Copy" } }, { 0x15, { nullptr, "Flush D-Cache (Page)" } }, + { 0x06, { nullptr, "Region Map" } }, { 0x16, { nullptr, "Flush D-Cache (Context)" } }, + { 0x07, { nullptr, "Flush Cache (Region)" } }, { 0x17, { nullptr, "Flush D-Cache (User)" } }, + { 0x08, { nullptr, "User Instruction" } }, + { 0x09, { nullptr, "Supervisor Instruction" } }, + { 0x0a, { nullptr, "User Data" } }, + { 0x0b, { nullptr, "Supervisor Data" } }, { 0x1b, { nullptr, "Flush I-Cache (Region)" } }, + { 0x0c, { nullptr, "Flush Cache (Segment)" } }, + { 0x0d, { nullptr, "Flush Cache (Page)" } }, + { 0x0e, { nullptr, "Flush Cache (Context)" } }, + { 0x0f, { nullptr, "Flush Cache (User)" } }, { 0x1f, { nullptr, "Flush D-Cache (Region)" } } +}; +/* TODO: make SPARCstation-1 a different machine type so it can load its own ASI descriptions - it's a subset of Sun4 +const sparc_disassembler::asi_desc_map::value_type sun4c_asi_desc[] = { + { 0x02, { nullptr, "System Space" } }, + { 0x03, { nullptr, "Segment Map" } }, + { 0x04, { nullptr, "Page Map" } }, + { 0x08, { nullptr, "User Instruction" } }, + { 0x09, { nullptr, "Supervisor Instruction" } }, + { 0x0a, { nullptr, "User Data" } }, + { 0x0b, { nullptr, "Supervisor Data" } }, + { 0x0c, { nullptr, "Flush Cache (Segment)" } }, + { 0x0d, { nullptr, "Flush Cache (Page)" } }, + { 0x0e, { nullptr, "Flush Cache (Context)" } } +}; +*/ +} + class sun4_state : public driver_device { public: @@ -465,7 +494,8 @@ protected: required_memory_region m_rom; UINT32 *m_rom_ptr; UINT32 m_context; - UINT32 m_system_enable; + UINT8 m_system_enable; + UINT32 m_buserror[4]; private: UINT32 *m_ram_ptr; @@ -496,9 +526,10 @@ READ32_MEMBER( sun4_state::sun4_mmu_r ) return m_context<<24; case 4: // system enable reg - return m_system_enable; + return m_system_enable<<24; case 6: // bus error register + printf("sun4: read buserror, PC=%x (mask %08x)\n", m_maincpu->pc(), mem_mask); return 0; case 8: // (d-)cache tags @@ -551,7 +582,7 @@ READ32_MEMBER( sun4_state::sun4_mmu_r ) UINT32 tmp = (m_pagemap[entry] & 0xffff) << 10; tmp |= (offset & 0x3ff); - //printf("sun4: translated vaddr %08x to phys %08x type %d, PTE %08x, PC=%x\n", offset<<2, tmp<<2, (m_pagemap[entry]>>26) & 3, m_pagemap[entry], m_maincpu->pc()); + //printf("sun4: read translated vaddr %08x to phys %08x type %d, PTE %08x, PC=%x\n", offset<<2, tmp<<2, (m_pagemap[entry]>>26) & 3, m_pagemap[entry], m_maincpu->pc()); switch ((m_pagemap[entry] >> 26) & 3) { @@ -574,7 +605,11 @@ READ32_MEMBER( sun4_state::sun4_mmu_r ) } else { - printf("sun4: INVALID PTE accessed! PC=%x\n", m_maincpu->pc()); + printf("sun4: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc()); + //m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION); + //m_buserror[0] = 0x88; // read, invalid PTE + //m_buserror[1] = offset<<2; + return 0; } } break; @@ -603,11 +638,11 @@ WRITE32_MEMBER( sun4_state::sun4_mmu_w ) { case 3: // context reg printf("%08x to context, mask %08x\n", data, mem_mask); - m_context = (UINT8)data<<24; + m_context = data>>24; return; case 4: // system enable reg - m_system_enable = (UINT8)data; + m_system_enable = data>>24; return; case 8: // cache tags @@ -667,7 +702,7 @@ WRITE32_MEMBER( sun4_state::sun4_mmu_w ) UINT32 tmp = (m_pagemap[entry] & 0xffff) << 10; tmp |= (offset & 0x3ff); - //printf("sun4: translated vaddr %08x to phys %08x type %d, PTE %08x, PC=%x\n", offset<<2, tmp<<2, (m_pagemap[entry]>>26) & 3, m_pagemap[entry], m_maincpu->pc()); + //printf("sun4: write translated vaddr %08x to phys %08x type %d, PTE %08x, PC=%x\n", offset<<2, tmp<<2, (m_pagemap[entry]>>26) & 3, m_pagemap[entry], m_maincpu->pc()); switch ((m_pagemap[entry] >> 26) & 3) { @@ -686,7 +721,11 @@ WRITE32_MEMBER( sun4_state::sun4_mmu_w ) } else { - printf("sun4: INVALID PTE accessed! PC=%x\n", m_maincpu->pc()); + printf("sun4: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc()); + //m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION); + //m_buserror[0] = 0x8; // invalid PTE + //m_buserror[1] = offset<<2; + return; } break; @@ -720,10 +759,9 @@ void sun4_state::machine_start() READ32_MEMBER( sun4_state::ram_r ) { - if (offset < m_ram_size_words) return m_ram_ptr[offset]; + //printf("ram_r: @ %08x (mask %08x)\n", offset<<2, mem_mask); - //printf("ram_r: DAEing on access to %08x\n", offset<<2); - m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION); + if (offset < m_ram_size_words) return m_ram_ptr[offset]; return 0xffffffff; } @@ -783,14 +821,13 @@ WRITE32_MEMBER( sun4_state::ram_w ) } #endif + //printf("ram_w: %08x to %08x (mask %08x)\n", data, offset<<2, mem_mask); + if (offset < m_ram_size_words) { COMBINE_DATA(&m_ram_ptr[offset]); return; } - - printf("ram_w: DAEing on access to %08x\n", offset<<2); - m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION); } static ADDRESS_MAP_START(type0space_map, AS_PROGRAM, 32, sun4_state) @@ -822,9 +859,10 @@ static MACHINE_CONFIG_START( sun4, sun4_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", MB86901, 16670000) MCFG_DEVICE_ADDRESS_MAP(AS_PROGRAM, sun4_mem) + MCFG_SPARC_ADD_ASI_DESC(sun4_asi_desc) MCFG_RAM_ADD(RAM_TAG) - MCFG_RAM_DEFAULT_SIZE("4M") + MCFG_RAM_DEFAULT_SIZE("16M") MCFG_RAM_DEFAULT_VALUE(0x00) MCFG_M48T02_ADD(TIMEKEEPER_TAG) diff --git a/src/mame/drivers/system1.cpp b/src/mame/drivers/system1.cpp index a3697e9df01..5eebb7b7c59 100644 --- a/src/mame/drivers/system1.cpp +++ b/src/mame/drivers/system1.cpp @@ -5290,9 +5290,9 @@ DRIVER_INIT_MEMBER(system1_state,nobb) DRIVER_INIT_CALL(bank44); iospace.install_read_handler(0x1c, 0x1c, read8_delegate(FUNC(system1_state::nobb_inport1c_r),this)); - iospace.install_read_handler(0x22, 0x22, read8_delegate(FUNC(system1_state::nobb_inport22_r),this)); - iospace.install_read_handler(0x23, 0x23, read8_delegate(FUNC(system1_state::nobb_inport23_r),this)); - iospace.install_write_handler(0x24, 0x24, write8_delegate(FUNC(system1_state::nobb_outport24_w),this)); + iospace.install_read_handler(0x02, 0x02, read8_delegate(FUNC(system1_state::nobb_inport22_r),this)); + iospace.install_read_handler(0x03, 0x03, read8_delegate(FUNC(system1_state::nobb_inport23_r),this)); + iospace.install_write_handler(0x04, 0x04, write8_delegate(FUNC(system1_state::nobb_outport24_w),this)); } diff --git a/src/mame/drivers/taitoair.cpp b/src/mame/drivers/taitoair.cpp index b81368cadf8..74b6eef6ef9 100644 --- a/src/mame/drivers/taitoair.cpp +++ b/src/mame/drivers/taitoair.cpp @@ -153,7 +153,7 @@ DIPs ---- They're now correct (including locations) according to the -manuals. Nevertherless, ainferno manual states that the coinage +manuals. Nevertheless, ainferno manual states that the coinage DIPs are the same as topland, which is clearly wrong if you try them ("SWB:7,8" do not set Coin B to multiple credits for each coin!) @@ -536,11 +536,6 @@ static ADDRESS_MAP_START( DSP_map_data, AS_DATA, 16, taitoair_state ) AM_RANGE(0x8000, 0xffff) AM_READWRITE(dspram_r, dspram_w) ADDRESS_MAP_END -static ADDRESS_MAP_START( DSP_map_io, AS_IO, 16, taitoair_state ) - AM_RANGE(TMS32025_HOLD, TMS32025_HOLD) AM_READ(dsp_HOLD_signal_r) - AM_RANGE(TMS32025_HOLDA, TMS32025_HOLDA) AM_WRITE(dsp_HOLDA_signal_w) -ADDRESS_MAP_END - /************************************************************ INPUT PORTS & DIPS @@ -726,7 +721,8 @@ static MACHINE_CONFIG_START( airsys, taitoair_state ) MCFG_CPU_ADD("dsp", TMS32025, XTAL_36MHz) // Unverified MCFG_CPU_PROGRAM_MAP(DSP_map_program) MCFG_CPU_DATA_MAP(DSP_map_data) - MCFG_CPU_IO_MAP(DSP_map_io) + MCFG_TMS32025_HOLD_IN_CB(READ16(taitoair_state, dsp_HOLD_signal_r)) + MCFG_TMS32025_HOLD_ACK_OUT_CB(WRITE16(taitoair_state, dsp_HOLDA_signal_w)) MCFG_QUANTUM_PERFECT_CPU("maincpu") diff --git a/src/mame/drivers/ti89.cpp b/src/mame/drivers/ti89.cpp index 5638d5f3c4c..a2241e363b8 100644 --- a/src/mame/drivers/ti89.cpp +++ b/src/mame/drivers/ti89.cpp @@ -569,7 +569,7 @@ MACHINE_CONFIG_END /* ROM definition */ ROM_START( ti89 ) - ROM_REGION( 0x200000, "flash", ROMREGION_ERASEFF ) + ROM_REGION16_BE( 0x200000, "flash", ROMREGION_ERASEFF ) ROM_SYSTEM_BIOS( 0, "v100", "V 1.00 - HW1" ) ROMX_LOAD( "ti89v100.rom", 0x000000, 0x200000, CRC(264b34ad) SHA1(c87586a7e9b6d49fbe908fbb6f3c0038f3498573), ROM_BIOS(1)) ROM_SYSTEM_BIOS( 1, "v100a", "V 1.00 [a] - HW1" ) @@ -605,7 +605,7 @@ ROM_START( ti89 ) ROM_END ROM_START( ti92 ) - ROM_REGION( 0x200000, "flash", ROMREGION_ERASEFF ) + ROM_REGION16_BE( 0x200000, "flash", ROMREGION_ERASEFF ) ROM_SYSTEM_BIOS( 0, "v111", "V 1.11" ) ROMX_LOAD( "ti92v111.rom", 0x000000, 0x100000, CRC(67878d52) SHA1(c0fdf162961922a76f286c93fd9b861ce20f23a3), ROM_BIOS(1)) ROM_SYSTEM_BIOS( 1, "v13e", "V 1.3 [e]" ) @@ -624,7 +624,7 @@ ROM_START( ti92 ) ROM_END ROM_START( ti92p ) - ROM_REGION( 0x200000, "flash", ROMREGION_ERASEFF ) + ROM_REGION16_BE( 0x200000, "flash", ROMREGION_ERASEFF ) ROM_SYSTEM_BIOS( 0, "v100", "V 1.00 - HW1" ) ROMX_LOAD( "ti92pv100.rom", 0x0000, 0x200000, CRC(c651a586) SHA1(fbbf7e053e70eefe517f9aae40c072036bc614ea), ROM_BIOS(1)) ROM_SYSTEM_BIOS( 1, "v101", "V 1.01 - HW1" ) @@ -650,7 +650,7 @@ ROM_START( ti92p ) ROM_END ROM_START( v200 ) - ROM_REGION( 0x400000, "flash", ROMREGION_ERASEFF ) + ROM_REGION16_BE( 0x400000, "flash", ROMREGION_ERASEFF ) ROM_SYSTEM_BIOS( 0, "v209", "V 2.09" ) ROMX_LOAD( "voyage200v209.rom", 0x0000, 0x400000, CRC(f805c7a6) SHA1(818b919058ba3bd7d15604f11fff6740010d07fc), ROM_BIOS(1)) ROM_SYSTEM_BIOS( 1, "v310", "V 3.10" ) @@ -658,7 +658,7 @@ ROM_START( v200 ) ROM_END ROM_START( ti89t ) - ROM_REGION( 0x400000, "flash", ROMREGION_ERASEFF ) + ROM_REGION16_BE( 0x400000, "flash", ROMREGION_ERASEFF ) ROM_SYSTEM_BIOS( 0, "v300", "V 3.00" ) ROMX_LOAD( "ti89tv300.rom", 0x0000, 0x400000, CRC(55eb4f5a) SHA1(4f919d7752caf2559a79883ec8711a9701d19513), ROM_BIOS(1)) ROM_SYSTEM_BIOS( 1, "v310", "V 3.10" ) diff --git a/src/mame/drivers/vk100.cpp b/src/mame/drivers/vk100.cpp index e2b482b8bbb..a432e4ea96e 100644 --- a/src/mame/drivers/vk100.cpp +++ b/src/mame/drivers/vk100.cpp @@ -728,7 +728,7 @@ ADDRESS_MAP_END */ static ADDRESS_MAP_START(vk100_io, AS_IO, 8, vk100_state) ADDRESS_MAP_UNMAP_HIGH - ADDRESS_MAP_GLOBAL_MASK(0x7f) // guess, probably correct + ADDRESS_MAP_GLOBAL_MASK(0xff) // guess, probably correct AM_RANGE(0x00, 0x00) AM_MIRROR(0xBE) AM_DEVWRITE("crtc", mc6845_device, address_w) AM_RANGE(0x01, 0x01) AM_MIRROR(0xBE) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w) // Comments are from page 118 (5-14) of http://web.archive.org/web/20091015205827/http://www.computer.museum.uq.edu.au/pdf/EK-VK100-TM-001%20VK100%20Technical%20Manual.pdf diff --git a/src/mame/drivers/vt240.cpp b/src/mame/drivers/vt240.cpp index 2aab791f0d7..a88e129e0cf 100644 --- a/src/mame/drivers/vt240.cpp +++ b/src/mame/drivers/vt240.cpp @@ -179,7 +179,7 @@ WRITE8_MEMBER(vt240_state::i8085_comm_w) break; case 2: m_i8085->set_input_line(INPUT_LINE_RESET, PULSE_LINE); - m_t11 = 0; + m_t11 = 1; m_i8085->set_input_line(I8085_RST65_LINE, CLEAR_LINE); break; } @@ -232,7 +232,7 @@ READ8_MEMBER(vt240_state::char_buf_r) WRITE8_MEMBER(vt240_state::char_buf_w) { - m_char_buf[m_char_idx++] = ~data; + m_char_buf[m_char_idx++] = BITSWAP8(data, 0, 1, 2, 3, 4, 5, 6, 7); m_char_idx &= 0xf; } @@ -256,7 +256,7 @@ WRITE8_MEMBER(vt240_state::vram_w) { offset = ((offset & 0x30000) >> 1) | (offset & 0x7fff); if(BIT(m_reg1, 2)) - data = m_video_ram[offset]; + data = m_video_ram[offset & 0xffff]; else if(BIT(m_reg0, 4)) { data = m_char_buf[m_char_idx++]; @@ -264,13 +264,13 @@ WRITE8_MEMBER(vt240_state::vram_w) offset = BIT(offset, 16) | (offset & 0xfffe); } if(!BIT(m_reg0, 3)) - data = (data & ~m_mask) | (m_video_ram[offset] & m_mask); + data = (data & ~m_mask) | (m_video_ram[offset & 0xffff] & m_mask); m_video_ram[offset & 0xffff] = data; } WRITE8_MEMBER(vt240_state::mask_w) { - m_mask = data; + m_mask = BITSWAP8(data, 0, 1, 2, 3, 4, 5, 6, 7); } WRITE8_MEMBER(vt240_state::nvr_store_w) @@ -351,12 +351,14 @@ void vt240_state::machine_reset() m_nvram->recall(ASSERT_LINE); m_nvram->recall(CLEAR_LINE); m_mem_map_sel = 0; + m_t11 = 1; + m_i8085_rdy = 1; } static const gfx_layout vt240_chars_8x10 = { 8,10, - RGN_FRAC(1,1), + 0x240, 1, { 0 }, { STEP8(0,1) }, @@ -365,7 +367,7 @@ static const gfx_layout vt240_chars_8x10 = }; static GFXDECODE_START( vt240 ) - GFXDECODE_ENTRY( "charcpu", 0x338*10-2, vt240_chars_8x10, 0, 8 ) + GFXDECODE_ENTRY( "charcpu", 0x338*10-3, vt240_chars_8x10, 0, 8 ) GFXDECODE_END static MACHINE_CONFIG_START( vt240, vt240_state ) diff --git a/src/mame/includes/namcos21.h b/src/mame/includes/namcos21.h index e35265aa830..1578ab84b09 100644 --- a/src/mame/includes/namcos21.h +++ b/src/mame/includes/namcos21.h @@ -47,7 +47,6 @@ public: : namcos2_shared_state(mconfig, type, tag), m_winrun_dspbios(*this,"winrun_dspbios"), m_winrun_polydata(*this,"winrun_polydata"), - m_winrun_gpucomram(*this,"winrun_comram"), m_dspram16(*this,"dspram16"), m_mpDualPortRAM(*this,"mpdualportram"), m_master_dsp_code(*this,"master_dsp_code"), @@ -57,7 +56,6 @@ public: optional_shared_ptr<UINT16> m_winrun_dspbios; optional_shared_ptr<UINT16> m_winrun_polydata; - optional_shared_ptr<UINT16> m_winrun_gpucomram; optional_shared_ptr<UINT16> m_dspram16; required_shared_ptr<UINT8> m_mpDualPortRAM; optional_shared_ptr<UINT16> m_master_dsp_code; @@ -146,8 +144,6 @@ public: DECLARE_READ16_MEMBER(winrun_dsp_pointrom_data_r); DECLARE_WRITE16_MEMBER(winrun_dsp_complete_w); DECLARE_READ16_MEMBER(winrun_table_r); - DECLARE_READ16_MEMBER(winrun_gpucomram_r); - DECLARE_WRITE16_MEMBER(winrun_gpucomram_w); DECLARE_WRITE16_MEMBER(winrun_dspbios_w); DECLARE_READ16_MEMBER(winrun_68k_dspcomram_r); DECLARE_WRITE16_MEMBER(winrun_68k_dspcomram_w); diff --git a/src/mame/layout/mdndclab.lay b/src/mame/layout/mdndclab.lay index 4f806c57060..10d9f9a2ff4 100644 --- a/src/mame/layout/mdndclab.lay +++ b/src/mame/layout/mdndclab.lay @@ -23,8 +23,25 @@ return nil end last_state = true - x = ((x / target:width()) * 95) - 15 - y = ((y / target:height()) * 82.5) - 2.5 + local h = target:height() + local w = target:width() + local x0, x1, y0, y1 = target:view_bounds() + local vw = (x1 - x0) + local vh = (y1 - y0) + if machine:options().entries.keepaspect:value() then + if (vh / h) < (vw / w) then + local oh = h + h = w * (vh / vw) + y = y - ((oh - h) / 2) + else + local ow = w + w = h * (vw / vh) + x = x - ((ow - w) / 2) + end + end + + x = ((x / w) * vw) + x0 + y = ((y / h) * vh) + y0 return x, y end diff --git a/src/mame/machine/mac.cpp b/src/mame/machine/mac.cpp index 5e1f70bb7c1..02b223fc423 100644 --- a/src/mame/machine/mac.cpp +++ b/src/mame/machine/mac.cpp @@ -155,16 +155,16 @@ void mac_state::mac_install_memory(offs_t memory_begin, offs_t memory_end, offs_t memory_mirror; memory_size = MIN(memory_size, (memory_end + 1 - memory_begin)); - memory_mirror = (memory_end - memory_begin) ^ (memory_size - 1); + memory_mirror = (memory_end - memory_begin) & ~(memory_size - 1); if (!is_rom) { - space.install_readwrite_bank(memory_begin, memory_end, memory_mirror, bank); + space.install_readwrite_bank(memory_begin, memory_end & ~memory_mirror, memory_mirror, bank); } else { space.unmap_write(memory_begin, memory_end); - space.install_read_bank(memory_begin, memory_end, memory_mirror, bank); + space.install_read_bank(memory_begin, memory_end & ~memory_mirror, memory_mirror, bank); } membank(bank)->set_base(memory_data); @@ -471,7 +471,7 @@ void mac_state::set_memory_overlay(int overlay) else { size_t rom_mirror = 0xfffffff ^ (memregion("bootrom")->bytes() - 1); - m_maincpu->space(AS_PROGRAM).install_read_bank(0x40000000, 0x4fffffff, rom_mirror, "bankR"); + m_maincpu->space(AS_PROGRAM).install_read_bank(0x40000000, 0x4fffffff & ~rom_mirror, rom_mirror, "bankR"); membank("bankR")->set_base((void *)memregion("bootrom")->base()); } } diff --git a/src/mame/video/abc1600.cpp b/src/mame/video/abc1600.cpp index 441d0a2c711..4b928d76635 100644 --- a/src/mame/video/abc1600.cpp +++ b/src/mame/video/abc1600.cpp @@ -188,11 +188,8 @@ static MACHINE_CONFIG_FRAGMENT( abc1600_mover ) MCFG_DEFAULT_LAYOUT(layout_abc1600) MCFG_SCREEN_ADD_MONOCHROME(SCREEN_TAG, RASTER, rgb_t::green) - MCFG_SCREEN_REFRESH_RATE(60) - MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) // not accurate MCFG_SCREEN_UPDATE_DRIVER(abc1600_mover_device, screen_update) - MCFG_SCREEN_SIZE(958, 1067) - MCFG_SCREEN_VISIBLE_AREA(0, 958-1, 0, 1067-1) + MCFG_SCREEN_RAW_PARAMS(XTAL_64MHz, 0x3e0, 0, 0x300, 0x433, 0, 0x400) MCFG_PALETTE_ADD_MONOCHROME("palette") diff --git a/src/mame/video/abc800.cpp b/src/mame/video/abc800.cpp index 422cf3ae6a0..4bd01b4160f 100644 --- a/src/mame/video/abc800.cpp +++ b/src/mame/video/abc800.cpp @@ -302,10 +302,7 @@ MACHINE_CONFIG_FRAGMENT( abc800m_video ) MCFG_SCREEN_ADD_MONOCHROME(SCREEN_TAG, RASTER, rgb_t(0xff, 0xff, 0x00)) MCFG_SCREEN_UPDATE_DRIVER(abc800m_state, screen_update) - MCFG_SCREEN_REFRESH_RATE(60) - MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) - MCFG_SCREEN_SIZE(768, 312) - MCFG_SCREEN_VISIBLE_AREA(0,768-1, 0, 312-1) + MCFG_SCREEN_RAW_PARAMS(XTAL_12MHz, 0x300, 0, 0x1e0, 0x13a, 0, 0xf0) MCFG_PALETTE_ADD_MONOCHROME("palette") MACHINE_CONFIG_END diff --git a/src/mame/video/abc802.cpp b/src/mame/video/abc802.cpp index c2786d0b024..579a0240f5a 100644 --- a/src/mame/video/abc802.cpp +++ b/src/mame/video/abc802.cpp @@ -210,11 +210,7 @@ MACHINE_CONFIG_FRAGMENT( abc802_video ) MCFG_SCREEN_ADD_MONOCHROME(SCREEN_TAG, RASTER, rgb_t::amber) MCFG_SCREEN_UPDATE_DRIVER(abc802_state, screen_update) - - MCFG_SCREEN_REFRESH_RATE(60) - MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) - MCFG_SCREEN_SIZE(768, 312) - MCFG_SCREEN_VISIBLE_AREA(0,768-1, 0, 312-1) + MCFG_SCREEN_RAW_PARAMS(XTAL_12MHz, 0x300, 0, 0x1e0, 0x13a, 0, 0xf0) MCFG_PALETTE_ADD_MONOCHROME("palette") MACHINE_CONFIG_END diff --git a/src/mame/video/abc806.cpp b/src/mame/video/abc806.cpp index 4e8ff8ba854..3d4a31ec39c 100644 --- a/src/mame/video/abc806.cpp +++ b/src/mame/video/abc806.cpp @@ -497,10 +497,7 @@ MACHINE_CONFIG_FRAGMENT( abc806_video ) MCFG_SCREEN_ADD(SCREEN_TAG, RASTER) MCFG_SCREEN_UPDATE_DRIVER(abc806_state, screen_update) - MCFG_SCREEN_REFRESH_RATE(60) - MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) - MCFG_SCREEN_SIZE(768, 312) - MCFG_SCREEN_VISIBLE_AREA(0, 768-1, 0, 312-1) + MCFG_SCREEN_RAW_PARAMS(XTAL_12MHz, 0x300, 0, 0x1e0, 0x13a, 0, 0xfa) MCFG_PALETTE_ADD("palette", 8) MCFG_PALETTE_INIT_OWNER(abc806_state, abc806) diff --git a/src/osd/modules/debugger/debugimgui.cpp b/src/osd/modules/debugger/debugimgui.cpp index 3a20219fd51..d1f17e08114 100644 --- a/src/osd/modules/debugger/debugimgui.cpp +++ b/src/osd/modules/debugger/debugimgui.cpp @@ -39,6 +39,7 @@ public: this->m_machine = &machine; this->width = 300; this->height = 300; + this->console_prev.clear(); /* specials */ switch (type) @@ -78,6 +79,7 @@ public: int src_sel; char console_input[512]; std::vector<std::string> console_history; + std::string console_prev; }; class debug_imgui : public osd_module, public debug_module @@ -465,7 +467,12 @@ void debug_imgui::handle_console(running_machine* machine) m_running = true; if(strcmp(view_main_console->console_input,"next") == 0) m_running = true; - view_main_console->console_history.push_back(std::string(view_main_console->console_input)); + // don't bother adding to history if the current command matches the previous one + if(view_main_console->console_prev != view_main_console->console_input) + { + view_main_console->console_history.push_back(std::string(view_main_console->console_input)); + view_main_console->console_prev = view_main_console->console_input; + } history_pos = view_main_console->console_history.size(); strcpy(view_main_console->console_input,""); view_main_console->exec_cmd = false; diff --git a/src/tools/unidasm.cpp b/src/tools/unidasm.cpp index ee125761ee6..aefde45d1c9 100644 --- a/src/tools/unidasm.cpp +++ b/src/tools/unidasm.cpp @@ -9,6 +9,7 @@ ****************************************************************************/ #include "emu.h" +#include "cpu/sparc/sparcdasm.h" #include <ctype.h> enum display_type @@ -206,6 +207,25 @@ CPU_DISASSEMBLE( z8 ); CPU_DISASSEMBLE( z80 ); CPU_DISASSEMBLE( z8000 ); +static sparc_disassembler sparcv7_dasm(7); +static sparc_disassembler sparcv8_dasm(8); +static sparc_disassembler sparcv9_dasm(9); +static sparc_disassembler sparcv9vis1_dasm(9); +static sparc_disassembler sparcv9vis2_dasm(9); +struct sparc_helper_c +{ + sparc_helper_c() + { + sparcv9vis1_dasm.enable_vis1(); + sparcv9vis2_dasm.enable_vis2(); + } +} sparc_helper; +CPU_DISASSEMBLE( sparcv7 ) { return sparcv7_dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); } +CPU_DISASSEMBLE( sparcv8 ) { return sparcv8_dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); } +CPU_DISASSEMBLE( sparcv9 ) { return sparcv9_dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); } +CPU_DISASSEMBLE( sparcv9vis1 ) { return sparcv9vis1_dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); } +CPU_DISASSEMBLE( sparcv9vis2 ) { return sparcv9vis2_dasm.dasm(buffer, pc, BIG_ENDIANIZE_INT32(*reinterpret_cast<const UINT32 *>(oprom))); } + static const dasm_table_entry dasm_table[] = { @@ -319,6 +339,11 @@ static const dasm_table_entry dasm_table[] = { "sm510", _8bit, 0, CPU_DISASSEMBLE_NAME(sm510) }, { "sm511", _8bit, 0, CPU_DISASSEMBLE_NAME(sm511) }, { "sm8500", _8bit, 0, CPU_DISASSEMBLE_NAME(sm8500) }, + { "sparcv7", _32be, 0, CPU_DISASSEMBLE_NAME(sparcv7) }, + { "sparcv8", _32be, 0, CPU_DISASSEMBLE_NAME(sparcv8) }, + { "sparcv9", _32be, 0, CPU_DISASSEMBLE_NAME(sparcv9) }, + { "sparcv9vis1",_32be, 0, CPU_DISASSEMBLE_NAME(sparcv9vis1) }, + { "sparcv9vis2",_32be, 0, CPU_DISASSEMBLE_NAME(sparcv9vis2) }, { "spc700", _8bit, 0, CPU_DISASSEMBLE_NAME(spc700) }, { "ssem", _32le, 0, CPU_DISASSEMBLE_NAME(ssem) }, { "ssp1601", _16be, -1, CPU_DISASSEMBLE_NAME(ssp1601) }, @@ -485,15 +510,15 @@ usage: printf(" [-skip <n>] [-count <n>]\n"); printf("\n"); printf("Supported architectures:"); - numrows = (ARRAY_LENGTH(dasm_table) + 6) / 7; - for (curarch = 0; curarch < numrows * 7; curarch++) + numrows = (ARRAY_LENGTH(dasm_table) + 5) / 6; + for (curarch = 0; curarch < numrows * 6; curarch++) { - int row = curarch / 7; - int col = curarch % 7; + int row = curarch / 6; + int col = curarch % 6; int index = col * numrows + row; if (col == 0) printf("\n "); - printf("%-11s", (index < ARRAY_LENGTH(dasm_table)) ? dasm_table[index].name : ""); + printf("%-12s", (index < ARRAY_LENGTH(dasm_table)) ? dasm_table[index].name : ""); } printf("\n"); return 1; |