diff options
| author | 2007-12-25 17:56:12 +0000 | |
|---|---|---|
| committer | 2007-12-25 17:56:12 +0000 | |
| commit | 24edb7d555a81318c6e4d6261fe23de63f31609a (patch) | |
| tree | f42c3bbeb0f1fdaccb9b645597128295ec729208 /src | |
| parent | 3ff2882ddaf160033b534635d7bac49fc65981ef (diff) | |
Fixed M65C02 optimization [Peter Trauner]
Diffstat (limited to 'src')
| -rw-r--r-- | src/emu/cpu/m6502/ops02.h | 22 | ||||
| -rw-r--r-- | src/emu/cpu/m6502/t6502.c | 16 |
2 files changed, 20 insertions, 18 deletions
diff --git a/src/emu/cpu/m6502/ops02.h b/src/emu/cpu/m6502/ops02.h index 45006b1de3f..12eac51a2a4 100644 --- a/src/emu/cpu/m6502/ops02.h +++ b/src/emu/cpu/m6502/ops02.h @@ -93,16 +93,18 @@ * extra cycle if page boundary is crossed ***************************************************************/ #define BRA(cond) \ - tmp = RDOPARG(); \ - if (cond) \ - { \ - RDMEM(PCW); \ - EAW = PCW + (signed char)tmp; \ - if ( EAH != PCH ) { \ - RDMEM( (PCH << 8 ) | EAL) ; \ - } \ - PCD = EAD; \ - CHANGE_PC; \ + { \ + INT8 tmp2 = RDOPARG(); \ + if (cond) \ + { \ + RDMEM(PCW); \ + EAW = PCW + (signed char)tmp2; \ + if ( EAH != PCH ) { \ + RDMEM( (PCH << 8 ) | EAL) ; \ + } \ + PCD = EAD; \ + CHANGE_PC; \ + } \ } /*************************************************************** diff --git a/src/emu/cpu/m6502/t6502.c b/src/emu/cpu/m6502/t6502.c index f171f4143c8..de281ac1b62 100644 --- a/src/emu/cpu/m6502/t6502.c +++ b/src/emu/cpu/m6502/t6502.c @@ -42,14 +42,14 @@ OP(a0) { int tmp; RD_IMM; LDY; } /* 2 LDY IMM */ OP(c0) { int tmp; RD_IMM; CPY; } /* 2 CPY IMM */ OP(e0) { int tmp; RD_IMM; CPX; } /* 2 CPX IMM */ -OP(10) { int tmp; BPL; } /* 2-4 BPL REL */ -OP(30) { int tmp; BMI; } /* 2-4 BMI REL */ -OP(50) { int tmp; BVC; } /* 2-4 BVC REL */ -OP(70) { int tmp; BVS; } /* 2-4 BVS REL */ -OP(90) { int tmp; BCC; } /* 2-4 BCC REL */ -OP(b0) { int tmp; BCS; } /* 2-4 BCS REL */ -OP(d0) { int tmp; BNE; } /* 2-4 BNE REL */ -OP(f0) { int tmp; BEQ; } /* 2-4 BEQ REL */ +OP(10) { BPL; } /* 2-4 BPL REL */ +OP(30) { BMI; } /* 2-4 BMI REL */ +OP(50) { BVC; } /* 2-4 BVC REL */ +OP(70) { BVS; } /* 2-4 BVS REL */ +OP(90) { BCC; } /* 2-4 BCC REL */ +OP(b0) { BCS; } /* 2-4 BCS REL */ +OP(d0) { BNE; } /* 2-4 BNE REL */ +OP(f0) { BEQ; } /* 2-4 BEQ REL */ OP(01) { int tmp; RD_IDX; ORA; } /* 6 ORA IDX */ OP(21) { int tmp; RD_IDX; AND; } /* 6 AND IDX */ |
