diff options
author | 2014-01-01 14:29:52 +0000 | |
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committer | 2014-01-01 14:29:52 +0000 | |
commit | 16c2005516324fe975ae4b32650c8028c16e72f4 (patch) | |
tree | c100d1d6329e106dd8b8fffd94cab195e92f712f /src | |
parent | 64dcec6b990a977ce54fbc50c6aee370150c7154 (diff) |
removed ca2 & cb2 callback, they didn't do anything [smf]
Diffstat (limited to 'src')
-rw-r--r-- | src/mame/drivers/aristmk4.c | 21 |
1 files changed, 1 insertions, 20 deletions
diff --git a/src/mame/drivers/aristmk4.c b/src/mame/drivers/aristmk4.c index 8b25692a0ca..426d9808a59 100644 --- a/src/mame/drivers/aristmk4.c +++ b/src/mame/drivers/aristmk4.c @@ -324,8 +324,6 @@ public: DECLARE_READ8_MEMBER(via_b_r); DECLARE_WRITE8_MEMBER(via_a_w); DECLARE_WRITE8_MEMBER(via_b_w); - DECLARE_READ_LINE_MEMBER(via_ca2_r); - DECLARE_READ_LINE_MEMBER(via_cb2_r); DECLARE_WRITE_LINE_MEMBER(via_ca2_w); DECLARE_WRITE_LINE_MEMBER(via_cb2_w); DECLARE_WRITE8_MEMBER(pblp_out); @@ -833,24 +831,9 @@ WRITE8_MEMBER(aristmk4_state::via_b_w) } } -READ_LINE_MEMBER(aristmk4_state::via_ca2_r) -{ - //logerror("Via Port CA2 read %02X\n",0) ; - // CA2 is connected to CDSOL1 on schematics ? - - return 0 ; -} - -READ_LINE_MEMBER(aristmk4_state::via_cb2_r) -{ - //logerror("Via Port CB2 read %02X\n",0) ; - // CB2 is connected to HOPMO1 on schematics ? - - return 0 ; -} - WRITE_LINE_MEMBER(aristmk4_state::via_ca2_w) { + // CA2 is connected to CDSOL1 on schematics ? //logerror("Via Port CA2 write %02X\n",data) ; } @@ -1729,8 +1712,6 @@ static MACHINE_CONFIG_START( aristmk4, aristmk4_state ) MCFG_DEVICE_ADD("via6522_0", VIA6522, 0) /* 1 MHz.(only 1 or 2 MHz.are valid) */ MCFG_VIA6522_READPA_HANDLER(READ8(aristmk4_state, via_a_r)) MCFG_VIA6522_READPB_HANDLER(READ8(aristmk4_state, via_b_r)) - MCFG_VIA6522_READCA2_HANDLER(READLINE(aristmk4_state, via_ca2_r)) - MCFG_VIA6522_READCB2_HANDLER(READLINE(aristmk4_state, via_cb2_r)) MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(aristmk4_state, via_a_w)) MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(aristmk4_state, via_b_w)) MCFG_VIA6522_CA2_HANDLER(WRITELINE(aristmk4_state, via_ca2_w)) |