summaryrefslogtreecommitdiffstatshomepage
path: root/src
diff options
context:
space:
mode:
author Aaron Giles <aaron@aarongiles.com>2021-04-22 08:49:31 -0700
committer Aaron Giles <aaron@aarongiles.com>2021-04-22 08:49:31 -0700
commit08688e308353b7041cb6208b2782b19e605a57ce (patch)
tree6648a2288ce8baa07ab3cf871a3c183f5f8b5f80 /src
parenta27f59b81a642c13fce8fcf4b51c6fc64744aee3 (diff)
mips3: Ensure there is at least 1 cycle to be counted after reading Count. Without this, some timing loops won't exit to the scheduler until they complete.
Diffstat (limited to 'src')
-rw-r--r--src/devices/cpu/mips/mips3drc.cpp12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/devices/cpu/mips/mips3drc.cpp b/src/devices/cpu/mips/mips3drc.cpp
index 9b3396a09f9..24813885088 100644
--- a/src/devices/cpu/mips/mips3drc.cpp
+++ b/src/devices/cpu/mips/mips3drc.cpp
@@ -2460,6 +2460,11 @@ bool mips3_device::generate_set_cop0_reg(drcuml_block &block, compiler_state &co
return true;
case COP0_Count:
+ // don't count the cycle for this instruction yet; we need a non-zero cycle
+ // count in case we are in a delay slot, otherwise the test for negative cycles
+ // won't be generated (due to compiler.cycles == 0); see the loop during early
+ // boot of gauntdl, @BFC01A24
+ compiler.cycles--;
generate_update_cycles(block, compiler, desc->pc, !in_delay_slot); // <subtract cycles>
UML_MOV(block, CPR032(COP0_Count), I0); // mov [Count],i0
UML_CALLC(block, cfunc_get_cycles, this); // callc cfunc_get_cycles,mips3
@@ -2468,6 +2473,7 @@ bool mips3_device::generate_set_cop0_reg(drcuml_block &block, compiler_state &co
UML_DSUB(block, mem(&m_core->count_zero_time), mem(&m_core->numcycles), I0);
// dsub [count_zero_time],[m_numcycles],i0
UML_CALLC(block, cfunc_mips3com_update_cycle_counting, this); // callc mips3com_update_cycle_counting,mips.core
+ compiler.cycles++;
return true;
case COP0_Compare:
@@ -2513,12 +2519,18 @@ bool mips3_device::generate_get_cop0_reg(drcuml_block &block, compiler_state &co
switch (reg)
{
case COP0_Count:
+ // don't count the cycle for this instruction yet; we need a non-zero cycle
+ // count in case we are in a delay slot, otherwise the test for negative cycles
+ // won't be generated (due to compiler.cycles == 0); see the loop during early
+ // boot of gauntdl, @BFC01A24
+ compiler.cycles--;
generate_update_cycles(block, compiler, desc->pc, false); // <subtract cycles>
UML_CALLC(block, cfunc_get_cycles, this); // callc cfunc_get_cycles,mips3
UML_DSUB(block, I0, mem(&m_core->numcycles), mem(&m_core->count_zero_time));
// dsub i0,[numcycles],[count_zero_time]
UML_DSHR(block, I0, I0, 1); // dshr i0,i0,1
UML_DSEXT(block, I0, I0, SIZE_DWORD); // dsext i0,i0,dword
+ compiler.cycles++;
return true;
case COP0_Random: