diff options
| author | 2026-03-02 05:38:00 +0100 | |
|---|---|---|
| committer | 2026-03-02 05:38:00 +0100 | |
| commit | d87f59736550a3d3f557f0fe268eb2e5436ae7b1 (patch) | |
| tree | 2adb760e6101ca031ba655ee0fd2cb69d0fbdbf9 /src/devices/cpu | |
| parent | 9abbbce27ba592f63d8ca3a05a73e13c77217ec9 (diff) | |
cpu/nec: correct name after prev commit (subc, not subb)
Diffstat (limited to 'src/devices/cpu')
| -rw-r--r-- | src/devices/cpu/nec/nec80inst.hxx | 18 | ||||
| -rw-r--r-- | src/devices/cpu/nec/necinstr.hxx | 20 | ||||
| -rw-r--r-- | src/devices/cpu/nec/necmacro.h | 4 |
3 files changed, 21 insertions, 21 deletions
diff --git a/src/devices/cpu/nec/nec80inst.hxx b/src/devices/cpu/nec/nec80inst.hxx index e5a106817da..a1be658a69d 100644 --- a/src/devices/cpu/nec/nec80inst.hxx +++ b/src/devices/cpu/nec/nec80inst.hxx @@ -149,14 +149,14 @@ OP80( 0x94, i_subh ) { uint32_t src = Breg(BH), dst = Breg(AL); SUBB; Breg(AL) OP80( 0x95, i_subl ) { uint32_t src = Breg(BL), dst = Breg(AL); SUBB; Breg(AL) = dst; CLK(1); } OP80( 0x96, i_subm ) { uint32_t src = GetMemB(DS0, Wreg(BW)), dst = Breg(AL); SUBB; Breg(AL) = dst; CLK(1); } OP80( 0x97, i_suba ) { uint32_t src = Breg(AL), dst = Breg(AL); SUBB; Breg(AL) = dst; CLK(1); } -OP80( 0x98, i_sbbb ) { uint32_t src = Breg(CH), dst = Breg(AL); SUBBB; Breg(AL) = dst; CLK(1); } -OP80( 0x99, i_sbbc ) { uint32_t src = Breg(CL), dst = Breg(AL); SUBBB; Breg(AL) = dst; CLK(1); } -OP80( 0x9a, i_sbbd ) { uint32_t src = Breg(DH), dst = Breg(AL); SUBBB; Breg(AL) = dst; CLK(1); } -OP80( 0x9b, i_sbbe ) { uint32_t src = Breg(DL), dst = Breg(AL); SUBBB; Breg(AL) = dst; CLK(1); } -OP80( 0x9c, i_sbbh ) { uint32_t src = Breg(BH), dst = Breg(AL); SUBBB; Breg(AL) = dst; CLK(1); } -OP80( 0x9d, i_sbbl ) { uint32_t src = Breg(BL), dst = Breg(AL); SUBBB; Breg(AL) = dst; CLK(1); } -OP80( 0x9e, i_sbbm ) { uint32_t src = GetMemB(DS0, Wreg(BW)), dst = Breg(AL); SUBBB; Breg(AL) = dst; CLK(1); } -OP80( 0x9f, i_sbba ) { uint32_t src = Breg(AL), dst = Breg(AL); SUBBB; Breg(AL) = dst; CLK(1); } +OP80( 0x98, i_sbbb ) { uint32_t src = Breg(CH), dst = Breg(AL); SUBCB; Breg(AL) = dst; CLK(1); } +OP80( 0x99, i_sbbc ) { uint32_t src = Breg(CL), dst = Breg(AL); SUBCB; Breg(AL) = dst; CLK(1); } +OP80( 0x9a, i_sbbd ) { uint32_t src = Breg(DH), dst = Breg(AL); SUBCB; Breg(AL) = dst; CLK(1); } +OP80( 0x9b, i_sbbe ) { uint32_t src = Breg(DL), dst = Breg(AL); SUBCB; Breg(AL) = dst; CLK(1); } +OP80( 0x9c, i_sbbh ) { uint32_t src = Breg(BH), dst = Breg(AL); SUBCB; Breg(AL) = dst; CLK(1); } +OP80( 0x9d, i_sbbl ) { uint32_t src = Breg(BL), dst = Breg(AL); SUBCB; Breg(AL) = dst; CLK(1); } +OP80( 0x9e, i_sbbm ) { uint32_t src = GetMemB(DS0, Wreg(BW)), dst = Breg(AL); SUBCB; Breg(AL) = dst; CLK(1); } +OP80( 0x9f, i_sbba ) { uint32_t src = Breg(AL), dst = Breg(AL); SUBCB; Breg(AL) = dst; CLK(1); } OP80( 0xa0, i_anab ) { uint32_t src = Breg(CH), dst = Breg(AL); ANDB; Breg(AL) = dst; CLK(1); } OP80( 0xa1, i_anac ) { uint32_t src = Breg(CL), dst = Breg(AL); ANDB; Breg(AL) = dst; CLK(1); } OP80( 0xa2, i_anad ) { uint32_t src = Breg(DH), dst = Breg(AL); ANDB; Breg(AL) = dst; CLK(1); } @@ -216,7 +216,7 @@ OP80( 0xd8, i_rc ) { if (CF) { POP80(m_ip); CHANGE_PC; } CLK(1); } OP80( 0xda, i_jc ) { uint32_t addr = fetchword(); if (CF) { m_ip = addr; CHANGE_PC; } CLK(1); } OP80( 0xdb, i_in ) { uint8_t port = fetch(); Breg(AL) = read_port_byte(port); CLK(1); } OP80( 0xdc, i_cc ) { uint32_t addr = fetchword(); if (CF) { PUSH80(m_ip); m_ip = addr; CHANGE_PC; } CLK(1); } -OP80( 0xde, i_sbi ) { uint32_t src = fetch(), dst = Breg(AL); SUBBB; Breg(AL) = dst; CLK(1); } +OP80( 0xde, i_sbi ) { uint32_t src = fetch(), dst = Breg(AL); SUBCB; Breg(AL) = dst; CLK(1); } OP80( 0xdf, i_rst3 ) { PUSH80(m_ip); m_ip = 0x18; CHANGE_PC; CLK(1); } OP80( 0xe0, i_rpo ) { if (!PF) { POP80(m_ip); CHANGE_PC; } CLK(1); } OP80( 0xe1, i_poph ) { POP80(Wreg(BW)); } diff --git a/src/devices/cpu/nec/necinstr.hxx b/src/devices/cpu/nec/necinstr.hxx index a8b598c93c3..b81009b17cf 100644 --- a/src/devices/cpu/nec/necinstr.hxx +++ b/src/devices/cpu/nec/necinstr.hxx @@ -293,12 +293,12 @@ OP( 0x15, i_adc_axd16) { DEF_axd16; ADDCW; Wreg(AW)=dst; CLKS(4,4,2) OP( 0x16, i_push_ss ) { PUSH(Sreg(SS)); CLKS(12,8,3); } OP( 0x17, i_pop_ss ) { POP(Sreg(SS)); CLKS(12,8,5); m_no_interrupt=1; } -OP( 0x18, i_sbb_br8 ) { DEF_br8; SUBBB; PutbackRMByte(ModRM,dst); CLKM(2,2,2,16,16,7); } -OP( 0x19, i_sbb_wr16 ) { DEF_wr16; SUBBW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,m_EA);} -OP( 0x1a, i_sbb_r8b ) { DEF_r8b; SUBBB; RegByte(ModRM)=dst; CLKM(2,2,2,11,11,6); } -OP( 0x1b, i_sbb_r16w ) { DEF_r16w; SUBBW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,m_EA); } -OP( 0x1c, i_sbb_ald8 ) { DEF_ald8; SUBBB; Breg(AL)=dst; CLKS(4,4,2); } -OP( 0x1d, i_sbb_axd16) { DEF_axd16; SUBBW; Wreg(AW)=dst; CLKS(4,4,2); } +OP( 0x18, i_sbb_br8 ) { DEF_br8; SUBCB; PutbackRMByte(ModRM,dst); CLKM(2,2,2,16,16,7); } +OP( 0x19, i_sbb_wr16 ) { DEF_wr16; SUBCW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,m_EA);} +OP( 0x1a, i_sbb_r8b ) { DEF_r8b; SUBCB; RegByte(ModRM)=dst; CLKM(2,2,2,11,11,6); } +OP( 0x1b, i_sbb_r16w ) { DEF_r16w; SUBCW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,m_EA); } +OP( 0x1c, i_sbb_ald8 ) { DEF_ald8; SUBCB; Breg(AL)=dst; CLKS(4,4,2); } +OP( 0x1d, i_sbb_axd16) { DEF_axd16; SUBCW; Wreg(AW)=dst; CLKS(4,4,2); } OP( 0x1e, i_push_ds ) { PUSH(Sreg(DS0)); CLKS(12,8,3); } OP( 0x1f, i_pop_ds ) { POP(Sreg(DS0)); CLKS(12,8,5); } @@ -444,7 +444,7 @@ OP( 0x80, i_80pre ) { uint32_t dst, src; GetModRM; dst = GetRMByte(ModRM); src case 0x00: ADDB; PutbackRMByte(ModRM,dst); break; case 0x08: ORB; PutbackRMByte(ModRM,dst); break; case 0x10: ADDCB; PutbackRMByte(ModRM,dst); break; - case 0x18: SUBBB; PutbackRMByte(ModRM,dst); break; + case 0x18: SUBCB; PutbackRMByte(ModRM,dst); break; case 0x20: ANDB; PutbackRMByte(ModRM,dst); break; case 0x28: SUBB; PutbackRMByte(ModRM,dst); break; case 0x30: XORB; PutbackRMByte(ModRM,dst); break; @@ -458,7 +458,7 @@ OP( 0x81, i_81pre ) { uint32_t dst, src; GetModRM; dst = GetRMWord(ModRM); src case 0x00: ADDW; PutbackRMWord(ModRM,dst); break; case 0x08: ORW; PutbackRMWord(ModRM,dst); break; case 0x10: ADDCW; PutbackRMWord(ModRM,dst); break; - case 0x18: SUBBW; PutbackRMWord(ModRM,dst); break; + case 0x18: SUBCW; PutbackRMWord(ModRM,dst); break; case 0x20: ANDW; PutbackRMWord(ModRM,dst); break; case 0x28: SUBW; PutbackRMWord(ModRM,dst); break; case 0x30: XORW; PutbackRMWord(ModRM,dst); break; @@ -472,7 +472,7 @@ OP( 0x82, i_82pre ) { uint32_t dst, src; GetModRM; dst = GetRMByte(ModRM); src case 0x00: ADDB; PutbackRMByte(ModRM,dst); break; case 0x08: ORB; PutbackRMByte(ModRM,dst); break; case 0x10: ADDCB; PutbackRMByte(ModRM,dst); break; - case 0x18: SUBBB; PutbackRMByte(ModRM,dst); break; + case 0x18: SUBCB; PutbackRMByte(ModRM,dst); break; case 0x20: ANDB; PutbackRMByte(ModRM,dst); break; case 0x28: SUBB; PutbackRMByte(ModRM,dst); break; case 0x30: XORB; PutbackRMByte(ModRM,dst); break; @@ -486,7 +486,7 @@ OP( 0x83, i_83pre ) { uint32_t dst, src; GetModRM; dst = GetRMWord(ModRM); src case 0x00: ADDW; PutbackRMWord(ModRM,dst); break; case 0x08: ORW; PutbackRMWord(ModRM,dst); break; case 0x10: ADDCW; PutbackRMWord(ModRM,dst); break; - case 0x18: SUBBW; PutbackRMWord(ModRM,dst); break; + case 0x18: SUBCW; PutbackRMWord(ModRM,dst); break; case 0x20: ANDW; PutbackRMWord(ModRM,dst); break; case 0x28: SUBW; PutbackRMWord(ModRM,dst); break; case 0x30: XORW; PutbackRMWord(ModRM,dst); break; diff --git a/src/devices/cpu/nec/necmacro.h b/src/devices/cpu/nec/necmacro.h index c9f1d31bb63..c286ef99071 100644 --- a/src/devices/cpu/nec/necmacro.h +++ b/src/devices/cpu/nec/necmacro.h @@ -31,8 +31,8 @@ #define SUBB { uint32_t res=dst-src; SetCFB(res); SetOFB_Sub(res,src,dst); SetAF(res,src,dst); SetSZPF_Byte(res); dst=(BYTE)res; } #define SUBW { uint32_t res=dst-src; SetCFW(res); SetOFW_Sub(res,src,dst); SetAF(res,src,dst); SetSZPF_Word(res); dst=(WORD)res; } -#define SUBBB { uint32_t res=dst-src-CF; SetCFB(res); SetOFB_Sub(res,src,dst); SetAF(res,src,dst); SetSZPF_Byte(res); dst=(BYTE)res; } -#define SUBBW { uint32_t res=dst-src-CF; SetCFW(res); SetOFW_Sub(res,src,dst); SetAF(res,src,dst); SetSZPF_Word(res); dst=(WORD)res; } +#define SUBCB { uint32_t res=dst-src-CF; SetCFB(res); SetOFB_Sub(res,src,dst); SetAF(res,src,dst); SetSZPF_Byte(res); dst=(BYTE)res; } +#define SUBCW { uint32_t res=dst-src-CF; SetCFW(res); SetOFW_Sub(res,src,dst); SetAF(res,src,dst); SetSZPF_Word(res); dst=(WORD)res; } #define ORB dst|=src; m_CarryVal=m_OverVal=m_AuxVal=0; SetSZPF_Byte(dst) #define ORW dst|=src; m_CarryVal=m_OverVal=m_AuxVal=0; SetSZPF_Word(dst) |
