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author hap <happppp@users.noreply.github.com>2026-03-02 04:50:28 +0100
committer hap <happppp@users.noreply.github.com>2026-03-02 04:50:28 +0100
commit9abbbce27ba592f63d8ca3a05a73e13c77217ec9 (patch)
treed8c4ffaef545d0596d4bdcd137d296ea5b5d04be /src/devices/cpu
parentb3f2f76124c46c62dc633d202ad75315e66de888 (diff)
cpu/nec: correction to addc/subb overflow flag calculation
Diffstat (limited to 'src/devices/cpu')
-rw-r--r--src/devices/cpu/nec/nec80inst.hxx36
-rw-r--r--src/devices/cpu/nec/necinstr.hxx40
-rw-r--r--src/devices/cpu/nec/necmacro.h6
3 files changed, 44 insertions, 38 deletions
diff --git a/src/devices/cpu/nec/nec80inst.hxx b/src/devices/cpu/nec/nec80inst.hxx
index 8bcf95f3acd..e5a106817da 100644
--- a/src/devices/cpu/nec/nec80inst.hxx
+++ b/src/devices/cpu/nec/nec80inst.hxx
@@ -133,14 +133,14 @@ OP80( 0x84, i_addh ) { uint32_t src = Breg(BH), dst = Breg(AL); ADDB; Breg(AL)
OP80( 0x85, i_addl ) { uint32_t src = Breg(BL), dst = Breg(AL); ADDB; Breg(AL) = dst; CLK(1); }
OP80( 0x86, i_addm ) { uint32_t src = GetMemB(DS0, Wreg(BW)), dst = Breg(AL); ADDB; Breg(AL) = dst; CLK(1); }
OP80( 0x87, i_adda ) { uint32_t src = Breg(AL), dst = Breg(AL); ADDB; Breg(AL) = dst; CLK(1); }
-OP80( 0x88, i_adcb ) { uint32_t src = Breg(CH), dst = Breg(AL); src+=CF; ADDB; Breg(AL) = dst; CLK(1); }
-OP80( 0x89, i_adcc ) { uint32_t src = Breg(CL), dst = Breg(AL); src+=CF; ADDB; Breg(AL) = dst; CLK(1); }
-OP80( 0x8a, i_adcd ) { uint32_t src = Breg(DH), dst = Breg(AL); src+=CF; ADDB; Breg(AL) = dst; CLK(1); }
-OP80( 0x8b, i_adce ) { uint32_t src = Breg(DL), dst = Breg(AL); src+=CF; ADDB; Breg(AL) = dst; CLK(1); }
-OP80( 0x8c, i_adch ) { uint32_t src = Breg(BH), dst = Breg(AL); src+=CF; ADDB; Breg(AL) = dst; CLK(1); }
-OP80( 0x8d, i_adcl ) { uint32_t src = Breg(BL), dst = Breg(AL); src+=CF; ADDB; Breg(AL) = dst; CLK(1); }
-OP80( 0x8e, i_adcm ) { uint32_t src = GetMemB(DS0, Wreg(BW)), dst = Breg(AL); src+=CF; ADDB; Breg(AL) = dst; CLK(1); }
-OP80( 0x8f, i_adca ) { uint32_t src = Breg(AL), dst = Breg(AL); src+=CF; ADDB; Breg(AL) = dst; CLK(1); }
+OP80( 0x88, i_adcb ) { uint32_t src = Breg(CH), dst = Breg(AL); ADDCB; Breg(AL) = dst; CLK(1); }
+OP80( 0x89, i_adcc ) { uint32_t src = Breg(CL), dst = Breg(AL); ADDCB; Breg(AL) = dst; CLK(1); }
+OP80( 0x8a, i_adcd ) { uint32_t src = Breg(DH), dst = Breg(AL); ADDCB; Breg(AL) = dst; CLK(1); }
+OP80( 0x8b, i_adce ) { uint32_t src = Breg(DL), dst = Breg(AL); ADDCB; Breg(AL) = dst; CLK(1); }
+OP80( 0x8c, i_adch ) { uint32_t src = Breg(BH), dst = Breg(AL); ADDCB; Breg(AL) = dst; CLK(1); }
+OP80( 0x8d, i_adcl ) { uint32_t src = Breg(BL), dst = Breg(AL); ADDCB; Breg(AL) = dst; CLK(1); }
+OP80( 0x8e, i_adcm ) { uint32_t src = GetMemB(DS0, Wreg(BW)), dst = Breg(AL); ADDCB; Breg(AL) = dst; CLK(1); }
+OP80( 0x8f, i_adca ) { uint32_t src = Breg(AL), dst = Breg(AL); ADDCB; Breg(AL) = dst; CLK(1); }
OP80( 0x90, i_subb ) { uint32_t src = Breg(CH), dst = Breg(AL); SUBB; Breg(AL) = dst; CLK(1); }
OP80( 0x91, i_subc ) { uint32_t src = Breg(CL), dst = Breg(AL); SUBB; Breg(AL) = dst; CLK(1); }
OP80( 0x92, i_subd ) { uint32_t src = Breg(DH), dst = Breg(AL); SUBB; Breg(AL) = dst; CLK(1); }
@@ -149,14 +149,14 @@ OP80( 0x94, i_subh ) { uint32_t src = Breg(BH), dst = Breg(AL); SUBB; Breg(AL)
OP80( 0x95, i_subl ) { uint32_t src = Breg(BL), dst = Breg(AL); SUBB; Breg(AL) = dst; CLK(1); }
OP80( 0x96, i_subm ) { uint32_t src = GetMemB(DS0, Wreg(BW)), dst = Breg(AL); SUBB; Breg(AL) = dst; CLK(1); }
OP80( 0x97, i_suba ) { uint32_t src = Breg(AL), dst = Breg(AL); SUBB; Breg(AL) = dst; CLK(1); }
-OP80( 0x98, i_sbbb ) { uint32_t src = Breg(CH), dst = Breg(AL); src+=CF; SUBB; Breg(AL) = dst; CLK(1); }
-OP80( 0x99, i_sbbc ) { uint32_t src = Breg(CL), dst = Breg(AL); src+=CF; SUBB; Breg(AL) = dst; CLK(1); }
-OP80( 0x9a, i_sbbd ) { uint32_t src = Breg(DH), dst = Breg(AL); src+=CF; SUBB; Breg(AL) = dst; CLK(1); }
-OP80( 0x9b, i_sbbe ) { uint32_t src = Breg(DL), dst = Breg(AL); src+=CF; SUBB; Breg(AL) = dst; CLK(1); }
-OP80( 0x9c, i_sbbh ) { uint32_t src = Breg(BH), dst = Breg(AL); src+=CF; SUBB; Breg(AL) = dst; CLK(1); }
-OP80( 0x9d, i_sbbl ) { uint32_t src = Breg(BL), dst = Breg(AL); src+=CF; SUBB; Breg(AL) = dst; CLK(1); }
-OP80( 0x9e, i_sbbm ) { uint32_t src = GetMemB(DS0, Wreg(BW)), dst = Breg(AL); src+=CF; SUBB; Breg(AL) = dst; CLK(1); }
-OP80( 0x9f, i_sbba ) { uint32_t src = Breg(AL), dst = Breg(AL); src+=CF; SUBB; Breg(AL) = dst; CLK(1); }
+OP80( 0x98, i_sbbb ) { uint32_t src = Breg(CH), dst = Breg(AL); SUBBB; Breg(AL) = dst; CLK(1); }
+OP80( 0x99, i_sbbc ) { uint32_t src = Breg(CL), dst = Breg(AL); SUBBB; Breg(AL) = dst; CLK(1); }
+OP80( 0x9a, i_sbbd ) { uint32_t src = Breg(DH), dst = Breg(AL); SUBBB; Breg(AL) = dst; CLK(1); }
+OP80( 0x9b, i_sbbe ) { uint32_t src = Breg(DL), dst = Breg(AL); SUBBB; Breg(AL) = dst; CLK(1); }
+OP80( 0x9c, i_sbbh ) { uint32_t src = Breg(BH), dst = Breg(AL); SUBBB; Breg(AL) = dst; CLK(1); }
+OP80( 0x9d, i_sbbl ) { uint32_t src = Breg(BL), dst = Breg(AL); SUBBB; Breg(AL) = dst; CLK(1); }
+OP80( 0x9e, i_sbbm ) { uint32_t src = GetMemB(DS0, Wreg(BW)), dst = Breg(AL); SUBBB; Breg(AL) = dst; CLK(1); }
+OP80( 0x9f, i_sbba ) { uint32_t src = Breg(AL), dst = Breg(AL); SUBBB; Breg(AL) = dst; CLK(1); }
OP80( 0xa0, i_anab ) { uint32_t src = Breg(CH), dst = Breg(AL); ANDB; Breg(AL) = dst; CLK(1); }
OP80( 0xa1, i_anac ) { uint32_t src = Breg(CL), dst = Breg(AL); ANDB; Breg(AL) = dst; CLK(1); }
OP80( 0xa2, i_anad ) { uint32_t src = Breg(DH), dst = Breg(AL); ANDB; Breg(AL) = dst; CLK(1); }
@@ -202,7 +202,7 @@ OP80( 0xc9, i_ret ) { POP80(m_ip); CHANGE_PC; CLK(1); } //0xd9
OP80( 0xca, i_jz ) { uint32_t addr = fetchword(); if (ZF) { m_ip = addr; CHANGE_PC; } CLK(1); }
OP80( 0xcc, i_cz ) { uint32_t addr = fetchword(); if (ZF) { PUSH80(m_ip); m_ip = addr; CHANGE_PC; } CLK(1); }
OP80( 0xcd, i_call ) { uint32_t addr = fetchword(); PUSH80(m_ip); m_ip = addr; CHANGE_PC; CLK(1); } // 0xdd, 0xfd
-OP80( 0xce, i_aci ) { uint32_t src = fetch(), dst = Breg(AL); src+=CF; ADDB; Breg(AL) = dst; CLK(1); }
+OP80( 0xce, i_aci ) { uint32_t src = fetch(), dst = Breg(AL); ADDCB; Breg(AL) = dst; CLK(1); }
OP80( 0xcf, i_rst1 ) { PUSH80(m_ip); m_ip = 8; CHANGE_PC; CLK(1); }
OP80( 0xd0, i_rnc ) { if (!CF) { POP80(m_ip); CHANGE_PC; } CLK(1); }
OP80( 0xd1, i_popd ) { POP80(Wreg(DW)); }
@@ -216,7 +216,7 @@ OP80( 0xd8, i_rc ) { if (CF) { POP80(m_ip); CHANGE_PC; } CLK(1); }
OP80( 0xda, i_jc ) { uint32_t addr = fetchword(); if (CF) { m_ip = addr; CHANGE_PC; } CLK(1); }
OP80( 0xdb, i_in ) { uint8_t port = fetch(); Breg(AL) = read_port_byte(port); CLK(1); }
OP80( 0xdc, i_cc ) { uint32_t addr = fetchword(); if (CF) { PUSH80(m_ip); m_ip = addr; CHANGE_PC; } CLK(1); }
-OP80( 0xde, i_sbi ) { uint32_t src = fetch(), dst = Breg(AL); src+=CF; SUBB; Breg(AL) = dst; CLK(1); }
+OP80( 0xde, i_sbi ) { uint32_t src = fetch(), dst = Breg(AL); SUBBB; Breg(AL) = dst; CLK(1); }
OP80( 0xdf, i_rst3 ) { PUSH80(m_ip); m_ip = 0x18; CHANGE_PC; CLK(1); }
OP80( 0xe0, i_rpo ) { if (!PF) { POP80(m_ip); CHANGE_PC; } CLK(1); }
OP80( 0xe1, i_poph ) { POP80(Wreg(BW)); }
diff --git a/src/devices/cpu/nec/necinstr.hxx b/src/devices/cpu/nec/necinstr.hxx
index f19e777027a..a8b598c93c3 100644
--- a/src/devices/cpu/nec/necinstr.hxx
+++ b/src/devices/cpu/nec/necinstr.hxx
@@ -284,21 +284,21 @@ OP( 0x0f, i_pre_nec ) { uint32_t ModRM, tmp, tmp2;
}
}
-OP( 0x10, i_adc_br8 ) { DEF_br8; src+=CF; ADDB; PutbackRMByte(ModRM,dst); CLKM(2,2,2,16,16,7); }
-OP( 0x11, i_adc_wr16 ) { DEF_wr16; src+=CF; ADDW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,m_EA);}
-OP( 0x12, i_adc_r8b ) { DEF_r8b; src+=CF; ADDB; RegByte(ModRM)=dst; CLKM(2,2,2,11,11,6); }
-OP( 0x13, i_adc_r16w ) { DEF_r16w; src+=CF; ADDW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,m_EA); }
-OP( 0x14, i_adc_ald8 ) { DEF_ald8; src+=CF; ADDB; Breg(AL)=dst; CLKS(4,4,2); }
-OP( 0x15, i_adc_axd16) { DEF_axd16; src+=CF; ADDW; Wreg(AW)=dst; CLKS(4,4,2); }
+OP( 0x10, i_adc_br8 ) { DEF_br8; ADDCB; PutbackRMByte(ModRM,dst); CLKM(2,2,2,16,16,7); }
+OP( 0x11, i_adc_wr16 ) { DEF_wr16; ADDCW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,m_EA);}
+OP( 0x12, i_adc_r8b ) { DEF_r8b; ADDCB; RegByte(ModRM)=dst; CLKM(2,2,2,11,11,6); }
+OP( 0x13, i_adc_r16w ) { DEF_r16w; ADDCW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,m_EA); }
+OP( 0x14, i_adc_ald8 ) { DEF_ald8; ADDCB; Breg(AL)=dst; CLKS(4,4,2); }
+OP( 0x15, i_adc_axd16) { DEF_axd16; ADDCW; Wreg(AW)=dst; CLKS(4,4,2); }
OP( 0x16, i_push_ss ) { PUSH(Sreg(SS)); CLKS(12,8,3); }
OP( 0x17, i_pop_ss ) { POP(Sreg(SS)); CLKS(12,8,5); m_no_interrupt=1; }
-OP( 0x18, i_sbb_br8 ) { DEF_br8; src+=CF; SUBB; PutbackRMByte(ModRM,dst); CLKM(2,2,2,16,16,7); }
-OP( 0x19, i_sbb_wr16 ) { DEF_wr16; src+=CF; SUBW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,m_EA);}
-OP( 0x1a, i_sbb_r8b ) { DEF_r8b; src+=CF; SUBB; RegByte(ModRM)=dst; CLKM(2,2,2,11,11,6); }
-OP( 0x1b, i_sbb_r16w ) { DEF_r16w; src+=CF; SUBW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,m_EA); }
-OP( 0x1c, i_sbb_ald8 ) { DEF_ald8; src+=CF; SUBB; Breg(AL)=dst; CLKS(4,4,2); }
-OP( 0x1d, i_sbb_axd16) { DEF_axd16; src+=CF; SUBW; Wreg(AW)=dst; CLKS(4,4,2); }
+OP( 0x18, i_sbb_br8 ) { DEF_br8; SUBBB; PutbackRMByte(ModRM,dst); CLKM(2,2,2,16,16,7); }
+OP( 0x19, i_sbb_wr16 ) { DEF_wr16; SUBBW; PutbackRMWord(ModRM,dst); CLKR(24,24,11,24,16,7,2,m_EA);}
+OP( 0x1a, i_sbb_r8b ) { DEF_r8b; SUBBB; RegByte(ModRM)=dst; CLKM(2,2,2,11,11,6); }
+OP( 0x1b, i_sbb_r16w ) { DEF_r16w; SUBBW; RegWord(ModRM)=dst; CLKR(15,15,8,15,11,6,2,m_EA); }
+OP( 0x1c, i_sbb_ald8 ) { DEF_ald8; SUBBB; Breg(AL)=dst; CLKS(4,4,2); }
+OP( 0x1d, i_sbb_axd16) { DEF_axd16; SUBBW; Wreg(AW)=dst; CLKS(4,4,2); }
OP( 0x1e, i_push_ds ) { PUSH(Sreg(DS0)); CLKS(12,8,3); }
OP( 0x1f, i_pop_ds ) { POP(Sreg(DS0)); CLKS(12,8,5); }
@@ -443,8 +443,8 @@ OP( 0x80, i_80pre ) { uint32_t dst, src; GetModRM; dst = GetRMByte(ModRM); src
switch (ModRM & 0x38) {
case 0x00: ADDB; PutbackRMByte(ModRM,dst); break;
case 0x08: ORB; PutbackRMByte(ModRM,dst); break;
- case 0x10: src+=CF; ADDB; PutbackRMByte(ModRM,dst); break;
- case 0x18: src+=CF; SUBB; PutbackRMByte(ModRM,dst); break;
+ case 0x10: ADDCB; PutbackRMByte(ModRM,dst); break;
+ case 0x18: SUBBB; PutbackRMByte(ModRM,dst); break;
case 0x20: ANDB; PutbackRMByte(ModRM,dst); break;
case 0x28: SUBB; PutbackRMByte(ModRM,dst); break;
case 0x30: XORB; PutbackRMByte(ModRM,dst); break;
@@ -457,8 +457,8 @@ OP( 0x81, i_81pre ) { uint32_t dst, src; GetModRM; dst = GetRMWord(ModRM); src
switch (ModRM & 0x38) {
case 0x00: ADDW; PutbackRMWord(ModRM,dst); break;
case 0x08: ORW; PutbackRMWord(ModRM,dst); break;
- case 0x10: src+=CF; ADDW; PutbackRMWord(ModRM,dst); break;
- case 0x18: src+=CF; SUBW; PutbackRMWord(ModRM,dst); break;
+ case 0x10: ADDCW; PutbackRMWord(ModRM,dst); break;
+ case 0x18: SUBBW; PutbackRMWord(ModRM,dst); break;
case 0x20: ANDW; PutbackRMWord(ModRM,dst); break;
case 0x28: SUBW; PutbackRMWord(ModRM,dst); break;
case 0x30: XORW; PutbackRMWord(ModRM,dst); break;
@@ -471,8 +471,8 @@ OP( 0x82, i_82pre ) { uint32_t dst, src; GetModRM; dst = GetRMByte(ModRM); src
switch (ModRM & 0x38) {
case 0x00: ADDB; PutbackRMByte(ModRM,dst); break;
case 0x08: ORB; PutbackRMByte(ModRM,dst); break;
- case 0x10: src+=CF; ADDB; PutbackRMByte(ModRM,dst); break;
- case 0x18: src+=CF; SUBB; PutbackRMByte(ModRM,dst); break;
+ case 0x10: ADDCB; PutbackRMByte(ModRM,dst); break;
+ case 0x18: SUBBB; PutbackRMByte(ModRM,dst); break;
case 0x20: ANDB; PutbackRMByte(ModRM,dst); break;
case 0x28: SUBB; PutbackRMByte(ModRM,dst); break;
case 0x30: XORB; PutbackRMByte(ModRM,dst); break;
@@ -485,8 +485,8 @@ OP( 0x83, i_83pre ) { uint32_t dst, src; GetModRM; dst = GetRMWord(ModRM); src
switch (ModRM & 0x38) {
case 0x00: ADDW; PutbackRMWord(ModRM,dst); break;
case 0x08: ORW; PutbackRMWord(ModRM,dst); break;
- case 0x10: src+=CF; ADDW; PutbackRMWord(ModRM,dst); break;
- case 0x18: src+=CF; SUBW; PutbackRMWord(ModRM,dst); break;
+ case 0x10: ADDCW; PutbackRMWord(ModRM,dst); break;
+ case 0x18: SUBBW; PutbackRMWord(ModRM,dst); break;
case 0x20: ANDW; PutbackRMWord(ModRM,dst); break;
case 0x28: SUBW; PutbackRMWord(ModRM,dst); break;
case 0x30: XORW; PutbackRMWord(ModRM,dst); break;
diff --git a/src/devices/cpu/nec/necmacro.h b/src/devices/cpu/nec/necmacro.h
index e6c04d6f44c..c9f1d31bb63 100644
--- a/src/devices/cpu/nec/necmacro.h
+++ b/src/devices/cpu/nec/necmacro.h
@@ -25,9 +25,15 @@
#define ADDB { uint32_t res=dst+src; SetCFB(res); SetOFB_Add(res,src,dst); SetAF(res,src,dst); SetSZPF_Byte(res); dst=(BYTE)res; }
#define ADDW { uint32_t res=dst+src; SetCFW(res); SetOFW_Add(res,src,dst); SetAF(res,src,dst); SetSZPF_Word(res); dst=(WORD)res; }
+#define ADDCB { uint32_t res=dst+src+CF; SetCFB(res); SetOFB_Add(res,src,dst); SetAF(res,src,dst); SetSZPF_Byte(res); dst=(BYTE)res; }
+#define ADDCW { uint32_t res=dst+src+CF; SetCFW(res); SetOFW_Add(res,src,dst); SetAF(res,src,dst); SetSZPF_Word(res); dst=(WORD)res; }
+
#define SUBB { uint32_t res=dst-src; SetCFB(res); SetOFB_Sub(res,src,dst); SetAF(res,src,dst); SetSZPF_Byte(res); dst=(BYTE)res; }
#define SUBW { uint32_t res=dst-src; SetCFW(res); SetOFW_Sub(res,src,dst); SetAF(res,src,dst); SetSZPF_Word(res); dst=(WORD)res; }
+#define SUBBB { uint32_t res=dst-src-CF; SetCFB(res); SetOFB_Sub(res,src,dst); SetAF(res,src,dst); SetSZPF_Byte(res); dst=(BYTE)res; }
+#define SUBBW { uint32_t res=dst-src-CF; SetCFW(res); SetOFW_Sub(res,src,dst); SetAF(res,src,dst); SetSZPF_Word(res); dst=(WORD)res; }
+
#define ORB dst|=src; m_CarryVal=m_OverVal=m_AuxVal=0; SetSZPF_Byte(dst)
#define ORW dst|=src; m_CarryVal=m_OverVal=m_AuxVal=0; SetSZPF_Word(dst)