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-rw-r--r--src/lib/netlist/examples/2n6027.cpp99
-rw-r--r--src/lib/netlist/examples/7400_astable.c36
-rw-r--r--src/lib/netlist/examples/74123_mstable.c48
-rw-r--r--src/lib/netlist/examples/74125.cpp43
-rw-r--r--src/lib/netlist/examples/7414.cpp34
-rw-r--r--src/lib/netlist/examples/9602_mstable.c54
-rw-r--r--src/lib/netlist/examples/bjt.c47
-rw-r--r--src/lib/netlist/examples/bjt_eb.c45
-rw-r--r--src/lib/netlist/examples/bjt_eb_pnp.c36
-rw-r--r--src/lib/netlist/examples/cccs.cpp40
-rw-r--r--src/lib/netlist/examples/cd4066.c47
-rw-r--r--src/lib/netlist/examples/cdelay.c55
-rw-r--r--src/lib/netlist/examples/cmos_inverter.cpp50
-rw-r--r--src/lib/netlist/examples/cmos_inverter_clk.cpp64
-rw-r--r--src/lib/netlist/examples/cmos_inverter_rs.cpp136
-rw-r--r--src/lib/netlist/examples/congo_bongo.cpp511
-rw-r--r--src/lib/netlist/examples/congo_bongo.csv21
-rw-r--r--src/lib/netlist/examples/cs.cpp28
-rw-r--r--src/lib/netlist/examples/diode.c32
-rw-r--r--src/lib/netlist/examples/lm3900_test.cpp104
-rw-r--r--src/lib/netlist/examples/lostfound.cpp218
-rw-r--r--src/lib/netlist/examples/mm5837_noise.c39
-rw-r--r--src/lib/netlist/examples/msx_mixer_stage.c66
-rw-r--r--src/lib/netlist/examples/ne555_astable.c54
-rw-r--r--src/lib/netlist/examples/ne566.cpp35
-rw-r--r--src/lib/netlist/examples/nld_74393_test.c27
-rw-r--r--src/lib/netlist/examples/nmos_fet.cpp55
-rw-r--r--src/lib/netlist/examples/noise.cpp37
-rw-r--r--src/lib/netlist/examples/norton_opamp.c129
-rw-r--r--src/lib/netlist/examples/opamp.c190
-rw-r--r--src/lib/netlist/examples/opamp_amplification_curve.cpp95
-rw-r--r--src/lib/netlist/examples/rc.c32
-rw-r--r--src/lib/netlist/examples/rl.c33
-rw-r--r--src/lib/netlist/examples/sn74ls629_osc.c36
-rw-r--r--src/lib/netlist/examples/test.c88
-rw-r--r--src/lib/netlist/examples/todo.c143
-rw-r--r--src/lib/netlist/examples/turkey_shoot.cpp214
-rw-r--r--src/lib/netlist/examples/turkey_shoot.csv256
-rw-r--r--src/lib/netlist/examples/vccs.c31
-rw-r--r--src/lib/netlist/examples/vccs1.c36
-rw-r--r--src/lib/netlist/examples/vs_cs.c53
-rw-r--r--src/lib/netlist/examples/zdiode.cpp46
42 files changed, 3443 insertions, 0 deletions
diff --git a/src/lib/netlist/examples/2n6027.cpp b/src/lib/netlist/examples/2n6027.cpp
new file mode 100644
index 00000000000..8585ace3ae6
--- /dev/null
+++ b/src/lib/netlist/examples/2n6027.cpp
@@ -0,0 +1,99 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+
+#include "netlist/devices/net_lib.h"
+
+/*
+ * Run with
+ * ./nltool -t 1 -f nl_examples/2N6027.cpp -l PUT.A -l PUT.K -l PUT.G -v
+ */
+
+/* ----------------------------------------------------------------------------
+ * Library section header START
+ * ---------------------------------------------------------------------------*/
+
+#ifndef __PLIB_PREPROCESSOR__
+
+#define PUT_2N6027(_name) \
+ NET_REGISTER_DEV(G501534_DIP, _name)
+
+//NETLIST_EXTERNAL(ex2N6027)
+NETLIST_EXTERNAL(loc_lib)
+
+#endif
+
+/* ----------------------------------------------------------------------------
+ * Library section header END
+ * ---------------------------------------------------------------------------*/
+
+NETLIST_START(ex2N6027)
+{
+
+ SOLVER(Solver, 48000)
+ PARAM(Solver.DYNAMIC_TS, 1)
+ PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 1e-9)
+ PARAM(Solver.METHOD, "MAT_CR")
+
+ LOCAL_SOURCE(loc_lib)
+ INCLUDE(loc_lib)
+
+ ANALOG_INPUT(VB, 10)
+
+ PUT_2N6027(PUT)
+
+ // Figure 3 from datasheet
+ RES(R1, RES_K(510))
+ RES(R2, RES_K(16))
+ RES(R3, RES_K(27))
+ RES(R4, 20)
+ CAP(C, CAP_U(0.1))
+
+ NET_C(VB, R1.1, R2.1)
+ NET_C(R1.2, C.1, PUT.A)
+ NET_C(PUT.K, R4.1)
+ NET_C(PUT.G, R2.2, R3.1)
+
+ NET_C(GND, C.2, R4.2, R3.2)
+
+}
+
+
+NETLIST_START(PUT_2N6027)
+{
+
+ NET_MODEL("2N6027_NPN NPN(IS=5E-15 VAF=100 IKF=0.3 ISE=1.85E-12 NE=1.45 RE=0.15 RC=0.15 CJE=7E-10 TF=0.6E-8 CJC=2.2E-10 TR=4.76E-8 XTB=3)")
+ NET_MODEL("2N6027_PNP PNP(IS=2E-15 VAF=100 IKF=0.3 ISE=1.90E-12 NE=1.5 RE=0.15 RC=0.15 CJE=7E-10 TF=1.6E-8 CJC=2.2E-10 TR=5.1E-8 XTB=3)")
+
+ QBJT_EB(Q1, "2N6027_NPN")
+ QBJT_EB(Q2, "2N6027_PNP")
+
+ /* The netlist transistor model currently doesn't support
+ * BE and BC capacitances.
+ * Adding those here significantly reduces NR loops.
+ * FIXME: Needs to be removed when added to the
+ * transistor EB model.
+ */
+#if 0
+ CAP(CJE1, CAP_N(1))
+ CAP(CJE2, CAP_N(1))
+
+ NET_C(CJE1.1, Q1.B)
+ NET_C(CJE1.2, Q1.E)
+ NET_C(CJE2.1, Q2.B)
+ NET_C(CJE2.2, Q2.E)
+#endif
+ NET_C(Q1.C, Q2.B)
+ NET_C(Q1.B, Q2.C)
+
+ ALIAS(G, Q2.B)
+ ALIAS(A, Q2.E)
+ ALIAS(K, Q1.E)
+
+}
+
+NETLIST_START(loc_lib)
+{
+
+ LOCAL_LIB_ENTRY(PUT_2N6027)
+
+}
diff --git a/src/lib/netlist/examples/7400_astable.c b/src/lib/netlist/examples/7400_astable.c
new file mode 100644
index 00000000000..207444568ea
--- /dev/null
+++ b/src/lib/netlist/examples/7400_astable.c
@@ -0,0 +1,36 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * 7400_astable.c
+ *
+ */
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(7400_astable)
+{
+
+ /*
+ * Astable multivibrator using two 7400 gates (or inverters)
+ *
+ */
+
+ /* Standard stuff */
+
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-5)
+
+ // astable NAND Multivibrator ==> f ~ 1.0 / (3 * R * C)
+ RES(R1, 4700)
+ CAP(C1, 0.22e-6)
+ TTL_7400_NAND(n1,R1.1,R1.1)
+ TTL_7400_NAND(n2,R1.2,R1.2)
+ NET_C(n1.Q, R1.2)
+ NET_C(n2.Q, C1.1)
+ NET_C(C1.2, R1.1)
+
+ LOG(logC12, C1.2)
+ LOG(logn1Q, n1.Q)
+ LOG(logn2Q, n2.Q)
+
+}
diff --git a/src/lib/netlist/examples/74123_mstable.c b/src/lib/netlist/examples/74123_mstable.c
new file mode 100644
index 00000000000..a6572920537
--- /dev/null
+++ b/src/lib/netlist/examples/74123_mstable.c
@@ -0,0 +1,48 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * 74123_mstable.c
+ *
+ */
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(74123_mstable)
+{
+
+ /*
+ * Monoflog
+ *
+ */
+
+ /* Standard stuff */
+
+ SOLVER(Solver, 48000)
+
+ ANALOG_INPUT(V5, 5) // 5V
+
+ /* Wiring up the 74123 */
+
+ CLOCK(clk, 50)
+ TTL_74123(mf)
+
+ RES(R, 10000)
+ CAP(C, 1e-6)
+
+ NET_C(GND, mf.GND)
+ NET_C(V5, mf.VCC)
+
+ NET_C(C.1, mf.C)
+ NET_C(mf.C, GND)
+ NET_C(C.2, mf.RC, R.2)
+ NET_C(R.1, V5)
+
+ NET_C(mf.CLRQ, V5)
+ NET_C(mf.B, V5)
+ NET_C(mf.A, clk.Q)
+
+ LOG(log_C, C.2)
+ LOG(log_Q, mf.Q)
+ LOG(log_X, clk.Q)
+
+}
diff --git a/src/lib/netlist/examples/74125.cpp b/src/lib/netlist/examples/74125.cpp
new file mode 100644
index 00000000000..48e443ccab0
--- /dev/null
+++ b/src/lib/netlist/examples/74125.cpp
@@ -0,0 +1,43 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+
+/*
+ * 74125.cpp
+ *
+ */
+
+//! [74125_example]
+#include "netlist/devices/net_lib.h"
+
+// ./nltool -c run -l RL.1 src/lib/netlist/examples/74125.cpp
+// RL.1 : Output
+
+NETLIST_START(main)
+{
+
+ SOLVER(Solver, 48000) // could be 1 in this example
+
+ ANALOG_INPUT(VCC, 5.0)
+
+ TTL_74125_GATE(X1)
+ TTL_74126_GATE(X2)
+ PARAM(X2.FORCE_TRISTATE_LOGIC, 0)
+
+ CLOCK(C1, 100)
+ CLOCK(C2, 300)
+ CLOCK(C3, 5)
+
+ RES(RL, 1000)
+
+ NET_C(C1.Q, X1.A)
+ NET_C(C2.Q, X2.A)
+ NET_C(C3.Q, X1.GQ, X2.G)
+
+ NET_C(X1.Y, X2.Y, RL.1)
+ //NET_C(X1.Y, RL.1)
+
+ NET_C(GND, RL.2, C1.GND, C2.GND, C3.GND, X1.GND, X2.GND)
+ NET_C(VCC, C1.VCC, C2.VCC, C3.VCC, X1.VCC, X2.VCC)
+
+}
+//! [74125_example]
diff --git a/src/lib/netlist/examples/7414.cpp b/src/lib/netlist/examples/7414.cpp
new file mode 100644
index 00000000000..1efc836fcd5
--- /dev/null
+++ b/src/lib/netlist/examples/7414.cpp
@@ -0,0 +1,34 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * 7414.c
+ *
+ */
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(7414_astable)
+{
+
+ /*
+ * Simple oscillator with 74LS14
+ *
+ * ./nltool -f nl_examples/7414.cpp -l C37.1 -l U4A1.Q
+ *
+ */
+
+ /* Standard stuff */
+
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-8)
+
+ TTL_74LS14_GATE(U4A1)
+ //TTL_7404_GATE(U4A1)
+ RES(R39, 2200)
+ CAP(C37, CAP_U(1))
+ NET_C(U4A1.A, R39.2, C37.1)
+ NET_C(GND, C37.2)
+ NET_C(GND, U4A1.GND)
+ NET_C(R39.1, U4A1.Q)
+
+}
diff --git a/src/lib/netlist/examples/9602_mstable.c b/src/lib/netlist/examples/9602_mstable.c
new file mode 100644
index 00000000000..46388dca3bc
--- /dev/null
+++ b/src/lib/netlist/examples/9602_mstable.c
@@ -0,0 +1,54 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * 9602_mstable.c
+ *
+ */
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(74123_mstable)
+{
+
+ /*
+ * Monoflog
+ *
+ */
+
+ /* Standard stuff */
+
+ SOLVER(Solver, 48000)
+
+ ANALOG_INPUT(V5, 5) // 5V
+
+ /* Wiring up the 74123 */
+
+ CLOCK(clk, 50)
+ TTL_9602_DIP(mf)
+
+ RES(R, 10000)
+ CAP(C, 1e-6)
+
+ NET_C(GND, mf.8) //
+ NET_C(V5, mf.16) //
+
+ NET_C(C.1, mf.1)
+ NET_C(mf.1, GND) // Test - can be removed
+ NET_C(C.2, mf.2, R.2)
+ NET_C(R.1, V5)
+
+ NET_C(mf.3, V5) // CLR
+ NET_C(mf.4, GND) // B
+ NET_C(mf.5, clk.Q) // A
+
+ LOG(logC, C.2)
+ LOG(logQ, mf.6) //Q
+ LOG(logX, clk.Q)
+
+ // avoid non connected inputs
+
+ NET_C(mf.11, V5)
+ NET_C(mf.12, V5)
+ NET_C(mf.13, V5)
+
+}
diff --git a/src/lib/netlist/examples/bjt.c b/src/lib/netlist/examples/bjt.c
new file mode 100644
index 00000000000..082049640a8
--- /dev/null
+++ b/src/lib/netlist/examples/bjt.c
@@ -0,0 +1,47 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * bjt.c
+ *
+ */
+
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(bjt)
+{
+ /* Standard stuff */
+
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 48000)
+ ANALOG_INPUT(V5, 5)
+ ANALOG_INPUT(V3, 3.5)
+
+ /* NPN - example */
+
+ QBJT_SW(Q, "BC237B")
+ RES(RB, 1000)
+ RES(RC, 1000)
+
+ NET_C(RC.1, V5)
+ NET_C(RC.2, Q.C)
+ NET_C(RB.1, clk)
+ NET_C(RB.2, Q.B)
+ NET_C(Q.E, GND)
+
+ /* PNP - example */
+
+ QBJT_SW(Q1, "BC556B")
+ RES(RB1, 1000)
+ RES(RC1, 1000)
+
+ NET_C(RC1.1, GND)
+ NET_C(RC1.2, Q1.C)
+ NET_C(RB1.1, clk)
+ NET_C(RB1.2, Q1.B)
+ NET_C(Q1.E, V3)
+
+ LOG(logB, Q.B)
+ LOG(logC, Q.C)
+
+}
diff --git a/src/lib/netlist/examples/bjt_eb.c b/src/lib/netlist/examples/bjt_eb.c
new file mode 100644
index 00000000000..dd681e5ac1a
--- /dev/null
+++ b/src/lib/netlist/examples/bjt_eb.c
@@ -0,0 +1,45 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * bjt.c
+ *
+ */
+
+
+#include "netlist/devices/net_lib.h"
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(bjt)
+{
+ /* Standard stuff */
+
+ CLOCK(clk, 10000) // 10000 Hz
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-6)
+ PARAM(Solver.RESCHED_LOOPS, 30)
+ ANALOG_INPUT(V5, 5)
+ ANALOG_INPUT(V3, 3.5)
+
+ /* NPN - example */
+
+ QBJT_EB(Q, "BC237B")
+ RES(RB, 1000)
+ RES(RC, 1000)
+
+ NET_C(RC.1, V5)
+ NET_C(RC.2, Q.C)
+ NET_C(RB.1, clk)
+ //NET_C(RB.1, V3)
+ NET_C(RB.2, Q.B)
+ NET_C(Q.E, GND)
+
+ // put some load on Q.C
+
+ RES(RCE, 150000)
+ NET_C(RCE.1, Q.C)
+ NET_C(RCE.2, GND)
+
+ //LOG(logB, Q.B)
+ //LOG(logC, Q.C)
+
+}
diff --git a/src/lib/netlist/examples/bjt_eb_pnp.c b/src/lib/netlist/examples/bjt_eb_pnp.c
new file mode 100644
index 00000000000..875f47623ab
--- /dev/null
+++ b/src/lib/netlist/examples/bjt_eb_pnp.c
@@ -0,0 +1,36 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * bjt.c
+ *
+ */
+
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(bjt)
+{
+ /* Standard stuff */
+
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 48000)
+ ANALOG_INPUT(V5, 5)
+ ANALOG_INPUT(V3, 3.5)
+
+ /* PNP - example */
+
+ QBJT_EB(Q1, "BC556B")
+ RES(RB1, 1000)
+ RES(RC1, 1000)
+
+ NET_C(RC1.1, GND)
+ NET_C(RC1.2, Q1.C)
+ NET_C(RB1.1, clk)
+ NET_C(RB1.2, Q1.B)
+ NET_C(Q1.E, V3)
+
+ LOG(logA, clk)
+ LOG(logB, Q1.B)
+ LOG(logC, Q1.C)
+
+}
diff --git a/src/lib/netlist/examples/cccs.cpp b/src/lib/netlist/examples/cccs.cpp
new file mode 100644
index 00000000000..709493c619e
--- /dev/null
+++ b/src/lib/netlist/examples/cccs.cpp
@@ -0,0 +1,40 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * cccs.cpp
+ *
+ */
+
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(cccs)
+{
+
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-12)
+ PARAM(Solver.METHOD, "MAT_CR")
+
+ ANALOG_INPUT(V5,5)
+ CCCS(VV, 0.9)
+ PARAM(VV.RI, 1e-3)
+
+ RES(R2, 1000)
+ RES(R1, 1000)
+
+ NET_C(V5, clk.VCC)
+ NET_C(clk, VV.IP)
+ NET_C(VV.IN, R1.1)
+ NET_C(GND, R1.2, R2.2, VV.OP, clk.GND)
+
+ NET_C(R2.1, VV.ON)
+
+ /* Simple current source */
+
+ CS(CS1, 1)
+ RES(R3, 1)
+ NET_C(R3.1, CS1.P)
+ NET_C(GND, CS1.N, R3.2)
+
+}
diff --git a/src/lib/netlist/examples/cd4066.c b/src/lib/netlist/examples/cd4066.c
new file mode 100644
index 00000000000..bba0a5c298e
--- /dev/null
+++ b/src/lib/netlist/examples/cd4066.c
@@ -0,0 +1,47 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * bjt.c
+ *
+ */
+
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(cd4066)
+{
+ /* Standard stuff */
+
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 48000)
+
+ ANALOG_INPUT(V5, 5)
+
+ CD_4066_DIP(SW)
+ RES(R1, 1000)
+
+ NET_C(SW.7, GND)
+ NET_C(SW.14, V5)
+
+ NET_C(SW.13, clk)
+ NET_C(SW.1, V5)
+
+ NET_C(SW.2, R1.1)
+ NET_C(R1.2, GND)
+
+ // ground anything else
+
+ NET_C(SW.3, GND)
+ NET_C(SW.4, GND)
+ NET_C(SW.5, GND)
+ NET_C(SW.6, GND)
+ NET_C(SW.8, GND)
+ NET_C(SW.9, GND)
+ NET_C(SW.10, GND)
+ NET_C(SW.11, GND)
+ NET_C(SW.12, GND)
+
+ LOG(logB, clk)
+ LOG(logC, R1.1)
+
+}
diff --git a/src/lib/netlist/examples/cdelay.c b/src/lib/netlist/examples/cdelay.c
new file mode 100644
index 00000000000..87bf184aa16
--- /dev/null
+++ b/src/lib/netlist/examples/cdelay.c
@@ -0,0 +1,55 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * cdelay.c
+ *
+ */
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(perf)
+{
+
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-20)
+ MAINCLOCK(clk, 50000000)
+
+ TTL_7400_NAND(n1,clk,clk)
+
+}
+
+#ifndef P_FREQ
+#define P_FREQ 4800
+#endif
+
+#ifndef P_DTS
+#define P_DTS 1
+#endif
+
+NETLIST_START(cap_delay)
+{
+
+ /*
+ * delay circuit
+ *
+ */
+
+ /* Standard stuff */
+
+ SOLVER(Solver, P_FREQ)
+ PARAM(Solver.ACCURACY, 1e-20)
+ PARAM(Solver.DYNAMIC_TS, P_DTS)
+ PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 1e-6)
+ CLOCK(clk, 5000)
+
+ TTL_7400_NAND(n1,clk,clk)
+ CAP(C, 1e-6)
+ NET_C(n1.Q, C.2)
+ NET_C(GND, C.1)
+ TTL_7400_NAND(n2,n1.Q, n1.Q)
+
+ LOG(logclk, clk)
+ LOG(logn1Q, C.2)
+ LOG(logn2Q, n1.Q)
+
+}
diff --git a/src/lib/netlist/examples/cmos_inverter.cpp b/src/lib/netlist/examples/cmos_inverter.cpp
new file mode 100644
index 00000000000..3db470744b7
--- /dev/null
+++ b/src/lib/netlist/examples/cmos_inverter.cpp
@@ -0,0 +1,50 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * bjt.c
+ *
+ */
+
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(cmos_inverter)
+{
+ /* Standard stuff */
+
+ //EXTERNAL_SOURCE(modules_lib)
+
+ //INCLUDE(modules_lib)
+
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-7)
+ PARAM(Solver.NR_LOOPS, 50)
+ PARAM(Solver.METHOD, "MAT_CR")
+ ANALOG_INPUT(V5, 5)
+
+ RTEST(X)
+ NET_C(X.1, V5)
+ NET_C(X.2, GND)
+
+ VS(IN, 5)
+ PARAM(IN.FUNC, "T * 5")
+
+ MOSFET(P, "PMOS(VTO=-1.0 KP=2e-3 LAMBDA=2E-2)")
+ MOSFET(M, "NMOS(VTO=1.0 KP=2e-3 LAMBDA=2E-2)")
+
+ NET_C(P.S, V5)
+ NET_C(P.D, M.D)
+ NET_C(GND, M.S, IN.N)
+
+ NET_C(IN.P, M.G, P.G)
+
+ // capacitance over D - S
+#if 0
+ CAP(C, CAP_N(1))
+ NET_C(M.D, C.1)
+ NET_C(M.S, C.2)
+#endif
+ LOG(log_G, M.G)
+ LOG(log_D, M.D)
+
+}
diff --git a/src/lib/netlist/examples/cmos_inverter_clk.cpp b/src/lib/netlist/examples/cmos_inverter_clk.cpp
new file mode 100644
index 00000000000..d913e8f6d6b
--- /dev/null
+++ b/src/lib/netlist/examples/cmos_inverter_clk.cpp
@@ -0,0 +1,64 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * cmos_inverter_clk
+ *
+ */
+
+
+#include "netlist/devices/net_lib.h"
+
+#define USE_CLOCK (1)
+
+NETLIST_START(cmos_inverter_clk)
+{
+ /* Standard stuff */
+
+ //SOLVER(Solver, 480000)
+ SOLVER(Solver, 1e5)
+ //SOLVER(Solver, 100000000000)
+ PARAM(Solver.ACCURACY, 1e-6 )
+ PARAM(Solver.NR_LOOPS, 50)
+ PARAM(Solver.DYNAMIC_TS, 1)
+ PARAM(Solver.DYNAMIC_LTE, 1e-5)
+ PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 2e-6)
+ ANALOG_INPUT(V5, 5)
+
+// CLOCK(clk, 0.5e6)
+
+#if (USE_CLOCK)
+ CLOCK(V, 5000)
+ PARAM(NETLIST.DEFAULT_MOS_CAPMODEL, 2) // Disable capacitance modeling
+ //CLOCK(V, 500000)
+#else
+ VS(V, 5)
+ PARAM(V.FUNC, "T * 5e6")
+#endif
+
+ MOSFET(P, "PMOS(VTO=-0.5 GAMMA=0.5 TOX=20n)")
+ MOSFET(M, "NMOS(VTO=0.5 GAMMA=0.5 TOX=20n)")
+ RES(RG, 1)
+
+ NET_C(P.S, V5)
+ NET_C(P.D, M.D)
+#if (USE_CLOCK)
+ NET_C(GND, M.S)
+ NET_C(V.Q, RG.1)
+#else
+ NET_C(GND, M.S, V.N)
+ NET_C(V.P, RG.1)
+#endif
+ NET_C(RG.2, M.G, P.G)
+
+ // capacitance over D - S
+#if 0
+ CAP(C, CAP_N(1))
+ NET_C(M.D, C.1)
+ NET_C(M.S, C.2)
+#endif
+#if 1
+ LOG(log_G, M.G)
+ LOG(log_D, M.D)
+ LOGD(log_X, RG.1, RG.2)
+#endif
+}
diff --git a/src/lib/netlist/examples/cmos_inverter_rs.cpp b/src/lib/netlist/examples/cmos_inverter_rs.cpp
new file mode 100644
index 00000000000..86a84e2e8fa
--- /dev/null
+++ b/src/lib/netlist/examples/cmos_inverter_rs.cpp
@@ -0,0 +1,136 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * bjt.c
+ *
+ */
+
+#include "netlist/devices/net_lib.h"
+
+// Run this with ... ./nltool -c run -t 1 -n cmos_inverter ../examples/cmos_inverter_dk.cpp
+
+static NETLIST_START(CD4069_ANALOG_GATE)
+{
+
+ //MOSFET(P, "PMOS(VTO=-1.0 KP=2e-3 LAMBDA=2E-2)")
+ //MOSFET(M, "NMOS(VTO=1.0 KP=2e-3 LAMBDA=2E-2)")
+ // https://www.youtube.com/watch?v=jayFN7XqPJw
+ MOSFET(P, "PMOS(VTO=-1.22 KP=0.044 LAMBDA=0.05 GAMMA=0.25 L=4.22e-6 W=30e-6)")
+ MOSFET(M, "NMOS(VTO=1.22 KP=0.044 LAMBDA=0.05 GAMMA=0.25 L=4.22e-6 W=30e-6)")
+
+ ALIAS(VDD, P.S)
+ ALIAS(VSS, M.S)
+ ALIAS(Q, M.D)
+ ALIAS(A, M.G)
+
+#if 0
+ // No real difference
+ DIODE(D1, "1N4148")
+ NET_C(D1.K, A)
+ NET_C(D1.A, VSS)
+
+ DIODE(D2, "1N4148")
+ NET_C(D2.A, A)
+ NET_C(D2.K, VDD)
+#endif
+ NET_C(P.D, M.D)
+ NET_C(M.G, P.G)
+
+}
+
+//- Identifier: CD4069_ANALOG_DIP
+//- Title: CD4069UBM/CD4069UBC Inverter Circuits
+//- Pinalias: A1,Y1,A2,Y2,A3,Y3,VSS,Y4,A4,Y5,A5,Y6,A6,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/150/206783_DS.pdf
+//-
+//- This uses two NMOS/PMOS transistors to model
+// the input to output voltage transfer function.
+//
+static NETLIST_START(CD4069_ANALOG_DIP)
+{
+ CD4069_ANALOG_GATE(A)
+ CD4069_ANALOG_GATE(B)
+ CD4069_ANALOG_GATE(C)
+ CD4069_ANALOG_GATE(D)
+ CD4069_ANALOG_GATE(E)
+ CD4069_ANALOG_GATE(F)
+
+ NET_C(A.VDD, B.VDD, C.VDD, D.VDD, E.VDD, F.VDD)
+ NET_C(A.VSS, B.VSS, C.VSS, D.VSS, E.VSS, F.VSS)
+
+ DIPPINS( /* +--------------+ */
+ A.A, /* A1 |1 ++ 14| VDD */ A.VDD,
+ A.Q, /* Y1 |2 13| A6 */ F.A,
+ B.A, /* A2 |3 12| Y6 */ F.Q,
+ B.Q, /* Y2 |4 4069 11| A5 */ E.A,
+ C.A, /* A3 |5 10| Y5 */ E.Q,
+ C.Q, /* Y3 |6 9| A4 */ D.A,
+ A.VSS, /* VSS |7 8| Y4 */ D.Q
+ /* +--------------+ */
+ )
+}
+
+NETLIST_START(cmos_inverter)
+{
+ /* Standard stuff */
+
+ //EXTERNAL_SOURCE(modules_lib)
+
+ //INCLUDE(modules_lib)
+
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-7)
+ PARAM(Solver.NR_LOOPS, 50)
+ PARAM(Solver.METHOD, "MAT_CR")
+ ANALOG_INPUT(V5, 5)
+
+ RTEST(X)
+ NET_C(X.1, V5)
+ NET_C(X.2, GND)
+
+ LOCAL_LIB_ENTRY(CD4069_ANALOG_GATE)
+ //SUBMODEL(CD4069_ANALOG_GATE, GATE)
+ CD4069_ANALOG_GATE(G1)
+ CD4069_ANALOG_GATE(G2)
+ CD4069_ANALOG_GATE(G3)
+
+ NET_C(V5, G1.VDD, G2.VDD, G3.VDD)
+ NET_C(GND, G1.VSS, G2.VSS, G3.VSS)
+
+ RES(R1, 18000)
+ RES(R2, 3300000)
+ CAP(C, CAP_U(10)) // is 20!
+ NET_C(G1.Q, G2.A)
+ NET_C(G2.Q, G3.A, C.1)
+ NET_C(G3.Q, R1.1)
+ NET_C(C.2, R1.2, R2.1)
+ NET_C(R2.2, G1.A)
+
+ RES(R47,10000)
+ RES(R46,1000)
+ RES(R48,2000) // is 1000!, but assume 50:50 on modulated signal
+ CAP(C45, CAP_U(22))
+ QBJT_EB(Q,"2SC1815")
+ NET_C(G1.Q, R47.1)
+ NET_C(R47.2, Q.B)
+ NET_C(V5, Q.C)
+ NET_C(R46.1, Q.E)
+ NET_C(R46.2, C45.1)
+ NET_C(R48.1, C45.1)
+ NET_C(GND, C45.2, R48.2)
+
+
+ // capacitance over D - S
+#if 0
+ CAP(C, CAP_N(1))
+ NET_C(M.D, C.1)
+ NET_C(M.S, C.2)
+#endif
+ //LOG(log_G, IN.P)
+ //LOG(log_D, G1.Q)
+ LOG(log_D, C45.1)
+
+}
diff --git a/src/lib/netlist/examples/congo_bongo.cpp b/src/lib/netlist/examples/congo_bongo.cpp
new file mode 100644
index 00000000000..50f265601b0
--- /dev/null
+++ b/src/lib/netlist/examples/congo_bongo.cpp
@@ -0,0 +1,511 @@
+// license:CC0-1.0
+// copyright-holders:Andrew Gardner,Couriersud
+
+#include "netlist/devices/net_lib.h"
+
+/* ----------------------------------------------------------------------------
+ * Define
+ * ---------------------------------------------------------------------------*/
+
+/* set to 1 to use optimizations increasing performance significantly */
+
+#ifndef USE_OPTIMOPTIMIZATIONS
+#define USE_OPTIMIZATIONS 1
+#endif
+
+#ifndef USE_FRONTIERS
+#define USE_FRONTIERS 1
+#endif
+
+/* ----------------------------------------------------------------------------
+ * Library section header START
+ * ---------------------------------------------------------------------------*/
+
+#ifndef __PLIB_PREPROCESSOR__
+
+#define G501534_DIP(_name) \
+ NET_REGISTER_DEV_X(G501534_DIP, _name)
+
+NETLIST_EXTERNAL(congob_lib)
+
+#endif
+
+/* ----------------------------------------------------------------------------
+ * Library section header END
+ * ---------------------------------------------------------------------------*/
+
+
+NETLIST_START(congo_bongo)
+{
+// EESCHEMA NETLIST VERSION 1.1 (SPICE FORMAT) CREATION DATE: WED 01 JUL 2015 11:09:25 PM CEST
+// TO EXCLUDE A COMPONENT FROM THE SPICE NETLIST ADD [SPICE_NETLIST_ENABLED] USER FIELD SET TO: N
+// TO REORDER THE COMPONENT SPICE NODE SEQUENCE ADD [SPICE_NODE_SEQUENCE] USER FIELD AND DEFINE SEQUENCE: 2,1,0
+// SHEET NAME:/
+// IGNORED O_AUDIO0: O_AUDIO0 64 0
+// .END
+
+ PARAM(Solver.RELTOL, 1e-2)
+ PARAM(Solver.VNTOL, 1e-6)
+ PARAM(Solver.NR_LOOPS, 30)
+ PARAM(Solver.GS_LOOPS, 99)
+ PARAM(Solver.METHOD, "MAT_CR")
+
+ //PARAM(Solver.METHOD, "GMRES")
+ //PARAM(Solver.ACCURACY, 1e-5)
+ //PARAM(Solver.METHOD, "SOR")
+
+#if USE_OPTIMIZATIONS
+ SOLVER(Solver, 48000)
+#else
+ SOLVER(Solver, 48000)
+ PARAM(Solver.DYNAMIC_TS, 1)
+ PARAM(Solver.PARALLEL, 0)
+ PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 2e-7)
+ PARAM(Solver.DYNAMIC_LTE, 1e-4)
+#endif
+
+ LOCAL_SOURCE(congob_lib)
+ INCLUDE(congob_lib)
+
+ // The following TTL_INPUTs need to be hooked up in MAME
+ // I_BASS_DRUM0, I_CONGA_H0, I_CONGA_L0, I_GORILLA0, I_RIM0
+ //
+ // 76489 outputs to ANALOG_INPUTS
+ //
+ // I_DSG4, I_DSG5
+
+ // Found here: https://hamesspam.sakura.ne.jp/hes2016/160521.html
+ NET_MODEL("1S2075 D(IS=1.387E-9 N=1.702 RS=1.53 CJO=1.92pf VJ=0.4996 M=0.0605 TT=5ns BV=75 IBV=100E-15)")
+
+ NET_MODEL("2SC1941 NPN(IS=46.416f BF=210 NF=1.0022 VAF=600 IKF=500m ISE=60f NE=1.5 BR=2.0122 NR=1.0022 VAR=10G IKR=10G ISC=300p NC=2 RB=13.22 IRB=10G RBM=13.22 RE=100m RC=790m CJE=26.52p VJE=900m MJE=518m TF=1.25n XTF=10 VTF=10 ITF=500m PTF=0 CJC=4.89p VJC=750m MJC=237m XCJC=500m TR=100n CJS=0 VJS=750m MJS=500m XTB=1.5 EG=1.11 XTI=3 KF=0 AF=1 FC=500m)")
+
+ INCLUDE(CongoBongo_schematics)
+ SUBMODEL(CongoBongo_amp, amp)
+ INCLUDE(CongoBongo_dsg)
+
+ NET_C(R94.1, SJ1)
+ NET_C(SOU1, amp.AMPIN1)
+ NET_C(GND, amp.GND)
+
+#if USE_OPTIMIZATIONS
+ /* The opamp has an UGF of about 1000k. This doesn't work here and causes oscillations.
+ * UGF here therefore about half the Solver clock.
+ */
+ PARAM(U16.B.MODEL, "MB3614(TYPE=3 UGF=22k)")
+ PARAM(U17.C.MODEL, "MB3614(TYPE=3 UGF=44k)")
+#endif
+#if USE_FRONTIERS
+ //OPTIMIZE_FRONTIER(C51.2, RES_K(47), 50)
+ //OPTIMIZE_FRONTIER(R78.2, RES_K(20), RES_K(47))
+ OPTIMIZE_FRONTIER(R77.2, RES_K(20), 50)
+
+ OPTIMIZE_FRONTIER(C25.2, RES_K(240), 50)
+ OPTIMIZE_FRONTIER(C29.2, RES_K(390), 50)
+ OPTIMIZE_FRONTIER(C37.2, RES_K(390), 50)
+ OPTIMIZE_FRONTIER(C44.2, RES_K(200), 50)
+
+ OPTIMIZE_FRONTIER(R90.2, RES_K(100), 50)
+ OPTIMIZE_FRONTIER(R92.2, RES_K(15), 50)
+
+ OPTIMIZE_FRONTIER(R19.2, RES_K(51), 50)
+#endif
+
+}
+
+NETLIST_START(CongoBongo_schematics)
+{
+
+ CAP(C20, CAP_N(68))
+ CAP(C21, CAP_U(1))
+ CAP(C22, CAP_U(47))
+ CAP(C23, CAP_N(100))
+ CAP(C24, CAP_N(100))
+ CAP(C25, CAP_U(1))
+ CAP(C26, CAP_N(68))
+ CAP(C27, CAP_N(33))
+ CAP(C28, CAP_U(47))
+ CAP(C29, CAP_U(1))
+ CAP(C30, CAP_N(33))
+ CAP(C31, CAP_N(33))
+ CAP(C32, CAP_N(68))
+ CAP(C33, CAP_N(33))
+ CAP(C34, CAP_U(47))
+ CAP(C35, CAP_N(33))
+ CAP(C36, CAP_N(33))
+ CAP(C37, CAP_U(1))
+ CAP(C38, CAP_N(10))
+ CAP(C39, CAP_N(3.300000))
+ CAP(C40, CAP_U(2.200000))
+ CAP(C41, CAP_N(6.800000))
+ CAP(C42, CAP_N(6.800000))
+ CAP(C43, CAP_N(47))
+ CAP(C44, CAP_U(1))
+ CAP(C45, CAP_U(33))
+ CAP(C46, CAP_N(100))
+ CAP(C47, CAP_P(470))
+ CAP(C48, CAP_N(1.500000))
+ CAP(C49, CAP_P(220))
+ CAP(C50, CAP_N(3.900000))
+ CAP(C51, CAP_U(1))
+ CAP(C52, CAP_U(1))
+ CAP(C53, CAP_U(1))
+ CAP(C54, CAP_U(1))
+ CAP(C55, CAP_U(1))
+ CAP(C56, CAP_U(10))
+ CAP(C57, CAP_N(47))
+ CAP(C58, CAP_N(22))
+ CAP(C59, CAP_U(10))
+ CAP(C60, CAP_N(22))
+ CAP(C61, CAP_U(1))
+ CAP(C62, CAP_N(22))
+ DIODE(D1, "1S2075")
+ DIODE(D2, "1S2075")
+ DIODE(D3, "1S2075")
+ DIODE(D4, "1S2075")
+ DIODE(D5, "1S2075")
+ DIODE(D6, "1S2075")
+ DIODE(D7, "1S2075")
+ DIODE(D8, "1S2075")
+ TTL_INPUT(I_BASS_DRUM0, 0)
+ TTL_INPUT(I_CONGA_H0, 0)
+ TTL_INPUT(I_CONGA_L0, 0)
+ TTL_INPUT(I_GORILLA0, 0)
+ TTL_INPUT(I_RIM0, 0)
+ ANALOG_INPUT(I_V12, 12)
+ ANALOG_INPUT(I_V5, 5)
+ ANALOG_INPUT(I_V6, 6)
+ QBJT_EB(Q2, "2SC1941")
+ RES(R21, RES_K(10))
+ RES(R22, RES_K(47))
+ RES(R23, RES_K(47))
+ RES(R24, RES_K(10))
+ RES(R25, RES_K(47))
+ RES(R26, RES_K(22))
+ RES(R27, RES_K(10))
+ RES(R28, RES_K(470))
+ RES(R29, RES_K(1))
+ RES(R30, RES_K(240))
+ RES(R31, RES_K(10))
+ RES(R32, RES_K(47))
+ RES(R33, RES_K(47))
+ RES(R34, RES_K(47))
+ RES(R35, RES_K(47))
+ RES(R36, RES_K(22))
+ RES(R37, RES_K(10))
+ RES(R38, RES_M(1))
+ RES(R39, 330)
+ RES(R40, RES_K(390))
+ RES(R41, RES_K(10))
+ RES(R42, RES_K(47))
+ RES(R43, RES_K(47))
+ RES(R44, RES_K(47))
+ RES(R45, RES_K(47))
+ RES(R46, RES_K(22))
+ RES(R47, RES_K(10))
+ RES(R48, RES_M(1))
+ RES(R49, 220)
+ RES(R50, RES_K(390))
+ RES(R51, RES_K(10))
+ RES(R52, RES_K(22))
+ RES(R53, RES_K(22))
+ RES(R54, RES_K(22))
+ RES(R55, RES_K(22))
+ RES(R56, RES_K(10))
+ RES(R57, RES_K(4.700000))
+ RES(R58, RES_M(1))
+ RES(R59, 470)
+ RES(R60, RES_M(2.200000))
+ RES(R61, RES_M(2.200000))
+ RES(R62, RES_K(200))
+ RES(R63, RES_K(22))
+ RES(R64, RES_K(22))
+ RES(R65, RES_K(20))
+ RES(R66, RES_K(20))
+ RES(R67, RES_K(20))
+
+ // Sallen-Key filter amplification is 1+R68/69 ~= 2
+
+ RES(R68, RES_K(20))
+ RES(R69, RES_K(20))
+ RES(R70, RES_K(100))
+ RES(R71, RES_K(150))
+ RES(R72, RES_K(330))
+ RES(R73, RES_K(1))
+ RES(R74, RES_K(1))
+ RES(R75, RES_K(470))
+ RES(R76, RES_K(10))
+ RES(R77, RES_K(20))
+ RES(R78, RES_K(47))
+ RES(R79, RES_K(22))
+ RES(R80, RES_K(20))
+ RES(R81, RES_K(10))
+ RES(R82, RES_K(100))
+ RES(R83, RES_K(51))
+ RES(R84, RES_K(51))
+ RES(R85, RES_K(51))
+ RES(R86, RES_K(51))
+ RES(R87, RES_K(100))
+ RES(R88, RES_K(2.200000))
+ RES(R89, RES_K(10))
+ RES(R90, RES_K(100))
+ RES(R91, RES_K(10))
+ RES(R92, RES_K(15))
+ RES(R93, RES_K(15))
+ RES(R94, RES_K(51))
+ MB3614_DIP(U13)
+ G501534_DIP(U15)
+ MB3614_DIP(U16)
+ MB3614_DIP(U17)
+ CD4001_DIP(U18)
+ CD4538_DIP(U19)
+ MM5837_DIP(U20)
+ //PARAM(U20.FREQ, 38000) // FIXME: after measurement
+ PARAM(U20.FREQ, 100000)
+ TTL_7416_DIP(U6)
+ NET_C(U15.3, C61.2)
+ NET_C(R89.2, R88.2, Q2.B)
+ NET_C(U16.13, U16.14, C57.1, C59.2)
+ NET_C(U16.8, U16.9, U15.13)
+ NET_C(U16.3, R86.2, I_V6.Q)
+ NET_C(U16.2, R90.1, R91.2)
+ NET_C(R89.1, D8.K)
+ NET_C(U16.1, R91.1, R92.2)
+ NET_C(U18.9, U19.6)
+ NET_C(R71.1, U19.14, C53.2)
+ NET_C(R76.1, U19.3, U19.13)
+ NET_C(R72.2, D6.A, U18.10)
+ NET_C(C51.2, R78.2)
+ NET_C(I_GORILLA0.Q, U19.5, U19.11)
+ NET_C(U17.12, C56.1, R81.2, R80.1)
+ NET_C(U17.6, U17.7, R77.2)
+ NET_C(U17.5, C55.1, R72.1, R73.1)
+ NET_C(U17.3, R83.1, R84.2)
+ NET_C(R73.2, D6.K)
+ NET_C(U17.2, R82.1, C62.2, R85.2)
+ NET_C(R92.1, C57.2, R93.2)
+ NET_C(U16.12, R93.1, C58.1)
+ NET_C(R68.2, C50.1, U17.8, C51.1)
+ NET_C(C59.1, U15.1)
+ NET_C(R68.1, R69.2, U17.9)
+ NET_C(R67.1, C49.1, U17.10)
+ NET_C(R70.1, C52.2, U19.2)
+ NET_C(R65.2, U18.4)
+ NET_C(U17.13, R78.1, R79.2, R77.1)
+ NET_C(R63.1, R64.2, C47.1, D5.A, U18.5, U18.6)
+ NET_C(R60.1, R61.2, C43.1)
+ NET_C(C40.1, R57.2, R56.1)
+ NET_C(R30.1, R40.1, R50.1, R62.1, R94.1)
+ NET_C(D7.K, R74.2)
+ NET_C(C20.2, R21.2, U6.8)
+ NET_C(GND, U13.11, C22.2, R29.2, R25.2, R23.2, R22.2, U6.1, U6.3, U6.7, C28.2, R39.2, R35.2, R33.2, R32.2, C34.2, R49.2, R45.2, R43.2, R42.2, C40.2, R59.2, R55.2, R53.2, R52.2, C43.2, R69.1, R64.1, C49.2, C48.2, C47.2, C46.1, C45.1, U17.11, C55.2, C52.1, U18.1, U18.2, U18.7, U18.12, U18.13, C54.2, U16.11, R84.1, R88.1, Q2.E, C58.2, C60.2, U20.1, U20.2, U15.4, I_GORILLA0.GND, U19.1, U19.4, U19.8, U19.12, U19.15, I_BASS_DRUM0.GND, I_CONGA_L0.GND, I_CONGA_H0.GND, I_RIM0.GND, C53.1, C56.2, R81.1)
+ NET_C(R74.1, R75.1, C54.1, U16.10)
+ NET_C(D3.K, C32.1, R42.1)
+ NET_C(U16.5, R86.1, R87.2)
+ NET_C(C24.2, C23.1, R29.1)
+ NET_C(U13.14, C25.2, C24.1, R28.1)
+ NET_C(U16.7, R87.1, D8.A, R90.2)
+ NET_C(U13.13, C23.2, R28.2)
+ NET_C(U13.12, R24.1, R26.2, R25.1)
+ NET_C(C21.1, R24.2)
+ NET_C(U18.8, U19.9)
+ NET_C(U13.8, C29.2, C31.1, R38.1)
+ NET_C(U17.1, U16.6, C62.1)
+ NET_C(U6.9, I_BASS_DRUM0.Q)
+ NET_C(U6.12, C32.2, R41.2)
+ NET_C(U13.10, R34.1, R36.2, R35.1)
+ NET_C(C39.1, R54.2)
+ NET_C(U6.10, C38.2, R51.2)
+ NET_C(R85.1, Q2.C)
+ NET_C(U13.3, R44.1, R46.2, R45.1)
+ NET_C(D1.A, C21.2, R23.1)
+ NET_C(C61.1, R94.2)
+ NET_C(U13.5, R54.1, R56.2, R55.1)
+ NET_C(U6.11, I_RIM0.Q)
+ NET_C(C33.1, R44.2)
+ NET_C(D7.A, R75.2, U19.10)
+ NET_C(C25.1, R30.2)
+ NET_C(C42.2, C41.1, R59.1)
+ NET_C(U13.6, C41.2, R58.2, R60.2)
+ NET_C(U13.7, C44.2, C42.1, R58.1, R61.1)
+ NET_C(C60.1, U15.2)
+ NET_C(U13.9, C30.2, R38.2)
+ NET_C(C44.1, R62.2)
+ NET_C(U6.5, I_CONGA_L0.Q)
+ NET_C(U6.13, I_CONGA_H0.Q)
+ NET_C(U6.14, D5.K, R70.2, R76.2, R71.2, U18.14, I_GORILLA0.VCC, U19.16, I_V5.Q, I_BASS_DRUM0.VCC, I_CONGA_L0.VCC, I_CONGA_H0.VCC, I_RIM0.VCC)
+ NET_C(U6.6, C26.2, R31.2)
+ NET_C(D2.A, C27.2, R33.1)
+ NET_C(D1.K, C20.1, R22.1)
+ NET_C(C29.1, R40.2)
+ NET_C(D2.K, C26.1, R32.1)
+ NET_C(C31.2, C30.1, R39.1)
+ NET_C(R66.1, R67.2, C50.2)
+#if 0
+ RES(XX, 1)
+ NET_C(C50.2, XX.1)
+ NET_C(R66.1, R67.2, XX.2)
+#endif
+ NET_C(R63.2, U20.3)
+ NET_C(C27.1, R34.2)
+ NET_C(C22.1, R27.2, R26.1)
+ NET_C(C28.1, R37.2, R36.1)
+ NET_C(R65.1, R66.2, C48.1)
+ NET_C(D3.A, C33.2, R43.1)
+ NET_C(U13.1, C37.2, C36.1, R48.1)
+ NET_C(C34.1, R47.2, R46.1)
+ NET_C(C37.1, R50.2)
+ NET_C(U17.14, R79.1, R82.2, R83.2)
+ NET_C(U13.2, C35.2, R48.2)
+ NET_C(U13.4, R27.1, R21.1, R37.1, R31.1, R47.1, R41.1, R57.1, R51.1, C46.2, C45.2, U17.4, U16.4, U20.4, U15.12, I_V12.Q, R80.2)
+ NET_C(C36.2, C35.1, R49.1)
+ NET_C(D4.A, C39.2, R53.1)
+ NET_C(D4.K, C38.1, R52.1)
+}
+
+NETLIST_START(CongoBongo_amp)
+{
+ // .INCLUDE "NLSPICE.LIB"
+ // .TRAN 1E-5 1
+ // .END
+ ALIAS(AMPIN1, R83.1)
+ ALIAS(AMPOUT1, R77.1)
+ ANALOG_INPUT(I_V12, 12)
+ //ANALOG_INPUT(GND, 0)
+ ALIAS(GND, C66.2)
+ CAP(C124, CAP_U(470))
+ CAP(C51, CAP_U(10))
+ CAP(C53, CAP_U(200))
+ CAP(C54, CAP_N(3.900000))
+ CAP(C55, CAP_P(220))
+ CAP(C56, CAP_N(1.500000))
+ CAP(C57, CAP_U(10))
+ CAP(C58, CAP_U(10))
+ CAP(C59, CAP_U(10))
+ CAP(C66, CAP_N(100))
+ RES(R77, RES_K(100))
+ RES(R80, RES_K(20))
+ RES(R81, RES_K(10))
+ RES(R82, RES_K(10))
+ RES(R83, RES_M(1))
+ RES(R84, RES_K(47))
+ RES(R85, RES_K(47))
+ RES(R86, RES_M(1))
+ RES(R87, RES_K(100))
+ RES(R88, RES_K(20))
+ RES(R89, RES_K(10))
+ RES(R90, RES_K(10))
+ RES(R91, RES_K(10))
+ LM324_DIP(U2)
+ POT(XVR1, 20000)
+ PARAM(XVR1.DIAL, 0.500000)
+ NET_C(R82.2, R81.1, C54.2)
+ NET_C(C51.2, R77.1)
+ NET_C(R91.2, C56.1, R82.1)
+ NET_C(R84.2, C57.1)
+ NET_C(R80.2, XVR1.1)
+ NET_C(U2.10, C55.1, R81.2)
+ NET_C(C58.2, XVR1.2)
+ NET_C(U2.8, U2.9, R80.1, C54.1)
+ NET_C(R77.2, C53.1)
+ NET_C(C66.1, U2.4, C124.1, R89.1, I_V12.Q)
+ NET_C(R83.1, R91.1)
+ //NET_C(GND, C66.2, U2.11, C124.2, C56.2, C55.2, C57.2, C59.2, R90.2, C53.2, XVR1.3)
+ NET_C(GND, U2.11, C124.2, C56.2, C55.2, C57.2, C59.2, R90.2, C53.2, XVR1.3)
+ NET_C(R83.2, U2.13, U2.14, R86.1)
+ NET_C(U2.1, R88.1, C51.1)
+ NET_C(U2.7, R85.1, R87.2)
+ NET_C(U2.3, U2.12, C59.1, R90.1, R89.2)
+ NET_C(U2.2, R87.1, R88.2)
+ NET_C(U2.5, R86.2, C58.1)
+ NET_C(U2.6, R84.1, R85.2)
+
+ RES(IN1, RES_K(50))
+ RES(IN2, RES_K(50))
+ NET_C(GND, IN1.2, IN2.2)
+ NET_C(IN1.1, R77.1)
+ NET_C(IN2.1, R77.2)
+
+}
+
+NETLIST_START(CongoBongo_dsg)
+{
+ // .INCLUDE "NLSPICE.LIB"
+ // .END
+ ALIAS(SOU1, U12.14)
+ ALIAS(SJ1, U12.13)
+ CAP(C12, CAP_N(100))
+ CAP(C13, CAP_N(100))
+ CAP(C14, CAP_U(1))
+ CAP(C15, CAP_U(1))
+ ANALOG_INPUT(I_DSG4, 0)
+ ANALOG_INPUT(I_DSG5, 0)
+ //ANALOG_INPUT(I_V12, 12)
+ //ANALOG_INPUT(I_V6, 6)
+ RES(R14, 10)
+ RES(R15, 10)
+ RES(R16, RES_K(51))
+ RES(R17, RES_K(51))
+ RES(R18, RES_K(100))
+ RES(R19, RES_K(51))
+ RES(R20, RES_K(20))
+ RES(ROU4, 150)
+ RES(ROU5, 150)
+ MB3614_DIP(U12)
+ NET_C(I_DSG4.Q, ROU4.1)
+ NET_C(R14.2, C12.1)
+ NET_C(U12.6, U12.7)
+ NET_C(R17.2, C15.1)
+ NET_C(U12.4, I_V12.Q)
+ NET_C(I_DSG5.Q, ROU5.1)
+ NET_C(GND, U12.3, U12.5, U12.11, C12.2, C13.2)
+ NET_C(U12.8, R18.1, R19.2)
+ NET_C(U12.1, U12.2)
+ NET_C(U12.14, R20.1)
+ NET_C(R15.2, C13.1)
+ NET_C(U12.9, R17.1, R16.1, R18.2)
+ NET_C(C14.2, R15.1, ROU4.2)
+ NET_C(R16.2, C14.1)
+ NET_C(U12.10, U12.12, I_V6.Q)
+ NET_C(U12.13, R19.1, R20.2)
+ NET_C(R14.1, C15.2, ROU5.2)
+}
+
+NETLIST_START(G501534_DIP)
+{
+ //AFUNC(f, 2, "A0 A1 A1 A1 * * 0.01 * *")
+ //AFUNC(f, 2, "A0")
+ //AFUNC(f, 2, "A0 6 - A1 3 pow * 0.02 * 6 +")
+ //AFUNC(f, 2, "A0 * pow(A1,3.0) * 0.02")
+ //AFUNC(f, 2, "A0 * A1 * 0.2")
+ //AFUNC(f, 2, "(A0 - 6) * max(0, A1 - 2) * 0.3 + 6")
+ AFUNC(f, 2, "(A0 - 6) * min(max(0.005, A1 - 2.3),0.3) * 2 + 6")
+
+ /*
+ * 12: VCC
+ * 4: GND
+ * 1: IN
+ * 3: OUT
+ * 13: CV
+ * 2: RDL - connected via Capacitor to ground
+ */
+
+ RES(DUMMY, RES_K(1))
+
+ RES(RO, 1000)
+
+ ALIAS(12, DUMMY.1) // VCC
+ ALIAS(4, DUMMY.2) // GND
+ ALIAS(2, DUMMY.2) // RDL
+ ALIAS(1, f.A0)
+ ALIAS(13, f.A1)
+ NET_C(f.Q, RO.1)
+ ALIAS(3, RO.2)
+
+}
+
+NETLIST_START(congob_lib)
+{
+
+ LOCAL_LIB_ENTRY(G501534_DIP)
+
+}
diff --git a/src/lib/netlist/examples/congo_bongo.csv b/src/lib/netlist/examples/congo_bongo.csv
new file mode 100644
index 00000000000..db4b9e65357
--- /dev/null
+++ b/src/lib/netlist/examples/congo_bongo.csv
@@ -0,0 +1,21 @@
+5.000,I_GORILLA0.IN,0
+5.100,I_GORILLA0.IN,1
+5.300,I_GORILLA0.IN,0
+6.000,I_BASS_DRUM0.IN,1
+6.100,I_BASS_DRUM0.IN,0
+7.000,I_CONGA_H0.IN,1
+7.100,I_CONGA_H0.IN,0
+8.000,I_CONGA_L0.IN,1
+8.100,I_CONGA_L0.IN,0
+9.000,I_RIM0.IN,1
+9.100,I_RIM0.IN,0
+10.000,I_GORILLA0.IN,1
+10.010,I_GORILLA0.IN,0
+10.500,I_GORILLA0.IN,1
+10.510,I_GORILLA0.IN,0
+11.000,I_GORILLA0.IN,1
+11.010,I_GORILLA0.IN,0
+11.500,I_GORILLA0.IN,1
+11.510,I_GORILLA0.IN,0
+12.000,I_GORILLA0.IN,1
+12.010,I_GORILLA0.IN,0
diff --git a/src/lib/netlist/examples/cs.cpp b/src/lib/netlist/examples/cs.cpp
new file mode 100644
index 00000000000..cb7ef7874d9
--- /dev/null
+++ b/src/lib/netlist/examples/cs.cpp
@@ -0,0 +1,28 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * cs.c
+ *
+ */
+
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(cs)
+{
+
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-12)
+ PARAM(Solver.METHOD, "MAT_CR")
+
+ /* Positive current flows into pin 1 of the current source
+ * Thus we observe a negative voltage on R1.1 !
+ */
+ CS(CS1, 1e-3)
+ RES(R1, 1000)
+
+ NET_C(CS1.1, R1.1)
+ NET_C(GND, CS1.2, R1.2)
+
+ LOG(log_P, R1.1)
+}
diff --git a/src/lib/netlist/examples/diode.c b/src/lib/netlist/examples/diode.c
new file mode 100644
index 00000000000..da45f8fe366
--- /dev/null
+++ b/src/lib/netlist/examples/diode.c
@@ -0,0 +1,32 @@
+/*
+ * diode.c
+ *
+ */
+
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(diode)
+{
+ /* Standard stuff */
+
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 48)
+ ANALOG_INPUT(V5, 5)
+
+ //DIODE(D, "1N914")
+ DIODE(D, "D(IS=1e-15)")
+
+ RES(R, RES_K(10))
+ RES(R1, RES_K(10))
+
+ NET_C(clk, D.K)
+ NET_C(D.A, R.1)
+ NET_C(R.2, V5)
+ NET_C(R1.2, GND)
+ NET_C(R.1, R1.1)
+
+ LOG(logB, clk)
+ LOG(logC, D.A)
+
+}
diff --git a/src/lib/netlist/examples/lm3900_test.cpp b/src/lib/netlist/examples/lm3900_test.cpp
new file mode 100644
index 00000000000..425eb36e16a
--- /dev/null
+++ b/src/lib/netlist/examples/lm3900_test.cpp
@@ -0,0 +1,104 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * Script to analyze opamp amplification as a function of frequency.
+ *
+ * ./nltool -t 0.5 -f nl_examples/LM9000_test.cpp
+ *
+ * t=0.0: 10 Hz
+ * t=0.1: 100 Hz
+ * t=0.2: 1000 Hz
+ * t=0.3: 10000 Hz
+ * t=0.4: 100000 Hz
+ * ....
+ *
+ * ./plot_nl.sh --db Y Z
+ */
+
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(main)
+{
+
+ /* Standard stuff */
+
+ //VARCLOCK(clk, "0.5 / pow(10, 1 + T * 4)")
+ //CLOCK(clk, 1000)
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-10)
+ PARAM(Solver.NR_LOOPS, 300)
+ PARAM(Solver.DYNAMIC_TS, 1)
+ PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 1e-7)
+
+ VS(vs, 0)
+ /*
+ * Having f(t)=sin(g(t)*t) the derivative becomes
+ *
+ * f'(t) = d/dt(g(t)*t) * cos(g(t)*t)
+ *
+ * w(t) = d/dt(g(t)*t) = 2*pi*freq(t) is the angular frequency at time t
+ *
+ * choosing freq(t) = pow(10, a+b*t) and integrating we get
+ *
+ * g(t)*t = 2 * pi /(b*ln(10)) * (pow(10, a+b*t)-pow(10,a))
+ */
+
+ PARAM(vs.FUNC, "0.001 * sin(0.2728752708 * (pow(10, 1 + 10*T) - 10))")
+
+ /*
+ * Stepwise ... same as above
+ */
+ //PARAM(vs.FUNC, "0.001 * sin(6.28 * pow(10, trunc((1 + T * 10)*10)/10) * T)")
+
+ /*
+ * Fixed Frequency:
+ * PARAM(vs.FUNC, "1.001 * sin(6.28 * 100 * T)")
+ */
+ PARAM(vs.R, 0.1)
+ ALIAS(clk, vs.1)
+ NET_C(vs.2, GND)
+ ANALOG_INPUT(V9, 9)
+ ANALOG_INPUT(V12, 12)
+ ANALOG_INPUT(VM12, -12)
+
+ //OPAMP(op, OPAMP_TEST)
+ LM3900(op)
+
+ NET_C(op.GND, VM12)
+ NET_C(op.VCC, V12)
+
+ /* Opamp B wired as inverting amplifier connected to output of first opamp */
+
+ RES(R1, 50)
+ RES(RP, 500000) // Set to R2 * 2 if VPlus == VCC (see datasheet)
+ RES(R2, 500000)
+
+ NET_C(op.PLUS, RP.1)
+
+ //NET_C(RP.2, V9)
+ NET_C(RP.2, GND)
+ //NET_C(RP.2, V12)
+
+ NET_C(op.MINUS, R2.2)
+ NET_C(op.MINUS, R1.2)
+
+ CAP(C, 10e-6)
+
+ NET_C(clk, C.1)
+ NET_C(C.2, R1.1)
+ NET_C(op.OUT, R2.1)
+
+ CAP(CL, 10.0e-6)
+ RES(RL, 2000)
+ NET_C(RL.2, GND)
+ NET_C(RL.1, CL.2)
+ NET_C(CL.1, op.OUT)
+
+ AFUNC(f, 1, "A0 * 1000")
+ NET_C(f.A0, RL.1)
+#if 1
+ LOG(log_Y, R1.1)
+ LOG(log_Z, f)
+#endif
+}
diff --git a/src/lib/netlist/examples/lostfound.cpp b/src/lib/netlist/examples/lostfound.cpp
new file mode 100644
index 00000000000..da9b1cca780
--- /dev/null
+++ b/src/lib/netlist/examples/lostfound.cpp
@@ -0,0 +1,218 @@
+///
+/// \file lostfound.cpp
+///
+/// This file contains various code removed from the core which may be
+/// useful again in the future or serve educational purposes.
+///
+/// Don't expect this file to compile
+
+
+/// \brief Use the truthtable implementation of 74107 instead of the coded device
+///
+/// FIXME: The truthtable implementation of 74107 (JK-Flipflop)
+/// is included for educational purposes to demonstrate how
+/// to implement state holding devices as truthtables.
+/// It will completely nuke performance for pong.
+
+#ifndef NL_USE_TRUTHTABLE_74107
+#define NL_USE_TRUTHTABLE_74107 (0)
+#endif
+
+#if (NL_USE_TRUTHTABLE_74107)
+ /*
+ * +-----+-----+-----+---++---+-----+
+ * | CLRQ| CLK | J | K || Q | QQ |
+ * +=====+=====+=====+===++===+=====+
+ * | 0 | X | X | X || 0 | 1 |
+ * | 1 | * | 0 | 0 || Q0| Q0Q |
+ * | 1 | * | 1 | 0 || 1 | 0 |
+ * | 1 | * | 0 | 1 || 0 | 1 |
+ * | 1 | * | 1 | 1 || TOGGLE |
+ * +-----+-----+-----+---++---+-----+
+ */
+ TRUTH_TABLE(TTL_74107, 6, 4, "+CLK,+J,+K,+CLRQ,@VCC,@GND")
+{
+ TT_HEAD("CLRQ, CLK, _CO, J, K,_QX | Q, QQ, CO, QX")
+ TT_LINE(" 0, 0, X, X, X, X | 0, 1, 0, 0 | 16, 25, 1, 1")
+ TT_LINE(" 0, 1, X, X, X, X | 0, 1, 1, 0 | 16, 25, 1, 1")
+
+ TT_LINE(" 1, 0, X, 0, 0, 0 | 0, 1, 0, 0 | 16, 25, 1, 1")
+ TT_LINE(" 1, 1, X, 0, 0, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
+ TT_LINE(" 1, 0, X, 0, 0, 1 | 1, 0, 0, 1 | 25, 16, 1, 1")
+ TT_LINE(" 1, 1, X, 0, 0, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
+
+ TT_LINE(" 1, 0, 1, 1, 0, X | 1, 0, 0, 1 | 25, 16, 1, 1")
+ TT_LINE(" 1, 0, 0, 1, 0, 0 | 0, 1, 0, 0 | 16, 25, 1, 1")
+ TT_LINE(" 1, 0, 0, 1, 0, 1 | 1, 0, 0, 1 | 25, 16, 1, 1")
+ TT_LINE(" 1, 1, X, 1, 0, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
+ TT_LINE(" 1, 1, X, 1, 0, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
+
+ TT_LINE(" 1, 0, 1, 0, 1, X | 0, 1, 0, 0 | 16, 25, 1, 1")
+ TT_LINE(" 1, 0, 0, 0, 1, 0 | 0, 1, 0, 0 | 16, 25, 1, 1")
+ TT_LINE(" 1, 0, 0, 0, 1, 1 | 1, 0, 0, 1 | 25, 16, 1, 1")
+ TT_LINE(" 1, 1, X, 0, 1, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
+ TT_LINE(" 1, 1, X, 0, 1, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
+
+ // Toggle
+ TT_LINE(" 1, 0, 0, 1, 1, 0 | 0, 1, 0, 0 | 16, 25, 1, 1")
+ TT_LINE(" 1, 0, 0, 1, 1, 1 | 1, 0, 0, 1 | 25, 16, 1, 1")
+ TT_LINE(" 1, 1, 0, 1, 1, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
+ TT_LINE(" 1, 1, 0, 1, 1, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
+ TT_LINE(" 1, 1, 1, 1, 1, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
+ TT_LINE(" 1, 1, 1, 1, 1, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
+
+ TT_LINE(" 1, 0, 1, 1, 1, 1 | 0, 1, 0, 0 | 16, 25, 1, 1")
+ TT_LINE(" 1, 0, 1, 1, 1, 0 | 1, 0, 0, 1 | 25, 16, 1, 1")
+ }
+#endif
+
+/// \brief Use the truthtable implementation of 7448 instead of the coded device
+///
+/// FIXME: Using truthtable is a lot slower than the explicit device
+/// in breakout. Performance drops by 20%. This can be fixed by
+/// setting param USE_DEACTIVATE for the device.
+
+#ifndef NL_USE_TRUTHTABLE_7448
+#define NL_USE_TRUTHTABLE_7448 (0)
+#endif
+
+#if (NL_USE_TRUTHTABLE_7448)
+ TRUTH_TABLE(TTL_7448, 7, 7, "+A,+B,+C,+D,+LTQ,+BIQ,+RBIQ,@VCC,@GND")
+{
+ TT_HEAD(" LTQ,BIQ,RBIQ, A , B , C , D | a, b, c, d, e, f, g")
+
+ TT_LINE(" 1, 1, 1, 0, 0, 0, 0 | 1, 1, 1, 1, 1, 1, 0|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 1, 0, 0, 0 | 0, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 0, 1, 0, 0 | 1, 1, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 1, 1, 0, 0 | 1, 1, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 0, 0, 1, 0 | 0, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 1, 0, 1, 0 | 1, 0, 1, 1, 0, 1, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 0, 1, 1, 0 | 0, 0, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 1, 1, 1, 0 | 1, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 0, 0, 0, 1 | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 1, 0, 0, 1 | 1, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 0, 1, 0, 1 | 0, 0, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 1, 1, 0, 1 | 0, 0, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 0, 0, 1, 1 | 0, 1, 0, 0, 0, 1, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 1, 0, 1, 1 | 1, 0, 0, 1, 0, 1, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 0, 1, 1, 1 | 0, 0, 0, 1, 1, 1, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 1, 1, 1, 1 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100")
+
+ // BI/RBO is input output. In the next case it is used as an input will go low.
+ TT_LINE(" 1, 1, 0, 0, 0, 0, 0 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // RBI
+
+ TT_LINE(" 0, 1, X, X, X, X, X | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100") // LT
+
+ // This condition has precedence
+ TT_LINE(" X, 0, X, X, X, X, X | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // BI
+ TT_FAMILY("74XX")
+
+ }
+
+ // FIXME: We need a more elegant solution than defining twice
+ TRUTH_TABLE(TTL_7448_TT, 7, 7, "")
+{
+ TT_HEAD(" LTQ,BIQ,RBIQ, A , B , C , D | a, b, c, d, e, f, g")
+
+ TT_LINE(" 1, 1, 1, 0, 0, 0, 0 | 1, 1, 1, 1, 1, 1, 0|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 1, 0, 0, 0 | 0, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 0, 1, 0, 0 | 1, 1, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 1, 1, 0, 0 | 1, 1, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 0, 0, 1, 0 | 0, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 1, 0, 1, 0 | 1, 0, 1, 1, 0, 1, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 0, 1, 1, 0 | 0, 0, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 1, 1, 1, 0 | 1, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 0, 0, 0, 1 | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 1, 0, 0, 1 | 1, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 0, 1, 0, 1 | 0, 0, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 1, 1, 0, 1 | 0, 0, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 0, 0, 1, 1 | 0, 1, 0, 0, 0, 1, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 1, 0, 1, 1 | 1, 0, 0, 1, 0, 1, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 0, 1, 1, 1 | 0, 0, 0, 1, 1, 1, 1|100,100,100,100,100,100,100")
+ TT_LINE(" 1, 1, X, 1, 1, 1, 1 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100")
+
+ // BI/RBO is input output. In the next case it is used as an input will go low.
+ TT_LINE(" 1, 1, 0, 0, 0, 0, 0 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // RBI
+
+ TT_LINE(" 0, 1, X, X, X, X, X | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100") // LT
+
+ // This condition has precedence
+ TT_LINE(" X, 0, X, X, X, X, X | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // BI
+ TT_FAMILY("74XX")
+
+ }
+
+#endif
+
+// This is an experimental approach to implement the analog switch.
+// This will make the switch a 3 terminal element which is completely
+// being dealt with as part as the linear system.
+//
+// The intention was to improve convergence when the switch is in a feedback
+// loop. One example are two-opamp tridiagonal wave generators.
+// Unfortunately the approach did not work out and in addition was performing
+// far worse than the net-separating original code.
+//
+// FIXME: The transfer function needs review
+//
+NETLIB_OBJECT(CD4066_GATE_DYNAMIC)
+{
+ NETLIB_CONSTRUCTOR_MODEL(CD4066_GATE_DYNAMIC, "CD4XXX")
+ , m_R(*this, "R", NETLIB_DELEGATE(analog_input_changed))
+ , m_DUM1(*this, "_DUM1", NETLIB_DELEGATE(analog_input_changed))
+ , m_DUM2(*this, "_DUM2", NETLIB_DELEGATE(analog_input_changed))
+ , m_base_r(*this, "BASER", nlconst::magic(270.0))
+ , m_last(*this, "m_last", false)
+ , m_supply(*this)
+ {
+ register_sub_alias("CTL", m_DUM1.P());
+
+ connect(m_DUM1.P(), m_DUM2.P());
+ connect(m_DUM1.N(), m_R.P());
+ connect(m_DUM2.N(), m_R.N());
+ }
+
+ NETLIB_RESETI()
+ {
+ // Start in off condition
+ // FIXME: is ROFF correct?
+ }
+
+ NETLIB_UPDATE_TERMINALSI()
+ {
+ nl_fptype sup = (m_supply.VCC().Q_Analog() - m_supply.GND().Q_Analog());
+ nl_fptype in = m_DUM1.P().net().Q_Analog() - m_supply.GND().Q_Analog();
+ nl_fptype rON = m_base_r() * nlconst::magic(5.0) / sup;
+ nl_fptype R = std::exp(-(in / sup - nlconst::magic(0.55)) * nlconst::magic(25.0)) + rON;
+ nl_fptype G = plib::reciprocal(R);
+ // dI/dVin = (VR1-VR2)*(1.0/sup*b) * exp((Vin/sup-a) * b)
+ const auto dfdz = nlconst::magic(25.0)/(R*sup) * m_R.deltaV();
+ const auto Ieq = dfdz * in;
+ const auto zero(nlconst::zero());
+ m_R.set_mat( G, -G, zero,
+ -G, G, zero);
+ //VIN VR1
+ m_DUM1.set_mat( zero, zero, zero, // IIN
+ dfdz, zero, Ieq); // IR1
+ m_DUM2.set_mat( zero, zero, zero, // IIN
+ -dfdz, zero, -Ieq); // IR2
+ }
+ NETLIB_IS_DYNAMIC(true)
+
+private:
+
+ NETLIB_HANDLERI(analog_input_changed)
+ {
+ m_R.solve_now();
+ }
+
+ analog::nld_twoterm m_R;
+ analog::nld_twoterm m_DUM1;
+ analog::nld_twoterm m_DUM2;
+ param_fp_t m_base_r;
+ state_var<bool> m_last;
+ nld_power_pins m_supply;
+};
+
+// NETLIB_DEVICE_IMPL(CD4066_GATE_DYNAMIC, "CD4066_GATE_DYNAMIC", "")
+
diff --git a/src/lib/netlist/examples/mm5837_noise.c b/src/lib/netlist/examples/mm5837_noise.c
new file mode 100644
index 00000000000..86c0b1cd415
--- /dev/null
+++ b/src/lib/netlist/examples/mm5837_noise.c
@@ -0,0 +1,39 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * mm5837_noise.c
+ *
+ */
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(ne555_astable)
+{
+
+ /*
+ * Astable ne555
+ *
+ */
+
+ /* Standard stuff */
+
+ SOLVER(Solver, 48000)
+
+ ANALOG_INPUT(V12, 12) // 5V
+
+ /* Wiring up the ne555 */
+
+ // astable NE555, 1.13 ms period
+
+ MM5837_DIP(NOISE)
+
+ RES(R, 10000)
+
+ NET_C(NOISE.1, NOISE.2, R.2, GND)
+ NET_C(NOISE.4, V12)
+
+ NET_C(NOISE.3, R.1)
+
+ LOG(log3, NOISE.3)
+
+}
diff --git a/src/lib/netlist/examples/msx_mixer_stage.c b/src/lib/netlist/examples/msx_mixer_stage.c
new file mode 100644
index 00000000000..e9ff145fcad
--- /dev/null
+++ b/src/lib/netlist/examples/msx_mixer_stage.c
@@ -0,0 +1,66 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * bjt.c
+ *
+ */
+
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(msx)
+{
+ /* The BJT is used as an amplifier. RESCHED_LOOPS must be relatively high to
+ * allow Newton-Raphson to finish. */
+
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-5)
+ //PARAM(Solver.CONVERG, 0.3)
+ PARAM(Solver.GS_LOOPS, 50)
+
+ RES(RAY8910, 2345) // Max Voltage
+
+ ANALOG_INPUT(V5, 5)
+ ANALOG_INPUT(V12, 12)
+
+ ANALOG_INPUT(SOUND, 5)
+ ANALOG_INPUT(SND, 5)
+
+ NET_MODEL("ss9014 NPN(is=2.87599e-14 bf=377.5 vaf=123 ikf=1.1841 ise=4.7863e-15 ne=1.5 br=4.79 var=11.29 ikr=0.275423 isc=1.44544e-14 nc=1.5 rb=200 irb=1e-5 rbm=10 re=0.56 rc=5 cje=1.7205e-11 vje=0.6905907 mje=0.3193434 tf=5.89463e-10 cjc=6.2956p vjc=0.4164212 mjc=0.2559546 xcjc=0.451391 xtb=1.8881 eg=1.2415 xti=3 fc=0.5 Vceo=45 Icrating=0.1 mfg=Fairchild)")
+
+ RES(R24, RES_K(51))
+ RES(R23, RES_K(5))
+ RES(R21, RES_K(51))
+ RES(R20, RES_K(1))
+ RES(R9, RES_K(10))
+ RES(R8, 330)
+
+ CAP(C55, CAP_U(5)) // Guessed
+
+ //NET_C(RAY8910.1, SND)
+ NET_C(RAY8910.1, clk)
+
+ //NET_C(C55.1, SOUND)
+ NET_C(C55.1, V5)
+ NET_C(C55.2, R24.1)
+ NET_C(R24.2, R23.2)
+ NET_C(R23.1, RAY8910.2)
+ NET_C(R23.1, R20.1)
+ NET_C(R20.2, GND)
+
+ NET_C(R21.1, V5)
+ NET_C(R21.2, R23.2)
+
+ QBJT_EB(T2, "ss9014")
+
+ NET_C(R9.1, V12)
+ NET_C(R9.2, T2.C)
+ NET_C(R21.2, T2.B)
+ NET_C(R8.1, T2.E)
+ NET_C(R8.2, GND)
+
+ //LOG(logB, T2.B)
+ LOG(logC, T2.C)
+
+}
diff --git a/src/lib/netlist/examples/ne555_astable.c b/src/lib/netlist/examples/ne555_astable.c
new file mode 100644
index 00000000000..c4fa454af65
--- /dev/null
+++ b/src/lib/netlist/examples/ne555_astable.c
@@ -0,0 +1,54 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+
+/*
+ * ne555_astable.c
+ *
+ */
+
+//! [ne555_example]
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(ne555_astable)
+{
+
+ /*
+ * Astable ne555
+ *
+ */
+
+ /* Standard stuff */
+
+ SOLVER(Solver, 48000)
+
+ ANALOG_INPUT(V5, 5) // 5V
+
+ /* Wiring up the ne555 */
+
+ // astable NE555, 1.13 ms period
+
+ RES(RA, 5000)
+ RES(RB, 3000)
+ CAP(C, 0.15e-6)
+ NE555(555)
+
+ NET_C(GND, 555.GND)
+ NET_C(V5, 555.VCC)
+ NET_C(V5, 555.RESET)
+
+ NET_C(RA.1, 555.VCC)
+ NET_C(RA.2, 555.DISCH)
+
+ NET_C(RB.1, 555.DISCH)
+ NET_C(RB.2, 555.TRIG)
+
+ NET_C(RB.2, 555.THRESH)
+
+ NET_C(555.TRIG, C.1)
+ NET_C(C.2, GND)
+
+ LOG(log2, C.1)
+ LOG(log3, 555.OUT)
+
+}
+//! [ne555_example]
diff --git a/src/lib/netlist/examples/ne566.cpp b/src/lib/netlist/examples/ne566.cpp
new file mode 100644
index 00000000000..f238308c501
--- /dev/null
+++ b/src/lib/netlist/examples/ne566.cpp
@@ -0,0 +1,35 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+
+/*
+ * ne566.cpp
+ *
+ */
+
+//! [ne566_example]
+#include "netlist/devices/net_lib.h"
+
+// ./nltool -t 1 -l X.3 -l X.4 -n oscillator src/lib/netlist/examples/ne566.cpp
+// X.3 : Square out
+// X.4 : Triangle out
+
+NETLIST_START(oscillator)
+{
+
+ SOLVER(Solver, 48000)
+
+ ANALOG_INPUT(I_V12, 12.0)
+
+ ANALOG_INPUT(I_VC, 11.9 - 0.2)
+
+ NE566_DIP(X)
+
+ RES(R1, 10000) // ~20 Hz.
+ CAP(C1, 1e-6)
+ NET_C(I_V12, R1.1, X.8)
+ NET_C(R1.2, X.6)
+ NET_C(I_VC, X.5)
+ NET_C(GND, X.1, C1.2)
+ NET_C(C1.1, X.7)
+}
+//! [ne566_example]
diff --git a/src/lib/netlist/examples/nld_74393_test.c b/src/lib/netlist/examples/nld_74393_test.c
new file mode 100644
index 00000000000..6b954b65ccf
--- /dev/null
+++ b/src/lib/netlist/examples/nld_74393_test.c
@@ -0,0 +1,27 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * cdelay.c
+ *
+ */
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(perf)
+{
+
+ SOLVER(Solver, 48000)
+
+ ANALOG_INPUT(V5, 5)
+
+ CLOCK(CLK, 100) // clock for driving the 74393
+ CLOCK(CLK2, 3) // off-beat clock for master reset
+ TTL_74393_DIP(TESTCHIP)
+
+ NET_C(V5, CLK.VCC, CLK2.VCC, TESTCHIP.14)
+ NET_C(GND, CLK.GND, CLK2.GND, TESTCHIP.7)
+
+ NET_C(CLK, TESTCHIP.1, TESTCHIP.13)
+ NET_C(CLK2, TESTCHIP.2, TESTCHIP.12)
+
+}
diff --git a/src/lib/netlist/examples/nmos_fet.cpp b/src/lib/netlist/examples/nmos_fet.cpp
new file mode 100644
index 00000000000..8ee91c97fc3
--- /dev/null
+++ b/src/lib/netlist/examples/nmos_fet.cpp
@@ -0,0 +1,55 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * nmos_fet.cpp
+ *
+ */
+
+
+#include "netlist/devices/net_lib.h"
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(nmos)
+{
+ /* Standard stuff */
+
+ CLOCK(clk, 100) // 100 Hz
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-9)
+ PARAM(Solver.NR_LOOPS, 50000)
+ PARAM(Solver.DYNAMIC_TS, 1)
+ PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 1e-9)
+ ANALOG_INPUT(V5, 5)
+ ANALOG_INPUT(V3, 3.5)
+
+ /* NMOS - example */
+
+ NET_MODEL("MM NMOS(VTO=1.0 KP=2e-3 LAMBDA=2E-2)")
+ MOSFET(M, "MM")
+
+ RES(RB, 1000)
+ RES(RC, 10000)
+
+ NET_C(RC.1, V5)
+ NET_C(RC.2, M.D)
+ NET_C(RB.1, clk)
+ //NET_C(RB.1, V3)
+ NET_C(RB.2, M.G)
+ NET_C(M.S, GND)
+
+ // put some load on M.D
+
+ RES(RCE, 150000)
+ NET_C(RCE.1, M.D)
+ NET_C(RCE.2, GND)
+
+ // capacitance over G - S
+
+ CAP(C, CAP_N(1))
+ NET_C(M.D, C.1)
+ NET_C(M.S, C.2)
+
+ LOG(log_G, M.G)
+ LOG(log_D, M.D)
+
+}
diff --git a/src/lib/netlist/examples/noise.cpp b/src/lib/netlist/examples/noise.cpp
new file mode 100644
index 00000000000..282f9bce343
--- /dev/null
+++ b/src/lib/netlist/examples/noise.cpp
@@ -0,0 +1,37 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+
+/*
+ * noise.cpp
+ *
+ */
+
+//! [noise_example]
+#include "netlist/devices/net_lib.h"
+
+// ./nltool -t 1 -l R1.2 -n noise src/lib/netlist/examples/noise.cpp
+// X.3 : Square out
+// X.4 : Triangle out
+
+NETLIST_START(noise)
+{
+
+ SOLVER(Solver, 48000)
+
+ CLOCK(nclk, 2000)
+
+ SYS_NOISE_MT_U(noise, 2.5)
+
+ RES(R1,1000)
+ RES(R2,1000)
+
+ ANALOG_INPUT(VP, 12.0)
+
+ NET_C(nclk.Q, noise.I)
+ NET_C(VP, R1.1, nclk.VCC)
+ NET_C(noise.1, R1.2)
+ NET_C(noise.2, R2.1)
+ NET_C(GND, R2.2, nclk.GND)
+
+}
+//! [noise_example]
diff --git a/src/lib/netlist/examples/norton_opamp.c b/src/lib/netlist/examples/norton_opamp.c
new file mode 100644
index 00000000000..cf9c55622b2
--- /dev/null
+++ b/src/lib/netlist/examples/norton_opamp.c
@@ -0,0 +1,129 @@
+/*
+ * opamp.c
+ *
+ */
+
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(main)
+{
+
+ /* Standard stuff */
+
+ CLOCK(clk, 10000) // 1000 Hz
+ SOLVER(Solver, 48000)
+ ANALOG_INPUT(V5, 5)
+ PARAM(Solver.ACCURACY, 1e-6)
+ PARAM(Solver.DYNAMIC_TS, 0)
+ PARAM(Solver.SOR_FACTOR, 1.0)
+ //PARAM(Solver.CONVERG, 1.0)
+ PARAM(Solver.GS_LOOPS, 5)
+
+ SUBMODEL(op1, opamp_fast)
+ /* Wired as non - inverting amplifier like in LM3900 datasheet */
+
+ RES(R1, 25000)
+ RES(R2, 100000)
+ RES(R3, 200000)
+ CAP(C1, CAP_U(0.05))
+
+ NET_C(clk, C1.1)
+ NET_C(C1.2, R1.1)
+
+ NET_C(op1.VM, GND)
+ NET_C(op1.VP, V5 )
+ NET_C(op1.PLUS, R1.2, R3.1)
+ NET_C(R3.2, V5)
+ //NET_C(R3.2, GND)
+ NET_C(op1.MINUS, R2.2)
+ NET_C(op1.OUT, R2.1)
+
+ RES(RL, 10000)
+ NET_C(RL.2, GND)
+ NET_C(RL.1, op1.OUT)
+
+ LOG(logX, op1.OUT)
+ LOG(logY, clk)
+}
+
+NETLIST_START(opamp)
+{
+
+ /* Opamp model from
+ *
+ * http://www.ecircuitcenter.com/Circuits/opmodel1/opmodel1.htm
+ *
+ * Bandwidth 10Mhz
+ *
+ */
+
+ /* Terminal definitions for calling netlists */
+
+ ALIAS(PLUS, G1.IP) // Positive input
+ ALIAS(MINUS, G2.IN) // Negative input
+ ALIAS(OUT, EBUF.OP) // Opamp output ...
+ ALIAS(VM, EBUF.ON) // V- terminal
+ ALIAS(VP, DUMMY.I) // V+ terminal
+
+ DUMMY_INPUT(DUMMY)
+
+ /* The opamp model */
+
+ CCCS(G1)
+ CCCS(G2)
+ //PARAM(G1.G, 100) // typical OP-AMP amplification 100 * 1000 = 100000
+ PARAM(G1.G, 1000000) // typical OP-AMP amplification 100 * 1000 = 100000
+ PARAM(G2.G, 1000000) // typical OP-AMP amplification 100 * 1000 = 100000
+ RES(RP1, 1000)
+ CAP(CP1, 1.59e-6) // <== change to 1.59e-3 for 10Khz bandwidth
+ VCVS(EBUF)
+ PARAM(EBUF.RO, 50)
+ PARAM(EBUF.G, 1)
+
+// NET_C(EBUF.ON, GND)
+
+ NET_C(G1.ON, GND)
+ NET_C(G2.ON, GND)
+ NET_C(RP1.2, GND)
+ NET_C(CP1.2, GND)
+ NET_C(EBUF.IN, GND)
+
+ NET_C(G1.IN, G2.IP, GND)
+
+ NET_C(RP1.1, G1.OP)
+ NET_C(RP1.1, G2.OP)
+ NET_C(CP1.1, RP1.1)
+ NET_C(EBUF.IP, RP1.1)
+
+}
+
+NETLIST_START(opamp_fast)
+{
+
+ /*
+ * Fast norton opamp model without bandwidth
+ */
+
+ /* Terminal definitions for calling netlists */
+
+ ALIAS(PLUS, R1.1) // Positive input
+ ALIAS(MINUS, R2.1) // Negative input
+ ALIAS(OUT, G1.OP) // Opamp output ...
+ ALIAS(VM, G1.ON) // V- terminal
+ ALIAS(VP, DUMMY.I) // V+ terminal
+
+ DUMMY_INPUT(DUMMY)
+
+ /* The opamp model */
+
+ RES(R1, 1)
+ RES(R2, 1)
+ NET_C(R1.1, G1.IP)
+ NET_C(R2.1, G1.IN)
+ NET_C(R1.2, R2.2, G1.ON)
+ VCVS(G1)
+ PARAM(G1.G, 1000000)
+ PARAM(G1.RO, RES_K(8))
+
+}
diff --git a/src/lib/netlist/examples/opamp.c b/src/lib/netlist/examples/opamp.c
new file mode 100644
index 00000000000..2075aa28531
--- /dev/null
+++ b/src/lib/netlist/examples/opamp.c
@@ -0,0 +1,190 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * opamp.c
+ *
+ */
+
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(main)
+{
+
+ /* Standard stuff */
+
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 480000)
+ PARAM(Solver.ACCURACY, 1e-10)
+ PARAM(Solver.NR_LOOPS, 30000 )
+ //PARAM(Solver.CONVERG, 1.0)
+ PARAM(Solver.GS_LOOPS, 30)
+
+ // Tie up +5 to opamps thought it's not currently needed
+ // Stay compatible
+ ANALOG_INPUT(V5, 5)
+ NET_C(op.VCC, V5)
+ NET_C(op1.VCC, V5)
+
+ /* Opamp wired as impedance changer */
+ SUBMODEL(opamp, op)
+
+ NET_C(op.GND, GND)
+ NET_C(op.PLUS, clk)
+ NET_C(op.MINUS, op.OUT)
+
+ SUBMODEL(opamp, op1)
+ /* Wired as inverting amplifier connected to output of first opamp */
+
+ RES(R1, 100000)
+ RES(R2, 200000)
+
+ NET_C(op1.GND, GND)
+ NET_C(op1.PLUS, GND)
+ NET_C(op1.MINUS, R2.2)
+ NET_C(op1.MINUS, R1.2)
+
+ NET_C(op.OUT, R1.1)
+ NET_C(op1.OUT, R2.1)
+
+ RES(RL, 1000)
+ NET_C(RL.2, GND)
+ NET_C(RL.1, op1.OUT)
+
+ LOG(log_X, op1.OUT)
+ LOG(log_Y, clk)
+}
+
+NETLIST_START(opamp)
+{
+
+ /* Opamp model from
+ *
+ * http://www.ecircuitcenter.com/Circuits/opmodel1/opmodel1.htm
+ *
+ * Bandwidth 10Mhz
+ *
+ */
+
+ /* Terminal definitions for calling netlists */
+
+ ALIAS(PLUS, G1.IP) // Positive input
+ ALIAS(MINUS, G1.IN) // Negative input
+ ALIAS(OUT, EBUF.OP) // Opamp output ...
+
+ ALIAS(GND, EBUF.ON) // GND terminal
+ ALIAS(VCC, DUMMY.I) // VCC terminal
+ DUMMY_INPUT(DUMMY)
+
+ /* The opamp model */
+
+ LVCCS(G1)
+ PARAM(G1.G, 0.0021)
+ PARAM(G1.CURLIM, 0.002)
+ RES(RP1, 1e7)
+ CAP(CP1, 0.00333e-6)
+ VCVS(EBUF)
+ PARAM(EBUF.RO, 50)
+ PARAM(EBUF.G, 1)
+
+// NET_C(EBUF.ON, GND)
+
+ NET_C(G1.ON, GND)
+ NET_C(RP1.2, GND)
+ NET_C(CP1.2, GND)
+ NET_C(EBUF.IN, GND)
+
+ NET_C(RP1.1, G1.OP)
+ NET_C(CP1.1, RP1.1)
+ NET_C(EBUF.IP, RP1.1)
+
+}
+
+NETLIST_START(opamp_mod)
+{
+
+ /* Opamp model from
+ *
+ * http://www.ecircuitcenter.com/Circuits/opmodel1/opmodel1.htm
+ *
+ * MB3614 Unit Gain frequency is about 500 kHz and the first pole frequency
+ * about 5 Hz. We have to keep the Unity Gain Frequency below our sampling
+ * frequency of 24 Khz.
+ *
+ * Simple Opamp Model Calculation
+ *
+ * First Pole Frequency 5 Hz
+ * Unity Gain Frequency 11,000 Hz
+ * RP 100,000 Ohm
+ * DC Gain / Aol 2200
+ * CP 0.318 uF
+ * KG 0.022
+ *
+ */
+
+ /* Terminal definitions for calling netlists */
+
+ ALIAS(PLUS, G1.IP) // Positive input
+ ALIAS(MINUS, G1.IN) // Negative input
+ ALIAS(OUT, EBUF.OP) // Opamp output ...
+
+ AFUNC(fUH, 1, "A0 1.2 -")
+ AFUNC(fUL, 1, "A0 1.2 +")
+
+ ALIAS(VCC, fUH.A0) // VCC terminal
+ ALIAS(GND, fUL.A0) // VGND terminal
+
+ AFUNC(fVREF, 2, "A0 A1 + 0.5 *")
+ NET_C(fUH.A0, fVREF.A0)
+ NET_C(fUL.A0, fVREF.A1)
+
+ NET_C(EBUF.ON, fVREF)
+ /* The opamp model */
+
+ LVCCS(G1)
+ PARAM(G1.RI, RES_K(1000))
+#if 0
+ PARAM(G1.G, 0.0022)
+ RES(RP1, 1e6)
+ CAP(CP1, 0.0318e-6)
+#else
+ PARAM(G1.G, 0.002)
+ PARAM(G1.CURLIM, 0.002)
+ RES(RP1, 9.5e6)
+ CAP(CP1, 0.0033e-6)
+#endif
+ VCVS(EBUF)
+ PARAM(EBUF.RO, 50)
+ PARAM(EBUF.G, 1)
+
+ NET_C(G1.ON, fVREF)
+ NET_C(RP1.2, fVREF)
+ NET_C(CP1.2, fVREF)
+ NET_C(EBUF.IN, fVREF)
+
+ NET_C(RP1.1, G1.OP)
+ NET_C(CP1.1, RP1.1)
+
+ DIODE(DP,"D(IS=1e-15 N=1)")
+ DIODE(DN,"D(IS=1e-15 N=1)")
+#if 1
+ NET_C(DP.K, fUH.Q)
+ NET_C(fUL.Q, DN.A)
+ NET_C(DP.A, DN.K, RP1.1)
+#else
+ /*
+ * This doesn't add any performance by decreasing iteration loops.
+ * To the contrary, it significantly decreases iterations
+ */
+ RES(RH1, 0.1)
+ RES(RL1, 0.1)
+ NET_C(DP.K, RH1.1)
+ NET_C(RH1.2, fUH.Q)
+ NET_C(fUL.Q, RL1.1)
+ NET_C(RL1.2, DN.A)
+ NET_C(DP.A, DN.K, RP1.1)
+
+#endif
+ NET_C(EBUF.IP, RP1.1)
+
+}
diff --git a/src/lib/netlist/examples/opamp_amplification_curve.cpp b/src/lib/netlist/examples/opamp_amplification_curve.cpp
new file mode 100644
index 00000000000..f34581c4977
--- /dev/null
+++ b/src/lib/netlist/examples/opamp_amplification_curve.cpp
@@ -0,0 +1,95 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * Script to analyze opamp amplification as a function of frequency.
+ *
+ * ./nltool -t 0.5 -f nl_examples/opamp_amplification_curve.cpp
+ *
+ * t=0.0: 10 Hz
+ * t=0.1: 100 Hz
+ * t=0.2: 1000 Hz
+ * t=0.3: 10000 Hz
+ * t=0.4: 100000 Hz
+ * ....
+ *
+ * ./plot_nl.sh --log Y Z
+ */
+
+
+#include "netlist/devices/net_lib.h"
+
+#define OPAMP_TEST "MB3614(DAB=0.0015)"
+
+NETLIST_START(main)
+{
+
+ /* Standard stuff */
+
+ //VARCLOCK(clk, "0.5 / pow(10, 1 + T * 4)")
+ //CLOCK(clk, 1000)
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-7)
+ PARAM(Solver.NR_LOOPS, 300)
+ PARAM(Solver.DYNAMIC_TS, 1)
+ PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 1e-7)
+
+ VS(vs, 0)
+ /*
+ * Having f(t)=sin(g(t)*t) the derivative becomes
+ *
+ * f'(t) = d/dt(g(t)*t) * cos(g(t)*t)
+ *
+ * w(t) = d/dt(g(t)*t) = 2*pi*freq(t) is the angular frequency at time t
+ *
+ * choosing freq(t) = pow(10, a+b*t) and integrating we get
+ *
+ * g(t)*t = 2 * pi /(b*ln(10)) * (pow(10, a+b*t)-pow(10,a))
+ */
+
+ PARAM(vs.FUNC, "0.001 * sin(0.2728752708 * (pow(10, 1 + 10*T) - 10))")
+
+ /*
+ * Stepwise ... same as above
+ */
+ //PARAM(vs.FUNC, "0.001 * sin(6.28 * pow(10, trunc((1 + T * 10)*10)/10) * T)")
+
+ /*
+ * Fixed Frequency:
+ * PARAM(vs.FUNC, "1.001 * sin(6.28 * 100 * T)")
+ */
+ PARAM(vs.R, 0.001)
+ ALIAS(clk, vs.1)
+ NET_C(vs.2, GND)
+ ANALOG_INPUT(V12, 12)
+ ANALOG_INPUT(VM12, -12)
+
+ OPAMP(op, OPAMP_TEST)
+
+ NET_C(op.GND, VM12)
+ NET_C(op.VCC, V12)
+
+ /* Opamp B wired as inverting amplifier connected to output of first opamp */
+
+ RES(R1, 100)
+ RES(RP, 100)
+ RES(R2, 10000000)
+
+ NET_C(op.PLUS, RP.1)
+ NET_C(RP.2, GND)
+ NET_C(op.MINUS, R2.2)
+ NET_C(op.MINUS, R1.2)
+
+ NET_C(clk, R1.1)
+ NET_C(op.OUT, R2.1)
+
+ RES(RL, 2000)
+ NET_C(RL.2, GND)
+ NET_C(RL.1, op.OUT)
+
+ AFUNC(f, 1, "A0 * 1000")
+ NET_C(f.A0, op.OUT)
+#if 1
+ LOG(log_Y, R1.1)
+ LOG(log_Z, f)
+#endif
+}
diff --git a/src/lib/netlist/examples/rc.c b/src/lib/netlist/examples/rc.c
new file mode 100644
index 00000000000..b18670292ab
--- /dev/null
+++ b/src/lib/netlist/examples/rc.c
@@ -0,0 +1,32 @@
+/*
+ * cdelay.c
+ *
+ */
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(rc)
+{
+
+ /*
+ * delay circuit
+ *
+ */
+
+ /* Standard stuff */
+
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-6)
+ CLOCK(clk, 20000)
+
+ CAP(C1, 0.022e-6)
+ RES(R1, 10000)
+ RES(R2, 20000)
+
+ NET_C(clk, R2.1)
+ NET_C(R2.2, R1.1, C1.1)
+ NET_C(C1.2, R1.2, GND)
+
+ LOG(tt, C1.1)
+
+}
diff --git a/src/lib/netlist/examples/rl.c b/src/lib/netlist/examples/rl.c
new file mode 100644
index 00000000000..3684aa1b701
--- /dev/null
+++ b/src/lib/netlist/examples/rl.c
@@ -0,0 +1,33 @@
+/*
+ * lr.c
+ *
+ */
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(lr)
+{
+
+ /*
+ * delay circuit
+ *
+ */
+
+ /* Standard stuff */
+
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-6)
+ CLOCK(clk, 50)
+ PARAM(Solver.METHOD, "MAT_CR")
+
+ IND(L1, 10)
+ RES(R1, 10000)
+
+ NET_C(clk, L1.1)
+ NET_C(L1.2, R1.1)
+ NET_C(R1.2, GND)
+
+ //LOG(log_1, R1.1)
+ //LOG(log_2, clk)
+
+}
diff --git a/src/lib/netlist/examples/sn74ls629_osc.c b/src/lib/netlist/examples/sn74ls629_osc.c
new file mode 100644
index 00000000000..518460c90b1
--- /dev/null
+++ b/src/lib/netlist/examples/sn74ls629_osc.c
@@ -0,0 +1,36 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * ne555_astable.c
+ *
+ */
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(ls629)
+{
+
+ /*
+ * Astable ne555
+ *
+ */
+
+ /* Standard stuff */
+
+ SOLVER(Solver, 48000)
+
+ ANALOG_INPUT(V5, 5) // 5V
+ ANALOG_INPUT(VF, 2.5) // 5V
+ ANALOG_INPUT(VR, 5) // 5V
+
+ SN74LS629(OSC, 0.022e-6)
+
+ NET_C(GND, OSC.GND)
+ NET_C(V5, OSC.VCC)
+ NET_C(VR, OSC.RNG)
+ NET_C(VF, OSC.FC)
+ NET_C(GND, OSC.ENQ)
+
+ LOG(log2, OSC.Y)
+
+}
diff --git a/src/lib/netlist/examples/test.c b/src/lib/netlist/examples/test.c
new file mode 100644
index 00000000000..8ae6de99db1
--- /dev/null
+++ b/src/lib/netlist/examples/test.c
@@ -0,0 +1,88 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * bjt.c
+ *
+ */
+
+// CURRENTLY BROKEN
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(bjt)
+{
+ /* Standard stuff */
+
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 48000)
+
+ ANALOG_INPUT(V3, 3)
+ ANALOG_INPUT(STOPG, 0)
+ ALIAS(SRSTQ, RYf.2)
+ ALIAS(SRST, RYc.2)
+ NET_C(antenna, GND)
+ ALIAS(runQ, Q1.C)
+
+ TTL_7404_INVERT(e4d, STOPG)
+
+ RES(RYf, 50) // output impedance
+ RES(RYc, 50) // output impedance
+
+ TTL_7404_INVERT(c9f, RYc.2)
+ TTL_7404_INVERT(c9c, RYf.2)
+ NET_C(c9f.Q, RYf.1)
+ NET_C(c9c.Q, RYc.1)
+
+ SWITCH2(coinsw, RYc.2, RYf.2)
+
+ NET_C(coinsw.Q, GND)
+
+ /* Antenna circuit */
+ /* Also has a diode to clamp negative voltages - omitted here */
+ NETDEV_QNPN(Q3, BC237B)
+ ALIAS(antenna, Q3.B)
+ NET_C(GND, Q3.E)
+ RES(RX5, 100)
+ CAP(CX1, 100)
+ NET_C(RX5.1, CX1.1)
+ NET_C(RX5.1, Q3.C)
+ NET_C(RX5.2, GND)
+ NET_C(CX1.2, GND)
+ NETDEV_QNPN(Q1, BC237B)
+ NET_C(Q1.B, RX5.1)
+ NET_C(Q1.E, GND)
+
+ DIODE(D3, 1N914)
+ NET_C(D3.A, Q1.C)
+ NET_C(D3.K, SRSTQ)
+
+ DIODE(D2, 1N914)
+ RES(RX4, 220)
+ NET_C(D2.K, e4d.Q)
+ NET_C(D2.A, RX4.1)
+ NET_C(RX4.2, Q3.C)
+
+ RES(RX1, 100)
+ RES(RX2, 100)
+ RES(RX3, 330)
+ CAP(CX2, CAP_U(0.1))
+
+ NET_C(RX3.2, D3.A)
+ NET_C(RX3.1, RX1.2)
+ NET_C(RX1.1, V3)
+
+ NET_C(RX1.1, CX2.1)
+ NET_C(RX1.2, CX2.2)
+
+ NETDEV_QPNP(Q2, BC556B)
+ NET_C(Q2.E, V3)
+ NET_C(Q2.B, RX1.2)
+ NET_C(Q2.C, RX2.2)
+
+ NET_C(RX2.1, D2.A)
+
+
+ //LOG(logB, Q1.B)
+ //LOG(logC, Q1.C)
+
+}
diff --git a/src/lib/netlist/examples/todo.c b/src/lib/netlist/examples/todo.c
new file mode 100644
index 00000000000..4426f44b3fa
--- /dev/null
+++ b/src/lib/netlist/examples/todo.c
@@ -0,0 +1,143 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * todo.c
+ *
+ */
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(7400_TTL)
+{
+ NET_REGISTER_DEV(7400, s1)
+ NET_REGISTER_DEV(7400, s2)
+ NET_REGISTER_DEV(7400, s3)
+ NET_REGISTER_DEV(7400, s4)
+
+ ALIAS(1, s1.A);
+ ALIAS(2, s1.B);
+ ALIAS(3, s1.Q);
+
+ ALIAS(4, s2.A);
+ ALIAS(5, s2.B);
+ ALIAS(6, s2.Q);
+
+ ALIAS(9, s3.A);
+ ALIAS(10, s3.B)
+ ALIAS(8, s3.Q);
+
+ ALIAS(12, s4.A);
+ ALIAS(13, s4.B);
+ ALIAS(11, s4.Q);
+
+}
+
+NETLIST_START(lib)
+{
+ TRUTH_TABLE(7400A, 2, 1, 0, "+A,B")
+{
+ TT_HEAD(" A , B | Q ")
+ TT_LINE(" 0 , X | 1 |22")
+ TT_LINE(" X , 0 | 1 |22")
+ TT_LINE(" 1 , 1 | 0 |15")
+ }
+}
+
+
+
+#if 0
+ RES(R1, 10)
+ RES(R2, 10)
+ RES(R3, 10)
+ NET_C(V5,R1.1)
+ NET_C(R1.2, R2.1)
+ NET_C(R2.2, R3.1)
+ NET_C(R3.2, GND)
+#endif
+#if 0
+ RES(R4, 1000)
+ CAP(C1, 1e-6)
+ NET_C(V5,R4.1)
+ NET_C(R4.2, C1.1)
+ NET_C(C1.2, GND)
+ //LOG(log1, C1.1)
+#endif
+
+#if 0
+ RES(R5, 1000)
+ NETDEV_1N914(D1)
+ NET_C(V5, R5.1)
+ NET_C(R5.2, D1.A)
+ NET_C(D1.K, GND)
+ //LOG(log1, D1.A)
+#endif
+
+#if 0
+#endif
+
+#if 0
+ NETDEV_VCVS(VV)
+ RES(R1, 1000)
+ RES(R2, 10000)
+
+ NET_C(V5, R1.1)
+ NET_C(R1.2, VV.IN)
+ NET_C(R2.1, VV.OP)
+ NET_C(R2.2, VV.IN)
+ NET_C(VV.ON, GND)
+ NET_C(VV.IP, GND)
+ LOG(logX, VV.OP)
+
+#endif
+
+#if 0
+#endif
+
+#if 0
+ NETDEV_VCVS(VV)
+ PARAM(VV.G, 100000) // typical OP-AMP amplification
+ PARAM(VV.RO, 50) // typical OP-AMP amplification
+ RES(R1, 1000)
+ RES(R3, 10000) // ==> 10x amplification (inverting)
+
+ NET_C(4V, R1.1)
+ NET_C(R1.2, VV.IN)
+ NET_C(R3.1, VV.IN)
+ NET_C(R3.2, VV.OP)
+ NET_C(VV.ON, GND)
+ NET_C(VV.IP, GND)
+ LOG(logX, VV.OP)
+ LOG(logY, 4V)
+
+#endif
+
+#if 0
+ // Impedance converter with resistor
+ NETDEV_VCVS(VV)
+ PARAM(VV.G, 100000) // typical OP-AMP amplification
+ PARAM(VV.RO, 50) // typical OP-AMP amplification
+ RES(R3, 10000)
+
+ NET_C(4V, VV.IP)
+ NET_C(R3.1, VV.IN)
+ NET_C(R3.2, VV.OP)
+ NET_C(VV.ON, GND)
+ LOG(logX, VV.OP)
+ LOG(logY, 4V)
+
+#endif
+
+#if 0
+ // Impedance converter without resistor
+ NETDEV_VCVS(VV)
+ PARAM(VV.G, 100000) // typical OP-AMP amplification
+ PARAM(VV.RO, 50) // typical OP-AMP amplification
+
+ NET_C(4V, VV.IP)
+ NET_C(VV.IN, VV.OP)
+ NET_C(VV.ON, GND)
+ LOG(logX, VV.OP)
+ LOG(logY, 4V)
+
+#endif
+
diff --git a/src/lib/netlist/examples/turkey_shoot.cpp b/src/lib/netlist/examples/turkey_shoot.cpp
new file mode 100644
index 00000000000..79c851f6a9e
--- /dev/null
+++ b/src/lib/netlist/examples/turkey_shoot.cpp
@@ -0,0 +1,214 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+
+/*
+ * This example illustrates how to use netlist to derive RGB output
+ * levels from complex output circuits.
+ *
+ * Create x.cpp:
+
+ #include <cstdio>
+
+ int main()
+ {
+ // Change IC86 output every micro second starting at 1ms
+ for (std::size_t i=0;i<256;i++)
+ printf("%.9f,IC86.D.IN,%d\n", (double) i / 1.0e6 + 1.0e-3, (int)i);
+ }
+
+ * Run these commands:
+ *
+ * c++ x.cpp
+ * ./a.out > src/lib/netlist/examples/turkey_shoot.csv
+ * ./nltool -c run -t 0.0013 -f src/lib/netlist/examples/turkey_shoot.cpp -i src/lib/netlist/examples/turkey_shoot.csv -l BLUE
+ * ./nlwav -f tab -o x.tab -s 0.0010005 -i 0.000001 -n 256 log_BLUE.log
+ *
+ * x.tab now contains 256 values representing the different output levels:
+ * low 4 bits: color value
+ * high 4 bits: attenuation value
+ *
+ */
+
+
+#include "netlist/devices/net_lib.h"
+
+/* ----------------------------------------------------------------------------
+ * Define
+ * ---------------------------------------------------------------------------*/
+
+/* set to 1 to use optimizations increasing performance significantly */
+
+#ifndef USE_OPTIMIZATIONS
+#define USE_OPTIMIZATIONS 0
+#endif
+
+/* ----------------------------------------------------------------------------
+ * Library section header START
+ * ---------------------------------------------------------------------------*/
+
+#ifndef __PLIB_PREPROCESSOR__
+
+#define SHIM74LS374_DIP(_name) \
+ NET_REGISTER_DEV_X(SHIM74LS374_DIP, _name)
+#endif
+
+/* ----------------------------------------------------------------------------
+ * Library section header END
+ * ---------------------------------------------------------------------------*/
+
+
+NETLIST_START(turkey_shoot_vga)
+{
+// EESCHEMA NETLIST VERSION 1.1 (SPICE FORMAT) CREATION DATE: WED 01 JUL 2015 11:09:25 PM CEST
+// TO EXCLUDE A COMPONENT FROM THE SPICE NETLIST ADD [SPICE_NETLIST_ENABLED] USER FIELD SET TO: N
+// TO REORDER THE COMPONENT SPICE NODE SEQUENCE ADD [SPICE_NODE_SEQUENCE] USER FIELD AND DEFINE SEQUENCE: 2,1,0
+// SHEET NAME:/
+// IGNORED O_AUDIO0: O_AUDIO0 64 0
+// .END
+
+ PARAM(Solver.RELTOL, 1e-2)
+ PARAM(Solver.VNTOL, 1e-6)
+ PARAM(Solver.NR_LOOPS, 30)
+ PARAM(Solver.GS_LOOPS, 99)
+ PARAM(Solver.METHOD, "MAT_CR")
+ PARAM(Solver.PARALLEL, 0)
+
+ //PARAM(Solver.METHOD, "GMRES")
+ //PARAM(Solver.ACCURACY, 1e-5)
+ //PARAM(Solver.METHOD, "SOR")
+
+#if USE_OPTIMIZATIONS
+ SOLVER(Solver, 48000)
+#else
+ SOLVER(Solver, 48000)
+ PARAM(Solver.DYNAMIC_TS, 1)
+ PARAM(Solver.PARALLEL, 0)
+ PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 2e-8)
+ PARAM(Solver.DYNAMIC_LTE, 1e-4)
+#endif
+
+ NET_MODEL("2N3904 NPN(IS=1E-14 VAF=100 Bf=300 IKF=0.4 XTB=1.5 BR=4 CJC=4E-12 CJE=8E-12 RB=20 RC=0.1 RE=0.1 TR=250E-9 TF=350E-12 ITF=1 VTF=2 XTF=3 Vceo=40 Icrating=200m mfg=Philips)")
+
+ LOCAL_SOURCE(SHIM74LS374_DIP)
+ LOCAL_LIB_ENTRY(SHIM74LS374_DIP)
+
+ INCLUDE(turkey_shoot_schematics)
+
+}
+
+NETLIST_START(turkey_shoot_schematics)
+{
+
+ ANALOG_INPUT(I_V12, 12)
+ ANALOG_INPUT(I_V5, 5)
+
+ TTL_INPUT(BLANK, 0)
+
+ IND(L1, 0.0000047)
+
+ CAP(C60, CAP_U(0.1))
+ CAP(C54, CAP_P(47))
+ CAP(C57, CAP_P(47))
+
+ RES(R32, RES_K(1))
+ RES(R33, RES_K(1))
+ RES(R34, 390)
+ RES(R6, RES_K(8.2))
+ RES(R7, RES_K(3.9))
+ RES(R8, RES_K(2))
+ RES(R9, RES_K(1))
+ RES(R10, RES_K(8.2))
+ RES(R11, RES_K(3.9))
+ RES(R12, RES_K(2))
+ RES(R13, RES_K(1))
+
+ RES(R35, RES_K(2.2))
+ RES(R36, RES_K(2.7))
+ RES(R31, 270)
+ RES(R30, RES_K(2))
+ RES(R29, RES_K(2))
+ RES(R28, RES_K(2))
+ RES(R22, 470)
+ RES(R23, 47)
+
+ DIODE(D1, "1N4148")
+ DIODE(D2, "1N4148")
+ DIODE(D3, "1N4148")
+ DIODE(D4, "1N4148")
+ DIODE(D5, "1N4148")
+ DIODE(D6, "1N4148")
+ DIODE(D7, "1N4148")
+ DIODE(D8, "1N4148")
+ DIODE(D17, "1N4148")
+
+ QBJT_EB(Q3, "2N3904")
+ QBJT_EB(Q4, "2N3904")
+ QBJT_EB(Q5, "2N3904")
+
+ SHIM74LS374_DIP(IC86)
+
+ NET_C(D8.K, IC86.19)
+ NET_C(D7.K, IC86.16)
+ NET_C(D6.K, IC86.15)
+ NET_C(D5.K, IC86.12)
+ NET_C(D4.K, IC86.9)
+ NET_C(D3.K, IC86.6)
+ NET_C(D2.K, IC86.5)
+ NET_C(D1.K, IC86.2)
+
+ NET_C(D8.A, R13.1)
+ NET_C(D7.A, R12.1)
+ NET_C(D6.A, R11.1)
+ NET_C(D5.A, R10.1)
+ NET_C(D4.A, R9.1)
+ NET_C(D3.A, R8.1)
+ NET_C(D2.A, R7.1)
+ NET_C(D1.A, R6.1)
+
+ NET_C(BLANK, C57.1, R32.1)
+ NET_C(C57.2, R32.2, R33.1, Q5.B)
+ NET_C(GND, R33.2, Q5.E, R36.2, C60.2)
+ NET_C(Q5.C, R34.1)
+ NET_C(R34.2, R13.2, R12.2, R11.2, R10.2, R35.2, R36.1, Q4.B)
+ NET_C(R35.1, Q4.C, C60.1, L1.2)
+
+ NET_C(I_V12, L1.1)
+
+ NET_C(Q4.E, R30.1, R29.1, R28.1, R31.1)
+
+ NET_C(GND, R31.2, R29.2, R28.2)
+ NET_C(R6.2, R7.2, R8.2, R9.2, R30.2, Q3.B)
+ NET_C(I_V5, Q3.C)
+ NET_C(GND, C54.2, R22.2)
+ NET_C(Q3.E, D17.A)
+ NET_C(D17.K, R22.1, R23.1)
+ NET_C(R23.2, C54.1)
+
+ NET_C(I_V5, IC86.20, BLANK.VCC)
+ NET_C(GND, IC86.10, BLANK.GND)
+
+ ALIAS(BLUE, C54.1)
+
+}
+
+
+NETLIST_START(SHIM74LS374_DIP)
+{
+
+ NET_MODEL("SPECIAL FAMILY(IVL=0.16 IVH=0.4 OVL=0.1 OVH=0.05 ORL=10.0 ORH=1.0e10)")
+ //LOGIC_INPUT8(D, 0, "74XX")
+ //LOGIC_INPUT8(D, 0, "74XXOC")
+ LOGIC_INPUT8(D, 0, "SPECIAL")
+ ALIAS(20, D.VCC)
+ ALIAS(10, D.GND)
+ ALIAS( 2, D.Q0)
+ ALIAS( 5, D.Q1)
+ ALIAS( 6, D.Q2)
+ ALIAS( 9, D.Q3)
+ ALIAS(12, D.Q4)
+ ALIAS(15, D.Q5)
+ ALIAS(16, D.Q6)
+ ALIAS(19, D.Q7)
+
+}
+
diff --git a/src/lib/netlist/examples/turkey_shoot.csv b/src/lib/netlist/examples/turkey_shoot.csv
new file mode 100644
index 00000000000..095d3d92e08
--- /dev/null
+++ b/src/lib/netlist/examples/turkey_shoot.csv
@@ -0,0 +1,256 @@
+0.001000000,IC86.D.IN,0
+0.001001000,IC86.D.IN,1
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diff --git a/src/lib/netlist/examples/vccs.c b/src/lib/netlist/examples/vccs.c
new file mode 100644
index 00000000000..4468a09c352
--- /dev/null
+++ b/src/lib/netlist/examples/vccs.c
@@ -0,0 +1,31 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * vccs.c
+ *
+ */
+
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(vccs)
+{
+
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-12)
+ PARAM(Solver.GS_LOOPS, 10000)
+
+ VCCS(VV)
+ PARAM(VV.G, 100) // typical OP-AMP amplification
+ RES(R2, 1)
+
+ NET_C(clk, VV.IN)
+ NET_C(R2.1, VV.OP)
+ NET_C(R2.2, GND)
+ NET_C(VV.ON, GND)
+ NET_C(VV.IP, GND)
+ LOG(logX, VV.OP)
+ LOG(logY, clk)
+
+}
diff --git a/src/lib/netlist/examples/vccs1.c b/src/lib/netlist/examples/vccs1.c
new file mode 100644
index 00000000000..c578aad6434
--- /dev/null
+++ b/src/lib/netlist/examples/vccs1.c
@@ -0,0 +1,36 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * vccs.c
+ *
+ */
+
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(vccs)
+{
+
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-6)
+
+
+ VCCS(VV)
+ PARAM(VV.G, 100000) // typical OP-AMP amplification
+ RES(R1, 10000)
+ RES(R2, 1)
+ RES(R3, 1000)
+
+ NET_C(clk, R1.1)
+ NET_C(R1.2, VV.IN)
+ NET_C(R2.1, VV.OP)
+ NET_C(R3.1, VV.IN)
+ NET_C(R3.2, VV.OP)
+ NET_C(R2.2, GND)
+ NET_C(VV.ON, GND)
+ NET_C(VV.IP, GND)
+ LOG(logX, VV.OP)
+ LOG(logY, clk)
+
+}
diff --git a/src/lib/netlist/examples/vs_cs.c b/src/lib/netlist/examples/vs_cs.c
new file mode 100644
index 00000000000..36a025996cc
--- /dev/null
+++ b/src/lib/netlist/examples/vs_cs.c
@@ -0,0 +1,53 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+/*
+ * vs_cs.c
+ *
+ * Voltage and current source test
+ *
+ */
+
+#include "netlist/devices/net_lib.h"
+
+NETLIST_START(rc)
+{
+
+ /*
+ * delay circuit
+ *
+ */
+
+ /* Standard stuff */
+
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-6)
+ CLOCK(clk, 20000)
+
+ /* Voltage source. Inner resistance will make clock visible */
+
+ RES(R1, 1000)
+ VS(VS1, 1)
+ NET_C(R1.1, clk)
+ NET_C(R1.2, VS1.P)
+ NET_C(GND, VS1.N)
+
+ /* Current source. Current flows from "+" to "-", thus for a source we
+ * need negative current
+ */
+
+ RES(R2, 1000)
+ RES(R3, 1000)
+ CS(CS1, -0.001)
+ NET_C(CS1.P, R2.1)
+ NET_C(R2.2, R3.1)
+ NET_C(GND, CS1.N, R3.2)
+
+ CAP(C1, CAP_U(1))
+ NET_C(C1.1, R3.1)
+ NET_C(C1.2, R3.2)
+
+
+ LOG(tt, VS1.P)
+ LOG(tx, R2.2)
+
+}
diff --git a/src/lib/netlist/examples/zdiode.cpp b/src/lib/netlist/examples/zdiode.cpp
new file mode 100644
index 00000000000..a059b09299e
--- /dev/null
+++ b/src/lib/netlist/examples/zdiode.cpp
@@ -0,0 +1,46 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+
+/*
+ * zdiode.cpp
+ *
+ */
+
+//! [zdiode_example]
+#include "netlist/devices/net_lib.h"
+
+// ./nltool -t 1 -l clk.Q -l ZD.K -v --extended src/lib/netlist/examples/zdiode.cpp
+// ./plot_nl.sh clk.Q ZD.K
+// clk.Q: clock output
+// ZD.K: voltage at Zener
+
+NETLIST_START(zdiode)
+{
+
+ SOLVER(Solver, 48000)
+ PARAM(Solver.DYNAMIC_TS, 1)
+ PARAM(Solver.VNTOL, 1e-7)
+ PARAM(Solver.RELTOL, 1e-4)
+
+ ANALOG_INPUT(V12, 12.0)
+ ANALOG_INPUT(V4, 4.0)
+
+ CLOCK(clk, 100)
+ ZDIODE(ZD, "D(BV=7.5 IBV=0.01 NBV=3)")
+ RES(R, 20)
+ RES(Rclk, 200)
+ CAP(C, 1e-6)
+
+ NET_C(V4, clk.GND) // make clock between 4 and 12 V
+ NET_C(V12, clk.VCC, R.1)
+
+ NET_C(GND, ZD.A, C.2)
+ NET_C(clk.Q, Rclk.1)
+ NET_C(Rclk.2, R.2, ZD.K, C.1)
+
+ RES(RL, 1000)
+ NET_C(RL.1, ZD.K)
+ NET_C(RL.2, GND)
+
+}
+//! [zdiode_example]