diff options
Diffstat (limited to 'src/lib/netlist/examples/vs_cs.c')
-rw-r--r-- | src/lib/netlist/examples/vs_cs.c | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/src/lib/netlist/examples/vs_cs.c b/src/lib/netlist/examples/vs_cs.c new file mode 100644 index 00000000000..36a025996cc --- /dev/null +++ b/src/lib/netlist/examples/vs_cs.c @@ -0,0 +1,53 @@ +// license:CC0-1.0 +// copyright-holders:Couriersud +/* + * vs_cs.c + * + * Voltage and current source test + * + */ + +#include "netlist/devices/net_lib.h" + +NETLIST_START(rc) +{ + + /* + * delay circuit + * + */ + + /* Standard stuff */ + + SOLVER(Solver, 48000) + PARAM(Solver.ACCURACY, 1e-6) + CLOCK(clk, 20000) + + /* Voltage source. Inner resistance will make clock visible */ + + RES(R1, 1000) + VS(VS1, 1) + NET_C(R1.1, clk) + NET_C(R1.2, VS1.P) + NET_C(GND, VS1.N) + + /* Current source. Current flows from "+" to "-", thus for a source we + * need negative current + */ + + RES(R2, 1000) + RES(R3, 1000) + CS(CS1, -0.001) + NET_C(CS1.P, R2.1) + NET_C(R2.2, R3.1) + NET_C(GND, CS1.N, R3.2) + + CAP(C1, CAP_U(1)) + NET_C(C1.1, R3.1) + NET_C(C1.2, R3.2) + + + LOG(tt, VS1.P) + LOG(tx, R2.2) + +} |