diff options
Diffstat (limited to 'src/devices')
| -rw-r--r-- | src/devices/bus/a2bus/a2themill.c | 2 | ||||
| -rw-r--r-- | src/devices/bus/cpc/ddi1.h | 2 | ||||
| -rw-r--r-- | src/devices/bus/cpc/doubler.c | 11 | ||||
| -rw-r--r-- | src/devices/bus/cpc/doubler.h | 10 | ||||
| -rw-r--r-- | src/devices/bus/isa/omti8621.c | 2 | ||||
| -rw-r--r-- | src/devices/bus/rs232/pty.c | 152 | ||||
| -rw-r--r-- | src/devices/bus/rs232/pty.h | 58 | ||||
| -rw-r--r-- | src/devices/bus/rs232/rs232.c | 2 | ||||
| -rw-r--r-- | src/devices/bus/tiki100/8088.c | 2 | ||||
| -rw-r--r-- | src/devices/bus/tiki100/8088.h | 2 | ||||
| -rw-r--r-- | src/devices/bus/tiki100/exp.h | 4 | ||||
| -rw-r--r-- | src/devices/bus/tiki100/hdc.c | 2 | ||||
| -rw-r--r-- | src/devices/bus/tiki100/hdc.h | 2 | ||||
| -rw-r--r-- | src/devices/cpu/mips/mips3.h | 2 | ||||
| -rw-r--r-- | src/devices/imagedev/floppy.c | 34 | ||||
| -rw-r--r-- | src/devices/imagedev/floppy.h | 12 | ||||
| -rw-r--r-- | src/devices/machine/z80scc.c | 296 | ||||
| -rw-r--r-- | src/devices/machine/z80scc.h | 416 | ||||
| -rw-r--r-- | src/devices/machine/z80sio.c | 190 | ||||
| -rw-r--r-- | src/devices/machine/z80sio.h | 302 | ||||
| -rw-r--r-- | src/devices/video/poly.h | 40 |
21 files changed, 771 insertions, 772 deletions
diff --git a/src/devices/bus/a2bus/a2themill.c b/src/devices/bus/a2bus/a2themill.c index 8f6fc5d1cc0..34b2cac13c1 100644 --- a/src/devices/bus/a2bus/a2themill.c +++ b/src/devices/bus/a2bus/a2themill.c @@ -255,7 +255,7 @@ READ8_MEMBER( a2bus_themill_device::dma_r ) { return slot_dma_read(space, (offset&0xfff) + 0xc000); } - else if (offset <= 0xcfff) // 6809 Cxxx -> 6502 ZP + else if (offset <= 0xcfff) // 6809 Cxxx -> 6502 ZP { return slot_dma_read(space, (offset&0xfff)); } diff --git a/src/devices/bus/cpc/ddi1.h b/src/devices/bus/cpc/ddi1.h index 404bc76120c..9d36783d9b4 100644 --- a/src/devices/bus/cpc/ddi1.h +++ b/src/devices/bus/cpc/ddi1.h @@ -42,7 +42,7 @@ private: required_device<upd765_family_device> m_fdc; required_device<floppy_connector> m_connector; - + bool m_rom_active; bool m_romen; }; diff --git a/src/devices/bus/cpc/doubler.c b/src/devices/bus/cpc/doubler.c index 50bdf437a5d..2c753d3565e 100644 --- a/src/devices/bus/cpc/doubler.c +++ b/src/devices/bus/cpc/doubler.c @@ -1,15 +1,15 @@ // license:BSD-3-Clause // copyright-holders:Barry Rodewald /* - * doubler.c -- Draysoft Doubler - external cassette interface for the 464 (works on 664/6128 with external cassette?), + * doubler.c -- Draysoft Doubler - external cassette interface for the 464 (works on 664/6128 with external cassette?), * intended for use in duplicating cassette software * */ - - #include "doubler.h" - #include "includes/amstrad.h" - //************************************************************************** + #include "doubler.h" + #include "includes/amstrad.h" + + //************************************************************************** // DEVICE DEFINITIONS //************************************************************************** @@ -72,4 +72,3 @@ READ8_MEMBER(cpc_doubler_device::ext_tape_r) data |= 0x20; return data; } - diff --git a/src/devices/bus/cpc/doubler.h b/src/devices/bus/cpc/doubler.h index 22cac02c3e2..6b650179b0f 100644 --- a/src/devices/bus/cpc/doubler.h +++ b/src/devices/bus/cpc/doubler.h @@ -1,13 +1,13 @@ // license:BSD-3-Clause // copyright-holders:Barry Rodewald /* - * doubler.c -- Draysoft Doubler - external cassette interface for the 464 (works on 664/6128 with external cassette?), + * doubler.c -- Draysoft Doubler - external cassette interface for the 464 (works on 664/6128 with external cassette?), * intended for use in duplicating cassette software * * Uses only port F0E0 (may conflict with other peripherals, PPI port A is not usable while Doubler software is running) * */ - + #ifndef DOUBLER_H_ #define DOUBLER_H_ @@ -27,7 +27,7 @@ public: virtual machine_config_constructor device_mconfig_additions() const; DECLARE_READ8_MEMBER(ext_tape_r); - + protected: // device-level overrides virtual void device_start(); @@ -35,11 +35,11 @@ protected: private: cpc_expansion_slot_device *m_slot; - + required_device<cassette_image_device> m_tape; }; // device type definition extern const device_type CPC_DOUBLER; - + #endif /* DOUBLER_H_ */ diff --git a/src/devices/bus/isa/omti8621.c b/src/devices/bus/isa/omti8621.c index fdb11304f5c..9f86243a90a 100644 --- a/src/devices/bus/isa/omti8621.c +++ b/src/devices/bus/isa/omti8621.c @@ -216,7 +216,7 @@ MACHINE_CONFIG_FRAGMENT( omti_disk ) MCFG_PC_FDC_DRQ_CALLBACK(WRITELINE(omti8621_device, fdc_drq_w)) MCFG_FLOPPY_DRIVE_ADD(OMTI_FDC_TAG":0", pc_hd_floppies, "525hd", omti8621_device::floppy_formats) // Apollo workstations never have more then 1 floppy drive -// MCFG_FLOPPY_DRIVE_ADD(OMTI_FDC_TAG":1", pc_hd_floppies, "525hd", omti8621_device::floppy_formats) +// MCFG_FLOPPY_DRIVE_ADD(OMTI_FDC_TAG":1", pc_hd_floppies, "525hd", omti8621_device::floppy_formats) MACHINE_CONFIG_END FLOPPY_FORMATS_MEMBER( omti8621_device::floppy_formats ) diff --git a/src/devices/bus/rs232/pty.c b/src/devices/bus/rs232/pty.c index bc673318e2a..0039925ac85 100644 --- a/src/devices/bus/rs232/pty.c +++ b/src/devices/bus/rs232/pty.c @@ -7,132 +7,132 @@ static const int TIMER_POLL = 1; pseudo_terminal_device::pseudo_terminal_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : - device_t(mconfig, PSEUDO_TERMINAL, "Pseudo terminal", tag, owner, clock, "pseudo_terminal", __FILE__), - device_serial_interface(mconfig, *this), - device_rs232_port_interface(mconfig, *this), - device_pty_interface(mconfig, *this), - m_rs232_txbaud(*this, "RS232_TXBAUD"), - m_rs232_rxbaud(*this, "RS232_RXBAUD"), - m_rs232_startbits(*this, "RS232_STARTBITS"), - m_rs232_databits(*this, "RS232_DATABITS"), - m_rs232_parity(*this, "RS232_PARITY"), - m_rs232_stopbits(*this, "RS232_STOPBITS"), - m_input_count(0), - m_input_index(0) + device_t(mconfig, PSEUDO_TERMINAL, "Pseudo terminal", tag, owner, clock, "pseudo_terminal", __FILE__), + device_serial_interface(mconfig, *this), + device_rs232_port_interface(mconfig, *this), + device_pty_interface(mconfig, *this), + m_rs232_txbaud(*this, "RS232_TXBAUD"), + m_rs232_rxbaud(*this, "RS232_RXBAUD"), + m_rs232_startbits(*this, "RS232_STARTBITS"), + m_rs232_databits(*this, "RS232_DATABITS"), + m_rs232_parity(*this, "RS232_PARITY"), + m_rs232_stopbits(*this, "RS232_STOPBITS"), + m_input_count(0), + m_input_index(0) { } WRITE_LINE_MEMBER(pseudo_terminal_device::update_serial) { - int startbits = convert_startbits(m_rs232_startbits->read()); - int databits = convert_databits(m_rs232_databits->read()); - parity_t parity = convert_parity(m_rs232_parity->read()); - stop_bits_t stopbits = convert_stopbits(m_rs232_stopbits->read()); + int startbits = convert_startbits(m_rs232_startbits->read()); + int databits = convert_databits(m_rs232_databits->read()); + parity_t parity = convert_parity(m_rs232_parity->read()); + stop_bits_t stopbits = convert_stopbits(m_rs232_stopbits->read()); - set_data_frame(startbits, databits, parity, stopbits); + set_data_frame(startbits, databits, parity, stopbits); - int txbaud = convert_baud(m_rs232_txbaud->read()); - set_tra_rate(txbaud); + int txbaud = convert_baud(m_rs232_txbaud->read()); + set_tra_rate(txbaud); - int rxbaud = convert_baud(m_rs232_rxbaud->read()); - set_rcv_rate(rxbaud); + int rxbaud = convert_baud(m_rs232_rxbaud->read()); + set_rcv_rate(rxbaud); - output_rxd(1); + output_rxd(1); - // TODO: make this configurable - output_dcd(0); - output_dsr(0); - output_cts(0); + // TODO: make this configurable + output_dcd(0); + output_dsr(0); + output_cts(0); } static INPUT_PORTS_START(pseudo_terminal) - MCFG_RS232_BAUD("RS232_TXBAUD", RS232_BAUD_9600, "TX Baud", pseudo_terminal_device, update_serial) - MCFG_RS232_BAUD("RS232_RXBAUD", RS232_BAUD_9600, "RX Baud", pseudo_terminal_device, update_serial) - MCFG_RS232_STARTBITS("RS232_STARTBITS", RS232_STARTBITS_1, "Start Bits", pseudo_terminal_device, update_serial) - MCFG_RS232_DATABITS("RS232_DATABITS", RS232_DATABITS_8, "Data Bits", pseudo_terminal_device, update_serial) - MCFG_RS232_PARITY("RS232_PARITY", RS232_PARITY_NONE, "Parity", pseudo_terminal_device, update_serial) - MCFG_RS232_STOPBITS("RS232_STOPBITS", RS232_STOPBITS_1, "Stop Bits", pseudo_terminal_device, update_serial) + MCFG_RS232_BAUD("RS232_TXBAUD", RS232_BAUD_9600, "TX Baud", pseudo_terminal_device, update_serial) + MCFG_RS232_BAUD("RS232_RXBAUD", RS232_BAUD_9600, "RX Baud", pseudo_terminal_device, update_serial) + MCFG_RS232_STARTBITS("RS232_STARTBITS", RS232_STARTBITS_1, "Start Bits", pseudo_terminal_device, update_serial) + MCFG_RS232_DATABITS("RS232_DATABITS", RS232_DATABITS_8, "Data Bits", pseudo_terminal_device, update_serial) + MCFG_RS232_PARITY("RS232_PARITY", RS232_PARITY_NONE, "Parity", pseudo_terminal_device, update_serial) + MCFG_RS232_STOPBITS("RS232_STOPBITS", RS232_STOPBITS_1, "Stop Bits", pseudo_terminal_device, update_serial) INPUT_PORTS_END ioport_constructor pseudo_terminal_device::device_input_ports() const { - return INPUT_PORTS_NAME(pseudo_terminal); + return INPUT_PORTS_NAME(pseudo_terminal); } void pseudo_terminal_device::device_start() { - m_timer_poll = timer_alloc(TIMER_POLL); + m_timer_poll = timer_alloc(TIMER_POLL); - open(); + open(); } void pseudo_terminal_device::device_stop() { - close(); + close(); } void pseudo_terminal_device::device_reset() { - update_serial(0); - queue(); + update_serial(0); + queue(); } void pseudo_terminal_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) { - switch (id) - { - case TIMER_POLL: - queue(); - break; - - default: - device_serial_interface::device_timer(timer, id, param, ptr); - } + switch (id) + { + case TIMER_POLL: + queue(); + break; + + default: + device_serial_interface::device_timer(timer, id, param, ptr); + } } void pseudo_terminal_device::tra_callback() { - output_rxd(transmit_register_get_data_bit()); + output_rxd(transmit_register_get_data_bit()); } void pseudo_terminal_device::tra_complete() { - queue(); + queue(); } void pseudo_terminal_device::rcv_complete() { - receive_register_extract(); - write(get_received_char()); + receive_register_extract(); + write(get_received_char()); } void pseudo_terminal_device::queue(void) { - if (is_transmit_register_empty()) - { - if (m_input_index == m_input_count) - { - m_input_index = 0; - int tmp = read(m_input_buffer , sizeof(m_input_buffer)); - if (tmp > 0) { - m_input_count = tmp; - } else { - m_input_count = 0; - } - } - - if (m_input_count != 0) - { - transmit_register_setup(m_input_buffer[ m_input_index++ ]); - - m_timer_poll->adjust(attotime::never); - } - else - { - int txbaud = convert_baud(m_rs232_txbaud->read()); - m_timer_poll->adjust(attotime::from_hz(txbaud)); - } - } + if (is_transmit_register_empty()) + { + if (m_input_index == m_input_count) + { + m_input_index = 0; + int tmp = read(m_input_buffer , sizeof(m_input_buffer)); + if (tmp > 0) { + m_input_count = tmp; + } else { + m_input_count = 0; + } + } + + if (m_input_count != 0) + { + transmit_register_setup(m_input_buffer[ m_input_index++ ]); + + m_timer_poll->adjust(attotime::never); + } + else + { + int txbaud = convert_baud(m_rs232_txbaud->read()); + m_timer_poll->adjust(attotime::from_hz(txbaud)); + } + } } const device_type PSEUDO_TERMINAL = &device_creator<pseudo_terminal_device>; diff --git a/src/devices/bus/rs232/pty.h b/src/devices/bus/rs232/pty.h index 1f4ddbce754..222ee446b53 100644 --- a/src/devices/bus/rs232/pty.h +++ b/src/devices/bus/rs232/pty.h @@ -7,44 +7,44 @@ #include "rs232.h" class pseudo_terminal_device : public device_t, - public device_serial_interface, - public device_rs232_port_interface, - public device_pty_interface + public device_serial_interface, + public device_rs232_port_interface, + public device_pty_interface { public: - pseudo_terminal_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + pseudo_terminal_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - virtual DECLARE_WRITE_LINE_MEMBER( input_txd ) { - device_serial_interface::rx_w(state); - } + virtual DECLARE_WRITE_LINE_MEMBER( input_txd ) { + device_serial_interface::rx_w(state); + } - DECLARE_WRITE_LINE_MEMBER(update_serial); + DECLARE_WRITE_LINE_MEMBER(update_serial); protected: - virtual ioport_constructor device_input_ports() const; - virtual void device_start(); - virtual void device_stop(); - virtual void device_reset(); - virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr); + virtual ioport_constructor device_input_ports() const; + virtual void device_start(); + virtual void device_stop(); + virtual void device_reset(); + virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr); - virtual void tra_callback(); - virtual void tra_complete(); - virtual void rcv_complete(); + virtual void tra_callback(); + virtual void tra_complete(); + virtual void rcv_complete(); private: - required_ioport m_rs232_txbaud; - required_ioport m_rs232_rxbaud; - required_ioport m_rs232_startbits; - required_ioport m_rs232_databits; - required_ioport m_rs232_parity; - required_ioport m_rs232_stopbits; - - UINT8 m_input_buffer[ 1024 ]; - UINT32 m_input_count; - UINT32 m_input_index; - emu_timer *m_timer_poll; - - void queue(void); + required_ioport m_rs232_txbaud; + required_ioport m_rs232_rxbaud; + required_ioport m_rs232_startbits; + required_ioport m_rs232_databits; + required_ioport m_rs232_parity; + required_ioport m_rs232_stopbits; + + UINT8 m_input_buffer[ 1024 ]; + UINT32 m_input_count; + UINT32 m_input_index; + emu_timer *m_timer_poll; + + void queue(void); }; extern const device_type PSEUDO_TERMINAL; diff --git a/src/devices/bus/rs232/rs232.c b/src/devices/bus/rs232/rs232.c index cb2d1771a6e..411a31a8f01 100644 --- a/src/devices/bus/rs232/rs232.c +++ b/src/devices/bus/rs232/rs232.c @@ -111,5 +111,5 @@ SLOT_INTERFACE_START( default_rs232_devices ) SLOT_INTERFACE("null_modem", NULL_MODEM) SLOT_INTERFACE("printer", SERIAL_PRINTER) SLOT_INTERFACE("terminal", SERIAL_TERMINAL) - SLOT_INTERFACE("pty", PSEUDO_TERMINAL) + SLOT_INTERFACE("pty", PSEUDO_TERMINAL) SLOT_INTERFACE_END diff --git a/src/devices/bus/tiki100/8088.c b/src/devices/bus/tiki100/8088.c index 1065c856340..d8c9fe201b5 100644 --- a/src/devices/bus/tiki100/8088.c +++ b/src/devices/bus/tiki100/8088.c @@ -14,7 +14,7 @@ // MACROS/CONSTANTS //************************************************************************** -#define I8088_TAG "u3" +#define I8088_TAG "u3" diff --git a/src/devices/bus/tiki100/8088.h b/src/devices/bus/tiki100/8088.h index 2700866a169..6bfa5e723bc 100644 --- a/src/devices/bus/tiki100/8088.h +++ b/src/devices/bus/tiki100/8088.h @@ -24,7 +24,7 @@ // ======================> tiki100_8088_t class tiki100_8088_t : public device_t, - public device_tiki100bus_card_interface + public device_tiki100bus_card_interface { public: // construction/destruction diff --git a/src/devices/bus/tiki100/exp.h b/src/devices/bus/tiki100/exp.h index fc25c522c79..e41b18e7831 100644 --- a/src/devices/bus/tiki100/exp.h +++ b/src/devices/bus/tiki100/exp.h @@ -105,8 +105,8 @@ public: // ======================> tiki100_bus_slot_t class tiki100_bus_slot_t : public device_t, - public device_slot_interface, - public device_z80daisy_interface + public device_slot_interface, + public device_z80daisy_interface { public: // construction/destruction diff --git a/src/devices/bus/tiki100/hdc.c b/src/devices/bus/tiki100/hdc.c index 2b978635ead..504222f0f48 100644 --- a/src/devices/bus/tiki100/hdc.c +++ b/src/devices/bus/tiki100/hdc.c @@ -14,7 +14,7 @@ // MACROS/CONSTANTS //************************************************************************** -#define WD1010_TAG "hdc" +#define WD1010_TAG "hdc" diff --git a/src/devices/bus/tiki100/hdc.h b/src/devices/bus/tiki100/hdc.h index d06342fc66c..fefde73c2e7 100644 --- a/src/devices/bus/tiki100/hdc.h +++ b/src/devices/bus/tiki100/hdc.h @@ -25,7 +25,7 @@ // ======================> tiki100_hdc_t class tiki100_hdc_t : public device_t, - public device_tiki100bus_card_interface + public device_tiki100bus_card_interface { public: // construction/destruction diff --git a/src/devices/cpu/mips/mips3.h b/src/devices/cpu/mips/mips3.h index 4ae8398dac0..87462f79d5b 100644 --- a/src/devices/cpu/mips/mips3.h +++ b/src/devices/cpu/mips/mips3.h @@ -366,7 +366,7 @@ private: UINT32 m_nextpc; UINT32 m_pcbase; UINT8 m_cf[4][8]; - bool m_delayslot; + bool m_delayslot; int m_op; int m_interrupt_cycles; UINT32 m_ll_value; diff --git a/src/devices/imagedev/floppy.c b/src/devices/imagedev/floppy.c index c248b10a1e7..47ddeb05f38 100644 --- a/src/devices/imagedev/floppy.c +++ b/src/devices/imagedev/floppy.c @@ -415,10 +415,10 @@ bool floppy_image_device::call_load() if (!cur_load_cb.isnull()) return cur_load_cb(this); - if (motor_always_on) { - // When disk is inserted, start motor - mon_w(0); - } else if(!mon) + if (motor_always_on) { + // When disk is inserted, start motor + mon_w(0); + } else if(!mon) ready_counter = 2; return IMAGE_INIT_PASS; @@ -446,10 +446,10 @@ void floppy_image_device::call_unload() if (!cur_unload_cb.isnull()) cur_unload_cb(this); - if (motor_always_on) { - // When disk is removed, stop motor - mon_w(1); - } else if(!ready) { + if (motor_always_on) { + // When disk is removed, stop motor + mon_w(1); + } else if(!ready) { ready = true; if(!cur_ready_cb.isnull()) cur_ready_cb(this, ready); @@ -497,15 +497,15 @@ void floppy_image_device::mon_w(int state) if (!mon && image) { revolution_start_time = machine().time(); - if (motor_always_on) { - // Drives with motor that is always spinning are immediately ready when a disk is loaded - // because there is no spin-up time - ready = false; - if(!cur_ready_cb.isnull()) - cur_ready_cb(this, ready); - } else { - ready_counter = 2; - } + if (motor_always_on) { + // Drives with motor that is always spinning are immediately ready when a disk is loaded + // because there is no spin-up time + ready = false; + if(!cur_ready_cb.isnull()) + cur_ready_cb(this, ready); + } else { + ready_counter = 2; + } index_resync(); } diff --git a/src/devices/imagedev/floppy.h b/src/devices/imagedev/floppy.h index a57b2c7b72e..5968ed6eeb8 100644 --- a/src/devices/imagedev/floppy.h +++ b/src/devices/imagedev/floppy.h @@ -290,11 +290,11 @@ private: sound_stream* m_sound; bool m_loaded; - bool m_is525; // true if this is a 5.25" floppy drive + bool m_is525; // true if this is a 5.25" floppy drive - int m_sampleindex_motor_start; - int m_sampleindex_motor_loop; - int m_sampleindex_motor_end; + int m_sampleindex_motor_start; + int m_sampleindex_motor_loop; + int m_sampleindex_motor_end; int m_samplesize_motor_start; int m_samplesize_motor_loop; int m_samplesize_motor_end; @@ -302,8 +302,8 @@ private: int m_motor_playback_state; bool m_motor_on; - int m_step_samples; - int m_sampleindex_step1; + int m_step_samples; + int m_sampleindex_step1; int m_samplesize_step[MAX_STEP_SAMPLES]; int m_samplepos_step; int m_step_playback_state; diff --git a/src/devices/machine/z80scc.c b/src/devices/machine/z80scc.c index 91221c8d339..1abc94fec86 100644 --- a/src/devices/machine/z80scc.c +++ b/src/devices/machine/z80scc.c @@ -73,7 +73,7 @@ TODO: #include "z80scc.h" //************************************************************************** -// MACROS / CONSTANTS +// MACROS / CONSTANTS //************************************************************************** #define VERBOSE 0 @@ -89,11 +89,11 @@ TODO: #define FUNCNAME __PRETTY_FUNCTION__ #endif -#define CHANA_TAG "cha" -#define CHANB_TAG "chb" +#define CHANA_TAG "cha" +#define CHANB_TAG "chb" //************************************************************************** -// DEVICE DEFINITIONS +// DEVICE DEFINITIONS //************************************************************************** // device type definition const device_type Z80SCC = &device_creator<z80scc_device>; @@ -108,7 +108,7 @@ const device_type SCC85233 = &device_creator<scc85233_device>; const device_type SCC8523L = &device_creator<scc8523L_device>; //------------------------------------------------- -// device_mconfig_additions - +// device_mconfig_additions - //------------------------------------------------- MACHINE_CONFIG_FRAGMENT( z80scc ) MCFG_DEVICE_ADD(CHANA_TAG, Z80SCC_CHANNEL, 0) @@ -121,11 +121,11 @@ machine_config_constructor z80scc_device::device_mconfig_additions() const } //************************************************************************** -// LIVE DEVICE +// LIVE DEVICE //************************************************************************** //------------------------------------------------- -// z80scc_device - constructor +// z80scc_device - constructor //------------------------------------------------- z80scc_device::z80scc_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source) @@ -213,7 +213,7 @@ scc8523L_device::scc8523L_device(const machine_config &mconfig, const char *tag, : z80scc_device(mconfig, SCC8523L, "SCC 8523L", tag, owner, clock, TYPE_SCC8523L, "scc8523L", __FILE__){ } //------------------------------------------------- -// device_start - device-specific startup +// device_start - device-specific startup //------------------------------------------------- void z80scc_device::device_start() @@ -252,7 +252,7 @@ void z80scc_device::device_start() //------------------------------------------------- -// device_reset - device-specific reset +// device_reset - device-specific reset //------------------------------------------------- void z80scc_device::device_reset() @@ -269,7 +269,7 @@ Each of the SCC's two channels contain three sources of interrupts, making a tot sources. These three sources of interrupts are: 1) Receiver, 2) Transmitter, and 3) External/Status conditions. In addition, there are several conditions that may cause these interrupts.*/ //------------------------------------------------- -// z80daisy_irq_state - get interrupt status +// z80daisy_irq_state - get interrupt status //------------------------------------------------- int z80scc_device::z80daisy_irq_state() @@ -278,8 +278,8 @@ int z80scc_device::z80daisy_irq_state() int i; LOG(("%s %s A:%d%d%d B:%d%d%d ",FUNCNAME, tag(), - m_int_state[0], m_int_state[1], m_int_state[2], - m_int_state[3], m_int_state[4], m_int_state[5])); + m_int_state[0], m_int_state[1], m_int_state[2], + m_int_state[3], m_int_state[4], m_int_state[5])); // loop over all interrupt sources for (i = 0; i < 6; i++) @@ -300,7 +300,7 @@ int z80scc_device::z80daisy_irq_state() //------------------------------------------------- -// z80daisy_irq_ack - interrupt acknowledge +// z80daisy_irq_ack - interrupt acknowledge //------------------------------------------------- int z80scc_device::z80daisy_irq_ack() @@ -333,7 +333,7 @@ int z80scc_device::z80daisy_irq_ack() //------------------------------------------------- -// z80daisy_irq_reti - return from interrupt +// z80daisy_irq_reti - return from interrupt //------------------------------------------------- void z80scc_device::z80daisy_irq_reti() @@ -360,7 +360,7 @@ void z80scc_device::z80daisy_irq_reti() //------------------------------------------------- -// check_interrupts - +// check_interrupts - //------------------------------------------------- void z80scc_device::check_interrupts() @@ -372,7 +372,7 @@ void z80scc_device::check_interrupts() //------------------------------------------------- -// reset_interrupts - +// reset_interrupts - //------------------------------------------------- void z80scc_device::reset_interrupts() @@ -394,24 +394,24 @@ UINT8 z80scc_device::modify_vector(UINT8 vec, int i, UINT8 src) Interrupt Vector Modification V3 V2 V1 Status High/Status Low =0 V4 V5 V6 Status High/Status Low =1 - 0 0 0 Ch B Transmit Buffer Empty - 0 0 1 Ch B External/Status Change - 0 1 0 Ch B Receive Char. Available - 0 1 1 Ch B Special Receive Condition - 1 0 0 Ch A Transmit Buffer Empty - 1 0 1 Ch A External/Status Change - 1 1 0 Ch A Receive Char. Available - 1 1 1 Ch A Special Receive Condition + 0 0 0 Ch B Transmit Buffer Empty + 0 0 1 Ch B External/Status Change + 0 1 0 Ch B Receive Char. Available + 0 1 1 Ch B Special Receive Condition + 1 0 0 Ch A Transmit Buffer Empty + 1 0 1 Ch A External/Status Change + 1 1 0 Ch A Receive Char. Available + 1 1 1 Ch A Special Receive Condition */ // Add channel offset according to table above - src |= (i == CHANNEL_A ? 0x04 : 0x00 ); + src |= (i == CHANNEL_A ? 0x04 : 0x00 ); // Modify vector according to Hi/lo bit of WR9 if (m_chanA->m_wr9 & z80scc_channel::WR9_BIT_SHSL) // Affect V4-V6 { vec |= src << 4; } - else // Affect V1-V3 + else // Affect V1-V3 { vec |= src << 1; } @@ -420,7 +420,7 @@ UINT8 z80scc_device::modify_vector(UINT8 vec, int i, UINT8 src) //------------------------------------------------- -// trigger_interrupt - +// trigger_interrupt - //------------------------------------------------- void z80scc_device::trigger_interrupt(int index, int state) { @@ -438,7 +438,7 @@ void z80scc_device::trigger_interrupt(int index, int state) LOG(("Master Interrupt Enable is not set, blocking attempt to interrupt\n")); return; } - + switch(state) { case z80scc_channel::INT_RECEIVE: @@ -477,13 +477,13 @@ void z80scc_device::trigger_interrupt(int index, int state) logerror("Attempt to trigger interrupt of unknown origin blocked: %02x on channel %c\n", state, 'A' + index); return; } - + // Vector modification requested? if (m_chanA->m_wr9 & z80scc_channel::WR9_BIT_VIS) { vector = modify_vector(vector, index, source); } - + //LOG(("Z80SCC \"%s\": %c : Interrupt Request %u\n", tag(), 'A' + index, state)); // update vector register // TODO: What if interrupts are nested? May we loose the modified vector or even get the wrong one? @@ -500,20 +500,20 @@ void z80scc_device::trigger_interrupt(int index, int state) */ // Add channel offset to priority according to table above priority = prio_level + (index == CHANNEL_A ? 3 : 0 ); - + // trigger interrupt m_int_state[priority] |= Z80_DAISY_INT; - + // Based on the fact that prio levels are aligned with the bitorder of rr3 we can do this... m_chanA->m_rr3 |= (prio_level << (index == CHANNEL_A ? 3 : 0 )); - + // check for interrupt check_interrupts(); } //------------------------------------------------- -// m1_r - interrupt acknowledge +// m1_r - interrupt acknowledge //------------------------------------------------- int z80scc_device::m1_r() @@ -523,7 +523,7 @@ int z80scc_device::m1_r() //------------------------------------------------- -// cd_ba_r - Universal Bus read +// cd_ba_r - Universal Bus read //------------------------------------------------- READ8_MEMBER( z80scc_device::cd_ba_r ) { @@ -537,28 +537,28 @@ READ8_MEMBER( z80scc_device::cd_ba_r ) logerror("Z80SCC cd_ba_r not supported by this device variant, you should probably use combinations of c*_r/w and d*_r/w (see z80scc.h)\n"); return 0; } - - // LOG(("z80scc_device::cd_ba_r ba:%02x cd:%02x\n", ba, cd)); + + // LOG(("z80scc_device::cd_ba_r ba:%02x cd:%02x\n", ba, cd)); return cd ? channel->control_read() : channel->data_read(); } //------------------------------------------------- -// cd_ba_w - Universal Bus write +// cd_ba_w - Universal Bus write //------------------------------------------------- WRITE8_MEMBER( z80scc_device::cd_ba_w ) { int ba = BIT(offset, 0); int cd = BIT(offset, 1); z80scc_channel *channel = ba ? m_chanB : m_chanA; - + /* Expell non-Universal Bus variants */ if ( !(m_variant & SET_Z85X3X) ) { logerror("Z80SCC cd_ba_w not supported by this device variant, you should probably use combinations of c*_r/w and d*_r/w (see z80scc.h)\n"); return; } - - // LOG(("z80scc_device::cd_ba_w ba:%02x cd:%02x\n", ba, cd)); + + // LOG(("z80scc_device::cd_ba_w ba:%02x cd:%02x\n", ba, cd)); if (cd) channel->control_write(data); else @@ -567,7 +567,7 @@ WRITE8_MEMBER( z80scc_device::cd_ba_w ) //------------------------------------------------- -// ba_cd_r - Universal Bus read +// ba_cd_r - Universal Bus read //------------------------------------------------- READ8_MEMBER( z80scc_device::ba_cd_r ) @@ -575,21 +575,21 @@ READ8_MEMBER( z80scc_device::ba_cd_r ) int ba = BIT(offset, 1); int cd = BIT(offset, 0); z80scc_channel *channel = ba ? m_chanB : m_chanA; - + /* Expell non-Universal Bus variants */ if ( !(m_variant & SET_Z85X3X) ) { logerror("Z80SCC ba_cd_r not supported by this device variant, you should probably use combinations of c*_r/w and d*_r/w (see z80scc.h)\n"); return 0; } - - // LOG(("z80scc_device::ba_cd_r ba:%02x cd:%02x\n", ba, cd)); + + // LOG(("z80scc_device::ba_cd_r ba:%02x cd:%02x\n", ba, cd)); return cd ? channel->control_read() : channel->data_read(); } //------------------------------------------------- -// ba_cd_w - +// ba_cd_w - //------------------------------------------------- WRITE8_MEMBER( z80scc_device::ba_cd_w ) @@ -597,14 +597,14 @@ WRITE8_MEMBER( z80scc_device::ba_cd_w ) int ba = BIT(offset, 1); int cd = BIT(offset, 0); z80scc_channel *channel = ba ? m_chanB : m_chanA; - + /* Expell non-Universal Bus variants */ if ( !(m_variant & SET_Z85X3X) ) { logerror("Z80SCC ba_cd_w not supported by this device variant, you should probably use combinations of c*_r/w and d*_r/w (see z80scc.h)\n"); return; } - + LOG(("z80scc_device::ba_cd_w ba:%02x cd:%02x\n", ba, cd)); if (cd) @@ -614,11 +614,11 @@ WRITE8_MEMBER( z80scc_device::ba_cd_w ) } //************************************************************************** -// SCC CHANNEL +// SCC CHANNEL //************************************************************************** //------------------------------------------------- -// SCC_channel - constructor +// SCC_channel - constructor //------------------------------------------------- z80scc_channel::z80scc_channel(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) @@ -641,11 +641,11 @@ z80scc_channel::z80scc_channel(const machine_config &mconfig, const char *tag, d LOG(("%s\n",FUNCNAME)); // Reset all registers - m_rr0 = m_rr1 = m_rr2 = m_rr3 = m_rr4 = m_rr5 = m_rr6 = m_rr7 = m_rr8 + m_rr0 = m_rr1 = m_rr2 = m_rr3 = m_rr4 = m_rr5 = m_rr6 = m_rr7 = m_rr8 = m_rr9 = m_rr10 = m_rr11 = m_rr12 = m_rr13 = m_rr14 = m_rr15 = 0; - m_wr0 = m_wr1 = m_wr2 = m_wr3 = m_wr4 = m_wr5 = m_wr6 = m_wr7 = m_wr8 + m_wr0 = m_wr1 = m_wr2 = m_wr3 = m_wr4 = m_wr5 = m_wr6 = m_wr7 = m_wr8 = m_wr9 = m_wr10 = m_wr11 = m_wr12 = m_wr13 = m_wr14 = m_wr15 = 0; - + for (int i = 0; i < 3; i++) // TODO adapt to SCC fifos { m_rx_data_fifo[i] = 0; @@ -655,7 +655,7 @@ z80scc_channel::z80scc_channel(const machine_config &mconfig, const char *tag, d //------------------------------------------------- -// start - channel startup +// start - channel startup //------------------------------------------------- void z80scc_channel::device_start() @@ -665,10 +665,10 @@ void z80scc_channel::device_start() m_index = m_uart->get_channel_index(this); m_uart->m_wr0_ptrbits = 0; - + m_rx_fifo_sz = (m_uart->m_variant & SET_ESCC) ? 8 : 3; m_rx_fifo_wp = m_rx_fifo_rp = 0; - + // state saving save_item(NAME(m_rr0)); save_item(NAME(m_rr1)); @@ -725,7 +725,7 @@ void z80scc_channel::device_start() //------------------------------------------------- -// reset - reset channel status +// reset - reset channel status //------------------------------------------------- void z80scc_channel::device_reset() @@ -737,24 +737,24 @@ void z80scc_channel::device_reset() transmit_register_reset(); // Soft/Channel Reset values according to SCC users manual - m_wr0 = 0x00; + m_wr0 = 0x00; m_wr1 &= 0x24; m_wr3 &= 0x01; m_wr4 |= 0x04; m_wr5 &= 0x61; if (m_uart->m_variant & (z80scc_device::TYPE_SCC85C30 | SET_ESCC)) m_wr7 = 0x20; - m_wr9 &= 0xdf; // WR9 has a different hard reset value + m_wr9 &= 0xdf; // WR9 has a different hard reset value m_wr10 &= 0x60; // WR10 has a different hard reset value m_wr11 &= 0xff; // WR11 has a different hard reset value m_wr14 &= 0xc3; // WR14 has a different hard reset value m_wr14 |= 0x20; - m_wr15 = 0xf8; + m_wr15 = 0xf8; m_rr0 &= 0xfc; m_rr0 |= 0x44; m_rr1 &= 0x07; m_rr1 |= 0x06; - m_rr3 = 0x00; + m_rr3 = 0x00; m_rr10 &= 0x40; #if 1 // old reset code @@ -786,7 +786,7 @@ void z80scc_channel::device_timer(emu_timer &timer, device_timer_id id, int para //------------------------------------------------- -// tra_callback - +// tra_callback - //------------------------------------------------- void z80scc_channel::tra_callback() @@ -812,7 +812,7 @@ void z80scc_channel::tra_callback() else if (!is_transmit_register_empty()) { int db = transmit_register_get_data_bit(); - + LOG(("%" I64FMT "d %s() \"%s \"Channel %c transmit data bit %d m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, db, m_wr5)); // transmit data if (m_index == z80scc_device::CHANNEL_A) @@ -829,7 +829,7 @@ void z80scc_channel::tra_callback() //------------------------------------------------- -// tra_complete - +// tra_complete - //------------------------------------------------- void z80scc_channel::tra_complete() @@ -880,7 +880,7 @@ void z80scc_channel::tra_complete() //------------------------------------------------- -// rcv_callback - +// rcv_callback - //------------------------------------------------- void z80scc_channel::rcv_callback() @@ -900,7 +900,7 @@ void z80scc_channel::rcv_callback() //------------------------------------------------- -// rcv_complete - +// rcv_complete - //------------------------------------------------- void z80scc_channel::rcv_complete() @@ -915,7 +915,7 @@ void z80scc_channel::rcv_complete() //------------------------------------------------- -// get_clock_mode - get clock divisor +// get_clock_mode - get clock divisor //------------------------------------------------- int z80scc_channel::get_clock_mode() @@ -924,10 +924,10 @@ int z80scc_channel::get_clock_mode() switch (m_wr4 & WR4_CLOCK_RATE_MASK) { - case WR4_CLOCK_RATE_X1: clocks = 1; break; - case WR4_CLOCK_RATE_X16: clocks = 16; break; - case WR4_CLOCK_RATE_X32: clocks = 32; break; - case WR4_CLOCK_RATE_X64: clocks = 64; break; + case WR4_CLOCK_RATE_X1: clocks = 1; break; + case WR4_CLOCK_RATE_X16: clocks = 16; break; + case WR4_CLOCK_RATE_X32: clocks = 32; break; + case WR4_CLOCK_RATE_X64: clocks = 64; break; } return clocks; @@ -955,7 +955,7 @@ void z80scc_channel::set_rts(int state) void z80scc_channel::update_rts() { -// LOG(("%s(%d) \"%s\": %c \n", FUNCNAME, state, m_owner->tag(), 'A' + m_index)); +// LOG(("%s(%d) \"%s\": %c \n", FUNCNAME, state, m_owner->tag(), 'A' + m_index)); if (m_wr5 & WR5_RTS) { // when the RTS bit is set, the _RTS output goes low @@ -973,7 +973,7 @@ void z80scc_channel::update_rts() } //------------------------------------------------- -// get_stop_bits - get number of stop bits +// get_stop_bits - get number of stop bits //------------------------------------------------- device_serial_interface::stop_bits_t z80scc_channel::get_stop_bits() @@ -990,7 +990,7 @@ device_serial_interface::stop_bits_t z80scc_channel::get_stop_bits() //------------------------------------------------- -// get_rx_word_length - get receive word length +// get_rx_word_length - get receive word length //------------------------------------------------- int z80scc_channel::get_rx_word_length() @@ -999,10 +999,10 @@ int z80scc_channel::get_rx_word_length() switch (m_wr3 & WR3_RX_WORD_LENGTH_MASK) { - case WR3_RX_WORD_LENGTH_5: bits = 5; break; - case WR3_RX_WORD_LENGTH_6: bits = 6; break; - case WR3_RX_WORD_LENGTH_7: bits = 7; break; - case WR3_RX_WORD_LENGTH_8: bits = 8; break; + case WR3_RX_WORD_LENGTH_5: bits = 5; break; + case WR3_RX_WORD_LENGTH_6: bits = 6; break; + case WR3_RX_WORD_LENGTH_7: bits = 7; break; + case WR3_RX_WORD_LENGTH_8: bits = 8; break; } return bits; @@ -1010,7 +1010,7 @@ int z80scc_channel::get_rx_word_length() //------------------------------------------------- -// get_tx_word_length - get transmit word length +// get_tx_word_length - get transmit word length //------------------------------------------------- int z80scc_channel::get_tx_word_length() @@ -1019,10 +1019,10 @@ int z80scc_channel::get_tx_word_length() switch (m_wr5 & WR5_TX_WORD_LENGTH_MASK) { - case WR5_TX_WORD_LENGTH_5: bits = 5; break; - case WR5_TX_WORD_LENGTH_6: bits = 6; break; - case WR5_TX_WORD_LENGTH_7: bits = 7; break; - case WR5_TX_WORD_LENGTH_8: bits = 8; break; + case WR5_TX_WORD_LENGTH_5: bits = 5; break; + case WR5_TX_WORD_LENGTH_6: bits = 6; break; + case WR5_TX_WORD_LENGTH_7: bits = 7; break; + case WR5_TX_WORD_LENGTH_8: bits = 8; break; } return bits; @@ -1231,7 +1231,7 @@ UINT8 z80scc_channel::do_sccreg_rr15() } //------------------------------------------------- -// control_read - read control register +// control_read - read control register //------------------------------------------------- UINT8 z80scc_channel::control_read() { @@ -1239,7 +1239,7 @@ UINT8 z80scc_channel::control_read() int reg = m_uart->m_wr0_ptrbits; //m_wr0; int regmask = (WR0_REGISTER_MASK | (m_uart->m_wr0_ptrbits & WR0_POINT_HIGH)); - // LOG(("%s(%02x) reg %02x, regmask %02x, WR0 %02x\n", __func__, data, reg, regmask, m_wr0)); + // LOG(("%s(%02x) reg %02x, regmask %02x, WR0 %02x\n", __func__, data, reg, regmask, m_wr0)); m_uart->m_wr0_ptrbits = 0; reg &= regmask; @@ -1252,23 +1252,23 @@ UINT8 z80scc_channel::control_read() /* TODO. Sort out 80X30 limitations in register access */ switch (reg) { - case REG_RR0_STATUS: data = do_sccreg_rr0(); break; // TODO: verify handling of SCC specific bits: D6 and D1 - case REG_RR1_SPEC_RCV_COND: data = do_sccreg_rr1(); break; + case REG_RR0_STATUS: data = do_sccreg_rr0(); break; // TODO: verify handling of SCC specific bits: D6 and D1 + case REG_RR1_SPEC_RCV_COND: data = do_sccreg_rr1(); break; case REG_RR2_INTERRUPT_VECT: data = do_sccreg_rr2(); break; // Channel dependent and SCC specific handling compared to SIO /* registers 3-7 are specific to SCC. TODO: Check variant and log/stop misuse */ case REG_RR3_INTERUPPT_PEND: data = do_sccreg_rr3(); break; - case REG_RR4_WR4_OR_RR0: data = do_sccreg_rr4(); break; - case REG_RR5_WR5_OR_RR0: data = do_sccreg_rr5(); break; - case REG_RR6_LSB_OR_RR2: data = do_sccreg_rr6(); break; - case REG_RR7_MSB_OR_RR3: data = do_sccreg_rr7(); break; + case REG_RR4_WR4_OR_RR0: data = do_sccreg_rr4(); break; + case REG_RR5_WR5_OR_RR0: data = do_sccreg_rr5(); break; + case REG_RR6_LSB_OR_RR2: data = do_sccreg_rr6(); break; + case REG_RR7_MSB_OR_RR3: data = do_sccreg_rr7(); break; /* registers 8-15 are specific to SCC */ - case REG_RR8_RECEIVE_DATA: data = data_read(); break; - case REG_RR9_WR3_OR_RR13: data = do_sccreg_rr9(); break; - case REG_RR10_MISC_STATUS: data = do_sccreg_rr10(); break; - case REG_RR11_WR10_OR_RR15: data = do_sccreg_rr11(); break; + case REG_RR8_RECEIVE_DATA: data = data_read(); break; + case REG_RR9_WR3_OR_RR13: data = do_sccreg_rr9(); break; + case REG_RR10_MISC_STATUS: data = do_sccreg_rr10(); break; + case REG_RR11_WR10_OR_RR15: data = do_sccreg_rr11(); break; case REG_RR12_LO_TIME_CONST: data = do_sccreg_rr12(); break; case REG_RR13_HI_TIME_CONST: data = do_sccreg_rr13(); break; - case REG_RR14_WR7_OR_R10: data = do_sccreg_rr14(); break; + case REG_RR14_WR7_OR_R10: data = do_sccreg_rr14(); break; case REG_RR15_WR15_EXT_STAT: data = do_sccreg_rr15(); break; default: logerror("Z80SCC \"%s\" %s: %c : Unsupported RRx register:%02x\n", m_owner->tag(), __func__, 'A' + m_index, reg); @@ -1308,7 +1308,7 @@ void z80scc_channel::do_sccreg_wr0(UINT8 data) m_wr0 = data; m_uart->m_wr0_ptrbits = data & WR0_REGISTER_MASK; - /* Sort out SCC specific behaviours from legacy SIO behaviour */ + /* Sort out SCC specific behaviours from legacy SIO behaviour */ /* WR0_Z_* are Z80X30 specific commands */ switch (data & WR0_COMMAND_MASK) { @@ -1340,7 +1340,7 @@ void z80scc_channel::do_sccreg_wr0(UINT8 data) External/Status interrupt. However, if this second status change does not persist (there are two transitions), another interrupt is not generated. Exceptions to this rule are detailed in the RR0 description.*/ - // do_sccreg_wr0(data); + // do_sccreg_wr0(data); if (!m_zc) { m_rr0 |= RR0_ZC; @@ -1441,21 +1441,21 @@ void z80scc_channel::do_sccreg_wr1(UINT8 data) LOG(("- Wait/Ready Enable %u\n", (data & WR1_WRDY_ENABLE) ? 1 : 0)); LOG(("- Wait/Ready Function %s\n", (data & WR1_WRDY_FUNCTION) ? "Ready" : "Wait")); LOG(("- Wait/Ready on %s\n", (data & WR1_WRDY_ON_RX_TX) ? "Receive" : "Transmit")); - + switch (data & WR1_RX_INT_MODE_MASK) { case WR1_RX_INT_DISABLE: LOG(("- Receiver Interrupt Disabled\n")); break; - + case WR1_RX_INT_FIRST: LOG(("- Receiver Interrupt on First Character\n")); break; - + case WR1_RX_INT_ALL_PARITY: LOG(("- Receiver Interrupt on All Characters, Parity Affects Vector\n")); break; - + case WR1_RX_INT_ALL: LOG(("- Receiver Interrupt on All Characters\n")); break; @@ -1472,7 +1472,7 @@ void z80scc_channel::do_sccreg_wr2(UINT8 data) m_wr2 = data; m_uart->m_chanA->m_rr2 = data; m_uart->m_chanB->m_rr2 = data; /* TODO: Sort out the setting of ChanB depending on bits in WR9 */ - + m_uart->check_interrupts(); } @@ -1589,13 +1589,13 @@ void z80scc_channel::do_sccreg_wr11(UINT8 data) /SYNC pin is unavailable for other use. The /SYNC signal is forced to zero internally. A hardware reset forces /NO XTAL. (At least 20 ms should be allowed after this bit is set to allow the oscillator to stabilize.)*/ - LOG((" Clock type %s\n", data & WR11_RCVCLK_TYPE ? "Crystal oscillator between RTxC and /SYNC pins" : "TTL level on RTxC pin")); + LOG((" Clock type %s\n", data & WR11_RCVCLK_TYPE ? "Crystal oscillator between RTxC and /SYNC pins" : "TTL level on RTxC pin")); /*Bits 6 and 5: Receiver Clock select bits 1 and 0 These bits determine the source of the receive clock as listed below. They do not interfere with any of the modes of operation in the SCC, but simply control a multiplexer just before the internal receive clock input. A hardware reset forces the receive clock to come from the /RTxC pin.*/ - LOG((" Receive clock source is: ")); + LOG((" Receive clock source is: ")); switch (data & WR11_RCVCLK_SRC_MASK) { case WR11_RCVCLK_SRC_RTXC: LOG(("RTxC\n")); break; @@ -1611,7 +1611,7 @@ void z80scc_channel::do_sccreg_wr11(UINT8 data) degrees the output of the DPLL used by the receiver. This makes the received and transmitted bit cells occur simultaneously, neglecting delays. A hardware reset selects the /TRxC pin as the source of the transmit clocks.*/ - LOG((" Transmit clock source is: ")); + LOG((" Transmit clock source is: ")); switch (data & WR11_TRACLK_SRC_MASK) { case WR11_TRACLK_SRC_RTXC: LOG(("RTxC\n")); break; @@ -1626,7 +1626,7 @@ void z80scc_channel::do_sccreg_wr11(UINT8 data) transmit clock is programmed to come from the /TRxC pin, /TRxC is an input, regardless of the state of this bit. The /TRxC pin is also an input if this bit is set to 0. A hardware reset forces this bit to 0.*/ - LOG((" TRxC pin is %s\n", data & WR11_TRXC_DIRECTION ? "Output" : "Input")); + LOG((" TRxC pin is %s\n", data & WR11_TRXC_DIRECTION ? "Output" : "Input")); /*Bits 1 and 0: /TRxC Output Source select bits 1 and 0 These bits determine the signal to be echoed out of the SCC via the /TRxC pin as listed in Table on page 167. No signal is produced if /TRxC has been programmed as the source of either the @@ -1634,7 +1634,7 @@ void z80scc_channel::do_sccreg_wr11(UINT8 data) If the XTAL oscillator output is programmed to be echoed, and the XTAL oscillator is not enabled, the /TRxC pin goes High. The DPLL signal that is echoed is the DPLL signal used by the receiver. Hardware reset selects the XTAL oscillator as the output source*/ - LOG((" TRxC clock source is: ")); + LOG((" TRxC clock source is: ")); switch (data & WR11_TRXSRC_SRC_MASK) { case WR11_TRXSRC_SRC_XTAL: LOG(("the Oscillator\n")); break; @@ -1656,9 +1656,9 @@ void z80scc_channel::do_sccreg_wr11(UINT8 data) the desired rate in bits per second and the BR clock period in seconds. This formula is derived because the counter decrements from N down to zero-plus-one-cycle for reloading the time constant. This is then fed to a toggle flip-flop to make the output a square wave. - + Time Constant = Clock Frequency / (2 * Desired Rate * Baud Rate Clock Period) - 2 - + */ void z80scc_channel::do_sccreg_wr12(UINT8 data) { @@ -1670,7 +1670,7 @@ void z80scc_channel::do_sccreg_wr12(UINT8 data) void z80scc_channel::do_sccreg_wr13(UINT8 data) { m_wr13 = data; - LOG(("Z80SCC \"%s\": %c : %s %02x High byte of Time Constant for Baudrate generator - not implemented \n", m_owner->tag(), 'A' + m_index, __func__, data)); + LOG(("Z80SCC \"%s\": %c : %s %02x High byte of Time Constant for Baudrate generator - not implemented \n", m_owner->tag(), 'A' + m_index, __func__, data)); } /* @@ -1743,14 +1743,14 @@ void z80scc_channel::do_sccreg_wr14(UINT8 data) interrupt. This is true, even if an External/Status condition is pending at the time the bit is set*/ void z80scc_channel::do_sccreg_wr15(UINT8 data) { - LOG(("%s(%d) \"%s\": %c : External/Status Control Bits - not implemented\n", - FUNCNAME, data, m_owner->tag(), 'A' + m_index)); + LOG(("%s(%d) \"%s\": %c : External/Status Control Bits - not implemented\n", + FUNCNAME, data, m_owner->tag(), 'A' + m_index)); m_wr15 = data; } /*TODO: Z80X30 Register Access ---------------------------- -The Shift Right/Shift Left bit in the Channel B WR0 controls which bits are decoded to form the register +The Shift Right/Shift Left bit in the Channel B WR0 controls which bits are decoded to form the register address. See do_sccreg_wr0() for details */ /*Z85X30 Register Access @@ -1771,7 +1771,7 @@ The fact that the pointer bits are reset to 0, unless explicitly set otherwise, RR0 may also be accessed in a single cycle. That is, it is not necessary to write the pointer bits with 0 before accessing WR0 or RR0.*/ //------------------------------------------------- -// control_write - write control register +// control_write - write control register //------------------------------------------------- void z80scc_channel::control_write(UINT8 data) @@ -1782,21 +1782,21 @@ void z80scc_channel::control_write(UINT8 data) m_uart->m_wr0_ptrbits = 0; // The "Point High" command is only valid for one access reg &= regmask; - + if (reg != 0) { // mask out register index m_wr0 &= ~regmask; } - + LOG(("\n%s(%02x) reg %02x, regmask %02x\n", FUNCNAME, data, reg, regmask)); - + /* TODO. Sort out 80X30 & other SCC variants limitations in register access */ switch (reg) { - case REG_WR0_COMMAND_REGPT: do_sccreg_wr0(data); ;break; + case REG_WR0_COMMAND_REGPT: do_sccreg_wr0(data); ;break; case REG_WR1_INT_DMA_ENABLE: do_sccreg_wr1(data); m_uart->check_interrupts(); break; - case REG_WR2_INT_VECTOR: do_sccreg_wr2(data); break; + case REG_WR2_INT_VECTOR: do_sccreg_wr2(data); break; case REG_WR3_RX_CONTROL: do_sccreg_wr3(data); update_serial(); @@ -1816,13 +1816,13 @@ void z80scc_channel::control_write(UINT8 data) break; case REG_WR6_SYNC_OR_SDLC_A: do_sccreg_wr6(data); break; case REG_WR7_SYNC_OR_SDLC_F: do_sccreg_wr7(data); break; - case REG_WR8_TRANSMIT_DATA: do_sccreg_wr8(data); break; + case REG_WR8_TRANSMIT_DATA: do_sccreg_wr8(data); break; case REG_WR9_MASTER_INT_CTRL: do_sccreg_wr9(data); break; case REG_WR10_MSC_RX_TX_CTRL: do_sccreg_wr10(data); break; - case REG_WR11_CLOCK_MODES: do_sccreg_wr11(data); break; - case REG_WR12_LO_BAUD_GEN: do_sccreg_wr12(data); break; - case REG_WR13_HI_BAUD_GEN: do_sccreg_wr13(data); break; - case REG_WR14_MISC_CTRL: do_sccreg_wr14(data); break; + case REG_WR11_CLOCK_MODES: do_sccreg_wr11(data); break; + case REG_WR12_LO_BAUD_GEN: do_sccreg_wr12(data); break; + case REG_WR13_HI_BAUD_GEN: do_sccreg_wr13(data); break; + case REG_WR14_MISC_CTRL: do_sccreg_wr14(data); break; case REG_WR15_EXT_ST_INT_CTRL:do_sccreg_wr15(data); break; default: logerror("Z80SCC \"%s\": %c : Unsupported WRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg); @@ -1831,7 +1831,7 @@ void z80scc_channel::control_write(UINT8 data) //------------------------------------------------- -// data_read - read data register from fifo +// data_read - read data register from fifo //------------------------------------------------- UINT8 z80scc_channel::data_read() @@ -1855,13 +1855,13 @@ UINT8 z80scc_channel::data_read() FIFO to preserve the status, it is necessary to issue the Error Reset command to unlock it. Only the exit location of the FIFO is locked allowing more data to be received into the other bytes of the Receive FIFO.*/ - + // load data from the FIFO data = m_rx_fifo_rp_data(); - + // load error status from the FIFO m_rr1 = (m_rr1 & ~(RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR)) | m_rx_error_fifo[m_rx_fifo_rp]; - + // trigger interrup and lock the fifo if an error is present if (m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR)) { @@ -1925,13 +1925,13 @@ void z80scc_channel::m_rx_fifo_rp_step() } } -READ8_MEMBER (z80scc_device::da_r) { return m_chanA->data_read(); } +READ8_MEMBER (z80scc_device::da_r) { return m_chanA->data_read(); } WRITE8_MEMBER (z80scc_device::da_w) { m_chanA->data_write(data); } -READ8_MEMBER (z80scc_device::db_r) { return m_chanB->data_read(); } +READ8_MEMBER (z80scc_device::db_r) { return m_chanB->data_read(); } WRITE8_MEMBER (z80scc_device::db_w) { m_chanB->data_write(data); } //------------------------------------------------- -// data_write - write data register +// data_write - write data register //------------------------------------------------- void z80scc_channel::data_write(UINT8 data) { @@ -1962,7 +1962,7 @@ void z80scc_channel::data_write(UINT8 data) //------------------------------------------------- -// receive_data - receive data word into fifo +// receive_data - receive data word into fifo //------------------------------------------------- void z80scc_channel::receive_data(UINT8 data) @@ -2013,7 +2013,7 @@ void z80scc_channel::receive_data(UINT8 data) //------------------------------------------------- -// cts_w - clear to send handler +// cts_w - clear to send handler //------------------------------------------------- WRITE_LINE_MEMBER( z80scc_channel::cts_w ) @@ -2052,7 +2052,7 @@ WRITE_LINE_MEMBER( z80scc_channel::cts_w ) //------------------------------------------------- -// dcd_w - data carrier detected handler +// dcd_w - data carrier detected handler //------------------------------------------------- WRITE_LINE_MEMBER( z80scc_channel::dcd_w ) @@ -2090,7 +2090,7 @@ WRITE_LINE_MEMBER( z80scc_channel::dcd_w ) //------------------------------------------------- -// ri_w - ring indicator handler +// ri_w - ring indicator handler //------------------------------------------------- WRITE_LINE_MEMBER( z80scc_channel::ri_w ) @@ -2122,7 +2122,7 @@ WRITE_LINE_MEMBER( z80scc_channel::ri_w ) } //------------------------------------------------- -// sync_w - sync handler +// sync_w - sync handler //------------------------------------------------- WRITE_LINE_MEMBER( z80scc_channel::sync_w ) { @@ -2130,7 +2130,7 @@ WRITE_LINE_MEMBER( z80scc_channel::sync_w ) } //------------------------------------------------- -// rxc_w - receive clock +// rxc_w - receive clock //------------------------------------------------- WRITE_LINE_MEMBER( z80scc_channel::rxc_w ) { @@ -2143,17 +2143,17 @@ WRITE_LINE_MEMBER( z80scc_channel::rxc_w ) else if(state) { rx_clock_w(m_rx_clock < clocks/2); - + m_rx_clock++; if (m_rx_clock == clocks) m_rx_clock = 0; - + } } } //------------------------------------------------- -// txc_w - transmit clock +// txc_w - transmit clock //------------------------------------------------- WRITE_LINE_MEMBER( z80scc_channel::txc_w ) { @@ -2166,7 +2166,7 @@ WRITE_LINE_MEMBER( z80scc_channel::txc_w ) else if(state) { tx_clock_w(m_tx_clock < clocks/2); - + m_tx_clock++; if (m_tx_clock == clocks) m_tx_clock = 0; @@ -2175,7 +2175,7 @@ WRITE_LINE_MEMBER( z80scc_channel::txc_w ) } //------------------------------------------------- -// update_serial - +// update_serial - //------------------------------------------------- void z80scc_channel::update_serial() { @@ -2202,18 +2202,18 @@ void z80scc_channel::update_serial() if (m_rxc > 0) { set_rcv_rate(m_rxc / clocks); - LOG((" - Receiver clock: %d mode: %d rate: %d/%xh\n", m_rxc, clocks, m_rxc / clocks, m_rxc / clocks)); + LOG((" - Receiver clock: %d mode: %d rate: %d/%xh\n", m_rxc, clocks, m_rxc / clocks, m_rxc / clocks)); } if (m_txc > 0) { set_tra_rate(m_txc / clocks); - LOG((" - Transmit clock: %d mode: %d rate: %d/%xh\n", m_rxc, clocks, m_rxc / clocks, m_rxc / clocks)); + LOG((" - Transmit clock: %d mode: %d rate: %d/%xh\n", m_rxc, clocks, m_rxc / clocks, m_rxc / clocks)); } } //------------------------------------------------- -// set_dtr - +// set_dtr - //------------------------------------------------- void z80scc_channel::set_dtr(int state) { @@ -2229,8 +2229,8 @@ void z80scc_channel::set_dtr(int state) //------------------------------------------------- -// write_rx - called by terminal through rs232/diserial -// when character is sent to board +// write_rx - called by terminal through rs232/diserial +// when character is sent to board //------------------------------------------------- WRITE_LINE_MEMBER(z80scc_channel::write_rx) { diff --git a/src/devices/machine/z80scc.h b/src/devices/machine/z80scc.h index 5e21b85bff7..800a9dc3a0f 100644 --- a/src/devices/machine/z80scc.h +++ b/src/devices/machine/z80scc.h @@ -2,7 +2,7 @@ // copyright-holders:Joakim Larsson Edstrom /*************************************************************************** - Z80-SCC Serial Communications Controller emulation + Z80-SCC Serial Communications Controller emulation **************************************************************************** _____ _____ _____ _____ @@ -38,7 +38,7 @@ #include "cpu/z80/z80daisy.h" //************************************************************************** -// DEVICE CONFIGURATION MACROS +// DEVICE CONFIGURATION MACROS //************************************************************************** #define MCFG_Z80SCC_ADD(_tag, _clock, _rxa, _txa, _rxb, _txb) \ @@ -101,7 +101,7 @@ //************************************************************************** -// TYPE DEFINITIONS +// TYPE DEFINITIONS //************************************************************************** // ======================> z80scc_channel @@ -187,7 +187,7 @@ public: int m_txc; // Register state - // read registers enum + // read registers enum UINT8 m_rr0; // REG_RR0_STATUS UINT8 m_rr1; // REG_RR1_SPEC_RCV_COND UINT8 m_rr2; // REG_RR2_INTERRUPT_VECT @@ -197,7 +197,7 @@ public: UINT8 m_rr6; // REG_RR6_LSB_OR_RR2 UINT8 m_rr7; // REG_RR7_MSB_OR_RR3 UINT8 m_rr8; // REG_RR8_RECEIVE_DATA - UINT8 m_rr9; // REG_RR9_WR3_OR_RR13 + UINT8 m_rr9; // REG_RR9_WR3_OR_RR13 UINT8 m_rr10; // REG_RR10_MISC_STATUS UINT8 m_rr11; // REG_RR11_WR10_OR_RR15 UINT8 m_rr12; // REG_RR12_LO_TIME_CONST @@ -205,7 +205,7 @@ public: UINT8 m_rr14; // REG_RR14_WR7_OR_R10 UINT8 m_rr15; // REG_RR15_WR15_EXT_STAT - // write registers enum + // write registers enum UINT8 m_wr0; // REG_WR0_COMMAND_REGPT UINT8 m_wr1; // REG_WR1_INT_DMA_ENABLE UINT8 m_wr2; // REG_WR2_INT_VECTOR @@ -229,241 +229,241 @@ protected: { INT_TRANSMIT = 0, INT_EXTERNAL = 1, - INT_RECEIVE = 2, - INT_SPECIAL = 3 + INT_RECEIVE = 2, + INT_SPECIAL = 3 }; // Read registers enum { - REG_RR0_STATUS = 0, // SIO - REG_RR1_SPEC_RCV_COND = 1, // SIO - REG_RR2_INTERRUPT_VECT = 2, // SIO - REG_RR3_INTERUPPT_PEND = 3, - REG_RR4_WR4_OR_RR0 = 4, - REG_RR5_WR5_OR_RR0 = 5, - REG_RR6_LSB_OR_RR2 = 6, - REG_RR7_MSB_OR_RR3 = 7, - REG_RR8_RECEIVE_DATA = 8, - REG_RR9_WR3_OR_RR13 = 9, - REG_RR10_MISC_STATUS = 10, - REG_RR11_WR10_OR_RR15 = 11, - REG_RR12_LO_TIME_CONST = 12, - REG_RR13_HI_TIME_CONST = 13, - REG_RR14_WR7_OR_R10 = 14, - REG_RR15_WR15_EXT_STAT = 15 + REG_RR0_STATUS = 0, // SIO + REG_RR1_SPEC_RCV_COND = 1, // SIO + REG_RR2_INTERRUPT_VECT = 2, // SIO + REG_RR3_INTERUPPT_PEND = 3, + REG_RR4_WR4_OR_RR0 = 4, + REG_RR5_WR5_OR_RR0 = 5, + REG_RR6_LSB_OR_RR2 = 6, + REG_RR7_MSB_OR_RR3 = 7, + REG_RR8_RECEIVE_DATA = 8, + REG_RR9_WR3_OR_RR13 = 9, + REG_RR10_MISC_STATUS = 10, + REG_RR11_WR10_OR_RR15 = 11, + REG_RR12_LO_TIME_CONST = 12, + REG_RR13_HI_TIME_CONST = 13, + REG_RR14_WR7_OR_R10 = 14, + REG_RR15_WR15_EXT_STAT = 15 }; - + // Write registers enum { - REG_WR0_COMMAND_REGPT = 0, // SIO - REG_WR1_INT_DMA_ENABLE = 1, // SIO - REG_WR2_INT_VECTOR = 2, // SIO - REG_WR3_RX_CONTROL = 3, // SIO - REG_WR4_RX_TX_MODES = 4, // SIO - REG_WR5_TX_CONTROL = 5, // SIO - REG_WR6_SYNC_OR_SDLC_A = 6, // SIO - REG_WR7_SYNC_OR_SDLC_F = 7, // SIO - REG_WR8_TRANSMIT_DATA = 8, + REG_WR0_COMMAND_REGPT = 0, // SIO + REG_WR1_INT_DMA_ENABLE = 1, // SIO + REG_WR2_INT_VECTOR = 2, // SIO + REG_WR3_RX_CONTROL = 3, // SIO + REG_WR4_RX_TX_MODES = 4, // SIO + REG_WR5_TX_CONTROL = 5, // SIO + REG_WR6_SYNC_OR_SDLC_A = 6, // SIO + REG_WR7_SYNC_OR_SDLC_F = 7, // SIO + REG_WR8_TRANSMIT_DATA = 8, REG_WR9_MASTER_INT_CTRL = 9, REG_WR10_MSC_RX_TX_CTRL = 10, - REG_WR11_CLOCK_MODES = 11, - REG_WR12_LO_BAUD_GEN = 12, - REG_WR13_HI_BAUD_GEN = 13, - REG_WR14_MISC_CTRL = 14, + REG_WR11_CLOCK_MODES = 11, + REG_WR12_LO_BAUD_GEN = 12, + REG_WR13_HI_BAUD_GEN = 13, + REG_WR14_MISC_CTRL = 14, REG_WR15_EXT_ST_INT_CTRL= 15 }; enum { - RR0_RX_CHAR_AVAILABLE = 0x01, // SIO bit - RR0_ZC = 0x02, // SCC bit - RR0_TX_BUFFER_EMPTY = 0x04, // SIO - RR0_DCD = 0x08, // SIO - RR0_RI = 0x10, // DART bit? TODO: investigate function and remove - RR0_SYNC_HUNT = 0x10, // SIO bit, not supported - RR0_CTS = 0x20, // SIO bit - RR0_TX_UNDERRUN = 0x40, // SIO bit, not supported - RR0_BREAK_ABORT = 0x80 // SIO bit, not supported + RR0_RX_CHAR_AVAILABLE = 0x01, // SIO bit + RR0_ZC = 0x02, // SCC bit + RR0_TX_BUFFER_EMPTY = 0x04, // SIO + RR0_DCD = 0x08, // SIO + RR0_RI = 0x10, // DART bit? TODO: investigate function and remove + RR0_SYNC_HUNT = 0x10, // SIO bit, not supported + RR0_CTS = 0x20, // SIO bit + RR0_TX_UNDERRUN = 0x40, // SIO bit, not supported + RR0_BREAK_ABORT = 0x80 // SIO bit, not supported }; enum { - RR1_ALL_SENT = 0x01, // SIO/SCC bit - RR1_RESIDUE_CODE_MASK = 0x0e, // SIO/SCC bits, not supported - RR1_PARITY_ERROR = 0x10, // SIO/SCC bits - RR1_RX_OVERRUN_ERROR = 0x20, // SIO/SCC bits - RR1_CRC_FRAMING_ERROR = 0x40, // SIO/SCC bits - RR1_END_OF_FRAME = 0x80 // SIO/SCC bits, not supported + RR1_ALL_SENT = 0x01, // SIO/SCC bit + RR1_RESIDUE_CODE_MASK = 0x0e, // SIO/SCC bits, not supported + RR1_PARITY_ERROR = 0x10, // SIO/SCC bits + RR1_RX_OVERRUN_ERROR = 0x20, // SIO/SCC bits + RR1_CRC_FRAMING_ERROR = 0x40, // SIO/SCC bits + RR1_END_OF_FRAME = 0x80 // SIO/SCC bits, not supported }; enum - { // TODO: overload SIO functionality - RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case) - RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B - RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B - RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B + { // TODO: overload SIO functionality + RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case) + RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B + RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B + RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B }; - + enum { - RR3_CHANB_EXT_IP = 0x01, // SCC IP pending registers - RR3_CHANB_TX_IP = 0x02, // only read in Channel A (for both channels) - RR3_CHANB_RX_IP = 0x04, // channel B return all zero - RR3_CHANA_EXT_IP = 0x08, - RR3_CHANA_TX_IP = 0x10, - RR3_CHANA_RX_IP = 0x20 + RR3_CHANB_EXT_IP = 0x01, // SCC IP pending registers + RR3_CHANB_TX_IP = 0x02, // only read in Channel A (for both channels) + RR3_CHANB_RX_IP = 0x04, // channel B return all zero + RR3_CHANA_EXT_IP = 0x08, + RR3_CHANA_TX_IP = 0x10, + RR3_CHANA_RX_IP = 0x20 }; - + enum // Universal Bus WR0 commands for 85X30 { - WR0_REGISTER_MASK = 0x07, - WR0_COMMAND_MASK = 0x38, // COMMANDS - WR0_NULL = 0x00, // 0 0 0 - WR0_POINT_HIGH = 0x08, // 0 0 1 - WR0_RESET_EXT_STATUS = 0x10, // 0 1 0 - WR0_SEND_ABORT = 0x18, // 0 1 1 - WR0_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0 - WR0_RESET_TX_INT = 0x28, // 1 0 1 - WR0_ERROR_RESET = 0x30, // 1 1 0 - WR0_RESET_HIGHEST_IUS = 0x38, // 1 1 1 - WR0_CRC_RESET_CODE_MASK = 0xc0, // RESET - WR0_CRC_RESET_NULL = 0x00, // 0 0 - WR0_CRC_RESET_RX = 0x40, // 0 1 - WR0_CRC_RESET_TX = 0x80, // 1 0 + WR0_REGISTER_MASK = 0x07, + WR0_COMMAND_MASK = 0x38, // COMMANDS + WR0_NULL = 0x00, // 0 0 0 + WR0_POINT_HIGH = 0x08, // 0 0 1 + WR0_RESET_EXT_STATUS = 0x10, // 0 1 0 + WR0_SEND_ABORT = 0x18, // 0 1 1 + WR0_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0 + WR0_RESET_TX_INT = 0x28, // 1 0 1 + WR0_ERROR_RESET = 0x30, // 1 1 0 + WR0_RESET_HIGHEST_IUS = 0x38, // 1 1 1 + WR0_CRC_RESET_CODE_MASK = 0xc0, // RESET + WR0_CRC_RESET_NULL = 0x00, // 0 0 + WR0_CRC_RESET_RX = 0x40, // 0 1 + WR0_CRC_RESET_TX = 0x80, // 1 0 WR0_CRC_RESET_TX_UNDERRUN = 0xc0 // 1 1 }; enum // ZBUS WR0 commands or 80X30 { - WR0_Z_COMMAND_MASK = 0x38, // COMMANDS - WR0_Z_NULL_1 = 0x00, // 0 0 0 - WR0_Z_NULL_2 = 0x08, // 0 0 1 - WR0_Z_RESET_EXT_STATUS = 0x10, // 0 1 0 - WR0_Z_SEND_ABORT = 0x18, // 0 1 1 - WR0_Z_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0 - WR0_Z_RESET_TX_INT = 0x28, // 1 0 1 - WR0_Z_ERROR_RESET = 0x30, // 1 1 0 - WR0_Z_RESET_HIGHEST_IUS = 0x38, // 1 1 1 - WR0_Z_SHIFT_MASK = 0x03, // SHIFT mode SDLC chan B - WR0_Z_SEL_SHFT_LEFT = 0x02, // 1 0 - WR0_Z_SEL_SHFT_RIGHT = 0x03 // 1 1 + WR0_Z_COMMAND_MASK = 0x38, // COMMANDS + WR0_Z_NULL_1 = 0x00, // 0 0 0 + WR0_Z_NULL_2 = 0x08, // 0 0 1 + WR0_Z_RESET_EXT_STATUS = 0x10, // 0 1 0 + WR0_Z_SEND_ABORT = 0x18, // 0 1 1 + WR0_Z_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0 + WR0_Z_RESET_TX_INT = 0x28, // 1 0 1 + WR0_Z_ERROR_RESET = 0x30, // 1 1 0 + WR0_Z_RESET_HIGHEST_IUS = 0x38, // 1 1 1 + WR0_Z_SHIFT_MASK = 0x03, // SHIFT mode SDLC chan B + WR0_Z_SEL_SHFT_LEFT = 0x02, // 1 0 + WR0_Z_SEL_SHFT_RIGHT = 0x03 // 1 1 }; enum { - WR1_EXT_INT_ENABLE = 0x01, - WR1_TX_INT_ENABLE = 0x02, - WR1_PARITY_IS_SPEC_COND = 0x04, - WR1_RX_INT_MODE_MASK = 0x18, - WR1_RX_INT_DISABLE = 0x00, - WR1_RX_INT_FIRST = 0x08, - WR1_RX_INT_ALL_PARITY = 0x10, // not supported - WR1_RX_INT_ALL = 0x18, - WR1_WRDY_ON_RX_TX = 0x20, // not supported - WR1_WRDY_FUNCTION = 0x40, // not supported - WR1_WRDY_ENABLE = 0x80 // not supported + WR1_EXT_INT_ENABLE = 0x01, + WR1_TX_INT_ENABLE = 0x02, + WR1_PARITY_IS_SPEC_COND = 0x04, + WR1_RX_INT_MODE_MASK = 0x18, + WR1_RX_INT_DISABLE = 0x00, + WR1_RX_INT_FIRST = 0x08, + WR1_RX_INT_ALL_PARITY = 0x10, // not supported + WR1_RX_INT_ALL = 0x18, + WR1_WRDY_ON_RX_TX = 0x20, // not supported + WR1_WRDY_FUNCTION = 0x40, // not supported + WR1_WRDY_ENABLE = 0x80 // not supported }; enum { - WR3_RX_ENABLE = 0x01, + WR3_RX_ENABLE = 0x01, WR3_SYNC_CHAR_LOAD_INHIBIT= 0x02, // not supported - WR3_ADDRESS_SEARCH_MODE = 0x04, // not supported - WR3_RX_CRC_ENABLE = 0x08, // not supported - WR3_ENTER_HUNT_PHASE = 0x10, // not supported - WR3_AUTO_ENABLES = 0x20, - WR3_RX_WORD_LENGTH_MASK = 0xc0, - WR3_RX_WORD_LENGTH_5 = 0x00, - WR3_RX_WORD_LENGTH_7 = 0x40, - WR3_RX_WORD_LENGTH_6 = 0x80, - WR3_RX_WORD_LENGTH_8 = 0xc0 + WR3_ADDRESS_SEARCH_MODE = 0x04, // not supported + WR3_RX_CRC_ENABLE = 0x08, // not supported + WR3_ENTER_HUNT_PHASE = 0x10, // not supported + WR3_AUTO_ENABLES = 0x20, + WR3_RX_WORD_LENGTH_MASK = 0xc0, + WR3_RX_WORD_LENGTH_5 = 0x00, + WR3_RX_WORD_LENGTH_7 = 0x40, + WR3_RX_WORD_LENGTH_6 = 0x80, + WR3_RX_WORD_LENGTH_8 = 0xc0 }; enum { - WR4_PARITY_ENABLE = 0x01, - WR4_PARITY_EVEN = 0x02, - WR4_STOP_BITS_MASK = 0x0c, - WR4_STOP_BITS_1 = 0x04, - WR4_STOP_BITS_1_5 = 0x08, // not supported - WR4_STOP_BITS_2 = 0x0c, - WR4_SYNC_MODE_MASK = 0x30, // not supported - WR4_SYNC_MODE_8_BIT = 0x00, // not supported - WR4_SYNC_MODE_16_BIT = 0x10, // not supported - WR4_SYNC_MODE_SDLC = 0x20, // not supported - WR4_SYNC_MODE_EXT = 0x30, // not supported - WR4_CLOCK_RATE_MASK = 0xc0, - WR4_CLOCK_RATE_X1 = 0x00, - WR4_CLOCK_RATE_X16 = 0x40, - WR4_CLOCK_RATE_X32 = 0x80, - WR4_CLOCK_RATE_X64 = 0xc0 + WR4_PARITY_ENABLE = 0x01, + WR4_PARITY_EVEN = 0x02, + WR4_STOP_BITS_MASK = 0x0c, + WR4_STOP_BITS_1 = 0x04, + WR4_STOP_BITS_1_5 = 0x08, // not supported + WR4_STOP_BITS_2 = 0x0c, + WR4_SYNC_MODE_MASK = 0x30, // not supported + WR4_SYNC_MODE_8_BIT = 0x00, // not supported + WR4_SYNC_MODE_16_BIT = 0x10, // not supported + WR4_SYNC_MODE_SDLC = 0x20, // not supported + WR4_SYNC_MODE_EXT = 0x30, // not supported + WR4_CLOCK_RATE_MASK = 0xc0, + WR4_CLOCK_RATE_X1 = 0x00, + WR4_CLOCK_RATE_X16 = 0x40, + WR4_CLOCK_RATE_X32 = 0x80, + WR4_CLOCK_RATE_X64 = 0xc0 }; enum { - WR5_TX_CRC_ENABLE = 0x01, // not supported - WR5_RTS = 0x02, - WR5_CRC16 = 0x04, // not supported - WR5_TX_ENABLE = 0x08, - WR5_SEND_BREAK = 0x10, - WR5_TX_WORD_LENGTH_MASK = 0x60, - WR5_TX_WORD_LENGTH_5 = 0x00, - WR5_TX_WORD_LENGTH_6 = 0x40, - WR5_TX_WORD_LENGTH_7 = 0x20, - WR5_TX_WORD_LENGTH_8 = 0x60, - WR5_DTR = 0x80 + WR5_TX_CRC_ENABLE = 0x01, // not supported + WR5_RTS = 0x02, + WR5_CRC16 = 0x04, // not supported + WR5_TX_ENABLE = 0x08, + WR5_SEND_BREAK = 0x10, + WR5_TX_WORD_LENGTH_MASK = 0x60, + WR5_TX_WORD_LENGTH_5 = 0x00, + WR5_TX_WORD_LENGTH_6 = 0x40, + WR5_TX_WORD_LENGTH_7 = 0x20, + WR5_TX_WORD_LENGTH_8 = 0x60, + WR5_DTR = 0x80 }; /* SCC specifics */ enum { - WR9_CMD_MASK = 0xC0, - WR9_CMD_NORESET = 0x00, - WR9_CMD_CHNB_RESET = 0x40, - WR9_CMD_CHNA_RESET = 0x80, - WR9_CMD_HW_RESET = 0xC0, - WR9_BIT_VIS = 0x01, - WR9_BIT_NV = 0x02, - WR9_BIT_DLC = 0x04, - WR9_BIT_MIE = 0x08, - WR9_BIT_SHSL = 0x10, - WR9_BIT_IACK = 0x20 + WR9_CMD_MASK = 0xC0, + WR9_CMD_NORESET = 0x00, + WR9_CMD_CHNB_RESET = 0x40, + WR9_CMD_CHNA_RESET = 0x80, + WR9_CMD_HW_RESET = 0xC0, + WR9_BIT_VIS = 0x01, + WR9_BIT_NV = 0x02, + WR9_BIT_DLC = 0x04, + WR9_BIT_MIE = 0x08, + WR9_BIT_SHSL = 0x10, + WR9_BIT_IACK = 0x20 }; enum { - WR11_RCVCLK_TYPE = 0x80, + WR11_RCVCLK_TYPE = 0x80, WR11_RCVCLK_SRC_MASK = 0x60, // RCV CLOCK WR11_RCVCLK_SRC_RTXC = 0x00, // 0 0 WR11_RCVCLK_SRC_TRXC = 0x20, // 0 1 - WR11_RCVCLK_SRC_BR = 0x40, // 1 0 + WR11_RCVCLK_SRC_BR = 0x40, // 1 0 WR11_RCVCLK_SRC_DPLL = 0x60, // 1 1 WR11_TRACLK_SRC_MASK = 0x18, // TRA CLOCK WR11_TRACLK_SRC_RTXC = 0x00, // 0 0 WR11_TRACLK_SRC_TRXC = 0x08, // 0 1 - WR11_TRACLK_SRC_BR = 0x10, // 1 0 + WR11_TRACLK_SRC_BR = 0x10, // 1 0 WR11_TRACLK_SRC_DPLL = 0x18, // 1 1 - WR11_TRXC_DIRECTION = 0x04, + WR11_TRXC_DIRECTION = 0x04, WR11_TRXSRC_SRC_MASK = 0x03, // TRXX CLOCK WR11_TRXSRC_SRC_XTAL = 0x00, // 0 0 - WR11_TRXSRC_SRC_TRA = 0x01, // 0 1 - WR11_TRXSRC_SRC_BR = 0x02, // 1 0 + WR11_TRXSRC_SRC_TRA = 0x01, // 0 1 + WR11_TRXSRC_SRC_BR = 0x02, // 1 0 WR11_TRXSRC_SRC_DPLL = 0x03 // 1 1 }; enum { - WR14_DPLL_CMD_MASK = 0xe0, // Command - WR14_CMD_NULL = 0x00, // 0 0 0 - WR14_CMD_ESM = 0x20, // 0 0 1 - WR14_CMD_RMC = 0x40, // 0 1 0 + WR14_DPLL_CMD_MASK = 0xe0, // Command + WR14_CMD_NULL = 0x00, // 0 0 0 + WR14_CMD_ESM = 0x20, // 0 0 1 + WR14_CMD_RMC = 0x40, // 0 1 0 WR14_CMD_DISABLE_DPLL = 0x60, // 0 1 1 - WR14_CMD_SS_BGR = 0x80, // 1 0 0 - WR14_CMD_SS_RTXC = 0xa0, // 1 0 1 - WR14_CMD_SET_FM = 0xc0, // 1 1 0 - WR14_CMD_SET_NRZI = 0xe0 // 1 1 1 + WR14_CMD_SS_BGR = 0x80, // 1 0 0 + WR14_CMD_SS_RTXC = 0xa0, // 1 0 1 + WR14_CMD_SET_FM = 0xc0, // 1 1 0 + WR14_CMD_SET_NRZI = 0xe0 // 1 1 1 }; void update_serial(); @@ -477,39 +477,39 @@ protected: int get_tx_word_length(); // receiver state - UINT8 m_rx_data_fifo[8]; // receive data FIFO - UINT8 m_rx_error_fifo[8]; // receive error FIFO - UINT8 m_rx_error; // current receive error - //int m_rx_fifo // receive FIFO pointer - int m_rx_fifo_rp; // receive FIFO read pointer - int m_rx_fifo_wp; // receive FIFO write pointer - int m_rx_fifo_sz; // receive FIFO size - - int m_rx_clock; // receive clock pulse count - int m_rx_first; // first character received - int m_rx_break; // receive break condition - UINT8 m_rx_rr0_latch; // read register 0 latched + UINT8 m_rx_data_fifo[8]; // receive data FIFO + UINT8 m_rx_error_fifo[8]; // receive error FIFO + UINT8 m_rx_error; // current receive error + //int m_rx_fifo // receive FIFO pointer + int m_rx_fifo_rp; // receive FIFO read pointer + int m_rx_fifo_wp; // receive FIFO write pointer + int m_rx_fifo_sz; // receive FIFO size + + int m_rx_clock; // receive clock pulse count + int m_rx_first; // first character received + int m_rx_break; // receive break condition + UINT8 m_rx_rr0_latch; // read register 0 latched int m_rxd; - int m_ri; // ring indicator latch - int m_cts; // clear to send latch - int m_dcd; // data carrier detect latch + int m_ri; // ring indicator latch + int m_cts; // clear to send latch + int m_dcd; // data carrier detect latch // transmitter state - UINT8 m_tx_data; // transmit data register - int m_tx_clock; // transmit clock pulse count + UINT8 m_tx_data; // transmit data register + int m_tx_clock; // transmit clock pulse count - int m_dtr; // data terminal ready - int m_rts; // request to send + int m_dtr; // data terminal ready + int m_rts; // request to send // synchronous state - UINT16 m_sync; // sync character + UINT16 m_sync; // sync character int m_index; z80scc_device *m_uart; // SCC specifics - int m_ph; // Point high command to access regs 08-0f + int m_ph; // Point high command to access regs 08-0f UINT8 m_zc; }; @@ -607,7 +607,7 @@ protected: // Variants in the SCC family enum { - TYPE_Z80SCC = 0x001, + TYPE_Z80SCC = 0x001, TYPE_SCC8030 = 0x002, TYPE_SCC80C30 = 0x004, TYPE_SCC80230 = 0x008, @@ -621,10 +621,10 @@ protected: #define SET_NMOS ( z80scc_device::TYPE_SCC8030 | z80scc_device::TYPE_SCC8530 ) #define SET_CMOS ( z80scc_device::TYPE_SCC80C30 | z80scc_device::TYPE_SCC85C30 ) #define SET_ESCC ( z80scc_device::TYPE_SCC80230 | z80scc_device::TYPE_SCC85230 | z80scc_device::TYPE_SCC8523L ) -#define SET_EMSCC z80scc_device::TYPE_SCC85233 +#define SET_EMSCC z80scc_device::TYPE_SCC85233 #define SET_Z80X30 ( z80scc_device::TYPE_SCC8030 | z80scc_device::TYPE_SCC80C30 | z80scc_device::TYPE_SCC80230 ) #define SET_Z85X3X ( z80scc_device::TYPE_SCC8530 | z80scc_device::TYPE_SCC85C30 | z80scc_device::TYPE_SCC85230 \ - | z80scc_device::TYPE_SCC8523L | z80scc_device::TYPE_SCC85233 ) + | z80scc_device::TYPE_SCC8523L | z80scc_device::TYPE_SCC85233 ) enum { @@ -641,25 +641,25 @@ protected: int m_rxcb; int m_txcb; - devcb_write_line m_out_txda_cb; - devcb_write_line m_out_dtra_cb; - devcb_write_line m_out_rtsa_cb; - devcb_write_line m_out_wrdya_cb; - devcb_write_line m_out_synca_cb; - - devcb_write_line m_out_txdb_cb; - devcb_write_line m_out_dtrb_cb; - devcb_write_line m_out_rtsb_cb; - devcb_write_line m_out_wrdyb_cb; - devcb_write_line m_out_syncb_cb; - - devcb_write_line m_out_int_cb; - devcb_write_line m_out_rxdrqa_cb; - devcb_write_line m_out_txdrqa_cb; - devcb_write_line m_out_rxdrqb_cb; - devcb_write_line m_out_txdrqb_cb; - - int m_int_state[6]; // interrupt state + devcb_write_line m_out_txda_cb; + devcb_write_line m_out_dtra_cb; + devcb_write_line m_out_rtsa_cb; + devcb_write_line m_out_wrdya_cb; + devcb_write_line m_out_synca_cb; + + devcb_write_line m_out_txdb_cb; + devcb_write_line m_out_dtrb_cb; + devcb_write_line m_out_rtsb_cb; + devcb_write_line m_out_wrdyb_cb; + devcb_write_line m_out_syncb_cb; + + devcb_write_line m_out_int_cb; + devcb_write_line m_out_rxdrqa_cb; + devcb_write_line m_out_txdrqa_cb; + devcb_write_line m_out_rxdrqb_cb; + devcb_write_line m_out_txdrqb_cb; + + int m_int_state[6]; // interrupt state int m_variant; UINT8 m_wr0_ptrbits; diff --git a/src/devices/machine/z80sio.c b/src/devices/machine/z80sio.c index 09c0e46663f..00f65a8e6b4 100644 --- a/src/devices/machine/z80sio.c +++ b/src/devices/machine/z80sio.c @@ -50,7 +50,7 @@ #include "z80sio.h" //************************************************************************** -// MACROS / CONSTANTS +// MACROS / CONSTANTS //************************************************************************** #define VERBOSE 0 @@ -68,13 +68,13 @@ #define FUNCNAME __PRETTY_FUNCTION__ #endif -#define CHANA_TAG "cha" -#define CHANB_TAG "chb" +#define CHANA_TAG "cha" +#define CHANB_TAG "chb" //************************************************************************** -// DEVICE DEFINITIONS +// DEVICE DEFINITIONS //************************************************************************** // device type definition @@ -82,7 +82,7 @@ const device_type Z80SIO = &device_creator<z80sio_device>; const device_type Z80SIO_CHANNEL = &device_creator<z80sio_channel>; //------------------------------------------------- -// device_mconfig_additions - +// device_mconfig_additions - //------------------------------------------------- MACHINE_CONFIG_FRAGMENT( z80sio ) @@ -96,11 +96,11 @@ machine_config_constructor z80sio_device::device_mconfig_additions() const } //************************************************************************** -// LIVE DEVICE +// LIVE DEVICE //************************************************************************** //------------------------------------------------- -// z80sio_device - constructor +// z80sio_device - constructor //------------------------------------------------- z80sio_device::z80sio_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source) @@ -164,7 +164,7 @@ z80sio_device::z80sio_device(const machine_config &mconfig, const char *tag, dev } //------------------------------------------------- -// device_start - device-specific startup +// device_start - device-specific startup //------------------------------------------------- void z80sio_device::device_start() { @@ -200,7 +200,7 @@ void z80sio_device::device_start() //------------------------------------------------- -// device_reset - device-specific reset +// device_reset - device-specific reset //------------------------------------------------- void z80sio_device::device_reset() { @@ -211,7 +211,7 @@ void z80sio_device::device_reset() } //------------------------------------------------- -// z80daisy_irq_state - get interrupt status +// z80daisy_irq_state - get interrupt status //------------------------------------------------- int z80sio_device::z80daisy_irq_state() { @@ -220,8 +220,8 @@ int z80sio_device::z80daisy_irq_state() LOG(("%s %s A:%d%d%d%d B:%d%d%d%d ",FUNCNAME, tag(), - m_int_state[0], m_int_state[1], m_int_state[2], m_int_state[3], - m_int_state[4], m_int_state[5], m_int_state[6], m_int_state[7])); + m_int_state[0], m_int_state[1], m_int_state[2], m_int_state[3], + m_int_state[4], m_int_state[5], m_int_state[6], m_int_state[7])); // loop over all interrupt sources for (i = 0; i < 8; i++) @@ -236,13 +236,13 @@ int z80sio_device::z80daisy_irq_state() } LOG(("Interrupt State %u\n", state)); - + return state; } //------------------------------------------------- -// z80daisy_irq_ack - interrupt acknowledge +// z80daisy_irq_ack - interrupt acknowledge //------------------------------------------------- int z80sio_device::z80daisy_irq_ack() { @@ -274,7 +274,7 @@ int z80sio_device::z80daisy_irq_ack() //------------------------------------------------- -// z80daisy_irq_reti - return from interrupt +// z80daisy_irq_reti - return from interrupt //------------------------------------------------- void z80sio_device::z80daisy_irq_reti() { @@ -300,7 +300,7 @@ void z80sio_device::z80daisy_irq_reti() //------------------------------------------------- -// check_interrupts - +// check_interrupts - //------------------------------------------------- void z80sio_device::check_interrupts() { @@ -311,7 +311,7 @@ void z80sio_device::check_interrupts() //------------------------------------------------- -// reset_interrupts - +// reset_interrupts - //------------------------------------------------- void z80sio_device::reset_interrupts() { @@ -327,7 +327,7 @@ void z80sio_device::reset_interrupts() //------------------------------------------------- -// trigger_interrupt - TODO: needs attention for SIO +// trigger_interrupt - TODO: needs attention for SIO //------------------------------------------------- void z80sio_device::trigger_interrupt(int index, int state) { @@ -384,7 +384,7 @@ void z80sio_device::trigger_interrupt(int index, int state) // status affects vector vector = (m_chanB->m_wr2 & 0xf1) | (!index << 3) | (state << 1); } -// } +// } // update vector register m_chanB->m_rr2 = vector; @@ -398,7 +398,7 @@ void z80sio_device::trigger_interrupt(int index, int state) //------------------------------------------------- -// m1_r - interrupt acknowledge +// m1_r - interrupt acknowledge //------------------------------------------------- int z80sio_device::m1_r() { @@ -408,7 +408,7 @@ int z80sio_device::m1_r() //------------------------------------------------- -// cd_ba_r - +// cd_ba_r - //------------------------------------------------- READ8_MEMBER( z80sio_device::cd_ba_r ) { @@ -423,7 +423,7 @@ READ8_MEMBER( z80sio_device::cd_ba_r ) //------------------------------------------------- -// cd_ba_w - +// cd_ba_w - //------------------------------------------------- WRITE8_MEMBER( z80sio_device::cd_ba_w ) { @@ -441,7 +441,7 @@ WRITE8_MEMBER( z80sio_device::cd_ba_w ) //------------------------------------------------- -// ba_cd_r - +// ba_cd_r - //------------------------------------------------- READ8_MEMBER( z80sio_device::ba_cd_r ) { @@ -456,7 +456,7 @@ READ8_MEMBER( z80sio_device::ba_cd_r ) //------------------------------------------------- -// ba_cd_w - +// ba_cd_w - //------------------------------------------------- WRITE8_MEMBER( z80sio_device::ba_cd_w ) { @@ -473,11 +473,11 @@ WRITE8_MEMBER( z80sio_device::ba_cd_w ) } //************************************************************************** -// SIO CHANNEL +// SIO CHANNEL //************************************************************************** //------------------------------------------------- -// z80sio_channel - constructor +// z80sio_channel - constructor //------------------------------------------------- z80sio_channel::z80sio_channel(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : device_t(mconfig, Z80SIO_CHANNEL, "Z80 SIO channel", tag, owner, clock, "z80sio_channel", __FILE__), @@ -512,7 +512,7 @@ z80sio_channel::z80sio_channel(const machine_config &mconfig, const char *tag, d //------------------------------------------------- -// start - channel startup +// start - channel startup //------------------------------------------------- void z80sio_channel::device_start() { @@ -555,7 +555,7 @@ void z80sio_channel::device_start() //------------------------------------------------- -// reset - reset channel status +// reset - reset channel status //------------------------------------------------- void z80sio_channel::device_reset() { @@ -590,7 +590,7 @@ void z80sio_channel::device_timer(emu_timer &timer, device_timer_id id, int para } //------------------------------------------------- -// tra_callback - +// tra_callback - //------------------------------------------------- void z80sio_channel::tra_callback() { @@ -615,7 +615,7 @@ void z80sio_channel::tra_callback() else if (!is_transmit_register_empty()) { int db = transmit_register_get_data_bit(); - + LOG(("%" I64FMT "d %s() \"%s \"Channel %c transmit data bit %d m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, db, m_wr5)); // transmit data if (m_index == z80sio_device::CHANNEL_A) @@ -632,7 +632,7 @@ void z80sio_channel::tra_callback() //------------------------------------------------- -// tra_complete - +// tra_complete - //------------------------------------------------- void z80sio_channel::tra_complete() { @@ -683,7 +683,7 @@ void z80sio_channel::tra_complete() //------------------------------------------------- -// rcv_callback - +// rcv_callback - //------------------------------------------------- void z80sio_channel::rcv_callback() { @@ -703,7 +703,7 @@ void z80sio_channel::rcv_callback() //------------------------------------------------- -// rcv_complete - +// rcv_complete - //------------------------------------------------- void z80sio_channel::rcv_complete() { @@ -717,7 +717,7 @@ void z80sio_channel::rcv_complete() //------------------------------------------------- -// get_clock_mode - get clock divisor +// get_clock_mode - get clock divisor //------------------------------------------------- int z80sio_channel::get_clock_mode() @@ -727,10 +727,10 @@ int z80sio_channel::get_clock_mode() switch (m_wr4 & WR4_CLOCK_RATE_MASK) { - case WR4_CLOCK_RATE_X1: clocks = 1; break; - case WR4_CLOCK_RATE_X16: clocks = 16; break; - case WR4_CLOCK_RATE_X32: clocks = 32; break; - case WR4_CLOCK_RATE_X64: clocks = 64; break; + case WR4_CLOCK_RATE_X1: clocks = 1; break; + case WR4_CLOCK_RATE_X16: clocks = 16; break; + case WR4_CLOCK_RATE_X32: clocks = 32; break; + case WR4_CLOCK_RATE_X64: clocks = 64; break; } return clocks; @@ -758,7 +758,7 @@ void z80sio_channel::set_rts(int state) void z80sio_channel::update_rts() { - // LOG(("%s(%d) \"%s\" Channel %c \n", FUNCNAME, state, m_owner->tag(), 'A' + m_index)); + // LOG(("%s(%d) \"%s\" Channel %c \n", FUNCNAME, state, m_owner->tag(), 'A' + m_index)); LOG(("%s() \"%s\" Channel %c \n", FUNCNAME, m_owner->tag(), 'A' + m_index)); if (m_wr5 & WR5_RTS) { @@ -771,13 +771,13 @@ void z80sio_channel::update_rts() // when the RTS bit is reset, the _RTS output goes high after the transmitter empties m_rts = 0; } - + // data terminal ready output follows the state programmed into the DTR bit*/ set_dtr((m_wr5 & WR5_DTR) ? 0 : 1); } //------------------------------------------------- -// get_stop_bits - get number of stop bits +// get_stop_bits - get number of stop bits //------------------------------------------------- device_serial_interface::stop_bits_t z80sio_channel::get_stop_bits() @@ -795,7 +795,7 @@ device_serial_interface::stop_bits_t z80sio_channel::get_stop_bits() //------------------------------------------------- -// get_rx_word_length - get receive word length +// get_rx_word_length - get receive word length //------------------------------------------------- int z80sio_channel::get_rx_word_length() @@ -805,10 +805,10 @@ int z80sio_channel::get_rx_word_length() switch (m_wr3 & WR3_RX_WORD_LENGTH_MASK) { - case WR3_RX_WORD_LENGTH_5: bits = 5; break; - case WR3_RX_WORD_LENGTH_6: bits = 6; break; - case WR3_RX_WORD_LENGTH_7: bits = 7; break; - case WR3_RX_WORD_LENGTH_8: bits = 8; break; + case WR3_RX_WORD_LENGTH_5: bits = 5; break; + case WR3_RX_WORD_LENGTH_6: bits = 6; break; + case WR3_RX_WORD_LENGTH_7: bits = 7; break; + case WR3_RX_WORD_LENGTH_8: bits = 8; break; } return bits; @@ -816,7 +816,7 @@ int z80sio_channel::get_rx_word_length() //------------------------------------------------- -// get_tx_word_length - get transmit word length +// get_tx_word_length - get transmit word length //------------------------------------------------- int z80sio_channel::get_tx_word_length() @@ -826,10 +826,10 @@ int z80sio_channel::get_tx_word_length() switch (m_wr5 & WR5_TX_WORD_LENGTH_MASK) { - case WR5_TX_WORD_LENGTH_5: bits = 5; break; - case WR5_TX_WORD_LENGTH_6: bits = 6; break; - case WR5_TX_WORD_LENGTH_7: bits = 7; break; - case WR5_TX_WORD_LENGTH_8: bits = 8; break; + case WR5_TX_WORD_LENGTH_5: bits = 5; break; + case WR5_TX_WORD_LENGTH_6: bits = 6; break; + case WR5_TX_WORD_LENGTH_7: bits = 7; break; + case WR5_TX_WORD_LENGTH_8: bits = 8; break; } return bits; @@ -869,7 +869,7 @@ UINT8 z80sio_channel::do_sioreg_rr2() //------------------------------------------------- -// control_read - read control register +// control_read - read control register //------------------------------------------------- UINT8 z80sio_channel::control_read() @@ -886,8 +886,8 @@ UINT8 z80sio_channel::control_read() switch (reg) { - case REG_RR0_STATUS: data = do_sioreg_rr0(); break; - case REG_RR1_SPEC_RCV_COND: data = do_sioreg_rr1(); break; + case REG_RR0_STATUS: data = do_sioreg_rr0(); break; + case REG_RR1_SPEC_RCV_COND: data = do_sioreg_rr1(); break; case REG_RR2_INTERRUPT_VECT: data = do_sioreg_rr2(); break; default: logerror("Z80SIO \"%s\" Channel %c : Unsupported RRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg); @@ -937,8 +937,8 @@ void z80sio_channel::do_sioreg_wr0(UINT8 data) // update register to reflect wire values TODO: Check if this will fire new interrupts if (!m_dcd) m_rr0 |= RR0_DCD; if (m_sync) m_rr0 |= RR0_SYNC_HUNT; - if (m_cts) m_rr0 |= RR0_CTS; - + if (m_cts) m_rr0 |= RR0_CTS; + LOG(("Z80SIO \"%s\" Channel %c : Reset External/Status Interrupt\n", m_owner->tag(), 'A' + m_index)); break; case WR0_CHANNEL_RESET: @@ -968,7 +968,7 @@ void z80sio_channel::do_sioreg_wr0(UINT8 data) break; default: LOG(("Z80SIO \"%s\" Channel %c : Unsupported WR0 command %02x mask %02x\n", m_owner->tag(), 'A' + m_index, data, WR0_REGISTER_MASK)); - + } do_sioreg_wr0_resets(data); } @@ -983,21 +983,21 @@ void z80sio_channel::do_sioreg_wr1(UINT8 data) LOG(("Z80SIO \"%s\" Channel %c : Wait/Ready Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ENABLE) ? 1 : 0)); LOG(("Z80SIO \"%s\" Channel %c : Wait/Ready Function %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_FUNCTION) ? "Ready" : "Wait")); LOG(("Z80SIO \"%s\" Channel %c : Wait/Ready on %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ON_RX_TX) ? "Receive" : "Transmit")); - + switch (data & WR1_RX_INT_MODE_MASK) { case WR1_RX_INT_DISABLE: LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt Disabled\n", m_owner->tag(), 'A' + m_index)); break; - + case WR1_RX_INT_FIRST: LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt on First Character\n", m_owner->tag(), 'A' + m_index)); break; - + case WR1_RX_INT_ALL_PARITY: LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt on All Characters, Parity Affects Vector\n", m_owner->tag(), 'A' + m_index)); break; - + case WR1_RX_INT_ALL: LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt on All Characters\n", m_owner->tag(), 'A' + m_index)); break; @@ -1058,30 +1058,30 @@ void z80sio_channel::do_sioreg_wr7(UINT8 data) } //------------------------------------------------- -// control_write - write control register +// control_write - write control register //------------------------------------------------- void z80sio_channel::control_write(UINT8 data) { - UINT8 reg = m_wr0 & WR0_REGISTER_MASK; + UINT8 reg = m_wr0 & WR0_REGISTER_MASK; if (reg != 0) { // mask out register index m_wr0 &= ~WR0_REGISTER_MASK; } - + LOG(("\n%s(%02x) reg %02x\n", FUNCNAME, data, reg)); - + switch (reg) { - case REG_WR0_COMMAND_REGPT: do_sioreg_wr0(data); break; - case REG_WR1_INT_DMA_ENABLE: do_sioreg_wr1(data); m_uart->check_interrupts(); break; - case REG_WR2_INT_VECTOR: do_sioreg_wr2(data); break; - case REG_WR3_RX_CONTROL: do_sioreg_wr3(data); update_serial(); break; - case REG_WR4_RX_TX_MODES: do_sioreg_wr4(data); update_serial(); break; - case REG_WR5_TX_CONTROL: do_sioreg_wr5(data); update_serial(); update_rts(); break; - case REG_WR6_SYNC_OR_SDLC_A: do_sioreg_wr6(data); break; - case REG_WR7_SYNC_OR_SDLC_F: do_sioreg_wr7(data); break; + case REG_WR0_COMMAND_REGPT: do_sioreg_wr0(data); break; + case REG_WR1_INT_DMA_ENABLE: do_sioreg_wr1(data); m_uart->check_interrupts(); break; + case REG_WR2_INT_VECTOR: do_sioreg_wr2(data); break; + case REG_WR3_RX_CONTROL: do_sioreg_wr3(data); update_serial(); break; + case REG_WR4_RX_TX_MODES: do_sioreg_wr4(data); update_serial(); break; + case REG_WR5_TX_CONTROL: do_sioreg_wr5(data); update_serial(); update_rts(); break; + case REG_WR6_SYNC_OR_SDLC_A: do_sioreg_wr6(data); break; + case REG_WR7_SYNC_OR_SDLC_F: do_sioreg_wr7(data); break; default: logerror("Z80SIO \"%s\" Channel %c : Unsupported WRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg); } @@ -1089,7 +1089,7 @@ void z80sio_channel::control_write(UINT8 data) //------------------------------------------------- -// data_read - read data register +// data_read - read data register //------------------------------------------------- UINT8 z80sio_channel::data_read() { @@ -1099,28 +1099,28 @@ UINT8 z80sio_channel::data_read() { // load data from the FIFO data = m_rx_data_fifo[m_rx_fifo]; - + // load error status from the FIFO m_rr1 = (m_rr1 & ~(RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR)) | m_rx_error_fifo[m_rx_fifo]; - + // decrease FIFO pointer m_rx_fifo--; - + if (m_rx_fifo < 0) { // no more characters available in the FIFO m_rr0 &= ~ RR0_RX_CHAR_AVAILABLE; } } - + LOG(("Z80SIO \"%s\" Channel %c : Data Register Read '%02x'\n", m_owner->tag(), 'A' + m_index, data)); - + return data; } - + //------------------------------------------------- -// data_write - write data register +// data_write - write data register //------------------------------------------------- void z80sio_channel::data_write(UINT8 data) { @@ -1140,7 +1140,7 @@ void z80sio_channel::data_write(UINT8 data) } else { - LOG((" Transmitter %s, data byte dropped\n", m_wr5 & WR5_TX_ENABLE ? "not enabled" : "not emptied")); + LOG((" Transmitter %s, data byte dropped\n", m_wr5 & WR5_TX_ENABLE ? "not enabled" : "not emptied")); m_rr0 &= ~RR0_TX_BUFFER_EMPTY; } @@ -1149,7 +1149,7 @@ void z80sio_channel::data_write(UINT8 data) //------------------------------------------------- -// receive_data - receive data word +// receive_data - receive data word //------------------------------------------------- void z80sio_channel::receive_data(UINT8 data) { @@ -1157,7 +1157,7 @@ void z80sio_channel::receive_data(UINT8 data) if (m_rx_fifo == 2) { - LOG((" Overrun detected\n")); + LOG((" Overrun detected\n")); // receive overrun error detected m_rx_error |= RR1_RX_OVERRUN_ERROR; @@ -1180,13 +1180,13 @@ void z80sio_channel::receive_data(UINT8 data) { m_rx_fifo++; } - + // store received character and error status into FIFO m_rx_data_fifo[m_rx_fifo] = data; m_rx_error_fifo[m_rx_fifo] = m_rx_error; - + m_rr0 |= RR0_RX_CHAR_AVAILABLE; - + // receive interrupt switch (m_wr1 & WR1_RX_INT_MODE_MASK) { @@ -1210,7 +1210,7 @@ void z80sio_channel::receive_data(UINT8 data) //------------------------------------------------- -// cts_w - clear to send handler +// cts_w - clear to send handler //------------------------------------------------- WRITE_LINE_MEMBER( z80sio_channel::cts_w ) @@ -1249,7 +1249,7 @@ WRITE_LINE_MEMBER( z80sio_channel::cts_w ) //------------------------------------------------- -// dcd_w - data carrier detected handler +// dcd_w - data carrier detected handler //------------------------------------------------- WRITE_LINE_MEMBER( z80sio_channel::dcd_w ) @@ -1287,7 +1287,7 @@ WRITE_LINE_MEMBER( z80sio_channel::dcd_w ) //------------------------------------------------- -// sh_w - Sync Hunt handler +// sh_w - Sync Hunt handler //------------------------------------------------- WRITE_LINE_MEMBER( z80sio_channel::sync_w ) @@ -1320,7 +1320,7 @@ WRITE_LINE_MEMBER( z80sio_channel::sync_w ) //------------------------------------------------- -// rxc_w - receive clock +// rxc_w - receive clock //------------------------------------------------- WRITE_LINE_MEMBER( z80sio_channel::rxc_w ) @@ -1342,7 +1342,7 @@ WRITE_LINE_MEMBER( z80sio_channel::rxc_w ) //------------------------------------------------- -// txc_w - transmit clock +// txc_w - transmit clock //------------------------------------------------- WRITE_LINE_MEMBER( z80sio_channel::txc_w ) @@ -1364,7 +1364,7 @@ WRITE_LINE_MEMBER( z80sio_channel::txc_w ) //------------------------------------------------- -// update_serial - +// update_serial - //------------------------------------------------- void z80sio_channel::update_serial() { @@ -1402,7 +1402,7 @@ void z80sio_channel::update_serial() //------------------------------------------------- -// set_dtr - +// set_dtr - //------------------------------------------------- void z80sio_channel::set_dtr(int state) @@ -1417,7 +1417,7 @@ void z80sio_channel::set_dtr(int state) } //------------------------------------------------- -// write_rx - +// write_rx - //------------------------------------------------- WRITE_LINE_MEMBER(z80sio_channel::write_rx) diff --git a/src/devices/machine/z80sio.h b/src/devices/machine/z80sio.h index bf75e8fe362..dc04bd5c020 100644 --- a/src/devices/machine/z80sio.h +++ b/src/devices/machine/z80sio.h @@ -59,7 +59,7 @@ #include "cpu/z80/z80daisy.h" //************************************************************************** -// DEVICE CONFIGURATION MACROS +// DEVICE CONFIGURATION MACROS //************************************************************************** #define MCFG_Z80SIO_ADD(_tag, _clock, _rxa, _txa, _rxb, _txb) \ @@ -116,7 +116,7 @@ //************************************************************************** -// TYPE DEFINITIONS +// TYPE DEFINITIONS //************************************************************************** // ======================> z80sio_channel @@ -146,7 +146,7 @@ public: UINT8 do_sioreg_rr0(); UINT8 do_sioreg_rr1(); UINT8 do_sioreg_rr2(); - + // write register handlers void do_sioreg_wr0(UINT8 data); void do_sioreg_wr0_resets(UINT8 data); @@ -157,7 +157,7 @@ public: void do_sioreg_wr5(UINT8 data); void do_sioreg_wr6(UINT8 data); void do_sioreg_wr7(UINT8 data); - + UINT8 control_read(); void control_write(UINT8 data); @@ -178,11 +178,11 @@ public: int m_txc; // Register state - // read registers enum + // read registers enum UINT8 m_rr0; // REG_RR0_STATUS UINT8 m_rr1; // REG_RR1_SPEC_RCV_COND UINT8 m_rr2; // REG_RR2_INTERRUPT_VECT - // write registers enum + // write registers enum UINT8 m_wr0; // REG_WR0_COMMAND_REGPT UINT8 m_wr1; // REG_WR1_INT_DMA_ENABLE UINT8 m_wr2; // REG_WR2_INT_VECTOR @@ -206,153 +206,153 @@ protected: // Read registers enum { - REG_RR0_STATUS = 0, - REG_RR1_SPEC_RCV_COND = 1, - REG_RR2_INTERRUPT_VECT = 2 + REG_RR0_STATUS = 0, + REG_RR1_SPEC_RCV_COND = 1, + REG_RR2_INTERRUPT_VECT = 2 }; - + // Write registers enum { - REG_WR0_COMMAND_REGPT = 0, - REG_WR1_INT_DMA_ENABLE = 1, - REG_WR2_INT_VECTOR = 2, - REG_WR3_RX_CONTROL = 3, - REG_WR4_RX_TX_MODES = 4, - REG_WR5_TX_CONTROL = 5, - REG_WR6_SYNC_OR_SDLC_A = 6, - REG_WR7_SYNC_OR_SDLC_F = 7 + REG_WR0_COMMAND_REGPT = 0, + REG_WR1_INT_DMA_ENABLE = 1, + REG_WR2_INT_VECTOR = 2, + REG_WR3_RX_CONTROL = 3, + REG_WR4_RX_TX_MODES = 4, + REG_WR5_TX_CONTROL = 5, + REG_WR6_SYNC_OR_SDLC_A = 6, + REG_WR7_SYNC_OR_SDLC_F = 7 }; - + enum { - RR0_RX_CHAR_AVAILABLE = 0x01, - RR0_INTERRUPT_PENDING = 0x02, - RR0_TX_BUFFER_EMPTY = 0x04, - RR0_DCD = 0x08, - RR0_SYNC_HUNT = 0x10, - RR0_CTS = 0x20, - RR0_TX_UNDERRUN = 0x40, - RR0_BREAK_ABORT = 0x80 + RR0_RX_CHAR_AVAILABLE = 0x01, + RR0_INTERRUPT_PENDING = 0x02, + RR0_TX_BUFFER_EMPTY = 0x04, + RR0_DCD = 0x08, + RR0_SYNC_HUNT = 0x10, + RR0_CTS = 0x20, + RR0_TX_UNDERRUN = 0x40, + RR0_BREAK_ABORT = 0x80 }; enum { - RR1_ALL_SENT = 0x01, - RR1_RESIDUE_CODE_MASK = 0x0e, - RR1_PARITY_ERROR = 0x10, - RR1_RX_OVERRUN_ERROR = 0x20, - RR1_CRC_FRAMING_ERROR = 0x40, - RR1_END_OF_FRAME = 0x80 + RR1_ALL_SENT = 0x01, + RR1_RESIDUE_CODE_MASK = 0x0e, + RR1_PARITY_ERROR = 0x10, + RR1_RX_OVERRUN_ERROR = 0x20, + RR1_CRC_FRAMING_ERROR = 0x40, + RR1_END_OF_FRAME = 0x80 }; enum - { // TODO: overload SIO functionality - RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case) - RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B - RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B - RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B + { // TODO: overload SIO functionality + RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case) + RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B + RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B + RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B }; - + enum { - WR0_REGISTER_MASK = 0x07, - WR0_COMMAND_MASK = 0x38, - WR0_NULL = 0x00, - WR0_SEND_ABORT = 0x08, // not supported - WR0_RESET_EXT_STATUS = 0x10, - WR0_CHANNEL_RESET = 0x18, - WR0_ENABLE_INT_NEXT_RX = 0x20, - WR0_RESET_TX_INT = 0x28, // not supported - WR0_ERROR_RESET = 0x30, - WR0_RETURN_FROM_INT = 0x38, // not supported - WR0_CRC_RESET_CODE_MASK = 0xc0, // not supported - WR0_CRC_RESET_NULL = 0x00, // not supported - WR0_CRC_RESET_RX = 0x40, // not supported - WR0_CRC_RESET_TX = 0x80, // not supported + WR0_REGISTER_MASK = 0x07, + WR0_COMMAND_MASK = 0x38, + WR0_NULL = 0x00, + WR0_SEND_ABORT = 0x08, // not supported + WR0_RESET_EXT_STATUS = 0x10, + WR0_CHANNEL_RESET = 0x18, + WR0_ENABLE_INT_NEXT_RX = 0x20, + WR0_RESET_TX_INT = 0x28, // not supported + WR0_ERROR_RESET = 0x30, + WR0_RETURN_FROM_INT = 0x38, // not supported + WR0_CRC_RESET_CODE_MASK = 0xc0, // not supported + WR0_CRC_RESET_NULL = 0x00, // not supported + WR0_CRC_RESET_RX = 0x40, // not supported + WR0_CRC_RESET_TX = 0x80, // not supported WR0_CRC_RESET_TX_UNDERRUN = 0xc0 // not supported }; enum { - WR1_EXT_INT_ENABLE = 0x01, - WR1_TX_INT_ENABLE = 0x02, - WR1_STATUS_VECTOR = 0x04, - WR1_RX_INT_MODE_MASK = 0x18, - WR1_RX_INT_DISABLE = 0x00, - WR1_RX_INT_FIRST = 0x08, - WR1_RX_INT_ALL_PARITY = 0x10, // not supported - WR1_RX_INT_ALL = 0x18, - WR1_WRDY_ON_RX_TX = 0x20, // not supported - WR1_WRDY_FUNCTION = 0x40, // not supported - WR1_WRDY_ENABLE = 0x80 // not supported + WR1_EXT_INT_ENABLE = 0x01, + WR1_TX_INT_ENABLE = 0x02, + WR1_STATUS_VECTOR = 0x04, + WR1_RX_INT_MODE_MASK = 0x18, + WR1_RX_INT_DISABLE = 0x00, + WR1_RX_INT_FIRST = 0x08, + WR1_RX_INT_ALL_PARITY = 0x10, // not supported + WR1_RX_INT_ALL = 0x18, + WR1_WRDY_ON_RX_TX = 0x20, // not supported + WR1_WRDY_FUNCTION = 0x40, // not supported + WR1_WRDY_ENABLE = 0x80 // not supported }; enum { - WR2_DATA_XFER_INT = 0x00, // not supported - WR2_DATA_XFER_DMA_INT = 0x01, // not supported - WR2_DATA_XFER_DMA = 0x02, // not supported - WR2_DATA_XFER_ILLEGAL = 0x03, // not supported - WR2_DATA_XFER_MASK = 0x03, // not supported - WR2_PRIORITY = 0x04, // not supported - WR2_MODE_8085_1 = 0x00, // not supported - WR2_MODE_8085_2 = 0x08, // not supported - WR2_MODE_8086_8088 = 0x10, // not supported - WR2_MODE_ILLEGAL = 0x18, // not supported - WR2_MODE_MASK = 0x18, // not supported - WR2_VECTORED_INT = 0x20, // not supported - WR2_PIN10_SYNDETB_RTSB = 0x80 // not supported + WR2_DATA_XFER_INT = 0x00, // not supported + WR2_DATA_XFER_DMA_INT = 0x01, // not supported + WR2_DATA_XFER_DMA = 0x02, // not supported + WR2_DATA_XFER_ILLEGAL = 0x03, // not supported + WR2_DATA_XFER_MASK = 0x03, // not supported + WR2_PRIORITY = 0x04, // not supported + WR2_MODE_8085_1 = 0x00, // not supported + WR2_MODE_8085_2 = 0x08, // not supported + WR2_MODE_8086_8088 = 0x10, // not supported + WR2_MODE_ILLEGAL = 0x18, // not supported + WR2_MODE_MASK = 0x18, // not supported + WR2_VECTORED_INT = 0x20, // not supported + WR2_PIN10_SYNDETB_RTSB = 0x80 // not supported }; enum { - WR3_RX_ENABLE = 0x01, + WR3_RX_ENABLE = 0x01, WR3_SYNC_CHAR_LOAD_INHIBIT= 0x02, // not supported - WR3_ADDRESS_SEARCH_MODE = 0x04, // not supported - WR3_RX_CRC_ENABLE = 0x08, // not supported - WR3_ENTER_HUNT_PHASE = 0x10, // not supported - WR3_AUTO_ENABLES = 0x20, - WR3_RX_WORD_LENGTH_MASK = 0xc0, - WR3_RX_WORD_LENGTH_5 = 0x00, - WR3_RX_WORD_LENGTH_7 = 0x40, - WR3_RX_WORD_LENGTH_6 = 0x80, - WR3_RX_WORD_LENGTH_8 = 0xc0 + WR3_ADDRESS_SEARCH_MODE = 0x04, // not supported + WR3_RX_CRC_ENABLE = 0x08, // not supported + WR3_ENTER_HUNT_PHASE = 0x10, // not supported + WR3_AUTO_ENABLES = 0x20, + WR3_RX_WORD_LENGTH_MASK = 0xc0, + WR3_RX_WORD_LENGTH_5 = 0x00, + WR3_RX_WORD_LENGTH_7 = 0x40, + WR3_RX_WORD_LENGTH_6 = 0x80, + WR3_RX_WORD_LENGTH_8 = 0xc0 }; enum { - WR4_PARITY_ENABLE = 0x01, - WR4_PARITY_EVEN = 0x02, - WR4_STOP_BITS_MASK = 0x0c, - WR4_STOP_BITS_1 = 0x04, - WR4_STOP_BITS_1_5 = 0x08, // not supported - WR4_STOP_BITS_2 = 0x0c, - WR4_SYNC_MODE_MASK = 0x30, // not supported - WR4_SYNC_MODE_8_BIT = 0x00, // not supported - WR4_SYNC_MODE_16_BIT = 0x10, // not supported - WR4_SYNC_MODE_SDLC = 0x20, // not supported - WR4_SYNC_MODE_EXT = 0x30, // not supported - WR4_CLOCK_RATE_MASK = 0xc0, - WR4_CLOCK_RATE_X1 = 0x00, - WR4_CLOCK_RATE_X16 = 0x40, - WR4_CLOCK_RATE_X32 = 0x80, - WR4_CLOCK_RATE_X64 = 0xc0 + WR4_PARITY_ENABLE = 0x01, + WR4_PARITY_EVEN = 0x02, + WR4_STOP_BITS_MASK = 0x0c, + WR4_STOP_BITS_1 = 0x04, + WR4_STOP_BITS_1_5 = 0x08, // not supported + WR4_STOP_BITS_2 = 0x0c, + WR4_SYNC_MODE_MASK = 0x30, // not supported + WR4_SYNC_MODE_8_BIT = 0x00, // not supported + WR4_SYNC_MODE_16_BIT = 0x10, // not supported + WR4_SYNC_MODE_SDLC = 0x20, // not supported + WR4_SYNC_MODE_EXT = 0x30, // not supported + WR4_CLOCK_RATE_MASK = 0xc0, + WR4_CLOCK_RATE_X1 = 0x00, + WR4_CLOCK_RATE_X16 = 0x40, + WR4_CLOCK_RATE_X32 = 0x80, + WR4_CLOCK_RATE_X64 = 0xc0 }; enum { - WR5_TX_CRC_ENABLE = 0x01, // not supported - WR5_RTS = 0x02, - WR5_CRC16 = 0x04, // not supported - WR5_TX_ENABLE = 0x08, - WR5_SEND_BREAK = 0x10, - WR5_TX_WORD_LENGTH_MASK = 0x60, - WR5_TX_WORD_LENGTH_5 = 0x00, - WR5_TX_WORD_LENGTH_6 = 0x40, - WR5_TX_WORD_LENGTH_7 = 0x20, - WR5_TX_WORD_LENGTH_8 = 0x60, - WR5_DTR = 0x80 + WR5_TX_CRC_ENABLE = 0x01, // not supported + WR5_RTS = 0x02, + WR5_CRC16 = 0x04, // not supported + WR5_TX_ENABLE = 0x08, + WR5_SEND_BREAK = 0x10, + WR5_TX_WORD_LENGTH_MASK = 0x60, + WR5_TX_WORD_LENGTH_5 = 0x00, + WR5_TX_WORD_LENGTH_6 = 0x40, + WR5_TX_WORD_LENGTH_7 = 0x20, + WR5_TX_WORD_LENGTH_8 = 0x60, + WR5_DTR = 0x80 }; void update_serial(); @@ -366,30 +366,30 @@ protected: int get_tx_word_length(); // receiver state - UINT8 m_rx_data_fifo[3]; // receive data FIFO - UINT8 m_rx_error_fifo[3]; // receive error FIFO - UINT8 m_rx_error; // current receive error - int m_rx_fifo; // receive FIFO pointer + UINT8 m_rx_data_fifo[3]; // receive data FIFO + UINT8 m_rx_error_fifo[3]; // receive error FIFO + UINT8 m_rx_error; // current receive error + int m_rx_fifo; // receive FIFO pointer - int m_rx_clock; // receive clock pulse count - int m_rx_first; // first character received - int m_rx_break; // receive break condition - UINT8 m_rx_rr0_latch; // read register 0 latched + int m_rx_clock; // receive clock pulse count + int m_rx_first; // first character received + int m_rx_break; // receive break condition + UINT8 m_rx_rr0_latch; // read register 0 latched int m_rxd; - int m_sh; // sync hunt - int m_cts; // clear to send latch - int m_dcd; // data carrier detect latch + int m_sh; // sync hunt + int m_cts; // clear to send latch + int m_dcd; // data carrier detect latch // transmitter state - UINT8 m_tx_data; // transmit data register - int m_tx_clock; // transmit clock pulse count + UINT8 m_tx_data; // transmit data register + int m_tx_clock; // transmit clock pulse count - int m_dtr; // data terminal ready - int m_rts; // request to send + int m_dtr; // data terminal ready + int m_rts; // request to send // synchronous state - UINT16 m_sync; // sync character + UINT16 m_sync; // sync character int m_index; z80sio_device *m_uart; @@ -403,11 +403,11 @@ class z80sio_device : public device_t, { friend class z80sio_channel; - public: + public: // construction/destruction z80sio_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source); z80sio_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + template<class _Object> static devcb_base &set_out_txda_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_txda_cb.set_callback(object); } template<class _Object> static devcb_base &set_out_dtra_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_dtra_cb.set_callback(object); } template<class _Object> static devcb_base &set_out_rtsa_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_rtsa_cb.set_callback(object); } @@ -504,25 +504,25 @@ protected: int m_rxcb; int m_txcb; - devcb_write_line m_out_txda_cb; - devcb_write_line m_out_dtra_cb; - devcb_write_line m_out_rtsa_cb; - devcb_write_line m_out_wrdya_cb; - devcb_write_line m_out_synca_cb; - - devcb_write_line m_out_txdb_cb; - devcb_write_line m_out_dtrb_cb; - devcb_write_line m_out_rtsb_cb; - devcb_write_line m_out_wrdyb_cb; - devcb_write_line m_out_syncb_cb; - - devcb_write_line m_out_int_cb; - devcb_write_line m_out_rxdrqa_cb; - devcb_write_line m_out_txdrqa_cb; - devcb_write_line m_out_rxdrqb_cb; - devcb_write_line m_out_txdrqb_cb; - - int m_int_state[8]; // interrupt state + devcb_write_line m_out_txda_cb; + devcb_write_line m_out_dtra_cb; + devcb_write_line m_out_rtsa_cb; + devcb_write_line m_out_wrdya_cb; + devcb_write_line m_out_synca_cb; + + devcb_write_line m_out_txdb_cb; + devcb_write_line m_out_dtrb_cb; + devcb_write_line m_out_rtsb_cb; + devcb_write_line m_out_wrdyb_cb; + devcb_write_line m_out_syncb_cb; + + devcb_write_line m_out_int_cb; + devcb_write_line m_out_rxdrqa_cb; + devcb_write_line m_out_txdrqa_cb; + devcb_write_line m_out_rxdrqb_cb; + devcb_write_line m_out_txdrqb_cb; + + int m_int_state[8]; // interrupt state int m_variant; }; diff --git a/src/devices/video/poly.h b/src/devices/video/poly.h index 0ba401e0755..c5f22c0409e 100644 --- a/src/devices/video/poly.h +++ b/src/devices/video/poly.h @@ -1177,7 +1177,7 @@ template<typename _BaseType, int _MaxParams> struct frustum_clip_vertex { _BaseType x, y, z, w; // A 3d coordinate already transformed by a projection matrix - _BaseType p[_MaxParams]; // Additional parameters to clip + _BaseType p[_MaxParams]; // Additional parameters to clip }; @@ -1212,11 +1212,11 @@ int frustum_clip_w(const frustum_clip_vertex<_BaseType, _MaxParams>* v, int num_ clipv[clip_verts].y = v[previ].y + ((v[i].y - v[previ].y) * t); clipv[clip_verts].z = v[previ].z + ((v[i].z - v[previ].z) * t); clipv[clip_verts].w = v[previ].w + ((v[i].w - v[previ].w) * t); - - // Interpolate the rest of the parameters - for (int pi = 0; pi < _MaxParams; pi++) - clipv[clip_verts].p[pi] = v[previ].p[pi] + ((v[i].p[pi] - v[previ].p[pi]) * t); - + + // Interpolate the rest of the parameters + for (int pi = 0; pi < _MaxParams; pi++) + clipv[clip_verts].p[pi] = v[previ].p[pi] + ((v[i].p[pi] - v[previ].p[pi]) * t); + ++clip_verts; } if (v1_side > 0) // current point is inside @@ -1280,12 +1280,12 @@ int frustum_clip(const frustum_clip_vertex<_BaseType, _MaxParams>* v, int num_ve clipv[clip_verts].y = v[previ].y + ((v[i].y - v[previ].y) * t); clipv[clip_verts].z = v[previ].z + ((v[i].z - v[previ].z) * t); clipv[clip_verts].w = v[previ].w + ((v[i].w - v[previ].w) * t); - - // Interpolate the rest of the parameters - for (int pi = 0; pi < _MaxParams; pi++) - clipv[clip_verts].p[pi] = v[previ].p[pi] + ((v[i].p[pi] - v[previ].p[pi]) * t); - ++clip_verts; + // Interpolate the rest of the parameters + for (int pi = 0; pi < _MaxParams; pi++) + clipv[clip_verts].p[pi] = v[previ].p[pi] + ((v[i].p[pi] - v[previ].p[pi]) * t); + + ++clip_verts; } if (v1_side > 0) // current point is inside { @@ -1304,15 +1304,15 @@ int frustum_clip(const frustum_clip_vertex<_BaseType, _MaxParams>* v, int num_ve template<typename _BaseType, int _MaxParams> int frustum_clip_all(frustum_clip_vertex<_BaseType, _MaxParams>* clip_vert, int num_vertices, frustum_clip_vertex<_BaseType, _MaxParams>* out) { - num_vertices = frustum_clip_w<_BaseType, _MaxParams>(clip_vert, num_vertices, clip_vert); - num_vertices = frustum_clip<_BaseType, _MaxParams>(clip_vert, num_vertices, clip_vert, 0, 0); // W <= -X - num_vertices = frustum_clip<_BaseType, _MaxParams>(clip_vert, num_vertices, clip_vert, 0, 1); // W <= +X - num_vertices = frustum_clip<_BaseType, _MaxParams>(clip_vert, num_vertices, clip_vert, 1, 0); // W <= -Y - num_vertices = frustum_clip<_BaseType, _MaxParams>(clip_vert, num_vertices, clip_vert, 1, 1); // W <= +X - num_vertices = frustum_clip<_BaseType, _MaxParams>(clip_vert, num_vertices, clip_vert, 2, 0); // W <= -Z - num_vertices = frustum_clip<_BaseType, _MaxParams>(clip_vert, num_vertices, clip_vert, 2, 1); // W <= +Z - out = clip_vert; - return num_vertices; + num_vertices = frustum_clip_w<_BaseType, _MaxParams>(clip_vert, num_vertices, clip_vert); + num_vertices = frustum_clip<_BaseType, _MaxParams>(clip_vert, num_vertices, clip_vert, 0, 0); // W <= -X + num_vertices = frustum_clip<_BaseType, _MaxParams>(clip_vert, num_vertices, clip_vert, 0, 1); // W <= +X + num_vertices = frustum_clip<_BaseType, _MaxParams>(clip_vert, num_vertices, clip_vert, 1, 0); // W <= -Y + num_vertices = frustum_clip<_BaseType, _MaxParams>(clip_vert, num_vertices, clip_vert, 1, 1); // W <= +X + num_vertices = frustum_clip<_BaseType, _MaxParams>(clip_vert, num_vertices, clip_vert, 2, 0); // W <= -Z + num_vertices = frustum_clip<_BaseType, _MaxParams>(clip_vert, num_vertices, clip_vert, 2, 1); // W <= +Z + out = clip_vert; + return num_vertices; } |
