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-rw-r--r--src/devices/cpu/sh/sh3comn.cpp2443
-rw-r--r--src/devices/cpu/sh/sh3comn.h73
-rw-r--r--src/devices/cpu/sh/sh4.cpp2023
-rw-r--r--src/devices/cpu/sh/sh4.h1537
-rw-r--r--src/devices/cpu/sh/sh4comn.cpp2623
-rw-r--r--src/devices/cpu/sh/sh4dmac.cpp330
-rw-r--r--src/devices/cpu/sh/sh4dmac.h35
-rw-r--r--src/devices/cpu/sh/sh4fe.cpp8
-rw-r--r--src/devices/cpu/sh/sh4regs.h157
-rw-r--r--src/devices/cpu/sh/sh4tmu.cpp260
10 files changed, 7423 insertions, 2066 deletions
diff --git a/src/devices/cpu/sh/sh3comn.cpp b/src/devices/cpu/sh/sh3comn.cpp
index 3ea57709ba4..63b270cbb72 100644
--- a/src/devices/cpu/sh/sh3comn.cpp
+++ b/src/devices/cpu/sh/sh3comn.cpp
@@ -9,674 +9,1787 @@
#include "sh4tmu.h"
#include "sh4dmac.h"
-/* High internal area (ffffxxxx) */
-
-void sh3_base_device::sh3_internal_high_w(offs_t offset, uint32_t data, uint32_t mem_mask)
-{
- COMBINE_DATA(&m_sh3internal_upper[offset]);
-
- switch (offset)
- {
- case SH3_ICR0_IPRA_ADDR:
- if (mem_mask & 0xffff0000)
- {
- logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - ICR0)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, data, mem_mask);
- }
-
- if (mem_mask & 0x0000ffff)
- {
- logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - IPRA)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, data, mem_mask);
- sh4_handler_ipra_w(data & 0xffff, mem_mask & 0xffff);
- }
-
- break;
-
- case SH3_IPRB_ADDR:
- logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_IPRB_ADDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, data, mem_mask);
- break;
-
- case SH3_TOCR_TSTR_ADDR:
- logerror("'%s' (%08x): TMU internal write to %08x = %08x & %08x (SH3_TOCR_TSTR_ADDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, data, mem_mask);
- if (mem_mask&0xff000000)
- {
- sh4_handle_tocr_addr_w((data>>24)&0xffff, (mem_mask>>24)&0xff);
- }
- if (mem_mask&0x0000ff00)
- {
- sh4_handle_tstr_addr_w((data>>8)&0xff, (mem_mask>>8)&0xff);
- }
- if (mem_mask&0x00ff00ff)
- {
- fatalerror("SH3_TOCR_TSTR_ADDR unused bits accessed (write)\n");
- }
- break;
- case SH3_TCOR0_ADDR: sh4_handle_tcor0_addr_w(data, mem_mask);break;
- case SH3_TCOR1_ADDR: sh4_handle_tcor1_addr_w(data, mem_mask);break;
- case SH3_TCOR2_ADDR: sh4_handle_tcor2_addr_w(data, mem_mask);break;
- case SH3_TCNT0_ADDR: sh4_handle_tcnt0_addr_w(data, mem_mask);break;
- case SH3_TCNT1_ADDR: sh4_handle_tcnt1_addr_w(data, mem_mask);break;
- case SH3_TCNT2_ADDR: sh4_handle_tcnt2_addr_w(data, mem_mask);break;
- case SH3_TCR0_ADDR: sh4_handle_tcr0_addr_w(data>>16, mem_mask>>16);break;
- case SH3_TCR1_ADDR: sh4_handle_tcr1_addr_w(data>>16, mem_mask>>16);break;
- case SH3_TCR2_ADDR: sh4_handle_tcr2_addr_w(data>>16, mem_mask>>16);break;
- case SH3_TCPR2_ADDR: sh4_handle_tcpr2_addr_w(data, mem_mask);break;
-
- default:
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (unk)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, data, mem_mask);
- break;
-
- }
-
-
-
-
-}
-
-uint32_t sh3_base_device::sh3_internal_high_r(offs_t offset, uint32_t mem_mask)
-{
- uint32_t ret = 0;
-
- switch (offset)
- {
- case SH3_ICR0_IPRA_ADDR:
- logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_ICR0_IPRA_ADDR - %08x)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, mem_mask, m_sh3internal_upper[offset]);
- return (m_sh3internal_upper[offset] & 0xffff0000) | (m_SH4_IPRA & 0xffff);
-
- case SH3_IPRB_ADDR:
- logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_IPRB_ADDR - %08x)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, mem_mask, m_sh3internal_upper[offset]);
- return m_sh3internal_upper[offset];
-
- case SH3_TOCR_TSTR_ADDR:
-
- if (mem_mask&0xff00000)
- {
- ret |= (sh4_handle_tocr_addr_r(mem_mask)&0xff)<<24;
- }
- if (mem_mask&0x0000ff00)
- {
- ret |= (sh4_handle_tstr_addr_r(mem_mask)&0xff)<<8;
- }
- if (mem_mask&0x00ff00ff)
- {
- fatalerror("SH3_TOCR_TSTR_ADDR unused bits accessed (read)\n");
- }
- return ret;
- case SH3_TCOR0_ADDR: return sh4_handle_tcor0_addr_r(mem_mask);
- case SH3_TCOR1_ADDR: return sh4_handle_tcor1_addr_r(mem_mask);
- case SH3_TCOR2_ADDR: return sh4_handle_tcor2_addr_r(mem_mask);
- case SH3_TCNT0_ADDR: return sh4_handle_tcnt0_addr_r(mem_mask);
- case SH3_TCNT1_ADDR: return sh4_handle_tcnt1_addr_r(mem_mask);
- case SH3_TCNT2_ADDR: return sh4_handle_tcnt2_addr_r(mem_mask);
- case SH3_TCR0_ADDR: return sh4_handle_tcr0_addr_r(mem_mask)<<16;
- case SH3_TCR1_ADDR: return sh4_handle_tcr1_addr_r(mem_mask)<<16;
- case SH3_TCR2_ADDR: return sh4_handle_tcr2_addr_r(mem_mask)<<16;
- case SH3_TCPR2_ADDR: return sh4_handle_tcpr2_addr_r(mem_mask);
-
-
- case SH3_TRA_ADDR:
- logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 TRA - %08x)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, mem_mask, m_sh3internal_upper[offset]);
- return m_sh3internal_upper[offset];
-
- case SH3_EXPEVT_ADDR:
- logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 EXPEVT - %08x)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, mem_mask, m_sh3internal_upper[offset]);
- return m_sh3internal_upper[offset];
-
- case SH3_INTEVT_ADDR:
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 INTEVT - %08x)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, mem_mask, m_sh3internal_upper[offset]);
- return m_sh3internal_upper[offset];
-
- case SH3_SCSSR_ADDR:
- // hack until SCI is not implemented
- return 0x84<<24;
-
-
- default:
- logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, mem_mask);
- return m_sh3internal_upper[offset];
- }
-}
-
-
-uint32_t sh3_base_device::sh3_internal_r(offs_t offset, uint32_t mem_mask)
-{
- if (offset<0x1000)
- {
- switch (offset)
- {
- case SH3_SAR0_ADDR: return sh4_handle_sar0_addr_r(mem_mask);
- case SH3_SAR1_ADDR: return sh4_handle_sar1_addr_r(mem_mask);
- case SH3_SAR2_ADDR: return sh4_handle_sar2_addr_r(mem_mask);
- case SH3_SAR3_ADDR: return sh4_handle_sar3_addr_r(mem_mask);
- case SH3_DAR0_ADDR: return sh4_handle_dar0_addr_r(mem_mask);
- case SH3_DAR1_ADDR: return sh4_handle_dar1_addr_r(mem_mask);
- case SH3_DAR2_ADDR: return sh4_handle_dar2_addr_r(mem_mask);
- case SH3_DAR3_ADDR: return sh4_handle_dar3_addr_r(mem_mask);
- case SH3_DMATCR0_ADDR: return sh4_handle_dmatcr0_addr_r(mem_mask);
- case SH3_DMATCR1_ADDR: return sh4_handle_dmatcr1_addr_r(mem_mask);
- case SH3_DMATCR2_ADDR: return sh4_handle_dmatcr2_addr_r(mem_mask);
- case SH3_DMATCR3_ADDR: return sh4_handle_dmatcr3_addr_r(mem_mask);
- case SH3_CHCR0_ADDR: return sh4_handle_chcr0_addr_r(mem_mask);
- case SH3_CHCR1_ADDR: return sh4_handle_chcr1_addr_r(mem_mask);
- case SH3_CHCR2_ADDR: return sh4_handle_chcr2_addr_r(mem_mask);
- case SH3_CHCR3_ADDR: return sh4_handle_chcr3_addr_r(mem_mask);
- case SH3_DMAOR_ADDR: return sh4_handle_dmaor_addr_r(mem_mask)<<16;
-
-
- case INTEVT2:
- {
- // logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (INTEVT2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_sh3internal_lower[offset];
- }
-
-
- case IRR0_IRR1:
- {
- {
- if (mem_mask & 0xff000000)
- {
- logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_sh3internal_lower[offset];
- }
-
- if (mem_mask & 0x0000ff00)
- {
- logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR1)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_sh3internal_lower[offset];
- }
-
- fatalerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0/1 unused bits)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- }
- }
-
- case PADR_PBDR:
- {
- if (mem_mask & 0xffff0000)
- {
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PADR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_io->read_qword(SH3_PORT_A) << 24;
- }
-
- if (mem_mask & 0x0000ffff)
- {
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PBDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_io->read_qword(SH3_PORT_B) << 8;
- }
- }
- break;
-
- case PCDR_PDDR:
- {
- if (mem_mask & 0xffff0000)
- {
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PCDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_io->read_qword(SH3_PORT_C) << 24;
- }
-
- if (mem_mask & 0x0000ffff)
- {
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PDDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_io->read_qword(SH3_PORT_D) << 8;
- }
- }
- break;
-
- case PEDR_PFDR:
- {
- if (mem_mask & 0xffff0000)
- {
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PEDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_io->read_qword(SH3_PORT_E) << 24;
- }
-
- if (mem_mask & 0x0000ffff)
- {
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PFDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_io->read_qword(SH3_PORT_F) << 8;
- }
- }
- break;
-
- case PGDR_PHDR:
- {
- if (mem_mask & 0xffff0000)
- {
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PGDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_io->read_qword(SH3_PORT_G) << 24;
- }
-
- if (mem_mask & 0x0000ffff)
- {
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PHDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_io->read_qword(SH3_PORT_H) << 8;
- }
- }
- break;
-
- case PJDR_PKDR:
- {
- if (mem_mask & 0xffff0000)
- {
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PJDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_io->read_qword(SH3_PORT_J) << 24;
- }
-
- if (mem_mask & 0x0000ffff)
- {
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PKDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_io->read_qword(SH3_PORT_K) << 8;
- }
- }
- break;
-
- case PLDR_SCPDR:
- {
- if (mem_mask & 0xffff0000)
- {
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PLDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_io->read_qword(SH3_PORT_L) << 24;
- }
-
- if (mem_mask & 0x0000ffff)
- {
- logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SCPDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- //return m_io->read_qword(SH3_PORT_K) << 8;
- }
- }
- break;
-
-
- case SCSMR2_SCBRR2:
- {
- if (mem_mask & 0xff000000)
- {
- logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSMR2 - Serial Mode Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_sh3internal_lower[offset];
- }
-
- if (mem_mask & 0x0000ff00)
- {
- logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCBRR2 - Bit Rate Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_sh3internal_lower[offset];
- }
- }
- break;
-
- case SCSCR2_SCFTDR2:
- {
- if (mem_mask & 0xff000000)
- {
- logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSCR2 - Serial Control Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_sh3internal_lower[offset];
- }
-
- if (mem_mask & 0x0000ff00)
- {
- logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_sh3internal_lower[offset];
- }
- }
- break;
-
- case SCSSR2_SCFRDR2:
- {
- if (mem_mask & 0xffff0000)
- {
- logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSSR2 - Serial Status Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_sh3internal_lower[offset];
- }
-
- if (mem_mask & 0x0000ff00)
- {
- logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFRDR2 - Receive FIFO Data Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_sh3internal_lower[offset];
- }
- }
- break;
-
- case SCFCR2_SCFDR2:
- {
- if (mem_mask & 0xff000000)
- {
- logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFCR2 - Fifo Control Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_sh3internal_lower[offset];
- }
-
- if (mem_mask & 0x0000ffff)
- {
- logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFDR2 - Fifo Data Count Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
- return m_sh3internal_lower[offset];
- }
- }
- break;
-
-
- default:
- {
- logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n",
- tag(), m_sh2_state->pc & SH34_AM,
- (offset *4)+0x4000000,
- mem_mask);
- }
- break;
-
- }
-
- }
- else
- {
- logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n",
- tag(), m_sh2_state->pc & SH34_AM,
- (offset *4)+0x4000000,
- mem_mask);
- }
+// CCN
+uint32_t sh3_base_device::pteh_r(offs_t offset, uint32_t mem_mask)
+{
+ logerror("'%s' (%08x): CCN unmapped internal read mask %08x (PTEH) %08x\n", tag(), m_sh2_state->pc, mem_mask, m_pteh);
+ return m_pteh;
+}
+
+void sh3_base_device::pteh_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pteh);
+ logerror("'%s' (%08x): CCN unmapped internal write %08x & %08x (PTEH)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint32_t sh3_base_device::ptel_r(offs_t offset, uint32_t mem_mask)
+{
+ logerror("'%s' (%08x): CCN unmapped internal read mask %08x (PTEL) %08x\n", tag(), m_sh2_state->pc, mem_mask, m_ptel);
+ return m_ptel;
+}
+
+void sh3_base_device::ptel_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_ptel);
+ logerror("'%s' (%08x): CCN unmapped internal write %08x & %08x (PTEL)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint32_t sh3_base_device::ttb_r(offs_t offset, uint32_t mem_mask)
+{
+ logerror("'%s' (%08x): CCN unmapped internal read mask %08x (TTB) %08x\n", tag(), m_sh2_state->pc, mem_mask, m_ttb);
+ return m_ttb;
+}
+void sh3_base_device::ttb_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_ttb);
+ logerror("'%s' (%08x): CCN unmapped internal write %08x & %08x (TTB)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint32_t sh3_base_device::tea_r(offs_t offset, uint32_t mem_mask)
+{
+ logerror("'%s' (%08x): CCN unmapped internal read mask %08x (TEA) %08x\n", tag(), m_sh2_state->pc, mem_mask, m_tea);
+ return m_tea;
+}
+
+void sh3_base_device::tea_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_tea);
+ logerror("'%s' (%08x): CCN unmapped internal write %08x & %08x (TEA)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint32_t sh3_base_device::mmucr_r(offs_t offset, uint32_t mem_mask)
+{
+ logerror("'%s' (%08x): CCN unmapped internal read mask %08x (MMUCR) %08x\n", tag(), m_sh2_state->pc, mem_mask, m_mmucr);
+ return m_mmucr;
+}
+
+void sh3_base_device::mmucr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_mmucr);
+ logerror("'%s' (%08x): CCN unmapped internal write %08x & %08x (MMUCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::basra_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): CCN unmapped internal read mask %02x (BASRA) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_basra);
+ return m_basra;
+}
+
+void sh3_base_device::basra_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_basra);
+ logerror("'%s' (%08x): CCN unmapped internal write %02x & %02x (BASRA)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::basrb_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): CCN unmapped internal read mask %02x (BASRB) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_basrb);
+ return m_basrb;
+}
+
+void sh3_base_device::basrb_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_basrb);
+ logerror("'%s' (%08x): CCN unmapped internal write %02x & %02x (BASRB)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint32_t sh3_base_device::ccr_r(offs_t offset, uint32_t mem_mask)
+{
+ logerror("'%s' (%08x): CCN unmapped internal read mask %08x (CCR) %08x\n", tag(), m_sh2_state->pc, mem_mask, m_ccr);
+ return m_ccr;
+}
+
+void sh3_base_device::ccr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_ccr);
+ logerror("'%s' (%08x): CCN unmapped internal write %08x & %08x (CCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint32_t sh3_base_device::tra_r(offs_t offset, uint32_t mem_mask)
+{
+ logerror("'%s' (%08x): CCN unmapped internal read mask %08x (TRA) %08x\n", tag(), m_sh2_state->pc, mem_mask, m_tra);
+ return m_tra;
+}
+
+void sh3_base_device::tra_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_tra);
+ logerror("'%s' (%08x): CCN unmapped internal write %08x & %08x (TRA)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint32_t sh3_base_device::expevt_r(offs_t offset, uint32_t mem_mask)
+{
+ logerror("'%s' (%08x): CCN unmapped internal read mask %08x (EXPEVT) %08x\n", tag(), m_sh2_state->pc, mem_mask, m_expevt);
+ return m_expevt;
+}
+
+void sh3_base_device::expevt_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_expevt);
+ logerror("'%s' (%08x): CCN unmapped internal write %08x & %08x (EXPEVT)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint32_t sh3_base_device::intevt_r(offs_t offset, uint32_t mem_mask)
+{
+ //logerror("'%s' (%08x): CCN unmapped internal read mask %08x (INTEVT) %08x\n", tag(), m_sh2_state->pc, mem_mask, m_intevt);
+ return m_intevt;
+}
+
+void sh3_base_device::intevt_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_intevt);
+ logerror("'%s' (%08x): CCN unmapped internal write %08x & %08x (INTEVT)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// CCN 7709S
+uint32_t sh3_base_device::ccr2_r(offs_t offset, uint32_t mem_mask)
+{
+ logerror("'%s' (%08x): CCN unmapped internal read mask %08x (CCR2) %08x\n", tag(), m_sh2_state->pc, mem_mask, m_ccr2);
+ return m_ccr2;
+}
+
+void sh3_base_device::ccr2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_ccr2);
+ logerror("'%s' (%08x): CCN unmapped internal write %08x & %08x (CCR2)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// UBC
+uint32_t sh3_base_device::bara_r(offs_t offset, uint32_t mem_mask)
+{
+ logerror("'%s' (%08x): UBC unmapped internal read mask %08x (BARA) %08x\n", tag(), m_sh2_state->pc, mem_mask, m_bara);
+ return m_bara;
+}
+
+void sh3_base_device::bara_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_bara);
+ logerror("'%s' (%08x): UBC unmapped internal write %08x & %08x (BARA)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::bamra_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): UBC unmapped internal read mask %02x (BAMRA) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_bamra);
+ return m_bamra;
+}
+
+void sh3_base_device::bamra_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_bamra);
+ logerror("'%s' (%08x): UBC unmapped internal write %02x & %02x (BAMRA)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::bbra_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): UBC unmapped internal read mask %04x (BBRA) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_bbra);
+ return m_bbra;
+}
+
+void sh3_base_device::bbra_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_bbra);
+ logerror("'%s' (%08x): UBC unmapped internal write %04x & %04x (BBRA)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint32_t sh3_base_device::barb_r(offs_t offset, uint32_t mem_mask)
+{
+ logerror("'%s' (%08x): UBC unmapped internal read mask %08x (BARB) %08x\n", tag(), m_sh2_state->pc, mem_mask, m_barb);
+ return m_barb;
+}
+
+void sh3_base_device::barb_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_barb);
+ logerror("'%s' (%08x): UBC unmapped internal write %08x & %08x (BARB)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::bamrb_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): UBC unmapped internal read mask %02x (BAMRB) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_bamrb);
+ return m_bamrb;
+}
+
+void sh3_base_device::bamrb_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_bamrb);
+ logerror("'%s' (%08x): UBC unmapped internal write %02x & %02x (BAMRB)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::bbrb_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): UBC unmapped internal read mask %04x (BBRB) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_bbrb);
+ return m_bbrb;
+}
+
+void sh3_base_device::bbrb_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_bbrb);
+ logerror("'%s' (%08x): UBC unmapped internal write %04x & %04x (BBRB)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint32_t sh3_base_device::bdrb_r(offs_t offset, uint32_t mem_mask)
+{
+ logerror("'%s' (%08x): UBC unmapped internal read mask %08x (BDRB) %08x\n", tag(), m_sh2_state->pc, mem_mask, m_bdrb);
+ return m_bdrb;
+}
+
+void sh3_base_device::bdrb_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_bdrb);
+ logerror("'%s' (%08x): UBC unmapped internal write %08x & %08x (BDRB)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint32_t sh3_base_device::bdmrb_r(offs_t offset, uint32_t mem_mask)
+{
+ logerror("'%s' (%08x): UBC unmapped internal read mask %08x (BDMRB) %08x\n", tag(), m_sh2_state->pc, mem_mask, m_bdmrb);
+ return m_bdmrb;
+}
+
+void sh3_base_device::bdmrb_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_bdmrb);
+ logerror("'%s' (%08x): UBC unmapped internal write %08x & %08x (BDMRB)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::brcr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): UBC unmapped internal read mask %04x (BRCR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_brcr);
+ return m_brcr;
+}
+
+void sh3_base_device::brcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_brcr);
+ logerror("'%s' (%08x): UBC unmapped internal write %04x & %04x (BRCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// UBC 7709S
+uint16_t sh3_base_device::betr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): UBC unmapped internal read mask %04x (BETR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_betr);
+ return m_betr;
+}
+
+void sh3_base_device::betr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_betr);
+ logerror("'%s' (%08x): UBC unmapped internal write %04x & %04x (BETR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint32_t sh3_base_device::brsr_r(offs_t offset, uint32_t mem_mask)
+{
+ logerror("'%s' (%08x): UBC unmapped internal read mask %08x (BRSR) %08x\n", tag(), m_sh2_state->pc, mem_mask, m_brsr);
+ return m_brsr;
+}
+
+void sh3_base_device::brsr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_brsr);
+ logerror("'%s' (%08x): UBC unmapped internal write %08x & %08x (BRSR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint32_t sh3_base_device::brdr_r(offs_t offset, uint32_t mem_mask)
+{
+ logerror("'%s' (%08x): UBC unmapped internal read mask %08x (BRDR) %08x\n", tag(), m_sh2_state->pc, mem_mask, m_brdr);
+ return m_brdr;
+}
+
+void sh3_base_device::brdr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_brdr);
+ logerror("'%s' (%08x): UBC unmapped internal write %08x & %08x (BRDR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// CPG
+uint16_t sh3_base_device::frqcr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): CPG unmapped internal read mask %04x (FRQCR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_frqcr);
+ return m_frqcr;
+}
+
+void sh3_base_device::frqcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_frqcr);
+ logerror("'%s' (%08x): CPG unmapped internal write %04x & %04x (FRQCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::stbcr_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): CPG unmapped internal read mask %02x (STBCR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_stbcr);
+ return m_stbcr;
+}
+
+void sh3_base_device::stbcr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_stbcr);
+ logerror("'%s' (%08x): CPG unmapped internal write %02x & %02x (STBCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::wtcnt_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): CPG unmapped internal read mask %02x (WTCNT) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_stbcr);
+ return m_wtcnt;
+}
+
+void sh3_base_device::wtcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ if ((data & 0xff00) == 0x5a00)
+ COMBINE_DATA(&m_wtcnt);
+
+ logerror("'%s' (%08x): CPG unmapped internal write %04x & %04x (WTCNT)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::wtcsr_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): CPG unmapped internal read mask %02x (WTCSR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_wtcsr);
+ return m_wtcsr;
+}
+
+void sh3_base_device::wtcsr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ if ((data & 0xff00) == 0xa500)
+ COMBINE_DATA(&m_wtcsr);
+ logerror("'%s' (%08x): CPG unmapped internal write %04x & %04x (WTCSR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// CPG 7709
+uint8_t sh3_base_device::stbcr2_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): CPG unmapped internal read mask %02x (STBCR2) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_stbcr2);
+ return m_stbcr2;
+}
+
+void sh3_base_device::stbcr2_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_stbcr2);
+ logerror("'%s' (%08x): CPG unmapped internal write %02x & %02x (STBCR2)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// BSC
+uint16_t sh3_base_device::bcr1_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (BCR1) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_bcr1);
+ return m_bcr1;
+}
+
+void sh3_base_device::bcr1_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_bcr1);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (BCR1)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::bcr2_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (BCR2) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_bcr2);
+ return m_bcr2;
+}
+
+void sh3_base_device::bcr2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_bcr2);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (BCR2)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::wcr1_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (WCR1) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_wcr1);
+ return m_wcr1;
+}
+
+void sh3_base_device::wcr1_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_wcr1);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (WCR1)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::wcr2_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (WCR2) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_wcr2);
+ return m_wcr2;
+}
+
+void sh3_base_device::wcr2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_wcr2);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (WCR2)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::mcr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (MCR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_mcr);
+ return m_mcr;
+}
+
+void sh3_base_device::mcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_mcr);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (MCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::pcr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (PCR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_pcr);
+ return m_pcr;
+}
+
+void sh3_base_device::pcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_pcr);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (PCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::rtcsr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (RTCSR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_rtcsr);
+ return m_rtcsr;
+}
+
+void sh3_base_device::rtcsr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_rtcsr);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (RTCSR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::rtcnt_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (RTCNT) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_rtcnt);
+ return m_rtcnt;
+}
+
+void sh3_base_device::rtcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_rtcnt);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (RTCNT)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::rtcor_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (RTCOR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_rtcor);
+ return m_rtcor;
+}
+
+void sh3_base_device::rtcor_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_rtcor);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (RTCOR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::rfcr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (RFCR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_rfcr);
+ return m_rfcr;
+}
+
+void sh3_base_device::rfcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_rfcr);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (RFCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::sdmr_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %02x @ %05x (SDMR)\n", tag(), m_sh2_state->pc, mem_mask, offset);
return 0;
}
-/* Lower internal area */
-
-void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_mask)
-{
- if (offset<0x1000)
- {
- //uint32_t old = m_sh3internal_lower[offset];
- COMBINE_DATA(&m_sh3internal_lower[offset]);
-
- switch (offset)
- {
- case SH3_SAR0_ADDR: sh4_handle_sar0_addr_w(data, mem_mask); break;
- case SH3_SAR1_ADDR: sh4_handle_sar1_addr_w(data, mem_mask); break;
- case SH3_SAR2_ADDR: sh4_handle_sar2_addr_w(data, mem_mask); break;
- case SH3_SAR3_ADDR: sh4_handle_sar3_addr_w(data, mem_mask); break;
- case SH3_DAR0_ADDR: sh4_handle_dar0_addr_w(data, mem_mask); break;
- case SH3_DAR1_ADDR: sh4_handle_dar1_addr_w(data, mem_mask); break;
- case SH3_DAR2_ADDR: sh4_handle_dar2_addr_w(data, mem_mask); break;
- case SH3_DAR3_ADDR: sh4_handle_dar3_addr_w(data, mem_mask); break;
- case SH3_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(data, mem_mask); break;
- case SH3_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(data, mem_mask); break;
- case SH3_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(data, mem_mask); break;
- case SH3_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(data, mem_mask); break;
- case SH3_CHCR0_ADDR: sh4_handle_chcr0_addr_w(data, mem_mask); break;
- case SH3_CHCR1_ADDR: sh4_handle_chcr1_addr_w(data, mem_mask); break;
- case SH3_CHCR2_ADDR: sh4_handle_chcr2_addr_w(data, mem_mask); break;
- case SH3_CHCR3_ADDR: sh4_handle_chcr3_addr_w(data, mem_mask); break;
- case SH3_DMAOR_ADDR: sh4_handle_dmaor_addr_w(data >> 16, mem_mask >> 16); break;
-
-
- case IRR0_IRR1:
- {
- {
- if (mem_mask & 0xff000000)
- {
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- // not sure if this is how we should clear lines in this core...
- if (!(data & 0x01000000)) execute_set_input(0, CLEAR_LINE);
- if (!(data & 0x02000000)) execute_set_input(1, CLEAR_LINE);
- if (!(data & 0x04000000)) execute_set_input(2, CLEAR_LINE);
- if (!(data & 0x08000000)) execute_set_input(3, CLEAR_LINE);
-
- }
- if (mem_mask & 0x0000ff00)
- {
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR1)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
- if (mem_mask & 0x00ff00ff)
- {
- fatalerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0/1 unused bits)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
- }
- }
- break;
-
- case PINTER_IPRC:
- {
- if (mem_mask & 0xffff0000)
- {
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PINTER)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
-
- if (mem_mask & 0x0000ffff)
- {
- data &= 0xffff; mem_mask &= 0xffff;
- COMBINE_DATA(&m_SH4_IPRC);
- logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (IPRC)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- m_exception_priority[SH4_INTC_IRL0] = INTPRI((m_SH4_IPRC & 0x000f) >> 0, SH4_INTC_IRL0);
- m_exception_priority[SH4_INTC_IRL1] = INTPRI((m_SH4_IPRC & 0x00f0) >> 4, SH4_INTC_IRL1);
- m_exception_priority[SH4_INTC_IRL2] = INTPRI((m_SH4_IPRC & 0x0f00) >> 8, SH4_INTC_IRL2);
- m_exception_priority[SH4_INTC_IRL3] = INTPRI((m_SH4_IPRC & 0xf000) >> 12, SH4_INTC_IRL3);
- sh4_exception_recompute();
- }
- }
- break;
-
- case PCCR_PDCR:
- {
- if (mem_mask & 0xffff0000)
- {
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PCCR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
-
- if (mem_mask & 0x0000ffff)
- {
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PDCR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
- }
- break;
-
- case PECR_PFCR:
- {
- if (mem_mask & 0xffff0000)
- {
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PECR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
-
- if (mem_mask & 0x0000ffff)
- {
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFCR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
- }
- break;
-
-
- case PGCR_PHCR:
- {
- if (mem_mask & 0xffff0000)
- {
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGCR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
-
- if (mem_mask & 0x0000ffff)
- {
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHCR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
- }
- break;
-
-
- case PJCR_PKCR:
- {
- if (mem_mask & 0xffff0000)
- {
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJCR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
-
- if (mem_mask & 0x0000ffff)
- {
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKCR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
- }
- break;
-
-
- case PLCR_SCPCR:
- {
- if (mem_mask & 0xffff0000)
- {
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PLCR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
-
- if (mem_mask & 0x0000ffff)
- {
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (SCPCR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
- }
- break;
-
- case PADR_PBDR:
- {
- if (mem_mask & 0xffff0000)
- {
- m_io->write_qword(SH3_PORT_A, (data >> 24) & 0xff);
- // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
-
- if (mem_mask & 0x0000ffff)
- {
- m_io->write_qword(SH3_PORT_B, (data >> 8) & 0xff);
- // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
- }
- break;
-
- case PCDR_PDDR:
- {
- if (mem_mask & 0xffff0000)
- {
- m_io->write_qword(SH3_PORT_C, (data >> 24) & 0xff);
- // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
-
- if (mem_mask & 0x0000ffff)
- {
- m_io->write_qword(SH3_PORT_D, (data >> 8) & 0xff);
- // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
- }
- break;
- case PEDR_PFDR:
- {
- if (mem_mask & 0xffff0000)
- {
- m_io->write_qword(SH3_PORT_E, (data >> 24) & 0xff);
- // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PEDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
-
- if (mem_mask & 0x0000ffff)
- {
- m_io->write_qword(SH3_PORT_F, (data >> 8) & 0xff);
- // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
- }
- break;
-
- case PGDR_PHDR:
- {
- if (mem_mask & 0xffff0000)
- {
- m_io->write_qword(SH3_PORT_G, (data >> 24) & 0xff);
- // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
-
- if (mem_mask & 0x0000ffff)
- {
- m_io->write_qword(SH3_PORT_H, (data >> 8) & 0xff);
- // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
- }
- break;
-
-
- case PJDR_PKDR:
- {
- if (mem_mask & 0xffff0000)
- {
- m_io->write_qword(SH3_PORT_J, (data >> 24) & 0xff);
- // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
-
- if (mem_mask & 0x0000ffff)
- {
- m_io->write_qword(SH3_PORT_K, (data >> 8) & 0xff);
- //logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
- }
- break;
-
- case SCSMR2_SCBRR2:
- {
- if (mem_mask & 0xff000000)
- {
- logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSMR2 - Serial Mode Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
-
- if (mem_mask & 0x0000ff00)
- {
- logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCBRR2 - Bit Rate Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
- }
- break;
-
- case SCSCR2_SCFTDR2:
- {
- if (mem_mask & 0xff000000)
- {
- logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSCR2 - Serial Control Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
-
- if (mem_mask & 0x0000ff00)
- {
- logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
- }
- break;
-
- case SCSSR2_SCFRDR2:
- {
- if (mem_mask & 0xffff0000)
- {
- logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSSR2 - Serial Status Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
-
- if (mem_mask & 0x0000ff00)
- {
- logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFRDR2 - Receive FIFO Data Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
- }
- break;
-
- case SCFCR2_SCFDR2:
- {
- if (mem_mask & 0xff000000)
- {
- logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFCR2 - Fifo Control Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
-
- if (mem_mask & 0x0000ffff)
- {
- logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFDR2 - Fifo Data Count Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
- }
- }
- break;
-
- default:
- {
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x\n",
- tag(), m_sh2_state->pc & SH34_AM,
- (offset *4)+0x4000000,
- data,
- mem_mask);
- }
- break;
- }
-
- }
- else
- {
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x\n",
- tag(), m_sh2_state->pc & SH34_AM,
- (offset *4)+0x4000000,
- data,
- mem_mask);
- }
+void sh3_base_device::sdmr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal write %02x & %02x @ %05x (SDMR)\n", tag(), m_sh2_state->pc, data, mem_mask, offset);
+}
+
+// BSC 7708
+uint16_t sh3_base_device::dcr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (DCR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_dcr);
+ return m_dcr;
+}
+
+void sh3_base_device::dcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_dcr);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (DCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::pctr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (PCTR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_pctr);
+ return m_pctr;
+}
+
+void sh3_base_device::pctr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_pctr);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (PCTR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::pdtr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (PDTR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_pdtr);
+ return m_pdtr;
+}
+
+void sh3_base_device::pdtr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_pdtr);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (PDTR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// BSC 7709
+uint16_t sh3_base_device::bcr3_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (BCR3) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_bcr3);
+ return m_bcr3;
+}
+
+void sh3_base_device::bcr3_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_bcr3);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (BCR3)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// BSC 7709S
+uint16_t sh3_base_device::mcscr0_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (MCSCR0) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_mcscr0);
+ return m_mcscr0;
+}
+
+void sh3_base_device::mcscr0_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_mcscr0);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (MCSCR0)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::mcscr1_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (MCSCR1) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_mcscr1);
+ return m_mcscr1;
+}
+
+void sh3_base_device::mcscr1_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_mcscr1);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (MCSCR1)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::mcscr2_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (MCSCR2) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_mcscr2);
+ return m_mcscr2;
+}
+
+void sh3_base_device::mcscr2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_mcscr2);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (MCSCR2)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::mcscr3_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (MCSCR3) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_mcscr3);
+ return m_mcscr3;
+}
+
+void sh3_base_device::mcscr3_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_mcscr3);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (MCSCR3)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::mcscr4_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (MCSCR4) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_mcscr4);
+ return m_mcscr4;
+}
+
+void sh3_base_device::mcscr4_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_mcscr4);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (MCSCR4)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::mcscr5_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (MCSCR5) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_mcscr5);
+ return m_mcscr5;
+}
+
+void sh3_base_device::mcscr5_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_mcscr5);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (MCSCR5)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::mcscr6_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (MCSCR6) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_mcscr6);
+ return m_mcscr6;
+}
+
+void sh3_base_device::mcscr6_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_mcscr6);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (MCSCR6)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::mcscr7_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): BSC unmapped internal read mask %04x (MCSCR7) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_mcscr7);
+ return m_mcscr7;
+}
+
+void sh3_base_device::mcscr7_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_mcscr7);
+ logerror("'%s' (%08x): BSC unmapped internal write %04x & %04x (MCSCR7)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// RTC
+uint8_t sh3_base_device::r64cnt_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): RTC unmapped internal read mask %02x (R64CNT) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_r64cnt);
+ return m_r64cnt;
+}
+
+uint8_t sh3_base_device::rseccnt_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): RTC unmapped internal read mask %02x (RSECCNT) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_rseccnt);
+ return m_rseccnt;
+}
+
+void sh3_base_device::rseccnt_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rseccnt);
+ logerror("'%s' (%08x): RTC unmapped internal write %02x & %02x (RSECCNT)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::rmincnt_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): RTC unmapped internal read mask %02x (RMINCNT) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_rseccnt);
+ return m_rmincnt;
+}
+
+void sh3_base_device::rmincnt_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rmincnt);
+ logerror("'%s' (%08x): RTC unmapped internal write %02x & %02x (RMINCNT)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::rhrcnt_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): RTC unmapped internal read mask %02x (RHRCNT) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_rhrcnt);
+ return m_rhrcnt;
+}
+
+void sh3_base_device::rhrcnt_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rhrcnt);
+ logerror("'%s' (%08x): RTC unmapped internal write %02x & %02x (RHRCNT)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::rwkcnt_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): RTC unmapped internal read mask %02x (RWKCNT) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_rhrcnt);
+ return m_rwkcnt;
+}
+
+void sh3_base_device::rwkcnt_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rwkcnt);
+ logerror("'%s' (%08x): RTC unmapped internal write %02x & %02x (RWKCNT)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::rdaycnt_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): RTC unmapped internal read mask %02x (RDAYCNT) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_rdaycnt);
+ return m_rdaycnt;
+}
+
+void sh3_base_device::rdaycnt_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rdaycnt);
+ logerror("'%s' (%08x): RTC unmapped internal write %02x & %02x (RDAYCNT)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::rmoncnt_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): RTC unmapped internal read mask %02x (RMONCNT) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_rmoncnt);
+ return m_rmoncnt;
+}
+
+void sh3_base_device::rmoncnt_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rmoncnt);
+ logerror("'%s' (%08x): RTC unmapped internal write %02x & %02x (RMONCNT)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::ryrcnt_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): RTC unmapped internal read mask %02x (RYRCNT) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_ryrcnt);
+ return m_ryrcnt;
+}
+
+void sh3_base_device::ryrcnt_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_ryrcnt);
+ logerror("'%s' (%08x): RTC unmapped internal write %02x & %02x (RYRCNT)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::rsecar_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): RTC unmapped internal read mask %02x (RSECAR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_rsecar);
+ return m_rsecar;
+}
+
+void sh3_base_device::rsecar_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rsecar);
+ logerror("'%s' (%08x): RTC unmapped internal write %02x & %02x (RSECAR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::rminar_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): RTC unmapped internal read mask %02x (RMINAR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_rminar);
+ return m_rminar;
+}
+
+void sh3_base_device::rminar_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rminar);
+ logerror("'%s' (%08x): RTC unmapped internal write %02x & %02x (RMINAR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::rhrar_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): RTC unmapped internal read mask %02x (RHRAR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_rhrar);
+ return m_rhrar;
+}
+
+void sh3_base_device::rhrar_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rhrar);
+ logerror("'%s' (%08x): RTC unmapped internal write %02x & %02x (RHRAR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::rwkar_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): RTC unmapped internal read mask %02x (RWKAR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_rhrar);
+ return m_rwkar;
+}
+
+void sh3_base_device::rwkar_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rwkar);
+ logerror("'%s' (%08x): RTC unmapped internal write %02x & %02x (RWKAR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::rdayar_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): RTC unmapped internal read mask %02x (RDAYAR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_rdayar);
+ return m_rdayar;
+}
+
+void sh3_base_device::rdayar_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rdayar);
+ logerror("'%s' (%08x): RTC unmapped internal write %02x & %02x (RDAYAR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::rmonar_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): RTC unmapped internal read mask %02x (RMONAR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_rmonar);
+ return m_rmonar;
+}
+
+void sh3_base_device::rmonar_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rmonar);
+ logerror("'%s' (%08x): RTC unmapped internal write %02x & %02x (RMONAR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::rcr1_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): RTC unmapped internal read mask %02x (RCR1) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_rcr1);
+ return m_rcr1;
+}
+
+void sh3_base_device::rcr1_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rcr1);
+ logerror("'%s' (%08x): RTC unmapped internal write %02x & %02x (RCR1)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::rcr2_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): RTC unmapped internal read mask %04x (RCR2) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_rcr2);
+ return m_rcr2;
+}
+
+void sh3_base_device::rcr2_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rcr2);
+ logerror("'%s' (%08x): RTC unmapped internal write %02x & %02x (RCR2)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// INTC
+uint16_t sh3_base_device::icr0_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): INTC unmapped internal read mask %04x (ICR0) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_icr0);
+ return m_icr0;
+}
+
+void sh3_base_device::icr0_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_icr0);
+ logerror("'%s' (%08x): INTC unmapped internal write %04x & %04x (ICR0)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::iprb_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): INTC unmapped internal read mask %04x (IPRB) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_iprb);
+ return m_iprb;
+}
+
+void sh3_base_device::iprb_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_iprb);
+ logerror("'%s' (%08x): INTC unmapped internal write %04x & %04x (IPRB)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// INTC 7709
+uint32_t sh3_base_device::intevt2_r(offs_t offset, uint32_t mem_mask)
+{
+ //logerror("'%s' (%08x): INTC unmapped internal read mask %08x (INTEVT2) %08x\n", tag(), m_sh2_state->pc, mem_mask, m_intevt2);
+ return m_intevt2;
+}
+
+void sh3_base_device::intevt2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_intevt2);
+ logerror("'%s' (%08x): INTC unmapped internal write %08x & %08x (INTEVT2)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+uint8_t sh3_base_device::irr0_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): INTC unmapped internal read mask %02x (IRR0) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_irr0);
+ return m_irr0;
+}
+
+void sh3_base_device::irr0_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_irr0);
+ logerror("'%s' (%08x): INTC unmapped internal write %02x & %02x (IRR0)\n", tag(), m_sh2_state->pc, data, mem_mask);
+ // not sure if this is how we should clear lines in this core...
+ if (!(data & 0x01000000)) execute_set_input(0, CLEAR_LINE);
+ if (!(data & 0x02000000)) execute_set_input(1, CLEAR_LINE);
+ if (!(data & 0x04000000)) execute_set_input(2, CLEAR_LINE);
+ if (!(data & 0x08000000)) execute_set_input(3, CLEAR_LINE);
+}
+
+uint8_t sh3_base_device::irr1_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): INTC unmapped internal read mask %02x (IRR1) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_irr1);
+ return m_irr1;
+}
+
+void sh3_base_device::irr1_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_irr1);
+ logerror("'%s' (%08x): INTC unmapped internal write %02x & %02x (IRR1)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::irr2_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): INTC unmapped internal read mask %02x (IRR2) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_irr2);
+ return m_irr2;
+}
+
+void sh3_base_device::irr2_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_irr2);
+ logerror("'%s' (%08x): INTC unmapped internal write %02x & %02x (IRR2)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::icr1_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): INTC unmapped internal read mask %04x (ICR1) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_icr1);
+ return m_icr1;
+}
+
+void sh3_base_device::icr1_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_icr1);
+ logerror("'%s' (%08x): INTC unmapped internal write %04x & %04x (ICR1)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::icr2_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): INTC unmapped internal read mask %04x (ICR2) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_icr2);
+ return m_icr2;
+}
+
+void sh3_base_device::icr2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_icr2);
+ logerror("'%s' (%08x): INTC unmapped internal write %04x & %04x (ICR2)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::pinter_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): INTC unmapped internal read mask %04x (PINTER) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_pinter);
+ return m_pinter;
+}
+
+void sh3_base_device::pinter_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_pinter);
+ logerror("'%s' (%08x): INTC unmapped internal write %04x & %04x (PINTER)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::iprc_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): INTC unmapped internal read mask %04x (IPRC) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_iprc);
+ return m_iprc;
+}
+
+void sh3_base_device::iprc_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_iprc);
+ logerror("'%s' (%08x): INTC internal write %04x & %04x (IPRC)\n", tag(), m_sh2_state->pc, data, mem_mask);
+ m_exception_priority[SH4_INTC_IRL0] = INTPRI((m_iprc & 0x000f) >> 0, SH4_INTC_IRL0);
+ m_exception_priority[SH4_INTC_IRL1] = INTPRI((m_iprc & 0x00f0) >> 4, SH4_INTC_IRL1);
+ m_exception_priority[SH4_INTC_IRL2] = INTPRI((m_iprc & 0x0f00) >> 8, SH4_INTC_IRL2);
+ m_exception_priority[SH4_INTC_IRL3] = INTPRI((m_iprc & 0xf000) >> 12, SH4_INTC_IRL3);
+ sh4_exception_recompute();
+}
+
+uint16_t sh3_base_device::iprd_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): INTC unmapped internal read mask %04x (IPRD) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_iprd);
+ return m_iprd;
+}
+
+void sh3_base_device::iprd_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_iprd);
+ logerror("'%s' (%08x): INTC internal write %04x & %04x (IPRD)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::ipre_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): INTC unmapped internal read mask %04x (IPRE) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_ipre);
+ return m_ipre;
+}
+
+void sh3_base_device::ipre_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_ipre);
+ logerror("'%s' (%08x): INTC internal write %04x & %04x (IPRE)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// SCI
+uint8_t sh3_base_device::scsmr_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): SCI unmapped internal read mask %02x (SCSMR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scsmr);
+ return m_scsmr;
+}
+
+void sh3_base_device::scsmr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scsmr);
+ logerror("'%s' (%08x): SCI unmapped internal write %02x & %02x (SCSMR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::scbrr_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): SCI unmapped internal read mask %02x (SCBRR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scbrr);
+ return m_scbrr;
+}
+
+void sh3_base_device::scbrr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scbrr);
+ logerror("'%s' (%08x): SCSI unmapped internal write %02x & %02x (SCBRR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::scscr_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): SCI unmapped internal read mask %02x (SCSCR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scscr);
+ return m_scscr;
+}
+
+void sh3_base_device::scscr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scscr);
+ logerror("'%s' (%08x): SCI unmapped internal write %02x & %02x (SCSCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::sctdr_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): SCI unmapped internal read mask %02x (SCTDR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_sctdr);
+ return m_sctdr;
+}
+
+void sh3_base_device::sctdr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_sctdr);
+ logerror("'%s' (%08x): SCI unmapped internal write %02x & %02x (SCTDR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::scssr_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): SCI unmapped internal read mask %02x (SCSSR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scssr);
+ return m_scssr;
+}
+
+void sh3_base_device::scssr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ m_scssr = (m_scssr | (data & 1)) & (data | 6);
+ logerror("'%s' (%08x): SCI unmapped internal write %02x & %02x (SCSSR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::scrdr_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): SCI unmapped internal read mask %02x (SCRDR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scrdr);
+ return m_scrdr;
+}
+
+uint8_t sh3_base_device::scscmr_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): SCI unmapped internal read mask %02x (SCSCMR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scscmr);
+ return m_scscmr;
+}
+
+void sh3_base_device::scscmr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scscmr);
+ logerror("'%s' (%08x): SCI unmapped internal write %02x & %02x (SCSCMR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// SCI 7708
+uint8_t sh3_base_device::scsptr_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): SCI unmapped internal read mask %02x (SCSPTR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scsptr);
+ return m_scsptr;
+}
+
+void sh3_base_device::scsptr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scsptr);
+ logerror("'%s' (%08x): SCI unmapped internal write %02x & %02x (SCSPTR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// CMT 7709
+uint16_t sh3_base_device::cmstr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): CMT unmapped internal read mask %04x (CMSTR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_cmstr);
+ return m_cmstr;
+}
+
+void sh3_base_device::cmstr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_cmstr);
+ logerror("'%s' (%08x): CMT unmapped internal write %04x & %04x (CMSTR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::cmscr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): CMT unmapped internal read mask %04x (CMSCR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_cmscr);
+ return m_cmscr;
+}
+
+void sh3_base_device::cmscr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_cmscr);
+ logerror("'%s' (%08x): CMT unmapped internal write %04x & %04x (CMSCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::cmcnt_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): CMT unmapped internal read mask %04x (CMCNT) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_cmcnt);
+ return m_cmcnt;
+}
+
+void sh3_base_device::cmcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_cmcnt);
+ logerror("'%s' (%08x): CMT unmapped internal write %04x & %04x (CMCNT)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::cmcor_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): CMT unmapped internal read mask %04x (CMCOR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_cmcor);
+ return m_cmcor;
+}
+
+void sh3_base_device::cmcor_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_cmcor);
+ logerror("'%s' (%08x): CMT unmapped internal write %04x & %04x (CMCOR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// AD 7709
+uint8_t sh3_base_device::addrah_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): AD unmapped internal read mask %02x (ADDRAH) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_addrah);
+ return m_addrah;
+}
+
+void sh3_base_device::addrah_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_addrah);
+ logerror("'%s' (%08x): AD unmapped internal write %02x & %02x (ADDRAH)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::addral_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): AD unmapped internal read mask %02x (ADDRAL) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_addral);
+ return m_addral;
+}
+
+void sh3_base_device::addral_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_addral);
+ logerror("'%s' (%08x): AD unmapped internal write %02x & %02x (ADDRAL)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::addrbh_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): AD unmapped internal read mask %02x (ADDRBH) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_addrbh);
+ return m_addrbh;
+}
+
+void sh3_base_device::addrbh_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_addrbh);
+ logerror("'%s' (%08x): AD unmapped internal write %02x & %02x (ADDRBH)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::addrbl_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): AD unmapped internal read mask %02x (ADDRBL) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_addrbl);
+ return m_addrbl;
+}
+
+void sh3_base_device::addrbl_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_addrbl);
+ logerror("'%s' (%08x): AD unmapped internal write %02x & %02x (ADDRBL)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::addrch_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): AD unmapped internal read mask %02x (ADDRCH) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_addrch);
+ return m_addrch;
+}
+
+void sh3_base_device::addrch_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_addrch);
+ logerror("'%s' (%08x): AD unmapped internal write %02x & %02x (ADDRCH)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::addrcl_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): AD unmapped internal read mask %02x (ADDRCL) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_addrcl);
+ return m_addrcl;
+}
+
+void sh3_base_device::addrcl_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_addrcl);
+ logerror("'%s' (%08x): AD unmapped internal write %02x & %02x (ADDRCL)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::addrdh_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): AD unmapped internal read mask %02x (ADDRDH) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_addrdh);
+ return m_addrdh;
+}
+
+void sh3_base_device::addrdh_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_addrdh);
+ logerror("'%s' (%08x): AD unmapped internal write %02x & %02x (ADDRDH)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::addrdl_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): AD unmapped internal read mask %02x (ADDRDL) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_addrdl);
+ return m_addrdl;
+}
+
+void sh3_base_device::addrdl_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_addrdl);
+ logerror("'%s' (%08x): AD unmapped internal write %02x & %02x (ADDRDL)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::adcsr_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): AD unmapped internal read mask %02x (ADCSR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_adcsr);
+ return m_adcsr;
+}
+
+void sh3_base_device::adcsr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_adcsr);
+ logerror("'%s' (%08x): AD unmapped internal write %02x & %02x (ADCSR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::adcr_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): AD unmapped internal read mask %02x (ADCR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_adcr);
+ return m_adcr;
+}
+
+void sh3_base_device::adcr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_adcr);
+ logerror("'%s' (%08x): AD unmapped internal write %02x & %02x (ADCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// DA 7709
+uint8_t sh3_base_device::dadr0_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): DA unmapped internal read mask %02x (DADR0) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_dadr0);
+ return m_dadr0;
+}
+
+void sh3_base_device::dadr0_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_dadr0);
+ logerror("'%s' (%08x): AD unmapped internal write %02x & %02x (DADR0)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::dadr1_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): DA unmapped internal read mask %02x (DADR1) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_dadr1);
+ return m_dadr1;
+}
+
+void sh3_base_device::dadr1_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_dadr1);
+ logerror("'%s' (%08x): AD unmapped internal write %02x & %02x (DADR1)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::dadcr_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): DA unmapped internal read mask %02x (DADCR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_dadcr);
+ return m_dadcr;
+}
+
+void sh3_base_device::dadcr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_dadcr);
+ logerror("'%s' (%08x): AD unmapped internal write %02x & %02x (DADCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// PORT 7709
+uint16_t sh3_base_device::pacr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): PORT unmapped internal read mask %04x (PACR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_pacr);
+ return m_pacr;
+}
+
+void sh3_base_device::pacr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_pacr);
+ logerror("'%s' (%08x): PORT unmapped internal write %04x & %04x (PACR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::pbcr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): PORT unmapped internal read mask %04x (PBCR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_pbcr);
+ return m_pbcr;
+}
+
+void sh3_base_device::pbcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_pbcr);
+ logerror("'%s' (%08x): PORT unmapped internal write %04x & %04x (PBCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::pccr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): PORT unmapped internal read mask %04x (PCCR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_pccr);
+ return m_pccr;
+}
+
+void sh3_base_device::pccr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_pccr);
+ logerror("'%s' (%08x): PORT unmapped internal write %04x & %04x (PCCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::pdcr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): PORT unmapped internal read mask %04x (PDCR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_pdcr);
+ return m_pdcr;
+}
+
+void sh3_base_device::pdcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_pdcr);
+ logerror("'%s' (%08x): PORT unmapped internal write %04x & %04x (PDCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::pecr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): PORT unmapped internal read mask %04x (PECR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_pecr);
+ return m_pecr;
+}
+
+void sh3_base_device::pecr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_pecr);
+ logerror("'%s' (%08x): PORT unmapped internal write %04x & %04x (PECR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::pfcr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): PORT unmapped internal read mask %04x (PFCR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_pfcr);
+ return m_pfcr;
+}
+
+void sh3_base_device::pfcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_pfcr);
+ logerror("'%s' (%08x): PORT unmapped internal write %04x & %04x (PFCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::pgcr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): PORT unmapped internal read mask %04x (PGCR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_pgcr);
+ return m_pgcr;
+}
+
+void sh3_base_device::pgcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_pgcr);
+ logerror("'%s' (%08x): PORT unmapped internal write %04x & %04x (PGCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::phcr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): PORT unmapped internal read mask %04x (PHCR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_phcr);
+ return m_phcr;
+}
+
+void sh3_base_device::phcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_phcr);
+ logerror("'%s' (%08x): PORT unmapped internal write %04x & %04x (PHCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::pjcr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): PORT unmapped internal read mask %04x (PJCR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_pjcr);
+ return m_pjcr;
+}
+
+void sh3_base_device::pjcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_pjcr);
+ logerror("'%s' (%08x): PORT unmapped internal write %04x & %04x (PJCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::pkcr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): PORT unmapped internal read mask %04x (PKCR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_pkcr);
+ return m_pkcr;
+}
+
+void sh3_base_device::pkcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_pkcr);
+ logerror("'%s' (%08x): PORT unmapped internal write %04x & %04x (PKCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::plcr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): PORT unmapped internal read mask %04x (PLCR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_plcr);
+ return m_plcr;
+}
+
+void sh3_base_device::plcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_plcr);
+ logerror("'%s' (%08x): PORT unmapped internal write %04x & %04x (PLCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::scpcr_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): PORT unmapped internal read mask %04x (SCPCR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_scpcr);
+ return m_scpcr;
+}
+
+void sh3_base_device::scpcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_scpcr);
+ logerror("'%s' (%08x): PORT unmapped internal write %04x & %04x (SCPCR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::padr_r(offs_t offset, uint8_t mem_mask)
+{
+ //logerror("'%s' (%08x): PORT unmapped internal read mask %02x (PADR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_padr);
+ return m_io->read_qword(SH3_PORT_A);
+}
+
+void sh3_base_device::padr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_padr);
+ //logerror("'%s' (%08x): PORT unmapped internal write %02x & %02x (PADR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+ m_io->write_qword(SH3_PORT_A, data);
+}
+
+uint8_t sh3_base_device::pbdr_r(offs_t offset, uint8_t mem_mask)
+{
+ //logerror("'%s' (%08x): PORT unmapped internal read mask %02x (PBDR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_padr);
+ return m_io->read_qword(SH3_PORT_B);
+}
+
+void sh3_base_device::pbdr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_pbdr);
+ //logerror("'%s' (%08x): PORT unmapped internal write %02x & %02x (PBDR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+ m_io->write_qword(SH3_PORT_B, data);
+}
+
+uint8_t sh3_base_device::pcdr_r(offs_t offset, uint8_t mem_mask)
+{
+ //logerror("'%s' (%08x): PORT unmapped internal read mask %02x (PCDR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_pcdr);
+ return m_io->read_qword(SH3_PORT_C);
+}
+
+void sh3_base_device::pcdr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_pcdr);
+ //logerror("'%s' (%08x): PORT unmapped internal write %02x & %02x (PCDR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+ m_io->write_qword(SH3_PORT_C, data);
+}
+
+uint8_t sh3_base_device::pddr_r(offs_t offset, uint8_t mem_mask)
+{
+ //logerror("'%s' (%08x): PORT unmapped internal read mask %02x (PDDR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_pddr);
+ return m_io->read_qword(SH3_PORT_D);
+}
+
+void sh3_base_device::pddr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_pddr);
+ //logerror("'%s' (%08x): PORT unmapped internal write %02x & %02x (PDDR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+ m_io->write_qword(SH3_PORT_D, data);
+}
+
+uint8_t sh3_base_device::pedr_r(offs_t offset, uint8_t mem_mask)
+{
+ //logerror("'%s' (%08x): PORT unmapped internal read mask %02x (PEDR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_pedr);
+ return m_io->read_qword(SH3_PORT_E);
+}
+
+void sh3_base_device::pedr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_pedr);
+ //logerror("'%s' (%08x): PORT unmapped internal write %02x & %02x (PEDR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+ m_io->write_qword(SH3_PORT_E, data);
+}
+
+uint8_t sh3_base_device::pfdr_r(offs_t offset, uint8_t mem_mask)
+{
+ //logerror("'%s' (%08x): PORT unmapped internal read mask %02x (PFDR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_pfdr);
+ return m_io->read_qword(SH3_PORT_F);
+}
+
+void sh3_base_device::pfdr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_pfdr);
+ //logerror("'%s' (%08x): PORT unmapped internal write %02x & %02x (PFDR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+ m_io->write_qword(SH3_PORT_F, data);
+}
+
+uint8_t sh3_base_device::pgdr_r(offs_t offset, uint8_t mem_mask)
+{
+ //logerror("'%s' (%08x): PORT unmapped internal read mask %02x (PGDR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_pgdr);
+ return m_io->read_qword(SH3_PORT_G);
+}
+
+void sh3_base_device::pgdr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_pgdr);
+ //logerror("'%s' (%08x): PORT unmapped internal write %02x & %02x (PGDR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+ m_io->write_qword(SH3_PORT_G, data);
+}
+
+uint8_t sh3_base_device::phdr_r(offs_t offset, uint8_t mem_mask)
+{
+ //logerror("'%s' (%08x): PORT unmapped internal read mask %02x (PHDR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_phdr);
+ return m_io->read_qword(SH3_PORT_H);
+}
+
+void sh3_base_device::phdr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_phdr);
+ //logerror("'%s' (%08x): PORT unmapped internal write %02x & %02x (PHDR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+ m_io->write_qword(SH3_PORT_H, data);
+}
+
+uint8_t sh3_base_device::pjdr_r(offs_t offset, uint8_t mem_mask)
+{
+ //logerror("'%s' (%08x): PORT unmapped internal read mask %02x (PJDR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_pjdr);
+ return m_io->read_qword(SH3_PORT_J);
+}
+
+void sh3_base_device::pjdr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_pjdr);
+ //logerror("'%s' (%08x): PORT unmapped internal write %02x & %02x (PJDR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+ m_io->write_qword(SH3_PORT_J, data);
+}
+
+uint8_t sh3_base_device::pkdr_r(offs_t offset, uint8_t mem_mask)
+{
+ //logerror("'%s' (%08x): PORT unmapped internal read mask %02x (PKDR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_pkdr);
+ return m_io->read_qword(SH3_PORT_K);
+}
+
+void sh3_base_device::pkdr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_pkdr);
+ //logerror("'%s' (%08x): PORT unmapped internal write %02x & %02x (PKDR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+ m_io->write_qword(SH3_PORT_K, data);
+}
+
+uint8_t sh3_base_device::pldr_r(offs_t offset, uint8_t mem_mask)
+{
+ //logerror("'%s' (%08x): PORT unmapped internal read mask %02x (PLDR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_pldr);
+ return m_io->read_qword(SH3_PORT_L);
+}
+
+void sh3_base_device::pldr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_pldr);
+ //logerror("'%s' (%08x): PORT unmapped internal write %02x & %02x (PLDR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+ m_io->write_qword(SH3_PORT_L, data);
+}
+
+uint8_t sh3_base_device::scpdr_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): PORT unmapped internal read mask %02x (SCPDR) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scpdr);
+ return m_scpdr;
+}
+
+void sh3_base_device::scpdr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scpdr);
+ logerror("'%s' (%08x): PORT unmapped internal write %02x & %02x (SCPDR)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// IRDA 7709
+uint8_t sh3_base_device::scsmr1_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): IRDA unmapped internal read mask %02x (SCSMR1) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scsmr1);
+ return m_scsmr1;
+}
+
+void sh3_base_device::scsmr1_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scsmr1);
+ logerror("'%s' (%08x): IRDA unmapped internal write %02x & %02x (SCSMR1)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::scbrr1_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): IRDA unmapped internal read mask %02x (SCBRR1) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scbrr1);
+ return m_scbrr1;
+}
+
+void sh3_base_device::scbrr1_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scbrr1);
+ logerror("'%s' (%08x): IRDA unmapped internal write %02x & %02x (SCBRR1)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::scscr1_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): IRDA unmapped internal read mask %02x (SCSCR1) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scscr1);
+ return m_scscr1;
+}
+
+void sh3_base_device::scscr1_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scscr1);
+ logerror("'%s' (%08x): IRDA unmapped internal write %02x & %02x (SCSCR1)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::scftdr1_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): IRDA unmapped internal read mask %02x (SCFTDR1) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scftdr1);
+ return m_scftdr1;
+}
+
+void sh3_base_device::scftdr1_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scftdr1);
+ logerror("'%s' (%08x): IRDA unmapped internal write %02x & %02x (SCFTDR1)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::scssr1_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): IRDA unmapped internal read mask %04x (SCSSR1) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_scssr1);
+ return m_scssr1;
+}
+
+void sh3_base_device::scssr1_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_scssr1);
+ logerror("'%s' (%08x): IRDA unmapped internal write %04x & %04x (SCSSR1)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::scfrdr1_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): IRDA unmapped internal read mask %02x (SCFRDR1) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scfrdr1);
+ return m_scfrdr1;
+}
+
+void sh3_base_device::scfrdr1_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scfrdr1);
+ logerror("'%s' (%08x): IRDA unmapped internal write %02x & %02x (SCFRDR1)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::scfcr1_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): IRDA unmapped internal read mask %02x (SCFCR1) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scfcr1);
+ return m_scfcr1;
+}
+
+void sh3_base_device::scfcr1_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scfcr1);
+ logerror("'%s' (%08x): IRDA unmapped internal write %02x & %02x (SCFCR1)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::scfdr1_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): IRDA unmapped internal read mask %04x (SCFDR1) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_scfdr1);
+ return m_scfdr1;
+}
+
+void sh3_base_device::scfdr1_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_scfdr1);
+ logerror("'%s' (%08x): IRDA unmapped internal write %04x & %04x (SCFDR1)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// SCIF 7709
+uint8_t sh3_base_device::scsmr2_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): SCIF unmapped internal read mask %02x (SCSMR2) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scsmr2);
+ return m_scsmr2;
+}
+
+void sh3_base_device::scsmr2_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scsmr2);
+ logerror("'%s' (%08x): SCIF unmapped internal write %02x & %02x (SCSMR2)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::scbrr2_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): SCIF unmapped internal read mask %02x (SCBRR2) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scbrr2);
+ return m_scbrr2;
+}
+
+void sh3_base_device::scbrr2_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scbrr2);
+ logerror("'%s' (%08x): SCIF unmapped internal write %02x & %02x (SCBRR2)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::scscr2_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): SCIF unmapped internal read mask %02x (SCSCR2) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scscr2);
+ return m_scscr2;
+}
+
+void sh3_base_device::scscr2_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scscr2);
+ logerror("'%s' (%08x): SCIF unmapped internal write %02x & %02x (SCSCR2)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::scftdr2_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): SCIF unmapped internal read mask %02x (SCFTDR2) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scftdr2);
+ return m_scftdr2;
+}
+
+void sh3_base_device::scftdr2_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scftdr2);
+ logerror("'%s' (%08x): SCIF unmapped internal write %02x & %02x (SCFTDR2)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::scssr2_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): SCIF unmapped internal read mask %04x (SCSSR2) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_scssr2);
+ return m_scssr2;
+}
+
+void sh3_base_device::scssr2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_scssr2);
+ logerror("'%s' (%08x): SCIF unmapped internal write %04x & %04x (SCSSR2)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::scfrdr2_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): SCIF unmapped internal read mask %02x (SCFRDR2) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scfrdr2);
+ return m_scfrdr2;
+}
+
+void sh3_base_device::scfrdr2_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scfrdr2);
+ logerror("'%s' (%08x): SCIF unmapped internal write %02x & %02x (SCFRDR2)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint8_t sh3_base_device::scfcr2_r(offs_t offset, uint8_t mem_mask)
+{
+ logerror("'%s' (%08x): SCIF unmapped internal read mask %02x (SCFCR2) %02x\n", tag(), m_sh2_state->pc, mem_mask, m_scfcr2);
+ return m_scfcr2;
+}
+
+void sh3_base_device::scfcr2_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scfcr2);
+ logerror("'%s' (%08x): SCIF unmapped internal write %02x & %02x (SCFCR2)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+uint16_t sh3_base_device::scfdr2_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): SCIF unmapped internal read mask %04x (SCFDR2) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_scfdr2);
+ return m_scfdr2;
+}
+
+void sh3_base_device::scfdr2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_scfdr2);
+ logerror("'%s' (%08x): SCIF unmapped internal write %04x & %04x (SCFDR2)\n", tag(), m_sh2_state->pc, data, mem_mask);
+}
+
+// UDI 7709S
+uint16_t sh3_base_device::sdir_r(offs_t offset, uint16_t mem_mask)
+{
+ logerror("'%s' (%08x): UDI unmapped internal read mask %04x (SDIR) %04x\n", tag(), m_sh2_state->pc, mem_mask, m_sdir);
+ return m_sdir;
+}
+
+void sh3_base_device::sdir_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_sdir);
+ logerror("'%s' (%08x): UDI unmapped internal write %04x & %04x (SDIR)\n", tag(), m_sh2_state->pc, data, mem_mask);
}
diff --git a/src/devices/cpu/sh/sh3comn.h b/src/devices/cpu/sh/sh3comn.h
index 29aeef4cead..b735cdebec9 100644
--- a/src/devices/cpu/sh/sh3comn.h
+++ b/src/devices/cpu/sh/sh3comn.h
@@ -22,77 +22,4 @@
#define SH3_PORT_K (0x19*8)
#define SH3_PORT_L (0x1a*8)
-/* SH3 lower area regs */
-
-#define SH3_LOWER_REGBASE (0x04000000)
-#define SH3_LOWER_REGEND (0x07ffffff)
-
-#define INTEVT2 ((0x4000000 - SH3_LOWER_REGBASE)/4)
-#define IRR0_IRR1 ((0x4000004 - SH3_LOWER_REGBASE)/4)
-#define PINTER_IPRC ((0x4000014 - SH3_LOWER_REGBASE)/4)
-
-#define SH3_SAR0_ADDR ((0x4000020 - SH3_LOWER_REGBASE)/4)
-#define SH3_DAR0_ADDR ((0x4000024 - SH3_LOWER_REGBASE)/4)
-#define SH3_DMATCR0_ADDR ((0x4000028 - SH3_LOWER_REGBASE)/4)
-#define SH3_CHCR0_ADDR ((0x400002c - SH3_LOWER_REGBASE)/4)
-#define SH3_SAR1_ADDR ((0x4000030 - SH3_LOWER_REGBASE)/4)
-#define SH3_DAR1_ADDR ((0x4000034 - SH3_LOWER_REGBASE)/4)
-#define SH3_DMATCR1_ADDR ((0x4000038 - SH3_LOWER_REGBASE)/4)
-#define SH3_CHCR1_ADDR ((0x400003c - SH3_LOWER_REGBASE)/4)
-#define SH3_SAR2_ADDR ((0x4000040 - SH3_LOWER_REGBASE)/4)
-#define SH3_DAR2_ADDR ((0x4000044 - SH3_LOWER_REGBASE)/4)
-#define SH3_DMATCR2_ADDR ((0x4000048 - SH3_LOWER_REGBASE)/4)
-#define SH3_CHCR2_ADDR ((0x400004c - SH3_LOWER_REGBASE)/4)
-#define SH3_SAR3_ADDR ((0x4000050 - SH3_LOWER_REGBASE)/4)
-#define SH3_DAR3_ADDR ((0x4000054 - SH3_LOWER_REGBASE)/4)
-#define SH3_DMATCR3_ADDR ((0x4000058 - SH3_LOWER_REGBASE)/4)
-#define SH3_CHCR3_ADDR ((0x400005c - SH3_LOWER_REGBASE)/4)
-#define SH3_DMAOR_ADDR ((0x4000060 - SH3_LOWER_REGBASE)/4)
-
-
-#define PCCR_PDCR ((0x4000104 - SH3_LOWER_REGBASE)/4)
-#define PECR_PFCR ((0x4000108 - SH3_LOWER_REGBASE)/4)
-#define PGCR_PHCR ((0x400010c - SH3_LOWER_REGBASE)/4)
-#define PJCR_PKCR ((0x4000110 - SH3_LOWER_REGBASE)/4)
-#define PLCR_SCPCR ((0x4000114 - SH3_LOWER_REGBASE)/4)
-
-#define PADR_PBDR ((0x4000120 - SH3_LOWER_REGBASE)/4)
-#define PCDR_PDDR ((0x4000124 - SH3_LOWER_REGBASE)/4)
-#define PEDR_PFDR ((0x4000128 - SH3_LOWER_REGBASE)/4)
-#define PGDR_PHDR ((0x400012c - SH3_LOWER_REGBASE)/4)
-#define PJDR_PKDR ((0x4000130 - SH3_LOWER_REGBASE)/4)
-#define PLDR_SCPDR ((0x4000134 - SH3_LOWER_REGBASE)/4)
-
-#define SCSMR2_SCBRR2 ((0x4000150 - SH3_LOWER_REGBASE)/4)
-#define SCSCR2_SCFTDR2 ((0x4000154 - SH3_LOWER_REGBASE)/4)
-#define SCSSR2_SCFRDR2 ((0x4000158 - SH3_LOWER_REGBASE)/4)
-#define SCFCR2_SCFDR2 ((0x400015c - SH3_LOWER_REGBASE)/4)
-
-
-/* SH3 upper area */
-
-
-#define SH3_UPPER_REGBASE (0xffffd000)
-#define SH3_UPPER_REGEND (0xffffffff)
-
-#define SH3_ICR0_IPRA_ADDR ((0xfffffee0 - SH3_UPPER_REGBASE)/4)
-#define SH3_IPRB_ADDR ((0xfffffee4 - SH3_UPPER_REGBASE)/4)
-
-#define SH3_SCSSR_ADDR ((0xfffffe88 - SH3_UPPER_REGBASE)/4)
-
-#define SH3_TOCR_TSTR_ADDR ((0xfffffe90 - SH3_UPPER_REGBASE)/4)
-#define SH3_TCOR0_ADDR ((0xfffffe94 - SH3_UPPER_REGBASE)/4)
-#define SH3_TCNT0_ADDR ((0xfffffe98 - SH3_UPPER_REGBASE)/4)
-#define SH3_TCR0_ADDR ((0xfffffe9c - SH3_UPPER_REGBASE)/4)
-#define SH3_TCOR1_ADDR ((0xfffffea0 - SH3_UPPER_REGBASE)/4)
-#define SH3_TCNT1_ADDR ((0xfffffea4 - SH3_UPPER_REGBASE)/4)
-#define SH3_TCR1_ADDR ((0xfffffea8 - SH3_UPPER_REGBASE)/4)
-#define SH3_TCOR2_ADDR ((0xfffffeac - SH3_UPPER_REGBASE)/4)
-#define SH3_TCNT2_ADDR ((0xfffffeb0 - SH3_UPPER_REGBASE)/4)
-#define SH3_TCR2_ADDR ((0xfffffeb4 - SH3_UPPER_REGBASE)/4)
-#define SH3_TCPR2_ADDR ((0xfffffeb8 - SH3_UPPER_REGBASE)/4)
-#define SH3_TRA_ADDR ((0xffffffd0 - SH3_UPPER_REGBASE)/4)
-#define SH3_EXPEVT_ADDR ((0xffffffd4 - SH3_UPPER_REGBASE)/4)
-#define SH3_INTEVT_ADDR ((0xffffffd8 - SH3_UPPER_REGBASE)/4)
-
#endif // MAME_CPU_SH_SH3COMN_H
diff --git a/src/devices/cpu/sh/sh4.cpp b/src/devices/cpu/sh/sh4.cpp
index 0e83680dc64..6e73b69a531 100644
--- a/src/devices/cpu/sh/sh4.cpp
+++ b/src/devices/cpu/sh/sh4.cpp
@@ -34,10 +34,17 @@
#include "cpu/drcumlsh.h"
-DEFINE_DEVICE_TYPE(SH3LE, sh3_device, "sh3le", "Hitachi SH-3 (little)")
-DEFINE_DEVICE_TYPE(SH3BE, sh3be_device, "sh3be", "Hitachi SH-3 (big)")
-DEFINE_DEVICE_TYPE(SH4LE, sh4_device, "sh4le", "Hitachi SH-4 (little)")
-DEFINE_DEVICE_TYPE(SH4BE, sh4be_device, "sh4be", "Hitachi SH-4 (big)")
+DEFINE_DEVICE_TYPE(SH3, sh3_device, "sh3", "Hitachi SH-3 (Unidentified)")
+DEFINE_DEVICE_TYPE(SH7708S, sh7708s_device, "sh7708s", "Hitachi SH7708S")
+DEFINE_DEVICE_TYPE(SH7709, sh7709_device, "sh7709", "Hitachi SH7709")
+DEFINE_DEVICE_TYPE(SH7709S, sh7709s_device, "sh7709s", "Hitachi SH7709S")
+DEFINE_DEVICE_TYPE(SH4, sh4_device, "sh4", "Hitachi SH-4 (Unidentified)")
+DEFINE_DEVICE_TYPE(SH7091, sh7091_device, "sh7091", "Hitachi SH7091")
+DEFINE_DEVICE_TYPE(SH7750, sh7750_device, "sh7750", "Hitachi SH7750")
+DEFINE_DEVICE_TYPE(SH7750R, sh7750r_device, "sh7750r", "Hitachi SH7750R")
+DEFINE_DEVICE_TYPE(SH7750S, sh7750s_device, "sh7750s", "Hitachi SH7750S")
+DEFINE_DEVICE_TYPE(SH7751, sh7751_device, "sh7751", "Hitachi SH7751")
+DEFINE_DEVICE_TYPE(SH7751R, sh7751r_device, "sh7751r", "Hitachi SH7751R")
#if 0
@@ -47,6 +54,8 @@ void sh4_base_device::sh4_internal_map(address_map &map)
map(0x1C000000, 0x1C000FFF).ram().mirror(0x03FFD000);
map(0x1C002000, 0x1C002FFF).ram().mirror(0x03FFD000);
map(0xE0000000, 0xE000003F).ram().mirror(0x03FFFFC0);
+
+ sh4_register_map(map);
}
#endif
@@ -61,15 +70,819 @@ void sh4_base_device::sh4_internal_map(address_map &map)
map(0xF7000000, 0xF77FFFFF).rw(FUNC(sh4_base_device::sh4_utlb_data_array1_r), FUNC(sh4_base_device::sh4_utlb_data_array1_w));
map(0xF7800000, 0xF7FFFFFF).rw(FUNC(sh4_base_device::sh4_utlb_data_array2_r), FUNC(sh4_base_device::sh4_utlb_data_array2_w));
- map(0xFE000000, 0xFFFFFFFF).rw(FUNC(sh4_base_device::sh4_internal_r), FUNC(sh4_base_device::sh4_internal_w)).umask32(0xffffffff);
+ sh4_register_map(map);
+}
+
+void sh4_device::sh4_register_map(address_map &map)
+{
+ map(0xff000030, 0xff000033).lr32([] { return PVR_SH7751; }, "pvr_r");
+
+ ccn_map(map);
+ ubc_map(map);
+ bsc_map(map);
+ dmac_map(map);
+ cpg_7750r_map(map);
+ rtc_map(map);
+ intc_7750r_map(map);
+ tmu_7750r_map(map);
+ sci_map(map);
+ scif_map(map);
+ hudi_7750r_map(map);
+ pci_7751_map(map);
+}
+
+void sh7091_device::sh4_register_map(address_map& map)
+{
+ map(0xff000030, 0xff000033).lr32([] { return PVR_SH7091; }, "pvr_r");
+
+ ccn_map(map);
+ ubc_map(map);
+ bsc_map(map);
+ dmac_map(map);
+ cpg_map(map);
+ rtc_map(map);
+ intc_map(map);
+ tmu_map(map);
+ sci_map(map);
+ scif_map(map);
+ hudi_map(map);
+}
+
+void sh7750_device::sh4_register_map(address_map& map)
+{
+ map(0xff000030, 0xff000033).lr32([] { return PVR_SH7750; }, "pvr_r");
+
+ ccn_map(map);
+ ubc_map(map);
+ bsc_map(map);
+ dmac_map(map);
+ cpg_map(map);
+ rtc_map(map);
+ intc_map(map);
+ tmu_map(map);
+ sci_map(map);
+ scif_map(map);
+ hudi_map(map);
+}
+
+void sh7750s_device::sh4_register_map(address_map& map)
+{
+ map(0xff000030, 0xff000033).lr32([] { return PVR_SH7750S; }, "pvr_r");
+
+ ccn_map(map);
+ ubc_map(map);
+ bsc_map(map);
+ dmac_map(map);
+ cpg_map(map);
+ rtc_map(map);
+ intc_7750s_map(map);
+ tmu_map(map);
+ sci_map(map);
+ scif_map(map);
+ hudi_map(map);
+}
+
+void sh7750r_device::sh4_register_map(address_map& map)
+{
+ map(0xff000030, 0xff000033).lr32([] { return PVR_SH7750R; }, "pvr_r");
+ map(0xff000044, 0xff000047).lr32([] { return PRR_SH7750R; }, "prr_r");
+
+ ccn_map(map);
+ ubc_map(map);
+ bsc_7750r_map(map);
+ dmac_7750r_map(map);
+ cpg_7750r_map(map);
+ rtc_7750r_map(map);
+ intc_7750r_map(map);
+ tmu_7750r_map(map);
+ sci_map(map);
+ scif_map(map);
+ hudi_7750r_map(map);
+}
+
+void sh7751_device::sh4_register_map(address_map& map)
+{
+ map(0xff000030, 0xff000033).lr32([] { return PVR_SH7751; }, "pvr_r");
+
+ ccn_map(map);
+ ubc_map(map);
+ bsc_map(map);
+ dmac_map(map);
+ cpg_7750r_map(map);
+ rtc_map(map);
+ intc_7750r_map(map);
+ tmu_7750r_map(map);
+ sci_map(map);
+ scif_map(map);
+ hudi_7750r_map(map);
+ pci_7751_map(map);
+}
+
+void sh7751r_device::sh4_register_map(address_map& map)
+{
+ map(0xff000030, 0xff000033).lr32([] { return PVR_SH7751R; }, "pvr_r");
+ map(0xff000044, 0xff000047).lr32([] { return PRR_SH7751R; }, "prr_r");
+
+ ccn_map(map);
+ ubc_map(map);
+ bsc_7750r_map(map);
+ dmac_7750r_map(map);
+ cpg_7750r_map(map);
+ rtc_7750r_map(map);
+ intc_7750r_map(map);
+ tmu_7750r_map(map);
+ sci_map(map);
+ scif_map(map);
+ hudi_7750r_map(map);
+ pci_7751_map(map);
+}
+
+void sh4_base_device::ccn_map(address_map &map)
+{
+ map(0xff000000, 0xff000003).rw(FUNC(sh4_base_device::pteh_r), FUNC(sh4_base_device::pteh_w));
+ map(0xff000004, 0xff000007).rw(FUNC(sh4_base_device::ptel_r), FUNC(sh4_base_device::ptel_w));
+ map(0xff000008, 0xff00000b).rw(FUNC(sh4_base_device::ttb_r), FUNC(sh4_base_device::ttb_w));
+ map(0xff00000c, 0xff00000f).rw(FUNC(sh4_base_device::tea_r), FUNC(sh4_base_device::tea_w));
+ map(0xff000010, 0xff000013).rw(FUNC(sh4_base_device::mmucr_r), FUNC(sh4_base_device::mmucr_w));
+ map(0xff000014, 0xff000014).rw(FUNC(sh4_base_device::basra_r), FUNC(sh4_base_device::basra_w));
+ map(0xff000018, 0xff000018).rw(FUNC(sh4_base_device::basrb_r), FUNC(sh4_base_device::basrb_w));
+ map(0xff00001c, 0xff00001f).rw(FUNC(sh4_base_device::ccr_r), FUNC(sh4_base_device::ccr_w));
+ map(0xff000020, 0xff000023).rw(FUNC(sh4_base_device::tra_r), FUNC(sh4_base_device::tra_w));
+ map(0xff000024, 0xff000027).rw(FUNC(sh4_base_device::expevt_r), FUNC(sh4_base_device::expevt_w));
+ map(0xff000028, 0xff00002b).rw(FUNC(sh4_base_device::intevt_r), FUNC(sh4_base_device::intevt_w));
+ map(0xff000034, 0xff000037).rw(FUNC(sh4_base_device::ptea_r), FUNC(sh4_base_device::ptea_w));
+ map(0xff000038, 0xff00003b).rw(FUNC(sh4_base_device::qacr0_r), FUNC(sh4_base_device::qacr0_w));
+ map(0xff00003c, 0xff00003f).rw(FUNC(sh4_base_device::qacr1_r), FUNC(sh4_base_device::qacr1_w));
+}
+
+void sh4_base_device::ubc_map(address_map &map)
+{
+ map(0xff200000, 0xff200003).rw(FUNC(sh4_base_device::bara_r), FUNC(sh4_base_device::bara_w));
+ map(0xff200004, 0xff200004).rw(FUNC(sh4_base_device::bamra_r), FUNC(sh4_base_device::bamra_w));
+ map(0xff200008, 0xff200009).rw(FUNC(sh4_base_device::bbra_r), FUNC(sh4_base_device::bbra_w));
+ map(0xff20000c, 0xff20000f).rw(FUNC(sh4_base_device::barb_r), FUNC(sh4_base_device::barb_w));
+ map(0xff200010, 0xff200010).rw(FUNC(sh4_base_device::bamrb_r), FUNC(sh4_base_device::bamrb_w));
+ map(0xff200014, 0xff200015).rw(FUNC(sh4_base_device::bbrb_r), FUNC(sh4_base_device::bbrb_w));
+ map(0xff200018, 0xff20001b).rw(FUNC(sh4_base_device::bdrb_r), FUNC(sh4_base_device::bdrb_w));
+ map(0xff20001c, 0xff20001f).rw(FUNC(sh4_base_device::bdmrb_r), FUNC(sh4_base_device::bdmrb_w));
+ map(0xff200020, 0xff200021).rw(FUNC(sh4_base_device::brcr_r), FUNC(sh4_base_device::brcr_w));
+}
+
+void sh4_base_device::bsc_map(address_map& map)
+{
+ map(0xff800000, 0xff800003).rw(FUNC(sh4_base_device::bcr1_r), FUNC(sh4_base_device::bcr1_w));
+ map(0xff800004, 0xff800005).rw(FUNC(sh4_base_device::bcr2_r), FUNC(sh4_base_device::bcr2_w));
+ map(0xff800008, 0xff80000b).rw(FUNC(sh4_base_device::wcr1_r), FUNC(sh4_base_device::wcr1_w));
+ map(0xff80000c, 0xff80000f).rw(FUNC(sh4_base_device::wcr2_r), FUNC(sh4_base_device::wcr2_w));
+ map(0xff800010, 0xff800013).rw(FUNC(sh4_base_device::wcr3_r), FUNC(sh4_base_device::wcr3_w));
+ map(0xff800014, 0xff800017).rw(FUNC(sh4_base_device::mcr_r), FUNC(sh4_base_device::mcr_w));
+ map(0xff800018, 0xff800019).rw(FUNC(sh4_base_device::pcr_r), FUNC(sh4_base_device::pcr_w));
+ map(0xff80001c, 0xff80001d).rw(FUNC(sh4_base_device::rtcsr_r), FUNC(sh4_base_device::rtcsr_w));
+ map(0xff800020, 0xff800021).rw(FUNC(sh4_base_device::rtcnt_r), FUNC(sh4_base_device::rtcnt_w));
+ map(0xff800024, 0xff800025).rw(FUNC(sh4_base_device::rtcor_r), FUNC(sh4_base_device::rtcor_w));
+ map(0xff800028, 0xff800029).rw(FUNC(sh4_base_device::rfcr_r), FUNC(sh4_base_device::rfcr_w));
+ map(0xff80002c, 0xff80002f).rw(FUNC(sh4_base_device::pctra_r), FUNC(sh4_base_device::pctra_w));
+ map(0xff800030, 0xff800031).rw(FUNC(sh4_base_device::pdtra_r), FUNC(sh4_base_device::pdtra_w));
+ map(0xff800040, 0xff800043).rw(FUNC(sh4_base_device::pctrb_r), FUNC(sh4_base_device::pctrb_w));
+ map(0xff800044, 0xff800045).rw(FUNC(sh4_base_device::pdtrb_r), FUNC(sh4_base_device::pdtrb_w));
+ map(0xff800048, 0xff800049).rw(FUNC(sh4_base_device::gpioic_r), FUNC(sh4_base_device::gpioic_w));
+ map(0xff900000, 0xff90ffff).w(FUNC(sh4_base_device::sdmr2_w));
+ map(0xff940000, 0xff94ffff).w(FUNC(sh4_base_device::sdmr3_w));
+}
+
+void sh4_base_device::bsc_7750r_map(address_map& map)
+{
+ bsc_map(map);
+
+ map(0xff800050, 0xff800051).rw(FUNC(sh4_base_device::bcr3_r), FUNC(sh4_base_device::bcr3_w));
+ map(0xfe0a00f0, 0xfe0a00f3).rw(FUNC(sh4_base_device::bcr4_r), FUNC(sh4_base_device::bcr4_w));
+}
+
+void sh4_base_device::dmac_map(address_map& map)
+{
+ map(0xffa00000, 0xffa00003).rw(FUNC(sh4_base_device::sar0_r), FUNC(sh4_base_device::sar0_w));
+ map(0xffa00004, 0xffa00007).rw(FUNC(sh4_base_device::dar0_r), FUNC(sh4_base_device::dar0_w));
+ map(0xffa00008, 0xffa0000b).rw(FUNC(sh4_base_device::dmatcr0_r), FUNC(sh4_base_device::dmatcr0_w));
+ map(0xffa0000c, 0xffa0000f).rw(FUNC(sh4_base_device::chcr0_r), FUNC(sh4_base_device::chcr0_w));
+ map(0xffa00010, 0xffa00013).rw(FUNC(sh4_base_device::sar1_r), FUNC(sh4_base_device::sar1_w));
+ map(0xffa00014, 0xffa00017).rw(FUNC(sh4_base_device::dar1_r), FUNC(sh4_base_device::dar1_w));
+ map(0xffa00018, 0xffa0001b).rw(FUNC(sh4_base_device::dmatcr1_r), FUNC(sh4_base_device::dmatcr1_w));
+ map(0xffa0001c, 0xffa0001f).rw(FUNC(sh4_base_device::chcr1_r), FUNC(sh4_base_device::chcr1_w));
+ map(0xffa00020, 0xffa00023).rw(FUNC(sh4_base_device::sar2_r), FUNC(sh4_base_device::sar2_w));
+ map(0xffa00024, 0xffa00027).rw(FUNC(sh4_base_device::dar2_r), FUNC(sh4_base_device::dar2_w));
+ map(0xffa00028, 0xffa0002b).rw(FUNC(sh4_base_device::dmatcr2_r), FUNC(sh4_base_device::dmatcr2_w));
+ map(0xffa0002c, 0xffa0002f).rw(FUNC(sh4_base_device::chcr2_r), FUNC(sh4_base_device::chcr2_w));
+ map(0xffa00030, 0xffa00033).rw(FUNC(sh4_base_device::sar3_r), FUNC(sh4_base_device::sar3_w));
+ map(0xffa00034, 0xffa00037).rw(FUNC(sh4_base_device::dar3_r), FUNC(sh4_base_device::dar3_w));
+ map(0xffa00038, 0xffa0003b).rw(FUNC(sh4_base_device::dmatcr3_r), FUNC(sh4_base_device::dmatcr3_w));
+ map(0xffa0003c, 0xffa0003f).rw(FUNC(sh4_base_device::chcr3_r), FUNC(sh4_base_device::chcr3_w));
+ map(0xffa00040, 0xffa00043).rw(FUNC(sh4_base_device::dmaor_r), FUNC(sh4_base_device::dmaor_w));
+}
+
+void sh4_base_device::dmac_7750r_map(address_map& map)
+{
+ dmac_map(map);
+
+ map(0xffa00050, 0xffa00053).rw(FUNC(sh4_base_device::sar4_r), FUNC(sh4_base_device::sar4_w));
+ map(0xffa00054, 0xffa00057).rw(FUNC(sh4_base_device::dar4_r), FUNC(sh4_base_device::dar4_w));
+ map(0xffa00058, 0xffa0005b).rw(FUNC(sh4_base_device::dmatcr4_r), FUNC(sh4_base_device::dmatcr4_w));
+ map(0xffa0005c, 0xffa0005f).rw(FUNC(sh4_base_device::chcr4_r), FUNC(sh4_base_device::chcr4_w));
+ map(0xffa00060, 0xffa00063).rw(FUNC(sh4_base_device::sar5_r), FUNC(sh4_base_device::sar5_w));
+ map(0xffa00064, 0xffa00067).rw(FUNC(sh4_base_device::dar5_r), FUNC(sh4_base_device::dar5_w));
+ map(0xffa00068, 0xffa0006b).rw(FUNC(sh4_base_device::dmatcr5_r), FUNC(sh4_base_device::dmatcr5_w));
+ map(0xffa0006c, 0xffa0006f).rw(FUNC(sh4_base_device::chcr5_r), FUNC(sh4_base_device::chcr5_w));
+ map(0xffa00070, 0xffa00073).rw(FUNC(sh4_base_device::sar6_r), FUNC(sh4_base_device::sar6_w));
+ map(0xffa00074, 0xffa00077).rw(FUNC(sh4_base_device::dar6_r), FUNC(sh4_base_device::dar6_w));
+ map(0xffa00078, 0xffa0007b).rw(FUNC(sh4_base_device::dmatcr6_r), FUNC(sh4_base_device::dmatcr6_w));
+ map(0xffa0007c, 0xffa0007f).rw(FUNC(sh4_base_device::chcr6_r), FUNC(sh4_base_device::chcr6_w));
+ map(0xffa00080, 0xffa00083).rw(FUNC(sh4_base_device::sar7_r), FUNC(sh4_base_device::sar7_w));
+ map(0xffa00084, 0xffa00087).rw(FUNC(sh4_base_device::dar7_r), FUNC(sh4_base_device::dar7_w));
+ map(0xffa00088, 0xffa0008b).rw(FUNC(sh4_base_device::dmatcr7_r), FUNC(sh4_base_device::dmatcr7_w));
+ map(0xffa0008c, 0xffa0008f).rw(FUNC(sh4_base_device::chcr7_r), FUNC(sh4_base_device::chcr7_w));
+}
+
+void sh4_base_device::cpg_map(address_map& map)
+{
+ map(0xffc00000, 0xffc00001).rw(FUNC(sh4_base_device::frqcr_r), FUNC(sh4_base_device::frqcr_w));
+ map(0xffc00004, 0xffc00004).rw(FUNC(sh4_base_device::stbcr_r), FUNC(sh4_base_device::stbcr_w));
+ map(0xffc00008, 0xffc00008).r(FUNC(sh4_base_device::wtcnt_r));
+ map(0xffc00008, 0xffc00009).w(FUNC(sh4_base_device::wtcnt_w));
+ map(0xffc0000c, 0xffc0000c).r(FUNC(sh4_base_device::wtcsr_r));
+ map(0xffc0000c, 0xffc0000d).w(FUNC(sh4_base_device::wtcsr_w));
+ map(0xffc00010, 0xffc00010).rw(FUNC(sh4_base_device::stbcr2_r), FUNC(sh4_base_device::stbcr2_w));
+}
+
+void sh4_base_device::cpg_7750r_map(address_map& map)
+{
+ cpg_map(map);
+
+ map(0xfe0a0000, 0xfe0a0003).rw(FUNC(sh4_base_device::clkstp00_r), FUNC(sh4_base_device::clkstp00_w));
+ map(0xfe0a0008, 0xfe0a000b).w(FUNC(sh4_base_device::clkstpclr_w));
+}
+
+void sh4_base_device::rtc_map(address_map& map)
+{
+ map(0xffc80000, 0xffc80000).r(FUNC(sh4_base_device::r64cnt_r));
+ map(0xffc80004, 0xffc80004).rw(FUNC(sh4_base_device::rseccnt_r), FUNC(sh4_base_device::rseccnt_w));
+ map(0xffc80008, 0xffc80008).rw(FUNC(sh4_base_device::rmincnt_r), FUNC(sh4_base_device::rmincnt_w));
+ map(0xffc8000c, 0xffc8000c).rw(FUNC(sh4_base_device::rhrcnt_r), FUNC(sh4_base_device::rhrcnt_w));
+ map(0xffc80010, 0xffc80010).rw(FUNC(sh4_base_device::rwkcnt_r), FUNC(sh4_base_device::rwkcnt_w));
+ map(0xffc80014, 0xffc80014).rw(FUNC(sh4_base_device::rdaycnt_r), FUNC(sh4_base_device::rdaycnt_w));
+ map(0xffc80018, 0xffc80018).rw(FUNC(sh4_base_device::rmoncnt_r), FUNC(sh4_base_device::rmoncnt_w));
+ map(0xffc8001c, 0xffc8001d).rw(FUNC(sh4_base_device::ryrcnt_r), FUNC(sh4_base_device::ryrcnt_w));
+ map(0xffc80020, 0xffc80020).rw(FUNC(sh4_base_device::rsecar_r), FUNC(sh4_base_device::rsecar_w));
+ map(0xffc80024, 0xffc80024).rw(FUNC(sh4_base_device::rminar_r), FUNC(sh4_base_device::rminar_w));
+ map(0xffc80028, 0xffc80028).rw(FUNC(sh4_base_device::rhrar_r), FUNC(sh4_base_device::rhrar_w));
+ map(0xffc8002c, 0xffc8002c).rw(FUNC(sh4_base_device::rwkar_r), FUNC(sh4_base_device::rwkar_w));
+ map(0xffc80030, 0xffc80030).rw(FUNC(sh4_base_device::rdayar_r), FUNC(sh4_base_device::rdayar_w));
+ map(0xffc80034, 0xffc80034).rw(FUNC(sh4_base_device::rmonar_r), FUNC(sh4_base_device::rmonar_w));
+ map(0xffc80038, 0xffc80038).rw(FUNC(sh4_base_device::rcr1_r), FUNC(sh4_base_device::rcr1_w));
+ map(0xffc8003c, 0xffc8003c).rw(FUNC(sh4_base_device::rcr2_r), FUNC(sh4_base_device::rcr2_w));
+}
+
+void sh4_base_device::rtc_7750r_map(address_map& map)
+{
+ rtc_map(map);
+
+ map(0xffc80050, 0xffc80050).rw(FUNC(sh4_base_device::rcr3_r), FUNC(sh4_base_device::rcr3_w));
+ map(0xffc80054, 0xffc80055).rw(FUNC(sh4_base_device::ryrar_r), FUNC(sh4_base_device::ryrar_w));
+}
+
+void sh4_base_device::intc_map(address_map& map)
+{
+ map(0xffd00000, 0xffd00001).rw(FUNC(sh4_base_device::icr_r), FUNC(sh4_base_device::icr_w));
+ map(0xffd00004, 0xffd00005).rw(FUNC(sh4_base_device::ipra_r), FUNC(sh4_base_device::ipra_w));
+ map(0xffd00008, 0xffd00009).rw(FUNC(sh4_base_device::iprb_r), FUNC(sh4_base_device::iprb_w));
+ map(0xffd0000c, 0xffd0000d).rw(FUNC(sh4_base_device::iprc_r), FUNC(sh4_base_device::iprc_w));
+}
+
+void sh4_base_device::intc_7750s_map(address_map& map)
+{
+ intc_map(map);
+
+ map(0xffd00010, 0xffd00011).rw(FUNC(sh4_base_device::iprd_r), FUNC(sh4_base_device::iprd_w));
+}
+
+void sh4_base_device::intc_7750r_map(address_map& map)
+{
+ intc_7750s_map(map);
+
+ map(0xfe080000, 0xfe080003).rw(FUNC(sh4_base_device::intpri00_r), FUNC(sh4_base_device::intpri00_w));
+ map(0xfe080020, 0xfe080023).rw(FUNC(sh4_base_device::intreq00_r), FUNC(sh4_base_device::intreq00_w));
+ map(0xfe080040, 0xfe080043).rw(FUNC(sh4_base_device::intmsk00_r), FUNC(sh4_base_device::intmskclr_w));
+ map(0xfe080060, 0xfe080063).w(FUNC(sh4_base_device::intmsk00_w));
+}
+
+void sh4_base_device::tmu_map(address_map& map)
+{
+ map(0xffd80000, 0xffd80000).rw(FUNC(sh4_base_device::tocr_r), FUNC(sh4_base_device::tocr_w));
+ map(0xffd80004, 0xffd80004).rw(FUNC(sh4_base_device::tstr_r), FUNC(sh4_base_device::tstr_w));
+ map(0xffd80008, 0xffd8000b).rw(FUNC(sh4_base_device::tcor0_r), FUNC(sh4_base_device::tcor0_w));
+ map(0xffd8000c, 0xffd8000f).rw(FUNC(sh4_base_device::tcnt0_r), FUNC(sh4_base_device::tcnt0_w));
+ map(0xffd80010, 0xffd80011).rw(FUNC(sh4_base_device::tcr0_r), FUNC(sh4_base_device::tcr0_w));
+ map(0xffd80014, 0xffd80017).rw(FUNC(sh4_base_device::tcor1_r), FUNC(sh4_base_device::tcor1_w));
+ map(0xffd80018, 0xffd8001b).rw(FUNC(sh4_base_device::tcnt1_r), FUNC(sh4_base_device::tcnt1_w));
+ map(0xffd8001c, 0xffd8001d).rw(FUNC(sh4_base_device::tcr1_r), FUNC(sh4_base_device::tcr1_w));
+ map(0xffd80020, 0xffd80023).rw(FUNC(sh4_base_device::tcor2_r), FUNC(sh4_base_device::tcor2_w));
+ map(0xffd80024, 0xffd80027).rw(FUNC(sh4_base_device::tcnt2_r), FUNC(sh4_base_device::tcnt2_w));
+ map(0xffd80028, 0xffd80029).rw(FUNC(sh4_base_device::tcr2_r), FUNC(sh4_base_device::tcr2_w));
+ map(0xffd8002c, 0xffd8002f).rw(FUNC(sh4_base_device::tcpr2_r), FUNC(sh4_base_device::tcpr2_w));
+}
+
+void sh4_base_device::tmu_7750r_map(address_map& map)
+{
+ tmu_map(map);
+
+ map(0xfe100004, 0xfe100004).rw(FUNC(sh4_base_device::tstr2_r), FUNC(sh4_base_device::tstr2_w));
+ map(0xfe100008, 0xfe10000b).rw(FUNC(sh4_base_device::tcor3_r), FUNC(sh4_base_device::tcor3_w));
+ map(0xfe10000c, 0xfe10000f).rw(FUNC(sh4_base_device::tcnt3_r), FUNC(sh4_base_device::tcnt3_w));
+ map(0xfe100010, 0xfe100011).rw(FUNC(sh4_base_device::tcr3_r), FUNC(sh4_base_device::tcr3_w));
+ map(0xfe100014, 0xfe100017).rw(FUNC(sh4_base_device::tcor4_r), FUNC(sh4_base_device::tcor4_w));
+ map(0xfe100018, 0xfe10001b).rw(FUNC(sh4_base_device::tcnt4_r), FUNC(sh4_base_device::tcnt4_w));
+ map(0xfe10001c, 0xfe10001d).rw(FUNC(sh4_base_device::tcr4_r), FUNC(sh4_base_device::tcr4_w));
+}
+
+void sh4_base_device::sci_map(address_map& map)
+{
+ map(0xffe00000, 0xffe00000).rw(FUNC(sh4_base_device::scsmr1_r), FUNC(sh4_base_device::scsmr1_w));
+ map(0xffe00004, 0xffe00004).rw(FUNC(sh4_base_device::scbrr1_r), FUNC(sh4_base_device::scbrr1_w));
+ map(0xffe00008, 0xffe00008).rw(FUNC(sh4_base_device::scscr1_r), FUNC(sh4_base_device::scscr1_w));
+ map(0xffe0000c, 0xffe0000c).rw(FUNC(sh4_base_device::sctdr1_r), FUNC(sh4_base_device::sctdr1_w));
+ map(0xffe00010, 0xffe00010).rw(FUNC(sh4_base_device::scssr1_r), FUNC(sh4_base_device::scssr1_w));
+ map(0xffe00014, 0xffe00014).r(FUNC(sh4_base_device::scrdr1_r));
+ map(0xffe00018, 0xffe00018).rw(FUNC(sh4_base_device::scscmr1_r), FUNC(sh4_base_device::scscmr1_w));
+ map(0xffe0001c, 0xffe0001c).rw(FUNC(sh4_base_device::scsptr1_r), FUNC(sh4_base_device::scsptr1_w));
+}
+
+void sh4_base_device::scif_map(address_map& map)
+{
+ map(0xffe80000, 0xffe80001).rw(FUNC(sh4_base_device::scsmr2_r), FUNC(sh4_base_device::scsmr2_w));
+ map(0xffe80004, 0xffe80004).rw(FUNC(sh4_base_device::scbrr2_r), FUNC(sh4_base_device::scbrr2_w));
+ map(0xffe80008, 0xffe80009).rw(FUNC(sh4_base_device::scscr2_r), FUNC(sh4_base_device::scscr2_w));
+ map(0xffe8000c, 0xffe8000c).rw(FUNC(sh4_base_device::scftdr2_r), FUNC(sh4_base_device::scftdr2_w));
+ map(0xffe80010, 0xffe80011).rw(FUNC(sh4_base_device::scfsr2_r), FUNC(sh4_base_device::scfsr2_w));
+ map(0xffe80014, 0xffe80014).r(FUNC(sh4_base_device::scfrdr2_r));
+ map(0xffe80018, 0xffe80019).rw(FUNC(sh4_base_device::scfcr2_r), FUNC(sh4_base_device::scfcr2_w));
+ map(0xffe8001c, 0xffe8001d).r(FUNC(sh4_base_device::scfdr2_r));
+ map(0xffe80020, 0xffe80021).rw(FUNC(sh4_base_device::scsptr2_r), FUNC(sh4_base_device::scsptr2_w));
+ map(0xffe80024, 0xffe80025).rw(FUNC(sh4_base_device::sclsr2_r), FUNC(sh4_base_device::sclsr2_w));
+}
+
+void sh4_base_device::hudi_map(address_map &map)
+{
+ map(0xfff00000, 0xfff00001).rw(FUNC(sh4_base_device::sdir_r), FUNC(sh4_base_device::sdir_w));
+ map(0xfff00008, 0xfff0000b).rw(FUNC(sh4_base_device::sddr_r), FUNC(sh4_base_device::sddr_w));
+}
+
+void sh4_base_device::hudi_7750r_map(address_map& map)
+{
+ hudi_map(map);
+
+ map(0xfff00014, 0xfff00015).rw(FUNC(sh4_base_device::sdint_r), FUNC(sh4_base_device::sdint_w));
+}
+
+void sh4_base_device::pci_7751_map(address_map& map)
+{
+ // PCI
+ // 0xfd000000, 0xfdffffff PCIMEM
+
+ // PCIC
+ map(0xfe200000, 0xfe200003).r(FUNC(sh4_base_device::pciconf0_r));
+ map(0xfe200004, 0xfe200007).rw(FUNC(sh4_base_device::pciconf1_r), FUNC(sh4_base_device::pciconf1_w));
+ map(0xfe200008, 0xfe20000b).rw(FUNC(sh4_base_device::pciconf2_r), FUNC(sh4_base_device::pciconf2_w));
+ map(0xfe20000c, 0xfe20000f).rw(FUNC(sh4_base_device::pciconf3_r), FUNC(sh4_base_device::pciconf3_w));
+ map(0xfe200010, 0xfe200013).rw(FUNC(sh4_base_device::pciconf4_r), FUNC(sh4_base_device::pciconf4_w));
+ map(0xfe200014, 0xfe200017).rw(FUNC(sh4_base_device::pciconf5_r), FUNC(sh4_base_device::pciconf5_w));
+ map(0xfe200018, 0xfe20001b).rw(FUNC(sh4_base_device::pciconf6_r), FUNC(sh4_base_device::pciconf6_w));
+ map(0xfe20001c, 0xfe20001f).r(FUNC(sh4_base_device::pciconf7_r));
+ map(0xfe200020, 0xfe200023).r(FUNC(sh4_base_device::pciconf8_r));
+ map(0xfe200024, 0xfe200027).r(FUNC(sh4_base_device::pciconf9_r));
+ map(0xfe200028, 0xfe20002b).r(FUNC(sh4_base_device::pciconf10_r));
+ map(0xfe20002c, 0xfe20002f).rw(FUNC(sh4_base_device::pciconf11_r), FUNC(sh4_base_device::pciconf11_w));
+ map(0xfe200030, 0xfe200033).r(FUNC(sh4_base_device::pciconf12_r));
+ map(0xfe200034, 0xfe200037).r(FUNC(sh4_base_device::pciconf13_r));
+ map(0xfe200038, 0xfe20003b).r(FUNC(sh4_base_device::pciconf14_r));
+ map(0xfe20003c, 0xfe20003f).rw(FUNC(sh4_base_device::pciconf15_r), FUNC(sh4_base_device::pciconf15_w));
+ map(0xfe200040, 0xfe200043).rw(FUNC(sh4_base_device::pciconf16_r), FUNC(sh4_base_device::pciconf16_w));
+ map(0xfe200044, 0xfe200047).rw(FUNC(sh4_base_device::pciconf17_r), FUNC(sh4_base_device::pciconf17_w));
+ map(0xfe200100, 0xfe200103).rw(FUNC(sh4_base_device::pcicr_r), FUNC(sh4_base_device::pcicr_w));
+ map(0xfe200104, 0xfe200107).rw(FUNC(sh4_base_device::pcilsr0_r), FUNC(sh4_base_device::pcilsr0_w));
+ map(0xfe200108, 0xfe20010b).rw(FUNC(sh4_base_device::pcilsr1_r), FUNC(sh4_base_device::pcilsr1_w));
+ map(0xfe20010c, 0xfe20010f).rw(FUNC(sh4_base_device::pcilar0_r), FUNC(sh4_base_device::pcilar0_w));
+ map(0xfe200110, 0xfe200113).rw(FUNC(sh4_base_device::pcilar1_r), FUNC(sh4_base_device::pcilar1_w));
+ map(0xfe200114, 0xfe200117).rw(FUNC(sh4_base_device::pciint_r), FUNC(sh4_base_device::pciint_w));
+ map(0xfe200118, 0xfe20011b).rw(FUNC(sh4_base_device::pciintm_r), FUNC(sh4_base_device::pciintm_w));
+ map(0xfe20011c, 0xfe20011f).rw(FUNC(sh4_base_device::pcialr_r), FUNC(sh4_base_device::pcialr_w));
+ map(0xfe200120, 0xfe200123).rw(FUNC(sh4_base_device::pciclr_r), FUNC(sh4_base_device::pciclr_w));
+ map(0xfe200130, 0xfe200133).rw(FUNC(sh4_base_device::pciaint_r), FUNC(sh4_base_device::pciaint_w));
+ map(0xfe200134, 0xfe200137).rw(FUNC(sh4_base_device::pciaintm_r), FUNC(sh4_base_device::pciaintm_w));
+ map(0xfe200138, 0xfe20013b).rw(FUNC(sh4_base_device::pcibllr_r), FUNC(sh4_base_device::pcibllr_w));
+ map(0xfe200140, 0xfe200143).rw(FUNC(sh4_base_device::pcidmabt_r), FUNC(sh4_base_device::pcidmabt_w));
+ map(0xfe200180, 0xfe200183).rw(FUNC(sh4_base_device::pcidpa0_r), FUNC(sh4_base_device::pcidpa0_w));
+ map(0xfe200184, 0xfe200187).rw(FUNC(sh4_base_device::pcidla0_r), FUNC(sh4_base_device::pcidla0_w));
+ map(0xfe200188, 0xfe20018b).rw(FUNC(sh4_base_device::pcidtc0_r), FUNC(sh4_base_device::pcidtc0_w));
+ map(0xfe20018c, 0xfe20018f).rw(FUNC(sh4_base_device::pcidcr0_r), FUNC(sh4_base_device::pcidcr0_w));
+ map(0xfe200190, 0xfe200193).rw(FUNC(sh4_base_device::pcidpa1_r), FUNC(sh4_base_device::pcidpa1_w));
+ map(0xfe200194, 0xfe200197).rw(FUNC(sh4_base_device::pcidla1_r), FUNC(sh4_base_device::pcidla1_w));
+ map(0xfe200198, 0xfe20019b).rw(FUNC(sh4_base_device::pcidtc1_r), FUNC(sh4_base_device::pcidtc1_w));
+ map(0xfe20019c, 0xfe20019f).rw(FUNC(sh4_base_device::pcidcr1_r), FUNC(sh4_base_device::pcidcr1_w));
+ map(0xfe2001a0, 0xfe2001a3).rw(FUNC(sh4_base_device::pcidpa2_r), FUNC(sh4_base_device::pcidpa2_w));
+ map(0xfe2001a4, 0xfe2001a7).rw(FUNC(sh4_base_device::pcidla2_r), FUNC(sh4_base_device::pcidla2_w));
+ map(0xfe2001a8, 0xfe2001ab).rw(FUNC(sh4_base_device::pcidtc2_r), FUNC(sh4_base_device::pcidtc2_w));
+ map(0xfe2001ac, 0xfe2001af).rw(FUNC(sh4_base_device::pcidcr2_r), FUNC(sh4_base_device::pcidcr2_w));
+ map(0xfe2001b0, 0xfe2001b3).rw(FUNC(sh4_base_device::pcidpa3_r), FUNC(sh4_base_device::pcidpa3_w));
+ map(0xfe2001b4, 0xfe2001b7).rw(FUNC(sh4_base_device::pcidla3_r), FUNC(sh4_base_device::pcidla3_w));
+ map(0xfe2001b8, 0xfe2001bb).rw(FUNC(sh4_base_device::pcidtc3_r), FUNC(sh4_base_device::pcidtc3_w));
+ map(0xfe2001bc, 0xfe2001bf).rw(FUNC(sh4_base_device::pcidcr3_r), FUNC(sh4_base_device::pcidcr3_w));
+ map(0xfe2001c0, 0xfe2001c3).rw(FUNC(sh4_base_device::pcipar_r), FUNC(sh4_base_device::pcipar_w));
+ map(0xfe2001c4, 0xfe2001c7).rw(FUNC(sh4_base_device::pcimbr_r), FUNC(sh4_base_device::pcimbr_w));
+ map(0xfe2001c8, 0xfe2001cb).rw(FUNC(sh4_base_device::pciiobr_r), FUNC(sh4_base_device::pciiobr_w));
+ map(0xfe2001cc, 0xfe2001cf).rw(FUNC(sh4_base_device::pcipint_r), FUNC(sh4_base_device::pcipint_w));
+ map(0xfe2001d0, 0xfe2001d3).rw(FUNC(sh4_base_device::pcipintm_r), FUNC(sh4_base_device::pcipintm_w));
+ map(0xfe2001d4, 0xfe2001d7).rw(FUNC(sh4_base_device::pciclkr_r), FUNC(sh4_base_device::pciclkr_w));
+ map(0xfe2001e0, 0xfe2001e3).rw(FUNC(sh4_base_device::pcibcr1_r), FUNC(sh4_base_device::pcibcr1_w));
+ map(0xfe2001e4, 0xfe2001e7).rw(FUNC(sh4_base_device::pcibcr2_r), FUNC(sh4_base_device::pcibcr2_w));
+ map(0xfe2001f8, 0xfe2001fb).rw(FUNC(sh4_base_device::pcibcr3_r), FUNC(sh4_base_device::pcibcr3_w));
+ map(0xfe2001e8, 0xfe2001eb).rw(FUNC(sh4_base_device::pciwcr1_r), FUNC(sh4_base_device::pciwcr1_w));
+ map(0xfe2001ec, 0xfe2001ef).rw(FUNC(sh4_base_device::pciwcr2_r), FUNC(sh4_base_device::pciwcr2_w));
+ map(0xfe2001f0, 0xfe2001f3).rw(FUNC(sh4_base_device::pciwcr3_r), FUNC(sh4_base_device::pciwcr3_w));
+ map(0xfe2001f4, 0xfe2001f7).rw(FUNC(sh4_base_device::pcimcr_r), FUNC(sh4_base_device::pcimcr_w));
+ map(0xfe200200, 0xfe200203).rw(FUNC(sh4_base_device::pcipctr_r), FUNC(sh4_base_device::pcipctr_w));
+ map(0xfe200204, 0xfe200207).rw(FUNC(sh4_base_device::pcipdtr_r), FUNC(sh4_base_device::pcipdtr_w));
+ map(0xfe200220, 0xfe200223).rw(FUNC(sh4_base_device::pcipdr_r), FUNC(sh4_base_device::pcipdr_w));
+
+ // PCIIO
+ // 0xfe240000, 0xfe27ffff
}
void sh3_base_device::sh3_internal_map(address_map &map)
{
- map(SH3_LOWER_REGBASE, SH3_LOWER_REGEND).rw(FUNC(sh3_base_device::sh3_internal_r), FUNC(sh3_base_device::sh3_internal_w));
- map(SH3_UPPER_REGBASE, SH3_UPPER_REGEND).rw(FUNC(sh3_base_device::sh3_internal_high_r), FUNC(sh3_base_device::sh3_internal_high_w));
+ sh3_register_map(map);
+}
+
+void sh3_device::sh3_register_map(address_map& map)
+{
+ ccn_7709s_map(map);
+ ubc_7709s_map(map);
+ cpg_7709_map(map);
+ bsc_7709s_map(map);
+ rtc_map(map);
+ intc_7709_map(map);
+ dmac_7709_map(map);
+ tmu_map(map);
+ sci_7709_map(map);
+ cmt_7709_map(map);
+ ad_7709_map(map);
+ da_7709_map(map);
+ port_7709_map(map);
+ irda_7709_map(map);
+ scif_7709_map(map);
+ udi_7709s_map(map);
}
+void sh7708s_device::sh3_register_map(address_map& map)
+{
+ ccn_map(map);
+ ubc_map(map);
+ cpg_map(map);
+ bsc_7708_map(map);
+ rtc_map(map);
+ intc_map(map);
+ tmu_map(map);
+ sci_7708_map(map);
+}
+
+void sh7709_device::sh3_register_map(address_map& map)
+{
+ ccn_map(map);
+ ubc_map(map);
+ cpg_7709_map(map);
+ bsc_7709_map(map);
+ rtc_map(map);
+ intc_7709_map(map);
+ dmac_7709_map(map);
+ tmu_map(map);
+ sci_7709_map(map);
+ cmt_7709_map(map);
+ ad_7709_map(map);
+ da_7709_map(map);
+ port_7709_map(map);
+ irda_7709_map(map);
+ scif_7709_map(map);
+}
+
+void sh7709s_device::sh3_register_map(address_map& map)
+{
+ ccn_7709s_map(map);
+ ubc_7709s_map(map);
+ cpg_7709_map(map);
+ bsc_7709s_map(map);
+ rtc_map(map);
+ intc_7709_map(map);
+ dmac_7709_map(map);
+ tmu_map(map);
+ sci_7709_map(map);
+ cmt_7709_map(map);
+ ad_7709_map(map);
+ da_7709_map(map);
+ port_7709_map(map);
+ irda_7709_map(map);
+ scif_7709_map(map);
+ udi_7709s_map(map);
+}
+
+void sh3_base_device::ccn_map(address_map& map)
+{
+ map(0xfffffff0, 0xfffffff3).rw(FUNC(sh3_base_device::pteh_r), FUNC(sh3_base_device::pteh_w));
+ map(0xfffffff4, 0xfffffff7).rw(FUNC(sh3_base_device::ptel_r), FUNC(sh3_base_device::ptel_w));
+ map(0xfffffff8, 0xfffffffb).rw(FUNC(sh3_base_device::ttb_r), FUNC(sh3_base_device::ttb_w));
+ map(0xfffffffc, 0xffffffff).rw(FUNC(sh3_base_device::tea_r), FUNC(sh3_base_device::tea_w));
+ map(0xffffffe0, 0xffffffe3).rw(FUNC(sh3_base_device::mmucr_r), FUNC(sh3_base_device::mmucr_w));
+ map(0xffffffe4, 0xffffffe4).rw(FUNC(sh3_base_device::basra_r), FUNC(sh3_base_device::basra_w));
+ map(0xffffffe8, 0xffffffe8).rw(FUNC(sh3_base_device::basrb_r), FUNC(sh3_base_device::basrb_w));
+ map(0xffffffec, 0xffffffef).rw(FUNC(sh3_base_device::ccr_r), FUNC(sh3_base_device::ccr_w));
+ map(0xffffffd0, 0xffffffd3).rw(FUNC(sh3_base_device::tra_r), FUNC(sh3_base_device::tra_w));
+ map(0xffffffd4, 0xffffffd7).rw(FUNC(sh3_base_device::expevt_r), FUNC(sh3_base_device::expevt_w));
+ map(0xffffffd8, 0xffffffdb).rw(FUNC(sh3_base_device::intevt_r), FUNC(sh3_base_device::intevt_w));
+}
+
+void sh3_base_device::ccn_7709s_map(address_map& map)
+{
+ ccn_map(map);
+
+ map(0x400000b0, 0x400000b3).rw(FUNC(sh3_base_device::ccr2_r), FUNC(sh3_base_device::ccr2_w));
+}
+
+void sh3_base_device::ubc_map(address_map& map)
+{
+ map(0xffffffb0, 0xffffffb3).rw(FUNC(sh3_base_device::bara_r), FUNC(sh3_base_device::bara_w));
+ map(0xffffffb4, 0xffffffb4).rw(FUNC(sh3_base_device::bamra_r), FUNC(sh3_base_device::bamra_w));
+ map(0xffffffb8, 0xffffffb9).rw(FUNC(sh3_base_device::bbra_r), FUNC(sh3_base_device::bbra_w));
+ map(0xffffffa0, 0xffffffa3).rw(FUNC(sh3_base_device::barb_r), FUNC(sh3_base_device::barb_w));
+ map(0xffffffa4, 0xffffffa4).rw(FUNC(sh3_base_device::bamrb_r), FUNC(sh3_base_device::bamrb_w));
+ map(0xffffffa8, 0xffffffa9).rw(FUNC(sh3_base_device::bbrb_r), FUNC(sh3_base_device::bbrb_w));
+ map(0xffffff90, 0xffffff93).rw(FUNC(sh3_base_device::bdrb_r), FUNC(sh3_base_device::bdrb_w));
+ map(0xffffff94, 0xffffff97).rw(FUNC(sh3_base_device::bdmrb_r), FUNC(sh3_base_device::bdmrb_w));
+ map(0xffffff98, 0xffffff99).rw(FUNC(sh3_base_device::brcr_r), FUNC(sh3_base_device::brcr_w));
+}
+
+void sh3_base_device::ubc_7709s_map(address_map& map)
+{
+ ubc_map(map);
+
+ map(0xffffff9c, 0xffffff9d).rw(FUNC(sh3_base_device::betr_r), FUNC(sh3_base_device::betr_w));
+ map(0xffffffac, 0xffffffaf).rw(FUNC(sh3_base_device::brsr_r), FUNC(sh3_base_device::brsr_w));
+ map(0xffffffbc, 0xffffffbf).rw(FUNC(sh3_base_device::brdr_r), FUNC(sh3_base_device::brdr_w));
+}
+
+void sh3_base_device::cpg_map(address_map& map)
+{
+ map(0xffffff80, 0xffffff81).rw(FUNC(sh3_base_device::frqcr_r), FUNC(sh3_base_device::frqcr_w));
+ map(0xffffff82, 0xffffff83).rw(FUNC(sh3_base_device::stbcr_r), FUNC(sh3_base_device::stbcr_w));
+ map(0xffffff84, 0xffffff84).r(FUNC(sh3_base_device::wtcnt_r));
+ map(0xffffff84, 0xffffff85).w(FUNC(sh3_base_device::wtcnt_w));
+ map(0xffffff86, 0xffffff86).r(FUNC(sh3_base_device::wtcsr_r));
+ map(0xffffff86, 0xffffff87).w(FUNC(sh3_base_device::wtcsr_w));
+}
+
+void sh3_base_device::cpg_7709_map(address_map& map)
+{
+ cpg_map(map);
+
+ map(0xffffff88, 0xffffff88).rw(FUNC(sh3_base_device::stbcr2_r), FUNC(sh3_base_device::stbcr2_w));
+}
+
+void sh3_base_device::bsc_map(address_map& map)
+{
+ map(0xffffff60, 0xffffff61).rw(FUNC(sh3_base_device::bcr1_r), FUNC(sh3_base_device::bcr1_w));
+ map(0xffffff62, 0xffffff63).rw(FUNC(sh3_base_device::bcr2_r), FUNC(sh3_base_device::bcr2_w));
+ map(0xffffff64, 0xffffff65).rw(FUNC(sh3_base_device::wcr1_r), FUNC(sh3_base_device::wcr1_w));
+ map(0xffffff66, 0xffffff67).rw(FUNC(sh3_base_device::wcr2_r), FUNC(sh3_base_device::wcr2_w));
+ map(0xffffff68, 0xffffff69).rw(FUNC(sh3_base_device::mcr_r), FUNC(sh3_base_device::mcr_w));
+ map(0xffffff6c, 0xffffff6d).rw(FUNC(sh3_base_device::pcr_r), FUNC(sh3_base_device::pcr_w));
+ map(0xffffff6e, 0xffffff6f).rw(FUNC(sh3_base_device::rtcsr_r), FUNC(sh3_base_device::rtcsr_w));
+ map(0xffffff70, 0xffffff71).rw(FUNC(sh3_base_device::rtcnt_r), FUNC(sh3_base_device::rtcnt_w));
+ map(0xffffff72, 0xffffff73).rw(FUNC(sh3_base_device::rtcor_r), FUNC(sh3_base_device::rtcor_w));
+ map(0xffffff74, 0xffffff75).rw(FUNC(sh3_base_device::rfcr_r), FUNC(sh3_base_device::rfcr_w));
+ map(0xfffd0000, 0xffffeffe).rw(FUNC(sh3_base_device::sdmr_r), FUNC(sh3_base_device::sdmr_w));
+}
+
+void sh3_base_device::bsc_7708_map(address_map& map)
+{
+ bsc_map(map);
+
+ map(0xffffff6a, 0xffffff6b).rw(FUNC(sh3_base_device::dcr_r), FUNC(sh3_base_device::dcr_w));
+ map(0xffffff76, 0xffffff77).rw(FUNC(sh3_base_device::pctr_r), FUNC(sh3_base_device::pctr_w));
+ map(0xffffff78, 0xffffff79).rw(FUNC(sh3_base_device::pdtr_r), FUNC(sh3_base_device::pdtr_w));
+}
+
+void sh3_base_device::bsc_7709_map(address_map& map)
+{
+ bsc_map(map);
+
+ map(0xffffff6a, 0xffffff6b).rw(FUNC(sh3_base_device::dcr_r), FUNC(sh3_base_device::dcr_w));
+ map(0xffffff7e, 0xffffff7f).rw(FUNC(sh3_base_device::bcr3_r), FUNC(sh3_base_device::bcr3_w));
+}
+
+void sh3_base_device::bsc_7709s_map(address_map& map)
+{
+ bsc_map(map);
+
+ map(0xffffff50, 0xffffff51).rw(FUNC(sh3_base_device::mcscr0_r), FUNC(sh3_base_device::mcscr0_w));
+ map(0xffffff52, 0xffffff53).rw(FUNC(sh3_base_device::mcscr1_r), FUNC(sh3_base_device::mcscr1_w));
+ map(0xffffff54, 0xffffff55).rw(FUNC(sh3_base_device::mcscr2_r), FUNC(sh3_base_device::mcscr2_w));
+ map(0xffffff56, 0xffffff57).rw(FUNC(sh3_base_device::mcscr3_r), FUNC(sh3_base_device::mcscr3_w));
+ map(0xffffff58, 0xffffff59).rw(FUNC(sh3_base_device::mcscr4_r), FUNC(sh3_base_device::mcscr4_w));
+ map(0xffffff5a, 0xffffff5b).rw(FUNC(sh3_base_device::mcscr5_r), FUNC(sh3_base_device::mcscr5_w));
+ map(0xffffff5c, 0xffffff5d).rw(FUNC(sh3_base_device::mcscr6_r), FUNC(sh3_base_device::mcscr6_w));
+ map(0xffffff5e, 0xffffff5f).rw(FUNC(sh3_base_device::mcscr7_r), FUNC(sh3_base_device::mcscr7_w));
+}
+
+void sh3_base_device::rtc_map(address_map& map)
+{
+ map(0xfffffec0, 0xfffffec0).r(FUNC(sh3_base_device::r64cnt_r));
+ map(0xfffffec2, 0xfffffec2).rw(FUNC(sh3_base_device::rseccnt_r), FUNC(sh3_base_device::rseccnt_w));
+ map(0xfffffec4, 0xfffffec4).rw(FUNC(sh3_base_device::rmincnt_r), FUNC(sh3_base_device::rmincnt_w));
+ map(0xfffffec6, 0xfffffec6).rw(FUNC(sh3_base_device::rhrcnt_r), FUNC(sh3_base_device::rhrcnt_w));
+ map(0xfffffec8, 0xfffffec8).rw(FUNC(sh3_base_device::rwkcnt_r), FUNC(sh3_base_device::rwkcnt_w));
+ map(0xfffffeca, 0xfffffeca).rw(FUNC(sh3_base_device::rdaycnt_r), FUNC(sh3_base_device::rdaycnt_w));
+ map(0xfffffecc, 0xfffffecc).rw(FUNC(sh3_base_device::rmoncnt_r), FUNC(sh3_base_device::rmoncnt_w));
+ map(0xfffffece, 0xfffffece).rw(FUNC(sh3_base_device::ryrcnt_r), FUNC(sh3_base_device::ryrcnt_w));
+ map(0xfffffec0, 0xfffffec0).rw(FUNC(sh3_base_device::rsecar_r), FUNC(sh3_base_device::rsecar_w));
+ map(0xfffffed2, 0xfffffed2).rw(FUNC(sh3_base_device::rminar_r), FUNC(sh3_base_device::rminar_w));
+ map(0xfffffed4, 0xfffffed4).rw(FUNC(sh3_base_device::rhrar_r), FUNC(sh3_base_device::rhrar_w));
+ map(0xfffffed6, 0xfffffed6).rw(FUNC(sh3_base_device::rwkar_r), FUNC(sh3_base_device::rwkar_w));
+ map(0xfffffed8, 0xfffffed8).rw(FUNC(sh3_base_device::rdayar_r), FUNC(sh3_base_device::rdayar_w));
+ map(0xfffffeda, 0xfffffeda).rw(FUNC(sh3_base_device::rmonar_r), FUNC(sh3_base_device::rmonar_w));
+ map(0xfffffedc, 0xfffffedc).rw(FUNC(sh3_base_device::rcr1_r), FUNC(sh3_base_device::rcr1_w));
+ map(0xfffffede, 0xfffffede).rw(FUNC(sh3_base_device::rcr2_r), FUNC(sh3_base_device::rcr2_w));
+}
+
+void sh3_base_device::intc_map(address_map& map)
+{
+ map(0xfffffee0, 0xfffffee1).rw(FUNC(sh3_base_device::icr0_r), FUNC(sh3_base_device::icr0_w));
+ map(0xfffffee2, 0xfffffee3).rw(FUNC(sh3_base_device::ipra_r), FUNC(sh3_base_device::ipra_w));
+ map(0xfffffee4, 0xfffffee5).rw(FUNC(sh3_base_device::iprb_r), FUNC(sh3_base_device::iprb_w));
+}
+
+void sh3_base_device::intc_7709_map(address_map& map)
+{
+ intc_map(map);
+
+ map(0x04000000, 0x04000003).rw(FUNC(sh3_base_device::intevt2_r), FUNC(sh3_base_device::intevt2_w));
+ map(0x04000004, 0x04000004).rw(FUNC(sh3_base_device::irr0_r), FUNC(sh3_base_device::irr0_w));
+ map(0x04000006, 0x04000006).rw(FUNC(sh3_base_device::irr1_r), FUNC(sh3_base_device::irr1_w));
+ map(0x04000008, 0x04000008).rw(FUNC(sh3_base_device::irr2_r), FUNC(sh3_base_device::irr2_w));
+ map(0x04000010, 0x04000011).rw(FUNC(sh3_base_device::icr1_r), FUNC(sh3_base_device::icr1_w));
+ map(0x04000012, 0x04000013).rw(FUNC(sh3_base_device::icr2_r), FUNC(sh3_base_device::icr2_w));
+ map(0x04000014, 0x04000015).rw(FUNC(sh3_base_device::pinter_r), FUNC(sh3_base_device::pinter_w));
+ map(0x04000016, 0x04000017).rw(FUNC(sh3_base_device::iprc_r), FUNC(sh3_base_device::iprc_w));
+ map(0x04000018, 0x04000019).rw(FUNC(sh3_base_device::iprd_r), FUNC(sh3_base_device::iprd_w));
+ map(0x0400001a, 0x0400001b).rw(FUNC(sh3_base_device::ipre_r), FUNC(sh3_base_device::ipre_w));
+}
+
+void sh3_base_device::dmac_7709_map(address_map& map)
+{
+ map(0x04000020, 0x04000023).rw(FUNC(sh3_base_device::sar0_r), FUNC(sh3_base_device::sar0_w));
+ map(0x04000024, 0x04000027).rw(FUNC(sh3_base_device::dar0_r), FUNC(sh3_base_device::dar0_w));
+ map(0x04000028, 0x0400002b).rw(FUNC(sh3_base_device::dmatcr0_r), FUNC(sh3_base_device::dmatcr0_w));
+ map(0x0400002c, 0x0400002f).rw(FUNC(sh3_base_device::chcr0_r), FUNC(sh3_base_device::chcr0_w));
+ map(0x04000030, 0x04000033).rw(FUNC(sh3_base_device::sar1_r), FUNC(sh3_base_device::sar1_w));
+ map(0x04000034, 0x04000037).rw(FUNC(sh3_base_device::dar1_r), FUNC(sh3_base_device::dar1_w));
+ map(0x04000038, 0x0400003b).rw(FUNC(sh3_base_device::dmatcr1_r), FUNC(sh3_base_device::dmatcr1_w));
+ map(0x0400003c, 0x0400003f).rw(FUNC(sh3_base_device::chcr1_r), FUNC(sh3_base_device::chcr1_w));
+ map(0x04000040, 0x04000043).rw(FUNC(sh3_base_device::sar2_r), FUNC(sh3_base_device::sar2_w));
+ map(0x04000044, 0x04000047).rw(FUNC(sh3_base_device::dar2_r), FUNC(sh3_base_device::dar2_w));
+ map(0x04000048, 0x0400004b).rw(FUNC(sh3_base_device::dmatcr2_r), FUNC(sh3_base_device::dmatcr2_w));
+ map(0x0400004c, 0x0400004f).rw(FUNC(sh3_base_device::chcr2_r), FUNC(sh3_base_device::chcr2_w));
+ map(0x04000050, 0x04000053).rw(FUNC(sh3_base_device::sar3_r), FUNC(sh3_base_device::sar3_w));
+ map(0x04000054, 0x04000057).rw(FUNC(sh3_base_device::dar3_r), FUNC(sh3_base_device::dar3_w));
+ map(0x04000058, 0x0400005b).rw(FUNC(sh3_base_device::dmatcr3_r), FUNC(sh3_base_device::dmatcr3_w));
+ map(0x0400005c, 0x0400005f).rw(FUNC(sh3_base_device::chcr3_r), FUNC(sh3_base_device::chcr3_w));
+ map(0x04000060, 0x04000061).lrw16(
+ [this](offs_t offset, uint16_t mem_mask) { return dmaor_r(offset, mem_mask); }, "sh3_base_device::dmaor_r",
+ [this](offs_t offset, uint16_t data, uint16_t mem_mask) { dmaor_w(offset, data, mem_mask); }, "sh3_base_device::dmaor_w");
+}
+
+void sh3_base_device::tmu_map(address_map& map)
+{
+ map(0xfffffe90, 0xfffffe90).rw(FUNC(sh3_base_device::tocr_r), FUNC(sh3_base_device::tocr_w));
+ map(0xfffffe92, 0xfffffe92).rw(FUNC(sh3_base_device::tstr_r), FUNC(sh3_base_device::tstr_w));
+ map(0xfffffe94, 0xfffffe97).rw(FUNC(sh3_base_device::tcor0_r), FUNC(sh3_base_device::tcor0_w));
+ map(0xfffffe98, 0xfffffe9b).rw(FUNC(sh3_base_device::tcnt0_r), FUNC(sh3_base_device::tcnt0_w));
+ map(0xfffffe9c, 0xfffffe9d).rw(FUNC(sh3_base_device::tcr0_r), FUNC(sh3_base_device::tcr0_w));
+ map(0xfffffea0, 0xfffffea3).rw(FUNC(sh3_base_device::tcor1_r), FUNC(sh3_base_device::tcor1_w));
+ map(0xfffffea4, 0xfffffea7).rw(FUNC(sh3_base_device::tcnt1_r), FUNC(sh3_base_device::tcnt1_w));
+ map(0xfffffea8, 0xfffffea9).rw(FUNC(sh3_base_device::tcr1_r), FUNC(sh3_base_device::tcr1_w));
+ map(0xfffffeac, 0xfffffeaf).rw(FUNC(sh3_base_device::tcor2_r), FUNC(sh3_base_device::tcor2_w));
+ map(0xfffffeb0, 0xfffffeb3).rw(FUNC(sh3_base_device::tcnt2_r), FUNC(sh3_base_device::tcnt2_w));
+ map(0xfffffeb4, 0xfffffeb5).rw(FUNC(sh3_base_device::tcr2_r), FUNC(sh3_base_device::tcr2_w));
+ map(0xfffffeb8, 0xfffffebb).rw(FUNC(sh3_base_device::tcpr2_r), FUNC(sh3_base_device::tcpr2_w));
+}
+
+void sh3_base_device::sci_7708_map(address_map& map)
+{
+ sci_7709_map(map);
+
+ map(0xffffff7c, 0xffffff7c).rw(FUNC(sh3_base_device::scsptr_r), FUNC(sh3_base_device::scsptr_w));
+}
+
+void sh3_base_device::sci_7709_map(address_map& map)
+{
+ map(0xfffffe80, 0xfffffe80).rw(FUNC(sh3_base_device::scsmr_r), FUNC(sh3_base_device::scsmr_w));
+ map(0xfffffe82, 0xfffffe82).rw(FUNC(sh3_base_device::scbrr_r), FUNC(sh3_base_device::scbrr_w));
+ map(0xfffffe84, 0xfffffe84).rw(FUNC(sh3_base_device::scscr_r), FUNC(sh3_base_device::scscr_w));
+ map(0xfffffe86, 0xfffffe86).rw(FUNC(sh3_base_device::sctdr_r), FUNC(sh3_base_device::sctdr_w));
+ map(0xfffffe88, 0xfffffe88).rw(FUNC(sh3_base_device::scssr_r), FUNC(sh3_base_device::scssr_w));
+ map(0xfffffe8a, 0xfffffe8a).r(FUNC(sh3_base_device::scrdr_r));
+ map(0xfffffe8c, 0xfffffe8c).rw(FUNC(sh3_base_device::scscmr_r), FUNC(sh3_base_device::scscmr_w));
+}
+
+void sh3_base_device::cmt_7709_map(address_map& map)
+{
+ map(0x04000070, 0x04000071).rw(FUNC(sh3_base_device::cmstr_r), FUNC(sh3_base_device::cmstr_w));
+ map(0x04000072, 0x04000073).rw(FUNC(sh3_base_device::cmscr_r), FUNC(sh3_base_device::cmscr_w));
+ map(0x04000074, 0x04000075).rw(FUNC(sh3_base_device::cmcnt_r), FUNC(sh3_base_device::cmcnt_w));
+ map(0x04000076, 0x04000077).rw(FUNC(sh3_base_device::cmcor_r), FUNC(sh3_base_device::cmcor_w));
+}
+
+void sh3_base_device::ad_7709_map(address_map& map)
+{
+ map(0x04000080, 0x04000080).rw(FUNC(sh3_base_device::addrah_r), FUNC(sh3_base_device::addrah_w));
+ map(0x04000082, 0x04000082).rw(FUNC(sh3_base_device::addral_r), FUNC(sh3_base_device::addral_w));
+ map(0x04000084, 0x04000084).rw(FUNC(sh3_base_device::addrbh_r), FUNC(sh3_base_device::addrbh_w));
+ map(0x04000086, 0x04000086).rw(FUNC(sh3_base_device::addrbl_r), FUNC(sh3_base_device::addrbl_w));
+ map(0x04000088, 0x04000088).rw(FUNC(sh3_base_device::addrch_r), FUNC(sh3_base_device::addrch_w));
+ map(0x0400008a, 0x0400008a).rw(FUNC(sh3_base_device::addrcl_r), FUNC(sh3_base_device::addrcl_w));
+ map(0x0400008c, 0x0400008c).rw(FUNC(sh3_base_device::addrdh_r), FUNC(sh3_base_device::addrdh_w));
+ map(0x0400008e, 0x0400008e).rw(FUNC(sh3_base_device::addrdl_r), FUNC(sh3_base_device::addrdl_w));
+ map(0x04000090, 0x04000090).rw(FUNC(sh3_base_device::adcsr_r), FUNC(sh3_base_device::adcsr_w));
+ map(0x04000092, 0x04000092).rw(FUNC(sh3_base_device::adcr_r), FUNC(sh3_base_device::adcr_w));
+}
+
+void sh3_base_device::da_7709_map(address_map& map)
+{
+ map(0x040000a0, 0x040000a0).rw(FUNC(sh3_base_device::dadr0_r), FUNC(sh3_base_device::dadr0_w));
+ map(0x040000a2, 0x040000a2).rw(FUNC(sh3_base_device::dadr1_r), FUNC(sh3_base_device::dadr1_w));
+ map(0x040000a4, 0x040000a4).rw(FUNC(sh3_base_device::dadcr_r), FUNC(sh3_base_device::dadcr_w));
+}
+
+void sh3_base_device::port_7709_map(address_map& map)
+{
+ map(0x04000100, 0x04000101).rw(FUNC(sh3_base_device::pacr_r), FUNC(sh3_base_device::pacr_w));
+ map(0x04000102, 0x04000103).rw(FUNC(sh3_base_device::pbcr_r), FUNC(sh3_base_device::pbcr_w));
+ map(0x04000104, 0x04000105).rw(FUNC(sh3_base_device::pccr_r), FUNC(sh3_base_device::pccr_w));
+ map(0x04000106, 0x04000107).rw(FUNC(sh3_base_device::pdcr_r), FUNC(sh3_base_device::pdcr_w));
+ map(0x04000108, 0x04000109).rw(FUNC(sh3_base_device::pecr_r), FUNC(sh3_base_device::pecr_w));
+ map(0x0400010a, 0x0400010b).rw(FUNC(sh3_base_device::pfcr_r), FUNC(sh3_base_device::pfcr_w));
+ map(0x0400010c, 0x0400010d).rw(FUNC(sh3_base_device::pgcr_r), FUNC(sh3_base_device::pgcr_w));
+ map(0x0400010e, 0x0400010f).rw(FUNC(sh3_base_device::phcr_r), FUNC(sh3_base_device::phcr_w));
+ map(0x04000110, 0x04000111).rw(FUNC(sh3_base_device::pjcr_r), FUNC(sh3_base_device::pjcr_w));
+ map(0x04000112, 0x04000113).rw(FUNC(sh3_base_device::pkcr_r), FUNC(sh3_base_device::pkcr_w));
+ map(0x04000114, 0x04000115).rw(FUNC(sh3_base_device::plcr_r), FUNC(sh3_base_device::plcr_w));
+ map(0x04000116, 0x04000117).rw(FUNC(sh3_base_device::scpcr_r), FUNC(sh3_base_device::scpcr_w));
+ map(0x04000120, 0x04000120).rw(FUNC(sh3_base_device::padr_r), FUNC(sh3_base_device::padr_w));
+ map(0x04000122, 0x04000122).rw(FUNC(sh3_base_device::pbdr_r), FUNC(sh3_base_device::pbdr_w));
+ map(0x04000124, 0x04000124).rw(FUNC(sh3_base_device::pcdr_r), FUNC(sh3_base_device::pcdr_w));
+ map(0x04000126, 0x04000126).rw(FUNC(sh3_base_device::pddr_r), FUNC(sh3_base_device::pddr_w));
+ map(0x04000128, 0x04000128).rw(FUNC(sh3_base_device::pedr_r), FUNC(sh3_base_device::pedr_w));
+ map(0x0400012a, 0x0400012a).rw(FUNC(sh3_base_device::pfdr_r), FUNC(sh3_base_device::pfdr_w));
+ map(0x0400012c, 0x0400012c).rw(FUNC(sh3_base_device::pgdr_r), FUNC(sh3_base_device::pgdr_w));
+ map(0x0400012e, 0x0400012e).rw(FUNC(sh3_base_device::phdr_r), FUNC(sh3_base_device::phdr_w));
+ map(0x04000130, 0x04000130).rw(FUNC(sh3_base_device::pjdr_r), FUNC(sh3_base_device::pjdr_w));
+ map(0x04000132, 0x04000132).rw(FUNC(sh3_base_device::pkdr_r), FUNC(sh3_base_device::pkdr_w));
+ map(0x04000134, 0x04000134).rw(FUNC(sh3_base_device::pldr_r), FUNC(sh3_base_device::pldr_w));
+ map(0x04000136, 0x04000136).rw(FUNC(sh3_base_device::scpdr_r), FUNC(sh3_base_device::scpdr_w));
+}
+
+void sh3_base_device::irda_7709_map(address_map& map)
+{
+ map(0x04000140, 0x04000140).rw(FUNC(sh3_base_device::scsmr1_r), FUNC(sh3_base_device::scsmr1_w));
+ map(0x04000142, 0x04000142).rw(FUNC(sh3_base_device::scbrr1_r), FUNC(sh3_base_device::scbrr1_w));
+ map(0x04000144, 0x04000144).rw(FUNC(sh3_base_device::scscr1_r), FUNC(sh3_base_device::scscr1_w));
+ map(0x04000146, 0x04000146).rw(FUNC(sh3_base_device::scftdr1_r), FUNC(sh3_base_device::scftdr1_w));
+ map(0x04000148, 0x04000149).rw(FUNC(sh3_base_device::scssr1_r), FUNC(sh3_base_device::scssr1_w));
+ map(0x0400014a, 0x0400014a).rw(FUNC(sh3_base_device::scfrdr1_r), FUNC(sh3_base_device::scfrdr1_w));
+ map(0x0400014c, 0x0400014c).rw(FUNC(sh3_base_device::scfcr1_r), FUNC(sh3_base_device::scfcr1_w));
+ map(0x0400014e, 0x0400014f).rw(FUNC(sh3_base_device::scfdr1_r), FUNC(sh3_base_device::scfdr1_w));
+}
+
+void sh3_base_device::scif_7709_map(address_map& map)
+{
+ map(0x04000150, 0x04000150).rw(FUNC(sh3_base_device::scsmr2_r), FUNC(sh3_base_device::scsmr2_w));
+ map(0x04000152, 0x04000152).rw(FUNC(sh3_base_device::scbrr2_r), FUNC(sh3_base_device::scbrr2_w));
+ map(0x04000154, 0x04000154).rw(FUNC(sh3_base_device::scscr2_r), FUNC(sh3_base_device::scscr2_w));
+ map(0x04000156, 0x04000156).rw(FUNC(sh3_base_device::scftdr2_r), FUNC(sh3_base_device::scftdr2_w));
+ map(0x04000158, 0x04000159).rw(FUNC(sh3_base_device::scssr2_r), FUNC(sh3_base_device::scssr2_w));
+ map(0x0400015a, 0x0400015a).rw(FUNC(sh3_base_device::scfrdr2_r), FUNC(sh3_base_device::scfrdr2_w));
+ map(0x0400015c, 0x0400015c).rw(FUNC(sh3_base_device::scfcr2_r), FUNC(sh3_base_device::scfcr2_w));
+ map(0x0400015e, 0x0400015f).rw(FUNC(sh3_base_device::scfdr2_r), FUNC(sh3_base_device::scfdr2_w));
+}
+
+void sh3_base_device::udi_7709s_map(address_map& map)
+{
+ map(0x4000200, 0x4000201).rw(FUNC(sh3_base_device::sdir_r), FUNC(sh3_base_device::sdir_w));
+}
sh34_base_device::sh34_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, endianness_t endianness, address_map_constructor internal)
: sh_common_execution(mconfig, type, tag, owner, clock, endianness, internal)
@@ -90,6 +903,32 @@ device_memory_interface::space_config_vector sh34_base_device::memory_space_conf
};
}
+bool sh34_base_device::memory_translate(int spacenum, int intention, offs_t& address, address_space*& target_space)
+{
+ target_space = &space(spacenum);
+
+ if (address >= 0xe0000000)
+ return true;
+
+ if (address >= 0x80000000) // P1/P2/P3 region
+ {
+ address &= SH34_AM;
+ return true;
+ }
+ else // P0 region
+ {
+ if (!m_sh4_mmu_enabled)
+ {
+ address &= SH34_AM;
+ return true;
+ }
+ else
+ {
+ address = get_remap(address & SH34_AM);
+ return true;
+ }
+ }
+}
sh3_base_device::sh3_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, endianness_t endianness)
: sh34_base_device(mconfig, type, tag, owner, clock, endianness, address_map_constructor(FUNC(sh3_base_device::sh3_internal_map), this))
@@ -107,29 +946,63 @@ sh4_base_device::sh4_base_device(const machine_config &mconfig, device_type type
}
-sh3_device::sh3_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : sh3_base_device(mconfig, SH3LE, tag, owner, clock, ENDIANNESS_LITTLE)
+sh3_device::sh3_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, endianness_t endianness)
+ : sh3_base_device(mconfig, SH3, tag, owner, clock, endianness)
+{
+}
+
+sh7708s_device::sh7708s_device(const machine_config& mconfig, const char* tag, device_t* owner, uint32_t clock, endianness_t endianness)
+ : sh3_base_device(mconfig, SH7708S, tag, owner, clock, endianness)
+{
+}
+
+sh7709_device::sh7709_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, endianness_t endianness)
+ : sh3_base_device(mconfig, SH7709, tag, owner, clock, endianness)
+{
+}
+
+sh7709s_device::sh7709s_device(const machine_config& mconfig, const char* tag, device_t* owner, uint32_t clock, endianness_t endianness)
+ : sh3_base_device(mconfig, SH7709S, tag, owner, clock, endianness)
{
}
-sh3be_device::sh3be_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : sh3_base_device(mconfig, SH3BE, tag, owner, clock, ENDIANNESS_BIG)
+sh4_device::sh4_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, endianness_t endianness)
+ : sh4_base_device(mconfig, SH4, tag, owner, clock, endianness)
+{
+}
+
+sh7091_device::sh7091_device(const machine_config& mconfig, const char* tag, device_t* owner, uint32_t clock, endianness_t endianness)
+ : sh4_base_device(mconfig, SH7091, tag, owner, clock, endianness)
{
}
+sh7750_device::sh7750_device(const machine_config& mconfig, const char* tag, device_t* owner, uint32_t clock, endianness_t endianness)
+ : sh4_base_device(mconfig, SH7750, tag, owner, clock, endianness)
+{
+}
-sh4_device::sh4_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : sh4_base_device(mconfig, SH4LE, tag, owner, clock, ENDIANNESS_LITTLE)
+sh7750s_device::sh7750s_device(const machine_config& mconfig, const char* tag, device_t* owner, uint32_t clock, endianness_t endianness)
+ : sh4_base_device(mconfig, SH7750S, tag, owner, clock, endianness)
{
}
+sh7750r_device::sh7750r_device(const machine_config& mconfig, const char* tag, device_t* owner, uint32_t clock, endianness_t endianness)
+ : sh4_base_device(mconfig, SH7750R, tag, owner, clock, endianness)
+{
+}
-sh4be_device::sh4be_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : sh4_base_device(mconfig, SH4BE, tag, owner, clock, ENDIANNESS_BIG)
+sh7751_device::sh7751_device(const machine_config& mconfig, const char* tag, device_t* owner, uint32_t clock, endianness_t endianness)
+ : sh4_base_device(mconfig, SH7751, tag, owner, clock, endianness)
{
+ m_pciconf0 = 0x35051054;
}
+sh7751r_device::sh7751r_device(const machine_config& mconfig, const char* tag, device_t* owner, uint32_t clock, endianness_t endianness)
+ : sh4_base_device(mconfig, SH7751R, tag, owner, clock, endianness)
+{
+ m_pciconf0 = 0x350e1054;
+}
std::unique_ptr<util::disasm_interface> sh34_base_device::create_disassembler()
{
@@ -149,28 +1022,28 @@ void sh34_base_device::LDTLB(const uint16_t opcode)
void sh4_base_device::LDTLB(const uint16_t opcode)
{
- int replace = (m_m[MMUCR] & 0x0000fc00) >> 10;
+ int replace = (m_mmucr & 0x0000fc00) >> 10;
logerror("using LDTLB to replace UTLB entry %02x\n", replace);
// these come from PTEH
- m_utlb[replace].VPN = (m_m[PTEH] & 0xfffffc00) >> 10;
- // m_utlb[replace].D = (m_m[PTEH] & 0x00000200) >> 9; // from PTEL
- // m_utlb[replace].V = (m_m[PTEH] & 0x00000100) >> 8; // from PTEL
- m_utlb[replace].ASID = (m_m[PTEH] & 0x000000ff) >> 0;
+ m_utlb[replace].VPN = (m_pteh & 0xfffffc00) >> 10;
+ // m_utlb[replace].D = (m_pteh & 0x00000200) >> 9; // from PTEL
+ // m_utlb[replace].V = (m_pteh & 0x00000100) >> 8; // from PTEL
+ m_utlb[replace].ASID = (m_pteh & 0x000000ff) >> 0;
// these come from PTEL
- m_utlb[replace].PPN = (m_m[PTEL] & 0x1ffffc00) >> 10;
- m_utlb[replace].V = (m_m[PTEL] & 0x00000100) >> 8;
- m_utlb[replace].PSZ = (m_m[PTEL] & 0x00000080) >> 6;
- m_utlb[replace].PSZ |= (m_m[PTEL] & 0x00000010) >> 4;
- m_utlb[replace].PPR = (m_m[PTEL] & 0x00000060) >> 5;
- m_utlb[replace].C = (m_m[PTEL] & 0x00000008) >> 3;
- m_utlb[replace].D = (m_m[PTEL] & 0x00000004) >> 2;
- m_utlb[replace].SH = (m_m[PTEL] & 0x00000002) >> 1;
- m_utlb[replace].WT = (m_m[PTEL] & 0x00000001) >> 0;
+ m_utlb[replace].PPN = (m_ptel & 0x1ffffc00) >> 10;
+ m_utlb[replace].V = (m_ptel & 0x00000100) >> 8;
+ m_utlb[replace].PSZ = (m_ptel & 0x00000080) >> 6;
+ m_utlb[replace].PSZ |= (m_ptel & 0x00000010) >> 4;
+ m_utlb[replace].PPR = (m_ptel & 0x00000060) >> 5;
+ m_utlb[replace].C = (m_ptel & 0x00000008) >> 3;
+ m_utlb[replace].D = (m_ptel & 0x00000004) >> 2;
+ m_utlb[replace].SH = (m_ptel & 0x00000002) >> 1;
+ m_utlb[replace].WT = (m_ptel & 0x00000001) >> 0;
// these come from PTEA
- m_utlb[replace].TC = (m_m[PTEA] & 0x00000008) >> 3;
- m_utlb[replace].SA = (m_m[PTEA] & 0x00000007) >> 0;
+ m_utlb[replace].TC = (m_ptea & 0x00000008) >> 3;
+ m_utlb[replace].SA = (m_ptea & 0x00000007) >> 0;
}
#if 0
@@ -499,11 +1372,11 @@ inline void sh34_base_device::TRAPA(uint32_t i)
if (m_cpu_type == CPU_TYPE_SH4)
{
- m_m[TRA] = imm << 2;
+ m_tra = imm << 2;
}
else /* SH3 */
{
- m_sh3internal_upper[SH3_TRA_ADDR] = imm << 2;
+ m_tra = imm << 2;
}
m_sh2_state->m_ssr = m_sh2_state->sr;
@@ -522,11 +1395,11 @@ inline void sh34_base_device::TRAPA(uint32_t i)
if (m_cpu_type == CPU_TYPE_SH4)
{
- m_m[EXPEVT] = 0x00000160;
+ m_expevt = 0x00000160;
}
else /* SH3 */
{
- m_sh3internal_upper[SH3_EXPEVT_ADDR] = 0x00000160;
+ m_expevt = 0x00000160;
}
m_sh2_state->pc = m_sh2_state->vbr + 0x00000100;
@@ -813,7 +1686,7 @@ inline void sh34_base_device::PREFM(const uint16_t opcode)
{
if (m_cpu_type == CPU_TYPE_SH4)
{
- dest |= (m_m[QACR0] & 0x1C) << 24;
+ dest |= (m_qacr0 & 0x1C) << 24;
}
else
{
@@ -824,7 +1697,7 @@ inline void sh34_base_device::PREFM(const uint16_t opcode)
{
if (m_cpu_type == CPU_TYPE_SH4)
{
- dest |= (m_m[QACR1] & 0x1C) << 24;
+ dest |= (m_qacr1 & 0x1C) << 24;
}
else
{
@@ -1614,41 +2487,67 @@ void sh34_base_device::device_reset()
m_sh2_state->m_test_irq = 0;
memset(m_exception_priority, 0, sizeof(m_exception_priority));
memset(m_exception_requesting, 0, sizeof(m_exception_requesting));
- memset(m_m, 0, sizeof(m_m));
- memset(m_sh3internal_upper, 0, sizeof(m_sh3internal_upper));
- memset(m_sh3internal_lower, 0, sizeof(m_sh3internal_lower));
memset(m_irq_line_state, 0, sizeof(m_irq_line_state));
- m_SH4_TSTR = 0;
- m_SH4_TCNT0 = 0;
- m_SH4_TCNT1 = 0;
- m_SH4_TCNT2 = 0;
- m_SH4_TCR0 = 0;
- m_SH4_TCR1 = 0;
- m_SH4_TCR2 = 0;
- m_SH4_TCOR0 = 0;
- m_SH4_TCOR1 = 0;
- m_SH4_TCOR2 = 0;
- m_SH4_TOCR = 0;
- m_SH4_TCPR2 = 0;
- m_SH4_IPRA = 0;
- m_SH4_IPRC = 0;
- m_SH4_SAR0 = 0;
- m_SH4_SAR1 = 0;
- m_SH4_SAR2 = 0;
- m_SH4_SAR3 = 0;
- m_SH4_DAR0 = 0;
- m_SH4_DAR1 = 0;
- m_SH4_DAR2 = 0;
- m_SH4_DAR3 = 0;
- m_SH4_CHCR0 = 0;
- m_SH4_CHCR1 = 0;
- m_SH4_CHCR2 = 0;
- m_SH4_CHCR3 = 0;
- m_SH4_DMATCR0 = 0;
- m_SH4_DMATCR1 = 0;
- m_SH4_DMATCR2 = 0;
- m_SH4_DMATCR3 = 0;
- m_SH4_DMAOR = 0;
+
+ // CCN
+ m_pteh = 0;
+ m_ptel = 0;
+ m_ttb = 0;
+ m_mmucr = 0;
+ m_ccr = 0;
+ m_tra = 0;
+ m_expevt = 0;
+ m_intevt = 0;
+
+ // CCN 7709S
+ m_ccr2 = 0;
+
+ // CCN 7091
+ m_ptea = 0;
+ m_qacr0 = 0;
+ m_qacr1 = 0;
+
+ // TMU
+ m_tocr = 0;
+ m_tstr = 0;
+ m_tcor0 = 0xffffffff;
+ m_tcnt0 = 0xffffffff;
+ m_tcr0 = 0;
+ m_tcor1 = 0xffffffff;
+ m_tcnt1 = 0xffffffff;
+ m_tcr1 = 0;
+ m_tcor2 = 0xffffffff;
+ m_tcnt2 = 0xffffffff;
+ m_tcr2 = 0;
+ m_tcpr2 = 0;
+
+ // INTC
+ m_icr = 0;
+ m_ipra = 0;
+ m_iprc = 0;
+
+ // INTC 7709
+ m_intevt2 = 0;
+
+ // DMAC
+ m_sar0 = 0;
+ m_sar1 = 0;
+ m_sar2 = 0;
+ m_sar3 = 0;
+ m_dar0 = 0;
+ m_dar1 = 0;
+ m_dar2 = 0;
+ m_dar3 = 0;
+ m_chcr0 = 0;
+ m_chcr1 = 0;
+ m_chcr2 = 0;
+ m_chcr3 = 0;
+ m_dmatcr0 = 0;
+ m_dmatcr1 = 0;
+ m_dmatcr2 = 0;
+ m_dmatcr3 = 0;
+ m_dmaor = 0;
+
m_nmi_line_state = 0;
m_sh2_state->m_frt_input = 0;
m_internal_irq_vector = 0;
@@ -1662,11 +2561,6 @@ void sh34_base_device::device_reset()
if (m_dma_timer[i])
m_dma_timer[i]->adjust(attotime::never, i);
}
- if (m_refresh_timer)
- m_refresh_timer->adjust(attotime::never);
- m_refresh_timer_base = 0;
- if (m_rtc_timer)
- m_rtc_timer->adjust(attotime::never);
memset(m_dma_timer_active, 0, sizeof(m_dma_timer_active));
memset(m_dma_source, 0, sizeof(m_dma_source));
memset(m_dma_destination, 0, sizeof(m_dma_destination));
@@ -1682,10 +2576,8 @@ void sh34_base_device::device_reset()
sh4_default_exception_priorities();
- m_rtc_timer->adjust(attotime::from_hz(128));
-
m_sh2_state->pc = 0xa0000000;
- m_sh2_state->m_ppc = m_sh2_state->pc & SH34_AM;
+ m_sh2_state->m_ppc = m_sh2_state->pc;
m_sh2_state->r[15] = read_long(4);
m_sh2_state->sr = 0x700000f0;
m_sh2_state->m_fpscr = 0x00040001;
@@ -1710,25 +2602,158 @@ void sh3_base_device::device_reset()
{
sh34_base_device::device_reset();
- m_SH4_TCOR0 = 0xffffffff;
- m_SH4_TCNT0 = 0xffffffff;
- m_SH4_TCOR1 = 0xffffffff;
- m_SH4_TCNT1 = 0xffffffff;
- m_SH4_TCOR2 = 0xffffffff;
- m_SH4_TCNT2 = 0xffffffff;
+ // INTC
+ m_icr0 &= 0x8000;
+ m_iprb = 0;
+
+ // INTC 7709
+ m_irr0 = 0;
+ m_irr1 = 0;
+ m_irr2 = 0;
+ m_icr1 = 0;
+ m_icr2 = 0;
+ m_pinter = 0;
+ m_iprd = 0;
+ m_ipre = 0;
+
+ // SCI
+ m_scsmr = 0;
+ m_scbrr = 0xff;
+ m_scscr = 0;
+ m_sctdr = 0xff;
+ m_scssr = 0x84;
+ m_scrdr = 0;
+ m_scscmr = 0;
+
+ // SCI 7709
+ m_scsptr = 0;
+
+ // CMT 7709
+ m_cmstr = 0;
+ m_cmscr = 0;
+ m_cmcnt = 0;
+ m_cmcor = 0xffff;
+
+ // AD 7709
+ m_addrah = 0;
+ m_addral = 0;
+ m_addrbh = 0;
+ m_addrbl = 0;
+ m_addrch = 0;
+ m_addrcl = 0;
+ m_addrdh = 0;
+ m_addrdl = 0;
+ m_adcsr = 0;
+ m_adcr = 0x07;
+
+ // DA 7709
+ m_dadr0 = 0;
+ m_dadr1 = 0;
+ m_dadcr = 0x1f;
+
+ // PORT 7709
+ m_pacr = 0;
+ m_pbcr = 0;
+ m_pccr = 0xaaaa;
+ m_pdcr = 0xaa8a;
+ m_pecr = 0xaaaa; // asemd0=0x2aa8
+ m_pfcr = 0xaaaa; // asemd0=0x00aa
+ m_pgcr = 0xaaaa; // asemd0=0xa200
+ m_phcr = 0xaaaa; // asemd0=0x8aaa
+ m_pjcr = 0;
+ m_pkcr = 0;
+ m_plcr = 0;
+ m_scpcr = 0xa888;
+ m_padr = 0;
+ m_pbdr = 0;
+ m_pcdr = 0;
+ m_pddr = 0;
+ m_pedr = 0;
+ m_pfdr = 0;
+ m_pgdr = 0;
+ m_phdr = 0;
+ m_pjdr = 0;
+ m_pkdr = 0;
+ m_pldr = 0;
+ m_scpdr = 0;
+
+ // IRDA 7709
+ m_scsmr1 = 0;
+ m_scbrr1 = 0xff;
+ m_scscr1 = 0;
+ m_scftdr1 = 0;
+ m_scssr1 = 0x60;
+ m_scfrdr1 = 0;
+ m_scfcr1 = 0;
+ m_scfdr1 = 0;
+
+ // SCIF 7709
+ m_scsmr2 = 0;
+ m_scbrr2 = 0xff;
+ m_scscr2 = 0;
+ m_scftdr2 = 0;
+ m_scssr2 = 0x60;
+ m_scfrdr2 = 0;
+ m_scfcr2 = 0;
+ m_scfdr2 = 0;
+
+ // UDI 7709S
+ m_sdir = 0xffff;
}
void sh4_base_device::device_reset()
{
sh34_base_device::device_reset();
- m_m[RCR2] = 0x09;
- m_SH4_TCOR0 = 0xffffffff;
- m_SH4_TCNT0 = 0xffffffff;
- m_SH4_TCOR1 = 0xffffffff;
- m_SH4_TCNT1 = 0xffffffff;
- m_SH4_TCOR2 = 0xffffffff;
- m_SH4_TCNT2 = 0xffffffff;
+ m_rtc_timer->adjust(attotime::from_hz(128));
+ m_refresh_timer->adjust(attotime::never);
+ m_refresh_timer_base = 0;
+
+ // DMAC 7750R
+ m_sar4 = 0;
+ m_dar4 = 0;
+ m_sar5 = 0;
+ m_dar5 = 0;
+ m_sar6 = 0;
+ m_dar6 = 0;
+ m_sar7 = 0;
+ m_dar7 = 0;
+ m_chcr4 = 0;
+ m_chcr5 = 0;
+ m_chcr6 = 0;
+ m_chcr7 = 0;
+ m_dmatcr4 = 0;
+ m_dmatcr5 = 0;
+ m_dmatcr6 = 0;
+ m_dmatcr7 = 0;
+
+ // INTC
+ m_iprb = 0;
+
+ // INTC 7750S
+ m_iprd = 0xda74;
+
+ // SCI
+ m_scsmr1 = 0;
+ m_scbrr1 = 0xff;
+ m_scscr1 = 0;
+ m_sctdr1 = 0xff;
+ m_scssr1 = 0x84;
+ m_scrdr1 = 0x00;
+ m_scscmr1 = 0x00;
+ m_scsptr1 = 0;
+
+ // SCIF
+ m_scsmr2 = 0;
+ m_scbrr2 = 0xff;
+ m_scscr2 = 0;
+ m_scftdr2 = 0;
+ m_scfsr2 = 0x60;
+ m_scfrdr2 = 0;
+ m_scfcr2 = 0;
+ m_scfdr2 = 0;
+ m_scsptr2 = 0;
+ m_sclsr2 = 0;
}
inline void sh34_base_device::execute_one_0000(const uint16_t opcode)
@@ -1967,8 +2992,8 @@ void sh34_base_device::execute_run()
do
{
- m_sh2_state->m_ppc = m_sh2_state->pc & SH34_AM;
- debugger_instruction_hook(m_sh2_state->pc & SH34_AM);
+ m_sh2_state->m_ppc = m_sh2_state->pc;
+ debugger_instruction_hook(m_sh2_state->pc);
uint16_t opcode;
@@ -1994,92 +3019,265 @@ void sh34_base_device::execute_run()
} while (m_sh2_state->icount > 0);
}
-void sh3be_device::execute_run()
-{
- if (m_isdrc)
- {
- execute_run_drc();
- return;
- }
-
- if (m_sh2_state->m_cpu_off)
- {
- debugger_wait_hook();
- m_sh2_state->icount = 0;
- return;
- }
-
- do
- {
- m_sh2_state->m_ppc = m_sh2_state->pc & SH34_AM;
- debugger_instruction_hook(m_sh2_state->pc & SH34_AM);
-
- const uint16_t opcode = m_pr16(m_sh2_state->pc & SH34_AM);
-
- if (m_sh2_state->m_delay)
- {
- m_sh2_state->pc = m_sh2_state->m_delay;
- m_sh2_state->m_delay = 0;
- }
- else
- m_sh2_state->pc += 2;
-
- execute_one(opcode);
-
- if (m_sh2_state->m_test_irq && !m_sh2_state->m_delay)
- {
- sh4_check_pending_irq("mame_sh4_execute");
- }
-
- m_sh2_state->icount--;
- } while (m_sh2_state->icount > 0);
-}
-
-void sh4be_device::execute_run()
+void sh3_base_device::device_start()
{
- if (m_isdrc)
- {
- execute_run_drc();
- return;
- }
-
- if (m_sh2_state->m_cpu_off)
- {
- debugger_wait_hook();
- m_sh2_state->icount = 0;
- return;
- }
-
- do
- {
- m_sh2_state->m_ppc = m_sh2_state->pc & SH34_AM;
- debugger_instruction_hook(m_sh2_state->pc & SH34_AM);
-
- const uint16_t opcode = m_pr16(m_sh2_state->pc & SH34_AM);
-
- if (m_sh2_state->m_delay)
- {
- m_sh2_state->pc = m_sh2_state->m_delay;
- m_sh2_state->m_delay = 0;
- }
- else
- m_sh2_state->pc += 2;
-
- execute_one(opcode);
-
- if (m_sh2_state->m_test_irq && !m_sh2_state->m_delay)
- {
- sh4_check_pending_irq("mame_sh4_execute");
- }
+ sh34_base_device::device_start();
- m_sh2_state->icount--;
- } while (m_sh2_state->icount > 0);
+ // UBC
+ m_bara = 0;
+ m_bamra = 0;
+ m_bbra = 0;
+ m_barb = 0;
+ m_bamrb = 0;
+ m_bbrb = 0;
+ m_bdrb = 0;
+ m_bdmrb = 0;
+ m_brcr = 0;
+
+ // UBC 7709S
+ m_betr = 0;
+ m_brsr = 0;
+ m_brdr = 0;
+
+ // CPG
+ m_frqcr = 0x0102;
+ m_wtcnt = 0;
+ m_wtcsr = 0;
+ m_stbcr = 0;
+
+ // CPG 7709
+ m_stbcr2 = 0;
+
+ // BSC
+ m_bcr1 = 0;
+ m_bcr2 = 0x3ff0;
+ m_wcr1 = 0x3ff3;
+ m_wcr2 = 0xffff;
+ m_mcr = 0;
+ m_pcr = 0;
+ m_rtcsr = 0;
+ m_rtcnt = 0;
+ m_rtcor = 0;
+ m_rfcr = 0;
+
+ // BSC 7708
+ m_dcr = 0;
+ m_pctr = 0;
+ m_pdtr = 0;
+
+ // BSC 7709
+ m_bcr3 = 0;
+
+ // BSC 7709S
+ m_mcscr0 = 0;
+ m_mcscr1 = 0;
+ m_mcscr2 = 0;
+ m_mcscr3 = 0;
+ m_mcscr4 = 0;
+ m_mcscr5 = 0;
+ m_mcscr6 = 0;
+ m_mcscr7 = 0;
+
+ // RTC
+ m_r64cnt = 0;
+ m_rseccnt = 0;
+ m_rmincnt = 0;
+ m_rhrcnt = 0;
+ m_rwkcnt = 0;
+ m_rmoncnt = 0;
+ m_rdaycnt = 0;
+ m_ryrcnt = 0;
+ m_rsecar = 0;
+ m_rminar = 0;
+ m_rhrar = 0;
+ m_rwkar = 0;
+ m_rdayar = 0;
+ m_rmonar = 0;
+ m_rcr1 = 0;
+ m_rcr2 = 0x09;
+
+ // INTC
+ m_icr0 = 0;
+
+ // UBC
+ save_item(NAME(m_bara));
+ save_item(NAME(m_bamra));
+ save_item(NAME(m_bbra));
+ save_item(NAME(m_barb));
+ save_item(NAME(m_bamrb));
+ save_item(NAME(m_bbrb));
+ save_item(NAME(m_bdrb));
+ save_item(NAME(m_bdmrb));
+ save_item(NAME(m_brcr));
+
+ // UBC 7709S
+ save_item(NAME(m_betr));
+ save_item(NAME(m_brsr));
+ save_item(NAME(m_brdr));
+
+ // CPG
+ save_item(NAME(m_frqcr));
+ save_item(NAME(m_stbcr));
+ save_item(NAME(m_wtcnt));
+ save_item(NAME(m_wtcsr));
+
+ // CPG 7709
+ save_item(NAME(m_stbcr2));
+
+ // BSC
+ save_item(NAME(m_bcr1));
+ save_item(NAME(m_bcr2));
+ save_item(NAME(m_wcr1));
+ save_item(NAME(m_wcr2));
+ save_item(NAME(m_mcr));
+ save_item(NAME(m_pcr));
+ save_item(NAME(m_rtcsr));
+ save_item(NAME(m_rtcnt));
+ save_item(NAME(m_rtcor));
+ save_item(NAME(m_rfcr));
+
+ // BSC 7708
+ save_item(NAME(m_dcr));
+ save_item(NAME(m_pctr));
+ save_item(NAME(m_pdtr));
+
+ // BSC 7709
+ save_item(NAME(m_bcr3));
+
+ // BSC 7709S
+ save_item(NAME(m_mcscr0));
+ save_item(NAME(m_mcscr1));
+ save_item(NAME(m_mcscr2));
+ save_item(NAME(m_mcscr3));
+ save_item(NAME(m_mcscr4));
+ save_item(NAME(m_mcscr5));
+ save_item(NAME(m_mcscr6));
+ save_item(NAME(m_mcscr7));
+
+ // RTC
+ save_item(NAME(m_r64cnt));
+ save_item(NAME(m_rseccnt));
+ save_item(NAME(m_rmincnt));
+ save_item(NAME(m_rhrcnt));
+ save_item(NAME(m_rwkcnt));
+ save_item(NAME(m_rmoncnt));
+ save_item(NAME(m_rdaycnt));
+ save_item(NAME(m_ryrcnt));
+ save_item(NAME(m_rsecar));
+ save_item(NAME(m_rminar));
+ save_item(NAME(m_rhrar));
+ save_item(NAME(m_rwkar));
+ save_item(NAME(m_rdayar));
+ save_item(NAME(m_rmonar));
+ save_item(NAME(m_rcr1));
+ save_item(NAME(m_rcr2));
+
+ // INTC
+ save_item(NAME(m_icr0));
+ save_item(NAME(m_iprb));
+
+ // INTC 7709
+ save_item(NAME(m_irr0));
+ save_item(NAME(m_irr1));
+ save_item(NAME(m_irr2));
+ save_item(NAME(m_icr1));
+ save_item(NAME(m_icr2));
+ save_item(NAME(m_pinter));
+ save_item(NAME(m_iprd));
+ save_item(NAME(m_ipre));
+
+ // SCI
+ save_item(NAME(m_scsmr));
+ save_item(NAME(m_scbrr));
+ save_item(NAME(m_scscr));
+ save_item(NAME(m_sctdr));
+ save_item(NAME(m_scssr));
+ save_item(NAME(m_scrdr));
+ save_item(NAME(m_scscmr));
+
+ // SCI 7709
+ save_item(NAME(m_scsptr));
+
+ // CMT 7709
+ save_item(NAME(m_cmstr));
+ save_item(NAME(m_cmscr));
+ save_item(NAME(m_cmcnt));
+ save_item(NAME(m_cmcor));
+
+ // AD 7709
+ save_item(NAME(m_addrah));
+ save_item(NAME(m_addral));
+ save_item(NAME(m_addrbh));
+ save_item(NAME(m_addrbl));
+ save_item(NAME(m_addrch));
+ save_item(NAME(m_addrcl));
+ save_item(NAME(m_addrdh));
+ save_item(NAME(m_addrdl));
+ save_item(NAME(m_adcsr));
+ save_item(NAME(m_adcr));
+
+ // DA 7709
+ save_item(NAME(m_dadr0));
+ save_item(NAME(m_dadr1));
+ save_item(NAME(m_dadcr));
+
+ // PORT 7709
+ save_item(NAME(m_pacr));
+ save_item(NAME(m_pbcr));
+ save_item(NAME(m_pccr));
+ save_item(NAME(m_pdcr));
+ save_item(NAME(m_pecr));
+ save_item(NAME(m_pfcr));
+ save_item(NAME(m_pgcr));
+ save_item(NAME(m_phcr));
+ save_item(NAME(m_pjcr));
+ save_item(NAME(m_pkcr));
+ save_item(NAME(m_plcr));
+ save_item(NAME(m_scpcr));
+ save_item(NAME(m_padr));
+ save_item(NAME(m_pbdr));
+ save_item(NAME(m_pcdr));
+ save_item(NAME(m_pddr));
+ save_item(NAME(m_pedr));
+ save_item(NAME(m_pfdr));
+ save_item(NAME(m_pgdr));
+ save_item(NAME(m_phdr));
+ save_item(NAME(m_pjdr));
+ save_item(NAME(m_pkdr));
+ save_item(NAME(m_pldr));
+ save_item(NAME(m_scpdr));
+
+ // IRDA 7709
+ save_item(NAME(m_scsmr1));
+ save_item(NAME(m_scbrr1));
+ save_item(NAME(m_scscr1));
+ save_item(NAME(m_scftdr1));
+ save_item(NAME(m_scssr1));
+ save_item(NAME(m_scfrdr1));
+ save_item(NAME(m_scfcr1));
+ save_item(NAME(m_scfdr1));
+
+ // SCIF 7709
+ save_item(NAME(m_scsmr2));
+ save_item(NAME(m_scbrr2));
+ save_item(NAME(m_scscr2));
+ save_item(NAME(m_scftdr2));
+ save_item(NAME(m_scssr2));
+ save_item(NAME(m_scfrdr2));
+ save_item(NAME(m_scfcr2));
+ save_item(NAME(m_scfdr2));
+
+ // UDI 7709S
+ save_item(NAME(m_sdir));
}
void sh4_base_device::device_start()
{
sh34_base_device::device_start();
+ m_rtc_timer = timer_alloc(FUNC(sh4_base_device::sh4_rtc_timer_callback), this);
+ m_refresh_timer = timer_alloc(FUNC(sh4_base_device::sh4_refresh_timer_callback), this);
+
int i;
for (i = 0;i < 64;i++)
{
@@ -2097,6 +3295,156 @@ void sh4_base_device::device_start()
m_utlb[i].TC = 0;
}
+ // UBC
+ m_bara = 0;
+ m_bamra = 0;
+ m_bbra = 0;
+ m_barb = 0;
+ m_bamrb = 0;
+ m_bbrb = 0;
+ m_bdrb = 0;
+ m_bdmrb = 0;
+ m_brcr = 0;
+
+ // BSC
+ m_bcr1 = 0;
+ m_bcr2 = 0;
+ m_wcr1 = 0;
+ m_wcr2 = 0;
+ m_wcr3 = 0;
+ m_mcr = 0;
+ m_pcr = 0;
+ m_rtcsr = 0;
+ m_rtcnt = 0;
+ m_rtcor = 0;
+ m_rfcr = 0;
+ m_pctra = 0;
+ m_pdtra = 0;
+ m_pctrb = 0;
+ m_pdtrb = 0;
+ m_gpioic = 0;
+
+ // BSC 7750R
+ m_bcr3 = 0;
+ m_bcr4 = 0;
+
+ // CPG
+ m_frqcr = 0;
+ m_stbcr = 0;
+ m_wtcnt = 0;
+ m_wtcsr = 0;
+ m_stbcr2 = 0;
+
+ // RTC
+ m_r64cnt = 0;
+ m_rseccnt = 0;
+ m_rmincnt = 0;
+ m_rhrcnt = 0;
+ m_rwkcnt = 0;
+ m_rmoncnt = 0;
+ m_rdaycnt = 0;
+ m_ryrcnt = 0;
+ m_rsecar = 0;
+ m_rminar = 0;
+ m_rhrar = 0;
+ m_rwkar = 0;
+ m_rdayar = 0;
+ m_rmonar = 0;
+ m_rcr1 = 0;
+ m_rcr2 = 0x09;
+
+ // RTC 7750R
+ m_rcr3 = 0;
+ m_ryrar = 0;
+
+ // INTC 7750R
+ m_intpri00 = 0;
+ m_intreq00 = 0;
+ m_intmsk00 = 0x000003ff;
+
+ // CPG 7750R
+ m_clkstp00 = 0;
+
+ // TMU 7750R
+ m_tstr2 = 0;
+ m_tcor3 = 0xffffffff;
+ m_tcnt3 = 0xffffffff;
+ m_tcr3 = 0;
+ m_tcor4 = 0xffffffff;
+ m_tcnt4 = 0xffffffff;
+ m_tcr4 = 0;
+
+ // PCI 7751
+ m_pciconf1 = 0x02900080;
+ m_pciconf2 = 0;
+ m_pciconf3 = 0;
+ m_pciconf4 = 1;
+ m_pciconf5 = 0;
+ m_pciconf6 = 0;
+ m_pciconf7 = 0;
+ m_pciconf8 = 0;
+ m_pciconf9 = 0;
+ m_pciconf10 = 0;
+ m_pciconf11 = 0;
+ m_pciconf12 = 0;
+ m_pciconf13 = 0x00000040;
+ m_pciconf14 = 0;
+ m_pciconf15 = 0x00000100;
+ m_pciconf16 = 0x00010001;
+ m_pciconf17 = 0;
+ m_pcicr = 0;
+ m_pcilsr0 = 0;
+ m_pcilsr1 = 0;
+ m_pcilar0 = 0;
+ m_pcilar1 = 0;
+ m_pciint = 0;
+ m_pciintm = 0;
+ m_pcialr = 0;
+ m_pciclr = 0;
+ m_pciaint = 0;
+ m_pciaintm = 0;
+ m_pcibllr = 0;
+ m_pcidmabt = 0;
+ m_pcidpa0 = 0;
+ m_pcidla0 = 0;
+ m_pcidtc0 = 0;
+ m_pcidcr0 = 0;
+ m_pcidpa1 = 0;
+ m_pcidla1 = 0;
+ m_pcidtc1 = 0;
+ m_pcidcr1 = 0;
+ m_pcidpa2 = 0;
+ m_pcidla2 = 0;
+ m_pcidtc2 = 0;
+ m_pcidcr2 = 0;
+ m_pcidpa3 = 0;
+ m_pcidla3 = 0;
+ m_pcidtc3 = 0;
+ m_pcidcr3 = 0;
+ m_pcipar = 0;
+ m_pcimbr = 0;
+ m_pciiobr = 0;
+ m_pcipint = 0;
+ m_pcipintm = 0;
+ m_pciclkr = 0;
+ m_pcibcr1 = 0;
+ m_pcibcr2 = 0x00003ffc;
+ m_pcibcr3 = 1;
+ m_pciwcr1 = 0x77777777;
+ m_pciwcr2 = 0xfffeefff;
+ m_pciwcr3 = 0x07777777;
+ m_pcimcr = 0;
+ m_pcipctr = 0;
+ m_pcipdtr = 0;
+ m_pcipdr = 0;
+
+ // H-UDI
+ m_sdir = 0xffff;
+ m_sddr = 0;
+ m_sdint = 0;
+
+ save_item(NAME(m_refresh_timer_base));
+
for (i = 0;i < 64;i++)
{
save_item(NAME(m_utlb[i].ASID), i);
@@ -2112,6 +3460,201 @@ void sh4_base_device::device_start()
save_item(NAME(m_utlb[i].SA), i);
save_item(NAME(m_utlb[i].TC), i);
}
+
+ // UBC
+ save_item(NAME(m_bara));
+ save_item(NAME(m_bamra));
+ save_item(NAME(m_bbra));
+ save_item(NAME(m_barb));
+ save_item(NAME(m_bamrb));
+ save_item(NAME(m_bbrb));
+ save_item(NAME(m_bdrb));
+ save_item(NAME(m_bdmrb));
+ save_item(NAME(m_brcr));
+
+ // BSC
+ save_item(NAME(m_bcr1));
+ save_item(NAME(m_bcr2));
+ save_item(NAME(m_wcr1));
+ save_item(NAME(m_wcr2));
+ save_item(NAME(m_wcr3));
+ save_item(NAME(m_mcr));
+ save_item(NAME(m_pcr));
+ save_item(NAME(m_rtcsr));
+ save_item(NAME(m_rtcnt));
+ save_item(NAME(m_rtcor));
+ save_item(NAME(m_rfcr));
+ save_item(NAME(m_pctra));
+ save_item(NAME(m_pdtra));
+ save_item(NAME(m_pctrb));
+ save_item(NAME(m_pdtrb));
+ save_item(NAME(m_gpioic));
+
+ // BSC 7750R
+ save_item(NAME(m_bcr3));
+ save_item(NAME(m_bcr4));
+
+ // DMAC 7750R
+ save_item(NAME(m_sar4));
+ save_item(NAME(m_dar4));
+ save_item(NAME(m_dmatcr4));
+ save_item(NAME(m_chcr4));
+ save_item(NAME(m_sar5));
+ save_item(NAME(m_dar5));
+ save_item(NAME(m_dmatcr5));
+ save_item(NAME(m_chcr5));
+ save_item(NAME(m_sar6));
+ save_item(NAME(m_dar6));
+ save_item(NAME(m_dmatcr6));
+ save_item(NAME(m_chcr6));
+ save_item(NAME(m_sar7));
+ save_item(NAME(m_dar7));
+ save_item(NAME(m_dmatcr7));
+ save_item(NAME(m_chcr7));
+
+ // CPG
+ save_item(NAME(m_frqcr));
+ save_item(NAME(m_stbcr));
+ save_item(NAME(m_wtcnt));
+ save_item(NAME(m_wtcsr));
+ save_item(NAME(m_stbcr2));
+
+ // CPG 7750R
+ save_item(NAME(m_clkstp00));
+
+ // RTC
+ save_item(NAME(m_r64cnt));
+ save_item(NAME(m_rseccnt));
+ save_item(NAME(m_rmincnt));
+ save_item(NAME(m_rhrcnt));
+ save_item(NAME(m_rwkcnt));
+ save_item(NAME(m_rmoncnt));
+ save_item(NAME(m_rdaycnt));
+ save_item(NAME(m_ryrcnt));
+ save_item(NAME(m_rsecar));
+ save_item(NAME(m_rminar));
+ save_item(NAME(m_rhrar));
+ save_item(NAME(m_rwkar));
+ save_item(NAME(m_rdayar));
+ save_item(NAME(m_rmonar));
+ save_item(NAME(m_rcr1));
+ save_item(NAME(m_rcr2));
+
+ // INTC
+ save_item(NAME(m_iprb));
+
+ // INTC 7750S
+ save_item(NAME(m_iprd));
+
+ // INTC 7750R
+ save_item(NAME(m_intpri00));
+ save_item(NAME(m_intreq00));
+ save_item(NAME(m_intmsk00));
+
+ // TMU 7750R
+ save_item(NAME(m_tstr2));
+ save_item(NAME(m_tcor3));
+ save_item(NAME(m_tcnt3));
+ save_item(NAME(m_tcr3));
+ save_item(NAME(m_tcor4));
+ save_item(NAME(m_tcnt4));
+ save_item(NAME(m_tcr4));
+
+ // RTC 7750R
+ save_item(NAME(m_rcr3));
+ save_item(NAME(m_ryrar));
+
+ // SCI
+ save_item(NAME(m_scsmr1));
+ save_item(NAME(m_scbrr1));
+ save_item(NAME(m_scscr1));
+ save_item(NAME(m_sctdr1));
+ save_item(NAME(m_scssr1));
+ save_item(NAME(m_scrdr1));
+ save_item(NAME(m_scscmr1));
+ save_item(NAME(m_scsptr1));
+
+ // SCIF
+ save_item(NAME(m_scsmr2));
+ save_item(NAME(m_scbrr2));
+ save_item(NAME(m_scscr2));
+ save_item(NAME(m_scftdr2));
+ save_item(NAME(m_scfsr2));
+ save_item(NAME(m_scfrdr2));
+ save_item(NAME(m_scfcr2));
+ save_item(NAME(m_scfdr2));
+ save_item(NAME(m_scsptr2));
+ save_item(NAME(m_sclsr2));
+
+ // H-UDI
+ save_item(NAME(m_sdir));
+ save_item(NAME(m_sddr));
+ save_item(NAME(m_sdint));
+
+ // PCI 7751
+ save_item(NAME(m_pciconf0));
+ save_item(NAME(m_pciconf1));
+ save_item(NAME(m_pciconf2));
+ save_item(NAME(m_pciconf3));
+ save_item(NAME(m_pciconf4));
+ save_item(NAME(m_pciconf5));
+ save_item(NAME(m_pciconf6));
+ save_item(NAME(m_pciconf7));
+ save_item(NAME(m_pciconf8));
+ save_item(NAME(m_pciconf9));
+ save_item(NAME(m_pciconf10));
+ save_item(NAME(m_pciconf11));
+ save_item(NAME(m_pciconf12));
+ save_item(NAME(m_pciconf13));
+ save_item(NAME(m_pciconf14));
+ save_item(NAME(m_pciconf15));
+ save_item(NAME(m_pciconf16));
+ save_item(NAME(m_pciconf17));
+ save_item(NAME(m_pcicr));
+ save_item(NAME(m_pcilsr0));
+ save_item(NAME(m_pcilsr1));
+ save_item(NAME(m_pcilar0));
+ save_item(NAME(m_pcilar1));
+ save_item(NAME(m_pciint));
+ save_item(NAME(m_pciintm));
+ save_item(NAME(m_pcialr));
+ save_item(NAME(m_pciclr));
+ save_item(NAME(m_pciaint));
+ save_item(NAME(m_pciaintm));
+ save_item(NAME(m_pcibllr));
+ save_item(NAME(m_pcidmabt));
+ save_item(NAME(m_pcidpa0));
+ save_item(NAME(m_pcidla0));
+ save_item(NAME(m_pcidtc0));
+ save_item(NAME(m_pcidcr0));
+ save_item(NAME(m_pcidpa1));
+ save_item(NAME(m_pcidla1));
+ save_item(NAME(m_pcidtc1));
+ save_item(NAME(m_pcidcr1));
+ save_item(NAME(m_pcidpa2));
+ save_item(NAME(m_pcidla2));
+ save_item(NAME(m_pcidtc2));
+ save_item(NAME(m_pcidcr2));
+ save_item(NAME(m_pcidpa3));
+ save_item(NAME(m_pcidla3));
+ save_item(NAME(m_pcidtc3));
+ save_item(NAME(m_pcidcr3));
+ save_item(NAME(m_pcipar));
+ save_item(NAME(m_pcimbr));
+ save_item(NAME(m_pciiobr));
+ save_item(NAME(m_pcipint));
+ save_item(NAME(m_pcipintm));
+ save_item(NAME(m_pciclkr));
+ save_item(NAME(m_pcibcr1));
+ save_item(NAME(m_pcibcr2));
+ save_item(NAME(m_pcibcr3));
+ save_item(NAME(m_pciwcr1));
+ save_item(NAME(m_pciwcr2));
+ save_item(NAME(m_pciwcr3));
+ save_item(NAME(m_pcimcr));
+ save_item(NAME(m_pcipctr));
+ save_item(NAME(m_pcipdtr));
+ save_item(NAME(m_pcipdr));
}
@@ -2134,13 +3677,6 @@ void sh34_base_device::device_start()
m_dma_timer[i]->adjust(attotime::never, i);
}
- m_refresh_timer = timer_alloc(FUNC(sh34_base_device::sh4_refresh_timer_callback), this);
- m_refresh_timer->adjust(attotime::never);
- m_refresh_timer_base = 0;
-
- m_rtc_timer = timer_alloc(FUNC(sh34_base_device::sh4_rtc_timer_callback), this);
- m_rtc_timer->adjust(attotime::never);
-
sh4_parse_configuration();
m_internal = &space(AS_PROGRAM);
@@ -2202,41 +3738,80 @@ void sh34_base_device::device_start()
save_item(NAME(m_exception_priority));
save_item(NAME(m_exception_requesting));
save_item(NAME(m_irq_line_state));
- save_item(NAME(m_m));
- save_item(NAME(m_SH4_TSTR));
- save_item(NAME(m_SH4_TCNT0));
- save_item(NAME(m_SH4_TCNT1));
- save_item(NAME(m_SH4_TCNT2));
- save_item(NAME(m_SH4_TCR0));
- save_item(NAME(m_SH4_TCR1));
- save_item(NAME(m_SH4_TCR2));
- save_item(NAME(m_SH4_TCOR0));
- save_item(NAME(m_SH4_TCOR1));
- save_item(NAME(m_SH4_TCOR2));
- save_item(NAME(m_SH4_TOCR));
- save_item(NAME(m_SH4_TCPR2));
- save_item(NAME(m_SH4_IPRA));
- save_item(NAME(m_SH4_IPRC));
- save_item(NAME(m_SH4_DAR0));
- save_item(NAME(m_SH4_DAR1));
- save_item(NAME(m_SH4_DAR2));
- save_item(NAME(m_SH4_DAR3));
- save_item(NAME(m_SH4_CHCR0));
- save_item(NAME(m_SH4_CHCR1));
- save_item(NAME(m_SH4_CHCR2));
- save_item(NAME(m_SH4_CHCR3));
- save_item(NAME(m_SH4_DMATCR0));
- save_item(NAME(m_SH4_DMATCR1));
- save_item(NAME(m_SH4_DMATCR2));
- save_item(NAME(m_SH4_DMATCR3));
- save_item(NAME(m_SH4_DMAOR));
+
+ // CCN
+ m_tea = 0;
+ m_basra = 0;
+ m_basrb = 0;
+
+ // CCN
+ save_item(NAME(m_pteh));
+ save_item(NAME(m_ptel));
+ save_item(NAME(m_ttb));
+ save_item(NAME(m_tea));
+ save_item(NAME(m_mmucr));
+ save_item(NAME(m_basra));
+ save_item(NAME(m_basrb));
+ save_item(NAME(m_ccr));
+ save_item(NAME(m_tra));
+ save_item(NAME(m_expevt));
+ save_item(NAME(m_intevt));
+
+ // CCN 7709S
+ save_item(NAME(m_ccr2));
+
+ // CCN 7091
+ save_item(NAME(m_ptea));
+ save_item(NAME(m_qacr0));
+ save_item(NAME(m_qacr1));
+
+ // TMU
+ save_item(NAME(m_tocr));
+ save_item(NAME(m_tstr));
+ save_item(NAME(m_tcor0));
+ save_item(NAME(m_tcnt0));
+ save_item(NAME(m_tcr0));
+ save_item(NAME(m_tcor1));
+ save_item(NAME(m_tcnt1));
+ save_item(NAME(m_tcr1));
+ save_item(NAME(m_tcor2));
+ save_item(NAME(m_tcnt2));
+ save_item(NAME(m_tcr2));
+ save_item(NAME(m_tcpr2));
+
+ // INTC
+ save_item(NAME(m_icr));
+ save_item(NAME(m_ipra));
+ save_item(NAME(m_iprc));
+
+ // INTC 7709
+ save_item(NAME(m_intevt2));
+
+ // DMAC
+ save_item(NAME(m_sar0));
+ save_item(NAME(m_sar1));
+ save_item(NAME(m_sar2));
+ save_item(NAME(m_sar3));
+ save_item(NAME(m_dar0));
+ save_item(NAME(m_dar1));
+ save_item(NAME(m_dar2));
+ save_item(NAME(m_dar3));
+ save_item(NAME(m_chcr0));
+ save_item(NAME(m_chcr1));
+ save_item(NAME(m_chcr2));
+ save_item(NAME(m_chcr3));
+ save_item(NAME(m_dmatcr0));
+ save_item(NAME(m_dmatcr1));
+ save_item(NAME(m_dmatcr2));
+ save_item(NAME(m_dmatcr3));
+ save_item(NAME(m_dmaor));
+
save_item(NAME(m_nmi_line_state));
save_item(NAME(m_sh2_state->m_frt_input));
save_item(NAME(m_irln));
save_item(NAME(m_internal_irq_level));
save_item(NAME(m_internal_irq_vector));
- save_item(NAME(m_refresh_timer_base));
save_item(NAME(m_dma_timer_active));
save_item(NAME(m_dma_source));
save_item(NAME(m_dma_destination));
@@ -2254,8 +3829,6 @@ void sh34_base_device::device_start()
save_item(NAME(m_ioport4_pullup));
save_item(NAME(m_ioport4_direction));
save_item(NAME(m_sh4_mmu_enabled));
- save_item(NAME(m_sh3internal_upper));
- save_item(NAME(m_sh3internal_lower));
// Debugger state
@@ -2491,7 +4064,7 @@ void sh34_base_device::state_export(const device_state_entry &entry)
switch (entry.index())
{
case STATE_GENPC:
- m_debugger_temp = (m_sh2_state->pc & SH34_AM);
+ m_debugger_temp = m_sh2_state->pc;
break;
}
}
@@ -2657,43 +4230,23 @@ void sh34_base_device::sh4_set_ftcsr_callback(sh4_ftcsr_callback callback)
}
*/
-const opcode_desc* sh4be_device::get_desclist(offs_t pc)
-{
- return m_drcfe->describe_code(pc);
-}
-
-void sh4be_device::init_drc_frontend()
-{
- m_drcfe = std::make_unique<sh4be_frontend>(this, COMPILE_BACKWARDS_BYTES, COMPILE_FORWARDS_BYTES, SINGLE_INSTRUCTION_MODE ? 1 : COMPILE_MAX_SEQUENCE);
-}
-
-const opcode_desc* sh4_device::get_desclist(offs_t pc)
+const opcode_desc* sh4_base_device::get_desclist(offs_t pc)
{
return m_drcfe->describe_code(pc);
}
-void sh4_device::init_drc_frontend()
+void sh4_base_device::init_drc_frontend()
{
m_drcfe = std::make_unique<sh4_frontend>(this, COMPILE_BACKWARDS_BYTES, COMPILE_FORWARDS_BYTES, SINGLE_INSTRUCTION_MODE ? 1 : COMPILE_MAX_SEQUENCE);
}
-const opcode_desc* sh3be_device::get_desclist(offs_t pc)
-{
- return m_drcfe->describe_code(pc);
-}
-
-void sh3be_device::init_drc_frontend()
-{
- m_drcfe = std::make_unique<sh4be_frontend>(this, COMPILE_BACKWARDS_BYTES, COMPILE_FORWARDS_BYTES, SINGLE_INSTRUCTION_MODE ? 1 : COMPILE_MAX_SEQUENCE);
-}
-
-const opcode_desc* sh3_device::get_desclist(offs_t pc)
+const opcode_desc* sh3_base_device::get_desclist(offs_t pc)
{
return m_drcfe->describe_code(pc);
}
-void sh3_device::init_drc_frontend()
+void sh3_base_device::init_drc_frontend()
{
m_drcfe = std::make_unique<sh4_frontend>(this, COMPILE_BACKWARDS_BYTES, COMPILE_FORWARDS_BYTES, SINGLE_INSTRUCTION_MODE ? 1 : COMPILE_MAX_SEQUENCE);
}
diff --git a/src/devices/cpu/sh/sh4.h b/src/devices/cpu/sh/sh4.h
index cefe18843db..c4fc1c0cd1c 100644
--- a/src/devices/cpu/sh/sh4.h
+++ b/src/devices/cpu/sh/sh4.h
@@ -156,7 +156,6 @@ struct sh4_utlb
typedef void (*sh4_ftcsr_callback)(uint32_t);
class sh4_frontend;
-class sh4be_frontend;
class sh34_base_device : public sh_common_execution
{
@@ -168,8 +167,6 @@ public:
void set_mmu_hacktype(int hacktype) { m_mmuhack = hacktype; }
- TIMER_CALLBACK_MEMBER(sh4_refresh_timer_callback);
- TIMER_CALLBACK_MEMBER(sh4_rtc_timer_callback);
TIMER_CALLBACK_MEMBER(sh4_timer_callback);
TIMER_CALLBACK_MEMBER(sh4_dmac_callback);
@@ -269,6 +266,7 @@ protected:
// device_memory_interface overrides
virtual space_config_vector memory_space_config() const override;
+ virtual bool memory_translate(int spacenum, int intention, offs_t& address, address_space*& target_space) override;
// device_state_interface overrides
virtual void state_import(const device_state_entry &entry) override;
@@ -298,50 +296,67 @@ protected:
address_space *m_program;
address_space *m_io;
- // sh4 internal
- uint32_t m_m[16384];
-
- // timer regs handled manually for reuse
- uint32_t m_SH4_TSTR;
- uint32_t m_SH4_TCNT0;
- uint32_t m_SH4_TCNT1;
- uint32_t m_SH4_TCNT2;
- uint32_t m_SH4_TCR0;
- uint32_t m_SH4_TCR1;
- uint32_t m_SH4_TCR2;
- uint32_t m_SH4_TCOR0;
- uint32_t m_SH4_TCOR1;
- uint32_t m_SH4_TCOR2;
- uint32_t m_SH4_TOCR;
- uint32_t m_SH4_TCPR2;
-
- // INTC regs
- uint32_t m_SH4_IPRA;
-
- uint32_t m_SH4_IPRC;
-
- // DMAC regs
- uint32_t m_SH4_SAR0;
- uint32_t m_SH4_SAR1;
- uint32_t m_SH4_SAR2;
- uint32_t m_SH4_SAR3;
-
- uint32_t m_SH4_DAR0;
- uint32_t m_SH4_DAR1;
- uint32_t m_SH4_DAR2;
- uint32_t m_SH4_DAR3;
-
- uint32_t m_SH4_CHCR0;
- uint32_t m_SH4_CHCR1;
- uint32_t m_SH4_CHCR2;
- uint32_t m_SH4_CHCR3;
-
- uint32_t m_SH4_DMATCR0;
- uint32_t m_SH4_DMATCR1;
- uint32_t m_SH4_DMATCR2;
- uint32_t m_SH4_DMATCR3;
-
- uint32_t m_SH4_DMAOR;
+ // CCN
+ uint32_t m_pteh;
+ uint32_t m_ptel;
+ uint32_t m_ttb;
+ uint32_t m_tea;
+ uint32_t m_mmucr;
+ uint8_t m_basra;
+ uint8_t m_basrb;
+ uint32_t m_ccr;
+ uint32_t m_tra;
+ uint32_t m_expevt;
+ uint32_t m_intevt;
+
+ // CCN 7709S
+ uint32_t m_ccr2;
+
+ // CCN 7091
+ uint32_t m_ptea;
+ uint32_t m_qacr0;
+ uint32_t m_qacr1;
+
+ // TMU
+ uint8_t m_tocr;
+ uint8_t m_tstr;
+ uint32_t m_tcor0;
+ uint32_t m_tcnt0;
+ uint16_t m_tcr0;
+ uint32_t m_tcor1;
+ uint32_t m_tcnt1;
+ uint16_t m_tcr1;
+ uint32_t m_tcor2;
+ uint32_t m_tcnt2;
+ uint16_t m_tcr2;
+ uint32_t m_tcpr2;
+
+ // INTC
+ uint16_t m_icr;
+ uint16_t m_ipra;
+ uint16_t m_iprc;
+
+ // INTC 7709
+ uint32_t m_intevt2;
+
+ // DMAC
+ uint32_t m_sar0;
+ uint32_t m_dar0;
+ uint32_t m_dmatcr0;
+ uint32_t m_chcr0;
+ uint32_t m_sar1;
+ uint32_t m_dar1;
+ uint32_t m_dmatcr1;
+ uint32_t m_chcr1;
+ uint32_t m_sar2;
+ uint32_t m_dar2;
+ uint32_t m_dmatcr2;
+ uint32_t m_chcr2;
+ uint32_t m_sar3;
+ uint32_t m_dar3;
+ uint32_t m_dmatcr3;
+ uint32_t m_chcr3;
+ uint32_t m_dmaor;
int8_t m_nmi_line_state;
@@ -350,10 +365,7 @@ protected:
int m_internal_irq_vector;
emu_timer *m_dma_timer[4];
- emu_timer *m_refresh_timer;
- emu_timer *m_rtc_timer;
emu_timer *m_timer[3];
- uint32_t m_refresh_timer_base;
int m_dma_timer_active[4];
uint32_t m_dma_source[4];
uint32_t m_dma_destination[4];
@@ -378,10 +390,6 @@ protected:
bool m_sh4_mmu_enabled;
- // sh3 internal
- uint32_t m_sh3internal_upper[0x3000/4];
- uint32_t m_sh3internal_lower[0x1000];
-
uint64_t m_debugger_temp;
inline void sh4_check_pending_irq(const char *message) // look for highest priority active exception and handle it
@@ -418,76 +426,74 @@ protected:
void sh4_exception_checkunrequest(int exception);
void sh4_exception_process(int exception, uint32_t vector);
void sh4_exception(const char *message, int exception);
- uint32_t compute_ticks_refresh_timer(emu_timer *timer, int hertz, int base, int divisor);
- void sh4_refresh_timer_recompute();
- void increment_rtc_time(int mode);
void sh4_dmac_nmi();
- void sh4_handler_ipra_w(uint32_t data, uint32_t mem_mask);
+ uint16_t ipra_r(offs_t offset, uint16_t mem_mask);
+ void ipra_w(offs_t offset, uint16_t data, uint16_t mem_mask);
virtual uint32_t get_remap(uint32_t address);
virtual uint32_t sh4_getsqremap(uint32_t address);
void sh4_parse_configuration();
void sh4_timer_recompute(int which);
- uint32_t sh4_handle_tcnt0_addr_r(uint32_t mem_mask);
- uint32_t sh4_handle_tcnt1_addr_r(uint32_t mem_mask);
- uint32_t sh4_handle_tcnt2_addr_r(uint32_t mem_mask);
- uint32_t sh4_handle_tcor0_addr_r(uint32_t mem_mask);
- uint32_t sh4_handle_tcor1_addr_r(uint32_t mem_mask);
- uint32_t sh4_handle_tcor2_addr_r(uint32_t mem_mask);
- uint32_t sh4_handle_tcr0_addr_r(uint32_t mem_mask);
- uint32_t sh4_handle_tcr1_addr_r(uint32_t mem_mask);
- uint32_t sh4_handle_tcr2_addr_r(uint32_t mem_mask);
- uint32_t sh4_handle_tstr_addr_r(uint32_t mem_mask);
- uint32_t sh4_handle_tocr_addr_r(uint32_t mem_mask);
- uint32_t sh4_handle_tcpr2_addr_r(uint32_t mem_mask);
- void sh4_handle_tstr_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_tcr0_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_tcr1_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_tcr2_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_tcor0_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_tcor1_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_tcor2_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_tcnt0_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_tcnt1_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_tcnt2_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_tocr_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_tcpr2_addr_w(uint32_t data, uint32_t mem_mask);
+ uint8_t tocr_r(offs_t offset, uint8_t mem_mask);
+ void tocr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t tstr_r(offs_t offset, uint8_t mem_mask);
+ void tstr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint32_t tcor0_r(offs_t offset, uint32_t mem_mask);
+ void tcor0_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t tcnt0_r(offs_t offset, uint32_t mem_mask);
+ void tcnt0_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint16_t tcr0_r(offs_t offset, uint16_t mem_mask);
+ void tcr0_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint32_t tcor1_r(offs_t offset, uint32_t mem_mask);
+ void tcor1_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t tcnt1_r(offs_t offset, uint32_t mem_mask);
+ void tcnt1_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint16_t tcr1_r(offs_t offset, uint16_t mem_mask);
+ void tcr1_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint32_t tcor2_r(offs_t offset, uint32_t mem_mask);
+ void tcor2_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t tcnt2_r(offs_t offset, uint32_t mem_mask);
+ void tcnt2_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint16_t tcr2_r(offs_t offset, uint16_t mem_mask);
+ void tcr2_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint32_t tcpr2_r(offs_t offset, uint32_t mem_mask);
+ void tcpr2_w(offs_t offset, uint32_t data, uint32_t mem_mask);
int sh4_dma_transfer(int channel, int timermode, uint32_t chcr, uint32_t *sar, uint32_t *dar, uint32_t *dmatcr);
int sh4_dma_transfer_device(int channel, uint32_t chcr, uint32_t *sar, uint32_t *dar, uint32_t *dmatcr);
void sh4_dmac_check(int channel);
- void sh4_handle_sar0_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_sar1_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_sar2_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_sar3_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_dar0_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_dar1_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_dar2_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_dar3_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_dmatcr0_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_dmatcr1_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_dmatcr2_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_dmatcr3_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_chcr0_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_chcr1_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_chcr2_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_chcr3_addr_w(uint32_t data, uint32_t mem_mask);
- void sh4_handle_dmaor_addr_w(uint32_t data, uint32_t mem_mask);
- uint32_t sh4_handle_sar0_addr_r(uint32_t mem_mask) { return m_SH4_SAR0; }
- uint32_t sh4_handle_sar1_addr_r(uint32_t mem_mask) { return m_SH4_SAR1; }
- uint32_t sh4_handle_sar2_addr_r(uint32_t mem_mask) { return m_SH4_SAR2; }
- uint32_t sh4_handle_sar3_addr_r(uint32_t mem_mask) { return m_SH4_SAR3; }
- uint32_t sh4_handle_dar0_addr_r(uint32_t mem_mask) { return m_SH4_DAR0; }
- uint32_t sh4_handle_dar1_addr_r(uint32_t mem_mask) { return m_SH4_DAR1; }
- uint32_t sh4_handle_dar2_addr_r(uint32_t mem_mask) { return m_SH4_DAR2; }
- uint32_t sh4_handle_dar3_addr_r(uint32_t mem_mask) { return m_SH4_DAR3; }
- uint32_t sh4_handle_dmatcr0_addr_r(uint32_t mem_mask) { return m_SH4_DMATCR0; }
- uint32_t sh4_handle_dmatcr1_addr_r(uint32_t mem_mask) { return m_SH4_DMATCR1; }
- uint32_t sh4_handle_dmatcr2_addr_r(uint32_t mem_mask) { return m_SH4_DMATCR2; }
- uint32_t sh4_handle_dmatcr3_addr_r(uint32_t mem_mask) { return m_SH4_DMATCR3; }
- uint32_t sh4_handle_chcr0_addr_r(uint32_t mem_mask) { return m_SH4_CHCR0; }
- uint32_t sh4_handle_chcr1_addr_r(uint32_t mem_mask) { return m_SH4_CHCR1; }
- uint32_t sh4_handle_chcr2_addr_r(uint32_t mem_mask) { return m_SH4_CHCR2; }
- uint32_t sh4_handle_chcr3_addr_r(uint32_t mem_mask) { return m_SH4_CHCR3; }
- uint32_t sh4_handle_dmaor_addr_r(uint32_t mem_mask) { return m_SH4_DMAOR; }
+ uint32_t sar0_r(offs_t offset, uint32_t mem_mask);
+ void sar0_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t dar0_r(offs_t offset, uint32_t mem_mask);
+ void dar0_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t dmatcr0_r(offs_t offset, uint32_t mem_mask);
+ void dmatcr0_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t chcr0_r(offs_t offset, uint32_t mem_mask);
+ void chcr0_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t sar1_r(offs_t offset, uint32_t mem_mask);
+ void sar1_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t dar1_r(offs_t offset, uint32_t mem_mask);
+ void dar1_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t dmatcr1_r(offs_t offset, uint32_t mem_mask);
+ void dmatcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t chcr1_r(offs_t offset, uint32_t mem_mask);
+ void chcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t sar2_r(offs_t offset, uint32_t mem_mask);
+ void sar2_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t dar2_r(offs_t offset, uint32_t mem_mask);
+ void dar2_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t dmatcr2_r(offs_t offset, uint32_t mem_mask);
+ void dmatcr2_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t chcr2_r(offs_t offset, uint32_t mem_mask);
+ void chcr2_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t sar3_r(offs_t offset, uint32_t mem_mask);
+ void sar3_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t dar3_r(offs_t offset, uint32_t mem_mask);
+ void dar3_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t dmatcr3_r(offs_t offset, uint32_t mem_mask);
+ void dmatcr3_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t chcr3_r(offs_t offset, uint32_t mem_mask);
+ void chcr3_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t dmaor_r(offs_t offset, uint32_t mem_mask);
+ void dmaor_w(offs_t offset, uint32_t data, uint32_t mem_mask);
// memory handlers
virtual uint8_t read_byte(offs_t offset) override;
@@ -678,27 +684,592 @@ private:
class sh3_base_device : public sh34_base_device
{
-public:
- void sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
- uint32_t sh3_internal_r(offs_t offset, uint32_t mem_mask = ~0);
-
- void sh3_internal_high_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
- uint32_t sh3_internal_high_r(offs_t offset, uint32_t mem_mask = ~0);
+ friend class sh4_frontend;
- void sh3_internal_map(address_map &map) ATTR_COLD;
protected:
// construction/destruction
sh3_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, endianness_t endianness);
+ virtual void device_start() override ATTR_COLD;
virtual void device_reset() override ATTR_COLD;
+
+ void sh3_internal_map(address_map &map) ATTR_COLD;
+ virtual void sh3_register_map(address_map& map) ATTR_COLD {}
+
+ void ccn_map(address_map& map) ATTR_COLD;
+ void ccn_7709s_map(address_map& map) ATTR_COLD;
+ void ubc_map(address_map& map) ATTR_COLD;
+ void ubc_7709s_map(address_map& map) ATTR_COLD;
+ void cpg_map(address_map& map) ATTR_COLD;
+ void cpg_7709_map(address_map& map) ATTR_COLD;
+ void bsc_map(address_map& map) ATTR_COLD;
+ void bsc_7708_map(address_map& map) ATTR_COLD;
+ void bsc_7709_map(address_map& map) ATTR_COLD;
+ void bsc_7709s_map(address_map& map) ATTR_COLD;
+ void rtc_map(address_map& map) ATTR_COLD;
+ void intc_map(address_map& map) ATTR_COLD;
+ void intc_7709_map(address_map& map) ATTR_COLD;
+ void dmac_7709_map(address_map& map) ATTR_COLD;
+ void tmu_map(address_map& map) ATTR_COLD;
+ void sci_7708_map(address_map& map) ATTR_COLD;
+ void sci_7709_map(address_map& map) ATTR_COLD;
+ void cmt_7709_map(address_map& map) ATTR_COLD;
+ void ad_7709_map(address_map& map) ATTR_COLD;
+ void da_7709_map(address_map& map) ATTR_COLD;
+ void port_7709_map(address_map& map) ATTR_COLD;
+ void irda_7709_map(address_map& map) ATTR_COLD;
+ void scif_7709_map(address_map& map) ATTR_COLD;
+ void udi_7709s_map(address_map& map) ATTR_COLD;
+
+ // CCN
+ uint32_t pteh_r(offs_t offset, uint32_t mem_mask);
+ void pteh_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t ptel_r(offs_t offset, uint32_t mem_mask);
+ void ptel_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t ttb_r(offs_t offset, uint32_t mem_mask);
+ void ttb_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t tea_r(offs_t offset, uint32_t mem_mask);
+ void tea_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t mmucr_r(offs_t offset, uint32_t mem_mask);
+ void mmucr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint8_t basra_r(offs_t offset, uint8_t mem_mask);
+ void basra_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t basrb_r(offs_t offset, uint8_t mem_mask);
+ void basrb_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint32_t ccr_r(offs_t offset, uint32_t mem_mask);
+ void ccr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t tra_r(offs_t offset, uint32_t mem_mask);
+ void tra_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t expevt_r(offs_t offset, uint32_t mem_mask);
+ void expevt_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t intevt_r(offs_t offset, uint32_t mem_mask);
+ void intevt_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+
+ // CCN 7709S
+ uint32_t ccr2_r(offs_t offset, uint32_t mem_mask);
+ void ccr2_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+
+ // UBC
+ uint32_t bara_r(offs_t offset, uint32_t mem_mask);
+ void bara_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint8_t bamra_r(offs_t offset, uint8_t mem_mask);
+ void bamra_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint16_t bbra_r(offs_t offset, uint16_t mem_mask);
+ void bbra_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint32_t barb_r(offs_t offset, uint32_t mem_mask);
+ void barb_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint8_t bamrb_r(offs_t offset, uint8_t mem_mask);
+ void bamrb_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint16_t bbrb_r(offs_t offset, uint16_t mem_mask);
+ void bbrb_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint32_t bdrb_r(offs_t offset, uint32_t mem_mask);
+ void bdrb_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t bdmrb_r(offs_t offset, uint32_t mem_mask);
+ void bdmrb_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint16_t brcr_r(offs_t offset, uint16_t mem_mask);
+ void brcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+ // UBC 7709S
+ uint16_t betr_r(offs_t offset, uint16_t mem_mask);
+ void betr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint32_t brsr_r(offs_t offset, uint32_t mem_mask);
+ void brsr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t brdr_r(offs_t offset, uint32_t mem_mask);
+ void brdr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+
+ // CPG
+ uint16_t frqcr_r(offs_t offset, uint16_t mem_mask);
+ void frqcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint8_t stbcr_r(offs_t offset, uint8_t mem_mask);
+ void stbcr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t wtcnt_r(offs_t offset, uint8_t mem_mask);
+ void wtcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint8_t wtcsr_r(offs_t offset, uint8_t mem_mask);
+ void wtcsr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+ // CPG 7709
+ uint8_t stbcr2_r(offs_t offset, uint8_t mem_mask);
+ void stbcr2_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+
+ // BSC
+ uint16_t bcr1_r(offs_t offset, uint16_t mem_mask);
+ void bcr1_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t bcr2_r(offs_t offset, uint16_t mem_mask);
+ void bcr2_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t wcr1_r(offs_t offset, uint16_t mem_mask);
+ void wcr1_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t wcr2_r(offs_t offset, uint16_t mem_mask);
+ void wcr2_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t mcr_r(offs_t offset, uint16_t mem_mask);
+ void mcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t pcr_r(offs_t offset, uint16_t mem_mask);
+ void pcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t rtcsr_r(offs_t offset, uint16_t mem_mask);
+ void rtcsr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t rtcnt_r(offs_t offset, uint16_t mem_mask);
+ void rtcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t rtcor_r(offs_t offset, uint16_t mem_mask);
+ void rtcor_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t rfcr_r(offs_t offset, uint16_t mem_mask);
+ void rfcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint8_t sdmr_r(offs_t offset, uint8_t mem_mask);
+ void sdmr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+
+ // BSC 7708
+ uint16_t dcr_r(offs_t offset, uint16_t mem_mask);
+ void dcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t pctr_r(offs_t offset, uint16_t mem_mask);
+ void pctr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t pdtr_r(offs_t offset, uint16_t mem_mask);
+ void pdtr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+ // BSC 7709
+ uint16_t bcr3_r(offs_t offset, uint16_t mem_mask);
+ void bcr3_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+ // BSC 7709S
+ uint16_t mcscr0_r(offs_t offset, uint16_t mem_mask);
+ void mcscr0_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t mcscr1_r(offs_t offset, uint16_t mem_mask);
+ void mcscr1_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t mcscr2_r(offs_t offset, uint16_t mem_mask);
+ void mcscr2_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t mcscr3_r(offs_t offset, uint16_t mem_mask);
+ void mcscr3_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t mcscr4_r(offs_t offset, uint16_t mem_mask);
+ void mcscr4_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t mcscr5_r(offs_t offset, uint16_t mem_mask);
+ void mcscr5_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t mcscr6_r(offs_t offset, uint16_t mem_mask);
+ void mcscr6_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t mcscr7_r(offs_t offset, uint16_t mem_mask);
+ void mcscr7_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+ // RTC
+ uint8_t r64cnt_r(offs_t offset, uint8_t mem_mask);
+ uint8_t rseccnt_r(offs_t offset, uint8_t mem_mask);
+ void rseccnt_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rmincnt_r(offs_t offset, uint8_t mem_mask);
+ void rmincnt_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rhrcnt_r(offs_t offset, uint8_t mem_mask);
+ void rhrcnt_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rwkcnt_r(offs_t offset, uint8_t mem_mask);
+ void rwkcnt_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rdaycnt_r(offs_t offset, uint8_t mem_mask);
+ void rdaycnt_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rmoncnt_r(offs_t offset, uint8_t mem_mask);
+ void rmoncnt_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t ryrcnt_r(offs_t offset, uint8_t mem_mask);
+ void ryrcnt_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rsecar_r(offs_t offset, uint8_t mem_mask);
+ void rsecar_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rminar_r(offs_t offset, uint8_t mem_mask);
+ void rminar_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rhrar_r(offs_t offset, uint8_t mem_mask);
+ void rhrar_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rwkar_r(offs_t offset, uint8_t mem_mask);
+ void rwkar_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rdayar_r(offs_t offset, uint8_t mem_mask);
+ void rdayar_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rmonar_r(offs_t offset, uint8_t mem_mask);
+ void rmonar_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rcr1_r(offs_t offset, uint8_t mem_mask);
+ void rcr1_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rcr2_r(offs_t offset, uint8_t mem_mask);
+ void rcr2_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+
+ // INTC
+ uint16_t icr0_r(offs_t offset, uint16_t mem_mask);
+ void icr0_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t iprb_r(offs_t offset, uint16_t mem_mask);
+ void iprb_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+ // INTC 7709
+ uint32_t intevt2_r(offs_t offset, uint32_t mem_mask);
+ void intevt2_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint8_t irr0_r(offs_t offset, uint8_t mem_mask);
+ void irr0_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t irr1_r(offs_t offset, uint8_t mem_mask);
+ void irr1_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t irr2_r(offs_t offset, uint8_t mem_mask);
+ void irr2_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint16_t icr1_r(offs_t offset, uint16_t mem_mask);
+ void icr1_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t icr2_r(offs_t offset, uint16_t mem_mask);
+ void icr2_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t pinter_r(offs_t offset, uint16_t mem_mask);
+ void pinter_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t iprc_r(offs_t offset, uint16_t mem_mask);
+ void iprc_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t iprd_r(offs_t offset, uint16_t mem_mask);
+ void iprd_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t ipre_r(offs_t offset, uint16_t mem_mask);
+ void ipre_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+ // SCI
+ uint8_t scsmr_r(offs_t offset, uint8_t mem_mask);
+ void scsmr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scbrr_r(offs_t offset, uint8_t mem_mask);
+ void scbrr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scscr_r(offs_t offset, uint8_t mem_mask);
+ void scscr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t sctdr_r(offs_t offset, uint8_t mem_mask);
+ void sctdr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scssr_r(offs_t offset, uint8_t mem_mask);
+ void scssr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scrdr_r(offs_t offset, uint8_t mem_mask);
+ void scscmr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scscmr_r(offs_t offset, uint8_t mem_mask);
+
+ // SCI 7708
+ uint8_t scsptr_r(offs_t offset, uint8_t mem_mask);
+ void scsptr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+
+ // CMT 7709
+ uint16_t cmstr_r(offs_t offset, uint16_t mem_mask);
+ void cmstr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t cmscr_r(offs_t offset, uint16_t mem_mask);
+ void cmscr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t cmcnt_r(offs_t offset, uint16_t mem_mask);
+ void cmcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t cmcor_r(offs_t offset, uint16_t mem_mask);
+ void cmcor_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+ // AD 7709
+ uint8_t addrah_r(offs_t offset, uint8_t mem_mask);
+ void addrah_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t addral_r(offs_t offset, uint8_t mem_mask);
+ void addral_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t addrbh_r(offs_t offset, uint8_t mem_mask);
+ void addrbh_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t addrbl_r(offs_t offset, uint8_t mem_mask);
+ void addrbl_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t addrch_r(offs_t offset, uint8_t mem_mask);
+ void addrch_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t addrcl_r(offs_t offset, uint8_t mem_mask);
+ void addrcl_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t addrdh_r(offs_t offset, uint8_t mem_mask);
+ void addrdh_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t addrdl_r(offs_t offset, uint8_t mem_mask);
+ void addrdl_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t adcsr_r(offs_t offset, uint8_t mem_mask);
+ void adcsr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t adcr_r(offs_t offset, uint8_t mem_mask);
+ void adcr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+
+ // DA 7709
+ uint8_t dadr0_r(offs_t offset, uint8_t mem_mask);
+ void dadr0_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t dadr1_r(offs_t offset, uint8_t mem_mask);
+ void dadr1_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t dadcr_r(offs_t offset, uint8_t mem_mask);
+ void dadcr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+
+ // PORT 7709
+ uint16_t pacr_r(offs_t offset, uint16_t mem_mask);
+ void pacr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t pbcr_r(offs_t offset, uint16_t mem_mask);
+ void pbcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t pccr_r(offs_t offset, uint16_t mem_mask);
+ void pccr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t pdcr_r(offs_t offset, uint16_t mem_mask);
+ void pdcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t pecr_r(offs_t offset, uint16_t mem_mask);
+ void pecr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t pfcr_r(offs_t offset, uint16_t mem_mask);
+ void pfcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t pgcr_r(offs_t offset, uint16_t mem_mask);
+ void pgcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t phcr_r(offs_t offset, uint16_t mem_mask);
+ void phcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t pjcr_r(offs_t offset, uint16_t mem_mask);
+ void pjcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t pkcr_r(offs_t offset, uint16_t mem_mask);
+ void pkcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t plcr_r(offs_t offset, uint16_t mem_mask);
+ void plcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t scpcr_r(offs_t offset, uint16_t mem_mask);
+ void scpcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint8_t padr_r(offs_t offset, uint8_t mem_mask);
+ void padr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t pbdr_r(offs_t offset, uint8_t mem_mask);
+ void pbdr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t pcdr_r(offs_t offset, uint8_t mem_mask);
+ void pcdr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t pddr_r(offs_t offset, uint8_t mem_mask);
+ void pddr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t pedr_r(offs_t offset, uint8_t mem_mask);
+ void pedr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t pfdr_r(offs_t offset, uint8_t mem_mask);
+ void pfdr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t pgdr_r(offs_t offset, uint8_t mem_mask);
+ void pgdr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t phdr_r(offs_t offset, uint8_t mem_mask);
+ void phdr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t pjdr_r(offs_t offset, uint8_t mem_mask);
+ void pjdr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t pkdr_r(offs_t offset, uint8_t mem_mask);
+ void pkdr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t pldr_r(offs_t offset, uint8_t mem_mask);
+ void pldr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scpdr_r(offs_t offset, uint8_t mem_mask);
+ void scpdr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+
+ // IRDA 7709
+ uint8_t scsmr1_r(offs_t offset, uint8_t mem_mask);
+ void scsmr1_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scbrr1_r(offs_t offset, uint8_t mem_mask);
+ void scbrr1_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scscr1_r(offs_t offset, uint8_t mem_mask);
+ void scscr1_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scftdr1_r(offs_t offset, uint8_t mem_mask);
+ void scftdr1_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint16_t scssr1_r(offs_t offset, uint16_t mem_mask);
+ void scssr1_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint8_t scfrdr1_r(offs_t offset, uint8_t mem_mask);
+ void scfrdr1_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scfcr1_r(offs_t offset, uint8_t mem_mask);
+ void scfcr1_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint16_t scfdr1_r(offs_t offset, uint16_t mem_mask);
+ void scfdr1_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+ // SCIF 7709
+ uint8_t scsmr2_r(offs_t offset, uint8_t mem_mask);
+ void scsmr2_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scbrr2_r(offs_t offset, uint8_t mem_mask);
+ void scbrr2_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scscr2_r(offs_t offset, uint8_t mem_mask);
+ void scscr2_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scftdr2_r(offs_t offset, uint8_t mem_mask);
+ void scftdr2_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint16_t scssr2_r(offs_t offset, uint16_t mem_mask);
+ void scssr2_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint8_t scfrdr2_r(offs_t offset, uint8_t mem_mask);
+ void scfrdr2_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scfcr2_r(offs_t offset, uint8_t mem_mask);
+ void scfcr2_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint16_t scfdr2_r(offs_t offset, uint16_t mem_mask);
+ void scfdr2_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+ // UDI 7709S
+ uint16_t sdir_r(offs_t offset, uint16_t mem_mask);
+ void sdir_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+ std::unique_ptr<sh4_frontend> m_drcfe; /* pointer to the DRC front-end state */
+ virtual const opcode_desc* get_desclist(offs_t pc) override;
+ virtual void init_drc_frontend() override;
+
+ // UBC
+ uint32_t m_bara;
+ uint8_t m_bamra;
+ uint16_t m_bbra;
+ uint32_t m_barb;
+ uint8_t m_bamrb;
+ uint16_t m_bbrb;
+ uint32_t m_bdrb;
+ uint32_t m_bdmrb;
+ uint16_t m_brcr;
+
+ // UBC 7709S
+ uint16_t m_betr;
+ uint32_t m_brsr;
+ uint32_t m_brdr;
+
+ // CPG
+ uint16_t m_frqcr;
+ uint8_t m_stbcr;
+ uint16_t m_wtcnt;
+ uint16_t m_wtcsr;
+
+ // CPG 7709
+ uint8_t m_stbcr2;
+
+ // BSC
+ uint16_t m_bcr1;
+ uint16_t m_bcr2;
+ uint16_t m_wcr1;
+ uint16_t m_wcr2;
+ uint16_t m_mcr;
+ uint16_t m_pcr;
+ uint16_t m_rtcsr;
+ uint16_t m_rtcnt;
+ uint16_t m_rtcor;
+ uint16_t m_rfcr;
+
+ // BSC 7708
+ uint16_t m_dcr;
+ uint16_t m_pctr;
+ uint16_t m_pdtr;
+
+ // BSC 7709
+ uint16_t m_bcr3;
+
+ // BSC 7709S
+ uint16_t m_mcscr0;
+ uint16_t m_mcscr1;
+ uint16_t m_mcscr2;
+ uint16_t m_mcscr3;
+ uint16_t m_mcscr4;
+ uint16_t m_mcscr5;
+ uint16_t m_mcscr6;
+ uint16_t m_mcscr7;
+
+ // RTC
+ uint8_t m_r64cnt;
+ uint8_t m_rseccnt;
+ uint8_t m_rmincnt;
+ uint8_t m_rhrcnt;
+ uint8_t m_rwkcnt;
+ uint8_t m_rmoncnt;
+ uint8_t m_rdaycnt;
+ uint8_t m_ryrcnt;
+ uint8_t m_rsecar;
+ uint8_t m_rminar;
+ uint8_t m_rhrar;
+ uint8_t m_rwkar;
+ uint8_t m_rdayar;
+ uint8_t m_rmonar;
+ uint8_t m_rcr1;
+ uint8_t m_rcr2;
+
+ // INTC
+ uint16_t m_icr0;
+ uint16_t m_iprb;
+
+ // INTC 7709
+ uint8_t m_irr0;
+ uint8_t m_irr1;
+ uint8_t m_irr2;
+ uint16_t m_icr1;
+ uint16_t m_icr2;
+ uint16_t m_pinter;
+ uint16_t m_iprd;
+ uint16_t m_ipre;
+
+ // SCI
+ uint8_t m_scsmr;
+ uint8_t m_scbrr;
+ uint8_t m_scscr;
+ uint8_t m_sctdr;
+ uint8_t m_scssr;
+ uint8_t m_scrdr;
+ uint8_t m_scscmr;
+
+ // SCI 7709
+ uint8_t m_scsptr;
+
+ // CMT 7709
+ uint16_t m_cmstr;
+ uint16_t m_cmscr;
+ uint16_t m_cmcnt;
+ uint16_t m_cmcor;
+
+ // AD 7709
+ uint8_t m_addrah;
+ uint8_t m_addral;
+ uint8_t m_addrbh;
+ uint8_t m_addrbl;
+ uint8_t m_addrch;
+ uint8_t m_addrcl;
+ uint8_t m_addrdh;
+ uint8_t m_addrdl;
+ uint8_t m_adcsr;
+ uint8_t m_adcr;
+
+ // DA 7709
+ uint8_t m_dadr0;
+ uint8_t m_dadr1;
+ uint8_t m_dadcr;
+
+ // PORT 7709
+ uint16_t m_pacr;
+ uint16_t m_pbcr;
+ uint16_t m_pccr;
+ uint16_t m_pdcr;
+ uint16_t m_pecr;
+ uint16_t m_pfcr;
+ uint16_t m_pgcr;
+ uint16_t m_phcr;
+ uint16_t m_pjcr;
+ uint16_t m_pkcr;
+ uint16_t m_plcr;
+ uint16_t m_scpcr;
+ uint8_t m_padr;
+ uint8_t m_pbdr;
+ uint8_t m_pcdr;
+ uint8_t m_pddr;
+ uint8_t m_pedr;
+ uint8_t m_pfdr;
+ uint8_t m_pgdr;
+ uint8_t m_phdr;
+ uint8_t m_pjdr;
+ uint8_t m_pkdr;
+ uint8_t m_pldr;
+ uint8_t m_scpdr;
+
+ // IRDA 7709
+ uint8_t m_scsmr1;
+ uint8_t m_scbrr1;
+ uint8_t m_scscr1;
+ uint8_t m_scftdr1;
+ uint16_t m_scssr1;
+ uint8_t m_scfrdr1;
+ uint8_t m_scfcr1;
+ uint16_t m_scfdr1;
+
+ // SCIF 7709
+ uint8_t m_scsmr2;
+ uint8_t m_scbrr2;
+ uint8_t m_scscr2;
+ uint8_t m_scftdr2;
+ uint16_t m_scssr2;
+ uint16_t m_scfrdr2;
+ uint8_t m_scfcr2;
+ uint8_t m_scfdr2;
+
+ // UDI 7709S
+ uint16_t m_sdir;
};
class sh4_base_device : public sh34_base_device
{
-public:
- void sh4_internal_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
- uint32_t sh4_internal_r(offs_t offset, uint32_t mem_mask = ~0);
+protected:
+ friend class sh4_frontend;
+
+ // construction/destruction
+ sh4_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, endianness_t endianness);
+
+ virtual void device_start() override ATTR_COLD;
+ virtual void device_reset() override ATTR_COLD;
+
+ virtual void init_drc_frontend() override;
+ std::unique_ptr<sh4_frontend> m_drcfe; /* pointer to the DRC front-end state */
+ virtual const opcode_desc* get_desclist(offs_t pc) override;
+
+ void sh4_internal_map(address_map& map) ATTR_COLD;
+ virtual void sh4_register_map(address_map& map) ATTR_COLD {}
+
+ void ccn_map(address_map &map) ATTR_COLD;
+ void ubc_map(address_map& map) ATTR_COLD;
+ void bsc_map(address_map& map) ATTR_COLD;
+ void bsc_7750r_map(address_map& map) ATTR_COLD;
+ void dmac_map(address_map& map) ATTR_COLD;
+ void dmac_7750r_map(address_map& map) ATTR_COLD;
+ void cpg_map(address_map& map) ATTR_COLD;
+ void cpg_7750r_map(address_map& map) ATTR_COLD;
+ void rtc_map(address_map& map) ATTR_COLD;
+ void rtc_7750r_map(address_map& map) ATTR_COLD;
+ void intc_map(address_map& map) ATTR_COLD;
+ void intc_7750s_map(address_map& map) ATTR_COLD;
+ void intc_7750r_map(address_map& map) ATTR_COLD;
+ void tmu_map(address_map& map) ATTR_COLD;
+ void tmu_7750r_map(address_map& map) ATTR_COLD;
+ void sci_map(address_map &map) ATTR_COLD;
+ void scif_map(address_map &map) ATTR_COLD;
+ void hudi_map(address_map& map) ATTR_COLD;
+ void hudi_7750r_map(address_map& map) ATTR_COLD;
+ void pci_7751_map(address_map& map) ATTR_COLD;
uint64_t sh4_utlb_address_array_r(offs_t offset);
void sh4_utlb_address_array_w(offs_t offset, uint64_t data);
@@ -707,73 +1278,698 @@ public:
uint64_t sh4_utlb_data_array2_r(offs_t offset);
void sh4_utlb_data_array2_w(offs_t offset, uint64_t data);
+ // CCN
+ uint32_t pteh_r(offs_t offset, uint32_t mem_mask);
+ void pteh_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t ptel_r(offs_t offset, uint32_t mem_mask);
+ void ptel_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t ttb_r(offs_t offset, uint32_t mem_mask);
+ void ttb_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t tea_r(offs_t offset, uint32_t mem_mask);
+ void tea_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t mmucr_r(offs_t offset, uint32_t mem_mask);
+ void mmucr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint8_t basra_r(offs_t offset, uint8_t mem_mask);
+ void basra_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t basrb_r(offs_t offset, uint8_t mem_mask);
+ void basrb_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint32_t ccr_r(offs_t offset, uint32_t mem_mask);
+ void ccr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t tra_r(offs_t offset, uint32_t mem_mask);
+ void tra_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t expevt_r(offs_t offset, uint32_t mem_mask);
+ void expevt_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t intevt_r(offs_t offset, uint32_t mem_mask);
+ void intevt_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t ptea_r(offs_t offset, uint32_t mem_mask);
+ void ptea_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t qacr0_r(offs_t offset, uint32_t mem_mask);
+ void qacr0_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t qacr1_r(offs_t offset, uint32_t mem_mask);
+ void qacr1_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+
+ // UBC
+ uint32_t bara_r(offs_t offset, uint32_t mem_mask);
+ void bara_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint8_t bamra_r(offs_t offset, uint8_t mem_mask);
+ void bamra_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint16_t bbra_r(offs_t offset, uint16_t mem_mask);
+ void bbra_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint32_t barb_r(offs_t offset, uint32_t mem_mask);
+ void barb_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint8_t bamrb_r(offs_t offset, uint8_t mem_mask);
+ void bamrb_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint16_t bbrb_r(offs_t offset, uint16_t mem_mask);
+ void bbrb_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint32_t bdrb_r(offs_t offset, uint32_t mem_mask);
+ void bdrb_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t bdmrb_r(offs_t offset, uint32_t mem_mask);
+ void bdmrb_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint16_t brcr_r(offs_t offset, uint16_t mem_mask);
+ void brcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+ // BSC
+ uint32_t bcr1_r(offs_t offset, uint32_t mem_mask);
+ void bcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint16_t bcr2_r(offs_t offset, uint16_t mem_mask);
+ void bcr2_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint32_t wcr1_r(offs_t offset, uint32_t mem_mask);
+ void wcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t wcr2_r(offs_t offset, uint32_t mem_mask);
+ void wcr2_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t wcr3_r(offs_t offset, uint32_t mem_mask);
+ void wcr3_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t mcr_r(offs_t offset, uint32_t mem_mask);
+ void mcr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint16_t pcr_r(offs_t offset, uint16_t mem_mask);
+ void pcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t rtcsr_r(offs_t offset, uint16_t mem_mask);
+ void rtcsr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t rtcnt_r(offs_t offset, uint16_t mem_mask);
+ void rtcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t rtcor_r(offs_t offset, uint16_t mem_mask);
+ void rtcor_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t rfcr_r(offs_t offset, uint16_t mem_mask);
+ void rfcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint32_t pctra_r(offs_t offset, uint32_t mem_mask);
+ void pctra_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint16_t pdtra_r(offs_t offset, uint16_t mem_mask);
+ void pdtra_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint32_t pctrb_r(offs_t offset, uint32_t mem_mask);
+ void pctrb_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint16_t pdtrb_r(offs_t offset, uint16_t mem_mask);
+ void pdtrb_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t gpioic_r(offs_t offset, uint16_t mem_mask);
+ void gpioic_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ void sdmr2_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ void sdmr3_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+
+ // BSC 7750R
+ uint16_t bcr3_r(offs_t offset, uint16_t mem_mask);
+ void bcr3_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint32_t bcr4_r(offs_t offset, uint32_t mem_mask);
+ void bcr4_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+
+ // DMAC 7750R
+ uint32_t sar4_r(offs_t offset, uint32_t mem_mask);
+ void sar4_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t dar4_r(offs_t offset, uint32_t mem_mask);
+ void dar4_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t dmatcr4_r(offs_t offset, uint32_t mem_mask);
+ void dmatcr4_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t chcr4_r(offs_t offset, uint32_t mem_mask);
+ void chcr4_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t sar5_r(offs_t offset, uint32_t mem_mask);
+ void sar5_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t dar5_r(offs_t offset, uint32_t mem_mask);
+ void dar5_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t dmatcr5_r(offs_t offset, uint32_t mem_mask);
+ void dmatcr5_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t chcr5_r(offs_t offset, uint32_t mem_mask);
+ void chcr5_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t sar6_r(offs_t offset, uint32_t mem_mask);
+ void sar6_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t dar6_r(offs_t offset, uint32_t mem_mask);
+ void dar6_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t dmatcr6_r(offs_t offset, uint32_t mem_mask);
+ void dmatcr6_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t chcr6_r(offs_t offset, uint32_t mem_mask);
+ void chcr6_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t sar7_r(offs_t offset, uint32_t mem_mask);
+ void sar7_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t dar7_r(offs_t offset, uint32_t mem_mask);
+ void dar7_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t dmatcr7_r(offs_t offset, uint32_t mem_mask);
+ void dmatcr7_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t chcr7_r(offs_t offset, uint32_t mem_mask);
+ void chcr7_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+
+ // CPG
+ uint16_t frqcr_r(offs_t offset, uint16_t mem_mask);
+ void frqcr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint8_t stbcr_r(offs_t offset, uint8_t mem_mask);
+ void stbcr_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t wtcnt_r(offs_t offset, uint8_t mem_mask);
+ void wtcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint8_t wtcsr_r(offs_t offset, uint8_t mem_mask);
+ void wtcsr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint8_t stbcr2_r(offs_t offset, uint8_t mem_mask);
+ void stbcr2_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+
+ // CPG 7750R
+ uint32_t clkstp00_r(offs_t offset, uint32_t mem_mask);
+ void clkstp00_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ void clkstpclr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+
+ // RTC
+ uint8_t r64cnt_r(offs_t offset, uint8_t mem_mask);
+ uint8_t rseccnt_r(offs_t offset, uint8_t mem_mask);
+ void rseccnt_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rmincnt_r(offs_t offset, uint8_t mem_mask);
+ void rmincnt_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rhrcnt_r(offs_t offset, uint8_t mem_mask);
+ void rhrcnt_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rwkcnt_r(offs_t offset, uint8_t mem_mask);
+ void rwkcnt_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rdaycnt_r(offs_t offset, uint8_t mem_mask);
+ void rdaycnt_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rmoncnt_r(offs_t offset, uint8_t mem_mask);
+ void rmoncnt_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint16_t ryrcnt_r(offs_t offset, uint16_t mem_mask);
+ void ryrcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint8_t rsecar_r(offs_t offset, uint8_t mem_mask);
+ void rsecar_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rminar_r(offs_t offset, uint8_t mem_mask);
+ void rminar_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rhrar_r(offs_t offset, uint8_t mem_mask);
+ void rhrar_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rwkar_r(offs_t offset, uint8_t mem_mask);
+ void rwkar_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rdayar_r(offs_t offset, uint8_t mem_mask);
+ void rdayar_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rmonar_r(offs_t offset, uint8_t mem_mask);
+ void rmonar_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rcr1_r(offs_t offset, uint8_t mem_mask);
+ void rcr1_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t rcr2_r(offs_t offset, uint8_t mem_mask);
+ void rcr2_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+
+ // RTC 7750R
+ uint8_t rcr3_r(offs_t offset, uint8_t mem_mask);
+ void rcr3_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint16_t ryrar_r(offs_t offset, uint16_t mem_mask);
+ void ryrar_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+ // INTC
+ uint16_t icr_r(offs_t offset, uint16_t mem_mask);
+ void icr_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t iprb_r(offs_t offset, uint16_t mem_mask);
+ void iprb_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t iprc_r(offs_t offset, uint16_t mem_mask);
+ void iprc_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+ // INTC 7750S
+ uint16_t iprd_r(offs_t offset, uint16_t mem_mask);
+ void iprd_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+ // INTC 7750R
+ uint32_t intpri00_r(offs_t offset, uint32_t mem_mask);
+ void intpri00_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t intreq00_r(offs_t offset, uint32_t mem_mask);
+ void intreq00_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t intmsk00_r(offs_t offset, uint32_t mem_mask);
+ void intmsk00_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ void intmskclr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+
+ // TMU 7750R
+ uint8_t tstr2_r(offs_t offset, uint8_t mem_mask);
+ void tstr2_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint32_t tcor3_r(offs_t offset, uint32_t mem_mask);
+ void tcor3_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t tcnt3_r(offs_t offset, uint32_t mem_mask);
+ void tcnt3_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint16_t tcr3_r(offs_t offset, uint16_t mem_mask);
+ void tcr3_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint32_t tcor4_r(offs_t offset, uint32_t mem_mask);
+ void tcor4_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t tcnt4_r(offs_t offset, uint32_t mem_mask);
+ void tcnt4_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint16_t tcr4_r(offs_t offset, uint16_t mem_mask);
+ void tcr4_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+ // SCI
+ uint8_t scsmr1_r(offs_t offset, uint8_t mem_mask);
+ void scsmr1_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scbrr1_r(offs_t offset, uint8_t mem_mask);
+ void scbrr1_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scscr1_r(offs_t offset, uint8_t mem_mask);
+ void scscr1_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t sctdr1_r(offs_t offset, uint8_t mem_mask);
+ void sctdr1_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scssr1_r(offs_t offset, uint8_t mem_mask);
+ void scssr1_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scrdr1_r(offs_t offset, uint8_t mem_mask);
+ void scscmr1_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint8_t scscmr1_r(offs_t offset, uint8_t mem_mask);
+ uint8_t scsptr1_r(offs_t offset, uint8_t mem_mask);
+ void scsptr1_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+
+ // SCIF
+ uint16_t scsmr2_r(offs_t offset, uint16_t mem_mask);
+ void scsmr2_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint8_t scbrr2_r(offs_t offset, uint8_t mem_mask);
+ void scbrr2_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint16_t scscr2_r(offs_t offset, uint16_t mem_mask);
+ void scscr2_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint8_t scftdr2_r(offs_t offset, uint8_t mem_mask);
+ void scftdr2_w(offs_t offset, uint8_t data, uint8_t mem_mask);
+ uint16_t scfsr2_r(offs_t offset, uint16_t mem_mask);
+ void scfsr2_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint8_t scfrdr2_r(offs_t offset, uint8_t mem_mask);
+ uint16_t scfcr2_r(offs_t offset, uint16_t mem_mask);
+ void scfcr2_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t scfdr2_r(offs_t offset, uint16_t mem_mask);
+ uint16_t scsptr2_r(offs_t offset, uint16_t mem_mask);
+ void scsptr2_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint16_t sclsr2_r(offs_t offset, uint16_t mem_mask);
+ void sclsr2_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+ // H-UDI
+ uint16_t sdir_r(offs_t offset, uint16_t mem_mask);
+ void sdir_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+ uint32_t sddr_r(offs_t offset, uint32_t mem_mask);
+ void sddr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+
+ // H-UDI 7750R
+ uint16_t sdint_r(offs_t offset, uint16_t mem_mask);
+ void sdint_w(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+ // PCI 7751
+ uint32_t pciconf0_r(offs_t offset, uint32_t mem_mask);
+ uint32_t pciconf1_r(offs_t offset, uint32_t mem_mask);
+ void pciconf1_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciconf2_r(offs_t offset, uint32_t mem_mask);
+ void pciconf2_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciconf3_r(offs_t offset, uint32_t mem_mask);
+ void pciconf3_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciconf4_r(offs_t offset, uint32_t mem_mask);
+ void pciconf4_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciconf5_r(offs_t offset, uint32_t mem_mask);
+ void pciconf5_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciconf6_r(offs_t offset, uint32_t mem_mask);
+ void pciconf6_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciconf7_r(offs_t offset, uint32_t mem_mask);
+ uint32_t pciconf8_r(offs_t offset, uint32_t mem_mask);
+ uint32_t pciconf9_r(offs_t offset, uint32_t mem_mask);
+ uint32_t pciconf10_r(offs_t offset, uint32_t mem_mask);
+ uint32_t pciconf11_r(offs_t offset, uint32_t mem_mask);
+ void pciconf11_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciconf12_r(offs_t offset, uint32_t mem_mask);
+ uint32_t pciconf13_r(offs_t offset, uint32_t mem_mask);
+ uint32_t pciconf14_r(offs_t offset, uint32_t mem_mask);
+ uint32_t pciconf15_r(offs_t offset, uint32_t mem_mask);
+ void pciconf15_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciconf16_r(offs_t offset, uint32_t mem_mask);
+ void pciconf16_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciconf17_r(offs_t offset, uint32_t mem_mask);
+ void pciconf17_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcicr_r(offs_t offset, uint32_t mem_mask);
+ void pcicr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcilsr0_r(offs_t offset, uint32_t mem_mask);
+ void pcilsr0_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcilsr1_r(offs_t offset, uint32_t mem_mask);
+ void pcilsr1_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcilar0_r(offs_t offset, uint32_t mem_mask);
+ void pcilar0_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcilar1_r(offs_t offset, uint32_t mem_mask);
+ void pcilar1_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciint_r(offs_t offset, uint32_t mem_mask);
+ void pciint_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciintm_r(offs_t offset, uint32_t mem_mask);
+ void pciintm_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcialr_r(offs_t offset, uint32_t mem_mask);
+ void pcialr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciclr_r(offs_t offset, uint32_t mem_mask);
+ void pciclr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciaint_r(offs_t offset, uint32_t mem_mask);
+ void pciaint_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciaintm_r(offs_t offset, uint32_t mem_mask);
+ void pciaintm_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcibllr_r(offs_t offset, uint32_t mem_mask);
+ void pcibllr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcidmabt_r(offs_t offset, uint32_t mem_mask);
+ void pcidmabt_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcidpa0_r(offs_t offset, uint32_t mem_mask);
+ void pcidpa0_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcidla0_r(offs_t offset, uint32_t mem_mask);
+ void pcidla0_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcidtc0_r(offs_t offset, uint32_t mem_mask);
+ void pcidtc0_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcidcr0_r(offs_t offset, uint32_t mem_mask);
+ void pcidcr0_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcidpa1_r(offs_t offset, uint32_t mem_mask);
+ void pcidpa1_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcidla1_r(offs_t offset, uint32_t mem_mask);
+ void pcidla1_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcidtc1_r(offs_t offset, uint32_t mem_mask);
+ void pcidtc1_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcidcr1_r(offs_t offset, uint32_t mem_mask);
+ void pcidcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcidpa2_r(offs_t offset, uint32_t mem_mask);
+ void pcidpa2_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcidla2_r(offs_t offset, uint32_t mem_mask);
+ void pcidla2_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcidtc2_r(offs_t offset, uint32_t mem_mask);
+ void pcidtc2_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcidcr2_r(offs_t offset, uint32_t mem_mask);
+ void pcidcr2_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcidpa3_r(offs_t offset, uint32_t mem_mask);
+ void pcidpa3_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcidla3_r(offs_t offset, uint32_t mem_mask);
+ void pcidla3_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcidtc3_r(offs_t offset, uint32_t mem_mask);
+ void pcidtc3_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcidcr3_r(offs_t offset, uint32_t mem_mask);
+ void pcidcr3_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcipar_r(offs_t offset, uint32_t mem_mask);
+ void pcipar_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcimbr_r(offs_t offset, uint32_t mem_mask);
+ void pcimbr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciiobr_r(offs_t offset, uint32_t mem_mask);
+ void pciiobr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcipint_r(offs_t offset, uint32_t mem_mask);
+ void pcipint_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcipintm_r(offs_t offset, uint32_t mem_mask);
+ void pcipintm_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciclkr_r(offs_t offset, uint32_t mem_mask);
+ void pciclkr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcibcr1_r(offs_t offset, uint32_t mem_mask);
+ void pcibcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcibcr2_r(offs_t offset, uint32_t mem_mask);
+ void pcibcr2_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcibcr3_r(offs_t offset, uint32_t mem_mask);
+ void pcibcr3_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciwcr1_r(offs_t offset, uint32_t mem_mask);
+ void pciwcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciwcr2_r(offs_t offset, uint32_t mem_mask);
+ void pciwcr2_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pciwcr3_r(offs_t offset, uint32_t mem_mask);
+ void pciwcr3_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcimcr_r(offs_t offset, uint32_t mem_mask);
+ void pcimcr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcipctr_r(offs_t offset, uint32_t mem_mask);
+ void pcipctr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcipdtr_r(offs_t offset, uint32_t mem_mask);
+ void pcipdtr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+ uint32_t pcipdr_r(offs_t offset, uint32_t mem_mask);
+ void pcipdr_w(offs_t offset, uint32_t data, uint32_t mem_mask);
+
+ TIMER_CALLBACK_MEMBER(sh4_rtc_timer_callback);
+ TIMER_CALLBACK_MEMBER(sh4_refresh_timer_callback);
+ void increment_rtc_time(int mode);
+ uint32_t compute_ticks_refresh_timer(emu_timer* timer, int hertz, int base, int divisor);
+ void sh4_refresh_timer_recompute();
virtual void LDTLB(const uint16_t opcode) override;
virtual uint32_t get_remap(uint32_t address) override;
virtual uint32_t sh4_getsqremap(uint32_t address) override;
- sh4_utlb m_utlb[64];
- void sh4_internal_map(address_map &map) ATTR_COLD;
-protected:
- // construction/destruction
- sh4_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, endianness_t endianness);
+ emu_timer* m_rtc_timer;
+ emu_timer* m_refresh_timer;
+ uint32_t m_refresh_timer_base;
+ sh4_utlb m_utlb[64];
- virtual void device_start() override ATTR_COLD;
- virtual void device_reset() override ATTR_COLD;
+ // UBC
+ uint32_t m_bara;
+ uint8_t m_bamra;
+ uint16_t m_bbra;
+ uint32_t m_barb;
+ uint8_t m_bamrb;
+ uint16_t m_bbrb;
+ uint32_t m_bdrb;
+ uint32_t m_bdmrb;
+ uint16_t m_brcr;
+
+ // BSC
+ uint32_t m_bcr1;
+ uint16_t m_bcr2;
+ uint32_t m_wcr1;
+ uint32_t m_wcr2;
+ uint32_t m_wcr3;
+ uint32_t m_mcr;
+ uint16_t m_pcr;
+ uint16_t m_rtcsr;
+ uint16_t m_rtcnt;
+ uint16_t m_rtcor;
+ uint16_t m_rfcr;
+ uint32_t m_pctra;
+ uint16_t m_pdtra;
+ uint32_t m_pctrb;
+ uint16_t m_pdtrb;
+ uint16_t m_gpioic;
+
+ // BSC 7750R
+ uint32_t m_bcr3;
+ uint32_t m_bcr4;
+
+ // DMAC 7750R
+ uint32_t m_sar4;
+ uint32_t m_dar4;
+ uint32_t m_dmatcr4;
+ uint32_t m_chcr4;
+ uint32_t m_sar5;
+ uint32_t m_dar5;
+ uint32_t m_dmatcr5;
+ uint32_t m_chcr5;
+ uint32_t m_sar6;
+ uint32_t m_dar6;
+ uint32_t m_dmatcr6;
+ uint32_t m_chcr6;
+ uint32_t m_sar7;
+ uint32_t m_dar7;
+ uint32_t m_dmatcr7;
+ uint32_t m_chcr7;
+
+ // CPG
+ uint16_t m_frqcr;
+ uint8_t m_stbcr;
+ uint16_t m_wtcnt;
+ uint16_t m_wtcsr;
+ uint8_t m_stbcr2;
+
+ // CPG 7750R
+ uint32_t m_clkstp00;
+
+ // RTC
+ uint8_t m_r64cnt;
+ uint8_t m_rseccnt;
+ uint8_t m_rmincnt;
+ uint8_t m_rhrcnt;
+ uint8_t m_rwkcnt;
+ uint8_t m_rmoncnt;
+ uint8_t m_rdaycnt;
+ uint16_t m_ryrcnt;
+ uint8_t m_rsecar;
+ uint8_t m_rminar;
+ uint8_t m_rhrar;
+ uint8_t m_rwkar;
+ uint8_t m_rdayar;
+ uint8_t m_rmonar;
+ uint8_t m_rcr1;
+ uint8_t m_rcr2;
+
+ // RTC 7750R
+ uint8_t m_rcr3;
+ uint16_t m_ryrar;
+
+ // INTC
+ uint16_t m_iprb;
+
+ // INTC 7750S
+ uint16_t m_iprd;
+
+ // INTC 7750R
+ uint32_t m_intpri00;
+ uint32_t m_intreq00;
+ uint32_t m_intmsk00;
+
+ // TMU 7750R
+ uint8_t m_tstr2;
+ uint32_t m_tcor3;
+ uint32_t m_tcnt3;
+ uint16_t m_tcr3;
+ uint32_t m_tcor4;
+ uint32_t m_tcnt4;
+ uint16_t m_tcr4;
+
+ // SCI
+ uint8_t m_scsmr1;
+ uint8_t m_scbrr1;
+ uint8_t m_scscr1;
+ uint8_t m_sctdr1;
+ uint8_t m_scssr1;
+ uint8_t m_scrdr1;
+ uint8_t m_scscmr1;
+ uint8_t m_scsptr1;
+
+ // SCIF
+ uint16_t m_scsmr2;
+ uint8_t m_scbrr2;
+ uint16_t m_scscr2;
+ uint8_t m_scftdr2;
+ uint16_t m_scfsr2;
+ uint8_t m_scfrdr2;
+ uint16_t m_scfcr2;
+ uint16_t m_scfdr2;
+ uint16_t m_scsptr2;
+ uint16_t m_sclsr2;
+
+ // H-UDI
+ uint16_t m_sdir;
+ uint32_t m_sddr;
+ uint16_t m_sdint;
+
+ // PCI 7751
+ uint32_t m_pciconf0;
+ uint32_t m_pciconf1;
+ uint32_t m_pciconf2;
+ uint32_t m_pciconf3;
+ uint32_t m_pciconf4;
+ uint32_t m_pciconf5;
+ uint32_t m_pciconf6;
+ uint32_t m_pciconf7;
+ uint32_t m_pciconf8;
+ uint32_t m_pciconf9;
+ uint32_t m_pciconf10;
+ uint32_t m_pciconf11;
+ uint32_t m_pciconf12;
+ uint32_t m_pciconf13;
+ uint32_t m_pciconf14;
+ uint32_t m_pciconf15;
+ uint32_t m_pciconf16;
+ uint32_t m_pciconf17;
+ uint32_t m_pcicr;
+ uint32_t m_pcilsr0;
+ uint32_t m_pcilsr1;
+ uint32_t m_pcilar0;
+ uint32_t m_pcilar1;
+ uint32_t m_pciint;
+ uint32_t m_pciintm;
+ uint32_t m_pcialr;
+ uint32_t m_pciclr;
+ uint32_t m_pciaint;
+ uint32_t m_pciaintm;
+ uint32_t m_pcibllr;
+ uint32_t m_pcidmabt;
+ uint32_t m_pcidpa0;
+ uint32_t m_pcidla0;
+ uint32_t m_pcidtc0;
+ uint32_t m_pcidcr0;
+ uint32_t m_pcidpa1;
+ uint32_t m_pcidla1;
+ uint32_t m_pcidtc1;
+ uint32_t m_pcidcr1;
+ uint32_t m_pcidpa2;
+ uint32_t m_pcidla2;
+ uint32_t m_pcidtc2;
+ uint32_t m_pcidcr2;
+ uint32_t m_pcidpa3;
+ uint32_t m_pcidla3;
+ uint32_t m_pcidtc3;
+ uint32_t m_pcidcr3;
+ uint32_t m_pcipar;
+ uint32_t m_pcimbr;
+ uint32_t m_pciiobr;
+ uint32_t m_pcipint;
+ uint32_t m_pcipintm;
+ uint32_t m_pciclkr;
+ uint32_t m_pcibcr1;
+ uint32_t m_pcibcr2;
+ uint32_t m_pcibcr3;
+ uint32_t m_pciwcr1;
+ uint32_t m_pciwcr2;
+ uint32_t m_pciwcr3;
+ uint32_t m_pcimcr;
+ uint32_t m_pcipctr;
+ uint32_t m_pcipdtr;
+ uint32_t m_pcipdr;
};
class sh3_device : public sh3_base_device
{
- friend class sh4_frontend;
public:
- sh3_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- std::unique_ptr<sh4_frontend> m_drcfe; /* pointer to the DRC front-end state */
- virtual const opcode_desc* get_desclist(offs_t pc) override;
- virtual void init_drc_frontend() override;
+ sh3_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, endianness_t endianness = ENDIANNESS_LITTLE);
+
+ virtual void sh3_register_map(address_map& map) override ATTR_COLD;
};
+class sh7708s_device : public sh3_base_device
+{
+public:
+ sh7708s_device(const machine_config& mconfig, const char* tag, device_t* owner, uint32_t clock, endianness_t endianness = ENDIANNESS_LITTLE);
-class sh3be_device : public sh3_base_device
+ virtual void sh3_register_map(address_map& map) override ATTR_COLD;
+};
+
+class sh7709_device : public sh3_base_device
{
- friend class sh4be_frontend;
+public:
+ sh7709_device(const machine_config& mconfig, const char* tag, device_t* owner, uint32_t clock, endianness_t endianness = ENDIANNESS_LITTLE);
+ virtual void sh3_register_map(address_map& map) override ATTR_COLD;
+};
+
+class sh7709s_device : public sh3_base_device
+{
public:
- sh3be_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- std::unique_ptr<sh4be_frontend> m_drcfe; /* pointer to the DRC front-end state */
- virtual const opcode_desc* get_desclist(offs_t pc) override;
- virtual void init_drc_frontend() override;
+ sh7709s_device(const machine_config& mconfig, const char* tag, device_t* owner, uint32_t clock, endianness_t endianness = ENDIANNESS_LITTLE);
-protected:
- virtual void execute_run() override;
+ virtual void sh3_register_map(address_map& map) override ATTR_COLD;
};
class sh4_device : public sh4_base_device
{
- friend class sh4_frontend;
+public:
+ sh4_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, endianness_t endianness = ENDIANNESS_LITTLE);
+
+protected:
+ virtual void sh4_register_map(address_map& map) override ATTR_COLD;
+};
+class sh7091_device : public sh4_base_device
+{
public:
- sh4_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- std::unique_ptr<sh4_frontend> m_drcfe; /* pointer to the DRC front-end state */
- virtual const opcode_desc* get_desclist(offs_t pc) override;
- virtual void init_drc_frontend() override;
+ sh7091_device(const machine_config& mconfig, const char* tag, device_t* owner, uint32_t clock, endianness_t endianness = ENDIANNESS_LITTLE);
+protected:
+ virtual void sh4_register_map(address_map& map) override ATTR_COLD;
};
+class sh7750_device : public sh4_base_device
+{
+public:
+ sh7750_device(const machine_config& mconfig, const char* tag, device_t* owner, uint32_t clock, endianness_t endianness = ENDIANNESS_LITTLE);
+
+protected:
+ virtual void sh4_register_map(address_map& map) override ATTR_COLD;
+};
-class sh4be_device : public sh4_base_device
+class sh7750s_device : public sh4_base_device
{
- friend class sh4be_frontend;
+public:
+ sh7750s_device(const machine_config& mconfig, const char* tag, device_t* owner, uint32_t clock, endianness_t endianness = ENDIANNESS_LITTLE);
+protected:
+ virtual void sh4_register_map(address_map& map) override ATTR_COLD;
+};
+
+class sh7750r_device : public sh4_base_device
+{
public:
- sh4be_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- std::unique_ptr<sh4be_frontend> m_drcfe; /* pointer to the DRC front-end state */
- virtual const opcode_desc* get_desclist(offs_t pc) override;
- virtual void init_drc_frontend() override;
+ sh7750r_device(const machine_config& mconfig, const char* tag, device_t* owner, uint32_t clock, endianness_t endianness = ENDIANNESS_LITTLE);
protected:
- virtual void execute_run() override;
+ virtual void sh4_register_map(address_map& map) override ATTR_COLD;
+};
+
+class sh7751_device : public sh4_base_device
+{
+public:
+ sh7751_device(const machine_config& mconfig, const char* tag, device_t* owner, uint32_t clock, endianness_t endianness = ENDIANNESS_LITTLE);
+
+protected:
+ virtual void sh4_register_map(address_map& map) override ATTR_COLD;
+};
+
+class sh7751r_device : public sh4_base_device
+{
+public:
+ sh7751r_device(const machine_config& mconfig, const char* tag, device_t* owner, uint32_t clock, endianness_t endianness = ENDIANNESS_LITTLE);
+
+protected:
+ virtual void sh4_register_map(address_map& map) override ATTR_COLD;
};
class sh4_frontend : public sh_frontend
@@ -792,19 +1988,16 @@ private:
bool describe_op1111_0xf13(opcode_desc &desc, const opcode_desc *prev, uint16_t opcode);
};
-class sh4be_frontend : public sh4_frontend
-{
-public:
- sh4be_frontend(sh_common_execution *device, uint32_t window_start, uint32_t window_end, uint32_t max_sequence) :
- sh4_frontend(device, window_start, window_end, max_sequence)
- {}
-protected:
- virtual uint16_t read_word(opcode_desc &desc) override;
-};
-
-DECLARE_DEVICE_TYPE(SH3LE, sh3_device)
-DECLARE_DEVICE_TYPE(SH3BE, sh3be_device)
-DECLARE_DEVICE_TYPE(SH4LE, sh4_device)
-DECLARE_DEVICE_TYPE(SH4BE, sh4be_device)
+DECLARE_DEVICE_TYPE(SH3, sh3_device)
+DECLARE_DEVICE_TYPE(SH7708S, sh7708s_device)
+DECLARE_DEVICE_TYPE(SH7709, sh7709_device)
+DECLARE_DEVICE_TYPE(SH7709S, sh7709s_device)
+DECLARE_DEVICE_TYPE(SH4, sh4_device)
+DECLARE_DEVICE_TYPE(SH7091, sh7091_device)
+DECLARE_DEVICE_TYPE(SH7750, sh7750_device)
+DECLARE_DEVICE_TYPE(SH7750R, sh7750r_device)
+DECLARE_DEVICE_TYPE(SH7750S, sh7750s_device)
+DECLARE_DEVICE_TYPE(SH7751, sh7751_device)
+DECLARE_DEVICE_TYPE(SH7751R, sh7751r_device)
#endif // MAME_CPU_SH_SH4_H
diff --git a/src/devices/cpu/sh/sh4comn.cpp b/src/devices/cpu/sh/sh4comn.cpp
index aa424099012..6f2831585a2 100644
--- a/src/devices/cpu/sh/sh4comn.cpp
+++ b/src/devices/cpu/sh/sh4comn.cpp
@@ -392,11 +392,11 @@ void sh34_base_device::sh4_exception(const char *message, int exception) // hand
if (exception == SH4_INTC_NMI)
{
- if ((m_sh2_state->sr & BL) && !(m_m[ICR] & 0x200))
+ if ((m_sh2_state->sr & BL) && !(m_icr & 0x200))
return;
- m_m[ICR] &= ~0x200;
- m_m[INTEVT] = 0x1c0;
+ m_icr &= ~0x200;
+ m_intevt = 0x1c0;
vector = 0x600;
standard_irq_callback(INPUT_LINE_NMI, m_sh2_state->pc);
@@ -404,13 +404,13 @@ void sh34_base_device::sh4_exception(const char *message, int exception) // hand
}
else
{
- // if ((m_m[ICR] & 0x4000) && (m_nmi_line_state == ASSERT_LINE))
+ // if ((m_icr & 0x4000) && (m_nmi_line_state == ASSERT_LINE))
// return;
if (m_sh2_state->sr & BL)
return;
if (((m_exception_priority[exception] >> 8) & 255) <= ((m_sh2_state->sr >> 4) & 15))
return;
- m_m[INTEVT] = exception_codes[exception];
+ m_intevt = exception_codes[exception];
vector = 0x600;
if (exception >= SH4_INTC_IRL0 && exception <= SH4_INTC_IRL3)
standard_irq_callback((exception - SH4_INTC_IRL0) + SH4_IRL0, m_sh2_state->pc);
@@ -446,12 +446,12 @@ void sh34_base_device::sh4_exception(const char *message, int exception) // hand
if (sh3_intevt2_exception_codes[exception] == -1)
fatalerror("sh3_intevt2_exception_codes unpopulated for exception %02x\n", exception);
- m_sh3internal_lower[INTEVT2] = sh3_intevt2_exception_codes[exception];
- m_sh3internal_upper[SH3_EXPEVT_ADDR] = exception_codes[exception];
+ m_intevt2 = sh3_intevt2_exception_codes[exception];
+ m_expevt = exception_codes[exception];
if (sh3_intevt2_exception_codes[exception] >= 0x600)
- m_sh3internal_upper[SH3_INTEVT_ADDR] = 0x3e0 - ((m_exception_priority[exception] >> 8) & 255) * 0x20;
+ m_intevt = 0x3e0 - ((m_exception_priority[exception] >> 8) & 255) * 0x20;
else
- m_sh3internal_upper[SH3_INTEVT_ADDR] = sh3_intevt2_exception_codes[exception];
+ m_intevt = sh3_intevt2_exception_codes[exception];
LOG("SH-3 '%s' interrupt exception #%d after [%s]\n", tag(), exception, message);
@@ -464,63 +464,54 @@ void sh34_base_device::sh4_exception(const char *message, int exception) // hand
}
-uint32_t sh34_base_device::compute_ticks_refresh_timer(emu_timer *timer, int hertz, int base, int divisor)
+uint32_t sh4_base_device::compute_ticks_refresh_timer(emu_timer *timer, int hertz, int base, int divisor)
{
// elapsed:total = x : ticks
- // x=elapsed*tics/total -> x=elapsed*(double)100000000/rtcnt_div[(m_m[RTCSR] >> 3) & 7]
- // ticks/total=ticks / ((rtcnt_div[(m_m[RTCSR] >> 3) & 7] * ticks) / 100000000)=1/((rtcnt_div[(m_m[RTCSR] >> 3) & 7] / 100000000)=100000000/rtcnt_div[(m_m[RTCSR] >> 3) & 7]
+ // x=elapsed*tics/total -> x=elapsed*(double)100000000/rtcnt_div[(m_rtcsr >> 3) & 7]
+ // ticks/total=ticks / ((rtcnt_div[(m_rtcsr >> 3) & 7] * ticks) / 100000000)=1/((rtcnt_div[(m_rtcsr >> 3) & 7] / 100000000)=100000000/rtcnt_div[(m_rtcsr >> 3) & 7]
return base + (uint32_t)((timer->elapsed().as_double() * hertz) / divisor);
}
-void sh34_base_device::sh4_refresh_timer_recompute()
+void sh4_base_device::sh4_refresh_timer_recompute()
{
- if (m_cpu_type != CPU_TYPE_SH4)
- fatalerror("sh4_refresh_timer_recompute uses m_m[] with SH3\n");
-
//if rtcnt < rtcor then rtcor-rtcnt
//if rtcnt >= rtcor then 256-rtcnt+rtcor=256+rtcor-rtcnt
- uint32_t ticks = m_m[RTCOR]-m_m[RTCNT];
+ uint32_t ticks = m_rtcor-m_rtcnt;
if (ticks <= 0)
ticks = 256 + ticks;
- m_refresh_timer->adjust(attotime::from_hz(m_bus_clock) * rtcnt_div[(m_m[RTCSR] >> 3) & 7] * ticks);
- m_refresh_timer_base = m_m[RTCNT];
+ m_refresh_timer->adjust(attotime::from_hz(m_bus_clock) * rtcnt_div[(m_rtcsr >> 3) & 7] * ticks);
+ m_refresh_timer_base = m_rtcnt;
}
-TIMER_CALLBACK_MEMBER(sh34_base_device::sh4_refresh_timer_callback)
+TIMER_CALLBACK_MEMBER(sh4_base_device::sh4_refresh_timer_callback)
{
- if (m_cpu_type != CPU_TYPE_SH4)
- fatalerror("sh4_refresh_timer_callback uses m_m[] with SH3\n");
-
- m_m[RTCNT] = 0;
+ m_rtcnt = 0;
sh4_refresh_timer_recompute();
- m_m[RTCSR] |= 128;
- if ((m_m[MCR] & 4) && !(m_m[MCR] & 2))
+ m_rtcsr |= 128;
+ if ((m_mcr & 4) && !(m_mcr & 2))
{
- m_m[RFCR] = (m_m[RFCR] + 1) & 1023;
- if (((m_m[RTCSR] & 1) && m_m[RFCR] == 512) || m_m[RFCR] == 0)
+ m_rfcr = (m_rfcr + 1) & 1023;
+ if (((m_rtcsr & 1) && m_rfcr == 512) || m_rfcr == 0)
{
- m_m[RFCR] = 0;
- m_m[RTCSR] |= 4;
+ m_rfcr = 0;
+ m_rtcsr |= 4;
}
}
}
-void sh34_base_device::increment_rtc_time(int mode)
+void sh4_base_device::increment_rtc_time(int mode)
{
- if (m_cpu_type != CPU_TYPE_SH4)
- fatalerror("increment_rtc_time uses m_m[] with SH3\n");
-
int carry;
if (mode == 0)
{
carry = 0;
- m_m[RSECCNT] = m_m[RSECCNT] + 1;
- if ((m_m[RSECCNT] & 0xf) == 0xa)
- m_m[RSECCNT] = m_m[RSECCNT] + 6;
- if (m_m[RSECCNT] == 0x60)
+ m_rseccnt = m_rseccnt + 1;
+ if ((m_rseccnt & 0xf) == 0xa)
+ m_rseccnt = m_rseccnt + 6;
+ if (m_rseccnt == 0x60)
{
- m_m[RSECCNT] = 0;
+ m_rseccnt = 0;
carry = 1;
}
else
@@ -529,36 +520,36 @@ void sh34_base_device::increment_rtc_time(int mode)
else
carry = 1;
- m_m[RMINCNT] = m_m[RMINCNT] + carry;
- if ((m_m[RMINCNT] & 0xf) == 0xa)
- m_m[RMINCNT] = m_m[RMINCNT] + 6;
+ m_rmincnt = m_rmincnt + carry;
+ if ((m_rmincnt & 0xf) == 0xa)
+ m_rmincnt = m_rmincnt + 6;
carry = 0;
- if (m_m[RMINCNT] == 0x60)
+ if (m_rmincnt == 0x60)
{
- m_m[RMINCNT] = 0;
+ m_rmincnt = 0;
carry = 1;
}
- m_m[RHRCNT] = m_m[RHRCNT] + carry;
- if ((m_m[RHRCNT] & 0xf) == 0xa)
- m_m[RHRCNT] = m_m[RHRCNT] + 6;
+ m_rhrcnt = m_rhrcnt + carry;
+ if ((m_rhrcnt & 0xf) == 0xa)
+ m_rhrcnt = m_rhrcnt + 6;
carry = 0;
- if (m_m[RHRCNT] == 0x24)
+ if (m_rhrcnt == 0x24)
{
- m_m[RHRCNT] = 0;
+ m_rhrcnt = 0;
carry = 1;
}
- m_m[RWKCNT] = m_m[RWKCNT] + carry;
- if (m_m[RWKCNT] == 0x7)
+ m_rwkcnt = m_rwkcnt + carry;
+ if (m_rwkcnt == 0x7)
{
- m_m[RWKCNT] = 0;
+ m_rwkcnt = 0;
}
int days = 0;
- int year = (m_m[RYRCNT] & 0xf) + ((m_m[RYRCNT] & 0xf0) >> 4) * 10 + ((m_m[RYRCNT] & 0xf00) >> 8) * 100 + ((m_m[RYRCNT] & 0xf000) >> 12) * 1000;
+ int year = (m_ryrcnt & 0xf) + ((m_ryrcnt & 0xf0) >> 4) * 10 + ((m_ryrcnt & 0xf00) >> 8) * 100 + ((m_ryrcnt & 0xf000) >> 12) * 1000;
int leap = 0;
if (!(year % 100))
{
@@ -567,58 +558,52 @@ void sh34_base_device::increment_rtc_time(int mode)
}
else if (!(year % 4))
leap = 1;
- if (m_m[RMONCNT] != 2)
+ if (m_rmoncnt != 2)
leap = 0;
- if (m_m[RMONCNT])
- days = daysmonth[(m_m[RMONCNT] & 0xf) + ((m_m[RMONCNT] & 0xf0) >> 4) * 10 - 1];
+ if (m_rmoncnt)
+ days = daysmonth[(m_rmoncnt & 0xf) + ((m_rmoncnt & 0xf0) >> 4) * 10 - 1];
- m_m[RDAYCNT] = m_m[RDAYCNT] + carry;
- if ((m_m[RDAYCNT] & 0xf) == 0xa)
- m_m[RDAYCNT] = m_m[RDAYCNT] + 6;
+ m_rdaycnt = m_rdaycnt + carry;
+ if ((m_rdaycnt & 0xf) == 0xa)
+ m_rdaycnt = m_rdaycnt + 6;
carry = 0;
- if (m_m[RDAYCNT] > (days + leap))
+ if (m_rdaycnt > (days + leap))
{
- m_m[RDAYCNT] = 1;
+ m_rdaycnt = 1;
carry = 1;
}
- m_m[RMONCNT] = m_m[RMONCNT] + carry;
- if ((m_m[RMONCNT] & 0xf) == 0xa)
- m_m[RMONCNT] = m_m[RMONCNT] + 6;
+ m_rmoncnt = m_rmoncnt + carry;
+ if ((m_rmoncnt & 0xf) == 0xa)
+ m_rmoncnt = m_rmoncnt + 6;
carry = 0;
- if (m_m[RMONCNT] == 0x13)
+ if (m_rmoncnt == 0x13)
{
- m_m[RMONCNT] = 1;
+ m_rmoncnt = 1;
carry = 1;
}
- m_m[RYRCNT] = m_m[RYRCNT] + carry;
- if ((m_m[RYRCNT] & 0xf) >= 0xa)
- m_m[RYRCNT] = m_m[RYRCNT] + 6;
- if ((m_m[RYRCNT] & 0xf0) >= 0xa0)
- m_m[RYRCNT] = m_m[RYRCNT] + 0x60;
- if ((m_m[RYRCNT] & 0xf00) >= 0xa00)
- m_m[RYRCNT] = m_m[RYRCNT] + 0x600;
- if ((m_m[RYRCNT] & 0xf000) >= 0xa000)
- m_m[RYRCNT] = 0;
+ m_ryrcnt = m_ryrcnt + carry;
+ if ((m_ryrcnt & 0xf) >= 0xa)
+ m_ryrcnt = m_ryrcnt + 6;
+ if ((m_ryrcnt & 0xf0) >= 0xa0)
+ m_ryrcnt = m_ryrcnt + 0x60;
+ if ((m_ryrcnt & 0xf00) >= 0xa00)
+ m_ryrcnt = m_ryrcnt + 0x600;
+ if ((m_ryrcnt & 0xf000) >= 0xa000)
+ m_ryrcnt = 0;
}
-TIMER_CALLBACK_MEMBER(sh34_base_device::sh4_rtc_timer_callback)
+TIMER_CALLBACK_MEMBER(sh4_base_device::sh4_rtc_timer_callback)
{
- if (m_cpu_type != CPU_TYPE_SH4)
- {
- logerror("sh4_rtc_timer_callback uses m_m[] with SH3\n");
- return;
- }
-
m_rtc_timer->adjust(attotime::from_hz(128));
- m_m[R64CNT] = (m_m[R64CNT] + 1) & 0x7f;
- if (m_m[R64CNT] == 64)
+ m_r64cnt = (m_r64cnt + 1) & 0x7f;
+ if (m_r64cnt == 64)
{
- m_m[RCR1] |= 0x80;
+ m_rcr1 |= 0x80;
increment_rtc_time(0);
//sh4_exception_request(SH4_INTC_NMI); // TEST
}
@@ -629,7 +614,7 @@ void sh34_base_device::sh4_dmac_nmi() // manage dma when nmi gets asserted
{
int s;
- m_SH4_DMAOR |= DMAOR_NMIF;
+ m_dmaor |= DMAOR_NMIF;
for (s = 0;s < 4;s++)
{
if (m_dma_timer_active[s])
@@ -641,426 +626,2130 @@ void sh34_base_device::sh4_dmac_nmi() // manage dma when nmi gets asserted
}
}
-void sh34_base_device::sh4_handler_ipra_w(uint32_t data, uint32_t mem_mask)
+// CCN
+uint32_t sh4_base_device::pteh_r(offs_t offset, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_IPRA);
- /* 15 - 12 TMU0 */
- /* 11 - 8 TMU1 */
- /* 7 - 4 TMU2 */
- /* 3 - 0 RTC */
- m_exception_priority[SH4_INTC_ATI] = INTPRI(m_SH4_IPRA & 0x000f, SH4_INTC_ATI);
- m_exception_priority[SH4_INTC_PRI] = INTPRI(m_SH4_IPRA & 0x000f, SH4_INTC_PRI);
- m_exception_priority[SH4_INTC_CUI] = INTPRI(m_SH4_IPRA & 0x000f, SH4_INTC_CUI);
-
- m_exception_priority[SH4_INTC_TUNI2] = INTPRI((m_SH4_IPRA & 0x00f0) >> 4, SH4_INTC_TUNI2);
- m_exception_priority[SH4_INTC_TICPI2] = INTPRI((m_SH4_IPRA & 0x00f0) >> 4, SH4_INTC_TICPI2);
+ return m_pteh;
+}
- m_exception_priority[SH4_INTC_TUNI1] = INTPRI((m_SH4_IPRA & 0x0f00) >> 8, SH4_INTC_TUNI1);
+void sh4_base_device::pteh_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ // for use with LDTLB opcode
+ /*
+ NNNN NNNN NNNN NNNN NNNN NN-- AAAA AAAA
- m_exception_priority[SH4_INTC_TUNI0] = INTPRI((m_SH4_IPRA & 0xf000) >> 12, SH4_INTC_TUNI0);
+ N = VPM = Virtual Page Number
+ A = ASID = Address Space Identifier
- logerror("setting priorities TMU0 %01x TMU1 %01x TMU2 %01x RTC %01x\n", (m_SH4_IPRA & 0xf000)>>12, (m_SH4_IPRA & 0x0f00)>>8, (m_SH4_IPRA & 0x00f0)>>4, (m_SH4_IPRA & 0x000f)>>0);
+ same as the address table part of the utlb but with 2 unused bits (these are sourced from PTEL instead when LDTLB is called)
+ */
+ COMBINE_DATA(&m_pteh);
+}
- sh4_exception_recompute();
+uint32_t sh4_base_device::ptel_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_ptel;
}
+void sh4_base_device::ptel_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ /*
+ ---P PPPP PPPP PPPP PPPP PP-V zRRz CDHW
-void sh4_base_device::sh4_internal_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+ same format as data array 1 of the utlb
+ */
+ COMBINE_DATA(&m_ptel);
+}
+
+uint32_t sh4_base_device::ttb_r(offs_t offset, uint32_t mem_mask)
{
- uint32_t addr = (offset << 2) + 0xfe000000;
- offset = ((addr & 0xfc) >> 2) | ((addr & 0x1fe0000) >> 11);
+ return m_ttb;
+}
- if (m_cpu_type != CPU_TYPE_SH4)
- fatalerror("sh4_internal_w uses m_m[] with SH3\n");
+void sh4_base_device::ttb_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_ttb);
+ logerror("TTB set to %08x\n", m_ttb);
+}
- uint32_t old = m_m[offset];
- COMBINE_DATA(m_m + offset);
+uint32_t sh4_base_device::tea_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_tea;
+}
-// printf("sh4_internal_w: Write %08x (%x), %08x @ %08x\n", 0xfe000000 + ((offset & 0x3fc0) << 11) + ((offset & 0x3f) << 2), offset, data, mem_mask);
+void sh4_base_device::tea_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_tea);
+ logerror("TEA set to %08x\n", m_tea);
+}
- switch (offset)
- {
- case PTEH: // for use with LDTLB opcode
- m_m[PTEH] &= 0xffffffff;
- /*
- NNNN NNNN NNNN NNNN NNNN NN-- AAAA AAAA
-
- N = VPM = Virtual Page Number
- A = ASID = Address Space Identifier
-
- same as the address table part of the utlb but with 2 unused bits (these are sourced from PTEL instead when LDTLB is called)
- */
- break;
-
- case PTEL:
- m_m[PTEL] &= 0xffffffff;
- /*
- ---P PPPP PPPP PPPP PPPP PP-V zRRz CDHW
-
- same format as data array 1 of the utlb
- */
- break;
-
- case PTEA:
- m_m[PTEA] &= 0xffffffff;
- /*
- ---- ---- ---- ---- ---- ---- ---- TSSS
-
- same format as data array 2 of the utlb
- */
- break;
-
- case TTB:
- m_m[TTB] &= 0xffffffff;
- logerror("TTB set to %08x\n", data);
- break;
-
- case TEA:
- m_m[TEA] &= 0xffffffff;
- logerror("TEA set to %08x\n", data);
- break;
+uint32_t sh4_base_device::mmucr_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_mmucr;
+}
+void sh4_base_device::mmucr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ // MMU Control
/*
- LLLL LL-- BBBB BB-- CCCC CCQV ---- -T-A
-
- L = LRUI = Least recently used ITLB
- B = URB = UTLB replace boundary
- C = URC = UTLB replace counter
- Q = SQMD = Store Queue Mode Bit
- V = SV = Single Virtual Mode Bit
- T = TI = TLB invalidate
- A = AT = Address translation bit (enable)
+ LLLL LL-- BBBB BB-- CCCC CCQV ---- -T-A
+
+ L = LRUI = Least recently used ITLB
+ B = URB = UTLB replace boundary
+ C = URC = UTLB replace counter
+ Q = SQMD = Store Queue Mode Bit
+ V = SV = Single Virtual Mode Bit
+ T = TI = TLB invalidate
+ A = AT = Address translation bit (enable)
*/
- case MMUCR: // MMU Control
- m_m[MMUCR] &= 0xffffffff;
- // MMUCR_AT
- m_sh4_mmu_enabled = BIT(data, 0);
- logerror("%s: MMUCR %08x (enable: %d)\n", machine().describe_context(), data, m_sh4_mmu_enabled);
+ COMBINE_DATA(&m_mmucr);
+ // MMUCR_AT
+ m_sh4_mmu_enabled = BIT(data, 0);
+ logerror("%s: MMUCR %08x (enable: %d)\n", machine().describe_context(), data, m_sh4_mmu_enabled);
- if (m_sh4_mmu_enabled)
- {
- // Newer versions of the Dreamcast Katana SDK use MMU to remap the SQ write-back space (cfr. ikaruga and several later NAOMI GD-ROM releases)
- // Anything beyond that is bound to fail,
- // i.e. DC WinCE games, DC Linux distros, v2 Sega checkers, aristmk6.cpp
+ if (m_sh4_mmu_enabled)
+ {
+ // Newer versions of the Dreamcast Katana SDK use MMU to remap the SQ write-back space (cfr. ikaruga and several later NAOMI GD-ROM releases)
+ // Anything beyond that is bound to fail,
+ // i.e. DC WinCE games, DC Linux distros, v2 Sega checkers, aristmk6.cpp
#if 0
- if (m_mmuhack == 1)
- {
- printf("SH4 MMU Enabled\n");
- printf("If you're seeing this, but running something other than a Naomi GD-ROM game then chances are it won't work\n");
- printf("The MMU emulation is a hack specific to that system\n");
- }
+ if (m_mmuhack == 1)
+ {
+ printf("SH4 MMU Enabled\n");
+ printf("If you're seeing this, but running something other than a Naomi GD-ROM game then chances are it won't work\n");
+ printf("The MMU emulation is a hack specific to that system\n");
+ }
#endif
- if (m_mmuhack == 2)
+ if (m_mmuhack == 2)
+ {
+ for (int i = 0; i < 64; i++)
{
- for (int i = 0; i < 64; i++)
+ if (m_utlb[i].V)
{
- if (m_utlb[i].V)
- {
- // FIXME: potentially verbose, move to logmacro.h pattern
- // cfr. MMU Check_4 in v2.xx DC CHECKER
- logerror("(entry %02x | ASID: %02x VPN: %08x V: %02x PPN: %08x SZ: %02x SH: %02x C: %02x PPR: %02x D: %02x WT %02x: SA: %02x TC: %02x)\n",
- i,
- m_utlb[i].ASID,
- m_utlb[i].VPN << 10,
- m_utlb[i].V,
- m_utlb[i].PPN << 10,
- m_utlb[i].PSZ,
- m_utlb[i].SH,
- m_utlb[i].C,
- m_utlb[i].PPR,
- m_utlb[i].D,
- m_utlb[i].WT,
- m_utlb[i].SA,
- m_utlb[i].TC);
- }
+ // FIXME: potentially verbose, move to logmacro.h pattern
+ // cfr. MMU Check_4 in v2.xx DC CHECKER
+ logerror("(entry %02x | ASID: %02x VPN: %08x V: %02x PPN: %08x SZ: %02x SH: %02x C: %02x PPR: %02x D: %02x WT %02x: SA: %02x TC: %02x)\n",
+ i,
+ m_utlb[i].ASID,
+ m_utlb[i].VPN << 10,
+ m_utlb[i].V,
+ m_utlb[i].PPN << 10,
+ m_utlb[i].PSZ,
+ m_utlb[i].SH,
+ m_utlb[i].C,
+ m_utlb[i].PPR,
+ m_utlb[i].D,
+ m_utlb[i].WT,
+ m_utlb[i].SA,
+ m_utlb[i].TC);
}
}
}
- break;
+ }
+}
+
+uint8_t sh4_base_device::basra_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_basra;
+}
+
+void sh4_base_device::basra_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_basra);
+ logerror("basra_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::basrb_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_basrb;
+}
+
+void sh4_base_device::basrb_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_basrb);
+ logerror("basrb_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::ccr_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_ccr;
+}
+
+void sh4_base_device::ccr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_ccr);
+ logerror("ccr_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::tra_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_tra;
+}
+
+void sh4_base_device::tra_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_tra);
+ logerror("tra_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::expevt_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_expevt;
+}
+
+void sh4_base_device::expevt_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_expevt);
+ logerror("expevt: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::intevt_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_intevt;
+}
+
+void sh4_base_device::intevt_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_intevt);
+ logerror("intevt_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::ptea_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_ptea;
+}
+
+void sh4_base_device::ptea_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ /*
+ ---- ---- ---- ---- ---- ---- ---- TSSS
+
+ same format as data array 2 of the utlb
+ */
+ COMBINE_DATA(&m_ptea);
+}
+
+uint32_t sh4_base_device::qacr0_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_qacr0;
+}
+
+void sh4_base_device::qacr0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_qacr0);
+}
+
+uint32_t sh4_base_device::qacr1_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_qacr1;
+}
+
+void sh4_base_device::qacr1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_qacr1);
+}
+
+// UBC
+uint32_t sh4_base_device::bara_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_bara;
+}
+
+void sh4_base_device::bara_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_bara);
+ logerror("bara_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::bamra_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_bamra;
+}
+
+void sh4_base_device::bamra_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_bamra);
+ logerror("bamra_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint16_t sh4_base_device::bbra_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_bbra;
+}
+
+void sh4_base_device::bbra_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_bbra);
+ logerror("bbra_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::barb_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_barb;
+}
+
+void sh4_base_device::barb_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_barb);
+ logerror("barb_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::bamrb_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_bamrb;
+}
+
+void sh4_base_device::bamrb_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_bamrb);
+ logerror("bamrb_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint16_t sh4_base_device::bbrb_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_bbrb;
+}
+
+void sh4_base_device::bbrb_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_bbrb);
+ logerror("bbrb_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::bdrb_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_bdrb;
+}
+void sh4_base_device::bdrb_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_bdrb);
+ logerror("bdrb_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::bdmrb_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_bdmrb;
+}
+
+void sh4_base_device::bdmrb_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_bdmrb);
+ logerror("bdmrb_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint16_t sh4_base_device::brcr_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_brcr;
+}
+
+void sh4_base_device::brcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_brcr);
+ logerror("brcr_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+// BSC
+uint32_t sh4_base_device::bcr1_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_bcr1;
+}
+
+void sh4_base_device::bcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_bcr1);
+ logerror("bcr1_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint16_t sh4_base_device::bcr2_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_bcr2;
+}
+
+void sh4_base_device::bcr2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_bcr2);
+ logerror("bcr2_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::wcr1_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_wcr1;
+}
+
+void sh4_base_device::wcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_wcr1);
+ logerror("wcr1_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::wcr2_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_wcr2;
+}
+
+void sh4_base_device::wcr2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_wcr2);
+ logerror("wcr2_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::wcr3_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_wcr3;
+}
+
+void sh4_base_device::wcr3_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_wcr3);
+ logerror("wcr3_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::mcr_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_mcr;
+}
+
+void sh4_base_device::mcr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_mcr);
+ logerror("mcr_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint16_t sh4_base_device::pcr_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_pcr;
+}
+
+void sh4_base_device::pcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_pcr);
+ logerror("pcr_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+uint16_t sh4_base_device::rtcsr_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_rtcsr;
+}
+
+void sh4_base_device::rtcsr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
// Memory refresh
- case RTCSR:
- m_m[RTCSR] &= 255;
- if ((old >> 3) & 7)
- m_m[RTCNT] = compute_ticks_refresh_timer(m_refresh_timer, m_bus_clock, m_refresh_timer_base, rtcnt_div[(old >> 3) & 7]) & 0xff;
- if ((m_m[RTCSR] >> 3) & 7)
- { // activated
- sh4_refresh_timer_recompute();
- }
- else
- {
- m_refresh_timer->adjust(attotime::never);
- }
- break;
+ uint16_t old = m_rtcsr;
+ COMBINE_DATA(&m_rtcsr);
+ m_rtcsr &= 255;
+ if ((old >> 3) & 7)
+ m_rtcnt = compute_ticks_refresh_timer(m_refresh_timer, m_bus_clock, m_refresh_timer_base, rtcnt_div[(old >> 3) & 7]) & 0xff;
+ if ((m_rtcsr >> 3) & 7)
+ { // activated
+ sh4_refresh_timer_recompute();
+ }
+ else
+ {
+ m_refresh_timer->adjust(attotime::never);
+ }
+}
- case RTCNT:
- m_m[RTCNT] &= 255;
- if ((m_m[RTCSR] >> 3) & 7)
- { // active
- sh4_refresh_timer_recompute();
- }
- break;
-
- case RTCOR:
- m_m[RTCOR] &= 255;
- if ((m_m[RTCSR] >> 3) & 7)
- { // active
- m_m[RTCNT] = compute_ticks_refresh_timer(m_refresh_timer, m_bus_clock, m_refresh_timer_base, rtcnt_div[(m_m[RTCSR] >> 3) & 7]) & 0xff;
- sh4_refresh_timer_recompute();
- }
- break;
+uint16_t sh4_base_device::rtcnt_r(offs_t offset, uint16_t mem_mask)
+{
+ if ((m_rtcsr >> 3) & 7)
+ { // activated
+ //((double)rtcnt_div[(m_rtcsr >> 3) & 7] / (double)100000000)
+ //return (refresh_timer_base + (m_refresh_timer->elapsed() * (double)100000000) / (double)rtcnt_div[(m_rtcsr >> 3) & 7]) & 0xff;
+ return compute_ticks_refresh_timer(m_refresh_timer, m_bus_clock, m_refresh_timer_base, rtcnt_div[(m_rtcsr >> 3) & 7]) & 0xff;
+ }
+ else
+ return m_rtcnt;
+}
- case RFCR:
- m_m[RFCR] &= 1023;
- break;
+void sh4_base_device::rtcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_rtcnt);
+ m_rtcnt &= 255;
+ if ((m_rtcsr >> 3) & 7)
+ { // active
+ sh4_refresh_timer_recompute();
+ }
+}
- // RTC
- case RCR1:
- if ((m_m[RCR1] & 8) && (~old & 8)) // 0 -> 1
- m_m[RCR1] ^= 1;
- break;
+uint16_t sh4_base_device::rtcor_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_rtcor;
+}
- case RCR2:
- if (m_m[RCR2] & 2)
- {
- m_m[R64CNT] = 0;
- m_m[RCR2] ^= 2;
- }
- if (m_m[RCR2] & 4)
- {
- m_m[R64CNT] = 0;
- if (m_m[RSECCNT] >= 30)
- increment_rtc_time(1);
- m_m[RSECCNT] = 0;
- }
- if ((m_m[RCR2] & 8) && (~old & 8))
- { // 0 -> 1
- m_rtc_timer->adjust(attotime::from_hz(128));
- }
- else if (~m_m[RCR2] & 8)
- { // 0
- m_rtc_timer->adjust(attotime::never);
- }
- break;
-
-/*********************************************************************************************************************
- TMU (Timer Unit)
-*********************************************************************************************************************/
- case SH4_TSTR_ADDR: sh4_handle_tstr_addr_w(data, mem_mask); break;
- case SH4_TCR0_ADDR: sh4_handle_tcr0_addr_w(data, mem_mask); break;
- case SH4_TCR1_ADDR: sh4_handle_tcr1_addr_w(data, mem_mask); break;
- case SH4_TCR2_ADDR: sh4_handle_tcr2_addr_w(data, mem_mask); break;
- case SH4_TCOR0_ADDR: sh4_handle_tcor0_addr_w(data, mem_mask); break;
- case SH4_TCNT0_ADDR: sh4_handle_tcnt0_addr_w(data, mem_mask); break;
- case SH4_TCOR1_ADDR: sh4_handle_tcor1_addr_w(data, mem_mask); break;
- case SH4_TCNT1_ADDR: sh4_handle_tcnt1_addr_w(data, mem_mask); break;
- case SH4_TCOR2_ADDR: sh4_handle_tcor2_addr_w(data, mem_mask); break;
- case SH4_TCNT2_ADDR: sh4_handle_tcnt2_addr_w(data, mem_mask); break;
- case SH4_TOCR_ADDR: sh4_handle_tocr_addr_w(data, mem_mask); break; // not supported
- case SH4_TCPR2_ADDR: sh4_handle_tcpr2_addr_w(data, mem_mask); break; // not supported
-/*********************************************************************************************************************
- INTC (Interrupt Controller)
-*********************************************************************************************************************/
- case ICR:
- m_m[ICR] = (m_m[ICR] & 0x7fff) | (old & 0x8000);
- break;
- case IPRA: sh4_handler_ipra_w(data, mem_mask); break;
- case IPRB:
- m_exception_priority[SH4_INTC_SCI1ERI] = INTPRI((m_m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1ERI);
- m_exception_priority[SH4_INTC_SCI1RXI] = INTPRI((m_m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1RXI);
- m_exception_priority[SH4_INTC_SCI1TXI] = INTPRI((m_m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1TXI);
- m_exception_priority[SH4_INTC_SCI1TEI] = INTPRI((m_m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1TEI);
- m_exception_priority[SH4_INTC_RCMI] = INTPRI((m_m[IPRB] & 0x0f00) >> 8, SH4_INTC_RCMI);
- m_exception_priority[SH4_INTC_ROVI] = INTPRI((m_m[IPRB] & 0x0f00) >> 8, SH4_INTC_ROVI);
- m_exception_priority[SH4_INTC_ITI] = INTPRI((m_m[IPRB] & 0xf000) >> 12, SH4_INTC_ITI);
- sh4_exception_recompute();
- break;
- case IPRC:
- m_exception_priority[SH4_INTC_HUDI] = INTPRI(m_m[IPRC] & 0x000f, SH4_INTC_HUDI);
- m_exception_priority[SH4_INTC_SCIFERI] = INTPRI((m_m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFERI);
- m_exception_priority[SH4_INTC_SCIFRXI] = INTPRI((m_m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFRXI);
- m_exception_priority[SH4_INTC_SCIFBRI] = INTPRI((m_m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFBRI);
- m_exception_priority[SH4_INTC_SCIFTXI] = INTPRI((m_m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFTXI);
- m_exception_priority[SH4_INTC_DMTE0] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE0);
- m_exception_priority[SH4_INTC_DMTE1] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE1);
- m_exception_priority[SH4_INTC_DMTE2] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE2);
- m_exception_priority[SH4_INTC_DMTE3] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE3);
- m_exception_priority[SH4_INTC_DMAE] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMAE);
- m_exception_priority[SH4_INTC_GPOI] = INTPRI((m_m[IPRC] & 0xf000) >> 12, SH4_INTC_GPOI);
- sh4_exception_recompute();
- break;
-/*********************************************************************************************************************
- DMAC (DMA Controller)
-*********************************************************************************************************************/
- case SH4_SAR0_ADDR: sh4_handle_sar0_addr_w(data, mem_mask); break;
- case SH4_SAR1_ADDR: sh4_handle_sar1_addr_w(data, mem_mask); break;
- case SH4_SAR2_ADDR: sh4_handle_sar2_addr_w(data, mem_mask); break;
- case SH4_SAR3_ADDR: sh4_handle_sar3_addr_w(data, mem_mask); break;
- case SH4_DAR0_ADDR: sh4_handle_dar0_addr_w(data, mem_mask); break;
- case SH4_DAR1_ADDR: sh4_handle_dar1_addr_w(data, mem_mask); break;
- case SH4_DAR2_ADDR: sh4_handle_dar2_addr_w(data, mem_mask); break;
- case SH4_DAR3_ADDR: sh4_handle_dar3_addr_w(data, mem_mask); break;
- case SH4_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(data, mem_mask); break;
- case SH4_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(data, mem_mask); break;
- case SH4_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(data, mem_mask); break;
- case SH4_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(data, mem_mask); break;
- case SH4_CHCR0_ADDR: sh4_handle_chcr0_addr_w(data, mem_mask); break;
- case SH4_CHCR1_ADDR: sh4_handle_chcr1_addr_w(data, mem_mask); break;
- case SH4_CHCR2_ADDR: sh4_handle_chcr2_addr_w(data, mem_mask); break;
- case SH4_CHCR3_ADDR: sh4_handle_chcr3_addr_w(data, mem_mask); break;
- case SH4_DMAOR_ADDR: sh4_handle_dmaor_addr_w(data, mem_mask); break;
-/*********************************************************************************************************************
- Store Queues
-*********************************************************************************************************************/
- case QACR0:
- case QACR1:
- break;
-/*********************************************************************************************************************
- I/O
-*********************************************************************************************************************/
- case PCTRA:
- m_ioport16_pullup = 0;
- m_ioport16_direction = 0;
- for (int a = 0; a < 16; a++)
- {
- m_ioport16_direction |= (m_m[PCTRA] & (1 << (a * 2))) >> a;
- m_ioport16_pullup |= (m_m[PCTRA] & (1 << (a * 2 + 1))) >> (a + 1);
- }
- m_ioport16_direction &= 0xffff;
- m_ioport16_pullup = (m_ioport16_pullup | m_ioport16_direction) ^ 0xffff;
- if (m_m[BCR2] & 1)
- m_io->write_dword(SH4_IOPORT_16, (uint64_t)(m_m[PDTRA] & m_ioport16_direction) | ((uint64_t)m_m[PCTRA] << 16));
- break;
- case PDTRA:
- if (m_m[BCR2] & 1)
- m_io->write_dword(SH4_IOPORT_16, (uint64_t)(m_m[PDTRA] & m_ioport16_direction) | ((uint64_t)m_m[PCTRA] << 16));
- break;
- case PCTRB:
- m_ioport4_pullup = 0;
- m_ioport4_direction = 0;
- for (int a = 0; a < 4; a++)
- {
- m_ioport4_direction |= (m_m[PCTRB] & (1 << (a * 2))) >> a;
- m_ioport4_pullup |= (m_m[PCTRB] & (1 << (a * 2 + 1))) >> (a + 1);
- }
- m_ioport4_direction &= 0xf;
- m_ioport4_pullup = (m_ioport4_pullup | m_ioport4_direction) ^ 0xf;
- if (m_m[BCR2] & 1)
- m_io->write_dword(SH4_IOPORT_4, (m_m[PDTRB] & m_ioport4_direction) | (m_m[PCTRB] << 16));
- break;
- case PDTRB:
- if (m_m[BCR2] & 1)
- m_io->write_dword(SH4_IOPORT_4, (m_m[PDTRB] & m_ioport4_direction) | (m_m[PCTRB] << 16));
- break;
-
- case SCBRR2:
- break;
-
- case SCSPTR2: //trips often in aristocrat mk-6
- break;
-
- default:
- logerror("sh4_internal_w: Unmapped write %08x, %08x @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), data, mem_mask);
- break;
+void sh4_base_device::rtcor_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_rtcor);
+ m_rtcor &= 255;
+ if ((m_rtcsr >> 3) & 7)
+ { // active
+ m_rtcnt = compute_ticks_refresh_timer(m_refresh_timer, m_bus_clock, m_refresh_timer_base, rtcnt_div[(m_rtcsr >> 3) & 7]) & 0xff;
+ sh4_refresh_timer_recompute();
}
}
-uint32_t sh4_base_device::sh4_internal_r(offs_t offset, uint32_t mem_mask)
+uint16_t sh4_base_device::rfcr_r(offs_t offset, uint16_t mem_mask)
{
- if (m_cpu_type != CPU_TYPE_SH4)
- fatalerror("sh4_internal_r uses m_m[] with SH3\n");
+ return m_rfcr;
+}
- uint32_t addr = (offset << 2) + 0xfe000000;
- offset = ((addr & 0xfc) >> 2) | ((addr & 0x1fe0000) >> 11);
+void sh4_base_device::rfcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_rfcr);
+ m_rfcr &= 1023;
+}
-// printf("sh4_internal_r: Read %08x (%x) @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), offset, mem_mask);
+uint32_t sh4_base_device::pctra_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pctra;
+}
- switch (offset)
+void sh4_base_device::pctra_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pctra);
+ m_ioport16_pullup = 0;
+ m_ioport16_direction = 0;
+ for (int a = 0; a < 16; a++)
{
- case VERSION:
- return PVR_SH7091; // 0x040205c1, this is what a real SH7091 in a Dreamcast returns - the later Naomi BIOSes check and care!
- case PRR:
- return 0;
- case IPRD:
- return 0x00000000; // SH7750 ignores writes here and always returns zero
- case RTCNT:
- if ((m_m[RTCSR] >> 3) & 7)
- { // activated
- //((double)rtcnt_div[(m_m[RTCSR] >> 3) & 7] / (double)100000000)
- //return (refresh_timer_base + (m_refresh_timer->elapsed() * (double)100000000) / (double)rtcnt_div[(m_m[RTCSR] >> 3) & 7]) & 0xff;
- return compute_ticks_refresh_timer(m_refresh_timer, m_bus_clock, m_refresh_timer_base, rtcnt_div[(m_m[RTCSR] >> 3) & 7]) & 0xff;
- }
- else
- return m_m[RTCNT];
-
-/*********************************************************************************************************************
- INTC (Interrupt Controller)
-*********************************************************************************************************************/
-
- case IPRA:
- return m_SH4_IPRA;
-
-/*********************************************************************************************************************
- TMU (Timer Unit)
-*********************************************************************************************************************/
- case SH4_TSTR_ADDR: return sh4_handle_tstr_addr_r(mem_mask);
- case SH4_TCR0_ADDR: return sh4_handle_tcr0_addr_r(mem_mask);
- case SH4_TCR1_ADDR: return sh4_handle_tcr1_addr_r(mem_mask);
- case SH4_TCR2_ADDR: return sh4_handle_tcr2_addr_r(mem_mask);
- case SH4_TCNT0_ADDR: return sh4_handle_tcnt0_addr_r(mem_mask);
- case SH4_TCNT1_ADDR: return sh4_handle_tcnt1_addr_r(mem_mask);
- case SH4_TCNT2_ADDR: return sh4_handle_tcnt2_addr_r(mem_mask);
- case SH4_TCOR0_ADDR: return sh4_handle_tcor0_addr_r(mem_mask);
- case SH4_TCOR1_ADDR: return sh4_handle_tcor1_addr_r(mem_mask);
- case SH4_TCOR2_ADDR: return sh4_handle_tcor2_addr_r(mem_mask);
- case SH4_TOCR_ADDR: return sh4_handle_tocr_addr_r(mem_mask); // not supported
- case SH4_TCPR2_ADDR: return sh4_handle_tcpr2_addr_r(mem_mask); // not supported
-/*********************************************************************************************************************
- DMAC (DMA Controller)
-*********************************************************************************************************************/
- case SH4_SAR0_ADDR: return sh4_handle_sar0_addr_r(mem_mask);
- case SH4_SAR1_ADDR: return sh4_handle_sar1_addr_r(mem_mask);
- case SH4_SAR2_ADDR: return sh4_handle_sar2_addr_r(mem_mask);
- case SH4_SAR3_ADDR: return sh4_handle_sar3_addr_r(mem_mask);
- case SH4_DAR0_ADDR: return sh4_handle_dar0_addr_r(mem_mask);
- case SH4_DAR1_ADDR: return sh4_handle_dar1_addr_r(mem_mask);
- case SH4_DAR2_ADDR: return sh4_handle_dar2_addr_r(mem_mask);
- case SH4_DAR3_ADDR: return sh4_handle_dar3_addr_r(mem_mask);
- case SH4_DMATCR0_ADDR: return sh4_handle_dmatcr0_addr_r(mem_mask);
- case SH4_DMATCR1_ADDR: return sh4_handle_dmatcr1_addr_r(mem_mask);
- case SH4_DMATCR2_ADDR: return sh4_handle_dmatcr2_addr_r(mem_mask);
- case SH4_DMATCR3_ADDR: return sh4_handle_dmatcr3_addr_r(mem_mask);
- case SH4_CHCR0_ADDR: return sh4_handle_chcr0_addr_r(mem_mask);
- case SH4_CHCR1_ADDR: return sh4_handle_chcr1_addr_r(mem_mask);
- case SH4_CHCR2_ADDR: return sh4_handle_chcr2_addr_r(mem_mask);
- case SH4_CHCR3_ADDR: return sh4_handle_chcr3_addr_r(mem_mask);
- case SH4_DMAOR_ADDR: return sh4_handle_dmaor_addr_r(mem_mask);
-/*********************************************************************************************************************
- I/O Ports
-*********************************************************************************************************************/
-
- case PDTRA:
- if (m_m[BCR2] & 1)
- return (m_io->read_dword(SH4_IOPORT_16) & ~m_ioport16_direction) | (m_m[PDTRA] & m_ioport16_direction);
- break;
- case PDTRB:
- if (m_m[BCR2] & 1)
- return (m_io->read_dword(SH4_IOPORT_4) & ~m_ioport4_direction) | (m_m[PDTRB] & m_ioport4_direction);
- break;
-
- // SCIF (UART with FIFO)
- case SCFSR2:
- return 0x60; //read-only status register
+ m_ioport16_direction |= (m_pctra & (1 << (a * 2))) >> a;
+ m_ioport16_pullup |= (m_pctra & (1 << (a * 2 + 1))) >> (a + 1);
}
- return m_m[offset];
+ m_ioport16_direction &= 0xffff;
+ m_ioport16_pullup = (m_ioport16_pullup | m_ioport16_direction) ^ 0xffff;
+ if (m_bcr2 & 1)
+ m_io->write_dword(SH4_IOPORT_16, (uint64_t)(m_pdtra & m_ioport16_direction) | ((uint64_t)m_pctra << 16));
}
-void sh34_base_device::set_frt_input(int state)
+uint16_t sh4_base_device::pdtra_r(offs_t offset, uint16_t mem_mask)
{
- if (m_cpu_type != CPU_TYPE_SH4)
- fatalerror("sh4_set_frt_input uses m_m[] with SH3\n");
+ if (m_bcr2 & 1)
+ return (m_io->read_dword(SH4_IOPORT_16) & ~m_ioport16_direction) | (m_pdtra & m_ioport16_direction);
+
+ return m_pdtra;
+}
+
+void sh4_base_device::pdtra_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_pdtra);
+ if (m_bcr2 & 1)
+ m_io->write_dword(SH4_IOPORT_16, (uint64_t)(m_pdtra & m_ioport16_direction) | ((uint64_t)m_pctra << 16));
+}
+
+uint32_t sh4_base_device::pctrb_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pctrb;
+}
+
+void sh4_base_device::pctrb_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pctrb);
+ m_ioport4_pullup = 0;
+ m_ioport4_direction = 0;
+ for (int a = 0; a < 4; a++)
+ {
+ m_ioport4_direction |= (m_pctrb & (1 << (a * 2))) >> a;
+ m_ioport4_pullup |= (m_pctrb & (1 << (a * 2 + 1))) >> (a + 1);
+ }
+ m_ioport4_direction &= 0xf;
+ m_ioport4_pullup = (m_ioport4_pullup | m_ioport4_direction) ^ 0xf;
+ if (m_bcr2 & 1)
+ m_io->write_dword(SH4_IOPORT_4, (m_pdtrb & m_ioport4_direction) | (m_pctrb << 16));
+}
+
+uint16_t sh4_base_device::pdtrb_r(offs_t offset, uint16_t mem_mask)
+{
+ if (m_bcr2 & 1)
+ return (m_io->read_dword(SH4_IOPORT_4) & ~m_ioport4_direction) | (m_pdtrb & m_ioport4_direction);
+
+ return m_pdtrb;
+}
+
+void sh4_base_device::pdtrb_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_pdtrb);
+ if (m_bcr2 & 1)
+ m_io->write_dword(SH4_IOPORT_4, (m_pdtrb & m_ioport4_direction) | (m_pctrb << 16));
+}
+
+uint16_t sh4_base_device::gpioic_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_gpioic;
+}
+
+void sh4_base_device::gpioic_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_gpioic);
+ logerror("gpioic_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+void sh4_base_device::sdmr2_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ logerror("sdmr2_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+void sh4_base_device::sdmr3_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ logerror("sdmr3_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+// BSC 7750R
+uint16_t sh4_base_device::bcr3_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_bcr3;
+}
+
+void sh4_base_device::bcr3_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_bcr3);
+ logerror("bcr3_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::bcr4_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_bcr4;
+}
+
+void sh4_base_device::bcr4_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_bcr4);
+ logerror("bcr4_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+// DMAC 7750R
+uint32_t sh4_base_device::sar4_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_sar4;
+}
+
+void sh4_base_device::sar4_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_sar4);
+ logerror("sar4_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::dar4_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_dar4;
+}
+
+void sh4_base_device::dar4_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_dar4);
+ logerror("dar4_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::dmatcr4_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_dmatcr4;
+}
+
+void sh4_base_device::dmatcr4_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_dmatcr4);
+ logerror("dmatcr4_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::chcr4_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_chcr4;
+}
+
+void sh4_base_device::chcr4_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_chcr4);
+ logerror("chcr4_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::sar5_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_sar5;
+}
+
+void sh4_base_device::sar5_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_sar5);
+ logerror("sar5_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::dar5_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_dar5;
+}
+
+void sh4_base_device::dar5_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_dar5);
+ logerror("dar5_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::dmatcr5_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_dmatcr5;
+}
+
+void sh4_base_device::dmatcr5_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_dmatcr5);
+ logerror("dmatcr5_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::chcr5_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_chcr5;
+}
+
+void sh4_base_device::chcr5_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_chcr5);
+ logerror("chcr5_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::sar6_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_sar6;
+}
+
+void sh4_base_device::sar6_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_sar6);
+ logerror("sar6_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::dar6_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_dar6;
+}
+
+void sh4_base_device::dar6_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_dar6);
+ logerror("dar6_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::dmatcr6_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_dmatcr6;
+}
+
+void sh4_base_device::dmatcr6_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_dmatcr6);
+ logerror("dmatcr6_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::chcr6_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_chcr6;
+}
+
+void sh4_base_device::chcr6_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_chcr6);
+ logerror("chcr6_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::sar7_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_sar7;
+}
+
+void sh4_base_device::sar7_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_sar7);
+ logerror("sar7_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::dar7_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_dar7;
+}
+
+void sh4_base_device::dar7_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_dar7);
+ logerror("dar7_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::dmatcr7_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_dmatcr7;
+}
+
+void sh4_base_device::dmatcr7_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_dmatcr7);
+ logerror("dmatcr7_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::chcr7_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_chcr7;
+}
+
+void sh4_base_device::chcr7_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_chcr7);
+ logerror("chcr7_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+// CPG
+uint16_t sh4_base_device::frqcr_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_frqcr;
+}
+
+void sh4_base_device::frqcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_frqcr);
+ logerror("frqcr_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::stbcr_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_stbcr;
+}
+
+void sh4_base_device::stbcr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_stbcr);
+ logerror("stbcr_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::wtcnt_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_wtcnt;
+}
+
+void sh4_base_device::wtcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_wtcnt);
+ logerror("wtcnt_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::wtcsr_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_wtcsr;
+}
+
+void sh4_base_device::wtcsr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_wtcsr);
+ logerror("wtcsr_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::stbcr2_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_stbcr2;
+}
+
+void sh4_base_device::stbcr2_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_stbcr2);
+ logerror("stbcr2_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+// CPG 7750R
+uint32_t sh4_base_device::clkstp00_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_clkstp00;
+}
+
+void sh4_base_device::clkstp00_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_clkstp00);
+ logerror("clkstp00_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+void sh4_base_device::clkstpclr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ logerror("clkstpclr_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+// RTC
+uint8_t sh4_base_device::r64cnt_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_r64cnt;
+}
+
+uint8_t sh4_base_device::rseccnt_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_rseccnt;
+}
+
+void sh4_base_device::rseccnt_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rseccnt);
+}
+
+uint8_t sh4_base_device::rmincnt_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_rmincnt;
+}
+
+void sh4_base_device::rmincnt_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rmincnt);
+}
+
+uint8_t sh4_base_device::rhrcnt_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_rhrcnt;
+}
+
+void sh4_base_device::rhrcnt_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rhrcnt);
+}
+
+uint8_t sh4_base_device::rwkcnt_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_rwkcnt;
+}
+
+void sh4_base_device::rwkcnt_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rwkcnt);
+}
+
+uint8_t sh4_base_device::rdaycnt_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_rdaycnt;
+}
+
+void sh4_base_device::rdaycnt_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rdaycnt);
+}
+
+uint8_t sh4_base_device::rmoncnt_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_rmoncnt;
+}
+
+void sh4_base_device::rmoncnt_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rmoncnt);
+}
+
+uint16_t sh4_base_device::ryrcnt_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_ryrcnt;
+}
+
+void sh4_base_device::ryrcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_ryrcnt);
+}
+
+uint8_t sh4_base_device::rsecar_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_rsecar;
+}
+
+void sh4_base_device::rsecar_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rsecar);
+ logerror("rsecar_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::rminar_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_rminar;
+}
+
+void sh4_base_device::rminar_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rminar);
+ logerror("rminar_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::rhrar_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_rhrar;
+}
+
+void sh4_base_device::rhrar_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rhrar);
+ logerror("rhrar_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::rwkar_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_rwkar;
+}
+
+void sh4_base_device::rwkar_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rwkar);
+ logerror("rwkar_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::rdayar_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_rdayar;
+}
+
+void sh4_base_device::rdayar_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rdayar);
+ logerror("rdayar_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::rmonar_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_rmonar;
+}
+
+void sh4_base_device::rmonar_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rmonar);
+ logerror("rmonar_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::rcr1_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_rcr1;
+}
+
+void sh4_base_device::rcr1_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ uint8_t old = m_rcr1;
+ COMBINE_DATA(&m_rcr1);
+ if ((m_rcr1 & 8) && (~old & 8)) // 0 -> 1
+ m_rcr1 ^= 1;
+}
+
+uint8_t sh4_base_device::rcr2_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_rcr2;
+}
+
+void sh4_base_device::rcr2_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ uint8_t old = m_rcr2;
+ COMBINE_DATA(&m_rcr2);
+ if (m_rcr2 & 2)
+ {
+ m_r64cnt = 0;
+ m_rcr2 ^= 2;
+ }
+ if (m_rcr2 & 4)
+ {
+ m_r64cnt = 0;
+ if (m_rseccnt >= 30)
+ increment_rtc_time(1);
+ m_rseccnt = 0;
+ }
+ if ((m_rcr2 & 8) && (~old & 8))
+ { // 0 -> 1
+ m_rtc_timer->adjust(attotime::from_hz(128));
+ }
+ else if (~m_rcr2 & 8)
+ { // 0
+ m_rtc_timer->adjust(attotime::never);
+ }
+}
+
+// RTC 7750R
+uint8_t sh4_base_device::rcr3_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_rcr3;
+}
+
+void sh4_base_device::rcr3_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_rcr3);
+ logerror("rcr3_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint16_t sh4_base_device::ryrar_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_ryrar;
+}
+
+void sh4_base_device::ryrar_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_ryrar);
+ logerror("ryrar_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+// INTC
+uint16_t sh4_base_device::icr_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_icr;
+}
+
+void sh4_base_device::icr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ uint16_t old = m_icr;
+ COMBINE_DATA(&m_icr);
+ m_icr = (m_icr & 0x7fff) | (old & 0x8000);
+}
+
+uint16_t sh34_base_device::ipra_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_ipra;
+}
+
+void sh34_base_device::ipra_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_ipra);
+ /* 15 - 12 TMU0 */
+ /* 11 - 8 TMU1 */
+ /* 7 - 4 TMU2 */
+ /* 3 - 0 RTC */
+ m_exception_priority[SH4_INTC_ATI] = INTPRI(m_ipra & 0x000f, SH4_INTC_ATI);
+ m_exception_priority[SH4_INTC_PRI] = INTPRI(m_ipra & 0x000f, SH4_INTC_PRI);
+ m_exception_priority[SH4_INTC_CUI] = INTPRI(m_ipra & 0x000f, SH4_INTC_CUI);
+
+ m_exception_priority[SH4_INTC_TUNI2] = INTPRI((m_ipra & 0x00f0) >> 4, SH4_INTC_TUNI2);
+ m_exception_priority[SH4_INTC_TICPI2] = INTPRI((m_ipra & 0x00f0) >> 4, SH4_INTC_TICPI2);
+
+ m_exception_priority[SH4_INTC_TUNI1] = INTPRI((m_ipra & 0x0f00) >> 8, SH4_INTC_TUNI1);
+
+ m_exception_priority[SH4_INTC_TUNI0] = INTPRI((m_ipra & 0xf000) >> 12, SH4_INTC_TUNI0);
+
+ logerror("setting priorities TMU0 %01x TMU1 %01x TMU2 %01x RTC %01x\n", (m_ipra & 0xf000) >> 12, (m_ipra & 0x0f00) >> 8, (m_ipra & 0x00f0) >> 4, (m_ipra & 0x000f) >> 0);
+
+ sh4_exception_recompute();
+}
+
+uint16_t sh4_base_device::iprb_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_iprb;
+}
+
+void sh4_base_device::iprb_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_iprb);
+ m_exception_priority[SH4_INTC_SCI1ERI] = INTPRI((m_iprb & 0x00f0) >> 4, SH4_INTC_SCI1ERI);
+ m_exception_priority[SH4_INTC_SCI1RXI] = INTPRI((m_iprb & 0x00f0) >> 4, SH4_INTC_SCI1RXI);
+ m_exception_priority[SH4_INTC_SCI1TXI] = INTPRI((m_iprb & 0x00f0) >> 4, SH4_INTC_SCI1TXI);
+ m_exception_priority[SH4_INTC_SCI1TEI] = INTPRI((m_iprb & 0x00f0) >> 4, SH4_INTC_SCI1TEI);
+ m_exception_priority[SH4_INTC_RCMI] = INTPRI((m_iprb & 0x0f00) >> 8, SH4_INTC_RCMI);
+ m_exception_priority[SH4_INTC_ROVI] = INTPRI((m_iprb & 0x0f00) >> 8, SH4_INTC_ROVI);
+ m_exception_priority[SH4_INTC_ITI] = INTPRI((m_iprb & 0xf000) >> 12, SH4_INTC_ITI);
+ sh4_exception_recompute();
+}
+
+uint16_t sh4_base_device::iprc_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_iprc;
+}
+
+void sh4_base_device::iprc_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_iprc);
+ m_exception_priority[SH4_INTC_HUDI] = INTPRI(m_iprc & 0x000f, SH4_INTC_HUDI);
+ m_exception_priority[SH4_INTC_SCIFERI] = INTPRI((m_iprc & 0x00f0) >> 4, SH4_INTC_SCIFERI);
+ m_exception_priority[SH4_INTC_SCIFRXI] = INTPRI((m_iprc & 0x00f0) >> 4, SH4_INTC_SCIFRXI);
+ m_exception_priority[SH4_INTC_SCIFBRI] = INTPRI((m_iprc & 0x00f0) >> 4, SH4_INTC_SCIFBRI);
+ m_exception_priority[SH4_INTC_SCIFTXI] = INTPRI((m_iprc & 0x00f0) >> 4, SH4_INTC_SCIFTXI);
+ m_exception_priority[SH4_INTC_DMTE0] = INTPRI((m_iprc & 0x0f00) >> 8, SH4_INTC_DMTE0);
+ m_exception_priority[SH4_INTC_DMTE1] = INTPRI((m_iprc & 0x0f00) >> 8, SH4_INTC_DMTE1);
+ m_exception_priority[SH4_INTC_DMTE2] = INTPRI((m_iprc & 0x0f00) >> 8, SH4_INTC_DMTE2);
+ m_exception_priority[SH4_INTC_DMTE3] = INTPRI((m_iprc & 0x0f00) >> 8, SH4_INTC_DMTE3);
+ m_exception_priority[SH4_INTC_DMAE] = INTPRI((m_iprc & 0x0f00) >> 8, SH4_INTC_DMAE);
+ m_exception_priority[SH4_INTC_GPOI] = INTPRI((m_iprc & 0xf000) >> 12, SH4_INTC_GPOI);
+ sh4_exception_recompute();
+}
+
+// INTC 7750S
+uint16_t sh4_base_device::iprd_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_iprd;
+}
+
+void sh4_base_device::iprd_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_iprd);
+ logerror("iprd_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+// INTC 7750R
+uint32_t sh4_base_device::intpri00_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_intpri00;
+}
+
+void sh4_base_device::intpri00_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_intpri00);
+ logerror("intpri00_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::intreq00_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_intreq00;
+}
+
+void sh4_base_device::intreq00_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_intreq00);
+ logerror("intreq00_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::intmsk00_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_intmsk00;
+}
+
+void sh4_base_device::intmsk00_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_intmsk00);
+ logerror("intmsk00_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+void sh4_base_device::intmskclr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ logerror("intmskclr_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+// TMU 7750R
+uint8_t sh4_base_device::tstr2_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_tstr2;
+}
+
+void sh4_base_device::tstr2_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_tstr2);
+ logerror("tstr2_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::tcor3_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_tcor3;
+}
+
+void sh4_base_device::tcor3_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_tcor3);
+ logerror("tcor3_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::tcnt3_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_tcnt3;
+}
+
+void sh4_base_device::tcnt3_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_tcnt3);
+ logerror("tcnt3_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint16_t sh4_base_device::tcr3_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_tcr3;
+}
+
+void sh4_base_device::tcr3_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_tcr3);
+ logerror("tcr3_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::tcor4_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_tcor4;
+}
+
+void sh4_base_device::tcor4_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_tcor4);
+ logerror("tcor4_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+uint32_t sh4_base_device::tcnt4_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_tcnt4;
+}
+
+void sh4_base_device::tcnt4_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_tcnt4);
+ logerror("tcnt4_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint16_t sh4_base_device::tcr4_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_tcr4;
+}
+
+void sh4_base_device::tcr4_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_tcr4);
+ logerror("tcr4_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+// SCI
+uint8_t sh4_base_device::scsmr1_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_scsmr1;
+}
+
+void sh4_base_device::scsmr1_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scsmr1);
+ logerror("scsmr1_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::scbrr1_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_scbrr1;
+}
+
+void sh4_base_device::scbrr1_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scbrr1);
+ logerror("scbrr1_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::scscr1_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_scscr1;
+}
+
+void sh4_base_device::scscr1_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scscr1);
+ logerror("scscr1_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::sctdr1_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_sctdr1;
+}
+
+void sh4_base_device::sctdr1_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_sctdr1);
+ logerror("sctdr1_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::scssr1_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_scssr1;
+}
+
+void sh4_base_device::scssr1_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scssr1);
+ logerror("scssr1_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::scrdr1_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_scrdr1;
+}
+
+uint8_t sh4_base_device::scscmr1_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_scscmr1;
+}
+
+void sh4_base_device::scscmr1_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scscmr1);
+ logerror("scscmr1_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::scsptr1_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_scsptr1;
+}
+
+void sh4_base_device::scsptr1_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scsptr1);
+ logerror("scsptr1_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+// SCIF
+uint16_t sh4_base_device::scsmr2_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_scsmr2;
+}
+
+void sh4_base_device::scsmr2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_scsmr2);
+ logerror("scsmr2_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::scbrr2_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_scbrr2;
+}
+
+void sh4_base_device::scbrr2_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scbrr2);
+ logerror("scbrr2_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint16_t sh4_base_device::scscr2_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_scscr2;
+}
+
+void sh4_base_device::scscr2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_scscr2);
+ logerror("scscr2_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::scftdr2_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_scftdr2;
+}
+
+void sh4_base_device::scftdr2_w(offs_t offset, uint8_t data, uint8_t mem_mask)
+{
+ COMBINE_DATA(&m_scftdr2);
+ logerror("scftdr2_w: Unmapped write %02x @ %02x\n", data, mem_mask);
+}
+
+uint16_t sh4_base_device::scfsr2_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_scfsr2;
+}
+
+void sh4_base_device::scfsr2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ m_scfsr2 &= data | 0xff0c;
+ logerror("scfsr2_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+uint8_t sh4_base_device::scfrdr2_r(offs_t offset, uint8_t mem_mask)
+{
+ return m_scfrdr2;
+}
+
+uint16_t sh4_base_device::scfcr2_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_scfcr2;
+}
+
+void sh4_base_device::scfcr2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_scfcr2);
+ logerror("scfcr2_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+uint16_t sh4_base_device::scfdr2_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_scfdr2;
+}
+
+uint16_t sh4_base_device::scsptr2_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_scsptr2;
+}
+
+void sh4_base_device::scsptr2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_scsptr2);
+ //trips often in aristocrat mk-6
+}
+
+uint16_t sh4_base_device::sclsr2_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_sclsr2;
+}
+
+void sh4_base_device::sclsr2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ m_sclsr2 &= data | 0xfffe;
+ logerror("sclsr2_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+// H-UDI
+uint16_t sh4_base_device::sdir_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_sdir;
+}
+
+void sh4_base_device::sdir_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_sdir);
+ logerror("sdir_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::sddr_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_sddr;
+}
+
+void sh4_base_device::sddr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_sddr);
+ logerror("sddr_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+// H-UDI 7750R
+uint16_t sh4_base_device::sdint_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_sdint;
+}
+
+void sh4_base_device::sdint_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_sdint);
+ logerror("sdint_w: Unmapped write %04x @ %04x\n", data, mem_mask);
+}
+
+// PCI 7751
+uint32_t sh4_base_device::pciconf0_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciconf0;
+}
+
+uint32_t sh4_base_device::pciconf1_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciconf1;
+}
+
+void sh4_base_device::pciconf1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciconf1);
+ logerror("pciconf1_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciconf2_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciconf2;
+}
+
+void sh4_base_device::pciconf2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciconf2);
+ logerror("pciconf2_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciconf3_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciconf3;
+}
+
+void sh4_base_device::pciconf3_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciconf3);
+ logerror("pciconf3_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciconf4_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciconf4;
+}
+
+void sh4_base_device::pciconf4_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciconf4);
+ logerror("pciconf4_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciconf5_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciconf5;
+}
+
+void sh4_base_device::pciconf5_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciconf5);
+ logerror("pciconf5_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciconf6_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciconf6;
+}
+
+void sh4_base_device::pciconf6_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciconf6);
+ logerror("pciconf6_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciconf7_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciconf7;
+}
+
+uint32_t sh4_base_device::pciconf8_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciconf8;
+}
+
+uint32_t sh4_base_device::pciconf9_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciconf9;
+}
+
+uint32_t sh4_base_device::pciconf10_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciconf10;
+}
+
+uint32_t sh4_base_device::pciconf11_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciconf11;
+}
+
+void sh4_base_device::pciconf11_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciconf11);
+ logerror("pciconf11_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciconf12_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciconf12;
+}
+
+uint32_t sh4_base_device::pciconf13_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciconf13;
+}
+
+uint32_t sh4_base_device::pciconf14_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciconf14;
+}
+
+uint32_t sh4_base_device::pciconf15_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciconf15;
+}
+
+void sh4_base_device::pciconf15_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciconf15);
+ logerror("pciconf15_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciconf16_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciconf16;
+}
+
+void sh4_base_device::pciconf16_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciconf16);
+ logerror("pciconf16_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciconf17_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciconf17;
+}
+
+void sh4_base_device::pciconf17_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciconf17);
+ logerror("pciconf17_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcicr_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcicr;
+}
+
+void sh4_base_device::pcicr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcicr);
+ logerror("pcicr_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcilsr0_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcilsr0;
+}
+
+void sh4_base_device::pcilsr0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcilsr0);
+ logerror("pcilsr0_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcilsr1_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcilsr1;
+}
+
+void sh4_base_device::pcilsr1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcilsr1);
+ logerror("pcilsr1_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcilar0_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcilar0;
+}
+
+void sh4_base_device::pcilar0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcilar0);
+ logerror("pcilar0_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcilar1_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcilar1;
+}
+
+void sh4_base_device::pcilar1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcilar1);
+ logerror("pcilar1_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciint_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciint;
+}
+
+void sh4_base_device::pciint_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciint);
+ logerror("pciint_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciintm_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciintm;
+}
+
+void sh4_base_device::pciintm_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciintm);
+ logerror("pciintm_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcialr_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcialr;
+}
+
+void sh4_base_device::pcialr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcialr);
+ logerror("pcialr_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciclr_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciclr;
+}
+
+void sh4_base_device::pciclr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciclr);
+ logerror("pciclr_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciaint_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciaint;
+}
+
+void sh4_base_device::pciaint_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciaint);
+ logerror("pciaint_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciaintm_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciaintm;
+}
+
+void sh4_base_device::pciaintm_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciaintm);
+ logerror("pciaintm_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcibllr_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcibllr;
+}
+
+void sh4_base_device::pcibllr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcibllr);
+ logerror("pcibllr_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcidmabt_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcidmabt;
+}
+
+void sh4_base_device::pcidmabt_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcidmabt);
+ logerror("pcidmabt_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcidpa0_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcidpa0;
+}
+
+void sh4_base_device::pcidpa0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcidpa0);
+ logerror("pcidpa0_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcidla0_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcidla0;
+}
+
+void sh4_base_device::pcidla0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcidla0);
+ logerror("pcidla0_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcidtc0_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcidtc0;
+}
+
+void sh4_base_device::pcidtc0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcidtc0);
+ logerror("pcidtc0_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcidcr0_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcidcr0;
+}
+
+void sh4_base_device::pcidcr0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcidcr0);
+ logerror("pcidcr0_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcidpa1_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcidpa1;
+}
+
+void sh4_base_device::pcidpa1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcidpa1);
+ logerror("pcidpa1_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcidla1_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcidla1;
+}
+
+void sh4_base_device::pcidla1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcidla1);
+ logerror("pcidla1_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcidtc1_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcidtc1;
+}
+
+void sh4_base_device::pcidtc1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcidtc1);
+ logerror("pcidtc1_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcidcr1_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcidcr1;
+}
+
+void sh4_base_device::pcidcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcidcr1);
+ logerror("pcidcr1_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcidpa2_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcidpa2;
+}
+
+void sh4_base_device::pcidpa2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcidpa2);
+ logerror("pcidpa2_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcidla2_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcidla2;
+}
+
+void sh4_base_device::pcidla2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcidla2);
+ logerror("pcidla2_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcidtc2_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcidtc2;
+}
+
+void sh4_base_device::pcidtc2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcidtc2);
+ logerror("pcidtc2_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcidcr2_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcidcr2;
+}
+
+void sh4_base_device::pcidcr2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcidcr2);
+ logerror("pcidcr2_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcidpa3_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcidpa3;
+}
+
+void sh4_base_device::pcidpa3_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcidpa3);
+ logerror("pcidpa3_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcidla3_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcidla3;
+}
+
+void sh4_base_device::pcidla3_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcidla3);
+ logerror("pcidla3_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcidtc3_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcidtc3;
+}
+
+void sh4_base_device::pcidtc3_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcidtc3);
+ logerror("pcidtc3_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcidcr3_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcidcr3;
+}
+
+void sh4_base_device::pcidcr3_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcidcr3);
+ logerror("pcidcr3_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcipar_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcipar;
+}
+
+void sh4_base_device::pcipar_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcipar);
+ logerror("pcipar_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcimbr_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcimbr;
+}
+
+void sh4_base_device::pcimbr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcimbr);
+ logerror("pcimbr_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciiobr_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciiobr;
+}
+
+void sh4_base_device::pciiobr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciiobr);
+ logerror("pciiobr_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcipint_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcipint;
+}
+
+void sh4_base_device::pcipint_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcipint);
+ logerror("pcipint_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcipintm_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcipintm;
+}
+
+void sh4_base_device::pcipintm_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcipintm);
+ logerror("pcipintm_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciclkr_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciclkr;
+}
+
+void sh4_base_device::pciclkr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciclkr);
+ logerror("pciclkr_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcibcr1_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcibcr1;
+}
+
+void sh4_base_device::pcibcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcibcr1);
+ logerror("pcibcr1_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcibcr2_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcibcr2;
+}
+
+void sh4_base_device::pcibcr2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcibcr2);
+ logerror("pcibcr2_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcibcr3_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcibcr3;
+}
+
+void sh4_base_device::pcibcr3_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcibcr3);
+ logerror("pcibcr3_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciwcr1_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciwcr1;
+}
+
+void sh4_base_device::pciwcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciwcr1);
+ logerror("pciwcr1_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciwcr2_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciwcr2;
+}
+
+void sh4_base_device::pciwcr2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciwcr2);
+ logerror("pciwcr2_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pciwcr3_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pciwcr3;
+}
+
+void sh4_base_device::pciwcr3_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pciwcr3);
+ logerror("pciwcr3_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcimcr_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcimcr;
+}
+
+void sh4_base_device::pcimcr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcimcr);
+ logerror("pcimcr_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcipctr_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcipctr;
+}
+
+void sh4_base_device::pcipctr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcipctr);
+ logerror("pcipctr_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcipdtr_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcipdtr;
+}
+
+void sh4_base_device::pcipdtr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcipdtr);
+ logerror("pcipdtr_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+uint32_t sh4_base_device::pcipdr_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_pcipdr;
+}
+
+void sh4_base_device::pcipdr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_pcipdr);
+ logerror("pcipdr_w: Unmapped write %08x @ %08x\n", data, mem_mask);
+}
+
+void sh34_base_device::set_frt_input(int state)
+{
if (m_sh2_state->m_frt_input == state)
{
return;
@@ -1068,6 +2757,7 @@ void sh34_base_device::set_frt_input(int state)
m_sh2_state->m_frt_input = state;
+#if 0
if (m_cpu_type == CPU_TYPE_SH4)
{
if (m_m[5] & 0x8000)
@@ -1090,7 +2780,6 @@ void sh34_base_device::set_frt_input(int state)
fatalerror("sh4_set_frt_input uses m_m[] with SH3\n");
}
-#if 0
sh4_timer_resync();
m_icr = m_frc;
m_m[4] |= ICF;
@@ -1148,7 +2837,7 @@ void sh34_base_device::execute_set_input(int irqline, int state) // set state of
if (m_nmi_line_state == state)
return;
- if (m_m[ICR] & 0x100)
+ if (m_icr & 0x100)
{
if (state == CLEAR_LINE && m_nmi_line_state == ASSERT_LINE) // rising
{
@@ -1167,14 +2856,14 @@ void sh34_base_device::execute_set_input(int irqline, int state) // set state of
}
}
if (state == CLEAR_LINE)
- m_m[ICR] ^= 0x8000;
+ m_icr ^= 0x8000;
else
- m_m[ICR] |= 0x8000;
+ m_icr |= 0x8000;
m_nmi_line_state = state;
}
else
{
- if (m_m[ICR] & 0x80) // four independent external interrupt sources
+ if (m_icr & 0x80) // four independent external interrupt sources
{
if (irqline > SH4_IRL3)
return;
diff --git a/src/devices/cpu/sh/sh4dmac.cpp b/src/devices/cpu/sh/sh4dmac.cpp
index 51607032f64..77d571c4477 100644
--- a/src/devices/cpu/sh/sh4dmac.cpp
+++ b/src/devices/cpu/sh/sh4dmac.cpp
@@ -21,27 +21,27 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_dmac_callback )
switch (channel)
{
case 0:
- m_SH4_DMATCR0 = 0;
- m_SH4_CHCR0 |= CHCR_TE;
- if (m_SH4_CHCR0 & CHCR_IE)
+ m_dmatcr0 = 0;
+ m_chcr0 |= CHCR_TE;
+ if (m_chcr0 & CHCR_IE)
sh4_exception_request(SH4_INTC_DMTE0);
break;
case 1:
- m_SH4_DMATCR1 = 0;
- m_SH4_CHCR1 |= CHCR_TE;
- if (m_SH4_CHCR1 & CHCR_IE)
+ m_dmatcr1 = 0;
+ m_chcr1 |= CHCR_TE;
+ if (m_chcr1 & CHCR_IE)
sh4_exception_request(SH4_INTC_DMTE1);
break;
case 2:
- m_SH4_DMATCR2 = 0;
- m_SH4_CHCR2 |= CHCR_TE;
- if (m_SH4_CHCR2 & CHCR_IE)
+ m_dmatcr2 = 0;
+ m_chcr2 |= CHCR_TE;
+ if (m_chcr2 & CHCR_IE)
sh4_exception_request(SH4_INTC_DMTE2);
break;
case 3:
- m_SH4_DMATCR3 = 0;
- m_SH4_CHCR3 |= CHCR_TE;
- if (m_SH4_CHCR3 & CHCR_IE)
+ m_dmatcr3 = 0;
+ m_chcr3 |= CHCR_TE;
+ if (m_chcr3 & CHCR_IE)
sh4_exception_request(SH4_INTC_DMTE3);
break;
}
@@ -99,7 +99,7 @@ int sh34_base_device::sh4_dma_transfer(int channel, int timermode, uint32_t chcr
src --;
if (incd == 2)
dst --;
- m_program->write_byte(dst, m_program->read_byte(src));
+ m_program->write_byte(dst & SH34_AM, m_program->read_byte(src & SH34_AM));
if (incs == 1)
src ++;
if (incd == 1)
@@ -115,7 +115,7 @@ int sh34_base_device::sh4_dma_transfer(int channel, int timermode, uint32_t chcr
src -= 2;
if (incd == 2)
dst -= 2;
- m_program->write_word(dst, m_program->read_word(src));
+ m_program->write_word(dst & SH34_AM, m_program->read_word(src & SH34_AM));
if (incs == 1)
src += 2;
if (incd == 1)
@@ -131,7 +131,7 @@ int sh34_base_device::sh4_dma_transfer(int channel, int timermode, uint32_t chcr
src -= 8;
if (incd == 2)
dst -= 8;
- m_program->write_qword(dst, m_program->read_qword(src));
+ m_program->write_qword(dst & SH34_AM, m_program->read_qword(src & SH34_AM));
if (incs == 1)
src += 8;
if (incd == 1)
@@ -148,7 +148,7 @@ int sh34_base_device::sh4_dma_transfer(int channel, int timermode, uint32_t chcr
src -= 4;
if (incd == 2)
dst -= 4;
- m_program->write_dword(dst, m_program->read_dword(src));
+ m_program->write_dword(dst & SH34_AM, m_program->read_dword(src & SH34_AM));
if (incs == 1)
src += 4;
if (incd == 1)
@@ -165,10 +165,10 @@ int sh34_base_device::sh4_dma_transfer(int channel, int timermode, uint32_t chcr
src -= 32;
if (incd == 2)
dst -= 32;
- m_program->write_qword(dst, m_program->read_qword(src));
- m_program->write_qword(dst + 8, m_program->read_qword(src + 8));
- m_program->write_qword(dst + 16, m_program->read_qword(src + 16));
- m_program->write_qword(dst + 24, m_program->read_qword(src + 24));
+ m_program->write_qword(dst & SH34_AM, m_program->read_qword(src & SH34_AM));
+ m_program->write_qword((dst + 8) & SH34_AM, m_program->read_qword((src + 8) & SH34_AM));
+ m_program->write_qword((dst + 16) & SH34_AM, m_program->read_qword((src + 16) & SH34_AM));
+ m_program->write_qword((dst + 24) & SH34_AM, m_program->read_qword((src + 24) & SH34_AM));
if (incs == 1)
src += 32;
if (incd == 1)
@@ -238,41 +238,41 @@ void sh34_base_device::sh4_dmac_check(int channel)
switch (channel)
{
case 0:
- sar = m_SH4_SAR0;
- dar = m_SH4_DAR0;
- chcr = m_SH4_CHCR0;
- dmatcr = m_SH4_DMATCR0;
+ sar = m_sar0;
+ dar = m_dar0;
+ chcr = m_chcr0;
+ dmatcr = m_dmatcr0;
break;
case 1:
- sar = m_SH4_SAR1;
- dar = m_SH4_DAR1;
- chcr = m_SH4_CHCR1;
- dmatcr = m_SH4_DMATCR1;
+ sar = m_sar1;
+ dar = m_dar1;
+ chcr = m_chcr1;
+ dmatcr = m_dmatcr1;
break;
case 2:
- sar = m_SH4_SAR2;
- dar = m_SH4_DAR2;
- chcr = m_SH4_CHCR2;
- dmatcr = m_SH4_DMATCR2;
+ sar = m_sar2;
+ dar = m_dar2;
+ chcr = m_chcr2;
+ dmatcr = m_dmatcr2;
break;
case 3:
- sar = m_SH4_SAR3;
- dar = m_SH4_DAR3;
- chcr = m_SH4_CHCR3;
- dmatcr = m_SH4_DMATCR3;
+ sar = m_sar3;
+ dar = m_dar3;
+ chcr = m_chcr3;
+ dmatcr = m_dmatcr3;
break;
default:
return;
}
- if (chcr & m_SH4_DMAOR & DMAOR_DME)
+ if (chcr & m_dmaor & DMAOR_DME)
{
if ((((chcr & CHCR_RS) >> 8) < 2) || (((chcr & CHCR_RS) >> 8) > 6))
return;
- if (!m_dma_timer_active[channel] && !(chcr & CHCR_TE) && !(m_SH4_DMAOR & (DMAOR_AE | DMAOR_NMIF)))
+ if (!m_dma_timer_active[channel] && !(chcr & CHCR_TE) && !(m_dmaor & (DMAOR_AE | DMAOR_NMIF)))
{
if (((chcr & CHCR_RS) >> 8) > 3)
sh4_dma_transfer(channel, 1, chcr, &sar, &dar, &dmatcr);
- else if ((m_SH4_DMAOR & DMAOR_DDT) == 0)
+ else if ((m_dmaor & DMAOR_DDT) == 0)
sh4_dma_transfer_device(channel, chcr, &sar, &dar, &dmatcr); // tell device we are ready to transfer
}
}
@@ -311,38 +311,38 @@ int sh34_base_device::sh4_dma_data(struct sh4_device_dma *s)
case 8:
if (m_dma_source_increment[channel] == 2)
m_dma_source[channel] -= 8;
- *(uint64_t *)data = m_program->read_qword(m_dma_source[channel] & ~7);
+ *(uint64_t *)data = m_program->read_qword(m_dma_source[channel] & SH34_AM & ~7);
if (m_dma_source_increment[channel] == 1)
m_dma_source[channel] += 8;
break;
case 1:
if (m_dma_source_increment[channel] == 2)
m_dma_source[channel]--;
- *(uint8_t *)data = m_program->read_byte(m_dma_source[channel]);
+ *(uint8_t *)data = m_program->read_byte(m_dma_source[channel] & SH34_AM);
if (m_dma_source_increment[channel] == 1)
m_dma_source[channel]++;
break;
case 2:
if (m_dma_source_increment[channel] == 2)
m_dma_source[channel] -= 2;
- *(uint16_t *)data = m_program->read_word(m_dma_source[channel] & ~1);
+ *(uint16_t *)data = m_program->read_word(m_dma_source[channel] & SH34_AM & ~1);
if (m_dma_source_increment[channel] == 1)
m_dma_source[channel] += 2;
break;
case 4:
if (m_dma_source_increment[channel] == 2)
m_dma_source[channel] -= 4;
- *(uint32_t *)data = m_program->read_dword(m_dma_source[channel] & ~3);
+ *(uint32_t *)data = m_program->read_dword(m_dma_source[channel] & SH34_AM & ~3);
if (m_dma_source_increment[channel] == 1)
m_dma_source[channel] += 4;
break;
case 32:
if (m_dma_source_increment[channel] == 2)
m_dma_source[channel] -= 32;
- *(uint64_t *)data = m_program->read_qword(m_dma_source[channel] & ~31);
- *((uint64_t *)data+1) = m_program->read_qword((m_dma_source[channel] & ~31)+8);
- *((uint64_t *)data+2) = m_program->read_qword((m_dma_source[channel] & ~31)+16);
- *((uint64_t *)data+3) = m_program->read_qword((m_dma_source[channel] & ~31)+24);
+ *(uint64_t *)data = m_program->read_qword(m_dma_source[channel] & SH34_AM & ~31);
+ *((uint64_t *)data+1) = m_program->read_qword((m_dma_source[channel] & SH34_AM & ~31)+8);
+ *((uint64_t *)data+2) = m_program->read_qword((m_dma_source[channel] & SH34_AM & ~31)+16);
+ *((uint64_t *)data+3) = m_program->read_qword((m_dma_source[channel] & SH34_AM & ~31)+24);
if (m_dma_source_increment[channel] == 1)
m_dma_source[channel] += 32;
break;
@@ -370,38 +370,38 @@ int sh34_base_device::sh4_dma_data(struct sh4_device_dma *s)
case 8:
if (m_dma_destination_increment[channel] == 2)
m_dma_destination[channel]-=8;
- m_program->write_qword(m_dma_destination[channel] & ~7, *(uint64_t *)data);
+ m_program->write_qword(m_dma_destination[channel] & SH34_AM & ~7, *(uint64_t *)data);
if (m_dma_destination_increment[channel] == 1)
m_dma_destination[channel]+=8;
break;
case 1:
if (m_dma_destination_increment[channel] == 2)
m_dma_destination[channel]--;
- m_program->write_byte(m_dma_destination[channel], *(uint8_t *)data);
+ m_program->write_byte(m_dma_destination[channel] & SH34_AM, *(uint8_t *)data);
if (m_dma_destination_increment[channel] == 1)
m_dma_destination[channel]++;
break;
case 2:
if (m_dma_destination_increment[channel] == 2)
m_dma_destination[channel]-=2;
- m_program->write_word(m_dma_destination[channel] & ~1, *(uint16_t *)data);
+ m_program->write_word(m_dma_destination[channel] & SH34_AM & ~1, *(uint16_t *)data);
if (m_dma_destination_increment[channel] == 1)
m_dma_destination[channel]+=2;
break;
case 4:
if (m_dma_destination_increment[channel] == 2)
m_dma_destination[channel]-=4;
- m_program->write_dword(m_dma_destination[channel] & ~3, *(uint32_t *)data);
+ m_program->write_dword(m_dma_destination[channel] & SH34_AM & ~3, *(uint32_t *)data);
if (m_dma_destination_increment[channel] == 1)
m_dma_destination[channel]+=4;
break;
case 32:
if (m_dma_destination_increment[channel] == 2)
m_dma_destination[channel]-=32;
- m_program->write_qword(m_dma_destination[channel] & ~31, *(uint64_t *)data);
- m_program->write_qword((m_dma_destination[channel] & ~31)+8, *((uint64_t *)data+1));
- m_program->write_qword((m_dma_destination[channel] & ~31)+16, *((uint64_t *)data+2));
- m_program->write_qword((m_dma_destination[channel] & ~31)+24, *((uint64_t *)data+3));
+ m_program->write_qword(m_dma_destination[channel] & SH34_AM & ~31, *(uint64_t *)data);
+ m_program->write_qword((m_dma_destination[channel] & SH34_AM & ~31)+8, *((uint64_t *)data+1));
+ m_program->write_qword((m_dma_destination[channel] & SH34_AM & ~31)+16, *((uint64_t *)data+2));
+ m_program->write_qword((m_dma_destination[channel] & SH34_AM & ~31)+24, *((uint64_t *)data+3));
if (m_dma_destination_increment[channel] == 1)
m_dma_destination[channel]+=32;
break;
@@ -434,44 +434,44 @@ void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
{
case 0:
if (s->mode & 1)
- s->source = m_SH4_SAR0;
+ s->source = m_sar0;
if (s->mode & 2)
- m_SH4_SAR0 = s->source;
+ m_sar0 = s->source;
if (s->mode & 4)
- s->destination = m_SH4_DAR0;
+ s->destination = m_dar0;
if (s->mode & 8)
- m_SH4_DAR0 = s->destination;
+ m_dar0 = s->destination;
break;
case 1:
if (s->mode & 1)
- s->source = m_SH4_SAR1;
+ s->source = m_sar1;
if (s->mode & 2)
- m_SH4_SAR1 = s->source;
+ m_sar1 = s->source;
if (s->mode & 4)
- s->destination = m_SH4_DAR1;
+ s->destination = m_dar1;
if (s->mode & 8)
- m_SH4_DAR1 = s->destination;
+ m_dar1 = s->destination;
break;
case 2:
if (s->mode & 1)
- s->source = m_SH4_SAR2;
+ s->source = m_sar2;
if (s->mode & 2)
- m_SH4_SAR2 = s->source;
+ m_sar2 = s->source;
if (s->mode & 4)
- s->destination = m_SH4_DAR2;
+ s->destination = m_dar2;
if (s->mode & 8)
- m_SH4_DAR2 = s->destination;
+ m_dar2 = s->destination;
break;
case 3:
default:
if (s->mode & 1)
- s->source = m_SH4_SAR3;
+ s->source = m_sar3;
if (s->mode & 2)
- m_SH4_SAR3 = s->source;
+ m_sar3 = s->source;
if (s->mode & 4)
- s->destination = m_SH4_DAR3;
+ s->destination = m_dar3;
if (s->mode & 8)
- m_SH4_DAR3 = s->destination;
+ m_dar3 = s->destination;
break;
}
uint32_t len;
@@ -479,21 +479,21 @@ void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
switch (s->channel)
{
case 0:
- chcr = m_SH4_CHCR0;
- len = m_SH4_DMATCR0;
+ chcr = m_chcr0;
+ len = m_dmatcr0;
break;
case 1:
- chcr = m_SH4_CHCR1;
- len = m_SH4_DMATCR1;
+ chcr = m_chcr1;
+ len = m_dmatcr1;
break;
case 2:
- chcr = m_SH4_CHCR2;
- len = m_SH4_DMATCR2;
+ chcr = m_chcr2;
+ len = m_dmatcr2;
break;
case 3:
default:
- chcr = m_SH4_CHCR3;
- len = m_SH4_DMATCR3;
+ chcr = m_chcr3;
+ len = m_dmatcr3;
break;
}
@@ -528,7 +528,7 @@ void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
uint32_t *p32bits = (uint32_t *)s->buffer;
for (uint32_t pos = 0; pos < s->length; pos++)
{
- *p32bits++ = m_program->read_dword(s->source);
+ *p32bits++ = m_program->read_dword(s->source & SH34_AM);
s->source = s->source + 4;
}
}
@@ -537,7 +537,7 @@ void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
uint32_t *p32bits = (uint32_t *)s->buffer;
for (uint32_t pos = 0; pos < s->length; pos++)
{
- m_program->write_dword(s->destination, *p32bits);
+ m_program->write_dword(s->destination & SH34_AM, *p32bits);
p32bits++;
s->destination = s->destination + 4;
}
@@ -550,7 +550,7 @@ void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
uint64_t *p32bytes = (uint64_t *)s->buffer;
for (uint32_t pos = 0; pos < s->length * 4; pos++)
{
- *p32bytes++ = m_program->read_qword(s->source);
+ *p32bytes++ = m_program->read_qword(s->source & SH34_AM);
s->destination = s->destination + 8;
}
}
@@ -559,7 +559,7 @@ void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
uint64_t *p32bytes = (uint64_t *)s->buffer;
for (uint32_t pos = 0; pos < s->length * 4; pos++)
{
- m_program->write_qword(s->destination, *p32bytes);
+ m_program->write_qword(s->destination & SH34_AM, *p32bytes);
p32bytes++;
s->destination = s->destination + 8;
}
@@ -568,100 +568,184 @@ void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
}
}
+uint32_t sh34_base_device::sar0_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_sar0;
+}
- void sh34_base_device::sh4_handle_sar0_addr_w(uint32_t data, uint32_t mem_mask)
+void sh34_base_device::sar0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_SAR0);
+ COMBINE_DATA(&m_sar0);
}
- void sh34_base_device::sh4_handle_sar1_addr_w(uint32_t data, uint32_t mem_mask)
+uint32_t sh34_base_device::dar0_r(offs_t offset, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_SAR1);
+ return m_dar0;
}
- void sh34_base_device::sh4_handle_sar2_addr_w(uint32_t data, uint32_t mem_mask)
+void sh34_base_device::dar0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_SAR2);
+ COMBINE_DATA(&m_dar0);
}
- void sh34_base_device::sh4_handle_sar3_addr_w(uint32_t data, uint32_t mem_mask)
+uint32_t sh34_base_device::dmatcr0_r(offs_t offset, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_SAR3);
+ return m_dmatcr0;
}
- void sh34_base_device::sh4_handle_dar0_addr_w(uint32_t data, uint32_t mem_mask)
+void sh34_base_device::dmatcr0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_DAR0);
+ COMBINE_DATA(&m_dmatcr0);
}
- void sh34_base_device::sh4_handle_dar1_addr_w(uint32_t data, uint32_t mem_mask)
+uint32_t sh34_base_device::chcr0_r(offs_t offset, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_DAR1);
+ return m_chcr0;
}
- void sh34_base_device::sh4_handle_dar2_addr_w(uint32_t data, uint32_t mem_mask)
+void sh34_base_device::chcr0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_DAR2);
+ COMBINE_DATA(&m_chcr0);
+ sh4_dmac_check(0);
}
- void sh34_base_device::sh4_handle_dar3_addr_w(uint32_t data, uint32_t mem_mask)
+uint32_t sh34_base_device::sar1_r(offs_t offset, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_DAR3);
+ return m_sar1;
}
- void sh34_base_device::sh4_handle_dmatcr0_addr_w(uint32_t data, uint32_t mem_mask)
+void sh34_base_device::sar1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_DMATCR0);
+ COMBINE_DATA(&m_sar1);
}
- void sh34_base_device::sh4_handle_dmatcr1_addr_w(uint32_t data, uint32_t mem_mask)
+uint32_t sh34_base_device::dar1_r(offs_t offset, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_DMATCR1);
+ return m_dar1;
}
- void sh34_base_device::sh4_handle_dmatcr2_addr_w(uint32_t data, uint32_t mem_mask)
+void sh34_base_device::dar1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_DMATCR2);
+ COMBINE_DATA(&m_dar1);
}
- void sh34_base_device::sh4_handle_dmatcr3_addr_w(uint32_t data, uint32_t mem_mask)
+uint32_t sh34_base_device::dmatcr1_r(offs_t offset, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_DMATCR3);
+ return m_dmatcr1;
}
- void sh34_base_device::sh4_handle_chcr0_addr_w(uint32_t data, uint32_t mem_mask)
+void sh34_base_device::dmatcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_CHCR0);
- sh4_dmac_check(0);
+ COMBINE_DATA(&m_dmatcr1);
+}
+
+uint32_t sh34_base_device::chcr1_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_chcr1;
}
- void sh34_base_device::sh4_handle_chcr1_addr_w(uint32_t data, uint32_t mem_mask)
+void sh34_base_device::chcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_CHCR1);
+ COMBINE_DATA(&m_chcr1);
sh4_dmac_check(1);
}
- void sh34_base_device::sh4_handle_chcr2_addr_w(uint32_t data, uint32_t mem_mask)
+uint32_t sh34_base_device::sar2_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_sar2;
+}
+
+void sh34_base_device::sar2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_sar2);
+}
+
+uint32_t sh34_base_device::dar2_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_dar2;
+}
+
+void sh34_base_device::dar2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_dar2);
+}
+
+uint32_t sh34_base_device::dmatcr2_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_dmatcr2;
+}
+
+void sh34_base_device::dmatcr2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_dmatcr2);
+}
+
+uint32_t sh34_base_device::chcr2_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_chcr2;
+}
+
+void sh34_base_device::chcr2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_CHCR2);
+ COMBINE_DATA(&m_chcr2);
sh4_dmac_check(2);
}
- void sh34_base_device::sh4_handle_chcr3_addr_w(uint32_t data, uint32_t mem_mask)
+uint32_t sh34_base_device::sar3_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_sar3;
+}
+
+void sh34_base_device::sar3_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_sar3);
+}
+
+uint32_t sh34_base_device::dar3_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_dar3;
+}
+
+void sh34_base_device::dar3_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_dar3);
+}
+
+uint32_t sh34_base_device::dmatcr3_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_dmatcr3;
+}
+
+void sh34_base_device::dmatcr3_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_dmatcr3);
+}
+
+uint32_t sh34_base_device::chcr3_r(offs_t offset, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_CHCR3);
+ return m_chcr3;
+}
+
+void sh34_base_device::chcr3_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_chcr3);
sh4_dmac_check(3);
}
- void sh34_base_device::sh4_handle_dmaor_addr_w(uint32_t data, uint32_t mem_mask)
+uint32_t sh34_base_device::dmaor_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_dmaor;
+}
+
+void sh34_base_device::dmaor_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
- uint32_t old = m_SH4_DMAOR;
- COMBINE_DATA(&m_SH4_DMAOR);
+ uint32_t old = m_dmaor;
+ COMBINE_DATA(&m_dmaor);
- if ((m_SH4_DMAOR & DMAOR_AE) && (~old & DMAOR_AE))
- m_SH4_DMAOR &= ~DMAOR_AE;
- if ((m_SH4_DMAOR & DMAOR_NMIF) && (~old & DMAOR_NMIF))
- m_SH4_DMAOR &= ~DMAOR_NMIF;
+ if ((m_dmaor & DMAOR_AE) && (~old & DMAOR_AE))
+ m_dmaor &= ~DMAOR_AE;
+ if ((m_dmaor & DMAOR_NMIF) && (~old & DMAOR_NMIF))
+ m_dmaor &= ~DMAOR_NMIF;
sh4_dmac_check(0);
sh4_dmac_check(1);
sh4_dmac_check(2);
diff --git a/src/devices/cpu/sh/sh4dmac.h b/src/devices/cpu/sh/sh4dmac.h
index b7918fac997..a3ad1d0b5dc 100644
--- a/src/devices/cpu/sh/sh4dmac.h
+++ b/src/devices/cpu/sh/sh4dmac.h
@@ -26,38 +26,3 @@
#define DMAOR_AE 0x0004
#define DMAOR_NMIF 0x0002
#define DMAOR_DME 0x0001
-
-void sh4_handle_sar0_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_sar1_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_sar2_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_sar3_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_dar0_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_dar1_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_dar2_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_dar3_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_dmatcr0_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_dmatcr1_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_dmatcr2_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_dmatcr3_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_chcr0_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_chcr1_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_chcr2_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_chcr3_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_dmaor_addr_w(uint32_t data, uint32_t mem_mask);
-uint32_t sh4_handle_sar0_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_sar1_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_sar2_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_sar3_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_dar0_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_dar1_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_dar2_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_dar3_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_dmatcr0_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_dmatcr1_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_dmatcr2_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_dmatcr3_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_chcr0_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_chcr1_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_chcr2_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_chcr3_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_dmaor_addr_r(uint32_t mem_mask);
diff --git a/src/devices/cpu/sh/sh4fe.cpp b/src/devices/cpu/sh/sh4fe.cpp
index 61941b7ec26..cb3afaba6fe 100644
--- a/src/devices/cpu/sh/sh4fe.cpp
+++ b/src/devices/cpu/sh/sh4fe.cpp
@@ -31,14 +31,6 @@ uint16_t sh4_frontend::read_word(opcode_desc &desc)
return m_sh->m_pr16(desc.physpc & SH34_AM);
}
-uint16_t sh4be_frontend::read_word(opcode_desc &desc)
-{
- if (desc.physpc >= 0xe0000000)
- return m_sh->m_pr16(desc.physpc);
-
- return m_sh->m_pr16(desc.physpc & SH34_AM);
-}
-
bool sh4_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, uint16_t opcode)
{
diff --git a/src/devices/cpu/sh/sh4regs.h b/src/devices/cpu/sh/sh4regs.h
index 59f0044e283..691fef33998 100644
--- a/src/devices/cpu/sh/sh4regs.h
+++ b/src/devices/cpu/sh/sh4regs.h
@@ -5,163 +5,6 @@
#pragma once
-/* 00000001111111100000000011111100 */
-#define PTEH 0x2000 /* FF000000 */
-#define PTEL 0x2001 /* FF000004 */
-#define TTB 0x2002 /* FF000008 */
-#define TEA 0x2003 /* FF00000C */
-#define MMUCR 0x2004 /* FF000010 */
-#define BASRA 0x2005 /* FF000014 */
-#define BASRB 0x2006 /* FF000018 */
-#define CCR 0x2007 /* FF00001C */
-#define TRA 0x2008 /* FF000020 */
-#define EXPEVT 0x2009 /* FF000024 */
-#define INTEVT 0x200A /* FF000028 */
-#define VERSION 0x200C /* FF000030 */
-#define PTEA 0x200D /* FF000034 */
-#define QACR0 0x200E /* FF000038 */
-#define QACR1 0x200F /* FF00003C */
-#define PRR 0x2011 /* FF000044 */
-#define BARA 0x2400 /* FF200000 */
-#define BAMRA 0x2401 /* FF200004 */
-#define BBRA 0x2402 /* FF200008 */
-#define BARB 0x2403 /* FF20000C */
-#define BAMRB 0x2404 /* FF200010 */
-#define BBRB 0x2405 /* FF200014 */
-#define BDRB 0x2406 /* FF200018 */
-#define BDMRB 0x2407 /* FF20001C */
-#define BRCR 0x2408 /* FF200020 */
-#define BCR1 0x3000 /* FF800000 */
-#define BCR2 0x3001 /* FF800004 */
-#define BCR3 0x3014 /* FF800050 */
-#define BCR4 0x17C /* FE0A00F0 */
-#define WCR1 0x3002 /* FF800008 */
-#define WCR2 0x3003 /* FF80000C */
-#define WCR3 0x3004 /* FF800010 */
-#define MCR 0x3005 /* FF800014 */
-#define PCR 0x3006 /* FF800018 */
-#define RTCSR 0x3007 /* FF80001C */
-#define RTCNT 0x3008 /* FF800020 */
-#define RTCOR 0x3009 /* FF800024 */
-#define RFCR 0x300A /* FF800028 */
-#define PCTRA 0x300B /* FF80002C */
-#define PDTRA 0x300C /* FF800030 */
-#define PCTRB 0x3010 /* FF800040 */
-#define PDTRB 0x3011 /* FF800044 */
-#define GPIOIC 0x3012 /* FF800048 */
-#define SDMR2 0x3200 /* FF900000 */
-#define SDMR3 0x3280 /* FF940000 */
-#define SH4_SAR0_ADDR 0x3400 /* FFA00000 */
-#define SH4_DAR0_ADDR 0x3401 /* FFA00004 */
-#define SH4_DMATCR0_ADDR 0x3402 /* FFA00008 */
-#define SH4_CHCR0_ADDR 0x3403 /* FFA0000C */
-#define SH4_SAR1_ADDR 0x3404 /* FFA00010 */
-#define SH4_DAR1_ADDR 0x3405 /* FFA00014 */
-#define SH4_DMATCR1_ADDR 0x3406 /* FFA00018 */
-#define SH4_CHCR1_ADDR 0x3407 /* FFA0001C */
-#define SH4_SAR2_ADDR 0x3408 /* FFA00020 */
-#define SH4_DAR2_ADDR 0x3409 /* FFA00024 */
-#define SH4_DMATCR2_ADDR 0x340A /* FFA00028 */
-#define SH4_CHCR2_ADDR 0x340B /* FFA0002C */
-#define SH4_SAR3_ADDR 0x340C /* FFA00030 */
-#define SH4_DAR3_ADDR 0x340D /* FFA00034 */
-#define SH4_DMATCR3_ADDR 0x340E /* FFA00038 */
-#define SH4_CHCR3_ADDR 0x340F /* FFA0003C */
-#define SH4_DMAOR_ADDR 0x3410 /* FFA00040 */
-#define SAR4 0x3414 /* FFA00050 */
-#define DAR4 0x3415 /* FFA00054 */
-#define DMATCR4 0x3416 /* FFA00058 */
-#define CHCR4 0x3417 /* FFA0005C */
-#define SAR5 0x3418 /* FFA00060 */
-#define DAR5 0x3419 /* FFA00064 */
-#define DMATCR5 0x341A /* FFA00068 */
-#define CHCR5 0x341B /* FFA0006C */
-#define SAR6 0x341C /* FFA00070 */
-#define DAR6 0x341D /* FFA00074 */
-#define DMATCR6 0x341E /* FFA00078 */
-#define CHCR6 0x341F /* FFA0007C */
-#define SAR7 0x3420 /* FFA00080 */
-#define DAR7 0x3421 /* FFA00084 */
-#define DMATCR7 0x3422 /* FFA00088 */
-#define CHCR7 0x3423 /* FFA0008C */
-#define FRQCR 0x3800 /* FFC00000 */
-#define STBCR 0x3801 /* FFC00004 */
-#define WTCNT 0x3802 /* FFC00008 */
-#define WTCSR 0x3803 /* FFC0000C */
-#define STBCR2 0x3804 /* FFC00010 */
-#define R64CNT 0x3900 /* FFC80000 */
-#define RSECCNT 0x3901 /* FFC80004 */
-#define RMINCNT 0x3902 /* FFC80008 */
-#define RHRCNT 0x3903 /* FFC8000C */
-#define RWKCNT 0x3904 /* FFC80010 */
-#define RDAYCNT 0x3905 /* FFC80014 */
-#define RMONCNT 0x3906 /* FFC80018 */
-#define RYRCNT 0x3907 /* FFC8001C */
-#define RSECAR 0x3908 /* FFC80020 */
-#define RMINAR 0x3909 /* FFC80024 */
-#define RHRAR 0x390A /* FFC80028 */
-#define RWKAR 0x390B /* FFC8002C */
-#define RDAYAR 0x390C /* FFC80030 */
-#define RMONAR 0x390D /* FFC80034 */
-#define RCR1 0x390E /* FFC80038 */
-#define RCR2 0x390F /* FFC8003C */
-#define RCR3 0x3914 /* FFC80050 */
-#define RYRAR 0x3915 /* FFC80054 */
-#define ICR 0x3A00 /* FFD00000 */
-#define IPRA 0x3A01 /* FFD00004 */
-#define IPRB 0x3A02 /* FFD00008 */
-#define IPRC 0x3A03 /* FFD0000C */
-#define IPRD 0x3A04 /* FFD00010 */
-#define INTPRI00 0x100 /* FE080000 */
-#define INTREQ00 0x108 /* FE080020 */
-#define INTMSK00 0x110 /* FE080040 */
-#define INTMSKCLR00 0x118 /* FE080060 */
-#define CLKSTP00 0x140 /* FE0A0000 */
-#define CLKSTPCLR00 0x142 /* FE0A0008 */
-#define TSTR2 0x201 /* FE100004 */
-#define TCOR3 0x202 /* FE100008 */
-#define TCNT3 0x203 /* FE10000C */
-#define TCR3 0x204 /* FE100010 */
-#define TCOR4 0x205 /* FE100014 */
-#define TCNT4 0x206 /* FE100018 */
-#define TCR4 0x207 /* FE10001C */
-#define SH4_TOCR_ADDR 0x3B00 /* FFD80000 */
-#define SH4_TSTR_ADDR 0x3B01 /* FFD80004 */
-#define SH4_TCOR0_ADDR 0x3B02 /* FFD80008 */
-#define SH4_TCNT0_ADDR 0x3B03 /* FFD8000C */
-#define SH4_TCR0_ADDR 0x3B04 /* FFD80010 */
-#define SH4_TCOR1_ADDR 0x3B05 /* FFD80014 */
-#define SH4_TCNT1_ADDR 0x3B06 /* FFD80018 */
-#define SH4_TCR1_ADDR 0x3B07 /* FFD8001C */
-#define SH4_TCOR2_ADDR 0x3B08 /* FFD80020 */
-#define SH4_TCNT2_ADDR 0x3B09 /* FFD80024 */
-#define SH4_TCR2_ADDR 0x3B0A /* FFD80028 */
-#define SH4_TCPR2_ADDR 0x3B0B /* FFD8002C */
-#define SCSMR1 0x3C00 /* FFE00000 */
-#define SCBRR1 0x3C01 /* FFE00004 */
-#define SCSCR1 0x3C02 /* FFE00008 */
-#define SCTDR1 0x3C03 /* FFE0000C */
-#define SCSSR1 0x3C04 /* FFE00010 */
-#define SCRDR1 0x3C05 /* FFE00014 */
-#define SCSCMR1 0x3C06 /* FFE00018 */
-#define SCSPTR1 0x3C07 /* FFE0001C */
-#define SCSMR2 0x3D00 /* FFE80000 */
-#define SCBRR2 0x3D01 /* FFE80004 */
-#define SCSCR2 0x3D02 /* FFE80008 */
-#define SCFTDR2 0x3D03 /* FFE8000C */
-#define SCFSR2 0x3D04 /* FFE80010 */
-#define SCFRDR2 0x3D05 /* FFE80014 */
-#define SCFCR2 0x3D06 /* FFE80018 */
-#define SCFDR2 0x3D07 /* FFE8001C */
-#define SCSPTR2 0x3D08 /* FFE80020 */
-#define SCLSR2 0x3D09 /* FFE80024 */
-#define SDIR 0x3E00 /* FFF00000 */
-#define SDDR 0x3E02 /* FFF00008 */
-#define SDINT 0x3E05 /* FFF00014 */
-#define SIZEREGS 15878
-
-
-
#define MMUCR_LRUI 0xfc000000
#define MMUCR_URB 0x00fc0000
#define MMUCR_URC 0x0000fc00
diff --git a/src/devices/cpu/sh/sh4tmu.cpp b/src/devices/cpu/sh/sh4tmu.cpp
index 8bcce44b37a..dcdb9454e32 100644
--- a/src/devices/cpu/sh/sh4tmu.cpp
+++ b/src/devices/cpu/sh/sh4tmu.cpp
@@ -37,18 +37,18 @@ void sh34_base_device::sh4_timer_recompute(int which)
switch (which)
{
case 0:
- tcr = m_SH4_TCR0;
- tcnt = m_SH4_TCNT0;
+ tcr = m_tcr0;
+ tcnt = m_tcnt0;
break;
case 1:
- tcr = m_SH4_TCR1;
- tcnt = m_SH4_TCNT1;
+ tcr = m_tcr1;
+ tcnt = m_tcnt1;
break;
case 2:
- tcr = m_SH4_TCR2;
- tcnt = m_SH4_TCNT2;
+ tcr = m_tcr2;
+ tcnt = m_tcnt2;
break;
}
@@ -64,15 +64,15 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_timer_callback )
switch (which)
{
case 0:
- m_SH4_TCNT0 = m_SH4_TCOR0;
+ m_tcnt0 = m_tcor0;
break;
case 1:
- m_SH4_TCNT1 = m_SH4_TCOR1;
+ m_tcnt1 = m_tcor1;
break;
case 2:
- m_SH4_TCNT2 = m_SH4_TCOR2;
+ m_tcnt2 = m_tcor2;
break;
}
@@ -82,15 +82,15 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_timer_callback )
switch (which)
{
case 0:
- m_SH4_TCR0 |= 0x100;
+ m_tcr0 |= 0x100;
break;
case 1:
- m_SH4_TCR1 |= 0x100;
+ m_tcr1 |= 0x100;
break;
case 2:
- m_SH4_TCR2 |= 0x100;
+ m_tcr2 |= 0x100;
break;
}
@@ -98,7 +98,7 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_timer_callback )
switch (which)
{
case 0:
- if (m_SH4_TCR0 & 0x20)
+ if (m_tcr0 & 0x20)
{
sh4_exception_request(SH4_INTC_TUNI0);
// logerror("SH4_INTC_TUNI0 requested\n");
@@ -106,7 +106,7 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_timer_callback )
break;
case 1:
- if (m_SH4_TCR1 & 0x20)
+ if (m_tcr1 & 0x20)
{
sh4_exception_request(SH4_INTC_TUNI1);
// logerror("SH4_INTC_TUNI1 requested\n");
@@ -114,7 +114,7 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_timer_callback )
break;
case 2:
- if (m_SH4_TCR2 & 0x20)
+ if (m_tcr2 & 0x20)
{
sh4_exception_request(SH4_INTC_TUNI2);
// logerror("SH4_INTC_TUNI2 requested\n");
@@ -124,88 +124,32 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_timer_callback )
}
}
-
-uint32_t sh34_base_device::sh4_handle_tcnt0_addr_r(uint32_t mem_mask)
-{
- if (m_SH4_TSTR & 1)
- return compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[m_SH4_TCR0 & 7]);
- else
- return m_SH4_TCNT0;
-}
-
-uint32_t sh34_base_device::sh4_handle_tcnt1_addr_r(uint32_t mem_mask)
-{
- if (m_SH4_TSTR & 2)
- return compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[m_SH4_TCR1 & 7]);
- else
- return m_SH4_TCNT1;
-}
-
-uint32_t sh34_base_device::sh4_handle_tcnt2_addr_r(uint32_t mem_mask)
-{
- if (m_SH4_TSTR & 4)
- return compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[m_SH4_TCR2 & 7]);
- else
- return m_SH4_TCNT2;
-}
-
-uint32_t sh34_base_device::sh4_handle_tcor0_addr_r(uint32_t mem_mask)
-{
- return m_SH4_TCOR0;
-}
-
-uint32_t sh34_base_device::sh4_handle_tcor1_addr_r(uint32_t mem_mask)
-{
- return m_SH4_TCOR1;
-}
-
-uint32_t sh34_base_device::sh4_handle_tcor2_addr_r(uint32_t mem_mask)
+void sh34_base_device::tocr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
{
- return m_SH4_TCOR2;
+ COMBINE_DATA(&m_tocr);
}
-uint32_t sh34_base_device::sh4_handle_tcr0_addr_r(uint32_t mem_mask)
+uint8_t sh34_base_device::tocr_r(offs_t offset, uint8_t mem_mask)
{
- return m_SH4_TCR0;
+ return m_tocr;
}
-uint32_t sh34_base_device::sh4_handle_tcr1_addr_r(uint32_t mem_mask)
+uint8_t sh34_base_device::tstr_r(offs_t offset, uint8_t mem_mask)
{
- return m_SH4_TCR1;
+ return m_tstr;
}
-uint32_t sh34_base_device::sh4_handle_tcr2_addr_r(uint32_t mem_mask)
+void sh34_base_device::tstr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
{
- return m_SH4_TCR2;
-}
-
-uint32_t sh34_base_device::sh4_handle_tstr_addr_r(uint32_t mem_mask)
-{
- return m_SH4_TSTR;
-}
-
-uint32_t sh34_base_device::sh4_handle_tocr_addr_r(uint32_t mem_mask)
-{
- return m_SH4_TOCR;
-}
-
-uint32_t sh34_base_device::sh4_handle_tcpr2_addr_r(uint32_t mem_mask)
-{
- return m_SH4_TCPR2;
-}
-
-
-void sh34_base_device::sh4_handle_tstr_addr_w(uint32_t data, uint32_t mem_mask)
-{
- uint32_t chg = m_SH4_TSTR;
- COMBINE_DATA(&m_SH4_TSTR);
- chg ^= m_SH4_TSTR;
+ uint32_t chg = m_tstr;
+ COMBINE_DATA(&m_tstr);
+ chg ^= m_tstr;
if (chg & 1)
{
- if ((m_SH4_TSTR & 1) == 0)
+ if ((m_tstr & 1) == 0)
{
- m_SH4_TCNT0 = compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[m_SH4_TCR0 & 7]);
+ m_tcnt0 = compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[m_tcr0 & 7]);
m_timer[0]->adjust(attotime::never);
}
else
@@ -214,9 +158,9 @@ void sh34_base_device::sh4_handle_tstr_addr_w(uint32_t data, uint32_t mem_mask)
if (chg & 2)
{
- if ((m_SH4_TSTR & 2) == 0)
+ if ((m_tstr & 2) == 0)
{
- m_SH4_TCNT1 = compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[m_SH4_TCR1 & 7]);
+ m_tcnt1 = compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[m_tcr1 & 7]);
m_timer[1]->adjust(attotime::never);
}
else
@@ -225,9 +169,9 @@ void sh34_base_device::sh4_handle_tstr_addr_w(uint32_t data, uint32_t mem_mask)
if (chg & 4)
{
- if ((m_SH4_TSTR & 4) == 0)
+ if ((m_tstr & 4) == 0)
{
- m_SH4_TCNT2 = compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[m_SH4_TCR2 & 7]);
+ m_tcnt2 = compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[m_tcr2 & 7]);
m_timer[2]->adjust(attotime::never);
}
else
@@ -235,87 +179,141 @@ void sh34_base_device::sh4_handle_tstr_addr_w(uint32_t data, uint32_t mem_mask)
}
}
-void sh34_base_device::sh4_handle_tcr0_addr_w(uint32_t data, uint32_t mem_mask)
+uint32_t sh34_base_device::tcor0_r(offs_t offset, uint32_t mem_mask)
+{
+ return m_tcor0;
+}
+
+void sh34_base_device::tcor0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_tcor0);
+}
+
+uint32_t sh34_base_device::tcnt0_r(offs_t offset, uint32_t mem_mask)
{
- uint32_t old2 = m_SH4_TCR0;
- COMBINE_DATA(&m_SH4_TCR0);
- if (m_SH4_TSTR & 1)
+ if (m_tstr & 1)
+ return compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[m_tcr0 & 7]);
+ else
+ return m_tcnt0;
+}
+
+void sh34_base_device::tcnt0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_tcnt0);
+ if (m_tstr & 1)
+ sh4_timer_recompute(0);
+}
+
+uint16_t sh34_base_device::tcr0_r(offs_t offset, uint16_t mem_mask)
+{
+ return m_tcr0;
+}
+
+void sh34_base_device::tcr0_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ uint32_t old2 = m_tcr0;
+ COMBINE_DATA(&m_tcr0);
+ if (m_tstr & 1)
{
- m_SH4_TCNT0 = compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[old2 & 7]);
+ m_tcnt0 = compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[old2 & 7]);
sh4_timer_recompute(0);
}
- if (!(m_SH4_TCR0 & 0x20) || !(m_SH4_TCR0 & 0x100))
+ if (!(m_tcr0 & 0x20) || !(m_tcr0 & 0x100))
sh4_exception_unrequest(SH4_INTC_TUNI0);
}
-void sh34_base_device::sh4_handle_tcr1_addr_w(uint32_t data, uint32_t mem_mask)
+uint32_t sh34_base_device::tcor1_r(offs_t offset, uint32_t mem_mask)
{
- uint32_t old2 = m_SH4_TCR1;
- COMBINE_DATA(&m_SH4_TCR1);
- if (m_SH4_TSTR & 2)
- {
- m_SH4_TCNT1 = compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[old2 & 7]);
+ return m_tcor1;
+}
+
+void sh34_base_device::tcor1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_tcor1);
+}
+
+uint32_t sh34_base_device::tcnt1_r(offs_t offset, uint32_t mem_mask)
+{
+ if (m_tstr & 2)
+ return compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[m_tcr1 & 7]);
+ else
+ return m_tcnt1;
+}
+
+void sh34_base_device::tcnt1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ COMBINE_DATA(&m_tcnt1);
+ if (m_tstr & 2)
sh4_timer_recompute(1);
- }
- if (!(m_SH4_TCR1 & 0x20) || !(m_SH4_TCR1 & 0x100))
- sh4_exception_unrequest(SH4_INTC_TUNI1);
}
-void sh34_base_device::sh4_handle_tcr2_addr_w(uint32_t data, uint32_t mem_mask)
+uint16_t sh34_base_device::tcr1_r(offs_t offset, uint16_t mem_mask)
{
- uint32_t old2 = m_SH4_TCR2;
- COMBINE_DATA(&m_SH4_TCR2);
- if (m_SH4_TSTR & 4)
+ return m_tcr1;
+}
+
+void sh34_base_device::tcr1_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ uint32_t old2 = m_tcr1;
+ COMBINE_DATA(&m_tcr1);
+ if (m_tstr & 2)
{
- m_SH4_TCNT2 = compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[old2 & 7]);
- sh4_timer_recompute(2);
+ m_tcnt1 = compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[old2 & 7]);
+ sh4_timer_recompute(1);
}
- if (!(m_SH4_TCR2 & 0x20) || !(m_SH4_TCR2 & 0x100))
- sh4_exception_unrequest(SH4_INTC_TUNI2);
+ if (!(m_tcr1 & 0x20) || !(m_tcr1 & 0x100))
+ sh4_exception_unrequest(SH4_INTC_TUNI1);
}
-void sh34_base_device::sh4_handle_tcor0_addr_w(uint32_t data, uint32_t mem_mask)
+uint32_t sh34_base_device::tcor2_r(offs_t offset, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_TCOR0);
+ return m_tcor2;
}
-void sh34_base_device::sh4_handle_tcor1_addr_w(uint32_t data, uint32_t mem_mask)
+void sh34_base_device::tcor2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_TCOR1);
+ COMBINE_DATA(&m_tcor2);
}
-void sh34_base_device::sh4_handle_tcor2_addr_w(uint32_t data, uint32_t mem_mask)
+uint32_t sh34_base_device::tcnt2_r(offs_t offset, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_TCOR2);
+ if (m_tstr & 4)
+ return compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[m_tcr2 & 7]);
+ else
+ return m_tcnt2;
}
-void sh34_base_device::sh4_handle_tcnt0_addr_w(uint32_t data, uint32_t mem_mask)
+void sh34_base_device::tcnt2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_TCNT0);
- if (m_SH4_TSTR & 1)
- sh4_timer_recompute(0);
+ COMBINE_DATA(&m_tcnt2);
+ if (m_tstr & 4)
+ sh4_timer_recompute(2);
}
-void sh34_base_device::sh4_handle_tcnt1_addr_w(uint32_t data, uint32_t mem_mask)
+uint16_t sh34_base_device::tcr2_r(offs_t offset, uint16_t mem_mask)
{
- COMBINE_DATA(&m_SH4_TCNT1);
- if (m_SH4_TSTR & 2)
- sh4_timer_recompute(1);
+ return m_tcr2;
}
-void sh34_base_device::sh4_handle_tcnt2_addr_w(uint32_t data, uint32_t mem_mask)
+void sh34_base_device::tcr2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
- COMBINE_DATA(&m_SH4_TCNT2);
- if (m_SH4_TSTR & 4)
+ uint32_t old2 = m_tcr2;
+ COMBINE_DATA(&m_tcr2);
+ if (m_tstr & 4)
+ {
+ m_tcnt2 = compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[old2 & 7]);
sh4_timer_recompute(2);
+ }
+ if (!(m_tcr2 & 0x20) || !(m_tcr2 & 0x100))
+ sh4_exception_unrequest(SH4_INTC_TUNI2);
}
-void sh34_base_device::sh4_handle_tocr_addr_w(uint32_t data, uint32_t mem_mask)
+uint32_t sh34_base_device::tcpr2_r(offs_t offset, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_TOCR);
+ return m_tcpr2;
}
-void sh34_base_device::sh4_handle_tcpr2_addr_w(uint32_t data, uint32_t mem_mask)
+void sh34_base_device::tcpr2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
- COMBINE_DATA(&m_SH4_TCPR2);
+ COMBINE_DATA(&m_tcpr2);
}