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-rw-r--r--src/devices/cpu/rsp/rsp.cpp4
-rw-r--r--src/devices/cpu/rsp/rsp.h12
-rw-r--r--src/devices/cpu/rsp/rspcp2.h8
-rw-r--r--src/devices/cpu/rsp/rspcp2d.cpp162
-rw-r--r--src/devices/cpu/rsp/rspcp2d.h8
-rw-r--r--src/devices/cpu/rsp/rspdrc.cpp146
6 files changed, 170 insertions, 170 deletions
diff --git a/src/devices/cpu/rsp/rsp.cpp b/src/devices/cpu/rsp/rsp.cpp
index 98cef6ff670..76fe3f63779 100644
--- a/src/devices/cpu/rsp/rsp.cpp
+++ b/src/devices/cpu/rsp/rsp.cpp
@@ -106,7 +106,7 @@ rsp_device::rsp_device(const machine_config &mconfig, const char *tag, device_t
// , m_drcuml(*this, m_cache, 0, 8, 32, 2)
, m_drcfe(nullptr)
, m_drcoptions(0)
- , m_cache_dirty(TRUE)
+ , m_cache_dirty(true)
, m_numcycles(0)
, m_format(nullptr)
, m_arg2(0)
@@ -420,7 +420,7 @@ void rsp_device::device_start()
}
/* mark the cache dirty so it is updated on next execute */
- m_cache_dirty = TRUE;
+ m_cache_dirty = true;
state_add( RSP_PC, "PC", m_debugger_temp).callimport().callexport().formatstr("%08X");
state_add( RSP_R0, "R0", m_rsp_state->r[0]).formatstr("%08X");
diff --git a/src/devices/cpu/rsp/rsp.h b/src/devices/cpu/rsp/rsp.h
index a00feb1c03b..dbb97511ef6 100644
--- a/src/devices/cpu/rsp/rsp.h
+++ b/src/devices/cpu/rsp/rsp.h
@@ -210,7 +210,7 @@ private:
{
offs_t start; /* start of the RAM block */
offs_t end; /* end of the RAM block */
- uint8_t readonly; /* TRUE if read-only */
+ bool readonly; /* true if read-only */
void * base; /* base in memory where the RAM lives */
};
@@ -311,15 +311,15 @@ private:
void static_generate_nocode_handler();
void static_generate_out_of_cycles();
void static_generate_memory_accessor(int size, int iswrite, const char *name, uml::code_handle *&handleptr);
- void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
+ void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception);
void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
void generate_delay_slot_and_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint8_t linkreg);
void generate_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
void log_add_disasm_comment(drcuml_block *block, uint32_t pc, uint32_t op);
};
diff --git a/src/devices/cpu/rsp/rspcp2.h b/src/devices/cpu/rsp/rspcp2.h
index 5f477963940..ad12d82b601 100644
--- a/src/devices/cpu/rsp/rspcp2.h
+++ b/src/devices/cpu/rsp/rspcp2.h
@@ -85,9 +85,9 @@ protected:
virtual void init();
virtual void start();
- virtual int generate_cop2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return TRUE; }
- virtual int generate_lwc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return TRUE; }
- virtual int generate_swc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return TRUE; }
+ virtual bool generate_cop2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return true; }
+ virtual bool generate_lwc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return true; }
+ virtual bool generate_swc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return true; }
virtual void state_string_export(const int index, std::string &str) const;
@@ -172,7 +172,7 @@ public:
void dump_dmem();
protected:
- virtual int generate_vector_opcode(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return TRUE; }
+ virtual bool generate_vector_opcode(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return true; }
uint16_t SATURATE_ACCUM(int accum, int slice, uint16_t negative, uint16_t positive);
diff --git a/src/devices/cpu/rsp/rspcp2d.cpp b/src/devices/cpu/rsp/rspcp2d.cpp
index 7efb3f34b12..f770f07b4aa 100644
--- a/src/devices/cpu/rsp/rspcp2d.cpp
+++ b/src/devices/cpu/rsp/rspcp2d.cpp
@@ -707,7 +707,7 @@ static void cfunc_ltv(void *param)
}
-int rsp_cop2_drc::generate_lwc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
+bool rsp_cop2_drc::generate_lwc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
int offset = (op & 0x7f);
@@ -721,65 +721,65 @@ int rsp_cop2_drc::generate_lwc2(drcuml_block *block, rsp_device::compiler_state
case 0x00: /* LBV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_lbv, this);
- return TRUE;
+ return true;
case 0x01: /* LSV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_lsv, this);
- return TRUE;
+ return true;
case 0x02: /* LLV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_llv, this);
- return TRUE;
+ return true;
case 0x03: /* LDV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_ldv, this);
- return TRUE;
+ return true;
case 0x04: /* LQV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_lqv, this);
- return TRUE;
+ return true;
case 0x05: /* LRV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_lrv, this);
- return TRUE;
+ return true;
case 0x06: /* LPV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_lpv, this);
- return TRUE;
+ return true;
case 0x07: /* LUV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_luv, this);
- return TRUE;
+ return true;
case 0x08: /* LHV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_lhv, this);
- return TRUE;
+ return true;
case 0x09: /* LFV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_lfv, this);
- return TRUE;
+ return true;
case 0x0a: /* LWV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_lwv, this);
- return TRUE;
+ return true;
case 0x0b: /* LTV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_ltv, this);
- return TRUE;
+ return true;
default:
- return FALSE;
+ return false;
}
}
@@ -1257,7 +1257,7 @@ static void cfunc_stv(void *param)
((rsp_cop2 *)param)->stv();
}
-int rsp_cop2_drc::generate_swc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
+bool rsp_cop2_drc::generate_swc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
int offset = (op & 0x7f);
@@ -1271,69 +1271,69 @@ int rsp_cop2_drc::generate_swc2(drcuml_block *block, rsp_device::compiler_state
case 0x00: /* SBV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_sbv, this);
- return TRUE;
+ return true;
case 0x01: /* SSV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_ssv, this);
- return TRUE;
+ return true;
case 0x02: /* SLV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_slv, this);
- return TRUE;
+ return true;
case 0x03: /* SDV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_sdv, this);
- return TRUE;
+ return true;
case 0x04: /* SQV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_sqv, this);
- return TRUE;
+ return true;
case 0x05: /* SRV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_srv, this);
- return TRUE;
+ return true;
case 0x06: /* SPV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_spv, this);
- return TRUE;
+ return true;
case 0x07: /* SUV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_suv, this);
- return TRUE;
+ return true;
case 0x08: /* SHV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_shv, this);
- return TRUE;
+ return true;
case 0x09: /* SFV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_sfv, this);
- return TRUE;
+ return true;
case 0x0a: /* SWV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_swv, this);
- return TRUE;
+ return true;
case 0x0b: /* STV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_stv, this);
- return TRUE;
+ return true;
default:
m_rsp.unimplemented_opcode(op);
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
@@ -3251,7 +3251,7 @@ static void cfunc_vrsqh(void *param)
vector opcode
-------------------------------------------------*/
-int rsp_cop2_drc::generate_vector_opcode(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
+bool rsp_cop2_drc::generate_vector_opcode(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
// Opcode legend:
@@ -3265,226 +3265,226 @@ int rsp_cop2_drc::generate_vector_opcode(drcuml_block *block, rsp_device::compil
case 0x00: /* VMULF */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmulf, this);
- return TRUE;
+ return true;
case 0x01: /* VMULU */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmulu, this);
- return TRUE;
+ return true;
case 0x04: /* VMUDL */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmudl, this);
- return TRUE;
+ return true;
case 0x05: /* VMUDM */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmudm, this);
- return TRUE;
+ return true;
case 0x06: /* VMUDN */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmudn, this);
- return TRUE;
+ return true;
case 0x07: /* VMUDH */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmudh, this);
- return TRUE;
+ return true;
case 0x08: /* VMACF */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmacf, this);
- return TRUE;
+ return true;
case 0x09: /* VMACU */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmacu, this);
- return TRUE;
+ return true;
case 0x0c: /* VMADL */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmadl, this);
- return TRUE;
+ return true;
case 0x0d: /* VMADM */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmadm, this);
- return TRUE;
+ return true;
case 0x0e: /* VMADN */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmadn, this);
- return TRUE;
+ return true;
case 0x0f: /* VMADH */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmadh, this);
- return TRUE;
+ return true;
case 0x10: /* VADD */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vadd, this);
- return TRUE;
+ return true;
case 0x11: /* VSUB */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vsub, this);
- return TRUE;
+ return true;
case 0x13: /* VABS */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vabs, this);
- return TRUE;
+ return true;
case 0x14: /* VADDC */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vaddc, this);
- return TRUE;
+ return true;
case 0x15: /* VSUBC */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vsubc, this);
- return TRUE;
+ return true;
case 0x16: /* VADDB */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vaddb, this);
- return TRUE;
+ return true;
case 0x17: /* VSUBB (reserved, functionally identical to VADDB) */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vaddb, this);
- return TRUE;
+ return true;
case 0x18: /* VACCB (reserved, functionally identical to VADDB) */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vaddb, this);
- return TRUE;
+ return true;
case 0x19: /* VSUCB (reserved, functionally identical to VADDB) */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vaddb, this);
- return TRUE;
+ return true;
case 0x1d: /* VSAW */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vsaw, this);
- return TRUE;
+ return true;
case 0x20: /* VLT */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vlt, this);
- return TRUE;
+ return true;
case 0x21: /* VEQ */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_veq, this);
- return TRUE;
+ return true;
case 0x22: /* VNE */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vne, this);
- return TRUE;
+ return true;
case 0x23: /* VGE */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vge, this);
- return TRUE;
+ return true;
case 0x24: /* VCL */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vcl, this);
- return TRUE;
+ return true;
case 0x25: /* VCH */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vch, this);
- return TRUE;
+ return true;
case 0x26: /* VCR */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vcr, this);
- return TRUE;
+ return true;
case 0x27: /* VMRG */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmrg, this);
- return TRUE;
+ return true;
case 0x28: /* VAND */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vand, this);
- return TRUE;
+ return true;
case 0x29: /* VNAND */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vnand, this);
- return TRUE;
+ return true;
case 0x2a: /* VOR */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vor, this);
- return TRUE;
+ return true;
case 0x2b: /* VNOR */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vnor, this);
- return TRUE;
+ return true;
case 0x2c: /* VXOR */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vxor, this);
- return TRUE;
+ return true;
case 0x2d: /* VNXOR */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vnxor, this);
- return TRUE;
+ return true;
case 0x30: /* VRCP */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vrcp, this);
- return TRUE;
+ return true;
case 0x31: /* VRCPL */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vrcpl, this);
- return TRUE;
+ return true;
case 0x32: /* VRCPH */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vrcph, this);
- return TRUE;
+ return true;
case 0x33: /* VMOV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmov, this);
- return TRUE;
+ return true;
case 0x34: /* VRSQ */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vrsq, this);
- return TRUE;
+ return true;
case 0x35: /* VRSQL */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vrsql, this);
- return TRUE;
+ return true;
case 0x36: /* VRSQH */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vrsqh, this);
- return TRUE;
+ return true;
case 0x37: /* VNOP */
case 0x3F: /* VNULL */
- return TRUE;
+ return true;
default:
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, unimplemented_opcode, &m_rsp);
- return FALSE;
+ return false;
}
}
@@ -3695,7 +3695,7 @@ static void cfunc_ctc2(void *param)
COP2 Opcode Compilation
***************************************************************************/
-int rsp_cop2_drc::generate_cop2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
+bool rsp_cop2_drc::generate_cop2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
uint8_t opswitch = RSREG;
@@ -3708,7 +3708,7 @@ int rsp_cop2_drc::generate_cop2(drcuml_block *block, rsp_device::compiler_state
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_mfc2, this); // callc mfc2
}
- return TRUE;
+ return true;
case 0x02: /* CFCz */
if (RTREG != 0)
@@ -3716,21 +3716,21 @@ int rsp_cop2_drc::generate_cop2(drcuml_block *block, rsp_device::compiler_state
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_cfc2, this); // callc cfc2
}
- return TRUE;
+ return true;
case 0x04: /* MTCz */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_mtc2, this); // callc mtc2
- return TRUE;
+ return true;
case 0x06: /* CTCz */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_ctc2, this); // callc ctc2
- return TRUE;
+ return true;
case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
return generate_vector_opcode(block, compiler, desc);
}
- return FALSE;
+ return false;
}
diff --git a/src/devices/cpu/rsp/rspcp2d.h b/src/devices/cpu/rsp/rspcp2d.h
index 62fc25fe475..2e07403458d 100644
--- a/src/devices/cpu/rsp/rspcp2d.h
+++ b/src/devices/cpu/rsp/rspcp2d.h
@@ -24,9 +24,9 @@ class rsp_cop2_drc : public rsp_cop2
public:
rsp_cop2_drc(rsp_device &rsp, running_machine &machine) : rsp_cop2(rsp, machine) { }
private:
- virtual int generate_cop2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
- virtual int generate_lwc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
- virtual int generate_swc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
+ virtual bool generate_cop2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
+ virtual bool generate_lwc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
+ virtual bool generate_swc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
virtual void state_string_export(const int index, std::string &str) const override;
@@ -103,7 +103,7 @@ public:
virtual void ctc2() override;
private:
- virtual int generate_vector_opcode(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
+ virtual bool generate_vector_opcode(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
};
#endif /* __RSPCP2D_H__ */
diff --git a/src/devices/cpu/rsp/rspdrc.cpp b/src/devices/cpu/rsp/rspdrc.cpp
index 9849c07a71f..fe838519652 100644
--- a/src/devices/cpu/rsp/rspdrc.cpp
+++ b/src/devices/cpu/rsp/rspdrc.cpp
@@ -266,7 +266,7 @@ void rsp_device::execute_run_drc()
/* reset the cache if dirty */
if (m_cache_dirty)
code_flush_cache();
- m_cache_dirty = FALSE;
+ m_cache_dirty = false;
/* execute */
do
@@ -308,7 +308,7 @@ void rsp_device::execute_run_drc()
void rsp_device::rspdrc_flush_drc_cache()
{
if (!allow_drc()) return;
- m_cache_dirty = TRUE;
+ m_cache_dirty = true;
}
/*-------------------------------------------------
@@ -329,12 +329,12 @@ void rsp_device::code_flush_cache()
static_generate_out_of_cycles();
/* add subroutines for memory accesses */
- static_generate_memory_accessor(1, FALSE, "read8", m_read8);
- static_generate_memory_accessor(1, TRUE, "write8", m_write8);
- static_generate_memory_accessor(2, FALSE, "read16", m_read16);
- static_generate_memory_accessor(2, TRUE, "write16", m_write16);
- static_generate_memory_accessor(4, FALSE, "read32", m_read32);
- static_generate_memory_accessor(4, TRUE, "write32", m_write32);
+ static_generate_memory_accessor(1, false, "read8", m_read8);
+ static_generate_memory_accessor(1, true, "write8", m_write8);
+ static_generate_memory_accessor(2, false, "read16", m_read16);
+ static_generate_memory_accessor(2, true, "write16", m_write16);
+ static_generate_memory_accessor(4, false, "read32", m_read32);
+ static_generate_memory_accessor(4, true, "write32", m_write32);
}
catch (drcuml_block::abort_compilation &)
{
@@ -354,7 +354,7 @@ void rsp_device::code_compile_block(offs_t pc)
compiler_state compiler = { 0 };
const opcode_desc *seqhead, *seqlast;
const opcode_desc *desclist;
- int override = FALSE;
+ int override = false;
drcuml_block *block;
g_profiler.start(PROFILER_DRC_COMPILE);
@@ -394,7 +394,7 @@ void rsp_device::code_compile_block(offs_t pc)
/* are recompiling due to being out of sync and allow future overrides */
else if (seqhead == desclist)
{
- override = TRUE;
+ override = true;
UML_HASH(block, 0, seqhead->pc); // hash mode,pc
}
@@ -428,7 +428,7 @@ void rsp_device::code_compile_block(offs_t pc)
nextpc = seqlast->pc + (seqlast->skipslots + 1) * 4;
/* count off cycles and go there */
- generate_update_cycles(block, &compiler, nextpc, TRUE); // <subtract cycles>
+ generate_update_cycles(block, &compiler, nextpc, true); // <subtract cycles>
/* if the last instruction can change modes, use a variable mode; otherwise, assume the same mode */
if (seqlast->next() == nullptr || seqlast->next()->pc != nextpc)
@@ -638,7 +638,7 @@ void rsp_device::static_generate_memory_accessor(int size, int iswrite, const ch
subtract cycles from the icount and generate
an exception if out
-------------------------------------------------*/
-void rsp_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception)
+void rsp_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception)
{
/* account for cycles */
if (compiler->cycles > 0)
@@ -783,7 +783,7 @@ void rsp_device::generate_branch(drcuml_block *block, compiler_state *compiler,
/* update the cycles and jump through the hash table to the target */
if (desc->targetpc != BRANCH_TARGET_DYNAMIC)
{
- generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE); // <subtract cycles>
+ generate_update_cycles(block, &compiler_temp, desc->targetpc, true); // <subtract cycles>
if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
UML_JMP(block, desc->targetpc | 0x80000000); // jmp desc->targetpc
else
@@ -791,7 +791,7 @@ void rsp_device::generate_branch(drcuml_block *block, compiler_state *compiler,
}
else
{
- generate_update_cycles(block, &compiler_temp, mem(&m_rsp_state->jmpdest), TRUE); // <subtract cycles>
+ generate_update_cycles(block, &compiler_temp, mem(&m_rsp_state->jmpdest), true); // <subtract cycles>
UML_HASHJMP(block, 0, mem(&m_rsp_state->jmpdest), *m_nocode); // hashjmp <mode>,<rsreg>,nocode
}
}
@@ -832,7 +832,7 @@ void rsp_device::generate_delay_slot_and_branch(drcuml_block *block, compiler_st
UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
}
-int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
int in_delay_slot = ((desc->flags & OPFLAG_IN_DELAY_SLOT) != 0);
uint32_t op = desc->opptr.l[0];
@@ -853,25 +853,25 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
case 0x02: /* J - MIPS I */
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
- return TRUE;
+ return true;
case 0x03: /* JAL - MIPS I */
generate_delay_slot_and_branch(block, compiler, desc, 31); // <next instruction + hashjmp>
- return TRUE;
+ return true;
case 0x04: /* BEQ - MIPS I */
UML_CMP(block, R32(RSREG), R32(RTREG)); // cmp <rsreg>,<rtreg>
UML_JMPc(block, COND_NE, skip = compiler->labelnum++); // jmp skip,NE
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
- return TRUE;
+ return true;
case 0x05: /* BNE - MIPS I */
UML_CMP(block, R32(RSREG), R32(RTREG)); // dcmp <rsreg>,<rtreg>
UML_JMPc(block, COND_E, skip = compiler->labelnum++); // jmp skip,E
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
- return TRUE;
+ return true;
case 0x06: /* BLEZ - MIPS I */
if (RSREG != 0)
@@ -883,14 +883,14 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
}
else
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
- return TRUE;
+ return true;
case 0x07: /* BGTZ - MIPS I */
UML_CMP(block, R32(RSREG), 0); // dcmp <rsreg>,0
UML_JMPc(block, COND_LE, skip = compiler->labelnum++); // jmp skip,LE
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
- return TRUE;
+ return true;
/* ----- immediate arithmetic ----- */
@@ -898,7 +898,7 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
case 0x0f: /* LUI - MIPS I */
if (RTREG != 0)
UML_MOV(block, R32(RTREG), SIMMVAL << 16); // dmov <rtreg>,SIMMVAL << 16
- return TRUE;
+ return true;
case 0x08: /* ADDI - MIPS I */
case 0x09: /* ADDIU - MIPS I */
@@ -906,7 +906,7 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
{
UML_ADD(block, R32(RTREG), R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL,V
}
- return TRUE;
+ return true;
case 0x0a: /* SLTI - MIPS I */
if (RTREG != 0)
@@ -914,7 +914,7 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_CMP(block, R32(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL
UML_SETc(block, COND_L, R32(RTREG)); // dset <rtreg>,l
}
- return TRUE;
+ return true;
case 0x0b: /* SLTIU - MIPS I */
if (RTREG != 0)
@@ -922,23 +922,23 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_CMP(block, R32(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL
UML_SETc(block, COND_B, R32(RTREG)); // dset <rtreg>,b
}
- return TRUE;
+ return true;
case 0x0c: /* ANDI - MIPS I */
if (RTREG != 0)
UML_AND(block, R32(RTREG), R32(RSREG), UIMMVAL); // dand <rtreg>,<rsreg>,UIMMVAL
- return TRUE;
+ return true;
case 0x0d: /* ORI - MIPS I */
if (RTREG != 0)
UML_OR(block, R32(RTREG), R32(RSREG), UIMMVAL); // dor <rtreg>,<rsreg>,UIMMVAL
- return TRUE;
+ return true;
case 0x0e: /* XORI - MIPS I */
if (RTREG != 0)
UML_XOR(block, R32(RTREG), R32(RSREG), UIMMVAL); // dxor <rtreg>,<rsreg>,UIMMVAL
- return TRUE;
+ return true;
/* ----- memory load operations ----- */
@@ -948,8 +948,8 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
if (RTREG != 0)
UML_SEXT(block, R32(RTREG), I0, SIZE_BYTE); // dsext <rtreg>,i0,byte
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x21: /* LH - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -957,8 +957,8 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
if (RTREG != 0)
UML_SEXT(block, R32(RTREG), I0, SIZE_WORD); // dsext <rtreg>,i0,word
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x23: /* LW - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -966,8 +966,8 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
if (RTREG != 0)
UML_MOV(block, R32(RTREG), I0);
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x24: /* LBU - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -975,8 +975,8 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
if (RTREG != 0)
UML_AND(block, R32(RTREG), I0, 0xff); // dand <rtreg>,i0,0xff
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x25: /* LHU - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -984,8 +984,8 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
if (RTREG != 0)
UML_AND(block, R32(RTREG), I0, 0xffff); // dand <rtreg>,i0,0xffff
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x32: /* LWC2 - MIPS I */
return m_cop2->generate_lwc2(block, compiler, desc);
@@ -998,24 +998,24 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg>
UML_CALLH(block, *m_write8); // callh write8
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x29: /* SH - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg>
UML_CALLH(block, *m_write16); // callh write16
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x2b: /* SW - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg>
UML_CALLH(block, *m_write32); // callh write32
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x3a: /* SWC2 - MIPS I */
return m_cop2->generate_swc2(block, compiler, desc);
@@ -1034,7 +1034,7 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
//default: /* ??? */ invalid_instruction(op); break;
}
- return FALSE;
+ return false;
}
@@ -1043,7 +1043,7 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
'SPECIAL' group
-------------------------------------------------*/
-int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool rsp_device::generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
uint8_t opswitch = op & 63;
@@ -1058,42 +1058,42 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
{
UML_SHL(block, R32(RDREG), R32(RTREG), SHIFT);
}
- return TRUE;
+ return true;
case 0x02: /* SRL - MIPS I */
if (RDREG != 0)
{
UML_SHR(block, R32(RDREG), R32(RTREG), SHIFT);
}
- return TRUE;
+ return true;
case 0x03: /* SRA - MIPS I */
if (RDREG != 0)
{
UML_SAR(block, R32(RDREG), R32(RTREG), SHIFT);
}
- return TRUE;
+ return true;
case 0x04: /* SLLV - MIPS I */
if (RDREG != 0)
{
UML_SHL(block, R32(RDREG), R32(RTREG), R32(RSREG));
}
- return TRUE;
+ return true;
case 0x06: /* SRLV - MIPS I */
if (RDREG != 0)
{
UML_SHR(block, R32(RDREG), R32(RTREG), R32(RSREG));
}
- return TRUE;
+ return true;
case 0x07: /* SRAV - MIPS I */
if (RDREG != 0)
{
UML_SAR(block, R32(RDREG), R32(RTREG), R32(RSREG));
}
- return TRUE;
+ return true;
/* ----- basic arithmetic ----- */
@@ -1103,7 +1103,7 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
{
UML_ADD(block, R32(RDREG), R32(RSREG), R32(RTREG));
}
- return TRUE;
+ return true;
case 0x22: /* SUB - MIPS I */
case 0x23: /* SUBU - MIPS I */
@@ -1111,7 +1111,7 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
{
UML_SUB(block, R32(RDREG), R32(RSREG), R32(RTREG));
}
- return TRUE;
+ return true;
/* ----- basic logical ops ----- */
@@ -1120,21 +1120,21 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
{
UML_AND(block, R32(RDREG), R32(RSREG), R32(RTREG)); // dand <rdreg>,<rsreg>,<rtreg>
}
- return TRUE;
+ return true;
case 0x25: /* OR - MIPS I */
if (RDREG != 0)
{
UML_OR(block, R32(RDREG), R32(RSREG), R32(RTREG)); // dor <rdreg>,<rsreg>,<rtreg>
}
- return TRUE;
+ return true;
case 0x26: /* XOR - MIPS I */
if (RDREG != 0)
{
UML_XOR(block, R32(RDREG), R32(RSREG), R32(RTREG)); // dxor <rdreg>,<rsreg>,<rtreg>
}
- return TRUE;
+ return true;
case 0x27: /* NOR - MIPS I */
if (RDREG != 0)
@@ -1142,7 +1142,7 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
UML_OR(block, I0, R32(RSREG), R32(RTREG)); // dor i0,<rsreg>,<rtreg>
UML_XOR(block, R32(RDREG), I0, (uint64_t)~0); // dxor <rdreg>,i0,~0
}
- return TRUE;
+ return true;
/* ----- basic comparisons ----- */
@@ -1153,7 +1153,7 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
UML_CMP(block, R32(RSREG), R32(RTREG)); // dcmp <rsreg>,<rtreg>
UML_SETc(block, COND_L, R32(RDREG)); // dset <rdreg>,l
}
- return TRUE;
+ return true;
case 0x2b: /* SLTU - MIPS I */
if (RDREG != 0)
@@ -1161,18 +1161,18 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
UML_CMP(block, R32(RSREG), R32(RTREG)); // dcmp <rsreg>,<rtreg>
UML_SETc(block, COND_B, R32(RDREG)); // dset <rdreg>,b
}
- return TRUE;
+ return true;
/* ----- jumps and branches ----- */
case 0x08: /* JR - MIPS I */
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
- return TRUE;
+ return true;
case 0x09: /* JALR - MIPS I */
generate_delay_slot_and_branch(block, compiler, desc, RDREG); // <next instruction + hashjmp>
- return TRUE;
+ return true;
/* ----- system calls ----- */
@@ -1186,9 +1186,9 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
generate_branch(block, compiler, desc);
UML_EXIT(block, EXECUTE_OUT_OF_CYCLES);
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
@@ -1198,7 +1198,7 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
'REGIMM' group
-------------------------------------------------*/
-int rsp_device::generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool rsp_device::generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
uint8_t opswitch = RTREG;
@@ -1216,7 +1216,7 @@ int rsp_device::generate_regimm(drcuml_block *block, compiler_state *compiler, c
// <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
}
- return TRUE;
+ return true;
case 0x01: /* BGEZ */
case 0x11: /* BGEZAL */
@@ -1231,9 +1231,9 @@ int rsp_device::generate_regimm(drcuml_block *block, compiler_state *compiler, c
else
generate_delay_slot_and_branch(block, compiler, desc, (opswitch & 0x10) ? 31 : 0);
// <next instruction + hashjmp>
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
@@ -1241,7 +1241,7 @@ int rsp_device::generate_regimm(drcuml_block *block, compiler_state *compiler, c
generate_cop0 - compile COP0 opcodes
-------------------------------------------------*/
-int rsp_device::generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool rsp_device::generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
uint8_t opswitch = RSREG;
@@ -1256,20 +1256,20 @@ int rsp_device::generate_cop0(drcuml_block *block, compiler_state *compiler, con
UML_CALLC(block, cfunc_get_cop0_reg, this); // callc cfunc_get_cop0_reg
if(RDREG == 2)
{
- generate_update_cycles(block, compiler, mem(&m_rsp_state->pc), TRUE);
+ generate_update_cycles(block, compiler, mem(&m_rsp_state->pc), true);
UML_HASHJMP(block, 0, mem(&m_rsp_state->pc), *m_nocode);
}
}
- return TRUE;
+ return true;
case 0x04: /* MTCz */
UML_MOV(block, mem(&m_rsp_state->arg0), RDREG); // mov [arg0],<rdreg>
UML_MOV(block, mem(&m_rsp_state->arg1), R32(RTREG)); // mov [arg1],rtreg
UML_CALLC(block, cfunc_set_cop0_reg, this); // callc cfunc_set_cop0_reg
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/***************************************************************************