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-rw-r--r--src/devices/bus/a7800/a78_slot.cpp8
-rw-r--r--src/devices/bus/centronics/printer.cpp18
-rw-r--r--src/devices/bus/gba/gba_slot.cpp4
-rw-r--r--src/devices/bus/generic/slot.cpp2
-rw-r--r--src/devices/bus/generic/slot.h2
-rw-r--r--src/devices/bus/isa/3c503.cpp2
-rw-r--r--src/devices/bus/isa/fdc.cpp2
-rw-r--r--src/devices/bus/isa/gus.cpp4
-rw-r--r--src/devices/bus/isa/hdc.cpp2
-rw-r--r--src/devices/bus/isa/mcd.cpp2
-rw-r--r--src/devices/bus/isa/omti8621.cpp2
-rw-r--r--src/devices/bus/isa/sb16.cpp4
-rw-r--r--src/devices/bus/isa/sblaster.cpp8
-rw-r--r--src/devices/bus/isa/stereo_fx.cpp2
-rw-r--r--src/devices/bus/isa/wdxt_gen.cpp2
-rw-r--r--src/devices/bus/megadrive/md_slot.cpp6
-rw-r--r--src/devices/bus/megadrive/md_slot.h2
-rw-r--r--src/devices/bus/nes/jy.cpp10
-rw-r--r--src/devices/bus/nes/nes_ines.hxx36
-rw-r--r--src/devices/bus/nes/nes_pcb.hxx8
-rw-r--r--src/devices/bus/nes/nes_slot.cpp12
-rw-r--r--src/devices/bus/nes/nes_slot.h2
-rw-r--r--src/devices/bus/nes/nes_unif.hxx10
-rw-r--r--src/devices/bus/sega8/sega8_slot.cpp34
-rw-r--r--src/devices/bus/sega8/sega8_slot.h14
-rw-r--r--src/devices/bus/sms_ctrl/lphaser.cpp2
-rw-r--r--src/devices/bus/sms_ctrl/sports.cpp2
-rw-r--r--src/devices/bus/snes/spc7110.cpp8
-rw-r--r--src/devices/bus/snes/upd.cpp4
-rw-r--r--src/devices/bus/ti99_peb/bwg.h2
-rw-r--r--src/devices/bus/ti99_peb/hfdc.h2
-rw-r--r--src/devices/bus/ti99_peb/peribox.h4
-rw-r--r--src/devices/bus/ti99_peb/spchsyn.cpp2
-rw-r--r--src/devices/bus/ti99_peb/ti_fdc.h4
-rw-r--r--src/devices/bus/ti99x/990_dk.cpp32
-rw-r--r--src/devices/bus/ti99x/990_hd.h4
-rw-r--r--src/devices/bus/ti99x/990_tap.h6
-rw-r--r--src/devices/bus/ti99x/998board.cpp8
-rw-r--r--src/devices/bus/ti99x/handset.cpp4
-rw-r--r--src/devices/bus/vcs/vcs_slot.cpp2
-rw-r--r--src/devices/cpu/apexc/apexc.cpp4
-rw-r--r--src/devices/cpu/arm7/arm7.cpp6
-rw-r--r--src/devices/cpu/arm7/arm7.h4
-rw-r--r--src/devices/cpu/arm7/arm7drc.hxx30
-rw-r--r--src/devices/cpu/ccpu/ccpu.cpp6
-rw-r--r--src/devices/cpu/drcbec.cpp16
-rw-r--r--src/devices/cpu/drcbec.h4
-rw-r--r--src/devices/cpu/drcbex86.cpp8
-rw-r--r--src/devices/cpu/drcbex86.h4
-rw-r--r--src/devices/cpu/drcuml.cpp8
-rw-r--r--src/devices/cpu/dsp56k/dsp56k.cpp32
-rw-r--r--src/devices/cpu/dsp56k/dsp56k.h8
-rw-r--r--src/devices/cpu/h6280/h6280.cpp2
-rw-r--r--src/devices/cpu/i8085/i8085.cpp8
-rw-r--r--src/devices/cpu/i86/i286.cpp2
-rw-r--r--src/devices/cpu/m6800/m6800.cpp4
-rw-r--r--src/devices/cpu/m68000/m68kcpu.cpp6
-rw-r--r--src/devices/cpu/m68000/m68kcpu.h2
-rw-r--r--src/devices/cpu/m6809/6309dasm.cpp9
-rw-r--r--src/devices/cpu/m6809/6809dasm.cpp12
-rw-r--r--src/devices/cpu/m6809/knmidasm.cpp5
-rw-r--r--src/devices/cpu/mcs48/mcs48.cpp42
-rw-r--r--src/devices/cpu/mcs48/mcs48.h16
-rw-r--r--src/devices/cpu/mcs48/mcs48dsm.cpp6
-rw-r--r--src/devices/cpu/mips/mips3.cpp12
-rw-r--r--src/devices/cpu/mips/mips3.h26
-rw-r--r--src/devices/cpu/mips/mips3com.cpp8
-rw-r--r--src/devices/cpu/mips/mips3drc.cpp708
-rw-r--r--src/devices/cpu/powerpc/ppc.h20
-rw-r--r--src/devices/cpu/powerpc/ppccom.cpp52
-rw-r--r--src/devices/cpu/powerpc/ppcdrc.cpp748
-rw-r--r--src/devices/cpu/rsp/rsp.cpp4
-rw-r--r--src/devices/cpu/rsp/rsp.h12
-rw-r--r--src/devices/cpu/rsp/rspcp2.h8
-rw-r--r--src/devices/cpu/rsp/rspcp2d.cpp162
-rw-r--r--src/devices/cpu/rsp/rspcp2d.h8
-rw-r--r--src/devices/cpu/rsp/rspdrc.cpp146
-rw-r--r--src/devices/cpu/sc61860/sctable.hxx8
-rw-r--r--src/devices/cpu/sh2/sh2.cpp4
-rw-r--r--src/devices/cpu/sh2/sh2.h20
-rw-r--r--src/devices/cpu/sh2/sh2drc.cpp476
-rw-r--r--src/devices/cpu/sh4/sh4.cpp6
-rw-r--r--src/devices/cpu/sh4/sh4.h2
-rw-r--r--src/devices/cpu/sharc/sharc.h4
-rw-r--r--src/devices/cpu/sharc/sharcdrc.cpp112
-rw-r--r--src/devices/cpu/tms34010/tms34010.cpp14
-rw-r--r--src/devices/cpu/z80/z80.cpp24
-rw-r--r--src/devices/imagedev/flopdrv.cpp2
-rw-r--r--src/devices/imagedev/printer.cpp4
-rw-r--r--src/devices/machine/53c810.cpp4
-rw-r--r--src/devices/machine/6532riot.cpp2
-rw-r--r--src/devices/machine/6821pia.cpp36
-rw-r--r--src/devices/machine/6850acia.cpp2
-rw-r--r--src/devices/machine/appldriv.cpp6
-rw-r--r--src/devices/machine/bcreader.h2
-rw-r--r--src/devices/machine/ds2404.cpp2
-rw-r--r--src/devices/machine/e05a30.cpp20
-rw-r--r--src/devices/machine/f3853.cpp24
-rw-r--r--src/devices/machine/gt64xxx.cpp6
-rw-r--r--src/devices/machine/ldpr8210.cpp6
-rw-r--r--src/devices/machine/ldvp931.cpp2
-rw-r--r--src/devices/machine/mos6551.cpp2
-rw-r--r--src/devices/machine/pcf8593.cpp6
-rw-r--r--src/devices/machine/ram.cpp12
-rw-r--r--src/devices/machine/rtc65271.cpp2
-rw-r--r--src/devices/machine/s2636.h2
-rw-r--r--src/devices/machine/s3c24xx.hxx6
-rw-r--r--src/devices/machine/smartmed.cpp22
-rw-r--r--src/devices/machine/upd7002.cpp2
-rw-r--r--src/devices/machine/vrc4373.cpp6
-rw-r--r--src/devices/sound/cdda.cpp14
-rw-r--r--src/devices/sound/discrete.h2
-rw-r--r--src/devices/sound/hc55516.cpp8
-rw-r--r--src/devices/sound/pokey.cpp2
-rw-r--r--src/devices/sound/sid.cpp6
-rw-r--r--src/devices/sound/sidvoice.cpp14
-rw-r--r--src/devices/sound/t6w28.cpp2
-rw-r--r--src/devices/sound/tms5110.cpp18
-rw-r--r--src/devices/sound/tms5220.cpp24
-rw-r--r--src/devices/sound/upd7759.cpp2
-rw-r--r--src/devices/sound/ymf271.cpp2
-rw-r--r--src/devices/sound/ymz280b.cpp2
-rw-r--r--src/devices/video/crtc_ega.cpp26
-rw-r--r--src/devices/video/dl1416.cpp12
-rw-r--r--src/devices/video/ef9365.cpp2
-rw-r--r--src/devices/video/mc6845.cpp18
-rw-r--r--src/devices/video/tms9927.cpp20
-rw-r--r--src/devices/video/tms9927.h2
-rw-r--r--src/devices/video/vooddefs.h4
-rw-r--r--src/devices/video/voodoo.cpp118
-rw-r--r--src/devices/video/voodoo.h2
-rw-r--r--src/devices/video/zeus2.cpp30
-rw-r--r--src/devices/video/zeus2.h2
133 files changed, 1810 insertions, 1812 deletions
diff --git a/src/devices/bus/a7800/a78_slot.cpp b/src/devices/bus/a7800/a78_slot.cpp
index 31c0cf7c514..a68e0daeeb0 100644
--- a/src/devices/bus/a7800/a78_slot.cpp
+++ b/src/devices/bus/a7800/a78_slot.cpp
@@ -351,8 +351,8 @@ image_init_result a78_cart_slot_device::call_load()
if (software_entry() != nullptr)
{
const char *pcb_name;
- bool has_ram = get_software_region("ram") ? TRUE : FALSE;
- bool has_nvram = get_software_region("nvram") ? TRUE : FALSE;
+ bool has_ram = get_software_region("ram") ? true : false;
+ bool has_nvram = get_software_region("nvram") ? true : false;
len = get_software_region_length("rom");
m_cart->rom_alloc(len, tag());
@@ -389,7 +389,7 @@ image_init_result a78_cart_slot_device::call_load()
}
// let's try to auto-fix some common errors in the header
- mapper = validate_header((head[53] << 8) | head[54], TRUE);
+ mapper = validate_header((head[53] << 8) | head[54], true);
switch (mapper & 0x2e)
{
@@ -530,7 +530,7 @@ std::string a78_cart_slot_device::get_default_card_software()
m_file->read(&head[0], 128);
// let's try to auto-fix some common errors in the header
- mapper = validate_header((head[53] << 8) | head[54], FALSE);
+ mapper = validate_header((head[53] << 8) | head[54], false);
switch (mapper & 0x2e)
{
diff --git a/src/devices/bus/centronics/printer.cpp b/src/devices/bus/centronics/printer.cpp
index 3a09169ddee..3306cbf2d46 100644
--- a/src/devices/bus/centronics/printer.cpp
+++ b/src/devices/bus/centronics/printer.cpp
@@ -60,13 +60,13 @@ void centronics_printer_device::device_timer(emu_timer &timer, device_timer_id i
case TIMER_ACK:
output_ack(param);
- if (param == FALSE)
+ if (param == false)
{
/* data is now ready, output it */
m_printer->output(m_data);
/* ready to receive more data, return BUSY to low */
- timer_set(attotime::from_usec(7), TIMER_BUSY, FALSE);
+ timer_set(attotime::from_usec(7), TIMER_BUSY, false);
}
break;
@@ -74,15 +74,15 @@ void centronics_printer_device::device_timer(emu_timer &timer, device_timer_id i
m_busy = param;
output_busy(m_busy);
- if (param == TRUE)
+ if (param == true)
{
/* timer to turn ACK low to receive data */
- timer_set(attotime::from_usec(10), TIMER_ACK, FALSE);
+ timer_set(attotime::from_usec(10), TIMER_ACK, false);
}
else
{
/* timer to return ACK to high state */
- timer_set(attotime::from_usec(5), TIMER_ACK, TRUE);
+ timer_set(attotime::from_usec(5), TIMER_ACK, true);
}
}
}
@@ -97,7 +97,7 @@ void centronics_printer_device::device_start()
void centronics_printer_device::device_reset()
{
- m_busy = FALSE;
+ m_busy = false;
output_busy(m_busy);
output_fault(1);
output_ack(1);
@@ -112,10 +112,10 @@ void centronics_printer_device::device_reset()
WRITE_LINE_MEMBER( centronics_printer_device::input_strobe )
{
/* look for a high -> low transition */
- if (m_strobe == TRUE && state == FALSE && m_busy == FALSE)
+ if (m_strobe == true && state == false && m_busy == false)
{
/* STROBE has gone low, data is ready */
- timer_set(attotime::zero, TIMER_BUSY, TRUE);
+ timer_set(attotime::zero, TIMER_BUSY, true);
}
m_strobe = state;
@@ -130,6 +130,6 @@ WRITE_LINE_MEMBER( centronics_printer_device::input_strobe )
WRITE_LINE_MEMBER(centronics_printer_device::input_init)
{
/* reset printer if line is low */
- if (state == FALSE)
+ if (state == false)
device_reset();
}
diff --git a/src/devices/bus/gba/gba_slot.cpp b/src/devices/bus/gba/gba_slot.cpp
index bfedecb9d0a..fc8bcd038db 100644
--- a/src/devices/bus/gba/gba_slot.cpp
+++ b/src/devices/bus/gba/gba_slot.cpp
@@ -319,7 +319,7 @@ int gba_cart_slot_device::get_cart_type(uint8_t *ROM, uint32_t len)
if (gba_chip_has_conflict(chip))
{
char game_code[5] = { 0 };
- bool resolved = FALSE;
+ bool resolved = false;
if (len >= 0xac + 4)
memcpy(game_code, ROM + 0xac, 4);
@@ -335,7 +335,7 @@ int gba_cart_slot_device::get_cart_type(uint8_t *ROM, uint32_t len)
if (!strcmp(game_code, item->game_code))
{
chip |= item->chip;
- resolved = TRUE;
+ resolved = true;
break;
}
}
diff --git a/src/devices/bus/generic/slot.cpp b/src/devices/bus/generic/slot.cpp
index 9b5ddc4e2c8..a3db648b0e5 100644
--- a/src/devices/bus/generic/slot.cpp
+++ b/src/devices/bus/generic/slot.cpp
@@ -91,7 +91,7 @@ generic_slot_device::generic_slot_device(const machine_config &mconfig, const ch
m_interface(nullptr),
m_default_card("rom"),
m_extensions("bin"),
- m_must_be_loaded(FALSE),
+ m_must_be_loaded(false),
m_width(GENERIC_ROM8_WIDTH),
m_endianness(ENDIANNESS_LITTLE), m_cart(nullptr)
{
diff --git a/src/devices/bus/generic/slot.h b/src/devices/bus/generic/slot.h
index 4bf58ff4a3d..434f68fba10 100644
--- a/src/devices/bus/generic/slot.h
+++ b/src/devices/bus/generic/slot.h
@@ -64,7 +64,7 @@ enum
#define MCFG_GENERIC_MANDATORY \
- static_cast<generic_slot_device *>(device)->set_must_be_loaded(TRUE);
+ static_cast<generic_slot_device *>(device)->set_must_be_loaded(true);
#define MCFG_GENERIC_WIDTH(_width) \
static_cast<generic_slot_device *>(device)->set_width(_width);
diff --git a/src/devices/bus/isa/3c503.cpp b/src/devices/bus/isa/3c503.cpp
index 3bc90516cde..8caa4abe4e8 100644
--- a/src/devices/bus/isa/3c503.cpp
+++ b/src/devices/bus/isa/3c503.cpp
@@ -46,7 +46,7 @@ void el2_3c503_device::device_start() {
chan++;
idcfr >>= 1;
}
- m_isa->set_dma_channel(chan, this, FALSE);
+ m_isa->set_dma_channel(chan, this, false);
}
}
diff --git a/src/devices/bus/isa/fdc.cpp b/src/devices/bus/isa/fdc.cpp
index c3b1d18eb69..807e9cfebc5 100644
--- a/src/devices/bus/isa/fdc.cpp
+++ b/src/devices/bus/isa/fdc.cpp
@@ -83,7 +83,7 @@ void isa8_fdc_device::device_start()
{
set_isa_device();
m_isa->install_device(0x03f0, 0x03f7, *fdc, &pc_fdc_interface::map);
- m_isa->set_dma_channel(2, this, TRUE);
+ m_isa->set_dma_channel(2, this, true);
}
void isa8_fdc_device::device_reset()
diff --git a/src/devices/bus/isa/gus.cpp b/src/devices/bus/isa/gus.cpp
index 165937ea771..d7cc2ccb89b 100644
--- a/src/devices/bus/isa/gus.cpp
+++ b/src/devices/bus/isa/gus.cpp
@@ -1504,7 +1504,7 @@ WRITE_LINE_MEMBER(isa16_gus_device::sb_irq)
WRITE_LINE_MEMBER(isa16_gus_device::drq1_w)
{
- m_isa->set_dma_channel(m_gf1->dma_channel1(), this, TRUE);
+ m_isa->set_dma_channel(m_gf1->dma_channel1(), this, true);
switch(m_gf1->dma_channel1())
{
case 1:
@@ -1529,7 +1529,7 @@ WRITE_LINE_MEMBER(isa16_gus_device::drq1_w)
WRITE_LINE_MEMBER(isa16_gus_device::drq2_w)
{
- m_isa->set_dma_channel(m_gf1->dma_channel2(), this, TRUE);
+ m_isa->set_dma_channel(m_gf1->dma_channel2(), this, true);
switch(m_gf1->dma_channel2())
{
case 1:
diff --git a/src/devices/bus/isa/hdc.cpp b/src/devices/bus/isa/hdc.cpp
index 50859730064..10bd50349d0 100644
--- a/src/devices/bus/isa/hdc.cpp
+++ b/src/devices/bus/isa/hdc.cpp
@@ -1000,7 +1000,7 @@ void isa8_hdc_device::device_start()
{
set_isa_device();
m_isa->install_device(0x0320, 0x0323, read8_delegate( FUNC(isa8_hdc_device::pc_hdc_r), this ), write8_delegate( FUNC(isa8_hdc_device::pc_hdc_w), this ) );
- m_isa->set_dma_channel(3, this, FALSE);
+ m_isa->set_dma_channel(3, this, false);
}
//-------------------------------------------------
diff --git a/src/devices/bus/isa/mcd.cpp b/src/devices/bus/isa/mcd.cpp
index e525039e3fd..1ee7b66ccfd 100644
--- a/src/devices/bus/isa/mcd.cpp
+++ b/src/devices/bus/isa/mcd.cpp
@@ -49,7 +49,7 @@ void mcd_isa_device::device_start()
{
cdrom_image_device::device_start();
set_isa_device();
- m_isa->set_dma_channel(5, this, FALSE);
+ m_isa->set_dma_channel(5, this, false);
m_isa->install_device(0x0310, 0x0311, *this, &mcd_isa_device::map, 16);
}
diff --git a/src/devices/bus/isa/omti8621.cpp b/src/devices/bus/isa/omti8621.cpp
index 7b334a24f4c..fe475f4f0a1 100644
--- a/src/devices/bus/isa/omti8621.cpp
+++ b/src/devices/bus/isa/omti8621.cpp
@@ -331,7 +331,7 @@ void omti8621_device::device_reset()
m_isa->install_device(0x03f0, 0x03f7, *m_fdc, &pc_fdc_interface::map);
}
- m_isa->set_dma_channel(2, this, TRUE);
+ m_isa->set_dma_channel(2, this, true);
m_installed = true;
}
diff --git a/src/devices/bus/isa/sb16.cpp b/src/devices/bus/isa/sb16.cpp
index abf4ea3a513..b1ccd4cfd84 100644
--- a/src/devices/bus/isa/sb16.cpp
+++ b/src/devices/bus/isa/sb16.cpp
@@ -710,8 +710,8 @@ void sb16_lle_device::device_start()
m_isa->install_device(0x0388, 0x0389, read8_delegate(FUNC(ymf262_device::read), ymf262), write8_delegate(FUNC(ymf262_device::write), ymf262));
m_isa->install_device(0x0220, 0x0223, read8_delegate(FUNC(ymf262_device::read), ymf262), write8_delegate(FUNC(ymf262_device::write), ymf262));
m_isa->install_device(0x0228, 0x0229, read8_delegate(FUNC(ymf262_device::read), ymf262), write8_delegate(FUNC(ymf262_device::write), ymf262));
- m_isa->set_dma_channel(1, this, FALSE);
- m_isa->set_dma_channel(5, this, FALSE);
+ m_isa->set_dma_channel(1, this, false);
+ m_isa->set_dma_channel(5, this, false);
m_timer = timer_alloc();
}
diff --git a/src/devices/bus/isa/sblaster.cpp b/src/devices/bus/isa/sblaster.cpp
index a26bb27502d..6c1cd476d76 100644
--- a/src/devices/bus/isa/sblaster.cpp
+++ b/src/devices/bus/isa/sblaster.cpp
@@ -1311,7 +1311,7 @@ void isa8_sblaster1_0_device::device_start()
// 1.0 always has the SAA1099s for CMS back-compatibility
m_isa->install_device(0x0220, 0x0221, read8_delegate( FUNC(isa8_sblaster1_0_device::saa1099_16_r), this ), write8_delegate( FUNC(isa8_sblaster1_0_device::saa1099_1_16_w), this ) );
m_isa->install_device(0x0222, 0x0223, read8_delegate( FUNC(isa8_sblaster1_0_device::saa1099_16_r), this ), write8_delegate( FUNC(isa8_sblaster1_0_device::saa1099_2_16_w), this ) );
- m_isa->set_dma_channel(1, this, FALSE);
+ m_isa->set_dma_channel(1, this, false);
m_dsp.version = 0x0105;
sb8_device::device_start();
}
@@ -1320,7 +1320,7 @@ void isa8_sblaster1_5_device::device_start()
{
set_isa_device();
/* 1.5 makes CM/S support optional (empty sockets, but they work if the user populates them!) */
- m_isa->set_dma_channel(1, this, FALSE);
+ m_isa->set_dma_channel(1, this, false);
m_dsp.version = 0x0200;
sb8_device::device_start();
}
@@ -1363,8 +1363,8 @@ void sb16_device::device_start()
void isa16_sblaster16_device::device_start()
{
set_isa_device();
- m_isa->set_dma_channel(1, this, FALSE);
- m_isa->set_dma_channel(5, this, FALSE);
+ m_isa->set_dma_channel(1, this, false);
+ m_isa->set_dma_channel(5, this, false);
m_dsp.version = 0x0405; // diagnose.exe rejects anything lower than 0x0402
sb16_device::device_start();
}
diff --git a/src/devices/bus/isa/stereo_fx.cpp b/src/devices/bus/isa/stereo_fx.cpp
index 1119f09e2eb..8d239baa8f5 100644
--- a/src/devices/bus/isa/stereo_fx.cpp
+++ b/src/devices/bus/isa/stereo_fx.cpp
@@ -212,7 +212,7 @@ void stereo_fx_device::device_start()
m_isa->install_device(0x0228, 0x0229, read8_delegate(FUNC(ym3812_device::read), ym3812), write8_delegate(FUNC(ym3812_device::write), ym3812));
m_timer = timer_alloc();
m_timer->adjust(attotime::from_hz(2000000), 0, attotime::from_hz(2000000));
- m_isa->set_dma_channel(1, this, FALSE);
+ m_isa->set_dma_channel(1, this, false);
}
diff --git a/src/devices/bus/isa/wdxt_gen.cpp b/src/devices/bus/isa/wdxt_gen.cpp
index 518e081f6ab..9cc67d0d701 100644
--- a/src/devices/bus/isa/wdxt_gen.cpp
+++ b/src/devices/bus/isa/wdxt_gen.cpp
@@ -208,7 +208,7 @@ void wdxt_gen_device::device_start()
set_isa_device();
m_isa->install_rom(this, 0xc8000, 0xc9fff, "hdc", "hdc");
m_isa->install_device(0x0320, 0x0323, READ8_DEVICE_DELEGATE(m_host, wd11c00_17_device, io_r), WRITE8_DEVICE_DELEGATE(m_host, wd11c00_17_device, io_w));
- m_isa->set_dma_channel(3, this, FALSE);
+ m_isa->set_dma_channel(3, this, false);
}
diff --git a/src/devices/bus/megadrive/md_slot.cpp b/src/devices/bus/megadrive/md_slot.cpp
index 0886d204e98..2c34c4b58e3 100644
--- a/src/devices/bus/megadrive/md_slot.cpp
+++ b/src/devices/bus/megadrive/md_slot.cpp
@@ -1001,7 +1001,7 @@ void base_md_cart_slot_device::file_logging(uint8_t *ROM8, uint32_t rom_len, uin
char serial[14], io[16], modem[12], memo[40], country[16];
uint32_t rom_start, rom_end, ram_start, ram_end, sram_start = 0, sram_end = 0;
uint16_t checksum, csum = 0;
- bool valid_sram = FALSE, is_pico = FALSE;
+ bool valid_sram = false, is_pico = false;
std::string ctrl(""), reg("");
// LOG FILE DETAILS
@@ -1024,7 +1024,7 @@ void base_md_cart_slot_device::file_logging(uint8_t *ROM8, uint32_t rom_len, uin
for (int i = 0; i < 16; i++)
console[i] = ROM8[0x100 + (i ^ 1)];
if (!strncmp("SEGA PICO", console, 9))
- is_pico = TRUE;
+ is_pico = true;
for (int i = 0; i < 16; i++)
copyright[i] = ROM8[0x110 + (i ^ 1)];
for (int i = 0; i < 48; i++)
@@ -1051,7 +1051,7 @@ void base_md_cart_slot_device::file_logging(uint8_t *ROM8, uint32_t rom_len, uin
ram_end = (ROM8[0x1ad] << 24 | ROM8[0x1ac] << 16 | ROM8[0x1af] << 8 | ROM8[0x1ae]);;
if (ROM8[0x1b1] == 'R' && ROM8[0x1b0] == 'A')
{
- valid_sram = TRUE;
+ valid_sram = true;
sram_start = (ROM8[0x1b5] << 24 | ROM8[0x1b4] << 16 | ROM8[0x1b7] << 8 | ROM8[0x1b6]);
sram_end = (ROM8[0x1b9] << 24 | ROM8[0x1b8] << 16 | ROM8[0x1bb] << 8 | ROM8[0x1ba]);
}
diff --git a/src/devices/bus/megadrive/md_slot.h b/src/devices/bus/megadrive/md_slot.h
index 4953ac046cd..981b172661e 100644
--- a/src/devices/bus/megadrive/md_slot.h
+++ b/src/devices/bus/megadrive/md_slot.h
@@ -260,7 +260,7 @@ extern const device_type COPERA_CART_SLOT;
#define MCFG_MD_CARTRIDGE_NOT_MANDATORY \
- static_cast<md_cart_slot_device *>(device)->set_must_be_loaded(FALSE);
+ static_cast<md_cart_slot_device *>(device)->set_must_be_loaded(false);
#endif
diff --git a/src/devices/bus/nes/jy.cpp b/src/devices/bus/nes/jy.cpp
index cf947e4b74d..acba59d0a18 100644
--- a/src/devices/bus/nes/jy.cpp
+++ b/src/devices/bus/nes/jy.cpp
@@ -163,7 +163,7 @@ READ8_MEMBER(nes_jy_typea_device::chr_r)
void nes_jy_typea_device::irq_clock(int mode, int blanked)
{
- bool clock = FALSE, fire = FALSE;
+ bool clock = false, fire = false;
if (m_irq_mode != mode)
return;
@@ -177,7 +177,7 @@ void nes_jy_typea_device::irq_clock(int mode, int blanked)
{
if ((m_irq_prescale & m_irq_prescale_mask) == 0)
{
- clock = TRUE;
+ clock = true;
m_irq_prescale = (m_irq_prescale_mask == 7) ? ((m_irq_prescale & 0xf8) | 7) : 0xff;
}
else
@@ -188,7 +188,7 @@ void nes_jy_typea_device::irq_clock(int mode, int blanked)
{
if ((m_irq_prescale & m_irq_prescale_mask) == m_irq_prescale_mask)
{
- clock = TRUE;
+ clock = true;
m_irq_prescale = (m_irq_prescale_mask == 7) ? (m_irq_prescale & 0xf8) : 0;
}
else
@@ -202,7 +202,7 @@ void nes_jy_typea_device::irq_clock(int mode, int blanked)
{
if (m_irq_count == 0)
{
- fire = TRUE;
+ fire = true;
m_irq_count = 0xff;
}
else
@@ -213,7 +213,7 @@ void nes_jy_typea_device::irq_clock(int mode, int blanked)
{
if (m_irq_count == 0xff)
{
- fire = TRUE;
+ fire = true;
m_irq_count = 0;
}
else
diff --git a/src/devices/bus/nes/nes_ines.hxx b/src/devices/bus/nes/nes_ines.hxx
index c7214ee9bc0..0d053cd9e12 100644
--- a/src/devices/bus/nes/nes_ines.hxx
+++ b/src/devices/bus/nes/nes_ines.hxx
@@ -343,11 +343,11 @@ void nes_cart_slot_device::call_load_ines()
uint32_t prg_size, vrom_size;
uint8_t header[0x10];
uint8_t mapper, submapper = 0, local_options;
- bool ines20 = FALSE, prg16k;
+ bool ines20 = false, prg16k;
std::string mapinfo;
int pcb_id = 0, mapint1 = 0, mapint2 = 0, mapint3 = 0, mapint4 = 0;
int crc_hack = 0;
- bool bus_conflict = FALSE;
+ bool bus_conflict = false;
// read out the header
fseek(0, SEEK_SET);
@@ -371,7 +371,7 @@ void nes_cart_slot_device::call_load_ines()
break;
case 0x8: // it's iNES 2.0 format
- ines20 = TRUE;
+ ines20 = true;
case 0x0:
default:
mapper |= header[7] & 0xf0;
@@ -423,11 +423,11 @@ void nes_cart_slot_device::call_load_ines()
logerror("Unimplemented iNES2.0 submapper: SEROM/SHROM/SH1ROM.\n");
// 002, 003, 007: UxROM, CNROM, AxROM
else if (mapper == 2 && submapper == 2)
- bus_conflict = TRUE;
+ bus_conflict = true;
else if (mapper == 3 && submapper == 2)
- bus_conflict = TRUE;
+ bus_conflict = true;
else if (mapper == 7 && submapper == 2)
- bus_conflict = TRUE;
+ bus_conflict = true;
// 021, 023, 025: VRC4 / VRC2
else if (mapper == 21 || mapper == 23 || mapper == 25)
{
@@ -464,7 +464,7 @@ void nes_cart_slot_device::call_load_ines()
// iNES Mapper 071
else if (mapper == 71 && submapper == 1)
{
- m_cart->set_pcb_ctrl_mirror(TRUE); // Mapper 71 is used for 2 diff boards
+ m_cart->set_pcb_ctrl_mirror(true); // Mapper 71 is used for 2 diff boards
}
// iNES Mapper 078
else if (mapper == 78)
@@ -498,8 +498,8 @@ void nes_cart_slot_device::call_load_ines()
m_cart->set_mirroring(BIT(local_options, 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
if (BIT(local_options, 1))
battery_size = NES_BATTERY_SIZE; // with original iNES format we can only support 8K WRAM battery
- m_cart->set_trainer(BIT(local_options, 2) ? TRUE : FALSE);
- m_cart->set_four_screen_vram(BIT(local_options, 3) ? TRUE : FALSE);
+ m_cart->set_trainer(BIT(local_options, 2) ? true : false);
+ m_cart->set_four_screen_vram(BIT(local_options, 3) ? true : false);
if (ines20)
{
@@ -537,7 +537,7 @@ void nes_cart_slot_device::call_load_ines()
case NOCASH_NOCHR:
// this mapper uses mirroring flags differently
- m_cart->set_four_screen_vram(FALSE);
+ m_cart->set_four_screen_vram(false);
switch (local_options & 0x09)
{
case 0x00:
@@ -607,31 +607,31 @@ void nes_cart_slot_device::call_load_ines()
if (crc_hack && !submapper)
m_cart->set_mirroring(PPU_MIRROR_HIGH); // Major League has hardwired mirroring
else if (!submapper)
- m_cart->set_pcb_ctrl_mirror(TRUE);
+ m_cart->set_pcb_ctrl_mirror(true);
break;
case DIS_74X161X161X32:
if (mapper == 70)
m_cart->set_mirroring(PPU_MIRROR_VERT); // only hardwired mirroring makes different mappers 70 & 152
else
- m_cart->set_pcb_ctrl_mirror(TRUE);
+ m_cart->set_pcb_ctrl_mirror(true);
break;
case SUNSOFT_2:
if (mapper == 93)
m_cart->set_mirroring(PPU_MIRROR_VERT); // only hardwired mirroring makes different mappers 89 & 93
else
- m_cart->set_pcb_ctrl_mirror(TRUE);
+ m_cart->set_pcb_ctrl_mirror(true);
break;
case HES_BOARD:
if (crc_hack)
- m_cart->set_pcb_ctrl_mirror(TRUE); // Mapper 113 is used for 2 diff boards
+ m_cart->set_pcb_ctrl_mirror(true); // Mapper 113 is used for 2 diff boards
break;
case CAMERICA_BF9093:
if (crc_hack && !submapper)
- m_cart->set_pcb_ctrl_mirror(TRUE); // Mapper 71 is used for 2 diff boards
+ m_cart->set_pcb_ctrl_mirror(true); // Mapper 71 is used for 2 diff boards
break;
case STD_BXROM:
@@ -670,7 +670,7 @@ void nes_cart_slot_device::call_load_ines()
case TAITO_X1_005:
if (mapper == 207)
- m_cart->set_x1_005_alt(TRUE);
+ m_cart->set_x1_005_alt(true);
mapper_sram_size = m_cart->get_mapper_sram_size();
break;
@@ -814,7 +814,7 @@ void nes_cart_slot_device::call_load_ines()
const char * nes_cart_slot_device::get_default_card_ines(uint8_t *ROM, uint32_t len)
{
uint8_t mapper, submapper = 0;
- bool ines20 = FALSE;
+ bool ines20 = false;
std::string mapinfo;
int pcb_id = 0, mapint1 = 0, mapint2 = 0, mapint3 = 0, mapint4 = 0;
int crc_hack = 0;
@@ -829,7 +829,7 @@ const char * nes_cart_slot_device::get_default_card_ines(uint8_t *ROM, uint32_t
break;
case 0x8: // it's iNES 2.0 format
- ines20 = TRUE;
+ ines20 = true;
case 0x0:
default:
mapper |= ROM[7] & 0xf0;
diff --git a/src/devices/bus/nes/nes_pcb.hxx b/src/devices/bus/nes/nes_pcb.hxx
index cc4def22dc0..49a2e234b81 100644
--- a/src/devices/bus/nes/nes_pcb.hxx
+++ b/src/devices/bus/nes/nes_pcb.hxx
@@ -477,7 +477,7 @@ void nes_cart_slot_device::call_load_pcb()
{
// A few boards uses 4-screen mirroring: Gauntlet (DDROM or TRR1ROM or Tengen 800004),
// Rad Racer II (TVROM), and Napoleon Senki (IREM LROG017 with 74*161/161/21/138)
- m_cart->set_four_screen_vram(TRUE);
+ m_cart->set_four_screen_vram(true);
m_cart->set_mirroring(PPU_MIRROR_4SCREEN);
}
if (!strcmp(mirroring, "pcb_controlled"))
@@ -487,7 +487,7 @@ void nes_cart_slot_device::call_load_pcb()
// See e.g. HES 6-in-1 vs other HES games, Irem Major League vs other G-101 games,
// Sunsoft-2 Shanghai vs Mito Koumon, Camerica BF9093 games vs BF9097 games, etc.
// Boards where all games control mirroring do not make real use of this.
- m_cart->set_pcb_ctrl_mirror(TRUE);
+ m_cart->set_pcb_ctrl_mirror(true);
}
}
@@ -513,7 +513,7 @@ void nes_cart_slot_device::call_load_pcb()
if (m_pcb_id == TAITO_X1_005 && get_feature("x1-pin17") != nullptr && get_feature("x1-pin31") != nullptr)
{
if (!strcmp(get_feature("x1-pin17"), "CIRAM A10") && !strcmp(get_feature("x1-pin31"), "NC"))
- m_cart->set_x1_005_alt(TRUE);
+ m_cart->set_x1_005_alt(true);
}
if (m_pcb_id == KONAMI_VRC2)
@@ -554,7 +554,7 @@ void nes_cart_slot_device::call_load_pcb()
// pirate variants of boards with bus conflict are often not suffering from it
// and actually games glitch if bus conflict is emulated...
if (get_feature("bus_conflict") && !strcmp(get_feature("bus_conflict"), "no"))
- m_cart->set_bus_conflict(FALSE);
+ m_cart->set_bus_conflict(false);
// SETUP step 4: logging what we have found
diff --git a/src/devices/bus/nes/nes_slot.cpp b/src/devices/bus/nes/nes_slot.cpp
index 596ca7d8d40..8dcb2cc7ba1 100644
--- a/src/devices/bus/nes/nes_slot.cpp
+++ b/src/devices/bus/nes/nes_slot.cpp
@@ -119,11 +119,11 @@ device_nes_cart_interface::device_nes_cart_interface(const machine_config &mconf
m_vrc_ls_prg_b(0),
m_vrc_ls_chr(0),
m_mirroring(PPU_MIRROR_NONE),
- m_pcb_ctrl_mirror(FALSE),
- m_four_screen_vram(FALSE),
- m_has_trainer(FALSE),
- m_x1_005_alt_mirroring(FALSE),
- m_bus_conflict(TRUE),
+ m_pcb_ctrl_mirror(false),
+ m_four_screen_vram(false),
+ m_has_trainer(false),
+ m_x1_005_alt_mirroring(false),
+ m_bus_conflict(true),
m_open_bus(0),
m_prg_chunks(0),
m_prg_mask(0xffff),
@@ -583,7 +583,7 @@ uint8_t device_nes_cart_interface::hi_access_rom(uint32_t offset)
uint8_t device_nes_cart_interface::account_bus_conflict(uint32_t offset, uint8_t data)
{
// pirate variants of boards subject to bus conflict are often not subject to it
- // so we allow to set m_bus_conflict to FALSE at loading time when necessary
+ // so we allow to set m_bus_conflict to false at loading time when necessary
if (m_bus_conflict)
return data & hi_access_rom(offset);
else
diff --git a/src/devices/bus/nes/nes_slot.h b/src/devices/bus/nes/nes_slot.h
index 55adc6780e4..94b54c9542b 100644
--- a/src/devices/bus/nes/nes_slot.h
+++ b/src/devices/bus/nes/nes_slot.h
@@ -421,7 +421,7 @@ extern const device_type NES_CART_SLOT;
MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
#define MCFG_NES_CARTRIDGE_NOT_MANDATORY \
- static_cast<nes_cart_slot_device *>(device)->set_must_be_loaded(FALSE);
+ static_cast<nes_cart_slot_device *>(device)->set_must_be_loaded(false);
// Hacky configuration to add a slot with fixed disksys interface
diff --git a/src/devices/bus/nes/nes_unif.hxx b/src/devices/bus/nes/nes_unif.hxx
index 168ca61a7ab..1aba38c2b6f 100644
--- a/src/devices/bus/nes/nes_unif.hxx
+++ b/src/devices/bus/nes/nes_unif.hxx
@@ -210,7 +210,7 @@ void nes_cart_slot_device::call_load_unif()
uint8_t buffer[4], mirror = 0;
char magic2[4];
char unif_mapr[32]; // here we should store MAPR chunks
- bool mapr_chunk_found = FALSE, small_prg = FALSE;
+ bool mapr_chunk_found = false, small_prg = false;
// allocate space to temporarily store PRG & CHR banks
std::vector<uint8_t> temp_prg(256 * 0x4000);
@@ -237,7 +237,7 @@ void nes_cart_slot_device::call_load_unif()
{
if ((magic2[0] == 'M') && (magic2[1] == 'A') && (magic2[2] == 'P') && (magic2[3] == 'R'))
{
- mapr_chunk_found = TRUE;
+ mapr_chunk_found = true;
logerror("[MAPR] chunk found: ");
fread(&buffer, 4);
chunk_length = buffer[0] | (buffer[1] << 8) | (buffer[2] << 16) | (buffer[3] << 24);
@@ -384,7 +384,7 @@ void nes_cart_slot_device::call_load_unif()
logerror("It consists of %d 16K-blocks.\n", chunk_length / 0x4000);
else
{
- small_prg = TRUE;
+ small_prg = true;
logerror("This chunk is smaller than 16K: the emulation might have issues. Please report this file to the MESS forums.\n");
}
@@ -438,7 +438,7 @@ void nes_cart_slot_device::call_load_unif()
prgram_size = prgram * 0x2000;
vram_size = vram_chunks * 0x2000;
- m_cart->set_four_screen_vram(FALSE);
+ m_cart->set_four_screen_vram(false);
switch (mirror)
{
case 0: // Horizontal Mirroring (Hard Wired)
@@ -454,7 +454,7 @@ void nes_cart_slot_device::call_load_unif()
m_cart->set_mirroring(PPU_MIRROR_HIGH);
break;
case 4: // Four Screens of VRAM (Hard Wired)
- m_cart->set_four_screen_vram(TRUE);
+ m_cart->set_four_screen_vram(true);
m_cart->set_mirroring(PPU_MIRROR_4SCREEN);
break;
case 5: // Mirroring Controlled By Mapper Hardware
diff --git a/src/devices/bus/sega8/sega8_slot.cpp b/src/devices/bus/sega8/sega8_slot.cpp
index 41ae0e6cf17..8a40d997421 100644
--- a/src/devices/bus/sega8/sega8_slot.cpp
+++ b/src/devices/bus/sega8/sega8_slot.cpp
@@ -54,8 +54,8 @@ device_sega8_cart_interface::device_sega8_cart_interface(const machine_config &m
m_rom(nullptr),
m_rom_size(0),
m_rom_page_count(0),
- has_battery(FALSE),
- m_late_battery_enable(FALSE),
+ has_battery(false),
+ m_late_battery_enable(false),
m_lphaser_xoffs(-1),
m_sms_mode(0)
{
@@ -112,7 +112,7 @@ sega8_cart_slot_device::sega8_cart_slot_device(const machine_config &mconfig, de
device_image_interface(mconfig, *this),
device_slot_interface(mconfig, *this),
m_type(SEGA8_BASE_ROM),
- m_must_be_loaded(FALSE),
+ m_must_be_loaded(false),
m_interface("sms_cart"),
m_extensions("bin"), m_cart(nullptr)
{
@@ -124,15 +124,15 @@ sega8_cart_slot_device::sega8_cart_slot_device(const machine_config &mconfig, co
device_image_interface(mconfig, *this),
device_slot_interface(mconfig, *this),
m_type(SEGA8_BASE_ROM),
- m_must_be_loaded(FALSE),
- m_is_card(FALSE),
+ m_must_be_loaded(false),
+ m_is_card(false),
m_interface("sms_cart"),
m_extensions("bin"), m_cart(nullptr)
{
}
sega8_card_slot_device::sega8_card_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
- sega8_cart_slot_device(mconfig, SEGA8_CARD_SLOT, "Sega Master System / Game Gear / SG1000 Card Slot", tag, owner, clock, TRUE, "sega8_card_slot", __FILE__)
+ sega8_cart_slot_device(mconfig, SEGA8_CARD_SLOT, "Sega Master System / Game Gear / SG1000 Card Slot", tag, owner, clock, true, "sega8_card_slot", __FILE__)
{
}
@@ -275,45 +275,45 @@ void sega8_cart_slot_device::setup_ram()
if (m_type == SEGA8_CASTLE)
{
m_cart->ram_alloc(0x2000);
- m_cart->set_has_battery(FALSE);
+ m_cart->set_has_battery(false);
}
else if (m_type == SEGA8_OTHELLO)
{
m_cart->ram_alloc(0x800);
- m_cart->set_has_battery(FALSE);
+ m_cart->set_has_battery(false);
}
else if (m_type == SEGA8_BASIC_L3)
{
m_cart->ram_alloc(0x8000);
- m_cart->set_has_battery(FALSE);
+ m_cart->set_has_battery(false);
}
else if (m_type == SEGA8_MUSIC_EDITOR)
{
m_cart->ram_alloc(0x2800);
- m_cart->set_has_battery(FALSE);
+ m_cart->set_has_battery(false);
}
else if (m_type == SEGA8_DAHJEE_TYPEA)
{
m_cart->ram_alloc(0x2400);
- m_cart->set_has_battery(FALSE);
+ m_cart->set_has_battery(false);
}
else if (m_type == SEGA8_DAHJEE_TYPEB)
{
m_cart->ram_alloc(0x2000);
- m_cart->set_has_battery(FALSE);
+ m_cart->set_has_battery(false);
}
else if (m_type == SEGA8_CODEMASTERS)
{
// Codemasters cart can have 64KB of RAM (Ernie Els Golf? or 8KB?) and no battery
m_cart->ram_alloc(0x10000);
- m_cart->set_has_battery(FALSE);
+ m_cart->set_has_battery(false);
}
else
{
// for generic carts loaded from fullpath we have no way to know exactly if there was RAM,
// how much RAM was in the cart and if there was a battery so we always alloc 32KB and
// we save its content only if the game enable the RAM
- m_cart->set_late_battery(TRUE);
+ m_cart->set_late_battery(true);
m_cart->ram_alloc(0x08000);
}
}
@@ -321,13 +321,13 @@ void sega8_cart_slot_device::setup_ram()
{
// from softlist we rely on the xml to only allocate the correct amount of RAM and to save it only if a battery was present
const char *battery = get_feature("battery");
- m_cart->set_late_battery(FALSE);
+ m_cart->set_late_battery(false);
if (get_software_region_length("ram"))
m_cart->ram_alloc(get_software_region_length("ram"));
if (battery && !strcmp(battery, "yes"))
- m_cart->set_has_battery(TRUE);
+ m_cart->set_has_battery(true);
}
}
@@ -388,7 +388,7 @@ image_init_result sega8_cart_slot_device::call_load()
m_cart->set_sms_mode(1);
}
- // when loading from fullpath m_late_battery_enable can be TRUE and in that case
+ // when loading from fullpath m_late_battery_enable can be true and in that case
// we attempt to load a battery because the game might have it!
if (m_cart->get_ram_size() && (m_cart->get_has_battery() || m_cart->get_late_battery()))
battery_load(m_cart->get_ram_base(), m_cart->get_ram_size(), 0x00);
diff --git a/src/devices/bus/sega8/sega8_slot.h b/src/devices/bus/sega8/sega8_slot.h
index 408f0aa9d87..85ab4a2cb96 100644
--- a/src/devices/bus/sega8/sega8_slot.h
+++ b/src/devices/bus/sega8/sega8_slot.h
@@ -179,42 +179,42 @@ public:
#define MCFG_SG1000_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
MCFG_DEVICE_ADD(_tag, SEGA8_CART_SLOT, 0) \
MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
- static_cast<sega8_cart_slot_device *>(device)->set_mandatory(TRUE); \
+ static_cast<sega8_cart_slot_device *>(device)->set_mandatory(true); \
static_cast<sega8_cart_slot_device *>(device)->set_intf("sg1000_cart"); \
static_cast<sega8_cart_slot_device *>(device)->set_ext("bin,sg");
#define MCFG_OMV_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
MCFG_DEVICE_ADD(_tag, SEGA8_CART_SLOT, 0) \
MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
- static_cast<sega8_cart_slot_device *>(device)->set_mandatory(FALSE); \
+ static_cast<sega8_cart_slot_device *>(device)->set_mandatory(false); \
static_cast<sega8_cart_slot_device *>(device)->set_intf("sg1000_cart"); \
static_cast<sega8_cart_slot_device *>(device)->set_ext("bin,sg");
#define MCFG_SC3000_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
MCFG_DEVICE_ADD(_tag, SEGA8_CART_SLOT, 0) \
MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
- static_cast<sega8_cart_slot_device *>(device)->set_mandatory(TRUE); \
+ static_cast<sega8_cart_slot_device *>(device)->set_mandatory(true); \
static_cast<sega8_cart_slot_device *>(device)->set_intf("sg1000_cart"); \
static_cast<sega8_cart_slot_device *>(device)->set_ext("bin,sg,sc");
#define MCFG_SG1000MK3_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
MCFG_DEVICE_ADD(_tag, SEGA8_CART_SLOT, 0) \
MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
- static_cast<sega8_cart_slot_device *>(device)->set_mandatory(FALSE); \
+ static_cast<sega8_cart_slot_device *>(device)->set_mandatory(false); \
static_cast<sega8_cart_slot_device *>(device)->set_intf("sms_cart,sg1000_cart"); \
static_cast<sega8_cart_slot_device *>(device)->set_ext("bin,sms,sg");
#define MCFG_SMS_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
MCFG_DEVICE_ADD(_tag, SEGA8_CART_SLOT, 0) \
MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
- static_cast<sega8_cart_slot_device *>(device)->set_mandatory(FALSE); \
+ static_cast<sega8_cart_slot_device *>(device)->set_mandatory(false); \
static_cast<sega8_cart_slot_device *>(device)->set_intf("sms_cart"); \
static_cast<sega8_cart_slot_device *>(device)->set_ext("bin,sms");
#define MCFG_GG_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
MCFG_DEVICE_ADD(_tag, SEGA8_CART_SLOT, 0) \
MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
- static_cast<sega8_cart_slot_device *>(device)->set_mandatory(TRUE); \
+ static_cast<sega8_cart_slot_device *>(device)->set_mandatory(true); \
static_cast<sega8_cart_slot_device *>(device)->set_intf("gamegear_cart"); \
static_cast<sega8_cart_slot_device *>(device)->set_ext("bin,gg");
@@ -223,7 +223,7 @@ public:
#define MCFG_SMS_CARD_ADD(_tag,_slot_intf,_def_slot) \
MCFG_DEVICE_ADD(_tag, SEGA8_CARD_SLOT, 0) \
MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
- static_cast<sega8_card_slot_device *>(device)->set_mandatory(FALSE); \
+ static_cast<sega8_card_slot_device *>(device)->set_mandatory(false); \
static_cast<sega8_card_slot_device *>(device)->set_intf("sms_card"); \
static_cast<sega8_card_slot_device *>(device)->set_ext("bin");
#define MCFG_SG1000_CARD_ADD(_tag,_slot_intf,_def_slot) \
diff --git a/src/devices/bus/sms_ctrl/lphaser.cpp b/src/devices/bus/sms_ctrl/lphaser.cpp
index 3ba680032dc..de7e0bafd79 100644
--- a/src/devices/bus/sms_ctrl/lphaser.cpp
+++ b/src/devices/bus/sms_ctrl/lphaser.cpp
@@ -298,6 +298,6 @@ void sms_light_phaser_device::device_timer(emu_timer &timer, device_timer_id id,
sensor_check();
break;
default:
- assert_always(FALSE, "Unknown id in sms_light_phaser_device::device_timer");
+ assert_always(false, "Unknown id in sms_light_phaser_device::device_timer");
}
}
diff --git a/src/devices/bus/sms_ctrl/sports.cpp b/src/devices/bus/sms_ctrl/sports.cpp
index 5cd92b4e565..b98861a4fa0 100644
--- a/src/devices/bus/sms_ctrl/sports.cpp
+++ b/src/devices/bus/sms_ctrl/sports.cpp
@@ -71,7 +71,7 @@ void sms_sports_pad_device::device_timer(emu_timer &timer, device_timer_id id, i
break;
default:
- assert_always(FALSE, "Unknown id in sms_sports_pad_device::device_timer");
+ assert_always(false, "Unknown id in sms_sports_pad_device::device_timer");
}
}
diff --git a/src/devices/bus/snes/spc7110.cpp b/src/devices/bus/snes/spc7110.cpp
index 03cea5805e0..1a611146366 100644
--- a/src/devices/bus/snes/spc7110.cpp
+++ b/src/devices/bus/snes/spc7110.cpp
@@ -972,14 +972,14 @@ void sns_rom_spc7110_device::spc7110_update_time(uint8_t offset)
machine().current_datetime(curtime);
int64_t diff = curtime.time - m_rtc_basetime.time - offset;
// printf("diff %llx\n", diff);
- bool update = TRUE;
+ bool update = true;
// TEST: can we go beyond 24hrs of rounding?!? I doubt it will ever go beyond 3600, but I could be wrong...
assert(diff < 86400);
/* do not update if CR0 or CR2 timer disable flags are set */
if ((m_rtc_ram[13] & 0x01) || (m_rtc_ram[15] & 0x03))
- update = FALSE;
+ update = false;
if (update && diff > 0)
{
@@ -1021,11 +1021,11 @@ void sns_rom_spc7110_device::spc7110_update_time(uint8_t offset)
// check for feb 29th
if (days == 28)
{
- bool leap = FALSE;
+ bool leap = false;
if ((year % 4) == 0)
{
if(year % 100 || !(year % 400))
- leap = TRUE;
+ leap = true;
}
if (leap)
days++;
diff --git a/src/devices/bus/snes/upd.cpp b/src/devices/bus/snes/upd.cpp
index f87e41194fa..25cd416e8b1 100644
--- a/src/devices/bus/snes/upd.cpp
+++ b/src/devices/bus/snes/upd.cpp
@@ -240,7 +240,7 @@ WRITE8_MEMBER( sns_rom21_necdsp_device::chip_write )
READ8_MEMBER( sns_rom_setadsp_device::chip_read )
{
if (offset >= 0x600000 && offset < 0x680000 && (offset & 0xffff) < 0x4000)
- m_upd96050->snesdsp_read((offset & 0x01) ? FALSE : TRUE);
+ m_upd96050->snesdsp_read((offset & 0x01) ? false : true);
if (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x8000)
{
@@ -260,7 +260,7 @@ WRITE8_MEMBER( sns_rom_setadsp_device::chip_write )
{
if (offset >= 0x600000 && offset < 0x680000 && (offset & 0xffff) < 0x4000)
{
- m_upd96050->snesdsp_write((offset & 0x01) ? FALSE : TRUE, data);
+ m_upd96050->snesdsp_write((offset & 0x01) ? false : true, data);
return;
}
diff --git a/src/devices/bus/ti99_peb/bwg.h b/src/devices/bus/ti99_peb/bwg.h
index 47955637ea7..cdebe19bad0 100644
--- a/src/devices/bus/ti99_peb/bwg.h
+++ b/src/devices/bus/ti99_peb/bwg.h
@@ -94,7 +94,7 @@ private:
// Indicates whether the clock is mapped into the address space.
bool m_rtc_enabled;
- // Signal motor_on. When TRUE, makes all drives turning.
+ // Signal motor_on. When true, makes all drives turning.
int m_MOTOR_ON;
// Needed for triggering the motor monoflop
diff --git a/src/devices/bus/ti99_peb/hfdc.h b/src/devices/bus/ti99_peb/hfdc.h
index 38a95c787a1..5824bd5471a 100644
--- a/src/devices/bus/ti99_peb/hfdc.h
+++ b/src/devices/bus/ti99_peb/hfdc.h
@@ -170,7 +170,7 @@ private:
// Needed for triggering the motor monoflop
uint8_t m_lastval;
- // Signal motor_on. When TRUE, makes all drives turning.
+ // Signal motor_on. When true, makes all drives turning.
int m_MOTOR_ON;
// Calculates the index from the bit
diff --git a/src/devices/bus/ti99_peb/peribox.h b/src/devices/bus/ti99_peb/peribox.h
index 51aa007497c..7d9b11910e9 100644
--- a/src/devices/bus/ti99_peb/peribox.h
+++ b/src/devices/bus/ti99_peb/peribox.h
@@ -231,10 +231,10 @@ protected:
int m_senila;
int m_senilb;
- // When TRUE, card is accessible. Indicated by a LED.
+ // When true, card is accessible. Indicated by a LED.
bool m_selected;
- // When TRUE, GenMod is selected. Modified by peribox_slot_device.
+ // When true, GenMod is selected. Modified by peribox_slot_device.
bool m_genmod;
// CRU base. Used to configure the address by which a card is selected.
diff --git a/src/devices/bus/ti99_peb/spchsyn.cpp b/src/devices/bus/ti99_peb/spchsyn.cpp
index 9a3ad050c75..1ce0f3faeb8 100644
--- a/src/devices/bus/ti99_peb/spchsyn.cpp
+++ b/src/devices/bus/ti99_peb/spchsyn.cpp
@@ -104,7 +104,7 @@ SETADDRESS_DBIN_MEMBER( ti_speech_synthesizer_device::setaddress_dbin )
WRITE_LINE_MEMBER( ti_speech_synthesizer_device::speech_ready )
{
- // The TMS5200 implementation uses TRUE/FALSE, not ASSERT/CLEAR semantics
+ // The TMS5200 implementation uses true/false, not ASSERT/CLEAR semantics
// and we have to adapt a /READY to a READY line.
// The real synthesizer board uses a transistor for that purpose.
m_slot->set_ready((state==0)? ASSERT_LINE : CLEAR_LINE);
diff --git a/src/devices/bus/ti99_peb/ti_fdc.h b/src/devices/bus/ti99_peb/ti_fdc.h
index aeba6d6fdc2..2eb76edba53 100644
--- a/src/devices/bus/ti99_peb/ti_fdc.h
+++ b/src/devices/bus/ti99_peb/ti_fdc.h
@@ -68,13 +68,13 @@ private:
// Needed for triggering the motor monoflop
uint8_t m_lastval;
- // Signal DVENA. When TRUE, makes some drive turning.
+ // Signal DVENA. When true, makes some drive turning.
int m_DVENA;
// Set when address is in card area
bool m_inDsrArea;
- // When TRUE the CPU is halted while DRQ/IRQ are true.
+ // When true the CPU is halted while DRQ/IRQ are true.
bool m_WAITena;
// WD chip selected
diff --git a/src/devices/bus/ti99x/990_dk.cpp b/src/devices/bus/ti99x/990_dk.cpp
index f36e93a963e..a68253adff5 100644
--- a/src/devices/bus/ti99x/990_dk.cpp
+++ b/src/devices/bus/ti99x/990_dk.cpp
@@ -100,7 +100,7 @@ void fd800_machine_init(void (*interrupt_callback)(running_machine &machine, int
cylinder_id: cylinder ID read
sector_id: sector ID read
- Return TRUE if an ID was found
+ Return true if an ID was found
*/
int fd800_legacy_device::read_id(int unit, int head, int *cylinder_id, int *sector_id)
{
@@ -117,11 +117,11 @@ int fd800_legacy_device::read_id(int unit, int head, int *cylinder_id, int *sect
*cylinder_id = id.C;
if (sector_id)
*sector_id = id.R;
- return TRUE;
+ return true;
}
}*/
- return FALSE;
+ return false;
}
/*
@@ -132,7 +132,7 @@ int fd800_legacy_device::read_id(int unit, int head, int *cylinder_id, int *sect
sector: sector ID to search
data_id: data ID to be used when calling sector read/write functions
- Return TRUE if the given sector ID was found
+ Return true if the given sector ID was found
*/
int fd800_legacy_device::find_sector(int unit, int head, int sector, int *data_id)
{
@@ -151,12 +151,12 @@ int fd800_legacy_device::find_sector(int unit, int head, int sector, int *data_i
*data_id = id.data_id;
// get ddam status
// w->ddam = id.flags & ID_FLAG_DELETED_DATA;
- return TRUE;
+ return true;
}
}
}
*/
- return FALSE;
+ return false;
}
/*
@@ -166,7 +166,7 @@ int fd800_legacy_device::find_sector(int unit, int head, int sector, int *data_i
cylinder: track to seek for
head: head for which the seek is performed
- Return FALSE if the seek was successful
+ Return false if the seek was successful
*/
int fd800_legacy_device::do_seek(int unit, int cylinder, int head)
{
@@ -175,13 +175,13 @@ int fd800_legacy_device::do_seek(int unit, int cylinder, int head)
if (cylinder > 76)
{
m_stat_reg |= status_invalid_cmd;
- return TRUE;
+ return true;
}
if (m_drv[unit].img == nullptr || !m_drv[unit].img->exists())
{
m_stat_reg |= status_drv_not_ready;
- return TRUE;
+ return true;
}
if (m_drv[unit].log_cylinder[head] == -1)
@@ -189,14 +189,14 @@ int fd800_legacy_device::do_seek(int unit, int cylinder, int head)
if (!read_id(unit, head, &m_drv[unit].log_cylinder[head], nullptr))
{
m_stat_reg |= status_ID_not_found;
- return TRUE;
+ return true;
}
}
if (m_drv[unit].log_cylinder[head] == cylinder)
{
- return FALSE;
+ return false;
}
for (retries=0; retries<10; retries++)
{
@@ -209,19 +209,19 @@ int fd800_legacy_device::do_seek(int unit, int cylinder, int head)
{
m_drv[unit].log_cylinder[head] = -1;
m_stat_reg |= status_ID_not_found;
- return TRUE;
+ return true;
}
if (m_drv[unit].log_cylinder[head] == cylinder)
{
- return FALSE;
+ return false;
}
}
m_stat_reg |= status_seek_err;
*/
- return TRUE;
+ return true;
}
/*
@@ -229,7 +229,7 @@ int fd800_legacy_device::do_seek(int unit, int cylinder, int head)
unit: floppy drive index
- Return FALSE if the restore was successful
+ Return false if the restore was successful
*/
int fd800_legacy_device::do_restore(int unit)
{
@@ -239,7 +239,7 @@ int fd800_legacy_device::do_restore(int unit)
if (!m_drv[unit].img->exists())
{
m_stat_reg |= status_drv_not_ready;
- return TRUE;
+ return true;
}
diff --git a/src/devices/bus/ti99x/990_hd.h b/src/devices/bus/ti99x/990_hd.h
index 8c1435d0eb5..aef9de11591 100644
--- a/src/devices/bus/ti99x/990_hd.h
+++ b/src/devices/bus/ti99x/990_hd.h
@@ -58,8 +58,8 @@ private:
device_image_interface *img; /* image descriptor */
format_t format;
hard_disk_file *hd_handle; /* mame hard disk descriptor - only if format == format_mame */
- unsigned int wp : 1; /* TRUE if disk is write-protected */
- unsigned int unsafe : 1; /* TRUE when a disk has just been connected */
+ unsigned int wp : 1; /* true if disk is write-protected */
+ unsigned int unsafe : 1; /* true when a disk has just been connected */
/* disk geometry */
unsigned int cylinders, heads, sectors_per_track, bytes_per_sector;
diff --git a/src/devices/bus/ti99x/990_tap.h b/src/devices/bus/ti99x/990_tap.h
index b4599837aa5..ca3f78a3038 100644
--- a/src/devices/bus/ti99x/990_tap.h
+++ b/src/devices/bus/ti99x/990_tap.h
@@ -10,9 +10,9 @@ extern const device_type TI990_TAPE_CTRL;
struct tape_unit_t
{
device_image_interface *img; // image descriptor
- bool bot; // TRUE if we are at the beginning of tape
- bool eot; // TRUE if we are at the end of tape
- bool wp; // TRUE if tape is write-protected
+ bool bot; // true if we are at the beginning of tape
+ bool eot; // true if we are at the end of tape
+ bool wp; // true if tape is write-protected
};
class tap_990_device : public device_t
diff --git a/src/devices/bus/ti99x/998board.cpp b/src/devices/bus/ti99x/998board.cpp
index 074336f3441..fc16e9f23cb 100644
--- a/src/devices/bus/ti99x/998board.cpp
+++ b/src/devices/bus/ti99x/998board.cpp
@@ -197,8 +197,8 @@ SETOFFSET_MEMBER( mainboard8_device::setoffset )
select_groms();
// Speech select lines will always be asserted/cleared as soon as the address is available
- m_speech->wsq_w((m_vaquerro->spwt_out() == ASSERT_LINE)? FALSE : TRUE);
- m_speech->rsq_w((m_vaquerro->sprd_out() == ASSERT_LINE)? FALSE : TRUE);
+ m_speech->wsq_w((m_vaquerro->spwt_out() == ASSERT_LINE)? false : true);
+ m_speech->rsq_w((m_vaquerro->sprd_out() == ASSERT_LINE)? false : true);
// If it is a logical space address, tell the mapper to stay inactive
line_state lasreq = (line_state)m_vaquerro->lascsq_out();
@@ -746,8 +746,8 @@ WRITE_LINE_MEMBER( mainboard8_device::sound_ready )
WRITE_LINE_MEMBER( mainboard8_device::speech_ready )
{
- // The TMS5200 implementation uses TRUE/FALSE, not ASSERT/CLEAR semantics
- m_speech_ready = (state==FALSE)? ASSERT_LINE : CLEAR_LINE;
+ // The TMS5200 implementation uses true/false, not ASSERT/CLEAR semantics
+ m_speech_ready = (state==false)? ASSERT_LINE : CLEAR_LINE;
}
WRITE_LINE_MEMBER( mainboard8_device::pbox_ready )
diff --git a/src/devices/bus/ti99x/handset.cpp b/src/devices/bus/ti99x/handset.cpp
index c4a3f86630c..ec40b68005c 100644
--- a/src/devices/bus/ti99x/handset.cpp
+++ b/src/devices/bus/ti99x/handset.cpp
@@ -148,7 +148,7 @@ void ti99_handset_device::post_message(int message)
poll_keyboard()
Poll the current state of one given handset keypad.
num: number of the keypad to poll (0-3)
- Returns TRUE if the handset state has changed and a message was posted.
+ Returns true if the handset state has changed and a message was posted.
*/
bool ti99_handset_device::poll_keyboard(int num)
{
@@ -219,7 +219,7 @@ bool ti99_handset_device::poll_keyboard(int num)
Poll the current state of one given handset joystick.
num: number of the joystick to poll (0-3)
- Returns TRUE if the handset state has changed and a message was posted.
+ Returns true if the handset state has changed and a message was posted.
*/
bool ti99_handset_device::poll_joystick(int num)
{
diff --git a/src/devices/bus/vcs/vcs_slot.cpp b/src/devices/bus/vcs/vcs_slot.cpp
index 8ae6783e2dd..ce28ddcbbfb 100644
--- a/src/devices/bus/vcs/vcs_slot.cpp
+++ b/src/devices/bus/vcs/vcs_slot.cpp
@@ -222,7 +222,7 @@ image_init_result vcs_cart_slot_device::call_load()
if (software_entry() != nullptr)
{
const char *pcb_name;
- bool has_ram = get_software_region("ram") ? TRUE : FALSE;
+ bool has_ram = get_software_region("ram") ? true : false;
memcpy(ROM, get_software_region("rom"), len);
if ((pcb_name = get_feature("slot")) != nullptr)
diff --git a/src/devices/cpu/apexc/apexc.cpp b/src/devices/cpu/apexc/apexc.cpp
index 3b490b2339d..e0df11d902a 100644
--- a/src/devices/cpu/apexc/apexc.cpp
+++ b/src/devices/cpu/apexc/apexc.cpp
@@ -524,7 +524,7 @@ void apexc_cpu_device::execute()
case 0:
/* stop */
- m_running = FALSE;
+ m_running = false;
/* BTW, I don't know whether stop loads y into ml or not, and whether
subsequent fetch is done */
@@ -835,7 +835,7 @@ void apexc_cpu_device::device_reset()
/* next two lines are just the product of my bold fantasy */
m_cr = 0; /* first instruction executed will be a stop */
- m_running = TRUE; /* this causes the CPU to load the instruction at 0/0,
+ m_running = true; /* this causes the CPU to load the instruction at 0/0,
which enables easy booting (just press run on the panel) */
m_a = 0;
m_r = 0;
diff --git a/src/devices/cpu/arm7/arm7.cpp b/src/devices/cpu/arm7/arm7.cpp
index 5a3dd15be17..b855eb04d57 100644
--- a/src/devices/cpu/arm7/arm7.cpp
+++ b/src/devices/cpu/arm7/arm7.cpp
@@ -353,7 +353,7 @@ bool arm7_cpu_device::arm7_tlb_translate(offs_t &addr, int flags)
LOG( ( "ARM7: Translation fault on unmapped virtual address, PC = %08x, vaddr = %08x\n", m_r[eR15], addr ) );
m_pendingAbtP = true;
}
- return FALSE;
+ return false;
}
else
{
@@ -383,7 +383,7 @@ bool arm7_cpu_device::arm7_tlb_translate(offs_t &addr, int flags)
LOG( ( "ARM7: Translation fault on unmapped virtual address, vaddr = %08x, PC %08X\n", addr, m_r[eR15] ) );
m_pendingAbtP = true;
}
- return FALSE;
+ return false;
case COPRO_TLB_LARGE_PAGE:
// Large page descriptor
addr = ( desc_lvl2 & COPRO_TLB_LARGE_PAGE_MASK ) | ( addr & ~COPRO_TLB_LARGE_PAGE_MASK );
@@ -578,7 +578,7 @@ void arm7_cpu_device::device_reset()
SwitchMode(eARM7_MODE_SVC);
m_r[eR15] = 0;
- m_impstate.cache_dirty = TRUE;
+ m_impstate.cache_dirty = true;
}
diff --git a/src/devices/cpu/arm7/arm7.h b/src/devices/cpu/arm7/arm7.h
index 94b0f9cff4e..8309b3b7dee 100644
--- a/src/devices/cpu/arm7/arm7.h
+++ b/src/devices/cpu/arm7/arm7.h
@@ -279,7 +279,7 @@ protected:
{
offs_t start; /* start of the RAM block */
offs_t end; /* end of the RAM block */
- uint8_t readonly; /* TRUE if read-only */
+ bool readonly; /* true if read-only */
void * base; /* base in memory where the RAM lives */
};
@@ -486,7 +486,7 @@ protected:
bool drcarm7ops_cd(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t op);
bool drcarm7ops_e(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t op);
bool drcarm7ops_f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t op);
- int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
};
diff --git a/src/devices/cpu/arm7/arm7drc.hxx b/src/devices/cpu/arm7/arm7drc.hxx
index ae7255f6714..2dc32cd68c2 100644
--- a/src/devices/cpu/arm7/arm7drc.hxx
+++ b/src/devices/cpu/arm7/arm7drc.hxx
@@ -188,7 +188,7 @@ void arm7_cpu_device::arm7_drc_init()
}
/* mark the cache dirty so it is updated on next execute */
- m_impstate.cache_dirty = TRUE;
+ m_impstate.cache_dirty = true;
}
@@ -205,7 +205,7 @@ void arm7_cpu_device::execute_run_drc()
/* reset the cache if dirty */
if (m_impstate.cache_dirty)
code_flush_cache();
- m_impstate.cache_dirty = FALSE;
+ m_impstate.cache_dirty = false;
/* execute */
do
@@ -307,12 +307,12 @@ void arm7_cpu_device::code_flush_cache()
//static_generate_tlb_mismatch();
/* add subroutines for memory accesses */
- static_generate_memory_accessor(1, FALSE, FALSE, "read8", &m_impstate.read8);
- static_generate_memory_accessor(1, TRUE, FALSE, "write8", &m_impstate.write8);
- static_generate_memory_accessor(2, FALSE, FALSE, "read16", &m_impstate.read16);
- static_generate_memory_accessor(2, TRUE, FALSE, "write16", &m_impstate.write16);
- static_generate_memory_accessor(4, FALSE, FALSE, "read32", &m_impstate.read32);
- static_generate_memory_accessor(4, TRUE, FALSE, "write32", &m_impstate.write32);
+ static_generate_memory_accessor(1, false, false, "read8", &m_impstate.read8);
+ static_generate_memory_accessor(1, true, false, "write8", &m_impstate.write8);
+ static_generate_memory_accessor(2, false, false, "read16", &m_impstate.read16);
+ static_generate_memory_accessor(2, true, false, "write16", &m_impstate.write16);
+ static_generate_memory_accessor(4, false, false, "read32", &m_impstate.read32);
+ static_generate_memory_accessor(4, true, false, "write32", &m_impstate.write32);
}
catch (drcuml_block::abort_compilation &)
{
@@ -331,7 +331,7 @@ void arm7_cpu_device::code_compile_block(uint8_t mode, offs_t pc)
drcuml_state *drcuml = m_impstate.drcuml;
compiler_state compiler = { 0 };
const opcode_desc *seqlast;
- int override = FALSE;
+ bool override = false;
g_profiler.start(PROFILER_DRC_COMPILE);
@@ -374,7 +374,7 @@ void arm7_cpu_device::code_compile_block(uint8_t mode, offs_t pc)
/* are recompiling due to being out of sync and allow future overrides */
else if (seqhead == desclist)
{
- override = TRUE;
+ override = true;
UML_HASH(block, mode, seqhead->pc); // hash mode,pc
}
@@ -1169,7 +1169,7 @@ void arm7_cpu_device::generate_update_cycles(drcuml_block *block, compiler_state
{
uml::code_label skip;
- compiler->checkints = FALSE;
+ compiler->checkints = false;
UML_CALLH(block, *m_impstate.check_irq);
}
@@ -1685,7 +1685,7 @@ bool arm7_cpu_device::drcarm7ops_f(drcuml_block *block, compiler_state *compiler
opcode
-------------------------------------------------*/
-int arm7_cpu_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool arm7_cpu_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
//int in_delay_slot = ((desc->flags & OPFLAG_IN_DELAY_SLOT) != 0);
uint32_t op = desc->opptr.l[0];
@@ -1711,7 +1711,7 @@ int arm7_cpu_device::generate_opcode(drcuml_block *block, compiler_state *compil
if (T_IS_SET(GET_CPSR))
{
//UML_CALLH(block, *m_impstate.drcthumb[(op & 0xffc0) >> 6]); // callh drcthumb[op] // TODO FIXME
- return TRUE;
+ return true;
}
switch (op >> INSN_COND_SHIFT)
@@ -1825,10 +1825,10 @@ int arm7_cpu_device::generate_opcode(drcuml_block *block, compiler_state *compil
/* ----- sub-groups ----- */
case 0x00: /* SPECIAL - MIPS I */
- return TRUE;
+ return true;
// TODO: FINISH ME
}
- return FALSE;
+ return false;
}
diff --git a/src/devices/cpu/ccpu/ccpu.cpp b/src/devices/cpu/ccpu/ccpu.cpp
index 419dcd23061..cc40e4edcd4 100644
--- a/src/devices/cpu/ccpu/ccpu.cpp
+++ b/src/devices/cpu/ccpu/ccpu.cpp
@@ -83,7 +83,7 @@ READ8_MEMBER( ccpu_cpu_device::read_jmi )
void ccpu_cpu_device::wdt_timer_trigger()
{
- m_waiting = FALSE;
+ m_waiting = false;
m_watchdog++;
if (m_watchdog >= 3)
m_PC = 0;
@@ -180,7 +180,7 @@ void ccpu_cpu_device::device_reset()
m_miflag = m_nextmiflag = m_nextnextmiflag = 0;
m_drflag = 0;
- m_waiting = FALSE;
+ m_waiting = false;
m_watchdog = 0;
}
@@ -568,7 +568,7 @@ void ccpu_cpu_device::execute_run()
/* FRM */
case 0xe5:
case 0xf5:
- m_waiting = TRUE;
+ m_waiting = true;
NEXT_ACC_A;
m_icount = -1;
diff --git a/src/devices/cpu/drcbec.cpp b/src/devices/cpu/drcbec.cpp
index 6ad8085afd6..d8e093f126c 100644
--- a/src/devices/cpu/drcbec.cpp
+++ b/src/devices/cpu/drcbec.cpp
@@ -1581,19 +1581,19 @@ int drcbe_c::execute(code_handle &entry)
break;
case MAKE_OPCODE_SHORT(OP_MULU, 8, 0): // DMULU dst,edst,src1,src2[,f]
- dmulu(*inst[0].puint64, *inst[1].puint64, DPARAM2, DPARAM3, FALSE);
+ dmulu(*inst[0].puint64, *inst[1].puint64, DPARAM2, DPARAM3, false);
break;
case MAKE_OPCODE_SHORT(OP_MULU, 8, 1):
- flags = dmulu(*inst[0].puint64, *inst[1].puint64, DPARAM2, DPARAM3, TRUE);
+ flags = dmulu(*inst[0].puint64, *inst[1].puint64, DPARAM2, DPARAM3, true);
break;
case MAKE_OPCODE_SHORT(OP_MULS, 8, 0): // DMULS dst,edst,src1,src2[,f]
- dmuls(*inst[0].puint64, *inst[1].puint64, DPARAM2, DPARAM3, FALSE);
+ dmuls(*inst[0].puint64, *inst[1].puint64, DPARAM2, DPARAM3, false);
break;
case MAKE_OPCODE_SHORT(OP_MULS, 8, 1):
- flags = dmuls(*inst[0].puint64, *inst[1].puint64, DPARAM2, DPARAM3, TRUE);
+ flags = dmuls(*inst[0].puint64, *inst[1].puint64, DPARAM2, DPARAM3, true);
break;
case MAKE_OPCODE_SHORT(OP_DIVU, 8, 0): // DDIVU dst,edst,src1,src2[,f]
@@ -2220,10 +2220,10 @@ void drcbe_c::fixup_label(void *parameter, drccodeptr labelcodeptr)
// dmulu - perform a double-wide unsigned multiply
//-------------------------------------------------
-int drcbe_c::dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src2, int flags)
+int drcbe_c::dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src2, bool flags)
{
// shortcut if we don't care about the high bits or the flags
- if (&dstlo == &dsthi && flags == 0)
+ if (&dstlo == &dsthi && flags == false)
{
dstlo = src1 * src2;
return 0;
@@ -2264,10 +2264,10 @@ int drcbe_c::dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src
// dmuls - perform a double-wide signed multiply
//-------------------------------------------------
-int drcbe_c::dmuls(uint64_t &dstlo, uint64_t &dsthi, int64_t src1, int64_t src2, int flags)
+int drcbe_c::dmuls(uint64_t &dstlo, uint64_t &dsthi, int64_t src1, int64_t src2, bool flags)
{
// shortcut if we don't care about the high bits or the flags
- if (&dstlo == &dsthi && flags == 0)
+ if (&dstlo == &dsthi && flags == false)
{
dstlo = src1 * src2;
return 0;
diff --git a/src/devices/cpu/drcbec.h b/src/devices/cpu/drcbec.h
index d92fc7672e9..d9c28612fea 100644
--- a/src/devices/cpu/drcbec.h
+++ b/src/devices/cpu/drcbec.h
@@ -42,8 +42,8 @@ private:
// helpers
void output_parameter(drcbec_instruction **dstptr, void **immedptr, int size, const uml::parameter &param);
void fixup_label(void *parameter, drccodeptr labelcodeptr);
- int dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src2, int flags);
- int dmuls(uint64_t &dstlo, uint64_t &dsthi, int64_t src1, int64_t src2, int flags);
+ int dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src2, bool flags);
+ int dmuls(uint64_t &dstlo, uint64_t &dsthi, int64_t src1, int64_t src2, bool flags);
uint32_t tzcount32(uint32_t value);
uint64_t tzcount64(uint64_t value);
diff --git a/src/devices/cpu/drcbex86.cpp b/src/devices/cpu/drcbex86.cpp
index 53dbe1eb347..7cc67502093 100644
--- a/src/devices/cpu/drcbex86.cpp
+++ b/src/devices/cpu/drcbex86.cpp
@@ -6615,10 +6615,10 @@ void drcbe_x86::op_icopyf(x86code *&dst, const instruction &inst)
// dmulu - perform a double-wide unsigned multiply
//-------------------------------------------------
-int drcbe_x86::dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src2, int flags)
+int drcbe_x86::dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src2, bool flags)
{
// shortcut if we don't care about the high bits or the flags
- if (&dstlo == &dsthi && flags == 0)
+ if (&dstlo == &dsthi && flags == false)
{
dstlo = src1 * src2;
return 0;
@@ -6659,13 +6659,13 @@ int drcbe_x86::dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t s
// dmuls - perform a double-wide signed multiply
//-------------------------------------------------
-int drcbe_x86::dmuls(uint64_t &dstlo, uint64_t &dsthi, int64_t src1, int64_t src2, int flags)
+int drcbe_x86::dmuls(uint64_t &dstlo, uint64_t &dsthi, int64_t src1, int64_t src2, bool flags)
{
uint64_t lo, hi, prevlo;
uint64_t a, b, temp;
// shortcut if we don't care about the high bits or the flags
- if (&dstlo == &dsthi && flags == 0)
+ if (&dstlo == &dsthi && flags == false)
{
dstlo = src1 * src2;
return 0;
diff --git a/src/devices/cpu/drcbex86.h b/src/devices/cpu/drcbex86.h
index b7baaf8c9a7..ef1bf57f010 100644
--- a/src/devices/cpu/drcbex86.h
+++ b/src/devices/cpu/drcbex86.h
@@ -286,8 +286,8 @@ private:
void emit_fstp_p(x86code *&dst, int size, const be_parameter &param);
// callback helpers
- static int dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src2, int flags);
- static int dmuls(uint64_t &dstlo, uint64_t &dsthi, int64_t src1, int64_t src2, int flags);
+ static int dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src2, bool flags);
+ static int dmuls(uint64_t &dstlo, uint64_t &dsthi, int64_t src1, int64_t src2, bool flags);
static int ddivu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src2);
static int ddivs(uint64_t &dstlo, uint64_t &dsthi, int64_t src1, int64_t src2);
diff --git a/src/devices/cpu/drcuml.cpp b/src/devices/cpu/drcuml.cpp
index 252efa332e5..b017b6a64c8 100644
--- a/src/devices/cpu/drcuml.cpp
+++ b/src/devices/cpu/drcuml.cpp
@@ -470,7 +470,7 @@ void drcuml_block::disassemble()
{
m_drcuml.log_printf("\t%-50.50s; %s\n", dasm.c_str(), get_comment_text(m_inst[firstcomment], comment));
firstcomment++;
- flushcomments = TRUE;
+ flushcomments = true;
}
else
m_drcuml.log_printf("\t%s\n", dasm.c_str());
@@ -766,7 +766,7 @@ static void bevalidate_iterate_over_params(drcuml_state *drcuml, code_handle **h
// iterate over possibilities
for (pindex = 0; pindex < pcount; pindex++)
{
- int skip = FALSE;
+ bool skip = false;
int pscannum;
// for param 0, print a dot
@@ -779,7 +779,7 @@ static void bevalidate_iterate_over_params(drcuml_state *drcuml, code_handle **h
// loop over all parameters we've done before; if the parameter is a source and matches us, skip this case
for (pscannum = 0; pscannum < pnum; pscannum++)
if ((opinfo->param[pscannum].output & PIO_IN) && ptype == paramlist[pscannum].type && pindex == paramlist[pscannum].value)
- skip = TRUE;
+ skip = true;
// can't duplicate multiple dest parameters
if (opinfo->param[pnum].output & PIO_OUT)
@@ -787,7 +787,7 @@ static void bevalidate_iterate_over_params(drcuml_state *drcuml, code_handle **h
// loop over all parameters we've done before; if the parameter is a source and matches us, skip this case
for (pscannum = 0; pscannum < pnum; pscannum++)
if ((opinfo->param[pscannum].output & PIO_OUT) && ptype == paramlist[pscannum].type && pindex == paramlist[pscannum].value)
- skip = TRUE;
+ skip = true;
// iterate over the next parameter in line
if (!skip)
diff --git a/src/devices/cpu/dsp56k/dsp56k.cpp b/src/devices/cpu/dsp56k/dsp56k.cpp
index 29492ae9c79..1442aa8254d 100644
--- a/src/devices/cpu/dsp56k/dsp56k.cpp
+++ b/src/devices/cpu/dsp56k/dsp56k.cpp
@@ -147,11 +147,11 @@ void dsp56k_device::execute_set_input(int irqline, int state)
logerror("DSP56k IRQA is set to fire on the \"Negative Edge\".\n");
if (state != CLEAR_LINE)
- m_dsp56k_core.modA_state = TRUE;
+ m_dsp56k_core.modA_state = true;
else
- m_dsp56k_core.modA_state = FALSE;
+ m_dsp56k_core.modA_state = false;
- if (m_dsp56k_core.reset_state != TRUE)
+ if (m_dsp56k_core.reset_state != true)
dsp56k_add_pending_interrupt(&m_dsp56k_core, "IRQA");
break;
@@ -161,33 +161,33 @@ void dsp56k_device::execute_set_input(int irqline, int state)
logerror("DSP56k IRQB is set to fire on the \"Negative Edge\".\n");
if (state != CLEAR_LINE)
- m_dsp56k_core.modB_state = TRUE;
+ m_dsp56k_core.modB_state = true;
else
- m_dsp56k_core.modB_state = FALSE;
+ m_dsp56k_core.modB_state = false;
- if (m_dsp56k_core.reset_state != TRUE)
+ if (m_dsp56k_core.reset_state != true)
dsp56k_add_pending_interrupt(&m_dsp56k_core, "IRQB");
break;
case DSP56K_IRQ_MODC:
if (state != CLEAR_LINE)
- m_dsp56k_core.modC_state = TRUE;
+ m_dsp56k_core.modC_state = true;
else
- m_dsp56k_core.modC_state = FALSE;
+ m_dsp56k_core.modC_state = false;
// TODO : Set bus mode or whatever
break;
case DSP56K_IRQ_RESET:
if (state != CLEAR_LINE)
- m_dsp56k_core.reset_state = TRUE;
+ m_dsp56k_core.reset_state = true;
else
{
/* If it changes state from asserted to cleared. Call the reset function. */
- if (m_dsp56k_core.reset_state == TRUE)
+ if (m_dsp56k_core.reset_state == true)
device_reset();
- m_dsp56k_core.reset_state = FALSE;
+ m_dsp56k_core.reset_state = false;
}
// dsp56k_add_pending_interrupt("Hardware RESET");
@@ -200,7 +200,7 @@ void dsp56k_device::execute_set_input(int irqline, int state)
/* If the reset line isn't asserted, service interrupts */
// TODO: Is it right to immediately service interrupts?
- //if (cpustate->reset_state != TRUE)
+ //if (cpustate->reset_state != true)
// pcu_service_interrupts();
}
@@ -251,10 +251,10 @@ void dsp56k_device::device_start()
m_dsp56k_core.bootstrap_mode = BOOTSTRAP_OFF;
/* Clear the irq states */
- m_dsp56k_core.modA_state = FALSE;
- m_dsp56k_core.modB_state = FALSE;
- m_dsp56k_core.modC_state = FALSE;
- m_dsp56k_core.reset_state = FALSE;
+ m_dsp56k_core.modA_state = false;
+ m_dsp56k_core.modB_state = false;
+ m_dsp56k_core.modC_state = false;
+ m_dsp56k_core.reset_state = false;
/* save states - dsp56k_core members */
save_item(NAME(m_dsp56k_core.modA_state));
diff --git a/src/devices/cpu/dsp56k/dsp56k.h b/src/devices/cpu/dsp56k/dsp56k.h
index 6d497941d3a..419800a3265 100644
--- a/src/devices/cpu/dsp56k/dsp56k.h
+++ b/src/devices/cpu/dsp56k/dsp56k.h
@@ -170,10 +170,10 @@ struct dsp56k_core
dsp56k_host_interface HI;
// IRQ line states
- uint8_t modA_state;
- uint8_t modB_state;
- uint8_t modC_state;
- uint8_t reset_state;
+ bool modA_state;
+ bool modB_state;
+ bool modC_state;
+ bool reset_state;
// HACK - Bootstrap mode state variable.
uint8_t bootstrap_mode;
diff --git a/src/devices/cpu/h6280/h6280.cpp b/src/devices/cpu/h6280/h6280.cpp
index 469e057c88d..ecb2420e366 100644
--- a/src/devices/cpu/h6280/h6280.cpp
+++ b/src/devices/cpu/h6280/h6280.cpp
@@ -2568,7 +2568,7 @@ bool h6280_device::memory_translate(address_spacenum spacenum, int intention, of
if (spacenum == AS_PROGRAM)
address = translated(address);
- return TRUE;
+ return true;
}
uint8_t h6280_device::io_get_buffer()
diff --git a/src/devices/cpu/i8085/i8085.cpp b/src/devices/cpu/i8085/i8085.cpp
index b28ebab7380..09f4a1375d5 100644
--- a/src/devices/cpu/i8085/i8085.cpp
+++ b/src/devices/cpu/i8085/i8085.cpp
@@ -334,7 +334,7 @@ void i8085a_cpu_device::check_for_interrupts()
m_trap_im_copy = m_IM | 0x80;
/* reset the pending state */
- m_trap_pending = FALSE;
+ m_trap_pending = false;
/* break out of HALT state and call the IRQ ack callback */
break_halt_for_interrupt();
@@ -987,8 +987,8 @@ void i8085a_cpu_device::device_reset()
m_HALT = 0;
m_IM &= ~IM_I75;
m_IM |= IM_M55 | IM_M65 | IM_M75;
- m_after_ei = FALSE;
- m_trap_pending = FALSE;
+ m_after_ei = false;
+ m_trap_pending = false;
m_trap_im_copy = 0;
set_inte(0);
set_sod(0);
@@ -1076,7 +1076,7 @@ void i8085a_cpu_device::execute_set_input(int irqline, int state)
if (irqline == INPUT_LINE_NMI)
{
if (!m_nmi_state && newstate)
- m_trap_pending = TRUE;
+ m_trap_pending = true;
m_nmi_state = newstate;
}
diff --git a/src/devices/cpu/i86/i286.cpp b/src/devices/cpu/i86/i286.cpp
index e6358a2f88b..4872f6f223e 100644
--- a/src/devices/cpu/i86/i286.cpp
+++ b/src/devices/cpu/i86/i286.cpp
@@ -317,7 +317,7 @@ bool i80286_cpu_device::memory_translate(address_spacenum spacenum, int intentio
if(spacenum == AS_PROGRAM)
address &= m_amask;
- return TRUE;
+ return true;
}
void i80286_cpu_device::execute_set_input(int inptnum, int state)
diff --git a/src/devices/cpu/m6800/m6800.cpp b/src/devices/cpu/m6800/m6800.cpp
index 11109fbe59a..4fbdc76c58a 100644
--- a/src/devices/cpu/m6800/m6800.cpp
+++ b/src/devices/cpu/m6800/m6800.cpp
@@ -711,7 +711,7 @@ void m6800_cpu_device::CHECK_IRQ_LINES()
if(m_wai_state & M6800_SLP)
m_wai_state &= ~M6800_SLP;
- m_nmi_pending = FALSE;
+ m_nmi_pending = false;
enter_interrupt("M6800 '%s' take NMI\n",0xfffc);
}
else
@@ -1212,7 +1212,7 @@ void m6800_cpu_device::execute_set_input(int irqline, int state)
{
case INPUT_LINE_NMI:
if (!m_nmi_state && state != CLEAR_LINE)
- m_nmi_pending = TRUE;
+ m_nmi_pending = true;
m_nmi_state = state;
break;
diff --git a/src/devices/cpu/m68000/m68kcpu.cpp b/src/devices/cpu/m68000/m68kcpu.cpp
index 8bacd096a35..63a90d59dbe 100644
--- a/src/devices/cpu/m68000/m68kcpu.cpp
+++ b/src/devices/cpu/m68000/m68kcpu.cpp
@@ -656,7 +656,7 @@ static void set_irq_line(m68000_base_device *m68k, int irqline, int state)
/* A transition from < 7 to 7 always interrupts (NMI) */
/* Note: Level 7 can also level trigger like a normal IRQ */
if(old_level != 0x0700 && m68k->int_level == 0x0700)
- m68k->nmi_pending = TRUE;
+ m68k->nmi_pending = true;
}
void m68000_base_device::presave()
@@ -733,7 +733,7 @@ bool m68000_base_device::memory_translate(address_spacenum space, int intention,
mmu_tmp_sr = temp_mmu_tmp_sr;
}
}
- return TRUE;
+ return true;
}
@@ -2623,7 +2623,7 @@ bool m68020hmmu_device::memory_translate(address_spacenum space, int intention,
address = hmmu_translate_addr(this, address);
}
}
- return TRUE;
+ return true;
}
diff --git a/src/devices/cpu/m68000/m68kcpu.h b/src/devices/cpu/m68000/m68kcpu.h
index e452ece67ec..d9ad9656bf2 100644
--- a/src/devices/cpu/m68000/m68kcpu.h
+++ b/src/devices/cpu/m68000/m68kcpu.h
@@ -1682,7 +1682,7 @@ static inline void m68ki_check_interrupts(m68000_base_device *m68k)
{
if(m68k->nmi_pending)
{
- m68k->nmi_pending = FALSE;
+ m68k->nmi_pending = false;
m68k->m68ki_exception_interrupt(m68k, 7);
}
else if(m68k->int_level > m68k->int_mask)
diff --git a/src/devices/cpu/m6809/6309dasm.cpp b/src/devices/cpu/m6809/6309dasm.cpp
index 16f4c3b1752..439c83a718a 100644
--- a/src/devices/cpu/m6809/6309dasm.cpp
+++ b/src/devices/cpu/m6809/6309dasm.cpp
@@ -613,7 +613,8 @@ CPU_DISASSEMBLE( hd6309 )
unsigned int ea, flags;
int numoperands, offset, indirect;
- int i, p = 0, page = 0, opcode_found;
+ int i, p = 0, page = 0;
+ bool opcode_found;
do
{
@@ -623,7 +624,7 @@ CPU_DISASSEMBLE( hd6309 )
break;
if (i < hd6309_numops[page])
- opcode_found = TRUE;
+ opcode_found = true;
else
{
strcpy(buffer, "Illegal Opcode");
@@ -633,7 +634,7 @@ CPU_DISASSEMBLE( hd6309 )
if (hd6309_pgpointers[page][i].mode >= PG1)
{
page = hd6309_pgpointers[page][i].mode - PG1 + 1;
- opcode_found = FALSE;
+ opcode_found = false;
}
} while (!opcode_found);
@@ -749,7 +750,7 @@ CPU_DISASSEMBLE( hd6309 )
reg = (pb >> 5) & 3;
pbm = pb & 0x8f;
- indirect = ((pb & 0x90) == 0x90 )? TRUE : FALSE;
+ indirect = ((pb & 0x90) == 0x90 )? true : false;
// open brackets if indirect
if (indirect && pbm != 0x82)
diff --git a/src/devices/cpu/m6809/6809dasm.cpp b/src/devices/cpu/m6809/6809dasm.cpp
index 971abc9b2a8..e255f386e53 100644
--- a/src/devices/cpu/m6809/6809dasm.cpp
+++ b/src/devices/cpu/m6809/6809dasm.cpp
@@ -371,8 +371,10 @@ CPU_DISASSEMBLE( m6809 )
uint8_t opcode, mode, pb, pbm, reg;
const uint8_t *operandarray;
unsigned int ea, flags;
- int numoperands, offset, indirect;
- int i, p = 0, page = 0, opcode_found;
+ int numoperands, offset;
+ bool indirect;
+ int i, p = 0, page = 0;
+ bool opcode_found;
do
{
@@ -383,7 +385,7 @@ CPU_DISASSEMBLE( m6809 )
break;
if (i < m6809_numops[page])
- opcode_found = TRUE;
+ opcode_found = true;
else
{
strcpy(buffer, "Illegal Opcode");
@@ -393,7 +395,7 @@ CPU_DISASSEMBLE( m6809 )
if (m6809_pgpointers[page][i].mode >= PG1)
{
page = m6809_pgpointers[page][i].mode - PG1 + 1;
- opcode_found = FALSE;
+ opcode_found = false;
}
} while (!opcode_found);
@@ -485,7 +487,7 @@ CPU_DISASSEMBLE( m6809 )
pb = operandarray[0];
reg = (pb >> 5) & 3;
pbm = pb & 0x8f;
- indirect = ((pb & 0x90) == 0x90 )? TRUE : FALSE;
+ indirect = ((pb & 0x90) == 0x90 )? true : false;
// open brackets if indirect
if (indirect && pbm != 0x80 && pbm != 0x82)
diff --git a/src/devices/cpu/m6809/knmidasm.cpp b/src/devices/cpu/m6809/knmidasm.cpp
index 5c325e81718..f4de8a22048 100644
--- a/src/devices/cpu/m6809/knmidasm.cpp
+++ b/src/devices/cpu/m6809/knmidasm.cpp
@@ -4,11 +4,6 @@
#include "debugger.h"
#include "konami.h"
-#ifndef TRUE
-#define TRUE -1
-#define FALSE 0
-#endif
-
/*
0x08 leax indexed
diff --git a/src/devices/cpu/mcs48/mcs48.cpp b/src/devices/cpu/mcs48/mcs48.cpp
index 88b4185cf0a..d27e8cf438e 100644
--- a/src/devices/cpu/mcs48/mcs48.cpp
+++ b/src/devices/cpu/mcs48/mcs48.cpp
@@ -640,8 +640,8 @@ OPHANDLER( dec_r5 ) { R5--; return 1; }
OPHANDLER( dec_r6 ) { R6--; return 1; }
OPHANDLER( dec_r7 ) { R7--; return 1; }
-OPHANDLER( dis_i ) { m_xirq_enabled = FALSE; return 1; }
-OPHANDLER( dis_tcnti ) { m_tirq_enabled = FALSE; m_timer_overflow = FALSE; return 1; }
+OPHANDLER( dis_i ) { m_xirq_enabled = false; return 1; }
+OPHANDLER( dis_tcnti ) { m_tirq_enabled = false; m_timer_overflow = false; return 1; }
OPHANDLER( djnz_r0 ) { execute_jcc(--R0 != 0); return 2; }
OPHANDLER( djnz_r1 ) { execute_jcc(--R1 != 0); return 2; }
@@ -652,10 +652,10 @@ OPHANDLER( djnz_r5 ) { execute_jcc(--R5 != 0); return 2; }
OPHANDLER( djnz_r6 ) { execute_jcc(--R6 != 0); return 2; }
OPHANDLER( djnz_r7 ) { execute_jcc(--R7 != 0); return 2; }
-OPHANDLER( en_i ) { m_xirq_enabled = TRUE; return 1 + check_irqs(); }
-OPHANDLER( en_tcnti ) { m_tirq_enabled = TRUE; return 1 + check_irqs(); }
-OPHANDLER( en_dma ) { m_dma_enabled = TRUE; port_w(2, m_p2); return 1; }
-OPHANDLER( en_flags ) { m_flags_enabled = TRUE; port_w(2, m_p2); return 1; }
+OPHANDLER( en_i ) { m_xirq_enabled = true; return 1 + check_irqs(); }
+OPHANDLER( en_tcnti ) { m_tirq_enabled = true; return 1 + check_irqs(); }
+OPHANDLER( en_dma ) { m_dma_enabled = true; port_w(2, m_p2); return 1; }
+OPHANDLER( en_flags ) { m_flags_enabled = true; port_w(2, m_p2); return 1; }
OPHANDLER( ent0_clk )
{
logerror("MCS-48 PC:%04X - Unimplemented opcode = %02x\n", m_pc - 1, program_r(m_pc - 1));
@@ -709,7 +709,7 @@ OPHANDLER( jnt_0 ) { execute_jcc(test_r(0) == 0); return 2; }
OPHANDLER( jnt_1 ) { execute_jcc(test_r(1) == 0); return 2; }
OPHANDLER( jnz ) { execute_jcc(m_a != 0); return 2; }
OPHANDLER( jobf ) { execute_jcc((m_sts & STS_OBF) != 0); return 2; }
-OPHANDLER( jtf ) { execute_jcc(m_timer_flag); m_timer_flag = FALSE; return 2; }
+OPHANDLER( jtf ) { execute_jcc(m_timer_flag); m_timer_flag = false; return 2; }
OPHANDLER( jt_0 ) { execute_jcc(test_r(0) != 0); return 2; }
OPHANDLER( jt_1 ) { execute_jcc(test_r(1) != 0); return 2; }
OPHANDLER( jz ) { execute_jcc(m_a == 0); return 2; }
@@ -823,7 +823,7 @@ OPHANDLER( retr )
pull_pc_psw();
/* implicitly clear the IRQ in progress flip flop and re-check interrupts */
- m_irq_in_progress = FALSE;
+ m_irq_in_progress = false;
return 2 + check_irqs();
}
@@ -1036,17 +1036,17 @@ void mcs48_cpu_device::device_reset()
m_p2 = 0xff;
port_w(1, m_p1);
port_w(2, m_p2);
- m_tirq_enabled = FALSE;
- m_xirq_enabled = FALSE;
+ m_tirq_enabled = false;
+ m_xirq_enabled = false;
m_timecount_enabled = 0;
- m_timer_flag = FALSE;
+ m_timer_flag = false;
m_sts = 0;
- m_flags_enabled = FALSE;
- m_dma_enabled = FALSE;
+ m_flags_enabled = false;
+ m_dma_enabled = false;
/* confirmed from interrupt logic description */
- m_irq_in_progress = FALSE;
- m_timer_overflow = FALSE;
+ m_irq_in_progress = false;
+ m_timer_overflow = false;
}
@@ -1068,7 +1068,7 @@ int mcs48_cpu_device::check_irqs()
/* external interrupts take priority */
if ((m_irq_state || (m_sts & STS_IBF) != 0) && m_xirq_enabled)
{
- m_irq_in_progress = TRUE;
+ m_irq_in_progress = true;
/* transfer to location 0x03 */
push_pc_psw();
@@ -1082,14 +1082,14 @@ int mcs48_cpu_device::check_irqs()
/* timer overflow interrupts follow */
if (m_timer_overflow && m_tirq_enabled)
{
- m_irq_in_progress = TRUE;
+ m_irq_in_progress = true;
/* transfer to location 0x07 */
push_pc_psw();
m_pc = 0x07;
/* timer overflow flip-flop is reset once taken */
- m_timer_overflow = FALSE;
+ m_timer_overflow = false;
return 2;
}
return 0;
@@ -1103,7 +1103,7 @@ int mcs48_cpu_device::check_irqs()
void mcs48_cpu_device::burn_cycles(int count)
{
- int timerover = FALSE;
+ int timerover = false;
/* if the timer is enabled, accumulate prescaler cycles */
if (m_timecount_enabled & TIMER_ENABLED)
@@ -1127,12 +1127,12 @@ void mcs48_cpu_device::burn_cycles(int count)
/* if either source caused a timer overflow, set the flags and check IRQs */
if (timerover)
{
- m_timer_flag = TRUE;
+ m_timer_flag = true;
/* according to the docs, if an overflow occurs with interrupts disabled, the overflow is not stored */
if (m_tirq_enabled)
{
- m_timer_overflow = TRUE;
+ m_timer_overflow = true;
check_irqs();
}
}
diff --git a/src/devices/cpu/mcs48/mcs48.h b/src/devices/cpu/mcs48/mcs48.h
index 81e5b85fc29..096b1e6331c 100644
--- a/src/devices/cpu/mcs48/mcs48.h
+++ b/src/devices/cpu/mcs48/mcs48.h
@@ -175,15 +175,15 @@ protected:
uint8_t m_dbbi; /* 8-bit input data buffer (UPI-41 only) */
uint8_t m_dbbo; /* 8-bit output data buffer (UPI-41 only) */
- uint8_t m_irq_state; /* TRUE if an IRQ is pending */
- uint8_t m_irq_in_progress; /* TRUE if an IRQ is in progress */
- uint8_t m_timer_overflow; /* TRUE on a timer overflow; cleared by taking interrupt */
- uint8_t m_timer_flag; /* TRUE on a timer overflow; cleared on JTF */
- uint8_t m_tirq_enabled; /* TRUE if the timer IRQ is enabled */
- uint8_t m_xirq_enabled; /* TRUE if the external IRQ is enabled */
+ bool m_irq_state; /* true if an IRQ is pending */
+ bool m_irq_in_progress; /* true if an IRQ is in progress */
+ bool m_timer_overflow; /* true on a timer overflow; cleared by taking interrupt */
+ bool m_timer_flag; /* true on a timer overflow; cleared on JTF */
+ bool m_tirq_enabled; /* true if the timer IRQ is enabled */
+ bool m_xirq_enabled; /* true if the external IRQ is enabled */
uint8_t m_timecount_enabled; /* bitmask of timer/counter enabled */
- uint8_t m_flags_enabled; /* TRUE if I/O flags have been enabled (UPI-41 only) */
- uint8_t m_dma_enabled; /* TRUE if DMA has been enabled (UPI-41 only) */
+ bool m_flags_enabled; /* true if I/O flags have been enabled (UPI-41 only) */
+ bool m_dma_enabled; /* true if DMA has been enabled (UPI-41 only) */
uint16_t m_a11; /* A11 value, either 0x000 or 0x800 */
diff --git a/src/devices/cpu/mcs48/mcs48dsm.cpp b/src/devices/cpu/mcs48/mcs48dsm.cpp
index 15a74946ff0..ae86798ec92 100644
--- a/src/devices/cpu/mcs48/mcs48dsm.cpp
+++ b/src/devices/cpu/mcs48/mcs48dsm.cpp
@@ -12,7 +12,7 @@
#include "emu.h"
-static uint32_t common_dasm(device_t *device, char *buffer, offs_t pc, const uint8_t *oprom, const uint8_t *opram, int upi41)
+static uint32_t common_dasm(device_t *device, char *buffer, offs_t pc, const uint8_t *oprom, const uint8_t *opram, bool upi41)
{
const uint8_t *startram = opram;
uint32_t flags = 0;
@@ -317,11 +317,11 @@ static uint32_t common_dasm(device_t *device, char *buffer, offs_t pc, const uin
CPU_DISASSEMBLE( mcs48 )
{
- return common_dasm(device, buffer, pc, oprom, opram, FALSE);
+ return common_dasm(device, buffer, pc, oprom, opram, false);
}
CPU_DISASSEMBLE( upi41 )
{
- return common_dasm(device, buffer, pc, oprom, opram, TRUE);
+ return common_dasm(device, buffer, pc, oprom, opram, true);
}
diff --git a/src/devices/cpu/mips/mips3.cpp b/src/devices/cpu/mips/mips3.cpp
index fd174f6dccb..a2bc7cbfa7f 100644
--- a/src/devices/cpu/mips/mips3.cpp
+++ b/src/devices/cpu/mips/mips3.cpp
@@ -421,7 +421,7 @@ void mips3_device::device_start()
}
/* mark the cache dirty so it is updated on next execute */
- m_cache_dirty = TRUE;
+ m_cache_dirty = true;
/* register for save states */
@@ -943,7 +943,7 @@ void mips3_device::device_reset()
vtlb_load(2 * m_tlbentries + 1, (0xc0000000 - 0xa0000000) >> MIPS3_MIN_PAGE_SHIFT, 0xa0000000, 0x00000000 | VTLB_READ_ALLOWED | VTLB_WRITE_ALLOWED | VTLB_FETCH_ALLOWED | VTLB_FLAG_VALID);
m_core->mode = (MODE_KERNEL << 1) | 0;
- m_cache_dirty = TRUE;
+ m_cache_dirty = true;
m_interrupt_cycles = 0;
}
@@ -1156,7 +1156,7 @@ inline void mips3_device::WBYTE(offs_t address, uint8_t data)
const uint32_t tlbaddress = (tlbval & ~0xfff) | (address & 0xfff);
for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
{
- if (m_fastram[ramnum].readonly == TRUE || tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
+ if (m_fastram[ramnum].readonly == true || tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
{
continue;
}
@@ -1190,7 +1190,7 @@ inline void mips3_device::WHALF(offs_t address, uint16_t data)
const uint32_t tlbaddress = (tlbval & ~0xfff) | (address & 0xfff);
for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
{
- if (m_fastram[ramnum].readonly == TRUE || tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
+ if (m_fastram[ramnum].readonly == true || tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
{
continue;
}
@@ -1224,7 +1224,7 @@ inline void mips3_device::WWORD(offs_t address, uint32_t data)
const uint32_t tlbaddress = (tlbval & ~0xfff) | (address & 0xfff);
for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
{
- if (m_fastram[ramnum].readonly == TRUE || tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
+ if (m_fastram[ramnum].readonly == true || tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
{
continue;
}
@@ -2718,7 +2718,7 @@ void mips3_device::execute_run()
/* reset the cache if dirty */
if (m_cache_dirty)
code_flush_cache();
- m_cache_dirty = FALSE;
+ m_cache_dirty = false;
/* execute */
do
diff --git a/src/devices/cpu/mips/mips3.h b/src/devices/cpu/mips/mips3.h
index 247b21bd993..64997ca67ad 100644
--- a/src/devices/cpu/mips/mips3.h
+++ b/src/devices/cpu/mips/mips3.h
@@ -396,7 +396,7 @@ private:
{
offs_t start; /* start of the RAM block */
offs_t end; /* end of the RAM block */
- uint8_t readonly; /* TRUE if read-only */
+ bool readonly; /* true if read-only */
void * base; /* base in memory where the RAM lives */
uint8_t * offset_base8; /* base in memory where the RAM lives, 8-bit pointer, with the start offset pre-applied */
uint16_t * offset_base16; /* base in memory where the RAM lives, 16-bit pointer, with the start offset pre-applied */
@@ -544,27 +544,27 @@ private:
void static_generate_memory_accessor(int mode, int size, int iswrite, int ismasked, const char *name, uml::code_handle **handleptr);
void generate_update_mode(drcuml_block *block);
- void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
+ void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception);
void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
void generate_delay_slot_and_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint8_t linkreg);
- int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_idt(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_idt(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_set_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint8_t reg);
- int generate_get_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint8_t reg);
- int generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_cop1_fr0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_cop1_fr1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_set_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint8_t reg);
+ bool generate_get_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint8_t reg);
+ bool generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_cop1_fr0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_cop1_fr1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
void generate_get_cop1_reg64(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, const uint32_t reg, const uml::parameter& param);
void generate_get_cop1_reg64_d2i(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, const uint32_t reg, const uml::parameter& param);
void generate_set_cop1_reg64(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, const uint32_t reg, const uml::parameter& param);
void generate_set_cop1_reg64_i2d(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, const uint32_t reg, const uml::parameter& param);
- int generate_cop1x_fr0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_cop1x_fr1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_cop1x_fr0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_cop1x_fr1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
void check_cop0_access(drcuml_block *block);
void check_cop1_access(drcuml_block *block);
diff --git a/src/devices/cpu/mips/mips3com.cpp b/src/devices/cpu/mips/mips3com.cpp
index 8da695c4833..3410843c3e1 100644
--- a/src/devices/cpu/mips/mips3com.cpp
+++ b/src/devices/cpu/mips/mips3com.cpp
@@ -25,22 +25,22 @@ static void tlb_entry_log_half(mips3_tlb_entry *entry, int tlbindex, int which);
***************************************************************************/
/*-------------------------------------------------
- tlb_entry_matches_asid - TRUE if the given
+ tlb_entry_matches_asid - true if the given
TLB entry matches the provided ASID
-------------------------------------------------*/
-static inline int tlb_entry_matches_asid(const mips3_tlb_entry *entry, uint8_t asid)
+static inline bool tlb_entry_matches_asid(const mips3_tlb_entry *entry, uint8_t asid)
{
return (entry->entry_hi & 0xff) == asid;
}
/*-------------------------------------------------
- tlb_entry_is_global - TRUE if the given
+ tlb_entry_is_global - true if the given
TLB entry is global
-------------------------------------------------*/
-static inline int tlb_entry_is_global(const mips3_tlb_entry *entry)
+static inline bool tlb_entry_is_global(const mips3_tlb_entry *entry)
{
return (entry->entry_lo[0] & entry->entry_lo[1] & TLB_GLOBAL);
}
diff --git a/src/devices/cpu/mips/mips3drc.cpp b/src/devices/cpu/mips/mips3drc.cpp
index 4d1de76e309..981f3f6328c 100644
--- a/src/devices/cpu/mips/mips3drc.cpp
+++ b/src/devices/cpu/mips/mips3drc.cpp
@@ -186,7 +186,7 @@ void mips3_device::clear_fastram(uint32_t select_start)
}
m_fastram_select=select_start;
// Set cache to dirty so that re-mapping occurs
- m_cache_dirty = TRUE;
+ m_cache_dirty = true;
}
/*-------------------------------------------------
@@ -253,37 +253,37 @@ void mips3_device::code_flush_cache()
static_generate_tlb_mismatch();
/* append exception handlers for various types */
- static_generate_exception(EXCEPTION_INTERRUPT, TRUE, "exception_interrupt");
- static_generate_exception(EXCEPTION_INTERRUPT, FALSE, "exception_interrupt_norecover");
- static_generate_exception(EXCEPTION_TLBMOD, TRUE, "exception_tlbmod");
- static_generate_exception(EXCEPTION_TLBLOAD, TRUE, "exception_tlbload");
- static_generate_exception(EXCEPTION_TLBSTORE, TRUE, "exception_tlbstore");
- static_generate_exception(EXCEPTION_TLBLOAD_FILL, TRUE, "exception_tlbload_fill");
- static_generate_exception(EXCEPTION_TLBSTORE_FILL, TRUE, "exception_tlbstore_fill");
- static_generate_exception(EXCEPTION_ADDRLOAD, TRUE, "exception_addrload");
- static_generate_exception(EXCEPTION_ADDRSTORE, TRUE, "exception_addrstore");
- static_generate_exception(EXCEPTION_SYSCALL, TRUE, "exception_syscall");
- static_generate_exception(EXCEPTION_BREAK, TRUE, "exception_break");
- static_generate_exception(EXCEPTION_INVALIDOP, TRUE, "exception_invalidop");
- static_generate_exception(EXCEPTION_BADCOP, TRUE, "exception_badcop");
- static_generate_exception(EXCEPTION_OVERFLOW, TRUE, "exception_overflow");
- static_generate_exception(EXCEPTION_TRAP, TRUE, "exception_trap");
+ static_generate_exception(EXCEPTION_INTERRUPT, true, "exception_interrupt");
+ static_generate_exception(EXCEPTION_INTERRUPT, false, "exception_interrupt_norecover");
+ static_generate_exception(EXCEPTION_TLBMOD, true, "exception_tlbmod");
+ static_generate_exception(EXCEPTION_TLBLOAD, true, "exception_tlbload");
+ static_generate_exception(EXCEPTION_TLBSTORE, true, "exception_tlbstore");
+ static_generate_exception(EXCEPTION_TLBLOAD_FILL, true, "exception_tlbload_fill");
+ static_generate_exception(EXCEPTION_TLBSTORE_FILL, true, "exception_tlbstore_fill");
+ static_generate_exception(EXCEPTION_ADDRLOAD, true, "exception_addrload");
+ static_generate_exception(EXCEPTION_ADDRSTORE, true, "exception_addrstore");
+ static_generate_exception(EXCEPTION_SYSCALL, true, "exception_syscall");
+ static_generate_exception(EXCEPTION_BREAK, true, "exception_break");
+ static_generate_exception(EXCEPTION_INVALIDOP, true, "exception_invalidop");
+ static_generate_exception(EXCEPTION_BADCOP, true, "exception_badcop");
+ static_generate_exception(EXCEPTION_OVERFLOW, true, "exception_overflow");
+ static_generate_exception(EXCEPTION_TRAP, true, "exception_trap");
/* add subroutines for memory accesses */
for (mode = 0; mode < 3; mode++)
{
- static_generate_memory_accessor(mode, 1, FALSE, FALSE, "read8", &m_read8[mode]);
- static_generate_memory_accessor(mode, 1, TRUE, FALSE, "write8", &m_write8[mode]);
- static_generate_memory_accessor(mode, 2, FALSE, FALSE, "read16", &m_read16[mode]);
- static_generate_memory_accessor(mode, 2, TRUE, FALSE, "write16", &m_write16[mode]);
- static_generate_memory_accessor(mode, 4, FALSE, FALSE, "read32", &m_read32[mode]);
- static_generate_memory_accessor(mode, 4, FALSE, TRUE, "read32mask", &m_read32mask[mode]);
- static_generate_memory_accessor(mode, 4, TRUE, FALSE, "write32", &m_write32[mode]);
- static_generate_memory_accessor(mode, 4, TRUE, TRUE, "write32mask", &m_write32mask[mode]);
- static_generate_memory_accessor(mode, 8, FALSE, FALSE, "read64", &m_read64[mode]);
- static_generate_memory_accessor(mode, 8, FALSE, TRUE, "read64mask", &m_read64mask[mode]);
- static_generate_memory_accessor(mode, 8, TRUE, FALSE, "write64", &m_write64[mode]);
- static_generate_memory_accessor(mode, 8, TRUE, TRUE, "write64mask", &m_write64mask[mode]);
+ static_generate_memory_accessor(mode, 1, false, false, "read8", &m_read8[mode]);
+ static_generate_memory_accessor(mode, 1, true, false, "write8", &m_write8[mode]);
+ static_generate_memory_accessor(mode, 2, false, false, "read16", &m_read16[mode]);
+ static_generate_memory_accessor(mode, 2, true, false, "write16", &m_write16[mode]);
+ static_generate_memory_accessor(mode, 4, false, false, "read32", &m_read32[mode]);
+ static_generate_memory_accessor(mode, 4, false, true, "read32mask", &m_read32mask[mode]);
+ static_generate_memory_accessor(mode, 4, true, false, "write32", &m_write32[mode]);
+ static_generate_memory_accessor(mode, 4, true, true, "write32mask", &m_write32mask[mode]);
+ static_generate_memory_accessor(mode, 8, false, false, "read64", &m_read64[mode]);
+ static_generate_memory_accessor(mode, 8, false, true, "read64mask", &m_read64mask[mode]);
+ static_generate_memory_accessor(mode, 8, true, false, "write64", &m_write64[mode]);
+ static_generate_memory_accessor(mode, 8, true, true, "write64mask", &m_write64mask[mode]);
}
}
catch (drcuml_block::abort_compilation &)
@@ -304,7 +304,7 @@ void mips3_device::code_compile_block(uint8_t mode, offs_t pc)
compiler_state compiler = { 0 };
const opcode_desc *seqhead, *seqlast;
const opcode_desc *desclist;
- int override = FALSE;
+ bool override = false;
drcuml_block *block;
g_profiler.start(PROFILER_DRC_COMPILE);
@@ -347,7 +347,7 @@ void mips3_device::code_compile_block(uint8_t mode, offs_t pc)
/* are recompiling due to being out of sync and allow future overrides */
else if (seqhead == desclist)
{
- override = TRUE;
+ override = true;
UML_HASH(block, mode, seqhead->pc); // hash mode,pc
}
@@ -381,7 +381,7 @@ void mips3_device::code_compile_block(uint8_t mode, offs_t pc)
nextpc = seqlast->pc + (seqlast->skipslots + 1) * 4;
/* count off cycles and go there */
- generate_update_cycles(block, &compiler, nextpc, TRUE); // <subtract cycles>
+ generate_update_cycles(block, &compiler, nextpc, true); // <subtract cycles>
/* if the last instruction can change modes, use a variable mode; otherwise, assume the same mode */
if (seqlast->flags & OPFLAG_CAN_CHANGE_MODES)
@@ -1049,14 +1049,14 @@ void mips3_device::generate_update_mode(drcuml_block *block)
an exception if out
-------------------------------------------------*/
-void mips3_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception)
+void mips3_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception)
{
/* check software interrupts if pending */
if (compiler->checksoftints)
{
code_label skip;
- compiler->checksoftints = FALSE;
+ compiler->checksoftints = false;
UML_AND(block, I0, CPR032(COP0_Cause), CPR032(COP0_Status)); // and i0,[Cause],[Status]
UML_AND(block, I0, I0, 0x0300); // and i0,i0,0x0300
UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z
@@ -1071,7 +1071,7 @@ void mips3_device::generate_update_cycles(drcuml_block *block, compiler_state *c
{
code_label skip;
- compiler->checkints = FALSE;
+ compiler->checkints = false;
UML_AND(block, I0, CPR032(COP0_Cause), CPR032(COP0_Status)); // and i0,[Cause],[Status]
UML_AND(block, I0, I0, 0xfc00); // and i0,i0,0xfc00
UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z
@@ -1324,7 +1324,7 @@ void mips3_device::generate_delay_slot_and_branch(drcuml_block *block, compiler_
/* update the cycles and jump through the hash table to the target */
if (desc->targetpc != BRANCH_TARGET_DYNAMIC)
{
- generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE); // <subtract cycles>
+ generate_update_cycles(block, &compiler_temp, desc->targetpc, true); // <subtract cycles>
if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
UML_JMP(block, desc->targetpc | 0x80000000); // jmp desc->targetpc | 0x80000000
else
@@ -1333,7 +1333,7 @@ void mips3_device::generate_delay_slot_and_branch(drcuml_block *block, compiler_
}
else
{
- generate_update_cycles(block, &compiler_temp, mem(&m_core->jmpdest), TRUE);
+ generate_update_cycles(block, &compiler_temp, mem(&m_core->jmpdest), true);
// <subtract cycles>
UML_HASHJMP(block, m_core->mode, mem(&m_core->jmpdest), *m_nocode);
// hashjmp <mode>,<rsreg>,nocode
@@ -1353,7 +1353,7 @@ void mips3_device::generate_delay_slot_and_branch(drcuml_block *block, compiler_
opcode
-------------------------------------------------*/
-int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
int in_delay_slot = ((desc->flags & OPFLAG_IN_DELAY_SLOT) != 0);
uint32_t op = desc->opptr.l[0];
@@ -1378,11 +1378,11 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
case 0x02: /* J - MIPS I */
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
- return TRUE;
+ return true;
case 0x03: /* JAL - MIPS I */
generate_delay_slot_and_branch(block, compiler, desc, 31); // <next instruction + hashjmp>
- return TRUE;
+ return true;
case 0x04: /* BEQ - MIPS I */
case 0x14: /* BEQL - MIPS II */
@@ -1390,7 +1390,7 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_JMPc(block, COND_NE, skip = compiler->labelnum++); // jmp skip,NE
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
- return TRUE;
+ return true;
case 0x05: /* BNE - MIPS I */
case 0x15: /* BNEL - MIPS II */
@@ -1398,7 +1398,7 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_JMPc(block, COND_E, skip = compiler->labelnum++); // jmp skip,E
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
- return TRUE;
+ return true;
case 0x06: /* BLEZ - MIPS I */
case 0x16: /* BLEZL - MIPS II */
@@ -1411,7 +1411,7 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
}
else
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
- return TRUE;
+ return true;
case 0x07: /* BGTZ - MIPS I */
case 0x17: /* BGTZL - MIPS II */
@@ -1419,7 +1419,7 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_JMPc(block, COND_LE, skip = compiler->labelnum++); // jmp skip,LE
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
- return TRUE;
+ return true;
/* ----- immediate arithmetic ----- */
@@ -1427,7 +1427,7 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
case 0x0f: /* LUI - MIPS I */
if (RTREG != 0)
UML_DMOV(block, R64(RTREG), UIMMVAL << 16); // dmov <rtreg>,UIMMVAL << 16
- return TRUE;
+ return true;
case 0x08: /* ADDI - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -1436,7 +1436,7 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
// exh overflow,0
if (RTREG != 0)
UML_DSEXT(block, R64(RTREG), I0, SIZE_DWORD); // dsext <rtreg>,i0,dword
- return TRUE;
+ return true;
case 0x09: /* ADDIU - MIPS I */
if (RTREG != 0)
@@ -1444,7 +1444,7 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL,V
UML_DSEXT(block, R64(RTREG), I0, SIZE_DWORD); // dsext <rtreg>,i0,dword
}
- return TRUE;
+ return true;
case 0x18: /* DADDI - MIPS III */
UML_DADD(block, I0, R64(RSREG), SIMMVAL); // dadd i0,<rsreg>,SIMMVAL
@@ -1453,27 +1453,27 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
// exh overflow,0
if (RTREG != 0)
UML_DMOV(block, R64(RTREG), I0); // dmov <rtreg>,i0
- return TRUE;
+ return true;
case 0x19: /* DADDIU - MIPS III */
if (RTREG != 0)
UML_DADD(block, R64(RTREG), R64(RSREG), SIMMVAL); // dadd <rtreg>,<rsreg>,SIMMVAL
- return TRUE;
+ return true;
case 0x0c: /* ANDI - MIPS I */
if (RTREG != 0)
UML_DAND(block, R64(RTREG), R64(RSREG), UIMMVAL); // dand <rtreg>,<rsreg>,UIMMVAL
- return TRUE;
+ return true;
case 0x0d: /* ORI - MIPS I */
if (RTREG != 0)
UML_DOR(block, R64(RTREG), R64(RSREG), UIMMVAL); // dor <rtreg>,<rsreg>,UIMMVAL
- return TRUE;
+ return true;
case 0x0e: /* XORI - MIPS I */
if (RTREG != 0)
UML_DXOR(block, R64(RTREG), R64(RSREG), UIMMVAL); // dxor <rtreg>,<rsreg>,UIMMVAL
- return TRUE;
+ return true;
case 0x0a: /* SLTI - MIPS I */
if (RTREG != 0)
@@ -1481,7 +1481,7 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL
UML_DSETc(block, COND_L, R64(RTREG)); // dset <rtreg>,l
}
- return TRUE;
+ return true;
case 0x0b: /* SLTIU - MIPS I */
if (RTREG != 0)
@@ -1489,7 +1489,7 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL
UML_DSETc(block, COND_B, R64(RTREG)); // dset <rtreg>,b
}
- return TRUE;
+ return true;
/* ----- memory load operations ----- */
@@ -1500,8 +1500,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
if (RTREG != 0)
UML_DSEXT(block, R64(RTREG), I0, SIZE_BYTE); // dsext <rtreg>,i0,byte
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x21: /* LH - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -1509,8 +1509,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
if (RTREG != 0)
UML_DSEXT(block, R64(RTREG), I0, SIZE_WORD); // dsext <rtreg>,i0,word
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x23: /* LW - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -1518,8 +1518,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
if (RTREG != 0)
UML_DSEXT(block, R64(RTREG), I0, SIZE_DWORD); // dsext <rtreg>,i0
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x30: /* LL - MIPS II */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -1528,8 +1528,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_DSEXT(block, R64(RTREG), I0, SIZE_DWORD); // dsext <rtreg>,i0
UML_MOV(block, mem(&m_core->llbit), 1); // mov [llbit],1
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x24: /* LBU - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -1537,8 +1537,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
if (RTREG != 0)
UML_DAND(block, R64(RTREG), I0, 0xff); // dand <rtreg>,i0,0xff
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x25: /* LHU - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -1546,8 +1546,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
if (RTREG != 0)
UML_DAND(block, R64(RTREG), I0, 0xffff); // dand <rtreg>,i0,0xffff
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x27: /* LWU - MIPS III */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -1555,8 +1555,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
if (RTREG != 0)
UML_DAND(block, R64(RTREG), I0, 0xffffffff); // dand <rtreg>,i0,0xffffffff
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x37: /* LD - MIPS III */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -1564,8 +1564,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
if (RTREG != 0)
UML_DMOV(block, R64(RTREG), I0); // dmov <rtreg>,i0
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x34: /* LLD - MIPS III */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -1574,8 +1574,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_DMOV(block, R64(RTREG), I0); // dmov <rtreg>,i0
UML_MOV(block, mem(&m_core->llbit), 1); // mov [llbit],1
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x22: /* LWL - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -1594,8 +1594,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_DSEXT(block, R64(RTREG), I3, SIZE_DWORD); // dsext <rtreg>,i3,dword
}
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x26: /* LWR - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -1615,8 +1615,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_DSEXT(block, R64(RTREG), I3, SIZE_DWORD); // dsext <rtreg>,i3,dword
}
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x1a: /* LDL - MIPS III */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -1633,8 +1633,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_DROLINS(block, R64(RTREG), I0, I1, I2); // drolins <rtreg>,i0,i1,i2
}
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x1b: /* LDR - MIPS III */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -1651,8 +1651,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_DROLINS(block, R64(RTREG), I0, I1, I2); // drolins <rtreg>,i0,i1,i2
}
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x31: /* LWC1 - MIPS I */
check_cop1_access(block);
@@ -1660,8 +1660,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh read32
UML_MOV(block, FPR32_FR0(RTREG), I0); // mov <cpr1_rt>,i0
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x35: /* LDC1 - MIPS III */
check_cop1_access(block);
@@ -1669,24 +1669,24 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh read64
generate_set_cop1_reg64_i2d(block, compiler, desc, RTREG, I0);
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x32: /* LWC2 - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh read32
UML_DAND(block, CPR264(RTREG), I0, 0xffffffff); // dand <cpr2_rt>,i0,0xffffffff
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x36: /* LDC2 - MIPS II */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh read64
UML_DMOV(block, CPR264(RTREG), I0); // dmov <cpr2_rt>,i0
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
/* ----- memory store operations ----- */
@@ -1696,24 +1696,24 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg>
UML_CALLH(block, *m_write8[m_core->mode >> 1]); // callh write8
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x29: /* SH - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg>
UML_CALLH(block, *m_write16[m_core->mode >> 1]); // callh write16
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x2b: /* SW - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg>
UML_CALLH(block, *m_write32[m_core->mode >> 1]); // callh write32
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x38: /* SC - MIPS II */
UML_CMP(block, mem(&m_core->llbit), 0); // cmp [llbit],0
@@ -1724,16 +1724,16 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_LABEL(block, skip); // skip:
UML_DSEXT(block, R64(RTREG), mem(&m_core->llbit), SIZE_DWORD); // dsext <rtreg>,[llbit],dword
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x3f: /* SD - MIPS III */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
UML_DMOV(block, I1, R64(RTREG)); // dmov i1,<rtreg>
UML_CALLH(block, *m_write64[m_core->mode >> 1]); // callh write64
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x3c: /* SCD - MIPS III */
UML_CMP(block, mem(&m_core->llbit), 0); // cmp [llbit],0
@@ -1744,8 +1744,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_LABEL(block, skip); // skip:
UML_DSEXT(block, R64(RTREG), mem(&m_core->llbit), SIZE_DWORD); // dsext <rtreg>,[llbit],dword
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x2a: /* SWL - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -1759,8 +1759,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write32mask[m_core->mode >> 1]);
// callh write32mask
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x2e: /* SWR - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -1774,8 +1774,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write32mask[m_core->mode >> 1]);
// callh write32mask
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x2c: /* SDL - MIPS III */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -1789,8 +1789,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write64mask[m_core->mode >> 1]);// callh write64mask
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x2d: /* SDR - MIPS III */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -1804,8 +1804,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write64mask[m_core->mode >> 1]);// callh write64mask
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x39: /* SWC1 - MIPS I */
check_cop1_access(block);
@@ -1813,8 +1813,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_MOV(block, I1, FPR32_FR0(RTREG)); // mov i1,<cpr1_rt>
UML_CALLH(block, *m_write32[m_core->mode >> 1]); // callh write32
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x3d: /* SDC1 - MIPS III */
check_cop1_access(block);
@@ -1822,31 +1822,31 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
UML_CALLH(block, *m_write64[m_core->mode >> 1]); // callh write64
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x3a: /* SWC2 - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
UML_MOV(block, I1, CPR232(RTREG)); // mov i1,<cpr2_rt>
UML_CALLH(block, *m_write32[m_core->mode >> 1]); // callh write32
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x3e: /* SDC2 - MIPS II */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
UML_DMOV(block, I1, CPR264(RTREG)); // dmov i1,<cpr2_rt>
UML_CALLH(block, *m_write64[m_core->mode >> 1]); // callh write64
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
/* ----- effective no-ops ----- */
case 0x2f: /* CACHE - MIPS II */
case 0x33: /* PREF - MIPS IV */
- return TRUE;
+ return true;
/* ----- coprocessor instructions ----- */
@@ -1859,18 +1859,18 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
return generate_cop1_fr0(block, compiler, desc);
else
return generate_cop1_fr1(block, compiler, desc);
- return FALSE;
+ return false;
case 0x13: /* COP1X - MIPS IV */
if ((m_core->mode & 1) == 0)
return generate_cop1x_fr0(block, compiler, desc);
else
return generate_cop1x_fr1(block, compiler, desc);
- return FALSE;
+ return false;
case 0x12: /* COP2 - MIPS I */
UML_EXH(block, *m_exception[EXCEPTION_INVALIDOP], 0);// exh invalidop,0
- return TRUE;
+ return true;
/* ----- unimplemented/illegal instructions ----- */
@@ -1878,7 +1878,7 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
// default: /* ??? */ invalid_instruction(op); break;
}
- return FALSE;
+ return false;
}
@@ -1887,7 +1887,7 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
'SPECIAL' group
-------------------------------------------------*/
-int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool mips3_device::generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
uint8_t opswitch = op & 63;
@@ -1902,7 +1902,7 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
UML_SHL(block, I0, R32(RTREG), SHIFT); // shl i0,<rtreg>,<shift>
UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword
}
- return TRUE;
+ return true;
case 0x02: /* SRL - MIPS I */
if (RDREG != 0)
@@ -1910,7 +1910,7 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
UML_SHR(block, I0, R32(RTREG), SHIFT); // shr i0,<rtreg>,<shift>
UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword
}
- return TRUE;
+ return true;
case 0x03: /* SRA - MIPS I */
if (RDREG != 0)
@@ -1918,7 +1918,7 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
UML_SAR(block, I0, R32(RTREG), SHIFT); // sar i0,<rtreg>,<shift>
UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword
}
- return TRUE;
+ return true;
case 0x04: /* SLLV - MIPS I */
if (RDREG != 0)
@@ -1926,7 +1926,7 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
UML_SHL(block, I0, R32(RTREG), R32(RSREG)); // shl i0,<rtreg>,<rsreg>
UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword
}
- return TRUE;
+ return true;
case 0x06: /* SRLV - MIPS I */
if (RDREG != 0)
@@ -1934,7 +1934,7 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
UML_SHR(block, I0, R32(RTREG), R32(RSREG)); // shr i0,<rtreg>,<rsreg>
UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword
}
- return TRUE;
+ return true;
case 0x07: /* SRAV - MIPS I */
if (RDREG != 0)
@@ -1942,52 +1942,52 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
UML_SAR(block, I0, R32(RTREG), R32(RSREG)); // sar i0,<rtreg>,<rsreg>
UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword
}
- return TRUE;
+ return true;
case 0x38: /* DSLL - MIPS III */
if (RDREG != 0)
UML_DSHL(block, R64(RDREG), R64(RTREG), SHIFT); // dshl <rdreg>,<rtreg>,<shift>
- return TRUE;
+ return true;
case 0x3a: /* DSRL - MIPS III */
if (RDREG != 0)
UML_DSHR(block, R64(RDREG), R64(RTREG), SHIFT); // dshr <rdreg>,<rtreg>,<shift>
- return TRUE;
+ return true;
case 0x3b: /* DSRA - MIPS III */
if (RDREG != 0)
UML_DSAR(block, R64(RDREG), R64(RTREG), SHIFT); // dsar <rdreg>,<rtreg>,<shift>
- return TRUE;
+ return true;
case 0x3c: /* DSLL32 - MIPS III */
if (RDREG != 0)
UML_DSHL(block, R64(RDREG), R64(RTREG), SHIFT + 32); // dshl <rdreg>,<rtreg>,<shift>+32
- return TRUE;
+ return true;
case 0x3e: /* DSRL32 - MIPS III */
if (RDREG != 0)
UML_DSHR(block, R64(RDREG), R64(RTREG), SHIFT + 32); // dshr <rdreg>,<rtreg>,<shift>+32
- return TRUE;
+ return true;
case 0x3f: /* DSRA32 - MIPS III */
if (RDREG != 0)
UML_DSAR(block, R64(RDREG), R64(RTREG), SHIFT + 32); // dsar <rdreg>,<rtreg>,<shift>+32
- return TRUE;
+ return true;
case 0x14: /* DSLLV - MIPS III */
if (RDREG != 0)
UML_DSHL(block, R64(RDREG), R64(RTREG), R64(RSREG)); // dshl <rdreg>,<rtreg>,<rsreg>
- return TRUE;
+ return true;
case 0x16: /* DSRLV - MIPS III */
if (RDREG != 0)
UML_DSHR(block, R64(RDREG), R64(RTREG), R64(RSREG)); // dshr <rdreg>,<rtreg>,<rsreg>
- return TRUE;
+ return true;
case 0x17: /* DSRAV - MIPS III */
if (RDREG != 0)
UML_DSAR(block, R64(RDREG), R64(RTREG), R64(RSREG)); // dsar <rdreg>,<rtreg>,<rsreg>
- return TRUE;
+ return true;
/* ----- basic arithmetic ----- */
@@ -2006,7 +2006,7 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword
}
- return TRUE;
+ return true;
case 0x21: /* ADDU - MIPS I */
if (RDREG != 0)
@@ -2014,7 +2014,7 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword
}
- return TRUE;
+ return true;
case 0x2c: /* DADD - MIPS III */
if (m_drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
@@ -2027,12 +2027,12 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
}
else if (RDREG != 0)
UML_DADD(block, R64(RDREG), R64(RSREG), R64(RTREG)); // dadd <rdreg>,<rsreg>,<rtreg>
- return TRUE;
+ return true;
case 0x2d: /* DADDU - MIPS III */
if (RDREG != 0)
UML_DADD(block, R64(RDREG), R64(RSREG), R64(RTREG)); // dadd <rdreg>,<rsreg>,<rtreg>
- return TRUE;
+ return true;
case 0x22: /* SUB - MIPS I */
if (m_drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
@@ -2048,7 +2048,7 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
UML_SUB(block, I0, R32(RSREG), R32(RTREG)); // sub i0,<rsreg>,<rtreg>
UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword
}
- return TRUE;
+ return true;
case 0x23: /* SUBU - MIPS I */
if (RDREG != 0)
@@ -2056,7 +2056,7 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
UML_SUB(block, I0, R32(RSREG), R32(RTREG)); // sub i0,<rsreg>,<rtreg>
UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword
}
- return TRUE;
+ return true;
case 0x2e: /* DSUB - MIPS III */
if (m_drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
@@ -2069,52 +2069,52 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
}
else if (RDREG != 0)
UML_DSUB(block, R64(RDREG), R64(RSREG), R64(RTREG)); // dsub <rdreg>,<rsreg>,<rtreg>
- return TRUE;
+ return true;
case 0x2f: /* DSUBU - MIPS III */
if (RDREG != 0)
UML_DSUB(block, R64(RDREG), R64(RSREG), R64(RTREG)); // dsub <rdreg>,<rsreg>,<rtreg>
- return TRUE;
+ return true;
case 0x18: /* MULT - MIPS I */
UML_MULS(block, I0, I1, R32(RSREG), R32(RTREG)); // muls i0,i1,<rsreg>,<rtreg>
UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword
UML_DSEXT(block, HI64, I1, SIZE_DWORD); // dsext hi,i1,dword
- return TRUE;
+ return true;
case 0x19: /* MULTU - MIPS I */
UML_MULU(block, I0, I1, R32(RSREG), R32(RTREG)); // mulu i0,i1,<rsreg>,<rtreg>
UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword
UML_DSEXT(block, HI64, I1, SIZE_DWORD); // dsext hi,i1,dword
- return TRUE;
+ return true;
case 0x1c: /* DMULT - MIPS III */
UML_DMULS(block, LO64, HI64, R64(RSREG), R64(RTREG));
- return TRUE;
+ return true;
case 0x1d: /* DMULTU - MIPS III */
UML_DMULU(block, LO64, HI64, R64(RSREG), R64(RTREG));
- return TRUE;
+ return true;
case 0x1a: /* DIV - MIPS I */
UML_DIVS(block, I0, I1, R32(RSREG), R32(RTREG)); // divs i0,i1,<rsreg>,<rtreg>
UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword
UML_DSEXT(block, HI64, I1, SIZE_DWORD); // dsext hi,i1,dword
- return TRUE;
+ return true;
case 0x1b: /* DIVU - MIPS I */
UML_DIVU(block, I0, I1, R32(RSREG), R32(RTREG)); // divu i0,i1,<rsreg>,<rtreg>
UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword
UML_DSEXT(block, HI64, I1, SIZE_DWORD); // dsext hi,i1,dword
- return TRUE;
+ return true;
case 0x1e: /* DDIV - MIPS III */
UML_DDIVS(block, LO64, HI64, R64(RSREG), R64(RTREG)); // ddivs lo,hi,<rsreg>,<rtreg>
- return TRUE;
+ return true;
case 0x1f: /* DDIVU - MIPS III */
UML_DDIVU(block, LO64, HI64, R64(RSREG), R64(RTREG)); // ddivu lo,hi,<rsreg>,<rtreg>
- return TRUE;
+ return true;
/* ----- basic logical ops ----- */
@@ -2122,17 +2122,17 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
case 0x24: /* AND - MIPS I */
if (RDREG != 0)
UML_DAND(block, R64(RDREG), R64(RSREG), R64(RTREG)); // dand <rdreg>,<rsreg>,<rtreg>
- return TRUE;
+ return true;
case 0x25: /* OR - MIPS I */
if (RDREG != 0)
UML_DOR(block, R64(RDREG), R64(RSREG), R64(RTREG)); // dor <rdreg>,<rsreg>,<rtreg>
- return TRUE;
+ return true;
case 0x26: /* XOR - MIPS I */
if (RDREG != 0)
UML_DXOR(block, R64(RDREG), R64(RSREG), R64(RTREG)); // dxor <rdreg>,<rsreg>,<rtreg>
- return TRUE;
+ return true;
case 0x27: /* NOR - MIPS I */
if (RDREG != 0)
@@ -2140,7 +2140,7 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
UML_DOR(block, I0, R64(RSREG), R64(RTREG)); // dor i0,<rsreg>,<rtreg>
UML_DXOR(block, R64(RDREG), I0, (uint64_t)~0); // dxor <rdreg>,i0,~0
}
- return TRUE;
+ return true;
/* ----- basic comparisons ----- */
@@ -2151,7 +2151,7 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg>
UML_DSETc(block, COND_L, R64(RDREG)); // dset <rdreg>,l
}
- return TRUE;
+ return true;
case 0x2b: /* SLTU - MIPS I */
if (RDREG != 0)
@@ -2159,7 +2159,7 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg>
UML_DSETc(block, COND_B, R64(RDREG)); // dset <rdreg>,b
}
- return TRUE;
+ return true;
/* ----- conditional traps ----- */
@@ -2167,32 +2167,32 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
case 0x30: /* TGE - MIPS II */
UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg>
UML_EXHc(block, COND_GE, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,GE
- return TRUE;
+ return true;
case 0x31: /* TGEU - MIPS II */
UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg>
UML_EXHc(block, COND_AE, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,AE
- return TRUE;
+ return true;
case 0x32: /* TLT - MIPS II */
UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg>
UML_EXHc(block, COND_L, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,LT
- return TRUE;
+ return true;
case 0x33: /* TLTU - MIPS II */
UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg>
UML_EXHc(block, COND_B, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,B
- return TRUE;
+ return true;
case 0x34: /* TEQ - MIPS II */
UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg>
UML_EXHc(block, COND_E, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,E
- return TRUE;
+ return true;
case 0x36: /* TNE - MIPS II */
UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg>
UML_EXHc(block, COND_NE, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,NE
- return TRUE;
+ return true;
/* ----- conditional moves ----- */
@@ -2203,7 +2203,7 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
UML_DCMP(block, R64(RTREG), 0); // dcmp <rtreg>,0
UML_DMOVc(block, COND_Z, R64(RDREG), R64(RSREG)); // dmov <rdreg>,<rsreg>,Z
}
- return TRUE;
+ return true;
case 0x0b: /* MOVN - MIPS IV */
if (RDREG != 0)
@@ -2211,7 +2211,7 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
UML_DCMP(block, R64(RTREG), 0); // dcmp <rtreg>,0
UML_DMOVc(block, COND_NZ, R64(RDREG), R64(RSREG)); // dmov <rdreg>,<rsreg>,NZ
}
- return TRUE;
+ return true;
case 0x01: /* MOVF/MOVT - MIPS IV */
if (RDREG != 0)
@@ -2220,35 +2220,35 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
UML_DMOVc(block, ((op >> 16) & 1) ? COND_NZ : COND_Z, R64(RDREG), R64(RSREG));
// dmov <rdreg>,<rsreg>,NZ/Z
}
- return TRUE;
+ return true;
/* ----- jumps and branches ----- */
case 0x08: /* JR - MIPS I */
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
- return TRUE;
+ return true;
case 0x09: /* JALR - MIPS I */
generate_delay_slot_and_branch(block, compiler, desc, RDREG); // <next instruction + hashjmp>
- return TRUE;
+ return true;
/* ----- system calls ----- */
case 0x0c: /* SYSCALL - MIPS I */
UML_EXH(block, *m_exception[EXCEPTION_SYSCALL], 0); // exh syscall,0
- return TRUE;
+ return true;
case 0x0d: /* BREAK - MIPS I */
UML_EXH(block, *m_exception[EXCEPTION_BREAK], 0); // exh break,0
- return TRUE;
+ return true;
/* ----- effective no-ops ----- */
case 0x0f: /* SYNC - MIPS II */
- return TRUE;
+ return true;
/* ----- hi/lo register access ----- */
@@ -2256,22 +2256,22 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
case 0x10: /* MFHI - MIPS I */
if (RDREG != 0)
UML_DMOV(block, R64(RDREG), HI64); // dmov <rdreg>,hi
- return TRUE;
+ return true;
case 0x11: /* MTHI - MIPS I */
UML_DMOV(block, HI64, R64(RSREG)); // dmov hi,<rsreg>
- return TRUE;
+ return true;
case 0x12: /* MFLO - MIPS I */
if (RDREG != 0)
UML_DMOV(block, R64(RDREG), LO64); // dmov <rdreg>,lo
- return TRUE;
+ return true;
case 0x13: /* MTLO - MIPS I */
UML_DMOV(block, LO64, R64(RSREG)); // dmov lo,<rsreg>
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
@@ -2280,7 +2280,7 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
'REGIMM' group
-------------------------------------------------*/
-int mips3_device::generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool mips3_device::generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
uint8_t opswitch = RTREG;
@@ -2304,7 +2304,7 @@ int mips3_device::generate_regimm(drcuml_block *block, compiler_state *compiler,
// <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
}
- return TRUE;
+ return true;
case 0x01: /* BGEZ */
case 0x03: /* BGEZL */
@@ -2326,39 +2326,39 @@ int mips3_device::generate_regimm(drcuml_block *block, compiler_state *compiler,
{
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
}
- return TRUE;
+ return true;
case 0x08: /* TGEI */
UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL
UML_EXHc(block, COND_GE, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,GE
- return TRUE;
+ return true;
case 0x09: /* TGEIU */
UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL
UML_EXHc(block, COND_AE, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,AE
- return TRUE;
+ return true;
case 0x0a: /* TLTI */
UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL
UML_EXHc(block, COND_L, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,L
- return TRUE;
+ return true;
case 0x0b: /* TLTIU */
UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL
UML_EXHc(block, COND_B, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,B
- return TRUE;
+ return true;
case 0x0c: /* TEQI */
UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL
UML_EXHc(block, COND_E, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,E
- return TRUE;
+ return true;
case 0x0e: /* TNEI */
UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL
UML_EXHc(block, COND_NE, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,NE
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
@@ -2367,14 +2367,14 @@ int mips3_device::generate_regimm(drcuml_block *block, compiler_state *compiler,
specific group
-------------------------------------------------*/
-int mips3_device::generate_idt(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool mips3_device::generate_idt(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
uint8_t opswitch = op & 0x1f;
/* only enabled on IDT processors */
if (m_flavor != MIPS3_TYPE_R4650)
- return FALSE;
+ return false;
switch (opswitch)
{
@@ -2387,7 +2387,7 @@ int mips3_device::generate_idt(drcuml_block *block, compiler_state *compiler, co
UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword
UML_DSEXT(block, HI64, I1, SIZE_DWORD); // dsext hi,i1,dword
}
- return TRUE;
+ return true;
case 1: /* MADU */
if (RSREG != 0 && RTREG != 0)
@@ -2398,7 +2398,7 @@ int mips3_device::generate_idt(drcuml_block *block, compiler_state *compiler, co
UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword
UML_DSEXT(block, HI64, I1, SIZE_DWORD); // dsext hi,i1,dword
}
- return TRUE;
+ return true;
case 2: /* MUL */
if (RDREG != 0)
@@ -2406,9 +2406,9 @@ int mips3_device::generate_idt(drcuml_block *block, compiler_state *compiler, co
UML_MULS(block, I0, I0, R32(RSREG), R32(RTREG)); // muls i0,i0,rsreg,rtreg
UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext rdreg,i0,dword
}
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
@@ -2417,7 +2417,7 @@ int mips3_device::generate_idt(drcuml_block *block, compiler_state *compiler, co
handle special COP0 registers
-------------------------------------------------*/
-int mips3_device::generate_set_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint8_t reg)
+bool mips3_device::generate_set_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint8_t reg)
{
int in_delay_slot = ((desc->flags & OPFLAG_IN_DELAY_SLOT) != 0);
code_label link;
@@ -2426,10 +2426,10 @@ int mips3_device::generate_set_cop0_reg(drcuml_block *block, compiler_state *com
{
case COP0_Cause:
UML_ROLINS(block, CPR032(COP0_Cause), I0, 0, ~0xfc00); // rolins [Cause],i0,0,~0xfc00
- compiler->checksoftints = TRUE;
+ compiler->checksoftints = true;
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case COP0_Status:
generate_update_cycles(block, compiler, desc->pc, !in_delay_slot); // <subtract cycles>
@@ -2439,10 +2439,10 @@ int mips3_device::generate_set_cop0_reg(drcuml_block *block, compiler_state *com
UML_XOR(block, I0, I0, I1); // xor i0,i0,i1
UML_TEST(block, I0, 0x8000); // test i0,0x8000
UML_CALLCc(block, COND_NZ, cfunc_mips3com_update_cycle_counting, this); // callc mips3com_update_cycle_counting,mips.core,NZ
- compiler->checkints = TRUE;
+ compiler->checkints = true;
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case COP0_Count:
generate_update_cycles(block, compiler, desc->pc, !in_delay_slot); // <subtract cycles>
@@ -2453,7 +2453,7 @@ int mips3_device::generate_set_cop0_reg(drcuml_block *block, compiler_state *com
UML_DSUB(block, mem(&m_core->count_zero_time), mem(&m_core->numcycles), I0);
// dsub [count_zero_time],[m_numcycles],i0
UML_CALLC(block, cfunc_mips3com_update_cycle_counting, this); // callc mips3com_update_cycle_counting,mips.core
- return TRUE;
+ return true;
case COP0_Compare:
UML_MOV(block, mem(&m_core->compare_armed), 1); // mov [compare_armed],1
@@ -2461,14 +2461,14 @@ int mips3_device::generate_set_cop0_reg(drcuml_block *block, compiler_state *com
UML_MOV(block, CPR032(COP0_Compare), I0); // mov [Compare],i0
UML_AND(block, CPR032(COP0_Cause), CPR032(COP0_Cause), ~0x8000); // and [Cause],[Cause],~0x8000
UML_CALLC(block, cfunc_mips3com_update_cycle_counting, this); // callc mips3com_update_cycle_counting,mips.core
- return TRUE;
+ return true;
case COP0_PRId:
- return TRUE;
+ return true;
case COP0_Config:
UML_ROLINS(block, CPR032(COP0_Config), I0, 0, 0x0007); // rolins [Config],i0,0,0x0007
- return TRUE;
+ return true;
case COP0_EntryHi:
UML_XOR(block, I1, I0, CPR032(reg)); // xor i1,i0,cpr0[reg]
@@ -2477,11 +2477,11 @@ int mips3_device::generate_set_cop0_reg(drcuml_block *block, compiler_state *com
UML_JMPc(block, COND_Z, link = compiler->labelnum++); // jmp link,z
UML_CALLC(block, cfunc_mips3com_asid_changed, this); // callc mips3com_asid_changed
UML_LABEL(block, link); // link:
- return TRUE;
+ return true;
default:
UML_MOV(block, CPR032(reg), I0); // mov cpr0[reg],i0
- return TRUE;
+ return true;
}
}
@@ -2491,23 +2491,23 @@ int mips3_device::generate_set_cop0_reg(drcuml_block *block, compiler_state *com
read special COP0 registers
-------------------------------------------------*/
-int mips3_device::generate_get_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint8_t reg)
+bool mips3_device::generate_get_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint8_t reg)
{
code_label link1, link2;
switch (reg)
{
case COP0_Count:
- generate_update_cycles(block, compiler, desc->pc, FALSE); // <subtract cycles>
+ generate_update_cycles(block, compiler, desc->pc, false); // <subtract cycles>
UML_CALLC(block, cfunc_get_cycles, this); // callc cfunc_get_cycles,mips3
UML_DSUB(block, I0, mem(&m_core->numcycles), mem(&m_core->count_zero_time));
// dsub i0,[numcycles],[count_zero_time]
UML_DSHR(block, I0, I0, 1); // dshr i0,i0,1
UML_DSEXT(block, I0, I0, SIZE_DWORD); // dsext i0,i0,dword
- return TRUE;
+ return true;
case COP0_Random:
- generate_update_cycles(block, compiler, desc->pc, FALSE); // <subtract cycles>
+ generate_update_cycles(block, compiler, desc->pc, false); // <subtract cycles>
UML_CALLC(block, cfunc_get_cycles, this); // callc cfunc_get_cycles,mips3
UML_DSUB(block, I0, mem(&m_core->numcycles), mem(&m_core->count_zero_time));
// dsub i0,[numcycles],[count_zero_time]
@@ -2522,11 +2522,11 @@ int mips3_device::generate_get_cop0_reg(drcuml_block *block, compiler_state *com
UML_LABEL(block, link1); // link1:
UML_DMOV(block, I0, 47); // dmov i0,47
UML_LABEL(block, link2); // link2:
- return TRUE;
+ return true;
default:
UML_DSEXT(block, I0, CPR032(reg), SIZE_DWORD); // dsext i0,cpr0[reg],dword
- return TRUE;
+ return true;
}
}
@@ -2557,7 +2557,7 @@ void mips3_device::check_cop0_access(drcuml_block *block)
generate_cop0 - compile COP0 opcodes
-------------------------------------------------*/
-int mips3_device::generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool mips3_device::generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
uint8_t opswitch = RSREG;
@@ -2578,7 +2578,7 @@ int mips3_device::generate_cop0(drcuml_block *block, compiler_state *compiler, c
generate_get_cop0_reg(block, compiler, desc, RDREG); // <get cop0 reg>
UML_DSEXT(block, R64(RTREG), I0, SIZE_DWORD); // dsext <rtreg>,i0,dword
}
- return TRUE;
+ return true;
case 0x01: /* DMFCz */
if (RTREG != 0)
@@ -2586,26 +2586,26 @@ int mips3_device::generate_cop0(drcuml_block *block, compiler_state *compiler, c
generate_get_cop0_reg(block, compiler, desc, RDREG); // <get cop0 reg>
UML_DMOV(block, R64(RTREG), I0); // dmov <rtreg>,i0
}
- return TRUE;
+ return true;
case 0x02: /* CFCz */
if (RTREG != 0)
UML_DSEXT(block, R64(RTREG), CCR032(RDREG), SIZE_DWORD); // dsext <rtreg>,ccr0[rdreg],dword
- return TRUE;
+ return true;
case 0x04: /* MTCz */
UML_DSEXT(block, I0, R32(RTREG), SIZE_DWORD); // dsext i0,<rtreg>,dword
generate_set_cop0_reg(block, compiler, desc, RDREG); // <set cop0 reg>
- return TRUE;
+ return true;
case 0x05: /* DMTCz */
UML_DMOV(block, I0, R64(RTREG)); // dmov i0,<rtreg>
generate_set_cop0_reg(block, compiler, desc, RDREG); // <set cop0 reg>
- return TRUE;
+ return true;
case 0x06: /* CTCz */
UML_DSEXT(block, CCR064(RDREG), R32(RTREG), SIZE_DWORD); // dsext ccr0[rdreg],<rtreg>,dword
- return TRUE;
+ return true;
case 0x10:
case 0x11:
@@ -2627,19 +2627,19 @@ int mips3_device::generate_cop0(drcuml_block *block, compiler_state *compiler, c
{
case 0x01: /* TLBR */
UML_CALLC(block, cfunc_mips3com_tlbr, this); // callc mips3com_tlbr,mips3
- return TRUE;
+ return true;
case 0x02: /* TLBWI */
UML_CALLC(block, cfunc_mips3com_tlbwi, this); // callc mips3com_tlbwi,mips3
- return TRUE;
+ return true;
case 0x06: /* TLBWR */
UML_CALLC(block, cfunc_mips3com_tlbwr, this); // callc mips3com_tlbwr,mips3
- return TRUE;
+ return true;
case 0x08: /* TLBP */
UML_CALLC(block, cfunc_mips3com_tlbp, this); // callc mips3com_tlbp,mips3
- return TRUE;
+ return true;
case 0x18: /* ERET */
UML_MOV(block, mem(&m_core->llbit), 0); // mov [llbit],0
@@ -2649,28 +2649,28 @@ int mips3_device::generate_cop0(drcuml_block *block, compiler_state *compiler, c
UML_AND(block, I0, I0, ~SR_EXL); // and i0,i0,~SR_EXL
UML_MOV(block, CPR032(COP0_Status), I0); // mov [Status],i0
generate_update_mode(block);
- compiler->checkints = TRUE;
- generate_update_cycles(block, compiler, CPR032(COP0_EPC), TRUE);// <subtract cycles>
+ compiler->checkints = true;
+ generate_update_cycles(block, compiler, CPR032(COP0_EPC), true);// <subtract cycles>
UML_HASHJMP(block, mem(&m_core->mode), CPR032(COP0_EPC), *m_nocode);
// hashjmp <mode>,[EPC],nocode
UML_LABEL(block, skip); // skip:
UML_AND(block, I0, I0, ~SR_ERL); // and i0,i0,~SR_ERL
UML_MOV(block, CPR032(COP0_Status), I0); // mov [Status],i0
generate_update_mode(block);
- compiler->checkints = TRUE;
- generate_update_cycles(block, compiler, CPR032(COP0_ErrorPC), TRUE);
+ compiler->checkints = true;
+ generate_update_cycles(block, compiler, CPR032(COP0_ErrorPC), true);
// <subtract cycles>
UML_HASHJMP(block, mem(&m_core->mode), CPR032(COP0_ErrorPC), *m_nocode);
// hashjmp <mode>,[EPC],nocode
- return TRUE;
+ return true;
case 0x20: /* WAIT */
- return TRUE;
+ return true;
}
break;
}
- return FALSE;
+ return false;
}
@@ -2761,7 +2761,7 @@ void mips3_device::generate_set_cop1_reg64_i2d(drcuml_block *block, compiler_sta
generate_cop1_fr0 - compile COP1 opcodes in FR0 mode
---------------------------------------------------------*/
-int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
code_label skip;
@@ -2776,7 +2776,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
{
UML_DSEXT(block, R64(RTREG), FPR32_FR0(RDREG), SIZE_DWORD); // dsext <rtreg>,fpr[rdreg],dword
}
- return TRUE;
+ return true;
case 0x01: /* DMFC1 - MIPS III */
if (RTREG != 0)
@@ -2784,21 +2784,21 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
generate_get_cop1_reg64_d2i(block, compiler, desc, RDREG, I0);
UML_DMOV(block, R64(RTREG), I0);
}
- return TRUE;
+ return true;
case 0x02: /* CFC1 - MIPS I */
if (RTREG != 0)
UML_DSEXT(block, R64(RTREG), CCR132(RDREG), SIZE_DWORD); // dsext <rtreg>,ccr132[rdreg],dword
- return TRUE;
+ return true;
case 0x04: /* MTC1 - MIPS I */
UML_MOV(block, FPR32_FR0(RDREG), R32(RTREG)); // mov fpr[rdreg],<rtreg>
- return TRUE;
+ return true;
case 0x05: /* DMTC1 - MIPS III */
UML_DMOV(block, I0, R64(RTREG));
generate_set_cop1_reg64_i2d(block, compiler, desc, RDREG, I0);
- return TRUE;
+ return true;
case 0x06: /* CTC1 - MIPS I */
if (RDREG != 31)
@@ -2816,7 +2816,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_SETFMOD(block, I0); // setfmod i0
UML_LABEL(block, skip); // skip:
}
- return TRUE;
+ return true;
case 0x08: /* BC */
switch ((op >> 16) & 3)
@@ -2827,7 +2827,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_JMPc(block, COND_NZ, skip = compiler->labelnum++); // jmp skip,NZ
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
- return TRUE;
+ return true;
case 0x01: /* BCzT - MIPS I */
case 0x03: /* BCzTL - MIPS II */
@@ -2835,7 +2835,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
- return TRUE;
+ return true;
}
break;
@@ -2854,7 +2854,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_FDADD(block, F2, F0, F1); // fdadd F2,F0,F1
generate_set_cop1_reg64(block, compiler, desc, FDREG, F2); // dmov <fdreg>,F2
}
- return TRUE;
+ return true;
case 0x01:
if (IS_SINGLE(op)) /* SUB.S - MIPS I */
@@ -2868,7 +2868,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_FDSUB(block, F2, F0, F1); // fdsub F2,F0,F1
generate_set_cop1_reg64(block, compiler, desc, FDREG, F2); // dmov <fdreg>,F2
}
- return TRUE;
+ return true;
case 0x02:
if (IS_SINGLE(op)) /* MUL.S - MIPS I */
@@ -2882,7 +2882,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_FDMUL(block, F2, F0, F1); // fdmul F2,F0,F1
generate_set_cop1_reg64(block, compiler, desc, FDREG, F2); // dmov <fdreg>,F2
}
- return TRUE;
+ return true;
case 0x03:
if (IS_SINGLE(op)) /* DIV.S - MIPS I */
@@ -2896,7 +2896,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_FDDIV(block, F2, F0, F1); // fddiv F2,F0,F1
generate_set_cop1_reg64(block, compiler, desc, FDREG, F2); // dmov <fdreg>,F2
}
- return TRUE;
+ return true;
case 0x04:
if (IS_SINGLE(op)) /* SQRT.S - MIPS II */
@@ -2909,7 +2909,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_FDSQRT(block, F0, F0); // fdsqrt F0,F0
generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,F0
}
- return TRUE;
+ return true;
case 0x05:
if (IS_SINGLE(op)) /* ABS.S - MIPS I */
@@ -2922,7 +2922,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_FDABS(block, F0, F0); // fdabs F0,F0
generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,F0
}
- return TRUE;
+ return true;
case 0x06:
if (IS_SINGLE(op)) /* MOV.S - MIPS I */
@@ -2934,7 +2934,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,F0
}
- return TRUE;
+ return true;
case 0x07:
if (IS_SINGLE(op)) /* NEG.S - MIPS I */
@@ -2951,7 +2951,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_DMOVc(block, COND_E, F1, U64(0x8000000000000000)); // dmov F1,-0.0,e
generate_set_cop1_reg64(block, compiler, desc, FDREG, F1); // dmov <fdreg>,F1
}
- return TRUE;
+ return true;
case 0x08:
if (IS_SINGLE(op)) /* ROUND.L.S - MIPS III */
@@ -2965,7 +2965,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
UML_ICOPYFD(block, I0, F0); // icopyfd i0,f0
generate_set_cop1_reg64_i2d(block, compiler, desc, FDREG, I0); // dmov <fdreg>,f0
- return TRUE;
+ return true;
case 0x09:
if (IS_SINGLE(op)) /* TRUNC.L.S - MIPS III */
@@ -2979,7 +2979,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
UML_ICOPYFD(block, I0, F0); // icopyfd i0,f0
generate_set_cop1_reg64_i2d(block, compiler, desc, FDREG, I0); // dmov <fdreg>,i0
- return TRUE;
+ return true;
case 0x0a:
if (IS_SINGLE(op)) /* CEIL.L.S - MIPS III */
@@ -2993,7 +2993,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
UML_ICOPYFD(block, I0, F0); // icopyfd i0,f0
generate_set_cop1_reg64(block, compiler, desc, FDREG, I0); // dmov <fdreg>,f0
- return TRUE;
+ return true;
case 0x0b:
if (IS_SINGLE(op)) /* FLOOR.L.S - MIPS III */
@@ -3007,7 +3007,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
UML_ICOPYFD(block, I0, F0); // icopyfd i0,f0
generate_set_cop1_reg64(block, compiler, desc, FDREG, I0); // dmov <fdreg>,f0
- return TRUE;
+ return true;
case 0x0c:
if (IS_SINGLE(op)) /* ROUND.W.S - MIPS II */
@@ -3019,7 +3019,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
UML_FDTOINT(block, FDVALS_FR0, F0, SIZE_DWORD, ROUND_ROUND); // fdtoint <fdreg>,F0,dword,round
}
- return TRUE;
+ return true;
case 0x0d:
if (IS_SINGLE(op)) /* TRUNC.W.S - MIPS II */
@@ -3031,7 +3031,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
UML_FDTOINT(block, FDVALS_FR0, F0, SIZE_DWORD, ROUND_TRUNC); // fdtoint <fdreg>,F0,dword,trunc
}
- return TRUE;
+ return true;
case 0x0e:
if (IS_SINGLE(op)) /* CEIL.W.S - MIPS II */
@@ -3043,7 +3043,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
UML_FDTOINT(block, FDVALS_FR0, F0, SIZE_DWORD, ROUND_CEIL); // fdtoint <fdreg>,F0,dword,ceil
}
- return TRUE;
+ return true;
case 0x0f:
if (IS_SINGLE(op)) /* FLOOR.W.S - MIPS II */
@@ -3055,7 +3055,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
UML_FDTOINT(block, FDVALS_FR0, F0, SIZE_DWORD, ROUND_FLOOR); // fdtoint <fdreg>,F0,dword,floor
}
- return TRUE;
+ return true;
case 0x11:
@@ -3076,7 +3076,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_LABEL(block, skip);
generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,F0
}
- return TRUE;
+ return true;
case 0x12:
UML_DCMP(block, R64(RTREG), 0); // dcmp <rtreg>,0
@@ -3092,7 +3092,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_FDMOVc(block, COND_NZ, F2, F1); // fdmov f2,<fdreg>,NZ
generate_set_cop1_reg64(block, compiler, desc, FDREG, F2); // dmov <fdreg>,f0
}
- return TRUE;
+ return true;
case 0x13:
UML_DCMP(block, R64(RTREG), 0); // dcmp <rtreg>,0
@@ -3108,7 +3108,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_FDMOVc(block, COND_Z, F2, F1); // fdmov f2,<fdreg>,Z
generate_set_cop1_reg64(block, compiler, desc, FDREG, F2); // dmov <fdreg>,f2
}
- return TRUE;
+ return true;
case 0x15:
if (IS_SINGLE(op)) /* RECIP.S - MIPS IV */
@@ -3121,7 +3121,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_FDRECIP(block, F0, F0); // fdrecip f0,<fsreg>
generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,f0
}
- return TRUE;
+ return true;
case 0x16:
if (IS_SINGLE(op)) /* RSQRT.S - MIPS IV */
@@ -3134,7 +3134,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_FDRSQRT(block, F0, F0); // fdrsqrt f0,<fsreg>
generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,f0
}
- return TRUE;
+ return true;
case 0x20:
if (IS_INTEGRAL(op))
@@ -3154,7 +3154,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
UML_FSFRFLT(block, FDVALS_FR0, F0, SIZE_QWORD); // fsfrflt <fdreg>,f0,qword
}
- return TRUE;
+ return true;
case 0x21:
if (IS_INTEGRAL(op))
@@ -3174,7 +3174,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_FDFRFLT(block, F0, FSVALS_FR0, SIZE_DWORD); // fdfrflt f0,<fsreg>,dword
}
generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,f0
- return TRUE;
+ return true;
case 0x24:
if (IS_SINGLE(op)) /* CVT.W.S - MIPS I */
@@ -3186,7 +3186,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
UML_FDTOINT(block, FDVALS_FR0, F0, SIZE_DWORD, ROUND_DEFAULT);// fdtoint <fdreg>,f0,dword,default
}
- return TRUE;
+ return true;
case 0x25:
if (IS_SINGLE(op)) /* CVT.L.S - MIPS I */
@@ -3200,12 +3200,12 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_FDTOINT(block, F0, F0, SIZE_QWORD, ROUND_DEFAULT); // fdtoint <fdreg>,<fsreg>,qword,default
generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,f0
}
- return TRUE;
+ return true;
case 0x30:
case 0x38: /* C.F.S/D - MIPS I */
UML_AND(block, CCR132(31), CCR132(31), ~FCCMASK(op >> 8)); // and ccr31,ccr31,~fccmask[op]
- return TRUE;
+ return true;
case 0x31:
case 0x39:
@@ -3222,7 +3222,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_SETc(block, COND_U, I0); // set i0,u
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8));
// rolins ccr31,i0,fccshift,fcc
- return TRUE;
+ return true;
case 0x32:
case 0x3a:
@@ -3241,7 +3241,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_AND(block, I0, I0, I1); // and i0,i0,i1
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8));
// rolins ccr31,i0,fccshift,fcc
- return TRUE;
+ return true;
case 0x33:
case 0x3b:
@@ -3260,7 +3260,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_OR(block, I0, I0, I1); // or i0,i0,i1
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8));
// rolins ccr31,i0,fccshift,fcc
- return TRUE;
+ return true;
case 0x34:
case 0x3c:
@@ -3279,7 +3279,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_AND(block, I0, I0, I1); // and i0,i0,i1
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8));
// rolins ccr31,i0,fccshift,fcc
- return TRUE;
+ return true;
case 0x35:
case 0x3d:
@@ -3298,7 +3298,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_OR(block, I0, I0, I1); // or i0,i0,i1
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8));
// rolins ccr31,i0,fccshift,fcc
- return TRUE;
+ return true;
case 0x36:
case 0x3e:
@@ -3317,7 +3317,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_AND(block, I0, I0, I1); // and i0,i0,i1
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8));
// rolins ccr31,i0,fccshift,fcc
- return TRUE;
+ return true;
case 0x37:
case 0x3f:
@@ -3336,18 +3336,18 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
UML_OR(block, I0, I0, I1); // or i0,i0,i1
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8));
// rolins ccr31,i0,fccshift,fcc
- return TRUE;
+ return true;
}
break;
}
- return FALSE;
+ return false;
}
/*-------------------------------------------------------
generate_cop1_fr1 - compile COP1 opcodes in FR1 mode
---------------------------------------------------------*/
-int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
code_label skip;
@@ -3362,7 +3362,7 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
{
UML_DSEXT(block, R64(RTREG), FPR32_FR0(RDREG), SIZE_DWORD); // dsext <rtreg>,fpr[rdreg],dword
}
- return TRUE;
+ return true;
case 0x01: /* DMFC1 - MIPS III */
if (RTREG != 0)
@@ -3370,21 +3370,21 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
generate_get_cop1_reg64_d2i(block, compiler, desc, RDREG, I0);
UML_DMOV(block, R64(RTREG), I0);
}
- return TRUE;
+ return true;
case 0x02: /* CFC1 - MIPS I */
if (RTREG != 0)
UML_DSEXT(block, R64(RTREG), CCR132(RDREG), SIZE_DWORD); // dsext <rtreg>,ccr132[rdreg],dword
- return TRUE;
+ return true;
case 0x04: /* MTC1 - MIPS I */
UML_MOV(block, FPR32_FR0(RDREG), R32(RTREG)); // mov fpr[rdreg],<rtreg>
- return TRUE;
+ return true;
case 0x05: /* DMTC1 - MIPS III */
UML_DMOV(block, I0, R64(RTREG));
generate_set_cop1_reg64_i2d(block, compiler, desc, RDREG, I0);
- return TRUE;
+ return true;
case 0x06: /* CTC1 - MIPS I */
if (RDREG != 31)
@@ -3402,7 +3402,7 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
UML_SETFMOD(block, I0); // setfmod i0
UML_LABEL(block, skip); // skip:
}
- return TRUE;
+ return true;
case 0x08: /* BC */
switch ((op >> 16) & 3)
@@ -3413,7 +3413,7 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
UML_JMPc(block, COND_NZ, skip = compiler->labelnum++); // jmp skip,NZ
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
- return TRUE;
+ return true;
case 0x01: /* BCzT - MIPS I */
case 0x03: /* BCzTL - MIPS II */
@@ -3421,7 +3421,7 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
- return TRUE;
+ return true;
}
break;
@@ -3433,49 +3433,49 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
UML_FSADD(block, FDVALS_FR1, FSVALS_FR1, FTVALS_FR1); // fsadd <fdreg>,<fsreg>,<ftreg>
else /* ADD.D - MIPS I */
UML_FDADD(block, FDVALD_FR1, FSVALD_FR1, FTVALD_FR1); // fdadd <fdreg>,<fsreg>,<ftreg>
- return TRUE;
+ return true;
case 0x01:
if (IS_SINGLE(op)) /* SUB.S - MIPS I */
UML_FSSUB(block, FDVALS_FR1, FSVALS_FR1, FTVALS_FR1); // fssub <fdreg>,<fsreg>,<ftreg>
else /* SUB.D - MIPS I */
UML_FDSUB(block, FDVALD_FR1, FSVALD_FR1, FTVALD_FR1); // fdsub <fdreg>,<fsreg>,<ftreg>
- return TRUE;
+ return true;
case 0x02:
if (IS_SINGLE(op)) /* MUL.S - MIPS I */
UML_FSMUL(block, FDVALS_FR1, FSVALS_FR1, FTVALS_FR1); // fsmul <fdreg>,<fsreg>,<ftreg>
else /* MUL.D - MIPS I */
UML_FDMUL(block, FDVALD_FR1, FSVALD_FR1, FTVALD_FR1); // fdmul <fdreg>,<fsreg>,<ftreg>
- return TRUE;
+ return true;
case 0x03:
if (IS_SINGLE(op)) /* DIV.S - MIPS I */
UML_FSDIV(block, FDVALS_FR1, FSVALS_FR1, FTVALS_FR1); // fsdiv <fdreg>,<fsreg>,<ftreg>
else /* DIV.D - MIPS I */
UML_FDDIV(block, FDVALD_FR1, FSVALD_FR1, FTVALD_FR1); // fddiv <fdreg>,<fsreg>,<ftreg>
- return TRUE;
+ return true;
case 0x04:
if (IS_SINGLE(op)) /* SQRT.S - MIPS II */
UML_FSSQRT(block, FDVALS_FR1, FSVALS_FR1); // fssqrt <fdreg>,<fsreg>
else /* SQRT.D - MIPS II */
UML_FDSQRT(block, FDVALD_FR1, FSVALD_FR1); // fdsqrt <fdreg>,<fsreg>
- return TRUE;
+ return true;
case 0x05:
if (IS_SINGLE(op)) /* ABS.S - MIPS I */
UML_FSABS(block, FDVALS_FR1, FSVALS_FR1); // fsabs <fdreg>,<fsreg>
else /* ABS.D - MIPS I */
UML_FDABS(block, FDVALD_FR1, FSVALD_FR1); // fdabs <fdreg>,<fsreg>
- return TRUE;
+ return true;
case 0x06:
if (IS_SINGLE(op)) /* MOV.S - MIPS I */
UML_FSMOV(block, FDVALS_FR1, FSVALS_FR1); // fsmov <fdreg>,<fsreg>
else /* MOV.D - MIPS I */
UML_FDMOV(block, FDVALD_FR1, FSVALD_FR1); // fdmov <fdreg>,<fsreg>
- return TRUE;
+ return true;
case 0x07:
if (IS_SINGLE(op)) /* NEG.S - MIPS I */
@@ -3490,63 +3490,63 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
UML_DCMP(block, FSVALD_FR1, 0); // dcmp <fsreg>,0.0
UML_DMOVc(block, COND_E, FDVALD_FR1, 0x8000000000000000L);// mov <fdreg>,-0.0,e
}
- return TRUE;
+ return true;
case 0x08:
if (IS_SINGLE(op)) /* ROUND.L.S - MIPS III */
UML_FSTOINT(block, FDVALD_FR1, FSVALS_FR1, SIZE_QWORD, ROUND_ROUND); // fstoint f0,<fsreg>,qword,round
else /* ROUND.L.D - MIPS III */
UML_FDTOINT(block, FDVALD_FR1, FSVALD_FR1, SIZE_QWORD, ROUND_ROUND); // fdtoint f0,f0,qword,round
- return TRUE;
+ return true;
case 0x09:
if (IS_SINGLE(op)) /* TRUNC.L.S - MIPS III */
UML_FSTOINT(block, FDVALD_FR1, FSVALS_FR1, SIZE_QWORD, ROUND_TRUNC); // fstoint f0,<fsreg>,qword,trunc
else /* TRUNC.L.D - MIPS III */
UML_FDTOINT(block, FDVALD_FR1, FSVALD_FR1, SIZE_QWORD, ROUND_TRUNC); // fdtoint f0,f0,qword,trunc
- return TRUE;
+ return true;
case 0x0a:
if (IS_SINGLE(op)) /* CEIL.L.S - MIPS III */
UML_FSTOINT(block, FDVALD_FR1, FSVALS_FR1, SIZE_QWORD, ROUND_CEIL); // fstoint f0,<fsreg>,qword,ceil
else /* CEIL.L.D - MIPS III */
UML_FDTOINT(block, FDVALD_FR1, FSVALD_FR1, SIZE_QWORD, ROUND_CEIL); // fdtoint f0,<fsreg>,qword,ceil
- return TRUE;
+ return true;
case 0x0b:
if (IS_SINGLE(op)) /* FLOOR.L.S - MIPS III */
UML_FSTOINT(block, FDVALD_FR1, FSVALS_FR1, SIZE_QWORD, ROUND_FLOOR); // fstoint f0,<fsreg>,qword,floor
else /* FLOOR.L.D - MIPS III */
UML_FDTOINT(block, FDVALD_FR1, FSVALD_FR1, SIZE_QWORD, ROUND_FLOOR); // fdtoint f0,<fsreg>,qword,floor
- return TRUE;
+ return true;
case 0x0c:
if (IS_SINGLE(op)) /* ROUND.W.S - MIPS II */
UML_FSTOINT(block, FDVALS_FR1, FSVALS_FR1, SIZE_DWORD, ROUND_ROUND); // fstoint <fdreg>,<fsreg>,dword,round
else /* ROUND.W.D - MIPS II */
UML_FDTOINT(block, FDVALS_FR1, FSVALD_FR1, SIZE_DWORD, ROUND_ROUND); // fdtoint <fdreg>,F0,dword,round
- return TRUE;
+ return true;
case 0x0d:
if (IS_SINGLE(op)) /* TRUNC.W.S - MIPS II */
UML_FSTOINT(block, FDVALS_FR1, FSVALS_FR1, SIZE_DWORD, ROUND_TRUNC);// fstoint <fdreg>,<fsreg>,dword,trunc
else /* TRUNC.W.D - MIPS II */
UML_FDTOINT(block, FDVALS_FR1, FSVALD_FR1, SIZE_DWORD, ROUND_TRUNC); // fdtoint <fdreg>,F0,dword,trunc
- return TRUE;
+ return true;
case 0x0e:
if (IS_SINGLE(op)) /* CEIL.W.S - MIPS II */
UML_FSTOINT(block, FDVALS_FR1, FSVALS_FR1, SIZE_DWORD, ROUND_CEIL);// fstoint <fdreg>,<fsreg>,dword,ceil
else /* CEIL.W.D - MIPS II */
UML_FDTOINT(block, FDVALS_FR1, FSVALD_FR1, SIZE_DWORD, ROUND_CEIL); // fdtoint <fdreg>,F0,dword,ceil
- return TRUE;
+ return true;
case 0x0f:
if (IS_SINGLE(op)) /* FLOOR.W.S - MIPS II */
UML_FSTOINT(block, FDVALS_FR1, FSVALS_FR1, SIZE_DWORD, ROUND_FLOOR);// fstoint <fdreg>,<fsreg>,dword,floor
else /* FLOOR.W.D - MIPS II */
UML_FDTOINT(block, FDVALS_FR1, FSVALD_FR1, SIZE_DWORD, ROUND_FLOOR); // fdtoint <fdreg>,F0,dword,floor
- return TRUE;
+ return true;
case 0x11:
UML_TEST(block, CCR132(31), FCCMASK(op >> 18)); // test ccr31,fccmask[op]
@@ -3555,7 +3555,7 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
UML_FSMOVc(block, condition, FDVALS_FR1, FSVALS_FR1); // fsmov <fdreg>,<fsreg>,condition
else /* MOVT/F.D - MIPS IV */
UML_FDMOVc(block, condition, FDVALD_FR1, FSVALD_FR1); // fdmov <fdreg>,<fsreg>,condition
- return TRUE;
+ return true;
case 0x12:
UML_DCMP(block, R64(RTREG), 0); // dcmp <rtreg>,0
@@ -3563,7 +3563,7 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
UML_FSMOVc(block, COND_Z, FDVALS_FR1, FSVALS_FR1); // fsmov <fdreg>,<fsreg>,Z
else /* MOVZ.D - MIPS IV */
UML_FDMOVc(block, COND_Z, FDVALD_FR1, FSVALD_FR1); // fdmov <fdreg>,<fsreg>,Z
- return TRUE;
+ return true;
case 0x13:
UML_DCMP(block, R64(RTREG), 0); // dcmp <rtreg>,0
@@ -3571,21 +3571,21 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
UML_FSMOVc(block, COND_NZ, FDVALS_FR1, FSVALS_FR1); // fsmov <fdreg>,<fsreg>,NZ
else /* MOVN.D - MIPS IV */
UML_FDMOVc(block, COND_NZ, FDVALD_FR1, FSVALD_FR1); // fdmov <fdreg>,<fsreg>,NZ
- return TRUE;
+ return true;
case 0x15:
if (IS_SINGLE(op)) /* RECIP.S - MIPS IV */
UML_FSRECIP(block, FDVALS_FR1, FSVALS_FR1); // fsrecip <fdreg>,<fsreg>
else /* RECIP.D - MIPS IV */
UML_FDRECIP(block, FDVALD_FR1, FSVALD_FR1); // fdrecip <fdreg>,<fsreg>
- return TRUE;
+ return true;
case 0x16:
if (IS_SINGLE(op)) /* RSQRT.S - MIPS IV */
UML_FSRSQRT(block, FDVALS_FR1, FSVALS_FR1); // fsrsqrt <fdreg>,<fsreg>
else /* RSQRT.D - MIPS IV */
UML_FDRSQRT(block, FDVALD_FR1, FSVALD_FR1); // fdrsqrt <fdreg>,<fsreg>
- return TRUE;
+ return true;
case 0x20:
if (IS_INTEGRAL(op))
@@ -3599,7 +3599,7 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
{
UML_FSFRFLT(block, FDVALS_FR1, FSVALD_FR1, SIZE_QWORD); // fsfrflt <fdreg>,f0,qword
}
- return TRUE;
+ return true;
case 0x21:
if (IS_INTEGRAL(op))
@@ -3613,26 +3613,26 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
{
UML_FDFRFLT(block, FDVALD_FR1, FSVALS_FR1, SIZE_DWORD); // fdfrflt <fdreg>,<fsreg>,dword
}
- return TRUE;
+ return true;
case 0x24:
if (IS_SINGLE(op)) /* CVT.W.S - MIPS I */
UML_FSTOINT(block, FDVALS_FR1, FSVALS_FR1, SIZE_DWORD, ROUND_DEFAULT); // fstoint <fdreg>,<fsreg>,dword,default
else /* CVT.W.D - MIPS I */
UML_FDTOINT(block, FDVALS_FR1, FSVALD_FR1, SIZE_DWORD, ROUND_DEFAULT); // fdtoint <fdreg>,<fsreg>,dword,default
- return TRUE;
+ return true;
case 0x25:
if (IS_SINGLE(op)) /* CVT.L.S - MIPS I */
UML_FSTOINT(block, FDVALD_FR1, FSVALS_FR1, SIZE_QWORD, ROUND_DEFAULT); // fstoint <fdreg>,<fsreg>,qword,default
else /* CVT.L.D - MIPS I */
UML_FDTOINT(block, FDVALD_FR1, FSVALD_FR1, SIZE_QWORD, ROUND_DEFAULT); // fdtoint <fdreg>,<fsreg>,qword,default
- return TRUE;
+ return true;
case 0x30:
case 0x38: /* C.F.S/D - MIPS I */
UML_AND(block, CCR132(31), CCR132(31), ~FCCMASK(op >> 8)); // and ccr31,ccr31,~fccmask[op]
- return TRUE;
+ return true;
case 0x31:
case 0x39:
@@ -3642,7 +3642,7 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
UML_FDCMP(block, FSVALD_FR1, FTVALD_FR1); // fdcmp <fsreg>,<ftreg>
UML_SETc(block, COND_U, I0); // set i0,u
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc
- return TRUE;
+ return true;
case 0x32:
case 0x3a:
@@ -3654,7 +3654,7 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
UML_SETc(block, COND_NU, I1); // set i1,nu
UML_AND(block, I0, I0, I1); // and i0,i0,i1
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc
- return TRUE;
+ return true;
case 0x33:
case 0x3b:
@@ -3666,7 +3666,7 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
UML_SETc(block, COND_E, I1); // set i1,e
UML_OR(block, I0, I0, I1); // or i0,i0,i1
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc
- return TRUE;
+ return true;
case 0x34:
case 0x3c:
@@ -3678,7 +3678,7 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
UML_SETc(block, COND_NU, I1); // set i1,nu
UML_AND(block, I0, I0, I1); // and i0,i0,i1
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc
- return TRUE;
+ return true;
case 0x35:
case 0x3d:
@@ -3690,7 +3690,7 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
UML_SETc(block, COND_B, I1); // set i1,b
UML_OR(block, I0, I0, I1); // or i0,i0,i1
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc
- return TRUE;
+ return true;
case 0x36:
case 0x3e:
@@ -3702,7 +3702,7 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
UML_SETc(block, COND_NU, I1); // set i1,nu
UML_AND(block, I0, I0, I1); // and i0,i0,i1
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc
- return TRUE;
+ return true;
case 0x37:
case 0x3f:
@@ -3714,11 +3714,11 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
UML_SETc(block, COND_BE, I1); // set i1,be
UML_OR(block, I0, I0, I1); // or i0,i0,i1
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc
- return TRUE;
+ return true;
}
break;
}
- return FALSE;
+ return false;
}
/***************************************************************************
@@ -3729,7 +3729,7 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
generate_cop1x_fr0 - compile COP1X opcodes in FR0 mode
----------------------------------------------------------*/
-int mips3_device::generate_cop1x_fr0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool mips3_device::generate_cop1x_fr0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
int in_delay_slot = ((desc->flags & OPFLAG_IN_DELAY_SLOT) != 0);
uint32_t op = desc->opptr.l[0];
@@ -3743,40 +3743,40 @@ int mips3_device::generate_cop1x_fr0(drcuml_block *block, compiler_state *compil
UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh read32
UML_MOV(block, FDVALS_FR0, I0); // mov <cpr1_fd>,i0
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x01: /* LDXC1 - MIPS IV */
UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh read64
generate_set_cop1_reg64_i2d(block, compiler, desc, RTREG, I0);
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x08: /* SWXC1 - MIPS IV */
UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
UML_MOV(block, I1, FSVALS_FR0); // mov i1,<cpr1_fs>
UML_CALLH(block, *m_write32[m_core->mode >> 1]); // callh write32
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x09: /* SDXC1 - MIPS IV */
generate_get_cop1_reg64_d2i(block, compiler, desc, FSREG, I1);
UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
UML_CALLH(block, *m_write64[m_core->mode >> 1]); // callh write64
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x0f: /* PREFX */
- return TRUE;
+ return true;
case 0x20: /* MADD.S - MIPS IV */
UML_FSMUL(block, F0, FSVALS_FR0, FTVALS_FR0); // fsmul f0,<fsreg>,<ftreg>
UML_FSADD(block, FDVALS_FR0, F0, FRVALS_FR0); // fsadd <fdreg>,f0,<frreg>
- return TRUE;
+ return true;
case 0x21: /* MADD.D - MIPS IV */
generate_get_cop1_reg64(block, compiler, desc, FSREG, F0);
@@ -3785,12 +3785,12 @@ int mips3_device::generate_cop1x_fr0(drcuml_block *block, compiler_state *compil
UML_FDMUL(block, F3, F0, F1); // fdmul f3,f0,f1
UML_FDADD(block, F3, F3, F2); // fdadd f3,f3,f2
generate_set_cop1_reg64(block, compiler, desc, FDREG, F3); // dmov <fdreg>,f3
- return TRUE;
+ return true;
case 0x28: /* MSUB.S - MIPS IV */
UML_FSMUL(block, F0, FSVALS_FR0, FTVALS_FR0); // fsmul f0,<fsreg>,<ftreg>
UML_FSSUB(block, FDVALS_FR0, F0, FRVALS_FR0); // fssub <fdreg>,f0,<frreg>
- return TRUE;
+ return true;
case 0x29: /* MSUB.D - MIPS IV */
generate_get_cop1_reg64(block, compiler, desc, FSREG, F0);
@@ -3799,13 +3799,13 @@ int mips3_device::generate_cop1x_fr0(drcuml_block *block, compiler_state *compil
UML_FDMUL(block, F3, F0, F1); // fdmul f3,f0,f1
UML_FDSUB(block, F3, F3, F2); // fdadd f3,f3,f2
generate_set_cop1_reg64(block, compiler, desc, FDREG, F3); // dmov <fdreg>,f3
- return TRUE;
+ return true;
case 0x30: /* NMADD.S - MIPS IV */
UML_FSMUL(block, F0, FSVALS_FR0, FTVALS_FR0); // fsmul f0,<fsreg>,<ftreg>
UML_FSADD(block, F0, F0, FRVALS_FR0); // fsadd f0,f0,<frreg>
UML_FSNEG(block, FDVALS_FR0, F0); // fsneg <fdreg>,f0
- return TRUE;
+ return true;
case 0x31: /* NMADD.D - MIPS IV */
generate_get_cop1_reg64(block, compiler, desc, FSREG, F0);
@@ -3815,12 +3815,12 @@ int mips3_device::generate_cop1x_fr0(drcuml_block *block, compiler_state *compil
UML_FDADD(block, F3, F3, F2); // fdadd f3,f3,f2
UML_FDNEG(block, F3, F3); // fdneg f3,f3
generate_set_cop1_reg64(block, compiler, desc, FDREG, F3); // dmov <fdreg>,f3
- return TRUE;
+ return true;
case 0x38: /* NMSUB.S - MIPS IV */
UML_FSMUL(block, F0, FSVALS_FR0, FTVALS_FR0); // fsmul f0,<fsreg>,<ftreg>
UML_FSSUB(block, FDVALS_FR0, FRVALS_FR0, F0); // fssub <fdreg>,<frreg>,f0
- return TRUE;
+ return true;
case 0x39: /* NMSUB.D - MIPS IV */
generate_get_cop1_reg64(block, compiler, desc, FSREG, F0);
@@ -3829,20 +3829,20 @@ int mips3_device::generate_cop1x_fr0(drcuml_block *block, compiler_state *compil
UML_FDMUL(block, F3, F0, F1); // fdmul f4,f0,f1
UML_FDSUB(block, F3, F2, F0); // fdsub f3,f2,f0
generate_set_cop1_reg64(block, compiler, desc, FDREG, F3); // dmov <fdreg>,f3
- return TRUE;
+ return true;
default:
fprintf(stderr, "cop1x %X\n", op);
break;
}
- return FALSE;
+ return false;
}
/*----------------------------------------------------------
generate_cop1x_fr1 - compile COP1X opcodes in FR1 mode
----------------------------------------------------------*/
-int mips3_device::generate_cop1x_fr1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool mips3_device::generate_cop1x_fr1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
int in_delay_slot = ((desc->flags & OPFLAG_IN_DELAY_SLOT) != 0);
uint32_t op = desc->opptr.l[0];
@@ -3856,83 +3856,83 @@ int mips3_device::generate_cop1x_fr1(drcuml_block *block, compiler_state *compil
UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh read32
UML_MOV(block, FDVALS_FR1, I0); // mov <cpr1_fd>,i0
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x01: /* LDXC1 - MIPS IV */
UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh read64
UML_DMOV(block, FDVALD_FR1, I0); // dmov <cpr1_fd>,i0
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x08: /* SWXC1 - MIPS IV */
UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
UML_MOV(block, I1, FSVALS_FR1); // mov i1,<cpr1_fs>
UML_CALLH(block, *m_write32[m_core->mode >> 1]);// callh write32
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x09: /* SDXC1 - MIPS IV */
generate_get_cop1_reg64_d2i(block, compiler, desc, FSREG, I1);
UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
UML_CALLH(block, *m_write64[m_core->mode >> 1]); // callh write64
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x0f: /* PREFX */
- return TRUE;
+ return true;
case 0x20: /* MADD.S - MIPS IV */
UML_FSMUL(block, F0, FSVALS_FR1, FTVALS_FR1); // fsmul f0,<fsreg>,<ftreg>
UML_FSADD(block, FDVALS_FR1, F0, FRVALS_FR1); // fsadd <fdreg>,f0,<frreg>
- return TRUE;
+ return true;
case 0x21: /* MADD.D - MIPS IV */
UML_FDMUL(block, F0, FSVALD_FR1, FTVALD_FR1); // fdmul f0,<fsreg>,<ftreg>
UML_FDADD(block, FDVALD_FR1, F0, FRVALD_FR1); // fdadd <fdreg>,f0,<frreg>
- return TRUE;
+ return true;
case 0x28: /* MSUB.S - MIPS IV */
UML_FSMUL(block, F0, FSVALS_FR1, FTVALS_FR1); // fsmul f0,<fsreg>,<ftreg>
UML_FSSUB(block, FDVALS_FR1, F0, FRVALS_FR1); // fssub <fdreg>,f0,<frreg>
- return TRUE;
+ return true;
case 0x29: /* MSUB.D - MIPS IV */
UML_FDMUL(block, F0, FSVALD_FR1, FTVALD_FR1); // fdmul f0,<fsreg>,<ftreg>
UML_FDSUB(block, FDVALD_FR1, F0, FRVALD_FR1); // fdsub <fdreg>,f0,<frreg>
- return TRUE;
+ return true;
case 0x30: /* NMADD.S - MIPS IV */
UML_FSMUL(block, F0, FSVALS_FR1, FTVALS_FR1); // fsmul f0,<fsreg>,<ftreg>
UML_FSADD(block, F0, F0, FRVALS_FR1); // fsadd f0,f0,<frreg>
UML_FSNEG(block, FDVALS_FR1, F0); // fsneg <fdreg>,f0
- return TRUE;
+ return true;
case 0x31: /* NMADD.D - MIPS IV */
UML_FDMUL(block, F0, FSVALD_FR1, FTVALD_FR1); // fdmul f0,<fsreg>,<ftreg>
UML_FDADD(block, F0, F0, FRVALD_FR1); // fdadd f0,f0,<frreg>
UML_FDNEG(block, FDVALD_FR1, F0); // fdneg <fdreg>,f0
- return TRUE;
+ return true;
case 0x38: /* NMSUB.S - MIPS IV */
UML_FSMUL(block, F0, FSVALS_FR1, FTVALS_FR1); // fsmul f0,<fsreg>,<ftreg>
UML_FSSUB(block, FDVALS_FR1, FRVALS_FR1, F0); // fssub <fdreg>,<frreg>,f0
- return TRUE;
+ return true;
case 0x39: /* NMSUB.D - MIPS IV */
UML_FDMUL(block, F0, FSVALD_FR1, FTVALD_FR1); // fdmul f0,<fsreg>,<ftreg>
UML_FDSUB(block, FDVALD_FR1, FRVALD_FR1, F1); // fdsub <fdreg>,<frreg>,f0
- return TRUE;
+ return true;
default:
fprintf(stderr, "cop1x %X\n", op);
break;
}
- return FALSE;
+ return false;
}
diff --git a/src/devices/cpu/powerpc/ppc.h b/src/devices/cpu/powerpc/ppc.h
index 0951dfb6b56..0d20214d47f 100644
--- a/src/devices/cpu/powerpc/ppc.h
+++ b/src/devices/cpu/powerpc/ppc.h
@@ -588,7 +588,7 @@ protected:
{
offs_t start; /* start of the RAM block */
offs_t end; /* end of the RAM block */
- uint8_t readonly; /* TRUE if read-only */
+ bool readonly; /* true if read-only */
void * base; /* base in memory where the RAM lives */
};
@@ -629,9 +629,9 @@ protected:
void ppc4xx_set_irq_line(uint32_t bitmask, int state);
int ppc4xx_get_irq_line(uint32_t bitmask);
void ppc4xx_dma_update_irq_states();
- int ppc4xx_dma_decrement_count(int dmachan);
- int ppc4xx_dma_fetch_transmit_byte(int dmachan, uint8_t *byte);
- int ppc4xx_dma_handle_receive_byte(int dmachan, uint8_t byte);
+ bool ppc4xx_dma_decrement_count(int dmachan);
+ bool ppc4xx_dma_fetch_transmit_byte(int dmachan, uint8_t *byte);
+ bool ppc4xx_dma_handle_receive_byte(int dmachan, uint8_t byte);
void ppc4xx_dma_exec(int dmachan);
void ppc4xx_spu_update_irq_states();
void ppc4xx_spu_rx_data(uint8_t data);
@@ -656,7 +656,7 @@ protected:
void static_generate_lsw_entries(int mode);
void static_generate_stsw_entries(int mode);
void generate_update_mode(drcuml_block *block);
- void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
+ void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception);
void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
void generate_compute_flags(drcuml_block *block, const opcode_desc *desc, int updatecr, uint32_t xermask, int invertcarry);
@@ -664,11 +664,11 @@ protected:
void generate_fp_flags(drcuml_block *block, const opcode_desc *desc, int updatefprf);
void generate_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, int source, uint8_t link);
void generate_branch_bo(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t bo, uint32_t bi, int source, int link);
- int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_instruction_13(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_instruction_1f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_instruction_3b(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_instruction_3f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_instruction_13(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_instruction_1f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_instruction_3b(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_instruction_3f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
void log_add_disasm_comment(drcuml_block *block, uint32_t pc, uint32_t op);
const char *log_desc_flags_to_string(uint32_t flags);
void log_register_list(drcuml_state *drcuml, const char *string, const uint32_t *reglist, const uint32_t *regnostarlist);
diff --git a/src/devices/cpu/powerpc/ppccom.cpp b/src/devices/cpu/powerpc/ppccom.cpp
index 206535148ca..45dac1db7bd 100644
--- a/src/devices/cpu/powerpc/ppccom.cpp
+++ b/src/devices/cpu/powerpc/ppccom.cpp
@@ -311,10 +311,10 @@ ppc405gp_device::ppc405gp_device(const machine_config &mconfig, const char *tag,
of access and the protection bits
-------------------------------------------------*/
-static inline int page_access_allowed(int transtype, uint8_t key, uint8_t protbits)
+static inline bool page_access_allowed(int transtype, uint8_t key, uint8_t protbits)
{
if (key == 0)
- return (transtype == TRANSLATE_WRITE) ? (protbits != 3) : TRUE;
+ return (transtype == TRANSLATE_WRITE) ? (protbits != 3) : true;
else
return (transtype == TRANSLATE_WRITE) ? (protbits == 2) : (protbits != 0);
}
@@ -968,7 +968,7 @@ void ppc_device::device_start()
}
/* mark the cache dirty so it is updated on next execute */
- m_cache_dirty = TRUE;
+ m_cache_dirty = true;
}
void ppc_device::state_export(const device_state_entry &entry)
@@ -1223,7 +1223,7 @@ void ppc_device::device_reset()
/* Mark the cache dirty */
m_core->mode = 0;
- m_cache_dirty = TRUE;
+ m_cache_dirty = true;
}
@@ -1465,7 +1465,7 @@ bool ppc_device::memory_translate(address_spacenum spacenum, int intention, offs
{
/* only applies to the program address space */
if (spacenum != AS_PROGRAM)
- return TRUE;
+ return true;
/* translation is successful if the internal routine returns 0 or 1 */
return (ppccom_translate_address_internal(intention, address) <= 1);
@@ -1803,9 +1803,9 @@ void ppc_device::ppccom_execute_mtspr()
case SPR4XX_TCR:
m_core->spr[SPR4XX_TCR] = m_core->param1 | (oldval & PPC4XX_TCR_WRC_MASK);
if ((oldval ^ m_core->spr[SPR4XX_TCR]) & PPC4XX_TCR_FIE)
- ppc4xx_fit_callback(nullptr, FALSE);
+ ppc4xx_fit_callback(nullptr, false);
if ((oldval ^ m_core->spr[SPR4XX_TCR]) & PPC4XX_TCR_PIE)
- ppc4xx_pit_callback(nullptr, FALSE);
+ ppc4xx_pit_callback(nullptr, false);
return;
/* timer status register */
@@ -1818,7 +1818,7 @@ void ppc_device::ppccom_execute_mtspr()
case SPR4XX_PIT:
m_core->spr[SPR4XX_PIT] = m_core->param1;
m_pit_reload = m_core->param1;
- ppc4xx_pit_callback(nullptr, FALSE);
+ ppc4xx_pit_callback(nullptr, false);
return;
/* timebase */
@@ -2150,9 +2150,9 @@ void ppc_device::ppc4xx_set_irq_line(uint32_t bitmask, int state)
/* update the IRQ status */
m_core->irq_pending = ((m_dcr[DCR4XX_EXISR] & m_dcr[DCR4XX_EXIER]) != 0);
if ((m_core->spr[SPR4XX_TCR] & PPC4XX_TCR_FIE) && (m_core->spr[SPR4XX_TSR] & PPC4XX_TSR_FIS))
- m_core->irq_pending = TRUE;
+ m_core->irq_pending = true;
if ((m_core->spr[SPR4XX_TCR] & PPC4XX_TCR_PIE) && (m_core->spr[SPR4XX_TSR] & PPC4XX_TSR_PIS))
- m_core->irq_pending = TRUE;
+ m_core->irq_pending = true;
}
@@ -2213,7 +2213,7 @@ void ppc_device::ppc4xx_dma_update_irq_states()
to do so
-------------------------------------------------*/
-int ppc_device::ppc4xx_dma_decrement_count(int dmachan)
+bool ppc_device::ppc4xx_dma_decrement_count(int dmachan)
{
uint32_t *dmaregs = &m_dcr[8 * dmachan];
@@ -2222,7 +2222,7 @@ int ppc_device::ppc4xx_dma_decrement_count(int dmachan)
/* if non-zero, we keep going */
if ((dmaregs[DCR4XX_DMACT0] & 0xffff) != 0)
- return FALSE;
+ return false;
// if chained mode
if (dmaregs[DCR4XX_DMACR0] & PPC4XX_DMACR_CH)
@@ -2261,9 +2261,9 @@ int ppc_device::ppc4xx_dma_decrement_count(int dmachan)
// m_dcr[DCR4XX_DMASR] |= 1 << (27 - dmachan);
ppc4xx_dma_update_irq_states();
- m_buffered_dma_timer[dmachan]->adjust(attotime::never, FALSE);
+ m_buffered_dma_timer[dmachan]->adjust(attotime::never, false);
}
- return TRUE;
+ return true;
}
@@ -2376,22 +2376,22 @@ TIMER_CALLBACK_MEMBER( ppc_device::ppc4xx_buffered_dma_callback )
to send to a peripheral
-------------------------------------------------*/
-int ppc_device::ppc4xx_dma_fetch_transmit_byte(int dmachan, uint8_t *byte)
+bool ppc_device::ppc4xx_dma_fetch_transmit_byte(int dmachan, uint8_t *byte)
{
uint32_t *dmaregs = &m_dcr[8 * dmachan];
/* if the channel is not enabled, fail */
if (!(dmaregs[DCR4XX_DMACR0] & PPC4XX_DMACR_CE))
- return FALSE;
+ return false;
/* if no transfers remaining, fail */
if ((dmaregs[DCR4XX_DMACT0] & 0xffff) == 0)
- return FALSE;
+ return false;
/* fetch the data */
*byte = m_program->read_byte(dmaregs[DCR4XX_DMADA0]++);
ppc4xx_dma_decrement_count(dmachan);
- return TRUE;
+ return true;
}
@@ -2400,22 +2400,22 @@ int ppc_device::ppc4xx_dma_fetch_transmit_byte(int dmachan, uint8_t *byte)
transmitted by a peripheral
-------------------------------------------------*/
-int ppc_device::ppc4xx_dma_handle_receive_byte(int dmachan, uint8_t byte)
+bool ppc_device::ppc4xx_dma_handle_receive_byte(int dmachan, uint8_t byte)
{
uint32_t *dmaregs = &m_dcr[8 * dmachan];
/* if the channel is not enabled, fail */
if (!(dmaregs[DCR4XX_DMACR0] & PPC4XX_DMACR_CE))
- return FALSE;
+ return false;
/* if no transfers remaining, fail */
if ((dmaregs[DCR4XX_DMACT0] & 0xffff) == 0)
- return FALSE;
+ return false;
/* store the data */
m_program->write_byte(dmaregs[DCR4XX_DMADA0]++, byte);
ppc4xx_dma_decrement_count(dmachan);
- return TRUE;
+ return true;
}
@@ -2551,12 +2551,12 @@ TIMER_CALLBACK_MEMBER( ppc_device::ppc4xx_fit_callback )
uint32_t timebase = get_timebase();
uint32_t interval = 0x200 << (4 * ((m_core->spr[SPR4XX_TCR] & PPC4XX_TCR_FP_MASK) >> 24));
uint32_t target = (timebase + interval) & ~(interval - 1);
- m_fit_timer->adjust(cycles_to_attotime((target + 1 - timebase) / m_tb_divisor), TRUE);
+ m_fit_timer->adjust(cycles_to_attotime((target + 1 - timebase) / m_tb_divisor), true);
}
/* otherwise, turn ourself off */
else
- m_fit_timer->adjust(attotime::never, FALSE);
+ m_fit_timer->adjust(attotime::never, false);
}
@@ -2580,12 +2580,12 @@ TIMER_CALLBACK_MEMBER( ppc_device::ppc4xx_pit_callback )
uint32_t timebase = get_timebase();
uint32_t interval = m_pit_reload;
uint32_t target = timebase + interval;
- m_pit_timer->adjust(cycles_to_attotime((target + 1 - timebase) / m_tb_divisor), TRUE);
+ m_pit_timer->adjust(cycles_to_attotime((target + 1 - timebase) / m_tb_divisor), true);
}
/* otherwise, turn ourself off */
else
- m_pit_timer->adjust(attotime::never, FALSE);
+ m_pit_timer->adjust(attotime::never, false);
}
diff --git a/src/devices/cpu/powerpc/ppcdrc.cpp b/src/devices/cpu/powerpc/ppcdrc.cpp
index 837e23e4bd6..2f229eac758 100644
--- a/src/devices/cpu/powerpc/ppcdrc.cpp
+++ b/src/devices/cpu/powerpc/ppcdrc.cpp
@@ -233,7 +233,7 @@ void ppc_device::execute_run()
/* reset the cache if dirty */
if (m_cache_dirty)
code_flush_cache();
- m_cache_dirty = FALSE;
+ m_cache_dirty = false;
/* execute */
do
@@ -323,45 +323,45 @@ void ppc_device::code_flush_cache()
static_generate_swap_tgpr();
/* append exception handlers for various types */
- static_generate_exception(EXCEPTION_RESET, TRUE, "exception_reset");
- static_generate_exception(EXCEPTION_MACHCHECK, TRUE, "exception_machine_check");
- static_generate_exception(EXCEPTION_DSI, TRUE, "exception_dsi");
- static_generate_exception(EXCEPTION_ISI, TRUE, "exception_isi");
- static_generate_exception(EXCEPTION_EI, TRUE, "exception_ei");
- static_generate_exception(EXCEPTION_EI, FALSE, "exception_ei_norecover");
- static_generate_exception(EXCEPTION_ALIGN, TRUE, "exception_align");
- static_generate_exception(EXCEPTION_PROGRAM, TRUE, "exception_program");
- static_generate_exception(EXCEPTION_NOFPU, TRUE, "exception_fpu_unavailable");
- static_generate_exception(EXCEPTION_DECREMENT, TRUE, "exception_decrementer");
- static_generate_exception(EXCEPTION_SYSCALL, TRUE, "exception_syscall");
- static_generate_exception(EXCEPTION_TRACE, TRUE, "exception_trace");
- static_generate_exception(EXCEPTION_FPASSIST, TRUE, "exception_floating_point_assist");
+ static_generate_exception(EXCEPTION_RESET, true, "exception_reset");
+ static_generate_exception(EXCEPTION_MACHCHECK, true, "exception_machine_check");
+ static_generate_exception(EXCEPTION_DSI, true, "exception_dsi");
+ static_generate_exception(EXCEPTION_ISI, true, "exception_isi");
+ static_generate_exception(EXCEPTION_EI, true, "exception_ei");
+ static_generate_exception(EXCEPTION_EI, false, "exception_ei_norecover");
+ static_generate_exception(EXCEPTION_ALIGN, true, "exception_align");
+ static_generate_exception(EXCEPTION_PROGRAM, true, "exception_program");
+ static_generate_exception(EXCEPTION_NOFPU, true, "exception_fpu_unavailable");
+ static_generate_exception(EXCEPTION_DECREMENT, true, "exception_decrementer");
+ static_generate_exception(EXCEPTION_SYSCALL, true, "exception_syscall");
+ static_generate_exception(EXCEPTION_TRACE, true, "exception_trace");
+ static_generate_exception(EXCEPTION_FPASSIST, true, "exception_floating_point_assist");
if (m_cap & PPCCAP_603_MMU)
{
- static_generate_exception(EXCEPTION_ITLBMISS, TRUE, "exception_itlb_miss");
- static_generate_exception(EXCEPTION_DTLBMISSL, TRUE, "exception_dtlb_miss_load");
- static_generate_exception(EXCEPTION_DTLBMISSS, TRUE, "exception_dtlb_miss_store");
+ static_generate_exception(EXCEPTION_ITLBMISS, true, "exception_itlb_miss");
+ static_generate_exception(EXCEPTION_DTLBMISSL, true, "exception_dtlb_miss_load");
+ static_generate_exception(EXCEPTION_DTLBMISSS, true, "exception_dtlb_miss_store");
}
/* add subroutines for memory accesses */
for (int mode = 0; mode < 8; mode++)
{
- static_generate_memory_accessor(mode, 1, FALSE, FALSE, "read8", m_read8[mode], nullptr);
- static_generate_memory_accessor(mode, 1, TRUE, FALSE, "write8", m_write8[mode], nullptr);
- static_generate_memory_accessor(mode, 2, FALSE, TRUE, "read16mask", m_read16mask[mode], nullptr);
- static_generate_memory_accessor(mode, 2, FALSE, FALSE, "read16", m_read16[mode], m_read16mask[mode]);
- static_generate_memory_accessor(mode, 2, TRUE, TRUE, "write16mask", m_write16mask[mode], nullptr);
- static_generate_memory_accessor(mode, 2, TRUE, FALSE, "write16", m_write16[mode], m_write16mask[mode]);
- static_generate_memory_accessor(mode, 4, FALSE, TRUE, "read32mask", m_read32mask[mode], nullptr);
- static_generate_memory_accessor(mode, 4, FALSE, FALSE, "read32align", m_read32align[mode], nullptr);
- static_generate_memory_accessor(mode, 4, FALSE, FALSE, "read32", m_read32[mode], m_read32mask[mode]);
- static_generate_memory_accessor(mode, 4, TRUE, TRUE, "write32mask", m_write32mask[mode], nullptr);
- static_generate_memory_accessor(mode, 4, TRUE, FALSE, "write32align",m_write32align[mode],nullptr);
- static_generate_memory_accessor(mode, 4, TRUE, FALSE, "write32", m_write32[mode], m_write32mask[mode]);
- static_generate_memory_accessor(mode, 8, FALSE, TRUE, "read64mask", m_read64mask[mode], nullptr);
- static_generate_memory_accessor(mode, 8, FALSE, FALSE, "read64", m_read64[mode], m_read64mask[mode]);
- static_generate_memory_accessor(mode, 8, TRUE, TRUE, "write64mask", m_write64mask[mode], nullptr);
- static_generate_memory_accessor(mode, 8, TRUE, FALSE, "write64", m_write64[mode], m_write64mask[mode]);
+ static_generate_memory_accessor(mode, 1, false, false, "read8", m_read8[mode], nullptr);
+ static_generate_memory_accessor(mode, 1, true, false, "write8", m_write8[mode], nullptr);
+ static_generate_memory_accessor(mode, 2, false, true, "read16mask", m_read16mask[mode], nullptr);
+ static_generate_memory_accessor(mode, 2, false, false, "read16", m_read16[mode], m_read16mask[mode]);
+ static_generate_memory_accessor(mode, 2, true, true, "write16mask", m_write16mask[mode], nullptr);
+ static_generate_memory_accessor(mode, 2, true, false, "write16", m_write16[mode], m_write16mask[mode]);
+ static_generate_memory_accessor(mode, 4, false, true, "read32mask", m_read32mask[mode], nullptr);
+ static_generate_memory_accessor(mode, 4, false, false, "read32align", m_read32align[mode], nullptr);
+ static_generate_memory_accessor(mode, 4, false, false, "read32", m_read32[mode], m_read32mask[mode]);
+ static_generate_memory_accessor(mode, 4, true, true, "write32mask", m_write32mask[mode], nullptr);
+ static_generate_memory_accessor(mode, 4, true, false, "write32align",m_write32align[mode],nullptr);
+ static_generate_memory_accessor(mode, 4, true, false, "write32", m_write32[mode], m_write32mask[mode]);
+ static_generate_memory_accessor(mode, 8, false, true, "read64mask", m_read64mask[mode], nullptr);
+ static_generate_memory_accessor(mode, 8, false, false, "read64", m_read64[mode], m_read64mask[mode]);
+ static_generate_memory_accessor(mode, 8, true, true, "write64mask", m_write64mask[mode], nullptr);
+ static_generate_memory_accessor(mode, 8, true, false, "write64", m_write64[mode], m_write64mask[mode]);
static_generate_lsw_entries(mode);
static_generate_stsw_entries(mode);
}
@@ -383,7 +383,7 @@ void ppc_device::code_compile_block(uint8_t mode, offs_t pc)
compiler_state compiler = { 0 };
const opcode_desc *seqhead, *seqlast;
const opcode_desc *desclist;
- int override = FALSE;
+ bool override = false;
drcuml_block *block;
g_profiler.start(PROFILER_DRC_COMPILE);
@@ -425,7 +425,7 @@ void ppc_device::code_compile_block(uint8_t mode, offs_t pc)
/* are recompiling due to being out of sync and allow future overrides */
else if (seqhead == desclist)
{
- override = TRUE;
+ override = true;
UML_HASH(block, mode, seqhead->pc); // hash mode,pc
}
@@ -459,7 +459,7 @@ void ppc_device::code_compile_block(uint8_t mode, offs_t pc)
nextpc = seqlast->pc + (seqlast->skipslots + 1) * 4;
/* count off cycles and go there */
- generate_update_cycles(block, &compiler, nextpc, TRUE); // <subtract cycles>
+ generate_update_cycles(block, &compiler, nextpc, true); // <subtract cycles>
/* if the last instruction can change modes, use a variable mode; otherwise, assume the same mode */
if (seqlast->flags & OPFLAG_CAN_CHANGE_MODES)
@@ -1575,14 +1575,14 @@ void ppc_device::generate_update_mode(drcuml_block *block)
an exception if out
-------------------------------------------------*/
-void ppc_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception)
+void ppc_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception)
{
/* check full interrupts if pending */
if (compiler->checkints)
{
code_label skip;
- compiler->checkints = FALSE;
+ compiler->checkints = false;
UML_TEST(block, mem(&m_core->irq_pending), ~0); // test [irq_pending],0
UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z
UML_TEST(block, MSR32, MSR_EE); // test [msr],MSR_EE
@@ -1915,7 +1915,7 @@ void ppc_device::generate_branch(drcuml_block *block, compiler_state *compiler,
/* update the cycles and jump through the hash table to the target */
if (desc->targetpc != BRANCH_TARGET_DYNAMIC)
{
- generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE); // <subtract cycles>
+ generate_update_cycles(block, &compiler_temp, desc->targetpc, true); // <subtract cycles>
if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
UML_JMP(block, desc->targetpc | 0x80000000); // jmp desc->targetpc | 0x80000000
else
@@ -1924,7 +1924,7 @@ void ppc_device::generate_branch(drcuml_block *block, compiler_state *compiler,
}
else
{
- generate_update_cycles(block, &compiler_temp, mem(srcptr), TRUE); // <subtract cycles>
+ generate_update_cycles(block, &compiler_temp, mem(srcptr), true); // <subtract cycles>
UML_HASHJMP(block, m_core->mode, mem(srcptr), *m_nocode); // hashjmp <mode>,<rsreg>,nocode
}
@@ -1965,7 +1965,7 @@ void ppc_device::generate_branch_bo(drcuml_block *block, compiler_state *compile
opcode
-------------------------------------------------*/
-int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
uint32_t opswitch = op >> 26;
@@ -1976,7 +1976,7 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
case 0x1e: /* 0x1e group - 64-bit only */
case 0x3a: /* 0x3a group - 64-bit only */
case 0x3e: /* 0x3e group - 64-bit only */
- return FALSE;
+ return false;
case 0x03: /* TWI */
UML_CMP(block, R32(G_RA(op)), (int16_t)G_SIMM(op)); // cmp ra,simm
@@ -1990,62 +1990,62 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_EXHc(block, COND_B, *m_exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,b
if (G_TO(op) & 0x01)
UML_EXHc(block, COND_A, *m_exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,a
- return TRUE;
+ return true;
case 0x07: /* MULLI */
UML_MULS(block, R32(G_RD(op)), R32(G_RD(op)), R32(G_RA(op)), (int16_t)G_SIMM(op));
// muls rd,rd,ra,simm
- return TRUE;
+ return true;
case 0x0e: /* ADDI */
UML_ADD(block, R32(G_RD(op)), R32Z(G_RA(op)), (int16_t)G_SIMM(op)); // add rd,ra,simm
- return TRUE;
+ return true;
case 0x0f: /* ADDIS */
UML_ADD(block, R32(G_RD(op)), R32Z(G_RA(op)), G_SIMM(op) << 16); // add rd,ra,simm << 16
- return TRUE;
+ return true;
case 0x0a: /* CMPLI */
UML_CMP(block, R32(G_RA(op)), G_UIMM(op)); // cmp ra,uimm
UML_GETFLGS(block, I0, FLAG_Z | FLAG_C); // getflgs i0,zc
UML_LOAD(block, I0, m_cmpl_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmpl_cr_table,i0,byte
UML_OR(block, CR32(G_CRFD(op)), I0, XERSO32); // or [crn],i0,[xerso]
- return TRUE;
+ return true;
case 0x0b: /* CMPI */
UML_CMP(block, R32(G_RA(op)), (int16_t)G_SIMM(op)); // cmp ra,uimm
UML_GETFLGS(block, I0, FLAG_Z | FLAG_V | FLAG_C | FLAG_S); // getflgs i0,zvcs
UML_LOAD(block, I0, m_cmp_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmp_cr_table,i0,byte
UML_OR(block, CR32(G_CRFD(op)), I0, XERSO32); // or [crn],i0,[xerso]
- return TRUE;
+ return true;
case 0x08: /* SUBFIC */
UML_SUB(block, R32(G_RD(op)), (int16_t)G_SIMM(op), R32(G_RA(op))); // sub rd,simm,ra
- generate_compute_flags(block, desc, FALSE, XER_CA, TRUE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, false, XER_CA, true); // <update flags>
+ return true;
case 0x0c: /* ADDIC */
UML_ADD(block, R32(G_RD(op)), R32(G_RA(op)), (int16_t)G_SIMM(op)); // add rd,ra,simm
- generate_compute_flags(block, desc, FALSE, XER_CA, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, false, XER_CA, false); // <update flags>
+ return true;
case 0x0d: /* ADDIC. */
UML_ADD(block, R32(G_RD(op)), R32(G_RA(op)), (int16_t)G_SIMM(op)); // add rd,ra,simm
- generate_compute_flags(block, desc, TRUE, XER_CA, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, true, XER_CA, false); // <update flags>
+ return true;
case 0x10: /* BCx */
generate_branch_bo(block, compiler, desc, G_BO(op), G_BI(op), 0, op & M_LK);// <branch conditional>
- return TRUE;
+ return true;
case 0x11: /* SC */
UML_MAPVAR(block, MAPVAR_PC, desc->pc + 4); // mapvar PC,desc->pc+4
UML_EXH(block, *m_exception[EXCEPTION_SYSCALL], 0); // exh syscall,0
- return TRUE;
+ return true;
case 0x12: /* Bx */
generate_branch(block, compiler, desc, 0, op & M_LK); // <branch>
- return TRUE;
+ return true;
case 0x13: /* 0x13 group */
return generate_instruction_13(block, compiler, desc); // <group13>
@@ -2054,48 +2054,48 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_ROLINS(block, R32(G_RA(op)), R32(G_RS(op)), G_SH(op), compute_rlw_mask(G_MB(op), G_ME(op)));
// rolins ra,rs,sh,mask
if (op & M_RC)
- generate_compute_flags(block, desc, TRUE, 0, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, true, 0, false); // <update flags>
+ return true;
case 0x15: /* RLWINMx */
UML_ROLAND(block, R32(G_RA(op)), R32(G_RS(op)), G_SH(op), compute_rlw_mask(G_MB(op), G_ME(op)));
// roland ra,rs,sh,mask
if (op & M_RC)
- generate_compute_flags(block, desc, TRUE, 0, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, true, 0, false); // <update flags>
+ return true;
case 0x17: /* RLWNMx */
UML_ROLAND(block, R32(G_RA(op)), R32(G_RS(op)), R32(G_RB(op)), compute_rlw_mask(G_MB(op), G_ME(op)));
// roland ra,rs,rb,mask
if (op & M_RC)
- generate_compute_flags(block, desc, TRUE, 0, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, true, 0, false); // <update flags>
+ return true;
case 0x18: /* ORI */
UML_OR(block, R32(G_RA(op)), R32(G_RS(op)), G_UIMM(op)); // or ra,rs,uimm
- return TRUE;
+ return true;
case 0x19: /* ORIS */
UML_OR(block, R32(G_RA(op)), R32(G_RS(op)), G_UIMM(op) << 16); // or ra,rs,uimm << 16
- return TRUE;
+ return true;
case 0x1a: /* XORI */
UML_XOR(block, R32(G_RA(op)), R32(G_RS(op)), G_UIMM(op)); // xor ra,rs,uimm
- return TRUE;
+ return true;
case 0x1b: /* XORIS */
UML_XOR(block, R32(G_RA(op)), R32(G_RS(op)), G_UIMM(op) << 16); // xor ra,rs,uimm << 16
- return TRUE;
+ return true;
case 0x1c: /* ANDI. */
UML_AND(block, R32(G_RA(op)), R32(G_RS(op)), G_UIMM(op)); // and ra,rs,uimm
- generate_compute_flags(block, desc, TRUE, 0, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, true, 0, false); // <update flags>
+ return true;
case 0x1d: /* ANDIS. */
UML_AND(block, R32(G_RA(op)), R32(G_RS(op)), G_UIMM(op) << 16); // and ra,rs,uimm << 16
- generate_compute_flags(block, desc, TRUE, 0, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, true, 0, false); // <update flags>
+ return true;
case 0x1f: /* 0x1f group */
return generate_instruction_1f(block, compiler, desc); // <group1f>
@@ -2105,32 +2105,32 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
UML_CALLH(block, *m_read8[m_core->mode]); // callh read8
UML_AND(block, R32(G_RD(op)), I0, 0xff); // and rd,i0,0xff
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x28: /* LHZ */
UML_ADD(block, I0, R32Z(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
UML_CALLH(block, *m_read16[m_core->mode]); // callh read16
UML_AND(block, R32(G_RD(op)), I0, 0xffff); // and rd,i0,0xffff
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x2a: /* LHA */
UML_ADD(block, I0, R32Z(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
UML_CALLH(block, *m_read16[m_core->mode]); // callh read16
UML_SEXT(block, R32(G_RD(op)), I0, SIZE_WORD); // sext rd,i0,word
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x20: /* LWZ */
UML_ADD(block, I0, R32Z(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
UML_CALLH(block, *m_read32[m_core->mode]); // callh read32
UML_MOV(block, R32(G_RD(op)), I0); // mov rd,i0
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x23: /* LBZU */
UML_ADD(block, I0, R32(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
@@ -2139,8 +2139,8 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_CALLH(block, *m_read8[m_core->mode]); // callh read8
UML_AND(block, R32(G_RD(op)), I0, 0xff); // and rd,i0,0xff
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x29: /* LHZU */
UML_ADD(block, I0, R32(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
@@ -2149,8 +2149,8 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_CALLH(block, *m_read16[m_core->mode]); // callh read16
UML_AND(block, R32(G_RD(op)), I0, 0xffff); // and rd,i0,0xffff
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x2b: /* LHAU */
UML_ADD(block, I0, R32(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
@@ -2159,8 +2159,8 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_CALLH(block, *m_read16[m_core->mode]); // callh read16
UML_SEXT(block, R32(G_RD(op)), I0, SIZE_WORD); // sext rd,i0,word
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x21: /* LWZU */
UML_ADD(block, I0, R32(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
@@ -2169,32 +2169,32 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_CALLH(block, *m_read32[m_core->mode]); // callh read32
UML_MOV(block, R32(G_RD(op)), I0); // mov rd,i0
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x26: /* STB */
UML_ADD(block, I0, R32Z(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
UML_AND(block, I1, R32(G_RS(op)), 0xff); // and i1,rs,0xff
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
UML_CALLH(block, *m_write8[m_core->mode]); // callh write8
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x2c: /* STH */
UML_ADD(block, I0, R32Z(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
UML_AND(block, I1, R32(G_RS(op)), 0xffff); // and i1,rs,0xffff
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
UML_CALLH(block, *m_write16[m_core->mode]); // callh write16
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x24: /* STW */
UML_ADD(block, I0, R32Z(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
UML_MOV(block, I1, R32(G_RS(op))); // mov i1,rs
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
UML_CALLH(block, *m_write32[m_core->mode]); // callh write32
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x27: /* STBU */
UML_ADD(block, I0, R32(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
@@ -2203,8 +2203,8 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
UML_CALLH(block, *m_write8[m_core->mode]); // callh write8
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x2d: /* STHU */
UML_ADD(block, I0, R32(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
@@ -2213,8 +2213,8 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
UML_CALLH(block, *m_write16[m_core->mode]); // callh write16
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x25: /* STWU */
UML_ADD(block, I0, R32(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
@@ -2223,8 +2223,8 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
UML_CALLH(block, *m_write32[m_core->mode]); // callh write32
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x2e: /* LMW */
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
@@ -2236,8 +2236,8 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_CALLH(block, *m_read32align[m_core->mode]); // callh read32align
UML_MOV(block, R32(regnum), I0); // mov regnum,i0
}
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x2f: /* STMW */
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
@@ -2249,8 +2249,8 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_MOV(block, I1, R32(regnum)); // mov i1,regnum
UML_CALLH(block, *m_write32align[m_core->mode]); // callh write32align
}
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x30: /* LFS */
UML_ADD(block, I0, R32Z(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
@@ -2258,16 +2258,16 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_CALLH(block, *m_read32[m_core->mode]); // callh read32
UML_FSCOPYI(block, F0, I0); // fscopyi f0,i0
UML_FDFRFLT(block, F64(G_RD(op)), F0, SIZE_DWORD); // fdfrflt fd,f0,dword
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x32: /* LFD */
UML_ADD(block, I0, R32Z(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
UML_CALLH(block, *m_read64[m_core->mode]); // callh read64
UML_FDCOPYI(block, F64(G_RD(op)), I0); // fdcopyi fd,i0
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x31: /* LFSU */
UML_ADD(block, I0, R32(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
@@ -2277,8 +2277,8 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_FSCOPYI(block, F0, I0); // fscopyi f0,i0
UML_FDFRFLT(block, F64(G_RD(op)), F0, SIZE_DWORD); // fdfrflt fd,f0,dword
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x33: /* LFDU */
UML_ADD(block, I0, R32(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
@@ -2287,8 +2287,8 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_CALLH(block, *m_read64[m_core->mode]); // callh read64
UML_FDCOPYI(block, F64(G_RD(op)), I0); // fdcopyi fd,i0
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x34: /* STFS */
UML_ADD(block, I0, R32Z(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
@@ -2296,16 +2296,16 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_ICOPYFS(block, I1, F0); // icopyfs i1,f0
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
UML_CALLH(block, *m_write32[m_core->mode]); // callh write32
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x36: /* STFD */
UML_ADD(block, I0, R32Z(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
UML_ICOPYFD(block, I1, F64(G_RS(op))); // icopyfd i1,fs
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
UML_CALLH(block, *m_write64[m_core->mode]); // callh write64
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x35: /* STFSU */
UML_ADD(block, I0, R32(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
@@ -2315,8 +2315,8 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
UML_CALLH(block, *m_write32[m_core->mode]); // callh write32
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x37: /* STFDU */
UML_ADD(block, I0, R32(G_RA(op)), (int16_t)G_SIMM(op)); // add i0,ra,simm
@@ -2325,8 +2325,8 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
UML_CALLH(block, *m_write64[m_core->mode]); // callh write64
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x3b: /* 0x3b group */
return generate_instruction_3b(block, compiler, desc); // <group3b>
@@ -2335,7 +2335,7 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
return generate_instruction_3f(block, compiler, desc); // <group3f>
}
- return FALSE;
+ return false;
}
@@ -2344,7 +2344,7 @@ int ppc_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
the 0x13 group
-------------------------------------------------*/
-int ppc_device::generate_instruction_13(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool ppc_device::generate_instruction_13(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
uint32_t opswitch = (op >> 1) & 0x3ff;
@@ -2353,16 +2353,16 @@ int ppc_device::generate_instruction_13(drcuml_block *block, compiler_state *com
{
case 0x010: /* BCLRx */
generate_branch_bo(block, compiler, desc, G_BO(op), G_BI(op), SPR_LR, op & M_LK);// <branch conditional>
- return TRUE;
+ return true;
case 0x210: /* BCCTRx */
generate_branch_bo(block, compiler, desc, G_BO(op), G_BI(op), SPR_CTR, op & M_LK);
// <branch conditional>
- return TRUE;
+ return true;
case 0x000: /* MCRF */
UML_MOV(block, CR32(G_CRFD(op)), CR32(G_CRFS(op))); // mov [crd],[crs]
- return TRUE;
+ return true;
case 0x101: /* CRAND */
UML_SHL(block, I0, CR32(G_CRBA(op) / 4), G_CRBA(op) % 4); // shl i0,cr(a / 4),a % 4
@@ -2370,7 +2370,7 @@ int ppc_device::generate_instruction_13(drcuml_block *block, compiler_state *com
UML_AND(block, I0, I0, I1); // and i0,i1
UML_ROLINS(block, CR32(G_CRBD(op) / 4), I0, 32 - G_CRBD(op) % 4, 8 >> (G_CRBD(op) % 4));
// rolins cr(d / 4),i0,32-(d % 4),8 >> (d % 4)
- return TRUE;
+ return true;
case 0x081: /* CRANDC */
UML_SHL(block, I0, CR32(G_CRBA(op) / 4), G_CRBA(op) % 4); // shl i0,cr(a / 4),a % 4
@@ -2379,7 +2379,7 @@ int ppc_device::generate_instruction_13(drcuml_block *block, compiler_state *com
UML_AND(block, I0, I0, I1); // and i0,i1
UML_ROLINS(block, CR32(G_CRBD(op) / 4), I0, 32 - G_CRBD(op) % 4, 8 >> (G_CRBD(op) % 4));
// rolins cr(d / 4),i0,32-(d % 4),8 >> (d % 4)
- return TRUE;
+ return true;
case 0x0e1: /* CRNAND */
UML_SHL(block, I0, CR32(G_CRBA(op) / 4), G_CRBA(op) % 4); // shl i0,cr(a / 4),a % 4
@@ -2388,7 +2388,7 @@ int ppc_device::generate_instruction_13(drcuml_block *block, compiler_state *com
UML_XOR(block, I0, I0, ~0); // xor i0,~0
UML_ROLINS(block, CR32(G_CRBD(op) / 4), I0, 32 - G_CRBD(op) % 4, 8 >> (G_CRBD(op) % 4));
// rolins cr(d / 4),i0,32-(d % 4),8 >> (d % 4)
- return TRUE;
+ return true;
case 0x1c1: /* CROR */
UML_SHL(block, I0, CR32(G_CRBA(op) / 4), G_CRBA(op) % 4); // shl i0,cr(a / 4),a % 4
@@ -2396,7 +2396,7 @@ int ppc_device::generate_instruction_13(drcuml_block *block, compiler_state *com
UML_OR(block, I0, I0, I1); // or i0,i1
UML_ROLINS(block, CR32(G_CRBD(op) / 4), I0, 32 - G_CRBD(op) % 4, 8 >> (G_CRBD(op) % 4));
// rolins cr(d / 4),i0,32-(d % 4),8 >> (d % 4)
- return TRUE;
+ return true;
case 0x1a1: /* CRORC */
UML_SHL(block, I0, CR32(G_CRBA(op) / 4), G_CRBA(op) % 4); // shl i0,cr(a / 4),a % 4
@@ -2405,7 +2405,7 @@ int ppc_device::generate_instruction_13(drcuml_block *block, compiler_state *com
UML_OR(block, I0, I0, I1); // or i0,i1
UML_ROLINS(block, CR32(G_CRBD(op) / 4), I0, 32 - G_CRBD(op) % 4, 8 >> (G_CRBD(op) % 4));
// rolins cr(d / 4),i0,32-(d % 4),8 >> (d % 4)
- return TRUE;
+ return true;
case 0x021: /* CRNOR */
UML_SHL(block, I0, CR32(G_CRBA(op) / 4), G_CRBA(op) % 4); // shl i0,cr(a / 4),a % 4
@@ -2414,7 +2414,7 @@ int ppc_device::generate_instruction_13(drcuml_block *block, compiler_state *com
UML_XOR(block, I0, I0, ~0); // xor i0,~0
UML_ROLINS(block, CR32(G_CRBD(op) / 4), I0, 32 - G_CRBD(op) % 4, 8 >> (G_CRBD(op) % 4));
// rolins cr(d / 4),i0,32-(d % 4),8 >> (d % 4)
- return TRUE;
+ return true;
case 0x0c1: /* CRXOR */
UML_SHL(block, I0, CR32(G_CRBA(op) / 4), G_CRBA(op) % 4); // shl i0,cr(a / 4),a % 4
@@ -2422,7 +2422,7 @@ int ppc_device::generate_instruction_13(drcuml_block *block, compiler_state *com
UML_XOR(block, I0, I0, I1); // xor i0,i1
UML_ROLINS(block, CR32(G_CRBD(op) / 4), I0, 32 - G_CRBD(op) % 4, 8 >> (G_CRBD(op) % 4));
// rolins cr(d / 4),i0,32-(d % 4),8 >> (d % 4)
- return TRUE;
+ return true;
case 0x121: /* CREQV */
UML_SHL(block, I0, CR32(G_CRBA(op) / 4), G_CRBA(op) % 4); // shl i0,cr(a / 4),a % 4
@@ -2431,7 +2431,7 @@ int ppc_device::generate_instruction_13(drcuml_block *block, compiler_state *com
UML_XOR(block, I0, I0, ~0); // xor i0,~0
UML_ROLINS(block, CR32(G_CRBD(op) / 4), I0, 32 - G_CRBD(op) % 4, 8 >> (G_CRBD(op) % 4));
// rolins cr(d / 4),i0,32-(d % 4),8 >> (d % 4)
- return TRUE;
+ return true;
case 0x032: /* RFI */
if (m_cap & PPCCAP_OEA)
@@ -2451,28 +2451,28 @@ int ppc_device::generate_instruction_13(drcuml_block *block, compiler_state *com
else if (m_cap & PPCCAP_4XX)
UML_MOV(block, MSR32, SPR32(SPR4XX_SRR1)); // mov [msr],[srr1]
generate_update_mode(block); // <update mode>
- compiler->checkints = TRUE;
- generate_update_cycles(block, compiler, SPR32(SPROEA_SRR0), TRUE); // <subtract cycles>
+ compiler->checkints = true;
+ generate_update_cycles(block, compiler, SPR32(SPROEA_SRR0), true); // <subtract cycles>
UML_HASHJMP(block, mem(&m_core->mode), SPR32(SPROEA_SRR0), *m_nocode);
// hashjmp mode,[srr0],nocode
- return TRUE;
+ return true;
case 0x033: /* RFCI */
assert(m_cap & PPCCAP_4XX);
UML_MOV(block, MSR32, SPR32(SPR4XX_SRR3)); // mov [msr],[srr3]
generate_update_mode(block); // <update mode>
- compiler->checkints = TRUE;
- generate_update_cycles(block, compiler, SPR32(SPR4XX_SRR2), TRUE); // <subtract cycles>
+ compiler->checkints = true;
+ generate_update_cycles(block, compiler, SPR32(SPR4XX_SRR2), true); // <subtract cycles>
UML_HASHJMP(block, mem(&m_core->mode), SPR32(SPR4XX_SRR2), *m_nocode);
// hashjmp mode,[srr2],nocode
- return TRUE;
+ return true;
case 0x096: /* ISYNC */
/* effective no-op */
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
@@ -2481,7 +2481,7 @@ int ppc_device::generate_instruction_13(drcuml_block *block, compiler_state *com
the 0x1f group
-------------------------------------------------*/
-int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
uint32_t opswitch = (op >> 1) & 0x3ff;
@@ -2515,7 +2515,7 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
case 0x21b: /* SRDx - 64-bit only */
case 0x31a: /* SRADx - 64-bit only */
case 0x3da: /* EXTSW - 64-bit only */
- return FALSE;
+ return false;
case 0x004: /* TW */
UML_CMP(block, R32(G_RA(op)), R32(G_RB(op))); // cmp ra,rb
@@ -2529,131 +2529,131 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_EXHc(block, COND_B, *m_exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,b
if (G_TO(op) & 0x01)
UML_EXHc(block, COND_A, *m_exception[EXCEPTION_PROGRAM], 0x20000);// exh program,0x20000,a
- return TRUE;
+ return true;
case 0x10a: /* ADDx */
case 0x30a: /* ADDOx */
UML_ADD(block, R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // add rd,ra,rb
- generate_compute_flags(block, desc, op & M_RC, ((op & M_OE) ? XER_OV : 0), FALSE);
+ generate_compute_flags(block, desc, op & M_RC, ((op & M_OE) ? XER_OV : 0), false);
// <update flags>
- return TRUE;
+ return true;
case 0x00a: /* ADDCx */
case 0x20a: /* ADDCOx */
UML_ADD(block, R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // add rd,ra,rb
- generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE);
+ generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), false);
// <update flags>
- return TRUE;
+ return true;
case 0x08a: /* ADDEx */
case 0x28a: /* ADDEOx */
UML_CARRY(block, SPR32(SPR_XER), 29); // carry [xer],XER_CA
UML_ADDC(block, R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // addc rd,ra,rb
- generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE);
+ generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), false);
// <update flags>
- return TRUE;
+ return true;
case 0x0ca: /* ADDZEx */
case 0x2ca: /* ADDZEOx */
UML_CARRY(block, SPR32(SPR_XER), 29); // carry [xer],XER_CA
UML_ADDC(block, R32(G_RD(op)), R32(G_RA(op)), 0); // addc rd,ra,0
- generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE);
+ generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), false);
// <update flags>
- return TRUE;
+ return true;
case 0x0ea: /* ADDMEx */
case 0x2ea: /* ADDMEOx */
UML_CARRY(block, SPR32(SPR_XER), 29); // carry [xer],XER_CA
UML_ADDC(block, R32(G_RD(op)), R32(G_RA(op)), (uint32_t)-1); // addc rd,ra,-1
- generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), FALSE);
+ generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), false);
// <update flags>
- return TRUE;
+ return true;
case 0x028: /* SUBFx */
case 0x228: /* SUBFOx */
UML_SUB(block, R32(G_RD(op)), R32(G_RB(op)), R32(G_RA(op))); // sub rd,rb,ra
- generate_compute_flags(block, desc, op & M_RC, (op & M_OE) ? XER_OV : 0, TRUE);
+ generate_compute_flags(block, desc, op & M_RC, (op & M_OE) ? XER_OV : 0, true);
// <update flags>
- return TRUE;
+ return true;
case 0x008: /* SUBFCx */
case 0x208: /* SUBFCOx */
UML_SUB(block, R32(G_RD(op)), R32(G_RB(op)), R32(G_RA(op))); // sub rd,rb,ra
- generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE);
+ generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), true);
// <update flags>
- return TRUE;
+ return true;
case 0x088: /* SUBFEx */
case 0x288: /* SUBFEOx */
UML_XOR(block, I0, SPR32(SPR_XER), XER_CA); // xor i0,[xer],XER_CA
UML_CARRY(block, I0, 29); // carry i0,XER_CA
UML_SUBB(block, R32(G_RD(op)), R32(G_RB(op)), R32(G_RA(op))); // subc rd,rb,ra
- generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE);
+ generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), true);
// <update flags>
- return TRUE;
+ return true;
case 0x0c8: /* SUBFZEx */
case 0x2c8: /* SUBFZEOx */
UML_XOR(block, I0, SPR32(SPR_XER), XER_CA); // xor i0,[xer],XER_CA
UML_CARRY(block, I0, 29); // carry i0,XER_CA
UML_SUBB(block, R32(G_RD(op)), 0, R32(G_RA(op))); // subc rd,0,ra
- generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE);
+ generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), true);
// <update flags>
- return TRUE;
+ return true;
case 0x0e8: /* SUBFMEx */
case 0x2e8: /* SUBFMEOx */
UML_XOR(block, I0, SPR32(SPR_XER), XER_CA); // xor i0,[xer],XER_CA
UML_CARRY(block, I0, 29); // carry i0,XER_CA
UML_SUBB(block, R32(G_RD(op)), (uint32_t)-1, R32(G_RA(op))); // subc rd,-1,ra
- generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), TRUE);
+ generate_compute_flags(block, desc, op & M_RC, XER_CA | ((op & M_OE) ? XER_OV : 0), true);
// <update flags>
- return TRUE;
+ return true;
case 0x068: /* NEGx */
case 0x268: /* NEGOx */
UML_SUB(block, R32(G_RD(op)), 0, R32(G_RA(op))); // sub rd,0,ra
- generate_compute_flags(block, desc, op & M_RC, (op & M_OE) ? XER_OV : 0, TRUE);
+ generate_compute_flags(block, desc, op & M_RC, (op & M_OE) ? XER_OV : 0, true);
// <update flags>
- return TRUE;
+ return true;
case 0x000: /* CMP */
UML_CMP(block, R32(G_RA(op)), R32(G_RB(op))); // cmp ra,rb
UML_GETFLGS(block, I0, FLAG_Z | FLAG_V | FLAG_C | FLAG_S); // getflgs i0,zvcs
UML_LOAD(block, I0, m_cmp_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmp_cr_table,i0,byte
UML_OR(block, CR32(G_CRFD(op)), I0, XERSO32); // or [crn],i0,[xerso]
- return TRUE;
+ return true;
case 0x020: /* CMPL */
UML_CMP(block, R32(G_RA(op)), R32(G_RB(op))); // cmp ra,rb
UML_GETFLGS(block, I0, FLAG_Z | FLAG_C); // getflgs i0,zc
UML_LOAD(block, I0, m_cmpl_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmpl_cr_table,i0,byte
UML_OR(block, CR32(G_CRFD(op)), I0, XERSO32); // or [crn],i0,[xerso]
- return TRUE;
+ return true;
case 0x00b: /* MULHWUx */
UML_MULU(block, I0, R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // mulu i0,rd,ra,rb
if (op & M_RC)
{
UML_TEST(block, R32(G_RD(op)), ~0); // test rd,~0
- generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags>
+ generate_compute_flags(block, desc, op & M_RC, 0, false); // <update flags>
}
- return TRUE;
+ return true;
case 0x04b: /* MULHWx */
UML_MULS(block, I0, R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // muls i0,rd,ra,rb
if (op & M_RC)
{
UML_TEST(block, R32(G_RD(op)), ~0); // test rd,~0
- generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags>
+ generate_compute_flags(block, desc, op & M_RC, 0, false); // <update flags>
}
- return TRUE;
+ return true;
case 0x0eb: /* MULLWx */
case 0x2eb: /* MULLWOx */
UML_MULS(block, R32(G_RD(op)), R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // muls rd,rd,ra,rb
- generate_compute_flags(block, desc, op & M_RC, ((op & M_OE) ? XER_OV : 0), FALSE);// <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, op & M_RC, ((op & M_OE) ? XER_OV : 0), false);// <update flags>
+ return true;
case 0x1cb: /* DIVWUx */
case 0x3cb: /* DIVWUOx */
@@ -2677,10 +2677,10 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_LABEL(block, compiler->labelnum++); // 0:
UML_DIVU(block, R32(G_RD(op)), R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // divu rd,rd,ra,rb
- generate_compute_flags(block, desc, op & M_RC, ((op & M_OE) ? XER_OV : 0), FALSE);// <update flags>
+ generate_compute_flags(block, desc, op & M_RC, ((op & M_OE) ? XER_OV : 0), false);// <update flags>
UML_LABEL(block, compiler->labelnum++); // 1:
- return TRUE;
+ return true;
case 0x1eb: /* DIVWx */
case 0x3eb: /* DIVWOx */
@@ -2730,55 +2730,55 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_LABEL(block, compiler->labelnum++); // 2:
UML_DIVS(block, R32(G_RD(op)), R32(G_RD(op)), R32(G_RA(op)), R32(G_RB(op))); // divs rd,rd,ra,rb
- generate_compute_flags(block, desc, op & M_RC, ((op & M_OE) ? XER_OV : 0), FALSE);// <update flags>
+ generate_compute_flags(block, desc, op & M_RC, ((op & M_OE) ? XER_OV : 0), false);// <update flags>
UML_LABEL(block, compiler->labelnum++); // 3:
- return TRUE;
+ return true;
case 0x01c: /* ANDx */
UML_AND(block, R32(G_RA(op)), R32(G_RS(op)), R32(G_RB(op))); // and ra,rs,rb
- generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, op & M_RC, 0, false); // <update flags>
+ return true;
case 0x03c: /* ANDCx */
UML_XOR(block, I0, R32(G_RB(op)), ~0); // xor i0,rb,~0
UML_AND(block, R32(G_RA(op)), R32(G_RS(op)), I0); // and ra,rs,i0
- generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, op & M_RC, 0, false); // <update flags>
+ return true;
case 0x1dc: /* NANDx */
UML_AND(block, I0, R32(G_RS(op)), R32(G_RB(op))); // and i0,rs,rb
UML_XOR(block, R32(G_RA(op)), I0, ~0); // xor ra,i0,~0
- generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, op & M_RC, 0, false); // <update flags>
+ return true;
case 0x1bc: /* ORx */
UML_OR(block, R32(G_RA(op)), R32(G_RS(op)), R32(G_RB(op))); // or ra,rs,rb
- generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, op & M_RC, 0, false); // <update flags>
+ return true;
case 0x19c: /* ORCx */
UML_XOR(block, I0, R32(G_RB(op)), ~0); // xor i0,rb,~0
UML_OR(block, R32(G_RA(op)), R32(G_RS(op)), I0); // or ra,rs,i0
- generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, op & M_RC, 0, false); // <update flags>
+ return true;
case 0x07c: /* NORx */
UML_OR(block, I0, R32(G_RS(op)), R32(G_RB(op))); // or i0,rs,rb
UML_XOR(block, R32(G_RA(op)), I0, ~0); // xor ra,i0,~0
- generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, op & M_RC, 0, false); // <update flags>
+ return true;
case 0x13c: /* XORx */
UML_XOR(block, R32(G_RA(op)), R32(G_RS(op)), R32(G_RB(op))); // xor ra,rs,rb
- generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, op & M_RC, 0, false); // <update flags>
+ return true;
case 0x11c: /* EQVx */
UML_XOR(block, I0, R32(G_RS(op)), R32(G_RB(op))); // xor i0,rs,rb
UML_XOR(block, R32(G_RA(op)), I0, ~0); // xor ra,i0,~0
- generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, op & M_RC, 0, false); // <update flags>
+ return true;
case 0x018: /* SLWx */
UML_AND(block, I0, R32(G_RB(op)), 0x3f); // and i0, rb, 0x3f
@@ -2803,7 +2803,7 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
}
UML_LABEL(block, compiler->labelnum++); // 1:
- return TRUE;
+ return true;
case 0x218: /* SRWx */
UML_AND(block, I0, R32(G_RB(op)), 0x3f); // and i0, rb, 0x3f
@@ -2828,7 +2828,7 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
}
UML_LABEL(block, compiler->labelnum++); // 1:
- return TRUE;
+ return true;
case 0x318: /* SRAWx */
UML_AND(block, I2, R32(G_RB(op)), 0x3f); // and i2,rb,0x3f
@@ -2864,7 +2864,7 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
{
generate_shift_flags(block, desc, op);
}
- return TRUE;
+ return true;
case 0x338: /* SRAWIx */
if (DISABLE_FLAG_OPTIMIZATIONS || (desc->regreq[3] & REGFLAG_XER_CA))
@@ -2881,57 +2881,57 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
{
generate_shift_flags(block, desc, op);
}
- return TRUE;
+ return true;
case 0x01a: /* CNTLZWx */
UML_LZCNT(block, R32(G_RA(op)), R32(G_RS(op))); // lzcnt ra,rs
if (op & M_RC)
- generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, op & M_RC, 0, false); // <update flags>
+ return true;
case 0x3ba: /* EXTSBx */
UML_SEXT(block, R32(G_RA(op)), R32(G_RS(op)), SIZE_BYTE); // sext ra,rs,byte
if (op & M_RC)
- generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, op & M_RC, 0, false); // <update flags>
+ return true;
case 0x39a: /* EXTSHx */
UML_SEXT(block, R32(G_RA(op)), R32(G_RS(op)), SIZE_WORD); // sext ra,rs,word
if (op & M_RC)
- generate_compute_flags(block, desc, op & M_RC, 0, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, op & M_RC, 0, false); // <update flags>
+ return true;
case 0x057: /* LBZX */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_read8[m_core->mode]); // callh read8
UML_AND(block, R32(G_RD(op)), I0, 0xff); // and rd,i0,0xff
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x117: /* LHZX */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_read16[m_core->mode]); // callh read16
UML_AND(block, R32(G_RD(op)), I0, 0xffff); // and rd,i0,0xffff
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x157: /* LHAX */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_read16[m_core->mode]); // callh read16
UML_SEXT(block, R32(G_RD(op)), I0, SIZE_WORD); // sext rd,i0,word
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x017: /* LWZX */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_read32[m_core->mode]); // callh read32
UML_MOV(block, R32(G_RD(op)), I0); // mov rd,i0
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x217: /* LFSX */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
@@ -2939,16 +2939,16 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_CALLH(block, *m_read32[m_core->mode]); // callh read32
UML_FSCOPYI(block, F0, I0); // fscopyi f0,i0
UML_FDFRFLT(block, F64(G_RD(op)), F0, SIZE_DWORD); // fdfrflt fd,f0,dword
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x257: /* LFDX */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_read64[m_core->mode]); // callh read64
UML_FDCOPYI(block, F64(G_RD(op)), I0); // fdcopyi fd,i0
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x316: /* LHBRX */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
@@ -2956,16 +2956,16 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_CALLH(block, *m_read16[m_core->mode]); // callh read16
UML_BSWAP(block, I0, I0); // bswap i0,i0
UML_SHR(block, R32(G_RD(op)), I0, 16); // shr rd,i0,16
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x216: /* LWBRX */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_read32align[m_core->mode]); // callh read32align
UML_BSWAP(block, R32(G_RD(op)), I0); // bswap rd,i0
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x077: /* LBZUX */
UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
@@ -2974,8 +2974,8 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_CALLH(block, *m_read8[m_core->mode]); // callh read8
UML_AND(block, R32(G_RD(op)), I0, 0xff); // and rd,i0,0xff
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x137: /* LHZUX */
UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
@@ -2984,8 +2984,8 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_CALLH(block, *m_read16[m_core->mode]); // callh read16
UML_AND(block, R32(G_RD(op)), I0, 0xffff); // and rd,i0,0xffff
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x177: /* LHAUX */
UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
@@ -2994,8 +2994,8 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_CALLH(block, *m_read16[m_core->mode]); // callh read16
UML_SEXT(block, R32(G_RD(op)), I0, SIZE_WORD); // sext rd,i0,word
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x037: /* LWZUX */
UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
@@ -3004,8 +3004,8 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_CALLH(block, *m_read32[m_core->mode]); // callh read32
UML_MOV(block, R32(G_RD(op)), I0); // mov rd,i0
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x237: /* LFSUX */
UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
@@ -3015,8 +3015,8 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_FSCOPYI(block, F0, I0); // fscopyi f0,i0
UML_FDFRFLT(block, F64(G_RD(op)), F0, SIZE_DWORD); // fdfrflt fd,f0,dword
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x277: /* LFDUX */
UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
@@ -3025,59 +3025,59 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_CALLH(block, *m_read64[m_core->mode]); // callh read64
UML_FDCOPYI(block, F64(G_RD(op)), I0); // fdcopyi fd,i0
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x014: /* LWARX */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_read32align[m_core->mode]); // callh read32align
UML_MOV(block, R32(G_RD(op)), I0); // mov rd,i0
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x255: /* LSWI */
UML_MOV(block, mem(&m_core->updateaddr), R32Z(G_RA(op))); // mov [updateaddr],ra
UML_MOV(block, mem(&m_core->swcount), ((G_NB(op) - 1) & 0x1f) + 1); // mov [swcount],G_NB
UML_CALLH(block, *m_lsw[m_core->mode][G_RD(op)]); // call lsw[rd]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x215: /* LSWX */
UML_ADD(block, mem(&m_core->updateaddr), R32Z(G_RA(op)), R32(G_RB(op))); // add [updateaddr],ra,rb
UML_AND(block, mem(&m_core->swcount), SPR32(SPR_XER), 0x7f); // and [swcount],[xer],0x7f
UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), mem(&m_core->swcount));// sub icount,icount,[swcount]
UML_CALLHc(block, COND_NZ, *m_lsw[m_core->mode][G_RD(op)]); // call lsw[rd],nz
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x136: /* ECIWX */
/* not implemented */
- return FALSE;
+ return false;
case 0x0d7: /* STBX */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
UML_AND(block, I1, R32(G_RS(op)), 0xff); // and i1,rs,0xff
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_write8[m_core->mode]); // callh write8
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x197: /* STHX */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
UML_AND(block, I1, R32(G_RS(op)), 0xffff); // and i1,rs
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_write16[m_core->mode]); // callh write16
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x097: /* STWX */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
UML_MOV(block, I1, R32(G_RS(op))); // mov i1,rs
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_write32[m_core->mode]); // callh write32
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x297: /* STFSX */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
@@ -3085,8 +3085,8 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_ICOPYFS(block, I1, F0); // icopyfs i1,f0
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_write32[m_core->mode]); // callh write32
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x3d7: /* STFIWX */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
@@ -3094,16 +3094,16 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_MOV(block, I1, mem(&m_core->tempdata.w.l)); // mov i1,[tempdata.lo]
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_write32[m_core->mode]); // callh write32
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x2d7: /* STFDX */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
UML_ICOPYFD(block, I1, F64(G_RS(op))); // icopyfd i1,fs
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_write64[m_core->mode]); // callh write64
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x396: /* STHBRX */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
@@ -3111,16 +3111,16 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_SHR(block, I1, I1, 16); // shr i1,i1,16
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_write16[m_core->mode]); // callh write16
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x296: /* STWBRX */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
UML_BSWAP(block, I1, R32(G_RS(op))); // bswap i1,rs
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_write32[m_core->mode]); // callh write32
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x0f7: /* STBUX */
UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
@@ -3129,8 +3129,8 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_write8[m_core->mode]); // callh write8
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x1b7: /* STHUX */
UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
@@ -3139,8 +3139,8 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_write16[m_core->mode]); // callh write16
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x0b7: /* STWUX */
UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
@@ -3149,8 +3149,8 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDXU(op)); // mapvar dsisr,DSISR_IDXU(op)
UML_CALLH(block, *m_write32[m_core->mode]); // callh write32
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x2b7: /* STFSUX */
UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
@@ -3160,8 +3160,8 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_write32[m_core->mode]); // callh write32
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x2f7: /* STFDUX */
UML_ADD(block, I0, R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
@@ -3170,48 +3170,48 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_write64[m_core->mode]); // callh write64
UML_MOV(block, R32(G_RA(op)), mem(&m_core->updateaddr)); // mov ra,[updateaddr]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x096: /* STWCX. */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
UML_MOV(block, I1, R32(G_RS(op))); // mov i1,rs
UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
UML_CALLH(block, *m_write32align[m_core->mode]); // callh write32align
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
UML_CMP(block, I0, I0); // cmp i0,i0
UML_GETFLGS(block, I0, FLAG_Z | FLAG_C | FLAG_S); // getflgs i0,zcs
UML_LOAD(block, I0, m_cmp_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,cmp_cr_table,i0,byte
UML_OR(block, CR32(0), I0, XERSO32); // or [cr0],i0,[xerso]
- generate_compute_flags(block, desc, TRUE, 0, FALSE); // <update flags>
- return TRUE;
+ generate_compute_flags(block, desc, true, 0, false); // <update flags>
+ return true;
case 0x2d5: /* STSWI */
UML_MOV(block, mem(&m_core->updateaddr), R32Z(G_RA(op))); // mov [updateaddr],ra
UML_MOV(block, mem(&m_core->swcount), ((G_NB(op) - 1) & 0x1f) + 1); // mov [swcount],G_NB
UML_CALLH(block, *m_stsw[m_core->mode][G_RD(op)]); // call stsw[rd]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x295: /* STSWX */
UML_ADD(block, mem(&m_core->updateaddr), R32Z(G_RA(op)), R32(G_RB(op))); // add [updateaddr],ra,rb
UML_AND(block, mem(&m_core->swcount), SPR32(SPR_XER), 0x7f); // and [swcount],[xer],0x7f
UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), mem(&m_core->swcount));// sub icount,icount,[swcount]
UML_CALLHc(block, COND_NZ, *m_stsw[m_core->mode][G_RD(op)]); // call stsw[rd]
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x1b6: /* ECOWX */
/* not implemented */
- return FALSE;
+ return false;
case 0x036: /* DCBST */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
UML_MOV(block, mem(&m_core->param0), I0); // mov [param0],i0
UML_CALLC(block, (c_function)cfunc_ppccom_dcstore_callback, this);
- return TRUE;
+ return true;
case 0x056: /* DCBF */
case 0x0f6: /* DCBTST */
@@ -3222,7 +3222,7 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
case 0x1d6: /* DCBI */
case 0x236: /* TLBSYNC */
/* effective no-ops */
- return TRUE;
+ return true;
case 0x3f6: /* DCBZ */
UML_ADD(block, I0, R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
@@ -3234,30 +3234,30 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_DMOV(block, I1, 0); // dmov i1,0
UML_CALLH(block, *m_write64[m_core->mode]); // callh write64
}
- return TRUE;
+ return true;
case 0x132: /* TLBIE */
UML_MOV(block, mem(&m_core->param0), R32(G_RB(op))); // mov [param0],rb
UML_CALLC(block, (c_function)cfunc_ppccom_execute_tlbie, this); // callc ppccom_execute_tlbie,ppc
- return TRUE;
+ return true;
case 0x172: /* TLBIA */
UML_CALLC(block, (c_function)cfunc_ppccom_execute_tlbia, this); // callc ppccom_execute_tlbia,ppc
- return TRUE;
+ return true;
case 0x3d2: /* TLBLD */
assert(m_cap & PPCCAP_603_MMU);
UML_MOV(block, mem(&m_core->param0), R32(G_RB(op))); // mov [param0],rb
UML_MOV(block, mem(&m_core->param1), 0); // mov [param1],0
UML_CALLC(block, (c_function)cfunc_ppccom_execute_tlbl, this); // callc ppccom_execute_tlbl,ppc
- return TRUE;
+ return true;
case 0x3f2: /* TLBLI */
assert(m_cap & PPCCAP_603_MMU);
UML_MOV(block, mem(&m_core->param0), R32(G_RB(op))); // mov [param0],rb
UML_MOV(block, mem(&m_core->param1), 1); // mov [param1],1
UML_CALLC(block, (c_function)cfunc_ppccom_execute_tlbl, this); // callc ppccom_execute_tlbl,ppc
- return TRUE;
+ return true;
case 0x013: /* MFCR */
UML_SHL(block, I0, CR32(0), 28); // shl i0,cr(0),28
@@ -3275,11 +3275,11 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_OR(block, I0, I0, I1); // or i0,i0,i1
UML_ROLAND(block, I1, CR32(7), 0, 0x0000000f); // roland i1,cr(7),0,0x0000000f
UML_OR(block, R32(G_RD(op)), I0, I1); // or rd,i0,i1
- return TRUE;
+ return true;
case 0x053: /* MFMSR */
UML_MOV(block, R32(G_RD(op)), MSR32); // mov rd,msr
- return TRUE;
+ return true;
case 0x153: /* MFSPR */
{
@@ -3295,33 +3295,33 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_MOV(block, R32(G_RD(op)), m_flavor); // mov rd,flavor
else
{
- generate_update_cycles(block, compiler, desc->pc, TRUE); // <update cycles>
+ generate_update_cycles(block, compiler, desc->pc, true); // <update cycles>
UML_MOV(block, mem(&m_core->param0), spr); // mov [param0],spr
UML_CALLC(block, (c_function)cfunc_ppccom_execute_mfspr, this); // callc ppccom_execute_mfspr,ppc
UML_MOV(block, R32(G_RD(op)), mem(&m_core->param1)); // mov rd,[param1]
}
- return TRUE;
+ return true;
}
case 0x253: /* MFSR */
UML_MOV(block, R32(G_RD(op)), SR32(G_SR(op))); // mov rd,sr
- return TRUE;
+ return true;
case 0x293: /* MFSRIN */
UML_SHR(block, I0, R32(G_RB(op)), 28); // shr i0,G_RB,28
UML_LOAD(block, R32(G_RD(op)), &m_core->sr[0], I0, SIZE_DWORD, SCALE_x4); // load rd,sr,i0,dword
- return TRUE;
+ return true;
case 0x173: /* MFTB */
{
uint32_t tbr = compute_spr(G_SPR(op));
if (tbr != SPRVEA_TBL_R && tbr != SPRVEA_TBU_R)
- return FALSE;
- generate_update_cycles(block, compiler, desc->pc, TRUE); // <update cycles>
+ return false;
+ generate_update_cycles(block, compiler, desc->pc, true); // <update cycles>
UML_MOV(block, mem(&m_core->param0), tbr); // mov [param0],tbr
UML_CALLC(block, (c_function)cfunc_ppccom_execute_mftb, this); // callc ppccom_execute_mftb,ppc
UML_MOV(block, R32(G_RD(op)), mem(&m_core->param1)); // mov rd,[param1]
- return TRUE;
+ return true;
}
case 0x090: /* MTCRF */
@@ -3334,7 +3334,7 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
if (G_CRM(op) & 0x04) UML_ROLAND(block, CR32(5), I0, 24, 0xf); // roland cr(5),i0,24,0x0f
if (G_CRM(op) & 0x02) UML_ROLAND(block, CR32(6), I0, 28, 0xf); // roland cr(6),i0,28,0x0f
if (G_CRM(op) & 0x01) UML_ROLAND(block, CR32(7), I0, 0, 0xf); // roland cr(7),i0,0,0x0f
- return TRUE;
+ return true;
case 0x092: /* MTMSR */
if (m_cap & PPCCAP_603_MMU)
@@ -3346,7 +3346,7 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_CALLHc(block, COND_NZ, *m_swap_tgpr); // callh swap_tgpr,nz
}
generate_update_mode(block); // <update mode>
- return TRUE;
+ return true;
case 0x1d3: /* MTSPR */
{
@@ -3362,26 +3362,26 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
; // read only
else
{
- generate_update_cycles(block, compiler, desc->pc, TRUE); // <update cycles>
+ generate_update_cycles(block, compiler, desc->pc, true); // <update cycles>
UML_MOV(block, mem(&m_core->param0), spr); // mov [param0],spr
UML_MOV(block, mem(&m_core->param1), R32(G_RS(op))); // mov [param1],rs
UML_CALLC(block, (c_function)cfunc_ppccom_execute_mtspr, this); // callc ppccom_execute_mtspr,ppc
- compiler->checkints = TRUE;
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
+ compiler->checkints = true;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
}
- return TRUE;
+ return true;
}
case 0x0d2: /* MTSR */
UML_MOV(block, SR32(G_SR(op)), R32(G_RS(op))); // mov sr[G_SR],rs
UML_CALLC(block, (c_function)cfunc_ppccom_tlb_flush, this); // callc ppccom_tlb_flush,ppc
- return TRUE;
+ return true;
case 0x0f2: /* MTSRIN */
UML_SHR(block, I0, R32(G_RB(op)), 28); // shr i0,G_RB,28
UML_STORE(block, &m_core->sr[0], I0, R32(G_RS(op)), SIZE_DWORD, SCALE_x4); // store sr,i0,rs,dword
UML_CALLC(block, (c_function)cfunc_ppccom_tlb_flush, this); // callc ppccom_tlb_flush,ppc
- return TRUE;
+ return true;
case 0x200: /* MCRXR */
UML_ROLAND(block, I0, SPR32(SPR_XER), 28, 0x0f); // roland i0,[xer],28,0x0f
@@ -3389,71 +3389,71 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
UML_OR(block, CR32(G_CRFD(op)), I0, I1); // or [crd],i0,i1
UML_AND(block, SPR32(SPR_XER), SPR32(SPR_XER), ~0xf0000000); // and [xer],[xer],~0xf0000000
UML_MOV(block, XERSO32, 0); // mov [xerso],0
- return TRUE;
+ return true;
case 0x106: /* ICBT */
case 0x1c6: /* DCCCI */
case 0x3c6: /* ICCCI */
assert(m_cap & PPCCAP_4XX);
/* effective no-nop */
- return TRUE;
+ return true;
case 0x1e6: /* DCREAD */
case 0x3e6: /* ICREAD */
assert(m_cap & PPCCAP_4XX);
UML_MOV(block, R32(G_RT(op)), 0); // mov rt,0
- return TRUE;
+ return true;
case 0x143: /* MFDCR */
{
uint32_t spr = compute_spr(G_SPR(op));
assert(m_cap & PPCCAP_4XX);
- generate_update_cycles(block, compiler, desc->pc, TRUE); // <update cycles>
+ generate_update_cycles(block, compiler, desc->pc, true); // <update cycles>
UML_MOV(block, mem(&m_core->param0), spr); // mov [param0],spr
UML_CALLC(block, (c_function)cfunc_ppccom_execute_mfdcr, this); // callc ppccom_execute_mfdcr,ppc
UML_MOV(block, R32(G_RD(op)), mem(&m_core->param1)); // mov rd,[param1]
- return TRUE;
+ return true;
}
case 0x1c3: /* MTDCR */
{
uint32_t spr = compute_spr(G_SPR(op));
assert(m_cap & PPCCAP_4XX);
- generate_update_cycles(block, compiler, desc->pc, TRUE); // <update cycles>
+ generate_update_cycles(block, compiler, desc->pc, true); // <update cycles>
UML_MOV(block, mem(&m_core->param0), spr); // mov [param0],spr
UML_MOV(block, mem(&m_core->param1), R32(G_RS(op))); // mov [param1],rs
UML_CALLC(block, (c_function)cfunc_ppccom_execute_mtdcr, this); // callc ppccom_execute_mtdcr,ppc
- compiler->checkints = TRUE;
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ compiler->checkints = true;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
}
case 0x083: /* WRTEE */
assert(m_cap & PPCCAP_4XX);
UML_ROLINS(block, MSR32, R32(G_RS(op)), 0, MSR_EE); // rolins msr,rs,0,MSR_EE
- compiler->checkints = TRUE;
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
- return TRUE;
+ compiler->checkints = true;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
+ return true;
case 0x0a3: /* WRTEEI */
assert(m_cap & PPCCAP_4XX);
if (op & MSR_EE)
{
UML_OR(block, MSR32, MSR32, MSR_EE); // or msr,msr,MSR_EE
- compiler->checkints = TRUE;
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE); // <update cycles>
+ compiler->checkints = true;
+ generate_update_cycles(block, compiler, desc->pc + 4, true); // <update cycles>
}
else
UML_AND(block, MSR32, MSR32, ~MSR_EE); // and msr,msr,~MSR_EE
- return TRUE;
+ return true;
case 0x254: /* ESA */
case 0x274: /* DSA */
/* no-op for now */
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
@@ -3462,7 +3462,7 @@ int ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *com
the 0x3b group
-------------------------------------------------*/
-int ppc_device::generate_instruction_3b(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool ppc_device::generate_instruction_3b(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
uint32_t opswitch = (op >> 1) & 0x1f;
@@ -3474,24 +3474,24 @@ int ppc_device::generate_instruction_3b(drcuml_block *block, compiler_state *com
return generate_instruction_3f(block, compiler, desc);
UML_FDADD(block, F0, F64(G_RA(op)), F64(G_RB(op))); // fdadd f0,ra,rb
UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x14: /* FSUBSx */
if (!(m_drcoptions & PPCDRC_ACCURATE_SINGLES))
return generate_instruction_3f(block, compiler, desc);
UML_FDSUB(block, F0, F64(G_RA(op)), F64(G_RB(op))); // fdsub f0,ra,rb
UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x19: /* FMULSx */
if (!(m_drcoptions & PPCDRC_ACCURATE_SINGLES))
return generate_instruction_3f(block, compiler, desc);
UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x12: /* FDIVSx */
if (!(m_drcoptions & PPCDRC_ACCURATE_SINGLES))
@@ -3504,23 +3504,23 @@ int ppc_device::generate_instruction_3b(drcuml_block *block, compiler_state *com
UML_FDMOV(block, F0, mem(&m_core->fp0)); // fdmov f0,0
UML_LABEL(block, compiler->labelnum++); // 2:
UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x16: /* FSQRTSx */
if (!(m_drcoptions & PPCDRC_ACCURATE_SINGLES))
return generate_instruction_3f(block, compiler, desc);
UML_FDSQRT(block, F0, F64(G_RB(op))); // fdsqrt f0,rb
UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x18: /* FRESx */
UML_FSFRFLT(block, F0, F64(G_RB(op)), SIZE_QWORD); // fsfrlt f0,rb,qword
UML_FSRECIP(block, F0, F0); // fsrecip f0,f0
UML_FDFRFLT(block, F64(G_RD(op)), F0, SIZE_DWORD); // fdfrflt rd,f0,dword
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x1d: /* FMADDSx */
if (!(m_drcoptions & PPCDRC_ACCURATE_SINGLES))
@@ -3528,8 +3528,8 @@ int ppc_device::generate_instruction_3b(drcuml_block *block, compiler_state *com
UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
UML_FDADD(block, F0, F0, F64(G_RB(op))); // fdadd f0,f0,rb
UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x1c: /* FMSUBSx */
if (!(m_drcoptions & PPCDRC_ACCURATE_SINGLES))
@@ -3537,8 +3537,8 @@ int ppc_device::generate_instruction_3b(drcuml_block *block, compiler_state *com
UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
UML_FDSUB(block, F0, F0, F64(G_RB(op))); // fdsub f0,f0,rb
UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x1f: /* FNMADDSx */
if (!(m_drcoptions & PPCDRC_ACCURATE_SINGLES))
@@ -3547,8 +3547,8 @@ int ppc_device::generate_instruction_3b(drcuml_block *block, compiler_state *com
UML_FDADD(block, F0, F0, F64(G_RB(op))); // fdadd f0,f0,rb
UML_FDNEG(block, F0, F0); // fdneg f0,f0
UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x1e: /* FNMSUBSx */
if (!(m_drcoptions & PPCDRC_ACCURATE_SINGLES))
@@ -3556,11 +3556,11 @@ int ppc_device::generate_instruction_3b(drcuml_block *block, compiler_state *com
UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
UML_FDSUB(block, F0, F64(G_RB(op)), F0); // fdsub f0,rb,f0
UML_FDRNDS(block, F64(G_RD(op)), F0); // fdrnds rd,f0
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
}
- return FALSE;
+ return false;
}
@@ -3570,7 +3570,7 @@ int ppc_device::generate_instruction_3b(drcuml_block *block, compiler_state *com
the 0x3f group
-------------------------------------------------*/
-int ppc_device::generate_instruction_3f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool ppc_device::generate_instruction_3f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
uint32_t opswitch = (op >> 1) & 0x3ff;
@@ -3582,18 +3582,18 @@ int ppc_device::generate_instruction_3f(drcuml_block *block, compiler_state *com
{
case 0x15: /* FADDx */
UML_FDADD(block, F64(G_RD(op)), F64(G_RA(op)), F64(G_RB(op))); // fdadd rd,ra,rb
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x14: /* FSUBx */
UML_FDSUB(block, F64(G_RD(op)), F64(G_RA(op)), F64(G_RB(op))); // fdsub rd,ra,rb
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x19: /* FMULx */
UML_FDMUL(block, F64(G_RD(op)), F64(G_RA(op)), F64(G_REGC(op))); // fdmul rd,ra,rc
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x12: /* FDIVx */
UML_FDCMP(block, F64(G_RB(op)), mem(&m_core->fp0)); // fdcmp rb,0
@@ -3603,49 +3603,49 @@ int ppc_device::generate_instruction_3f(drcuml_block *block, compiler_state *com
UML_LABEL(block, compiler->labelnum++); // 1:
UML_FDMOV(block, F64(G_RD(op)), mem(&m_core->fp0)); // fdmov rd,0
UML_LABEL(block, compiler->labelnum++); // 2:
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x16: /* FSQRTx */
UML_FDSQRT(block, F64(G_RD(op)), F64(G_RB(op))); // fdsqrt rd,rb
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x1a: /* FRSQRTEx */
UML_FDRSQRT(block, F64(G_RD(op)), F64(G_RB(op))); // fdrsqrt rd,rb
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x17: /* FSELx */
UML_FDCMP(block, F64(G_RA(op)), mem(&m_core->fp0)); // fdcmp f0,ra,[fp0]
UML_FDMOVc(block, COND_AE, F64(G_RD(op)), F64(G_REGC(op))); // fdmov rd,rc,AE
UML_FDMOVc(block, COND_B, F64(G_RD(op)), F64(G_RB(op))); // fdmov rd,rb,B
- return TRUE;
+ return true;
case 0x1d: /* FMADDx */
UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
UML_FDADD(block, F64(G_RD(op)), F0, F64(G_RB(op))); // fdadd rd,f0,rb
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x1f: /* FNMADDx */
UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
UML_FDADD(block, F0, F0, F64(G_RB(op))); // fdadd f0,f0,rb
UML_FDNEG(block, F64(G_RD(op)), F0); // fdneg rd,f0
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x1c: /* FMSUBx */
UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
UML_FDSUB(block, F64(G_RD(op)), F0, F64(G_RB(op))); // fdsub rd,f0,rb
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x1e: /* FNMSUBx */
UML_FDMUL(block, F0, F64(G_RA(op)), F64(G_REGC(op))); // fdmul f0,ra,rc
UML_FDSUB(block, F64(G_RD(op)), F64(G_RB(op)), F0); // fdsub rd,rb,f0
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
}
}
else
@@ -3655,7 +3655,7 @@ int ppc_device::generate_instruction_3f(drcuml_block *block, compiler_state *com
case 0x32e: /* FCTIDx - 64-bit only */
case 0x32f: /* FCTIDZx - 64-bit only */
case 0x34e: /* FCFIDx - 64-bit only */
- return FALSE;
+ return false;
case 0x000: /* FCMPU */
case 0x020: /* FCMPO */
@@ -3663,75 +3663,75 @@ int ppc_device::generate_instruction_3f(drcuml_block *block, compiler_state *com
UML_GETFLGS(block, I0, FLAG_C | FLAG_Z | FLAG_U); // getflgs i0,czu
UML_LOAD(block, I0, m_fcmp_cr_table, I0, SIZE_BYTE, SCALE_x1);// load i0,fcmp_cr_table,i0,byte
UML_OR(block, CR32(G_CRFD(op)), I0, XERSO32); // or [crn],i0,[xerso]
- return TRUE;
+ return true;
case 0x00c: /* FRSPx */
UML_FDRNDS(block, F64(G_RD(op)), F64(G_RB(op))); // fdrnds rd,rb
- generate_fp_flags(block, desc, TRUE);
- return TRUE;
+ generate_fp_flags(block, desc, true);
+ return true;
case 0x00e: /* FCTIWx */
UML_FDTOINT(block, I0, F64(G_RB(op)), SIZE_DWORD, ROUND_DEFAULT); // fdtoint i0,rb,dword,default
UML_DAND(block, mem(&m_core->tempdata.w.l), I0, 0xffffffff);// dand i0,i0,0xffffffff
UML_FDMOV(block, F64(G_RD(op)), mem(&m_core->tempdata.w.l)); // fdmovr rd,i0
- return TRUE;
+ return true;
case 0x00f: /* FCTIWZx */
UML_FDTOINT(block, I0, F64(G_RB(op)), SIZE_DWORD, ROUND_TRUNC); // fdtoint i0,rb,dword,default
UML_DAND(block, mem(&m_core->tempdata.w.l), I0, 0xffffffff);// dand i0,i0,0xffffffff
UML_FDMOV(block, F64(G_RD(op)), mem(&m_core->tempdata.w.l)); // fdmovr rd,i0
- return TRUE;
+ return true;
case 0x028: /* FNEGx */
UML_FDNEG(block, F64(G_RD(op)), F64(G_RB(op))); // fdneg rd,rb
- return TRUE;
+ return true;
case 0x048: /* FMRx */
UML_FDMOV(block, F64(G_RD(op)), F64(G_RB(op))); // fdmov rd,rb
- return TRUE;
+ return true;
case 0x088: /* FNABSx */
UML_FDABS(block, F0, F64(G_RB(op))); // fdabs f0,rb
UML_FDNEG(block, F64(G_RD(op)), F0); // fdneg rd,f0
- return TRUE;
+ return true;
case 0x108: /* FABSx */
UML_FDABS(block, F64(G_RD(op)), F64(G_RB(op))); // fdabs rd,rb
- return TRUE;
+ return true;
case 0x046: /* MTFSB0x */
UML_AND(block, FPSCR32, FPSCR32, ~(0x80000000 >> G_CRBD(op))); // and fpscr32,fpscr32,~(0x80000000 >> G_CRBD)
- return TRUE;
+ return true;
case 0x026: /* MTFSB1x */
UML_OR(block, FPSCR32, FPSCR32, 0x80000000 >> G_CRBD(op)); // or fpscr32,fpscr32,(0x80000000 >> G_CRBD)
- return TRUE;
+ return true;
case 0x040: /* MCRFS */
UML_ROLAND(block, CR32(G_CRFD(op)), FPSCR32, ((G_CRFS(op) - 7) & 7) * 4, 0x0f);
// roland [crd],[fpscr],shift,0x0f
UML_AND(block, FPSCR32, FPSCR32, ~CRMASK(G_CRFS(op))); // and fpscr,fpscr,~crmask[crfs]
- return TRUE;
+ return true;
case 0x247: /* MFFSx */
UML_MOV(block, mem(&m_core->tempdata.w.l), FPSCR32); // mov [tempdata],fpscr
UML_FSMOV(block, F64(G_RD(op)), mem(&m_core->tempdata.d)); // fsmov rd,fpscr
- return TRUE;
+ return true;
case 0x2c7: /* MTFSFx */
UML_FDMOV(block, mem(&m_core->tempdata.d), F64(G_RB(op))); // fdmov [tempdata],fb
UML_ROLINS(block, FPSCR32, mem(&m_core->tempdata.w.l), 0, compute_crf_mask(G_FM(op)));
// rolins fpscr,rb,0,crf_mask
- return TRUE;
+ return true;
case 0x086: /* MTFSFIx */
UML_ROLINS(block, FPSCR32, G_IMM(op), 28 - 4 * G_CRFD(op), CRMASK(G_CRFD(op)));
// rolins fpscr,rb,0,crf_mask
- return TRUE;
+ return true;
}
}
- return FALSE;
+ return false;
}
diff --git a/src/devices/cpu/rsp/rsp.cpp b/src/devices/cpu/rsp/rsp.cpp
index 98cef6ff670..76fe3f63779 100644
--- a/src/devices/cpu/rsp/rsp.cpp
+++ b/src/devices/cpu/rsp/rsp.cpp
@@ -106,7 +106,7 @@ rsp_device::rsp_device(const machine_config &mconfig, const char *tag, device_t
// , m_drcuml(*this, m_cache, 0, 8, 32, 2)
, m_drcfe(nullptr)
, m_drcoptions(0)
- , m_cache_dirty(TRUE)
+ , m_cache_dirty(true)
, m_numcycles(0)
, m_format(nullptr)
, m_arg2(0)
@@ -420,7 +420,7 @@ void rsp_device::device_start()
}
/* mark the cache dirty so it is updated on next execute */
- m_cache_dirty = TRUE;
+ m_cache_dirty = true;
state_add( RSP_PC, "PC", m_debugger_temp).callimport().callexport().formatstr("%08X");
state_add( RSP_R0, "R0", m_rsp_state->r[0]).formatstr("%08X");
diff --git a/src/devices/cpu/rsp/rsp.h b/src/devices/cpu/rsp/rsp.h
index a00feb1c03b..dbb97511ef6 100644
--- a/src/devices/cpu/rsp/rsp.h
+++ b/src/devices/cpu/rsp/rsp.h
@@ -210,7 +210,7 @@ private:
{
offs_t start; /* start of the RAM block */
offs_t end; /* end of the RAM block */
- uint8_t readonly; /* TRUE if read-only */
+ bool readonly; /* true if read-only */
void * base; /* base in memory where the RAM lives */
};
@@ -311,15 +311,15 @@ private:
void static_generate_nocode_handler();
void static_generate_out_of_cycles();
void static_generate_memory_accessor(int size, int iswrite, const char *name, uml::code_handle *&handleptr);
- void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
+ void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception);
void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
void generate_delay_slot_and_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint8_t linkreg);
void generate_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
- int generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ bool generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
void log_add_disasm_comment(drcuml_block *block, uint32_t pc, uint32_t op);
};
diff --git a/src/devices/cpu/rsp/rspcp2.h b/src/devices/cpu/rsp/rspcp2.h
index 5f477963940..ad12d82b601 100644
--- a/src/devices/cpu/rsp/rspcp2.h
+++ b/src/devices/cpu/rsp/rspcp2.h
@@ -85,9 +85,9 @@ protected:
virtual void init();
virtual void start();
- virtual int generate_cop2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return TRUE; }
- virtual int generate_lwc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return TRUE; }
- virtual int generate_swc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return TRUE; }
+ virtual bool generate_cop2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return true; }
+ virtual bool generate_lwc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return true; }
+ virtual bool generate_swc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return true; }
virtual void state_string_export(const int index, std::string &str) const;
@@ -172,7 +172,7 @@ public:
void dump_dmem();
protected:
- virtual int generate_vector_opcode(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return TRUE; }
+ virtual bool generate_vector_opcode(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return true; }
uint16_t SATURATE_ACCUM(int accum, int slice, uint16_t negative, uint16_t positive);
diff --git a/src/devices/cpu/rsp/rspcp2d.cpp b/src/devices/cpu/rsp/rspcp2d.cpp
index 7efb3f34b12..f770f07b4aa 100644
--- a/src/devices/cpu/rsp/rspcp2d.cpp
+++ b/src/devices/cpu/rsp/rspcp2d.cpp
@@ -707,7 +707,7 @@ static void cfunc_ltv(void *param)
}
-int rsp_cop2_drc::generate_lwc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
+bool rsp_cop2_drc::generate_lwc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
int offset = (op & 0x7f);
@@ -721,65 +721,65 @@ int rsp_cop2_drc::generate_lwc2(drcuml_block *block, rsp_device::compiler_state
case 0x00: /* LBV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_lbv, this);
- return TRUE;
+ return true;
case 0x01: /* LSV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_lsv, this);
- return TRUE;
+ return true;
case 0x02: /* LLV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_llv, this);
- return TRUE;
+ return true;
case 0x03: /* LDV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_ldv, this);
- return TRUE;
+ return true;
case 0x04: /* LQV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_lqv, this);
- return TRUE;
+ return true;
case 0x05: /* LRV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_lrv, this);
- return TRUE;
+ return true;
case 0x06: /* LPV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_lpv, this);
- return TRUE;
+ return true;
case 0x07: /* LUV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_luv, this);
- return TRUE;
+ return true;
case 0x08: /* LHV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_lhv, this);
- return TRUE;
+ return true;
case 0x09: /* LFV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_lfv, this);
- return TRUE;
+ return true;
case 0x0a: /* LWV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_lwv, this);
- return TRUE;
+ return true;
case 0x0b: /* LTV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [m_rspcop2_state->op],desc->opptr.l
UML_CALLC(block, cfunc_ltv, this);
- return TRUE;
+ return true;
default:
- return FALSE;
+ return false;
}
}
@@ -1257,7 +1257,7 @@ static void cfunc_stv(void *param)
((rsp_cop2 *)param)->stv();
}
-int rsp_cop2_drc::generate_swc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
+bool rsp_cop2_drc::generate_swc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
int offset = (op & 0x7f);
@@ -1271,69 +1271,69 @@ int rsp_cop2_drc::generate_swc2(drcuml_block *block, rsp_device::compiler_state
case 0x00: /* SBV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_sbv, this);
- return TRUE;
+ return true;
case 0x01: /* SSV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_ssv, this);
- return TRUE;
+ return true;
case 0x02: /* SLV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_slv, this);
- return TRUE;
+ return true;
case 0x03: /* SDV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_sdv, this);
- return TRUE;
+ return true;
case 0x04: /* SQV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_sqv, this);
- return TRUE;
+ return true;
case 0x05: /* SRV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_srv, this);
- return TRUE;
+ return true;
case 0x06: /* SPV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_spv, this);
- return TRUE;
+ return true;
case 0x07: /* SUV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_suv, this);
- return TRUE;
+ return true;
case 0x08: /* SHV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_shv, this);
- return TRUE;
+ return true;
case 0x09: /* SFV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_sfv, this);
- return TRUE;
+ return true;
case 0x0a: /* SWV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_swv, this);
- return TRUE;
+ return true;
case 0x0b: /* STV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_stv, this);
- return TRUE;
+ return true;
default:
m_rsp.unimplemented_opcode(op);
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
@@ -3251,7 +3251,7 @@ static void cfunc_vrsqh(void *param)
vector opcode
-------------------------------------------------*/
-int rsp_cop2_drc::generate_vector_opcode(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
+bool rsp_cop2_drc::generate_vector_opcode(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
// Opcode legend:
@@ -3265,226 +3265,226 @@ int rsp_cop2_drc::generate_vector_opcode(drcuml_block *block, rsp_device::compil
case 0x00: /* VMULF */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmulf, this);
- return TRUE;
+ return true;
case 0x01: /* VMULU */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmulu, this);
- return TRUE;
+ return true;
case 0x04: /* VMUDL */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmudl, this);
- return TRUE;
+ return true;
case 0x05: /* VMUDM */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmudm, this);
- return TRUE;
+ return true;
case 0x06: /* VMUDN */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmudn, this);
- return TRUE;
+ return true;
case 0x07: /* VMUDH */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmudh, this);
- return TRUE;
+ return true;
case 0x08: /* VMACF */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmacf, this);
- return TRUE;
+ return true;
case 0x09: /* VMACU */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmacu, this);
- return TRUE;
+ return true;
case 0x0c: /* VMADL */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmadl, this);
- return TRUE;
+ return true;
case 0x0d: /* VMADM */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmadm, this);
- return TRUE;
+ return true;
case 0x0e: /* VMADN */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmadn, this);
- return TRUE;
+ return true;
case 0x0f: /* VMADH */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmadh, this);
- return TRUE;
+ return true;
case 0x10: /* VADD */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vadd, this);
- return TRUE;
+ return true;
case 0x11: /* VSUB */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vsub, this);
- return TRUE;
+ return true;
case 0x13: /* VABS */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vabs, this);
- return TRUE;
+ return true;
case 0x14: /* VADDC */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vaddc, this);
- return TRUE;
+ return true;
case 0x15: /* VSUBC */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vsubc, this);
- return TRUE;
+ return true;
case 0x16: /* VADDB */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vaddb, this);
- return TRUE;
+ return true;
case 0x17: /* VSUBB (reserved, functionally identical to VADDB) */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vaddb, this);
- return TRUE;
+ return true;
case 0x18: /* VACCB (reserved, functionally identical to VADDB) */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vaddb, this);
- return TRUE;
+ return true;
case 0x19: /* VSUCB (reserved, functionally identical to VADDB) */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vaddb, this);
- return TRUE;
+ return true;
case 0x1d: /* VSAW */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vsaw, this);
- return TRUE;
+ return true;
case 0x20: /* VLT */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vlt, this);
- return TRUE;
+ return true;
case 0x21: /* VEQ */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_veq, this);
- return TRUE;
+ return true;
case 0x22: /* VNE */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vne, this);
- return TRUE;
+ return true;
case 0x23: /* VGE */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vge, this);
- return TRUE;
+ return true;
case 0x24: /* VCL */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vcl, this);
- return TRUE;
+ return true;
case 0x25: /* VCH */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vch, this);
- return TRUE;
+ return true;
case 0x26: /* VCR */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vcr, this);
- return TRUE;
+ return true;
case 0x27: /* VMRG */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmrg, this);
- return TRUE;
+ return true;
case 0x28: /* VAND */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vand, this);
- return TRUE;
+ return true;
case 0x29: /* VNAND */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vnand, this);
- return TRUE;
+ return true;
case 0x2a: /* VOR */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vor, this);
- return TRUE;
+ return true;
case 0x2b: /* VNOR */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vnor, this);
- return TRUE;
+ return true;
case 0x2c: /* VXOR */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vxor, this);
- return TRUE;
+ return true;
case 0x2d: /* VNXOR */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vnxor, this);
- return TRUE;
+ return true;
case 0x30: /* VRCP */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vrcp, this);
- return TRUE;
+ return true;
case 0x31: /* VRCPL */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vrcpl, this);
- return TRUE;
+ return true;
case 0x32: /* VRCPH */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vrcph, this);
- return TRUE;
+ return true;
case 0x33: /* VMOV */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vmov, this);
- return TRUE;
+ return true;
case 0x34: /* VRSQ */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vrsq, this);
- return TRUE;
+ return true;
case 0x35: /* VRSQL */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vrsql, this);
- return TRUE;
+ return true;
case 0x36: /* VRSQH */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_vrsqh, this);
- return TRUE;
+ return true;
case 0x37: /* VNOP */
case 0x3F: /* VNULL */
- return TRUE;
+ return true;
default:
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, unimplemented_opcode, &m_rsp);
- return FALSE;
+ return false;
}
}
@@ -3695,7 +3695,7 @@ static void cfunc_ctc2(void *param)
COP2 Opcode Compilation
***************************************************************************/
-int rsp_cop2_drc::generate_cop2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
+bool rsp_cop2_drc::generate_cop2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
uint8_t opswitch = RSREG;
@@ -3708,7 +3708,7 @@ int rsp_cop2_drc::generate_cop2(drcuml_block *block, rsp_device::compiler_state
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_mfc2, this); // callc mfc2
}
- return TRUE;
+ return true;
case 0x02: /* CFCz */
if (RTREG != 0)
@@ -3716,21 +3716,21 @@ int rsp_cop2_drc::generate_cop2(drcuml_block *block, rsp_device::compiler_state
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_cfc2, this); // callc cfc2
}
- return TRUE;
+ return true;
case 0x04: /* MTCz */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_mtc2, this); // callc mtc2
- return TRUE;
+ return true;
case 0x06: /* CTCz */
UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_ctc2, this); // callc ctc2
- return TRUE;
+ return true;
case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
return generate_vector_opcode(block, compiler, desc);
}
- return FALSE;
+ return false;
}
diff --git a/src/devices/cpu/rsp/rspcp2d.h b/src/devices/cpu/rsp/rspcp2d.h
index 62fc25fe475..2e07403458d 100644
--- a/src/devices/cpu/rsp/rspcp2d.h
+++ b/src/devices/cpu/rsp/rspcp2d.h
@@ -24,9 +24,9 @@ class rsp_cop2_drc : public rsp_cop2
public:
rsp_cop2_drc(rsp_device &rsp, running_machine &machine) : rsp_cop2(rsp, machine) { }
private:
- virtual int generate_cop2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
- virtual int generate_lwc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
- virtual int generate_swc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
+ virtual bool generate_cop2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
+ virtual bool generate_lwc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
+ virtual bool generate_swc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
virtual void state_string_export(const int index, std::string &str) const override;
@@ -103,7 +103,7 @@ public:
virtual void ctc2() override;
private:
- virtual int generate_vector_opcode(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
+ virtual bool generate_vector_opcode(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
};
#endif /* __RSPCP2D_H__ */
diff --git a/src/devices/cpu/rsp/rspdrc.cpp b/src/devices/cpu/rsp/rspdrc.cpp
index 9849c07a71f..fe838519652 100644
--- a/src/devices/cpu/rsp/rspdrc.cpp
+++ b/src/devices/cpu/rsp/rspdrc.cpp
@@ -266,7 +266,7 @@ void rsp_device::execute_run_drc()
/* reset the cache if dirty */
if (m_cache_dirty)
code_flush_cache();
- m_cache_dirty = FALSE;
+ m_cache_dirty = false;
/* execute */
do
@@ -308,7 +308,7 @@ void rsp_device::execute_run_drc()
void rsp_device::rspdrc_flush_drc_cache()
{
if (!allow_drc()) return;
- m_cache_dirty = TRUE;
+ m_cache_dirty = true;
}
/*-------------------------------------------------
@@ -329,12 +329,12 @@ void rsp_device::code_flush_cache()
static_generate_out_of_cycles();
/* add subroutines for memory accesses */
- static_generate_memory_accessor(1, FALSE, "read8", m_read8);
- static_generate_memory_accessor(1, TRUE, "write8", m_write8);
- static_generate_memory_accessor(2, FALSE, "read16", m_read16);
- static_generate_memory_accessor(2, TRUE, "write16", m_write16);
- static_generate_memory_accessor(4, FALSE, "read32", m_read32);
- static_generate_memory_accessor(4, TRUE, "write32", m_write32);
+ static_generate_memory_accessor(1, false, "read8", m_read8);
+ static_generate_memory_accessor(1, true, "write8", m_write8);
+ static_generate_memory_accessor(2, false, "read16", m_read16);
+ static_generate_memory_accessor(2, true, "write16", m_write16);
+ static_generate_memory_accessor(4, false, "read32", m_read32);
+ static_generate_memory_accessor(4, true, "write32", m_write32);
}
catch (drcuml_block::abort_compilation &)
{
@@ -354,7 +354,7 @@ void rsp_device::code_compile_block(offs_t pc)
compiler_state compiler = { 0 };
const opcode_desc *seqhead, *seqlast;
const opcode_desc *desclist;
- int override = FALSE;
+ int override = false;
drcuml_block *block;
g_profiler.start(PROFILER_DRC_COMPILE);
@@ -394,7 +394,7 @@ void rsp_device::code_compile_block(offs_t pc)
/* are recompiling due to being out of sync and allow future overrides */
else if (seqhead == desclist)
{
- override = TRUE;
+ override = true;
UML_HASH(block, 0, seqhead->pc); // hash mode,pc
}
@@ -428,7 +428,7 @@ void rsp_device::code_compile_block(offs_t pc)
nextpc = seqlast->pc + (seqlast->skipslots + 1) * 4;
/* count off cycles and go there */
- generate_update_cycles(block, &compiler, nextpc, TRUE); // <subtract cycles>
+ generate_update_cycles(block, &compiler, nextpc, true); // <subtract cycles>
/* if the last instruction can change modes, use a variable mode; otherwise, assume the same mode */
if (seqlast->next() == nullptr || seqlast->next()->pc != nextpc)
@@ -638,7 +638,7 @@ void rsp_device::static_generate_memory_accessor(int size, int iswrite, const ch
subtract cycles from the icount and generate
an exception if out
-------------------------------------------------*/
-void rsp_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception)
+void rsp_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception)
{
/* account for cycles */
if (compiler->cycles > 0)
@@ -783,7 +783,7 @@ void rsp_device::generate_branch(drcuml_block *block, compiler_state *compiler,
/* update the cycles and jump through the hash table to the target */
if (desc->targetpc != BRANCH_TARGET_DYNAMIC)
{
- generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE); // <subtract cycles>
+ generate_update_cycles(block, &compiler_temp, desc->targetpc, true); // <subtract cycles>
if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
UML_JMP(block, desc->targetpc | 0x80000000); // jmp desc->targetpc
else
@@ -791,7 +791,7 @@ void rsp_device::generate_branch(drcuml_block *block, compiler_state *compiler,
}
else
{
- generate_update_cycles(block, &compiler_temp, mem(&m_rsp_state->jmpdest), TRUE); // <subtract cycles>
+ generate_update_cycles(block, &compiler_temp, mem(&m_rsp_state->jmpdest), true); // <subtract cycles>
UML_HASHJMP(block, 0, mem(&m_rsp_state->jmpdest), *m_nocode); // hashjmp <mode>,<rsreg>,nocode
}
}
@@ -832,7 +832,7 @@ void rsp_device::generate_delay_slot_and_branch(drcuml_block *block, compiler_st
UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles
}
-int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
int in_delay_slot = ((desc->flags & OPFLAG_IN_DELAY_SLOT) != 0);
uint32_t op = desc->opptr.l[0];
@@ -853,25 +853,25 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
case 0x02: /* J - MIPS I */
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
- return TRUE;
+ return true;
case 0x03: /* JAL - MIPS I */
generate_delay_slot_and_branch(block, compiler, desc, 31); // <next instruction + hashjmp>
- return TRUE;
+ return true;
case 0x04: /* BEQ - MIPS I */
UML_CMP(block, R32(RSREG), R32(RTREG)); // cmp <rsreg>,<rtreg>
UML_JMPc(block, COND_NE, skip = compiler->labelnum++); // jmp skip,NE
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
- return TRUE;
+ return true;
case 0x05: /* BNE - MIPS I */
UML_CMP(block, R32(RSREG), R32(RTREG)); // dcmp <rsreg>,<rtreg>
UML_JMPc(block, COND_E, skip = compiler->labelnum++); // jmp skip,E
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
- return TRUE;
+ return true;
case 0x06: /* BLEZ - MIPS I */
if (RSREG != 0)
@@ -883,14 +883,14 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
}
else
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
- return TRUE;
+ return true;
case 0x07: /* BGTZ - MIPS I */
UML_CMP(block, R32(RSREG), 0); // dcmp <rsreg>,0
UML_JMPc(block, COND_LE, skip = compiler->labelnum++); // jmp skip,LE
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
- return TRUE;
+ return true;
/* ----- immediate arithmetic ----- */
@@ -898,7 +898,7 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
case 0x0f: /* LUI - MIPS I */
if (RTREG != 0)
UML_MOV(block, R32(RTREG), SIMMVAL << 16); // dmov <rtreg>,SIMMVAL << 16
- return TRUE;
+ return true;
case 0x08: /* ADDI - MIPS I */
case 0x09: /* ADDIU - MIPS I */
@@ -906,7 +906,7 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
{
UML_ADD(block, R32(RTREG), R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL,V
}
- return TRUE;
+ return true;
case 0x0a: /* SLTI - MIPS I */
if (RTREG != 0)
@@ -914,7 +914,7 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_CMP(block, R32(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL
UML_SETc(block, COND_L, R32(RTREG)); // dset <rtreg>,l
}
- return TRUE;
+ return true;
case 0x0b: /* SLTIU - MIPS I */
if (RTREG != 0)
@@ -922,23 +922,23 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_CMP(block, R32(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL
UML_SETc(block, COND_B, R32(RTREG)); // dset <rtreg>,b
}
- return TRUE;
+ return true;
case 0x0c: /* ANDI - MIPS I */
if (RTREG != 0)
UML_AND(block, R32(RTREG), R32(RSREG), UIMMVAL); // dand <rtreg>,<rsreg>,UIMMVAL
- return TRUE;
+ return true;
case 0x0d: /* ORI - MIPS I */
if (RTREG != 0)
UML_OR(block, R32(RTREG), R32(RSREG), UIMMVAL); // dor <rtreg>,<rsreg>,UIMMVAL
- return TRUE;
+ return true;
case 0x0e: /* XORI - MIPS I */
if (RTREG != 0)
UML_XOR(block, R32(RTREG), R32(RSREG), UIMMVAL); // dxor <rtreg>,<rsreg>,UIMMVAL
- return TRUE;
+ return true;
/* ----- memory load operations ----- */
@@ -948,8 +948,8 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
if (RTREG != 0)
UML_SEXT(block, R32(RTREG), I0, SIZE_BYTE); // dsext <rtreg>,i0,byte
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x21: /* LH - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -957,8 +957,8 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
if (RTREG != 0)
UML_SEXT(block, R32(RTREG), I0, SIZE_WORD); // dsext <rtreg>,i0,word
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x23: /* LW - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -966,8 +966,8 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
if (RTREG != 0)
UML_MOV(block, R32(RTREG), I0);
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x24: /* LBU - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -975,8 +975,8 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
if (RTREG != 0)
UML_AND(block, R32(RTREG), I0, 0xff); // dand <rtreg>,i0,0xff
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x25: /* LHU - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
@@ -984,8 +984,8 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
if (RTREG != 0)
UML_AND(block, R32(RTREG), I0, 0xffff); // dand <rtreg>,i0,0xffff
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x32: /* LWC2 - MIPS I */
return m_cop2->generate_lwc2(block, compiler, desc);
@@ -998,24 +998,24 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg>
UML_CALLH(block, *m_write8); // callh write8
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x29: /* SH - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg>
UML_CALLH(block, *m_write16); // callh write16
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x2b: /* SW - MIPS I */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg>
UML_CALLH(block, *m_write32); // callh write32
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 4, true);
+ return true;
case 0x3a: /* SWC2 - MIPS I */
return m_cop2->generate_swc2(block, compiler, desc);
@@ -1034,7 +1034,7 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
//default: /* ??? */ invalid_instruction(op); break;
}
- return FALSE;
+ return false;
}
@@ -1043,7 +1043,7 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
'SPECIAL' group
-------------------------------------------------*/
-int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool rsp_device::generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
uint8_t opswitch = op & 63;
@@ -1058,42 +1058,42 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
{
UML_SHL(block, R32(RDREG), R32(RTREG), SHIFT);
}
- return TRUE;
+ return true;
case 0x02: /* SRL - MIPS I */
if (RDREG != 0)
{
UML_SHR(block, R32(RDREG), R32(RTREG), SHIFT);
}
- return TRUE;
+ return true;
case 0x03: /* SRA - MIPS I */
if (RDREG != 0)
{
UML_SAR(block, R32(RDREG), R32(RTREG), SHIFT);
}
- return TRUE;
+ return true;
case 0x04: /* SLLV - MIPS I */
if (RDREG != 0)
{
UML_SHL(block, R32(RDREG), R32(RTREG), R32(RSREG));
}
- return TRUE;
+ return true;
case 0x06: /* SRLV - MIPS I */
if (RDREG != 0)
{
UML_SHR(block, R32(RDREG), R32(RTREG), R32(RSREG));
}
- return TRUE;
+ return true;
case 0x07: /* SRAV - MIPS I */
if (RDREG != 0)
{
UML_SAR(block, R32(RDREG), R32(RTREG), R32(RSREG));
}
- return TRUE;
+ return true;
/* ----- basic arithmetic ----- */
@@ -1103,7 +1103,7 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
{
UML_ADD(block, R32(RDREG), R32(RSREG), R32(RTREG));
}
- return TRUE;
+ return true;
case 0x22: /* SUB - MIPS I */
case 0x23: /* SUBU - MIPS I */
@@ -1111,7 +1111,7 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
{
UML_SUB(block, R32(RDREG), R32(RSREG), R32(RTREG));
}
- return TRUE;
+ return true;
/* ----- basic logical ops ----- */
@@ -1120,21 +1120,21 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
{
UML_AND(block, R32(RDREG), R32(RSREG), R32(RTREG)); // dand <rdreg>,<rsreg>,<rtreg>
}
- return TRUE;
+ return true;
case 0x25: /* OR - MIPS I */
if (RDREG != 0)
{
UML_OR(block, R32(RDREG), R32(RSREG), R32(RTREG)); // dor <rdreg>,<rsreg>,<rtreg>
}
- return TRUE;
+ return true;
case 0x26: /* XOR - MIPS I */
if (RDREG != 0)
{
UML_XOR(block, R32(RDREG), R32(RSREG), R32(RTREG)); // dxor <rdreg>,<rsreg>,<rtreg>
}
- return TRUE;
+ return true;
case 0x27: /* NOR - MIPS I */
if (RDREG != 0)
@@ -1142,7 +1142,7 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
UML_OR(block, I0, R32(RSREG), R32(RTREG)); // dor i0,<rsreg>,<rtreg>
UML_XOR(block, R32(RDREG), I0, (uint64_t)~0); // dxor <rdreg>,i0,~0
}
- return TRUE;
+ return true;
/* ----- basic comparisons ----- */
@@ -1153,7 +1153,7 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
UML_CMP(block, R32(RSREG), R32(RTREG)); // dcmp <rsreg>,<rtreg>
UML_SETc(block, COND_L, R32(RDREG)); // dset <rdreg>,l
}
- return TRUE;
+ return true;
case 0x2b: /* SLTU - MIPS I */
if (RDREG != 0)
@@ -1161,18 +1161,18 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
UML_CMP(block, R32(RSREG), R32(RTREG)); // dcmp <rsreg>,<rtreg>
UML_SETc(block, COND_B, R32(RDREG)); // dset <rdreg>,b
}
- return TRUE;
+ return true;
/* ----- jumps and branches ----- */
case 0x08: /* JR - MIPS I */
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
- return TRUE;
+ return true;
case 0x09: /* JALR - MIPS I */
generate_delay_slot_and_branch(block, compiler, desc, RDREG); // <next instruction + hashjmp>
- return TRUE;
+ return true;
/* ----- system calls ----- */
@@ -1186,9 +1186,9 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
generate_branch(block, compiler, desc);
UML_EXIT(block, EXECUTE_OUT_OF_CYCLES);
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
@@ -1198,7 +1198,7 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
'REGIMM' group
-------------------------------------------------*/
-int rsp_device::generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool rsp_device::generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
uint8_t opswitch = RTREG;
@@ -1216,7 +1216,7 @@ int rsp_device::generate_regimm(drcuml_block *block, compiler_state *compiler, c
// <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
}
- return TRUE;
+ return true;
case 0x01: /* BGEZ */
case 0x11: /* BGEZAL */
@@ -1231,9 +1231,9 @@ int rsp_device::generate_regimm(drcuml_block *block, compiler_state *compiler, c
else
generate_delay_slot_and_branch(block, compiler, desc, (opswitch & 0x10) ? 31 : 0);
// <next instruction + hashjmp>
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
@@ -1241,7 +1241,7 @@ int rsp_device::generate_regimm(drcuml_block *block, compiler_state *compiler, c
generate_cop0 - compile COP0 opcodes
-------------------------------------------------*/
-int rsp_device::generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool rsp_device::generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
uint32_t op = desc->opptr.l[0];
uint8_t opswitch = RSREG;
@@ -1256,20 +1256,20 @@ int rsp_device::generate_cop0(drcuml_block *block, compiler_state *compiler, con
UML_CALLC(block, cfunc_get_cop0_reg, this); // callc cfunc_get_cop0_reg
if(RDREG == 2)
{
- generate_update_cycles(block, compiler, mem(&m_rsp_state->pc), TRUE);
+ generate_update_cycles(block, compiler, mem(&m_rsp_state->pc), true);
UML_HASHJMP(block, 0, mem(&m_rsp_state->pc), *m_nocode);
}
}
- return TRUE;
+ return true;
case 0x04: /* MTCz */
UML_MOV(block, mem(&m_rsp_state->arg0), RDREG); // mov [arg0],<rdreg>
UML_MOV(block, mem(&m_rsp_state->arg1), R32(RTREG)); // mov [arg1],rtreg
UML_CALLC(block, cfunc_set_cop0_reg, this); // callc cfunc_set_cop0_reg
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/***************************************************************************
diff --git a/src/devices/cpu/sc61860/sctable.hxx b/src/devices/cpu/sc61860/sctable.hxx
index 2e16dc51033..822867017fb 100644
--- a/src/devices/cpu/sc61860/sctable.hxx
+++ b/src/devices/cpu/sc61860/sctable.hxx
@@ -50,8 +50,8 @@ void sc61860_device::sc61860_instruction()
case 41: sc61860_jump_rel_minus(!m_zero);m_icount-=4;break;
case 42: sc61860_jump_rel_plus(!m_carry);m_icount-=4;break;
case 43: sc61860_jump_rel_minus(!m_carry);m_icount-=4;break;
- case 44: sc61860_jump_rel_plus(TRUE);m_icount-=4;break;
- case 45: sc61860_jump_rel_minus(TRUE);m_icount-=4;break;
+ case 44: sc61860_jump_rel_plus(true);m_icount-=4;break;
+ case 45: sc61860_jump_rel_minus(true);m_icount-=4;break;
case 47: sc61860_loop();m_icount-=7;break;
case 48: sc61860_load_imm_p(READ_RAM(A));m_icount-=2;break;
case 49: sc61860_load_imm_q(READ_RAM(A));m_icount-=2;break;
@@ -78,7 +78,7 @@ void sc61860_device::sc61860_instruction()
case 76: sc61860_in_a();m_icount-=2;break;
case 77: /*nopw*/;m_icount-=2;break;
case 78: sc61860_wait();m_icount-=6;break;
- case 79: sc61860_wait_x(FALSE);m_icount-=1;break;
+ case 79: sc61860_wait_x(false);m_icount-=1;break;
case 80: sc61860_inc_p();m_icount-=2;break;
case 81: sc61860_dec_p();m_icount-=2;break;
case 82: sc61860_store_ext(A);m_icount-=2;break;
@@ -103,7 +103,7 @@ void sc61860_device::sc61860_instruction()
case 103: sc61860_cmp(A, READ_OP());m_icount-=4;break;
case 105: sc61860_execute_table_call();m_icount-=3;break;
case 107: sc61860_test_special();m_icount-=4;break;
- case 111: sc61860_wait_x(TRUE);m_icount-=1;break;
+ case 111: sc61860_wait_x(true);m_icount-=1;break;
case 112: sc61860_add(m_p, READ_OP());m_icount-=4;break;
case 113: sc61860_sub(m_p, READ_OP());m_icount-=4;break;
case 116: sc61860_add(A, READ_OP());m_icount-=4;break;
diff --git a/src/devices/cpu/sh2/sh2.cpp b/src/devices/cpu/sh2/sh2.cpp
index 415d9cd9645..78bf317d3e2 100644
--- a/src/devices/cpu/sh2/sh2.cpp
+++ b/src/devices/cpu/sh2/sh2.cpp
@@ -2274,7 +2274,7 @@ void sh2_device::device_reset()
m_sh2_state->internal_irq_level = -1;
- m_cache_dirty = TRUE;
+ m_cache_dirty = true;
}
@@ -2565,7 +2565,7 @@ void sh2_device::device_start()
}
/* mark the cache dirty so it is updated on next execute */
- m_cache_dirty = TRUE;
+ m_cache_dirty = true;
}
diff --git a/src/devices/cpu/sh2/sh2.h b/src/devices/cpu/sh2/sh2.h
index dad81c972ec..cf38bea2526 100644
--- a/src/devices/cpu/sh2/sh2.h
+++ b/src/devices/cpu/sh2/sh2.h
@@ -252,7 +252,7 @@ private:
{
offs_t start; /* start of the RAM block */
offs_t end; /* end of the RAM block */
- uint8_t readonly; /* TRUE if read-only */
+ bool readonly; /* true if read-only */
void * base; /* base in memory where the RAM lives */
} m_fastram[SH2_MAX_FASTRAM];
@@ -456,18 +456,18 @@ private:
void log_register_list(drcuml_state *drcuml, const char *string, const uint32_t *reglist, const uint32_t *regnostarlist);
void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent);
void log_add_disasm_comment(drcuml_block *block, uint32_t pc, uint32_t op);
- void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
+ void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception);
void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t ovrpc);
void generate_delay_slot(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t ovrpc);
- int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t ovrpc);
- int generate_group_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
- int generate_group_2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
- int generate_group_3(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, uint32_t ovrpc);
- int generate_group_4(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
- int generate_group_6(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
- int generate_group_8(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
- int generate_group_12(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
+ bool generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t ovrpc);
+ bool generate_group_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
+ bool generate_group_2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
+ bool generate_group_3(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, uint32_t ovrpc);
+ bool generate_group_4(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
+ bool generate_group_6(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
+ bool generate_group_8(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
+ bool generate_group_12(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
public:
void func_printf_probe();
diff --git a/src/devices/cpu/sh2/sh2drc.cpp b/src/devices/cpu/sh2/sh2drc.cpp
index a77d48664e9..964e7cebb41 100644
--- a/src/devices/cpu/sh2/sh2drc.cpp
+++ b/src/devices/cpu/sh2/sh2drc.cpp
@@ -598,19 +598,19 @@ void sh2_device::code_flush_cache()
static_generate_entry_point();
/* add subroutines for memory accesses */
- static_generate_memory_accessor(1, FALSE, "read8", &m_read8);
- static_generate_memory_accessor(1, TRUE, "write8", &m_write8);
- static_generate_memory_accessor(2, FALSE, "read16", &m_read16);
- static_generate_memory_accessor(2, TRUE, "write16", &m_write16);
- static_generate_memory_accessor(4, FALSE, "read32", &m_read32);
- static_generate_memory_accessor(4, TRUE, "write32", &m_write32);
+ static_generate_memory_accessor(1, false, "read8", &m_read8);
+ static_generate_memory_accessor(1, true, "write8", &m_write8);
+ static_generate_memory_accessor(2, false, "read16", &m_read16);
+ static_generate_memory_accessor(2, true, "write16", &m_write16);
+ static_generate_memory_accessor(4, false, "read32", &m_read32);
+ static_generate_memory_accessor(4, true, "write32", &m_write32);
}
catch (drcuml_block::abort_compilation &)
{
fatalerror("Unable to generate SH2 static code\n");
}
- m_cache_dirty = FALSE;
+ m_cache_dirty = false;
}
/* Execute cycles - returns number of cycles actually run */
@@ -668,7 +668,7 @@ void sh2_device::code_compile_block(uint8_t mode, offs_t pc)
compiler_state compiler = { 0 };
const opcode_desc *seqhead, *seqlast;
const opcode_desc *desclist;
- int override = FALSE;
+ bool override = false;
drcuml_block *block;
g_profiler.start(PROFILER_DRC_COMPILE);
@@ -710,7 +710,7 @@ void sh2_device::code_compile_block(uint8_t mode, offs_t pc)
/* are recompiling due to being out of sync and allow future overrides */
else if (seqhead == desclist)
{
- override = TRUE;
+ override = true;
UML_HASH(block, mode, seqhead->pc); // hash mode,pc
}
@@ -751,7 +751,7 @@ void sh2_device::code_compile_block(uint8_t mode, offs_t pc)
}
/* count off cycles and go there */
- generate_update_cycles(block, &compiler, nextpc, TRUE); // <subtract cycles>
+ generate_update_cycles(block, &compiler, nextpc, true); // <subtract cycles>
/* SH2 has no modes */
if (seqlast->next() == nullptr || seqlast->next()->pc != nextpc)
@@ -1220,14 +1220,14 @@ void sh2_device::log_add_disasm_comment(drcuml_block *block, uint32_t pc, uint32
subtract cycles from the icount and generate
an exception if out
-------------------------------------------------*/
-void sh2_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception)
+void sh2_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception)
{
/* check full interrupts if pending */
if (compiler->checkints)
{
code_label skip = compiler->labelnum++;
- compiler->checkints = FALSE;
+ compiler->checkints = false;
compiler->labelnum += 4;
/* check for interrupts */
@@ -1455,7 +1455,7 @@ void sh2_device::generate_delay_slot(drcuml_block *block, compiler_state *compil
opcode
-------------------------------------------------*/
-int sh2_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t ovrpc)
+bool sh2_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t ovrpc)
{
uint32_t scratch, scratch2;
int32_t disp;
@@ -1476,8 +1476,8 @@ int sh2_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_CALLH(block, *m_write32);
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 2:
return generate_group_2(block, compiler, desc, opcode, in_delay_slot, ovrpc);
@@ -1494,8 +1494,8 @@ int sh2_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
UML_MOV(block, R32(Rn), I0); // mov Rn, r0
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 6:
return generate_group_6(block, compiler, desc, opcode, in_delay_slot, ovrpc);
@@ -1504,7 +1504,7 @@ int sh2_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
scratch = opcode & 0xff;
scratch2 = (uint32_t)(int32_t)(int16_t)(int8_t)scratch;
UML_ADD(block, R32(Rn), R32(Rn), scratch2); // add Rn, Rn, scratch2
- return TRUE;
+ return true;
case 8:
return generate_group_8(block, compiler, desc, opcode, in_delay_slot, ovrpc);
@@ -1533,8 +1533,8 @@ int sh2_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
}
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 10: // BRA
disp = ((int32_t)opcode << 20) >> 20;
@@ -1542,9 +1542,9 @@ int sh2_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
generate_delay_slot(block, compiler, desc, m_sh2_state->ea-2);
- generate_update_cycles(block, compiler, m_sh2_state->ea, TRUE); // <subtract cycles>
+ generate_update_cycles(block, compiler, m_sh2_state->ea, true); // <subtract cycles>
UML_HASHJMP(block, 0, m_sh2_state->ea, *m_nocode); // hashjmp m_sh2_state->ea
- return TRUE;
+ return true;
case 11: // BSR
// panicstr @ 403da22 relies on the delay slot clobbering the PR set by a BSR, so
@@ -1556,9 +1556,9 @@ int sh2_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
generate_delay_slot(block, compiler, desc, m_sh2_state->ea-2);
- generate_update_cycles(block, compiler, m_sh2_state->ea, TRUE); // <subtract cycles>
+ generate_update_cycles(block, compiler, m_sh2_state->ea, true); // <subtract cycles>
UML_HASHJMP(block, 0, m_sh2_state->ea, *m_nocode); // hashjmp m_sh2_state->ea
- return TRUE;
+ return true;
case 12:
return generate_group_12(block, compiler, desc, opcode, in_delay_slot, ovrpc);
@@ -1586,23 +1586,23 @@ int sh2_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
}
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 14: // MOVI
scratch = opcode & 0xff;
scratch2 = (uint32_t)(int32_t)(int16_t)(int8_t)scratch;
UML_MOV(block, R32(Rn), scratch2);
- return TRUE;
+ return true;
case 15:
- return FALSE;
+ return false;
}
- return FALSE;
+ return false;
}
-int sh2_device::generate_group_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
+bool sh2_device::generate_group_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
switch (opcode & 0x3F)
{
@@ -1621,14 +1621,14 @@ int sh2_device::generate_group_0(drcuml_block *block, compiler_state *compiler,
case 0x39:
case 0x3a:
case 0x3b:
- return FALSE;
+ return false;
case 0x09: // NOP();
- return TRUE;
+ return true;
case 0x02: // STCSR(Rn);
UML_MOV(block, R32(Rn), mem(&m_sh2_state->sr));
- return TRUE;
+ return true;
case 0x03: // BSRF(Rn);
if (m_cpu_type > CPU_TYPE_SH1)
@@ -1642,9 +1642,9 @@ int sh2_device::generate_group_0(drcuml_block *block, compiler_state *compiler,
generate_delay_slot(block, compiler, desc, m_sh2_state->target);
- generate_update_cycles(block, compiler, mem(&m_sh2_state->target), TRUE); // <subtract cycles>
+ generate_update_cycles(block, compiler, mem(&m_sh2_state->target), true); // <subtract cycles>
UML_HASHJMP(block, 0, mem(&m_sh2_state->target), *m_nocode); // jmp target
- return TRUE;
+ return true;
}
break;
@@ -1657,8 +1657,8 @@ int sh2_device::generate_group_0(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write8); // call write8
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x05: // MOVWS0(Rm, Rn);
case 0x15: // MOVWS0(Rm, Rn);
@@ -1669,8 +1669,8 @@ int sh2_device::generate_group_0(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write16); // call write16
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x06: // MOVLS0(Rm, Rn);
case 0x16: // MOVLS0(Rm, Rn);
@@ -1681,8 +1681,8 @@ int sh2_device::generate_group_0(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x07: // MULL(Rm, Rn);
case 0x17: // MULL(Rm, Rn);
@@ -1691,26 +1691,26 @@ int sh2_device::generate_group_0(drcuml_block *block, compiler_state *compiler,
if (m_cpu_type > CPU_TYPE_SH1)
{
UML_MULU(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->ea), R32(Rn), R32(Rm)); // mulu macl, ea, Rn, Rm
- return TRUE;
+ return true;
}
break;
case 0x08: // CLRT();
UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~T); // and r0, sr, ~T (clear the T bit)
- return TRUE;
+ return true;
case 0x0a: // STSMACH(Rn);
UML_MOV(block, R32(Rn), mem(&m_sh2_state->mach)); // mov Rn, mach
- return TRUE;
+ return true;
case 0x0b: // RTS();
UML_MOV(block, mem(&m_sh2_state->target), mem(&m_sh2_state->pr)); // mov target, pr (in case of d-slot shenanigans)
generate_delay_slot(block, compiler, desc, m_sh2_state->target);
- generate_update_cycles(block, compiler, mem(&m_sh2_state->target), TRUE); // <subtract cycles>
+ generate_update_cycles(block, compiler, mem(&m_sh2_state->target), true); // <subtract cycles>
UML_HASHJMP(block, 0, mem(&m_sh2_state->target), *m_nocode);
- return TRUE;
+ return true;
case 0x0c: // MOVBL0(Rm, Rn);
case 0x1c: // MOVBL0(Rm, Rn);
@@ -1721,8 +1721,8 @@ int sh2_device::generate_group_0(drcuml_block *block, compiler_state *compiler,
UML_SEXT(block, R32(Rn), I0, SIZE_BYTE); // sext Rn, r0, BYTE
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x0d: // MOVWL0(Rm, Rn);
case 0x1d: // MOVWL0(Rm, Rn);
@@ -1733,8 +1733,8 @@ int sh2_device::generate_group_0(drcuml_block *block, compiler_state *compiler,
UML_SEXT(block, R32(Rn), I0, SIZE_WORD); // sext Rn, r0, WORD
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x0e: // MOVLL0(Rm, Rn);
case 0x1e: // MOVLL0(Rm, Rn);
@@ -1745,8 +1745,8 @@ int sh2_device::generate_group_0(drcuml_block *block, compiler_state *compiler,
UML_MOV(block, R32(Rn), I0); // mov Rn, r0
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x0f: // MAC_L(Rm, Rn);
case 0x1f: // MAC_L(Rm, Rn);
@@ -1758,25 +1758,25 @@ int sh2_device::generate_group_0(drcuml_block *block, compiler_state *compiler,
UML_MOV(block, mem(&m_sh2_state->arg0), desc->opptr.w[0]);
UML_CALLC(block, cfunc_MAC_L, this);
load_fast_iregs(block);
- return TRUE;
+ return true;
}
break;
case 0x12: // STCGBR(Rn);
UML_MOV(block, R32(Rn), mem(&m_sh2_state->gbr)); // mov Rn, gbr
- return TRUE;
+ return true;
case 0x18: // SETT();
UML_OR(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), T); // or sr, sr, T
- return TRUE;
+ return true;
case 0x19: // DIV0U();
UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~(M|Q|T)); // and sr, sr, ~(M|Q|T)
- return TRUE;
+ return true;
case 0x1a: // STSMACL(Rn);
UML_MOV(block, R32(Rn), mem(&m_sh2_state->macl)); // mov Rn, macl
- return TRUE;
+ return true;
case 0x1b: // SLEEP();
UML_MOV(block, I0, mem(&m_sh2_state->sleep_mode)); // mov i0, sleep_mode
@@ -1784,20 +1784,20 @@ int sh2_device::generate_group_0(drcuml_block *block, compiler_state *compiler,
UML_JMPc(block, COND_E, compiler->labelnum); // beq labelnum
// sleep mode != 2
UML_MOV(block, mem(&m_sh2_state->sleep_mode), 0x1); // mov sleep_mode, #1
- generate_update_cycles(block, compiler, desc->pc, TRUE); // repeat this insn
+ generate_update_cycles(block, compiler, desc->pc, true); // repeat this insn
UML_JMP(block, compiler->labelnum+1); // jmp labelnum+1
UML_LABEL(block, compiler->labelnum++); // labelnum:
// sleep_mode == 2
UML_MOV(block, mem(&m_sh2_state->sleep_mode), 0x0); // sleep_mode = 0
- generate_update_cycles(block, compiler, desc->pc+2, TRUE); // go to next insn
+ generate_update_cycles(block, compiler, desc->pc+2, true); // go to next insn
UML_LABEL(block, compiler->labelnum++); // labelnum+1:
- return TRUE;
+ return true;
case 0x22: // STCVBR(Rn);
UML_MOV(block, R32(Rn), mem(&m_sh2_state->vbr)); // mov Rn, vbr
- return TRUE;
+ return true;
case 0x23: // BRAF(Rn);
if (m_cpu_type > CPU_TYPE_SH1)
@@ -1806,24 +1806,24 @@ int sh2_device::generate_group_0(drcuml_block *block, compiler_state *compiler,
generate_delay_slot(block, compiler, desc, m_sh2_state->target);
- generate_update_cycles(block, compiler, mem(&m_sh2_state->target), TRUE); // <subtract cycles>
+ generate_update_cycles(block, compiler, mem(&m_sh2_state->target), true); // <subtract cycles>
UML_HASHJMP(block, 0, mem(&m_sh2_state->target), *m_nocode); // jmp target
- return TRUE;
+ return true;
}
break;
case 0x28: // CLRMAC();
UML_MOV(block, mem(&m_sh2_state->macl), 0); // mov macl, #0
UML_MOV(block, mem(&m_sh2_state->mach), 0); // mov mach, #0
- return TRUE;
+ return true;
case 0x29: // MOVT(Rn);
UML_AND(block, R32(Rn), mem(&m_sh2_state->sr), T); // and Rn, sr, T
- return TRUE;
+ return true;
case 0x2a: // STSPR(Rn);
UML_MOV(block, R32(Rn), mem(&m_sh2_state->pr)); // mov Rn, pr
- return TRUE;
+ return true;
case 0x2b: // RTE();
generate_delay_slot(block, compiler, desc, 0xffffffff);
@@ -1838,18 +1838,18 @@ int sh2_device::generate_group_0(drcuml_block *block, compiler_state *compiler,
UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov sr, r0
UML_ADD(block, R32(15), R32(15), 4); // add R15, R15, #4
- compiler->checkints = TRUE;
+ compiler->checkints = true;
UML_MOV(block, mem(&m_sh2_state->ea), mem(&m_sh2_state->pc)); // mov ea, pc
- generate_update_cycles(block, compiler, mem(&m_sh2_state->ea), TRUE); // <subtract cycles>
+ generate_update_cycles(block, compiler, mem(&m_sh2_state->ea), true); // <subtract cycles>
UML_HASHJMP(block, 0, mem(&m_sh2_state->pc), *m_nocode); // and jump to the "resume PC"
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
-int sh2_device::generate_group_2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
+bool sh2_device::generate_group_2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
switch (opcode & 15)
{
@@ -1859,8 +1859,8 @@ int sh2_device::generate_group_2(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write8);
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 1: // MOVWS(Rm, Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
@@ -1868,8 +1868,8 @@ int sh2_device::generate_group_2(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write16);
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 2: // MOVLS(Rm, Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
@@ -1877,11 +1877,11 @@ int sh2_device::generate_group_2(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write32);
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 3:
- return FALSE;
+ return false;
case 4: // MOVBM(Rm, Rn);
UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
@@ -1890,8 +1890,8 @@ int sh2_device::generate_group_2(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write8); // call write8
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 5: // MOVWM(Rm, Rn);
UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
@@ -1900,8 +1900,8 @@ int sh2_device::generate_group_2(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write16); // call write16
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 6: // MOVLM(Rm, Rn);
UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
@@ -1910,8 +1910,8 @@ int sh2_device::generate_group_2(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 13: // XTRCT(Rm, Rn);
UML_SHL(block, I0, R32(Rm), 16); // shl r0, Rm, #16
@@ -1921,7 +1921,7 @@ int sh2_device::generate_group_2(drcuml_block *block, compiler_state *compiler,
UML_AND(block, I1, I1, 0xffff); // and r1, r1, #0x0000ffff
UML_OR(block, R32(Rn), I0, I1); // or Rn, r0, r1
- return TRUE;
+ return true;
case 7: // DIV0S(Rm, Rn);
UML_MOV(block, I0, mem(&m_sh2_state->sr)); // move r0, sr
@@ -1946,7 +1946,7 @@ int sh2_device::generate_group_2(drcuml_block *block, compiler_state *compiler,
UML_OR(block, I0, I0, T); // or r0, r0, T
UML_LABEL(block, compiler->labelnum++); // labelnum:
UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov sr, r0
- return TRUE;
+ return true;
case 8: // TST(Rm, Rn);
UML_AND(block, I0, mem(&m_sh2_state->sr), ~T); // and r0, sr, ~T (clear the T bit)
@@ -1957,7 +1957,7 @@ int sh2_device::generate_group_2(drcuml_block *block, compiler_state *compiler,
UML_LABEL(block, compiler->labelnum++); // desc->pc:
UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov m_sh2_state->sr, r0
- return TRUE;
+ return true;
case 12: // CMPSTR(Rm, Rn);
UML_XOR(block, I0, R32(Rn), R32(Rm)); // xor r0, Rn, Rm (temp)
@@ -1988,37 +1988,37 @@ int sh2_device::generate_group_2(drcuml_block *block, compiler_state *compiler,
UML_OR(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), T); // or sr, sr, T
UML_LABEL(block, compiler->labelnum++); // labelnum+1:
- return TRUE;
+ return true;
case 9: // AND(Rm, Rn);
UML_AND(block, R32(Rn), R32(Rn), R32(Rm)); // and Rn, Rn, Rm
- return TRUE;
+ return true;
case 10: // XOR(Rm, Rn);
UML_XOR(block, R32(Rn), R32(Rn), R32(Rm)); // xor Rn, Rn, Rm
- return TRUE;
+ return true;
case 11: // OR(Rm, Rn);
UML_OR(block, R32(Rn), R32(Rn), R32(Rm)); // or Rn, Rn, Rm
- return TRUE;
+ return true;
case 14: // MULU(Rm, Rn);
UML_AND(block, I0, R32(Rm), 0xffff); // and r0, Rm, 0xffff
UML_AND(block, I1, R32(Rn), 0xffff); // and r1, Rn, 0xffff
UML_MULU(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->ea), I0, I1); // mulu macl, ea, r0, r1
- return TRUE;
+ return true;
case 15: // MULS(Rm, Rn);
UML_SEXT(block, I0, R32(Rm), SIZE_WORD); // sext r0, Rm
UML_SEXT(block, I1, R32(Rn), SIZE_WORD); // sext r1, Rn
UML_MULS(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->ea), I0, I1); // muls macl, ea, r0, r1
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
-int sh2_device::generate_group_3(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, uint32_t ovrpc)
+bool sh2_device::generate_group_3(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, uint32_t ovrpc)
{
switch (opcode & 15)
{
@@ -2026,48 +2026,48 @@ int sh2_device::generate_group_3(drcuml_block *block, compiler_state *compiler,
UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
UML_SETc(block, COND_E, I0); // set E, r0
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
- return TRUE;
+ return true;
case 2: // CMPHS(Rm, Rn); (unsigned greater than or equal)
UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
UML_SETc(block, COND_AE, I0); // set AE, r0
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
- return TRUE;
+ return true;
case 3: // CMPGE(Rm, Rn); (signed greater than or equal)
UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
UML_SETc(block, COND_GE, I0); // set GE, r0
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
- return TRUE;
+ return true;
case 6: // CMPHI(Rm, Rn); (unsigned greater than)
UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
UML_SETc(block, COND_A, I0); // set A, r0
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
- return TRUE;
+ return true;
case 7: // CMPGT(Rm, Rn); (signed greater than)
UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
UML_SETc(block, COND_G, I0); // set G, r0
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
- return TRUE;
+ return true;
case 1:
case 9:
- return FALSE;
+ return false;
case 4: // DIV1(Rm, Rn);
save_fast_iregs(block);
UML_MOV(block, mem(&m_sh2_state->arg0), desc->opptr.w[0]);
UML_CALLC(block, cfunc_DIV1, this);
load_fast_iregs(block);
- return TRUE;
+ return true;
case 5: // DMULU(Rm, Rn);
if (m_cpu_type > CPU_TYPE_SH1)
{
UML_MULU(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->mach), R32(Rn), R32(Rm));
- return TRUE;
+ return true;
}
break;
@@ -2075,24 +2075,24 @@ int sh2_device::generate_group_3(drcuml_block *block, compiler_state *compiler,
if (m_cpu_type > CPU_TYPE_SH1)
{
UML_MULS(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->mach), R32(Rn), R32(Rm));
- return TRUE;
+ return true;
}
break;
case 8: // SUB(Rm, Rn);
UML_SUB(block, R32(Rn), R32(Rn), R32(Rm)); // sub Rn, Rn, Rm
- return TRUE;
+ return true;
case 12: // ADD(Rm, Rn);
UML_ADD(block, R32(Rn), R32(Rn), R32(Rm)); // add Rn, Rn, Rm
- return TRUE;
+ return true;
case 10: // SUBC(Rm, Rn);
UML_CARRY(block, mem(&m_sh2_state->sr), 0); // carry = T (T is bit 0 of SR)
UML_SUBB(block, R32(Rn), R32(Rn), R32(Rm)); // addc Rn, Rn, Rm
UML_SETc(block, COND_C, I0); // setc i0, C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, T); // rolins sr,i0,0,T
- return TRUE;
+ return true;
case 11: // SUBV(Rm, Rn);
#if ADDSUBV_DIRECT
@@ -2105,14 +2105,14 @@ int sh2_device::generate_group_3(drcuml_block *block, compiler_state *compiler,
UML_CALLC(block, cfunc_SUBV, this);
load_fast_iregs(block);
#endif
- return TRUE;
+ return true;
case 14: // ADDC(Rm, Rn);
UML_CARRY(block, mem(&m_sh2_state->sr), 0); // carry = T (T is bit 0 of SR)
UML_ADDC(block, R32(Rn), R32(Rn), R32(Rm)); // addc Rn, Rn, Rm
UML_SETc(block, COND_C, I0); // setc i0, C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, T); // rolins sr,i0,0,T
- return TRUE;
+ return true;
case 15: // ADDV(Rm, Rn);
#if ADDSUBV_DIRECT
@@ -2125,12 +2125,12 @@ int sh2_device::generate_group_3(drcuml_block *block, compiler_state *compiler,
UML_CALLC(block, cfunc_ADDV, this);
load_fast_iregs(block);
#endif
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
-int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
+bool sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
switch (opcode & 0x3F)
{
@@ -2138,25 +2138,25 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_SHL(block, R32(Rn), R32(Rn), 1); // shl Rn, Rn, 1
UML_SETc(block, COND_C, I0); // set i0,C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, T); // rolins [sr],i0,0,T
- return TRUE;
+ return true;
case 0x01: // SHLR(Rn);
UML_SHR(block, R32(Rn), R32(Rn), 1); // shr Rn, Rn, 1
UML_SETc(block, COND_C, I0); // set i0,C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, T); // rolins [sr],i0,0,T
- return TRUE;
+ return true;
case 0x04: // ROTL(Rn);
UML_ROL(block, R32(Rn), R32(Rn), 1); // rol Rn, Rn, 1
UML_SETc(block, COND_C, I0); // set i0,C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, T); // rolins [sr],i0,0,T
- return TRUE;
+ return true;
case 0x05: // ROTR(Rn);
UML_ROR(block, R32(Rn), R32(Rn), 1); // ror Rn, Rn, 1
UML_SETc(block, COND_C, I0); // set i0,C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, T); // rolins [sr],i0,0,T
- return TRUE;
+ return true;
case 0x02: // STSMMACH(Rn);
UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4
@@ -2166,8 +2166,8 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x03: // STCMSR(Rn);
UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4
@@ -2177,8 +2177,8 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x06: // LDSMMACH(Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
@@ -2188,8 +2188,8 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_MOV(block, mem(&m_sh2_state->mach), I0); // mov mach, r0
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x07: // LDCMSR(Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
@@ -2198,39 +2198,39 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, #4
UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov sr, r0
- compiler->checkints = TRUE;
+ compiler->checkints = true;
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x08: // SHLL2(Rn);
UML_SHL(block, R32(Rn), R32(Rn), 2);
- return TRUE;
+ return true;
case 0x09: // SHLR2(Rn);
UML_SHR(block, R32(Rn), R32(Rn), 2);
- return TRUE;
+ return true;
case 0x18: // SHLL8(Rn);
UML_SHL(block, R32(Rn), R32(Rn), 8);
- return TRUE;
+ return true;
case 0x19: // SHLR8(Rn);
UML_SHR(block, R32(Rn), R32(Rn), 8);
- return TRUE;
+ return true;
case 0x28: // SHLL16(Rn);
UML_SHL(block, R32(Rn), R32(Rn), 16);
- return TRUE;
+ return true;
case 0x29: // SHLR16(Rn);
UML_SHR(block, R32(Rn), R32(Rn), 16);
- return TRUE;
+ return true;
case 0x0a: // LDSMACH(Rn);
UML_MOV(block, mem(&m_sh2_state->mach), R32(Rn)); // mov mach, Rn
- return TRUE;
+ return true;
case 0x0b: // JSR(Rn);
UML_MOV(block, mem(&m_sh2_state->target), R32(Rn)); // mov target, Rn
@@ -2239,17 +2239,17 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
generate_delay_slot(block, compiler, desc, m_sh2_state->target-4);
- generate_update_cycles(block, compiler, mem(&m_sh2_state->target), TRUE); // <subtract cycles>
+ generate_update_cycles(block, compiler, mem(&m_sh2_state->target), true); // <subtract cycles>
UML_HASHJMP(block, 0, mem(&m_sh2_state->target), *m_nocode); // and do the jump
- return TRUE;
+ return true;
case 0x0e: // LDCSR(Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
UML_AND(block, I0, I0, FLAGS); // and r0, r0, FLAGS
UML_MOV(block, mem(&m_sh2_state->sr), I0);
- compiler->checkints = TRUE;
- return TRUE;
+ compiler->checkints = true;
+ return true;
case 0x0f: // MAC_W(Rm, Rn);
case 0x1f: // MAC_W(Rm, Rn);
@@ -2259,7 +2259,7 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_MOV(block, mem(&m_sh2_state->arg0), desc->opptr.w[0]);
UML_CALLC(block, cfunc_MAC_W, this);
load_fast_iregs(block);
- return TRUE;
+ return true;
case 0x10: // DT(Rn);
if (m_cpu_type > CPU_TYPE_SH1)
@@ -2272,7 +2272,7 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_LABEL(block, compiler->labelnum++); // desc->pc:
UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov m_sh2_state->sr, r0
- return TRUE;
+ return true;
}
break;
@@ -2286,7 +2286,7 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_LABEL(block, compiler->labelnum++); // desc->pc:
UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov m_sh2_state->sr, r0
- return TRUE;
+ return true;
case 0x15: // CMPPL(Rn);
UML_AND(block, I0, mem(&m_sh2_state->sr), ~T); // and r0, sr, ~T (clear the T bit)
@@ -2300,7 +2300,7 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_LABEL(block, compiler->labelnum++); // desc->pc:
UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov m_sh2_state->sr, r0
- return TRUE;
+ return true;
case 0x12: // STSMMACL(Rn);
UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4
@@ -2310,8 +2310,8 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x13: // STCMGBR(Rn);
UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4
@@ -2321,8 +2321,8 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x16: // LDSMMACL(Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
@@ -2332,8 +2332,8 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_MOV(block, mem(&m_sh2_state->macl), I0); // mov macl, r0
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x17: // LDCMGBR(Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
@@ -2343,12 +2343,12 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_MOV(block, mem(&m_sh2_state->gbr), I0); // mov gbr, r0
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x1a: // LDSMACL(Rn);
UML_MOV(block, mem(&m_sh2_state->macl), R32(Rn)); // mov macl, Rn
- return TRUE;
+ return true;
case 0x1b: // TAS(Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
@@ -2370,12 +2370,12 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write8); // write the value back
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x1e: // LDCGBR(Rn);
UML_MOV(block, mem(&m_sh2_state->gbr), R32(Rn)); // mov gbr, Rn
- return TRUE;
+ return true;
case 0x20: // SHAL(Rn);
UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~T); // and sr, sr, ~T
@@ -2383,14 +2383,14 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_AND(block, I0, I0, T); // and r0, r0, T
UML_OR(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), I0); // or sr, sr, r0
UML_SHL(block, R32(Rn), R32(Rn), 1); // shl Rn, Rn, 1
- return TRUE;
+ return true;
case 0x21: // SHAR(Rn);
UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~T); // and sr, sr, ~T
UML_AND(block, I0, R32(Rn), T); // and r0, Rn, T
UML_OR(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), I0); // or sr, sr, r0
UML_SAR(block, R32(Rn), R32(Rn), 1); // sar Rn, Rn, 1
- return TRUE;
+ return true;
case 0x22: // STSMPR(Rn);
UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, 4
@@ -2400,8 +2400,8 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x23: // STCMVBR(Rn);
UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, 4
@@ -2411,22 +2411,22 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x24: // ROTCL(Rn);
UML_CARRY(block, mem(&m_sh2_state->sr), 0); // carry sr,0
UML_ROLC(block, R32(Rn), R32(Rn), 1); // rolc Rn,Rn,1
UML_SETc(block, COND_C, I0); // set i0,C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, T); // rolins sr,i0,0,T
- return TRUE;
+ return true;
case 0x25: // ROTCR(Rn);
UML_CARRY(block, mem(&m_sh2_state->sr), 0); // carry sr,0
UML_RORC(block, R32(Rn), R32(Rn), 1); // rorc Rn,Rn,1
UML_SETc(block, COND_C, I0); // set i0,C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, T); // rolins sr,i0,0,T
- return TRUE;
+ return true;
case 0x26: // LDSMPR(Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
@@ -2436,8 +2436,8 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, Rn, #4
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x27: // LDCMVBR(Rn);
UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
@@ -2447,25 +2447,25 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, Rn, #4
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 0x2a: // LDSPR(Rn);
UML_MOV(block, mem(&m_sh2_state->pr), R32(Rn)); // mov m_pr, Rn
- return TRUE;
+ return true;
case 0x2b: // JMP(Rn);
UML_MOV(block, mem(&m_sh2_state->target), R32(Rn)); // mov target, Rn
generate_delay_slot(block, compiler, desc, m_sh2_state->target);
- generate_update_cycles(block, compiler, mem(&m_sh2_state->target), TRUE); // <subtract cycles>
+ generate_update_cycles(block, compiler, mem(&m_sh2_state->target), true); // <subtract cycles>
UML_HASHJMP(block, 0, mem(&m_sh2_state->target), *m_nocode); // jmp (target)
- return TRUE;
+ return true;
case 0x2e: // LDCVBR(Rn);
UML_MOV(block, mem(&m_sh2_state->vbr), R32(Rn)); // mov vbr, Rn
- return TRUE;
+ return true;
case 0x0c:
case 0x0d:
@@ -2489,13 +2489,13 @@ int sh2_device::generate_group_4(drcuml_block *block, compiler_state *compiler,
case 0x3c:
case 0x3d:
case 0x3e:
- return FALSE;
+ return false;
}
- return FALSE;
+ return false;
}
-int sh2_device::generate_group_6(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
+bool sh2_device::generate_group_6(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
switch (opcode & 15)
{
@@ -2506,8 +2506,8 @@ int sh2_device::generate_group_6(drcuml_block *block, compiler_state *compiler,
UML_SEXT(block, R32(Rn), I0, SIZE_BYTE); // sext Rn, r0, BYTE
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 1: // MOVWL(Rm, Rn);
UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
@@ -2516,8 +2516,8 @@ int sh2_device::generate_group_6(drcuml_block *block, compiler_state *compiler,
UML_SEXT(block, R32(Rn), I0, SIZE_WORD); // sext Rn, r0, WORD
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 2: // MOVLL(Rm, Rn);
UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
@@ -2526,40 +2526,40 @@ int sh2_device::generate_group_6(drcuml_block *block, compiler_state *compiler,
UML_MOV(block, R32(Rn), I0); // mov Rn, r0
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 3: // MOV(Rm, Rn);
UML_MOV(block, R32(Rn), R32(Rm)); // mov Rn, Rm
- return TRUE;
+ return true;
case 7: // NOT(Rm, Rn);
UML_XOR(block, R32(Rn), R32(Rm), 0xffffffff); // xor Rn, Rm, 0xffffffff
- return TRUE;
+ return true;
case 9: // SWAPW(Rm, Rn);
UML_ROL(block, R32(Rn), R32(Rm), 16); // rol Rn, Rm, 16
- return TRUE;
+ return true;
case 11: // NEG(Rm, Rn);
UML_SUB(block, R32(Rn), 0, R32(Rm)); // sub Rn, 0, Rm
- return TRUE;
+ return true;
case 12: // EXTUB(Rm, Rn);
UML_AND(block, R32(Rn), R32(Rm), 0x000000ff); // and Rn, Rm, 0xff
- return TRUE;
+ return true;
case 13: // EXTUW(Rm, Rn);
UML_AND(block, R32(Rn), R32(Rm), 0x0000ffff); // and Rn, Rm, 0xffff
- return TRUE;
+ return true;
case 14: // EXTSB(Rm, Rn);
UML_SEXT(block, R32(Rn), R32(Rm), SIZE_BYTE); // sext Rn, Rm, BYTE
- return TRUE;
+ return true;
case 15: // EXTSW(Rm, Rn);
UML_SEXT(block, R32(Rn), R32(Rm), SIZE_WORD); // sext Rn, Rm, WORD
- return TRUE;
+ return true;
case 4: // MOVBP(Rm, Rn);
UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
@@ -2570,8 +2570,8 @@ int sh2_device::generate_group_6(drcuml_block *block, compiler_state *compiler,
UML_ADD(block, R32(Rm), R32(Rm), 1); // add Rm, Rm, #1
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 5: // MOVWP(Rm, Rn);
UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
@@ -2582,8 +2582,8 @@ int sh2_device::generate_group_6(drcuml_block *block, compiler_state *compiler,
UML_ADD(block, R32(Rm), R32(Rm), 2); // add Rm, Rm, #2
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 6: // MOVLP(Rm, Rn);
UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
@@ -2594,8 +2594,8 @@ int sh2_device::generate_group_6(drcuml_block *block, compiler_state *compiler,
UML_ADD(block, R32(Rm), R32(Rm), 4); // add Rm, Rm, #4
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 8: // SWAPB(Rm, Rn);
UML_AND(block, I0, R32(Rm), 0xffff0000); // and r0, Rm, #0xffff0000
@@ -2605,7 +2605,7 @@ int sh2_device::generate_group_6(drcuml_block *block, compiler_state *compiler,
UML_SHR(block, I2, I2, 8); // shr r2, r2, #8
UML_OR(block, I0, I0, I1); // or r0, r0, r1
UML_OR(block, R32(Rn), I0, I2); // or Rn, r0, r2
- return TRUE;
+ return true;
case 10: // NEGC(Rm, Rn);
UML_MOV(block, I0, mem(&m_sh2_state->sr)); // mov r0, sr (save SR)
@@ -2619,13 +2619,13 @@ int sh2_device::generate_group_6(drcuml_block *block, compiler_state *compiler,
UML_LABEL(block, compiler->labelnum++); // labelnum:
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
-int sh2_device::generate_group_8(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
+bool sh2_device::generate_group_8(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
int32_t disp;
uint32_t udisp;
@@ -2640,8 +2640,8 @@ int sh2_device::generate_group_8(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write8); // call write8
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 1 << 8: // MOVWS4(opcode & 0x0f, Rm);
udisp = (opcode & 0x0f) * 2;
@@ -2650,8 +2650,8 @@ int sh2_device::generate_group_8(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write16); // call write16
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 2<< 8:
case 3<< 8:
@@ -2660,7 +2660,7 @@ int sh2_device::generate_group_8(drcuml_block *block, compiler_state *compiler,
case 10<< 8:
case 12<< 8:
case 14<< 8:
- return FALSE;
+ return false;
case 4<< 8: // MOVBL4(Rm, opcode & 0x0f);
udisp = opcode & 0x0f;
@@ -2670,8 +2670,8 @@ int sh2_device::generate_group_8(drcuml_block *block, compiler_state *compiler,
UML_SEXT(block, R32(0), I0, SIZE_BYTE); // sext R0, r0, BYTE
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 5<< 8: // MOVWL4(Rm, opcode & 0x0f);
udisp = (opcode & 0x0f)*2;
@@ -2681,8 +2681,8 @@ int sh2_device::generate_group_8(drcuml_block *block, compiler_state *compiler,
UML_SEXT(block, R32(0), I0, SIZE_WORD); // sext R0, r0, WORD
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 8<< 8: // CMPIM(opcode & 0xff);
UML_AND(block, I0, mem(&m_sh2_state->sr), ~T); // and r0, sr, ~T (clear the T bit)
@@ -2695,7 +2695,7 @@ int sh2_device::generate_group_8(drcuml_block *block, compiler_state *compiler,
UML_LABEL(block, compiler->labelnum++); // labelnum:
UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov m_sh2_state->sr, r0
- return TRUE;
+ return true;
case 9<< 8: // BT(opcode & 0xff);
UML_TEST(block, mem(&m_sh2_state->sr), T); // test m_sh2_state->sr, T
@@ -2704,11 +2704,11 @@ int sh2_device::generate_group_8(drcuml_block *block, compiler_state *compiler,
disp = ((int32_t)opcode << 24) >> 24;
m_sh2_state->ea = (desc->pc + 2) + disp * 2 + 2; // m_sh2_state->ea = destination
- generate_update_cycles(block, compiler, m_sh2_state->ea, TRUE); // <subtract cycles>
+ generate_update_cycles(block, compiler, m_sh2_state->ea, true); // <subtract cycles>
UML_HASHJMP(block, 0, m_sh2_state->ea, *m_nocode); // jmp m_sh2_state->ea
UML_LABEL(block, compiler->labelnum++); // labelnum:
- return TRUE;
+ return true;
case 11<< 8: // BF(opcode & 0xff);
UML_TEST(block, mem(&m_sh2_state->sr), T); // test m_sh2_state->sr, T
@@ -2717,11 +2717,11 @@ int sh2_device::generate_group_8(drcuml_block *block, compiler_state *compiler,
disp = ((int32_t)opcode << 24) >> 24;
m_sh2_state->ea = (desc->pc + 2) + disp * 2 + 2; // m_sh2_state->ea = destination
- generate_update_cycles(block, compiler, m_sh2_state->ea, TRUE); // <subtract cycles>
+ generate_update_cycles(block, compiler, m_sh2_state->ea, true); // <subtract cycles>
UML_HASHJMP(block, 0, m_sh2_state->ea, *m_nocode); // jmp m_sh2_state->ea
UML_LABEL(block, compiler->labelnum++); // labelnum:
- return TRUE;
+ return true;
case 13<< 8: // BTS(opcode & 0xff);
if (m_cpu_type > CPU_TYPE_SH1)
@@ -2736,11 +2736,11 @@ int sh2_device::generate_group_8(drcuml_block *block, compiler_state *compiler,
compiler->labelnum++; // make sure the delay slot doesn't use it
generate_delay_slot(block, compiler, desc, m_sh2_state->ea-2);
- generate_update_cycles(block, compiler, m_sh2_state->ea, TRUE); // <subtract cycles>
+ generate_update_cycles(block, compiler, m_sh2_state->ea, true); // <subtract cycles>
UML_HASHJMP(block, 0, m_sh2_state->ea, *m_nocode); // jmp m_sh2_state->ea
UML_LABEL(block, templabel); // labelnum:
- return TRUE;
+ return true;
}
break;
@@ -2757,19 +2757,19 @@ int sh2_device::generate_group_8(drcuml_block *block, compiler_state *compiler,
compiler->labelnum++; // make sure the delay slot doesn't use it
generate_delay_slot(block, compiler, desc, m_sh2_state->ea-2); // delay slot only if the branch is taken
- generate_update_cycles(block, compiler, m_sh2_state->ea, TRUE); // <subtract cycles>
+ generate_update_cycles(block, compiler, m_sh2_state->ea, true); // <subtract cycles>
UML_HASHJMP(block, 0, m_sh2_state->ea, *m_nocode); // jmp m_sh2_state->ea
UML_LABEL(block, templabel); // labelnum:
- return TRUE;
+ return true;
}
break;
}
- return FALSE;
+ return false;
}
-int sh2_device::generate_group_12(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
+bool sh2_device::generate_group_12(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
uint32_t scratch;
@@ -2782,8 +2782,8 @@ int sh2_device::generate_group_12(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write8); // call write8
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 1<<8: // MOVWSG(opcode & 0xff);
scratch = (opcode & 0xff) * 2;
@@ -2792,8 +2792,8 @@ int sh2_device::generate_group_12(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write16); // call write16
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 2<<8: // MOVLSG(opcode & 0xff);
scratch = (opcode & 0xff) * 4;
@@ -2802,8 +2802,8 @@ int sh2_device::generate_group_12(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 3<<8: // TRAPA(opcode & 0xff);
scratch = (opcode & 0xff) * 4;
@@ -2823,7 +2823,7 @@ int sh2_device::generate_group_12(drcuml_block *block, compiler_state *compiler,
UML_CALLH(block, *m_read32); // read32
UML_HASHJMP(block, 0, I0, *m_nocode); // jmp (r0)
- return TRUE;
+ return true;
case 4<<8: // MOVBLG(opcode & 0xff);
scratch = (opcode & 0xff);
@@ -2832,8 +2832,8 @@ int sh2_device::generate_group_12(drcuml_block *block, compiler_state *compiler,
UML_SEXT(block, R32(0), I0, SIZE_BYTE); // sext R0, r0, BYTE
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 5<<8: // MOVWLG(opcode & 0xff);
scratch = (opcode & 0xff) * 2;
@@ -2842,8 +2842,8 @@ int sh2_device::generate_group_12(drcuml_block *block, compiler_state *compiler,
UML_SEXT(block, R32(0), I0, SIZE_WORD); // sext R0, r0, WORD
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 6<<8: // MOVLLG(opcode & 0xff);
scratch = (opcode & 0xff) * 4;
@@ -2852,15 +2852,15 @@ int sh2_device::generate_group_12(drcuml_block *block, compiler_state *compiler,
UML_MOV(block, R32(0), I0); // mov R0, r0
if (!in_delay_slot)
- generate_update_cycles(block, compiler, desc->pc + 2, TRUE);
- return TRUE;
+ generate_update_cycles(block, compiler, desc->pc + 2, true);
+ return true;
case 7<<8: // MOVA(opcode & 0xff);
scratch = (opcode & 0xff) * 4;
scratch += ((desc->pc + 4) & ~3);
UML_MOV(block, R32(0), scratch); // mov R0, scratch
- return TRUE;
+ return true;
case 8<<8: // TSTI(opcode & 0xff);
scratch = opcode & 0xff;
@@ -2873,19 +2873,19 @@ int sh2_device::generate_group_12(drcuml_block *block, compiler_state *compiler,
UML_OR(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), T); // or sr, sr, T
UML_LABEL(block, compiler->labelnum++); // labelnum:
- return TRUE;
+ return true;
case 9<<8: // ANDI(opcode & 0xff);
UML_AND(block, R32(0), R32(0), opcode & 0xff); // and r0, r0, opcode & 0xff
- return TRUE;
+ return true;
case 10<<8: // XORI(opcode & 0xff);
UML_XOR(block, R32(0), R32(0), opcode & 0xff); // xor r0, r0, opcode & 0xff
- return TRUE;
+ return true;
case 11<<8: // ORI(opcode & 0xff);
UML_OR(block, R32(0), R32(0), opcode & 0xff); // or r0, r0, opcode & 0xff
- return TRUE;
+ return true;
case 12<<8: // TSTM(opcode & 0xff);
UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~T); // and sr, sr, ~T (clear the T bit)
@@ -2899,7 +2899,7 @@ int sh2_device::generate_group_12(drcuml_block *block, compiler_state *compiler,
UML_OR(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), T); // or sr, sr, T
UML_LABEL(block, compiler->labelnum++); // labelnum:
- return TRUE;
+ return true;
case 13<<8: // ANDM(opcode & 0xff);
UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
@@ -2909,7 +2909,7 @@ int sh2_device::generate_group_12(drcuml_block *block, compiler_state *compiler,
UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
SETEA(0);
UML_CALLH(block, *m_write8); // write8
- return TRUE;
+ return true;
case 14<<8: // XORM(opcode & 0xff);
UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
@@ -2919,7 +2919,7 @@ int sh2_device::generate_group_12(drcuml_block *block, compiler_state *compiler,
UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
SETEA(0);
UML_CALLH(block, *m_write8); // write8
- return TRUE;
+ return true;
case 15<<8: // ORM(opcode & 0xff);
UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
@@ -2929,10 +2929,10 @@ int sh2_device::generate_group_12(drcuml_block *block, compiler_state *compiler,
UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
SETEA(0);
UML_CALLH(block, *m_write8); // write8
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/***************************************************************************
diff --git a/src/devices/cpu/sh4/sh4.cpp b/src/devices/cpu/sh4/sh4.cpp
index 481566905a1..831804260a8 100644
--- a/src/devices/cpu/sh4/sh4.cpp
+++ b/src/devices/cpu/sh4/sh4.cpp
@@ -338,7 +338,7 @@ inline void sh34_base_device::WB(offs_t A, uint8_t V)
const offs_t _A = A & AM;
for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
{
- if (m_fastram[ramnum].readonly == TRUE || _A < m_fastram[ramnum].start || _A > m_fastram[ramnum].end)
+ if (m_fastram[ramnum].readonly == true || _A < m_fastram[ramnum].start || _A > m_fastram[ramnum].end)
{
continue;
}
@@ -364,7 +364,7 @@ inline void sh34_base_device::WW(offs_t A, uint16_t V)
const offs_t _A = A & AM;
for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
{
- if (m_fastram[ramnum].readonly == TRUE || _A < m_fastram[ramnum].start || _A > m_fastram[ramnum].end)
+ if (m_fastram[ramnum].readonly == true || _A < m_fastram[ramnum].start || _A > m_fastram[ramnum].end)
{
continue;
}
@@ -390,7 +390,7 @@ inline void sh34_base_device::WL(offs_t A, uint32_t V)
const offs_t _A = A & AM;
for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
{
- if (m_fastram[ramnum].readonly == TRUE || _A < m_fastram[ramnum].start || _A > m_fastram[ramnum].end)
+ if (m_fastram[ramnum].readonly == true || _A < m_fastram[ramnum].start || _A > m_fastram[ramnum].end)
{
continue;
}
diff --git a/src/devices/cpu/sh4/sh4.h b/src/devices/cpu/sh4/sh4.h
index 0b8f33926f5..9af8dd3fa1c 100644
--- a/src/devices/cpu/sh4/sh4.h
+++ b/src/devices/cpu/sh4/sh4.h
@@ -703,7 +703,7 @@ protected:
{
offs_t start; /* start of the RAM block */
offs_t end; /* end of the RAM block */
- uint8_t readonly; /* TRUE if read-only */
+ bool readonly; /* true if read-only */
void * base; /* base in memory where the RAM lives */
} m_fastram[SH4_MAX_FASTRAM];
#endif
diff --git a/src/devices/cpu/sharc/sharc.h b/src/devices/cpu/sharc/sharc.h
index 49853a44602..bf3ae7edaa5 100644
--- a/src/devices/cpu/sharc/sharc.h
+++ b/src/devices/cpu/sharc/sharc.h
@@ -623,8 +623,8 @@ private:
void load_fast_iregs(drcuml_block *block);
void save_fast_iregs(drcuml_block *block);
void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, bool last_delayslot);
- void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
- int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+ void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception);
+ bool generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
void generate_unimplemented_compute(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
void generate_compute(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
void generate_if_condition(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, int condition, int skip_label);
diff --git a/src/devices/cpu/sharc/sharcdrc.cpp b/src/devices/cpu/sharc/sharcdrc.cpp
index a2422f1f8fc..75c0647da9f 100644
--- a/src/devices/cpu/sharc/sharcdrc.cpp
+++ b/src/devices/cpu/sharc/sharcdrc.cpp
@@ -1202,7 +1202,7 @@ void adsp21062_device::compile_block(offs_t pc)
/* count off cycles and go there */
- generate_update_cycles(block, &compiler, nextpc, TRUE); // <subtract cycles>
+ generate_update_cycles(block, &compiler, nextpc, true); // <subtract cycles>
if (seqlast->next() == nullptr || seqlast->next()->pc != nextpc)
UML_HASHJMP(block, 0, nextpc, *m_nocode); // hashjmp <mode>,nextpc,nocode
@@ -1536,13 +1536,13 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil
}
}
-void adsp21062_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception)
+void adsp21062_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception)
{
/* check full interrupts if pending */
if (compiler->checkints)
{
code_label skip = compiler->labelnum++;
- compiler->checkints = FALSE;
+ compiler->checkints = false;
UML_CMP(block, mem(&m_core->irq_pending), 0); // cmp [irq_pending],0
UML_JMPc(block, COND_E, skip); // je skip
@@ -1854,7 +1854,7 @@ void adsp21062_device::generate_call(drcuml_block *block, compiler_state *compil
// update cycles and hash jump
if (desc->targetpc != BRANCH_TARGET_DYNAMIC)
{
- generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE);
+ generate_update_cycles(block, &compiler_temp, desc->targetpc, true);
if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000
else
@@ -1862,7 +1862,7 @@ void adsp21062_device::generate_call(drcuml_block *block, compiler_state *compil
}
else
{
- generate_update_cycles(block, &compiler_temp, mem(&m_core->jmpdest), TRUE);
+ generate_update_cycles(block, &compiler_temp, mem(&m_core->jmpdest), true);
UML_HASHJMP(block, 0, mem(&m_core->jmpdest), *m_nocode); // hashjmp 0,jmpdest,nocode
}
@@ -1917,7 +1917,7 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil
// update cycles and hash jump
if (desc->targetpc != BRANCH_TARGET_DYNAMIC)
{
- generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE);
+ generate_update_cycles(block, &compiler_temp, desc->targetpc, true);
if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000
else
@@ -1925,7 +1925,7 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil
}
else
{
- generate_update_cycles(block, &compiler_temp, mem(&m_core->jmpdest), TRUE);
+ generate_update_cycles(block, &compiler_temp, mem(&m_core->jmpdest), true);
UML_HASHJMP(block, 0, mem(&m_core->jmpdest), *m_nocode); // hashjmp 0,jmpdest,nocode
}
@@ -1940,7 +1940,7 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil
void adsp21062_device::generate_loop_jump(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
// update cycles and hash jump
- generate_update_cycles(block, compiler, desc->userdata0, TRUE);
+ generate_update_cycles(block, compiler, desc->userdata0, true);
/*
if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
UML_JMP(block, desc->targetpc | 0x80000000); // jmp targetpc | 0x80000000
@@ -2280,7 +2280,7 @@ void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state *
}
}
-int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
{
uint64_t opcode = desc->opptr.q[0];
@@ -2297,12 +2297,12 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
// IDLE
UML_MOV(block, mem(&m_core->idle), 1);
UML_MOV(block, mem(&m_core->icount), 0);
- return TRUE;
+ return true;
}
else
{
// NOP
- return TRUE;
+ return true;
}
break;
@@ -2323,7 +2323,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
if (has_condition)
UML_LABEL(block, skip_label);
- return TRUE;
+ return true;
}
case 0x02: // immediate shift |000|00010|
@@ -2347,7 +2347,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
if (has_condition)
UML_LABEL(block, skip_label);
- return TRUE;
+ return true;
}
case 0x04: // compute / modify |000|00100|
@@ -2384,7 +2384,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
if (has_condition)
UML_LABEL(block, skip_label);
- return TRUE;
+ return true;
}
case 0x06: // direct jump|call |000|00110|
@@ -2413,7 +2413,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
}
if (has_condition)
UML_LABEL(block, skip_label);
- return TRUE;
+ return true;
}
case 0x07: // direct jump|call |000|00111|
@@ -2442,7 +2442,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
}
if (has_condition)
UML_LABEL(block, skip_label);
- return TRUE;
+ return true;
}
case 0x08: // indirect jump|call / compute |000|01000|
@@ -2505,7 +2505,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
UML_LABEL(block, skip_label);
}
- return TRUE;
+ return true;
}
case 0x09: // indirect jump|call / compute |000|01001|
@@ -2562,7 +2562,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
UML_LABEL(block, skip_label);
}
- return TRUE;
+ return true;
}
case 0x0a: // return from subroutine / compute |000|01010|
@@ -2607,7 +2607,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
UML_LABEL(block, skip_label);
}
- return TRUE;
+ return true;
}
case 0x0b: // return from interrupt / compute |000|01011|
@@ -2664,7 +2664,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
UML_LABEL(block, skip_label);
}
- return TRUE;
+ return true;
}
case 0x0c: // do until counter expired |000|01100|
@@ -2685,7 +2685,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
UML_MOV(block, I1, address);
UML_CALLH(block, *m_push_loop);
}
- return TRUE;
+ return true;
}
case 0x0d: // do until counter expired |000|01101|
@@ -2707,7 +2707,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
UML_MOV(block, I0, I3);
UML_MOV(block, I1, address);
UML_CALLH(block, *m_push_loop);
- return TRUE;
+ return true;
}
case 0x0e: // do until |000|01110|
@@ -2723,7 +2723,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
UML_MOV(block, I0, 0);
UML_MOV(block, I1, address);
UML_CALLH(block, *m_push_loop);
- return TRUE;
+ return true;
}
case 0x0f: // immediate data -> ureg |000|01111|
@@ -2732,7 +2732,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
uint32_t data = (uint32_t)opcode;
generate_write_ureg(block, compiler, desc, ureg, true, data);
- return TRUE;
+ return true;
}
case 0x10: // ureg <-> DM|PM (direct) |000|100|G|D|
@@ -2784,7 +2784,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
generate_write_ureg(block, compiler, desc, ureg, false, 0);
}
- return TRUE;
+ return true;
}
case 0x14: // system register bit manipulation |000|10100|
@@ -2872,9 +2872,9 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
break;
default:
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
case 1: // CLEAR
{
@@ -2953,9 +2953,9 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
break;
default:
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
case 2: // TOGGLE
{
@@ -2979,7 +2979,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
compiler->mode1_delay.mode = MODE1_TOGGLE;
break;
case 0xc: // ASTAT
- return FALSE;
+ return false;
case 0xd: // IMASK
UML_XOR(block, IMASK, IMASK, data);
break;
@@ -2991,9 +2991,9 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
break;
default:
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
case 4: // TEST
{
@@ -3025,7 +3025,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
UML_SETc(block, COND_E, ASTAT_BTF);
break;
case 0xc: // ASTAT
- return FALSE;
+ return false;
case 0xd: // IMASK
UML_AND(block, I0, IMASK, data);
UML_CMP(block, I0, data);
@@ -3043,26 +3043,26 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
break;
default:
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
case 5: // XOR
{
- return FALSE;
+ return false;
}
default:
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
case 0x16: // I register modify / bit-reverse |000|10110|
{
if (opcode & U64(0x008000000000)) // bit reverse
{
- return FALSE;
+ return false;
}
else // modify
{
@@ -3081,7 +3081,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
UML_ADD(block, DM_I(i), DM_I(i), data);
}
generate_update_circular_buffer(block, compiler, desc, g, i);
- return TRUE;
+ return true;
}
}
@@ -3112,17 +3112,17 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
{
UML_CALLH(block, *m_pop_pc);
}
- return TRUE;
+ return true;
}
case 0x18: // cjump |000|11000|
- return FALSE;
+ return false;
case 0x19: // rframe |000|11001|
- return FALSE;
+ return false;
default:
- return FALSE;
+ return false;
}
break;
}
@@ -3199,7 +3199,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
UML_ADD(block, DM_I(dmi), DM_I(dmi), DM_M(dmm));
generate_update_circular_buffer(block, compiler, desc, 0, dmi);
}
- return TRUE;
+ return true;
}
case 2: // compute / ureg <-> DM|PM, register modify |010|
@@ -3290,7 +3290,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
if (has_condition)
UML_LABEL(block, skip_label);
- return TRUE;
+ return true;
}
case 3:
@@ -3341,7 +3341,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
if (has_condition)
UML_LABEL(block, skip_label);
- return TRUE;
+ return true;
}
else // compute / dreg <-> DM|PM, immediate modify |011|0|
{
@@ -3413,7 +3413,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
if (has_condition)
UML_LABEL(block, skip_label);
- return TRUE;
+ return true;
}
break;
}
@@ -3446,7 +3446,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
generate_update_circular_buffer(block, compiler, desc, g, i);
- return TRUE;
+ return true;
}
else // immediate shift / dreg <-> DM|PM |100|0|
{
@@ -3515,7 +3515,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
if (has_condition)
UML_LABEL(block, skip_label);
- return TRUE;
+ return true;
}
break;
}
@@ -3552,7 +3552,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
generate_write_ureg(block, compiler, desc, ureg, false, 0);
}
- return TRUE;
+ return true;
}
case 6: // indirect jump / compute / dreg <-> DM |110|
@@ -3613,7 +3613,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
generate_update_circular_buffer(block, compiler, desc, 0, dmi);
- return TRUE;
+ return true;
}
case 7: // indirect jump / compute / dreg <-> DM |111|
@@ -3671,11 +3671,11 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
generate_update_circular_buffer(block, compiler, desc, 0, dmi);
- return TRUE;
+ return true;
}
}
- return FALSE;
+ return false;
}
void adsp21062_device::generate_unimplemented_compute(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
@@ -5303,7 +5303,7 @@ void adsp21062_device::generate_if_condition(drcuml_block *block, compiler_state
case 0x1e: /* NOT BM */
fatalerror("generate_if_condition 0x1e"); // should not happen
break;
- case 0x1f: /* TRUE */
+ case 0x1f: /* true */
fatalerror("generate_if_condition 0x1f"); // should not happen
break;
}
@@ -5452,7 +5452,7 @@ void adsp21062_device::generate_do_condition(drcuml_block *block, compiler_state
// always true
UML_JMP(block, skip_label);
break;
- case 0x1f: /* FALSE (FOREVER) */
+ case 0x1f: /* false (FOREVER) */
// infinite loop
break;
}
diff --git a/src/devices/cpu/tms34010/tms34010.cpp b/src/devices/cpu/tms34010/tms34010.cpp
index 7cea0c14032..71dfb7cc49e 100644
--- a/src/devices/cpu/tms34010/tms34010.cpp
+++ b/src/devices/cpu/tms34010/tms34010.cpp
@@ -37,7 +37,7 @@ tms340x0_device::tms340x0_device(const machine_config &mconfig, device_type type
: cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__)
, device_video_interface(mconfig, *this)
, m_program_config("program", ENDIANNESS_LITTLE, 16, 32, 3), m_pc(0), m_ppc(0), m_st(0), m_pixel_write(nullptr), m_pixel_read(nullptr), m_raster_op(nullptr), m_pixel_op(nullptr), m_pixel_op_timing(0), m_convsp(0), m_convdp(0), m_convmp(0), m_gfxcycles(0), m_pixelshift(0), m_is_34020(0), m_reset_deferred(false)
- , m_halt_on_reset(FALSE), m_hblank_stable(0), m_external_host_access(0), m_executing(0), m_program(nullptr), m_direct(nullptr)
+ , m_halt_on_reset(false), m_hblank_stable(0), m_external_host_access(0), m_executing(0), m_program(nullptr), m_direct(nullptr)
, m_pixclock(0)
, m_pixperclock(0), m_scantimer(nullptr), m_icount(0)
, m_output_int_cb(*this)
@@ -577,7 +577,7 @@ void tms340x0_device::device_start()
m_to_shiftreg_cb.bind_relative_to(*owner());
m_from_shiftreg_cb.bind_relative_to(*owner());
- m_external_host_access = FALSE;
+ m_external_host_access = false;
m_program = &space(AS_PROGRAM);
m_direct = &m_program->direct();
@@ -720,12 +720,12 @@ void tms340x0_device::execute_run()
/* if the CPU's reset was deferred, do it now */
if (m_reset_deferred)
{
- m_reset_deferred = FALSE;
+ m_reset_deferred = false;
m_pc = RLONG(0xffffffe0);
}
/* check interrupts first */
- m_executing = TRUE;
+ m_executing = true;
check_interrupt();
if ((machine().debug_flags & DEBUG_FLAG_ENABLED) == 0)
{
@@ -748,7 +748,7 @@ void tms340x0_device::execute_run()
(this->*s_opcode_table[op >> 4])(op);
} while (m_icount > 0);
}
- m_executing = FALSE;
+ m_executing = false;
}
@@ -1526,10 +1526,10 @@ WRITE16_MEMBER( tms340x0_device::host_w )
/* control register */
case TMS34010_HOST_CONTROL:
{
- m_external_host_access = TRUE;
+ m_external_host_access = true;
if (mem_mask&0xff00) io_register_w(*m_program, REG_HSTCTLH, data & 0xff00, 0xff00);
if (mem_mask&0x00ff) io_register_w(*m_program, REG_HSTCTLL, data & 0x00ff, 0x00ff);
- m_external_host_access = FALSE;
+ m_external_host_access = false;
break;
}
diff --git a/src/devices/cpu/z80/z80.cpp b/src/devices/cpu/z80/z80.cpp
index a23dfbe4bf6..5fc267ac7da 100644
--- a/src/devices/cpu/z80/z80.cpp
+++ b/src/devices/cpu/z80/z80.cpp
@@ -665,7 +665,7 @@ inline void z80_device::ld_a_r()
{
A = (m_r & 0x7f) | m_r2;
F = (F & CF) | SZ[A] | (m_iff2 << 2);
- m_after_ldair = TRUE;
+ m_after_ldair = true;
}
/***************************************************************
@@ -683,7 +683,7 @@ inline void z80_device::ld_a_i()
{
A = m_i;
F = (F & CF) | SZ[A] | (m_iff2 << 2);
- m_after_ldair = TRUE;
+ m_after_ldair = true;
}
/***************************************************************
@@ -1359,7 +1359,7 @@ inline void z80_device::otdr()
inline void z80_device::ei()
{
m_iff1 = m_iff2 = 1;
- m_after_ei = TRUE;
+ m_after_ei = true;
}
/**********************************************************
@@ -3139,7 +3139,7 @@ void z80_device::take_nmi()
PCD = 0x0066;
WZ=PCD;
m_icount -= 11;
- m_nmi_pending = FALSE;
+ m_nmi_pending = false;
}
void z80_device::take_interrupt()
@@ -3475,9 +3475,9 @@ void z80_device::device_reset()
m_i = 0;
m_r = 0;
m_r2 = 0;
- m_nmi_pending = FALSE;
- m_after_ei = FALSE;
- m_after_ldair = FALSE;
+ m_nmi_pending = false;
+ m_after_ei = false;
+ m_after_ldair = false;
m_iff1 = 0;
m_iff2 = 0;
@@ -3510,8 +3510,8 @@ void z80_device::execute_run()
else if (m_irq_state != CLEAR_LINE && m_iff1 && !m_after_ei)
take_interrupt();
- m_after_ei = FALSE;
- m_after_ldair = FALSE;
+ m_after_ei = false;
+ m_after_ldair = false;
PRVPC = PCD;
debugger_instruction_hook(this, PCD);
@@ -3539,8 +3539,8 @@ void nsc800_device::execute_run()
else if (m_irq_state != CLEAR_LINE && m_iff1 && !m_after_ei)
take_interrupt();
- m_after_ei = FALSE;
- m_after_ldair = FALSE;
+ m_after_ei = false;
+ m_after_ldair = false;
PRVPC = PCD;
debugger_instruction_hook(this, PCD);
@@ -3560,7 +3560,7 @@ void z80_device::execute_set_input(int inputnum, int state)
case INPUT_LINE_NMI:
/* mark an NMI pending on the rising edge */
if (m_nmi_state == CLEAR_LINE && state != CLEAR_LINE)
- m_nmi_pending = TRUE;
+ m_nmi_pending = true;
m_nmi_state = state;
break;
diff --git a/src/devices/imagedev/flopdrv.cpp b/src/devices/imagedev/flopdrv.cpp
index 2533e09d516..ad0884d3379 100644
--- a/src/devices/imagedev/flopdrv.cpp
+++ b/src/devices/imagedev/flopdrv.cpp
@@ -781,7 +781,7 @@ void legacy_floppy_image_device::device_start()
floppy_drive_init();
m_drive_id = floppy_get_drive(this);
- m_active = FALSE;
+ m_active = false;
/* resolve callbacks */
m_out_idx_func.resolve_safe();
diff --git a/src/devices/imagedev/printer.cpp b/src/devices/imagedev/printer.cpp
index 495ac5775d3..be6abe8df41 100644
--- a/src/devices/imagedev/printer.cpp
+++ b/src/devices/imagedev/printer.cpp
@@ -92,7 +92,7 @@ image_init_result printer_image_device::call_load()
{
/* send notify that the printer is now online */
if (!m_online_cb.isnull())
- m_online_cb(TRUE);
+ m_online_cb(true);
/* we don't need to do anything special */
return image_init_result::PASS;
@@ -106,5 +106,5 @@ void printer_image_device::call_unload()
{
/* send notify that the printer is now offline */
if (!m_online_cb.isnull())
- m_online_cb(FALSE);
+ m_online_cb(false);
}
diff --git a/src/devices/machine/53c810.cpp b/src/devices/machine/53c810.cpp
index 1ea3bd8e1cc..91775ef7d13 100644
--- a/src/devices/machine/53c810.cpp
+++ b/src/devices/machine/53c810.cpp
@@ -718,7 +718,7 @@ unsigned lsi53c810_device::lsi53c810_dasm(char *buf, uint32_t pc)
}
buf += sprintf(buf, "%s ", op_mnemonic);
- need_cojunction = FALSE;
+ need_cojunction = false;
for (i = 0; i < ARRAY_LENGTH(flags); i++)
{
@@ -727,7 +727,7 @@ unsigned lsi53c810_device::lsi53c810_dasm(char *buf, uint32_t pc)
if (need_cojunction)
buf += sprintf(buf, " AND ");
else
- need_cojunction = TRUE;
+ need_cojunction = true;
buf += sprintf(buf, "%s", flags[i].text);
}
}
diff --git a/src/devices/machine/6532riot.cpp b/src/devices/machine/6532riot.cpp
index 7ed81903115..94b56366d6d 100644
--- a/src/devices/machine/6532riot.cpp
+++ b/src/devices/machine/6532riot.cpp
@@ -483,6 +483,6 @@ void riot6532_device::device_timer(emu_timer &timer, device_timer_id id, int par
timer_end();
break;
default:
- assert_always(FALSE, "Unknown id in riot6532_device::device_timer");
+ assert_always(false, "Unknown id in riot6532_device::device_timer");
}
}
diff --git a/src/devices/machine/6821pia.cpp b/src/devices/machine/6821pia.cpp
index 85a5b4d9c3e..d47e7ffe1cb 100644
--- a/src/devices/machine/6821pia.cpp
+++ b/src/devices/machine/6821pia.cpp
@@ -143,8 +143,8 @@ void pia6821_device::device_reset()
// ports B,CB1,CB2 are three-state and undefined (set to 0)
//
m_in_a = 0xff;
- m_in_ca1 = TRUE;
- m_in_ca2 = TRUE;
+ m_in_ca1 = true;
+ m_in_ca2 = true;
m_out_a = 0;
m_out_ca2 = 0;
m_port_a_z_mask = 0;
@@ -183,8 +183,8 @@ void pia6821_device::device_reset()
// clear the IRQs
- m_irqa_handler(FALSE);
- m_irqb_handler(FALSE);
+ m_irqa_handler(false);
+ m_irqb_handler(false);
}
@@ -409,20 +409,20 @@ uint8_t pia6821_device::port_a_r()
uint8_t ret = get_in_a_value();
// IRQ flags implicitly cleared by a read
- m_irq_a1 = FALSE;
- m_irq_a2 = FALSE;
+ m_irq_a1 = false;
+ m_irq_a2 = false;
update_interrupts();
// CA2 is configured as output and in read strobe mode
if(C2_OUTPUT(m_ctl_a) && C2_STROBE_MODE(m_ctl_a))
{
// this will cause a transition low
- set_out_ca2(FALSE);
+ set_out_ca2(false);
// if the CA2 strobe is cleared by the E, reset it right away
if(STROBE_E_RESET(m_ctl_a))
{
- set_out_ca2(TRUE);
+ set_out_ca2(true);
}
}
@@ -460,12 +460,12 @@ uint8_t pia6821_device::port_b_r()
// from what happens with port A.
if(m_irq_b1 && C2_STROBE_MODE(m_ctl_b) && STROBE_C1_RESET(m_ctl_b))
{
- set_out_cb2(TRUE);
+ set_out_cb2(true);
}
// IRQ flags implicitly cleared by a read
- m_irq_b1 = FALSE;
- m_irq_b2 = FALSE;
+ m_irq_b1 = false;
+ m_irq_b2 = false;
update_interrupts();
LOG(("PIA #%s: port B read = %02X\n", tag(), ret));
@@ -740,12 +740,12 @@ void pia6821_device::port_b_w(uint8_t data)
if(C2_STROBE_MODE(m_ctl_b))
{
// this will cause a transition low
- set_out_cb2(FALSE);
+ set_out_cb2(false);
// if the CB2 strobe is cleared by the E, reset it right away
if(STROBE_E_RESET(m_ctl_b))
{
- set_out_cb2(TRUE);
+ set_out_cb2(true);
}
}
}
@@ -807,7 +807,7 @@ void pia6821_device::control_a_w(uint8_t data)
else
{
// strobe mode - output is always high unless strobed
- temp = TRUE;
+ temp = true;
}
set_out_ca2(temp);
@@ -842,7 +842,7 @@ void pia6821_device::control_b_w(uint8_t data)
else
{
// strobe mode - output is always high unless strobed
- temp = TRUE;
+ temp = true;
}
set_out_cb2(temp);
@@ -946,7 +946,7 @@ WRITE_LINE_MEMBER( pia6821_device::ca1_w )
LOG(("PIA #%s: CA1 triggering\n", tag()));
// mark the IRQ
- m_irq_a1 = TRUE;
+ m_irq_a1 = true;
// update externals
update_interrupts();
@@ -954,7 +954,7 @@ WRITE_LINE_MEMBER( pia6821_device::ca1_w )
// CA2 is configured as output and in read strobe mode and cleared by a CA1 transition
if(C2_OUTPUT(m_ctl_a) && C2_STROBE_MODE(m_ctl_a) && STROBE_C1_RESET(m_ctl_a))
{
- set_out_ca2(TRUE);
+ set_out_ca2(true);
}
}
@@ -978,7 +978,7 @@ WRITE_LINE_MEMBER( pia6821_device::ca2_w )
LOG(("PIA #%s: CA2 triggering\n", tag()));
// mark the IRQ
- m_irq_a2 = TRUE;
+ m_irq_a2 = true;
// update externals
update_interrupts();
diff --git a/src/devices/machine/6850acia.cpp b/src/devices/machine/6850acia.cpp
index 99882640fc4..775c3447f5e 100644
--- a/src/devices/machine/6850acia.cpp
+++ b/src/devices/machine/6850acia.cpp
@@ -362,7 +362,7 @@ WRITE_LINE_MEMBER( acia6850_device::write_rxc )
{
if (m_rx_counter != 1)
{
- if (LOG) logerror("MC6850 '%s': RX FALSE START BIT\n", tag());
+ if (LOG) logerror("MC6850 '%s': RX false START BIT\n", tag());
}
m_rx_counter = 0;
diff --git a/src/devices/machine/appldriv.cpp b/src/devices/machine/appldriv.cpp
index 43fc944eb6c..47b4408657e 100644
--- a/src/devices/machine/appldriv.cpp
+++ b/src/devices/machine/appldriv.cpp
@@ -101,7 +101,7 @@ static void apple525_seek_disk(apple525_floppy_image_device *img, signed int ste
disk = get_device(img);
- apple525_save_current_track(img, FALSE);
+ apple525_save_current_track(img, false);
track = img->floppy_drive_get_current_track();
pseudo_track = (track * 2) + disk->tween_tracks;
@@ -237,7 +237,7 @@ static uint8_t apple525_process_byte(device_t *img, int write_value)
/* when writing; save the current track after every full sector write */
if ((write_value >= 0) && ((disk->position % APPLE2_NIBBLE_SIZE) == 0))
- apple525_save_current_track(img, FALSE);
+ apple525_save_current_track(img, false);
return read_value;
}
@@ -330,7 +330,7 @@ image_init_result apple525_floppy_image_device::call_load()
void apple525_floppy_image_device::call_unload()
{
- apple525_save_current_track(this, TRUE);
+ apple525_save_current_track(this, true);
legacy_floppy_image_device::call_unload();
}
diff --git a/src/devices/machine/bcreader.h b/src/devices/machine/bcreader.h
index bc94f6dd92e..661c3008198 100644
--- a/src/devices/machine/bcreader.h
+++ b/src/devices/machine/bcreader.h
@@ -33,7 +33,7 @@ public:
int read_pixel();
// TODO: add checksum validation!
- bool is_valid(int len) { return (len != 12 && len != 13 && len != 8) ? FALSE : TRUE; }
+ bool is_valid(int len) { return (len != 12 && len != 13 && len != 8) ? false : true; }
void decode(int len);
protected:
diff --git a/src/devices/machine/ds2404.cpp b/src/devices/machine/ds2404.cpp
index 65db6cd82fa..08d4667da97 100644
--- a/src/devices/machine/ds2404.cpp
+++ b/src/devices/machine/ds2404.cpp
@@ -366,7 +366,7 @@ void ds2404_device::device_timer(emu_timer &timer, device_timer_id id, int param
}
default:
- assert_always(FALSE, "Unknown id in ds2404_device::device_timer");
+ assert_always(false, "Unknown id in ds2404_device::device_timer");
break;
}
}
diff --git a/src/devices/machine/e05a30.cpp b/src/devices/machine/e05a30.cpp
index 386ebd1f641..6f34b42d24c 100644
--- a/src/devices/machine/e05a30.cpp
+++ b/src/devices/machine/e05a30.cpp
@@ -73,13 +73,13 @@ void e05a30_device::device_reset()
m_cr_stepper = 0x00;
/* centronics init */
- m_centronics_nack = FALSE;
- m_centronics_busy = FALSE;
+ m_centronics_nack = false;
+ m_centronics_busy = false;
m_write_centronics_ack (!m_centronics_nack);
m_write_centronics_busy ( m_centronics_busy);
- m_write_centronics_perror(FALSE);
- m_write_centronics_fault (TRUE);
- m_write_centronics_select(TRUE);
+ m_write_centronics_perror(false);
+ m_write_centronics_fault (true);
+ m_write_centronics_select(true);
m_write_ready(1);
}
@@ -150,11 +150,11 @@ void e05a30_device::update_cr_stepper(uint8_t data)
WRITE_LINE_MEMBER( e05a30_device::centronics_input_strobe )
{
- if (m_centronics_strobe == TRUE && state == FALSE && !m_centronics_busy) {
+ if (m_centronics_strobe == true && state == false && !m_centronics_busy) {
m_centronics_data_latch = m_centronics_data;
- m_centronics_data_latched = TRUE;
- m_centronics_busy = TRUE;
+ m_centronics_data_latched = true;
+ m_centronics_busy = true;
m_write_centronics_busy(m_centronics_busy);
}
@@ -180,7 +180,7 @@ WRITE8_MEMBER( e05a30_device::write )
* assume the busy signal cannot be reset while the data hasn't been
* read. */
if (m_centronics_data_latched)
- m_centronics_busy = TRUE;
+ m_centronics_busy = true;
m_write_centronics_ack (!m_centronics_nack);
m_write_centronics_busy( m_centronics_busy);
break;
@@ -206,7 +206,7 @@ READ8_MEMBER( e05a30_device::read )
break;
case 0x03:
result = m_centronics_data_latch;
- m_centronics_data_latched = FALSE;
+ m_centronics_data_latched = false;
break;
case 0x04:
result |= m_centronics_busy << 0;
diff --git a/src/devices/machine/f3853.cpp b/src/devices/machine/f3853.cpp
index 747bd3cdc28..dd9e80434b1 100644
--- a/src/devices/machine/f3853.cpp
+++ b/src/devices/machine/f3853.cpp
@@ -63,10 +63,10 @@ void f3853_device::device_start()
uint8_t reg = 0xfe;
for(int32_t i=254 /* Known to get 0xfe after 255 cycles */; i >= 0; i--)
{
- int32_t o7 = (reg & 0x80) ? TRUE : FALSE;
- int32_t o5 = (reg & 0x20) ? TRUE : FALSE;
- int32_t o4 = (reg & 0x10) ? TRUE : FALSE;
- int32_t o3 = (reg & 0x08) ? TRUE : FALSE;
+ int32_t o7 = (reg & 0x80) ? true : false;
+ int32_t o5 = (reg & 0x20) ? true : false;
+ int32_t o4 = (reg & 0x10) ? true : false;
+ int32_t o3 = (reg & 0x08) ? true : false;
m_value_to_cycle[reg] = i;
reg <<= 1;
if (!((o7 != o5) != (o4 != o3)))
@@ -100,8 +100,8 @@ void f3853_device::device_reset()
m_external_enable = 0;
m_timer_enable = 0;
m_request_flipflop = 0;
- m_priority_line = FALSE;
- m_external_interrupt_line = TRUE;
+ m_priority_line = false;
+ m_external_interrupt_line = true;
m_timer->enable(false);
}
@@ -113,11 +113,11 @@ void f3853_device::set_interrupt_request_line()
return;
if (m_external_enable && !m_priority_line)
- m_interrupt_req_cb(INTERRUPT_VECTOR(TRUE), TRUE);
+ m_interrupt_req_cb(INTERRUPT_VECTOR(true), true);
else if (m_timer_enable && !m_priority_line && m_request_flipflop)
- m_interrupt_req_cb(INTERRUPT_VECTOR(FALSE), TRUE);
+ m_interrupt_req_cb(INTERRUPT_VECTOR(false), true);
else
- m_interrupt_req_cb(0, FALSE);
+ m_interrupt_req_cb(0, false);
}
@@ -132,7 +132,7 @@ TIMER_CALLBACK_MEMBER(f3853_device::timer_callback)
{
if(m_timer_enable)
{
- m_request_flipflop = TRUE;
+ m_request_flipflop = true;
set_interrupt_request_line();
}
timer_start(0xfe);
@@ -142,7 +142,7 @@ void f3853_device::set_external_interrupt_in_line(int level)
{
if(m_external_interrupt_line && !level && m_external_enable)
{
- m_request_flipflop = TRUE;
+ m_request_flipflop = true;
}
m_external_interrupt_line = level;
set_interrupt_request_line();
@@ -197,7 +197,7 @@ WRITE8_MEMBER(f3853_device::write)
break;
case 3: //timer
- m_request_flipflop = FALSE;
+ m_request_flipflop = false;
set_interrupt_request_line();
timer_start(data);
break;
diff --git a/src/devices/machine/gt64xxx.cpp b/src/devices/machine/gt64xxx.cpp
index 9d38fef3c7f..763f27be1e2 100644
--- a/src/devices/machine/gt64xxx.cpp
+++ b/src/devices/machine/gt64xxx.cpp
@@ -71,7 +71,7 @@ void gt64xxx_device::device_start()
uint32_t romSize = m_romRegion->bytes();
m_cpu_space->install_rom (0x1fc00000, 0x1fc00000 + romSize - 1, m_romRegion->base());
// ROM MIPS DRC
- m_cpu->add_fastram(0x1fc00000, 0x1fc00000 + romSize - 1, TRUE, m_romRegion->base());
+ m_cpu->add_fastram(0x1fc00000, 0x1fc00000 + romSize - 1, true, m_romRegion->base());
if (LOG_GALILEO)
logerror("%s: gt64xxx_device::device_start ROM Mapped size: 0x%08X start: 0x1fc00000 end: %08X\n", tag(), romSize, 0x1fc00000 + romSize - 1);
@@ -175,8 +175,8 @@ void gt64xxx_device::map_cpu_space()
winEnd = (m_reg[GREG_RAS_1_0_LO + 0x10 / 4 * (ramIndex / 2)] << 21) | (m_reg[GREG_RAS0_HI + 0x8 / 4 * ramIndex] << 20) | 0xfffff;
m_ram[ramIndex].resize((winEnd + 1 - winStart) / 4);
m_cpu_space->install_ram(winStart, winEnd, m_ram[ramIndex].data());
- //m_cpu->add_fastram(winStart, m_ram[ramIndex].size() * sizeof(m_ram[ramIndex][0]), FALSE, &m_ram[ramIndex][0]);
- //m_cpu->add_fastram(winStart, m_ram[ramIndex].size() * sizeof(uint32_t), FALSE, m_ram[ramIndex].data());
+ //m_cpu->add_fastram(winStart, m_ram[ramIndex].size() * sizeof(m_ram[ramIndex][0]), false, &m_ram[ramIndex][0]);
+ //m_cpu->add_fastram(winStart, m_ram[ramIndex].size() * sizeof(uint32_t), false, m_ram[ramIndex].data());
if (LOG_GALILEO)
logerror("%s: map_cpu_space ras[%i] start: %08X end: %08X\n", tag(), ramIndex, winStart, winEnd);
}
diff --git a/src/devices/machine/ldpr8210.cpp b/src/devices/machine/ldpr8210.cpp
index e90b2df40e1..834b38f056f 100644
--- a/src/devices/machine/ldpr8210.cpp
+++ b/src/devices/machine/ldpr8210.cpp
@@ -328,7 +328,7 @@ void pioneer_pr8210_device::device_timer(emu_timer &timer, device_timer_id id, i
// logging
if (LOG_VBLANK_VBI)
{
- uint32_t line1718 = get_field_code(LASERDISC_CODE_LINE1718, FALSE);
+ uint32_t line1718 = get_field_code(LASERDISC_CODE_LINE1718, false);
if ((line1718 & VBI_MASK_CAV_PICTURE) == VBI_CODE_CAV_PICTURE)
printf("%3d:VBI(%05d)\n", screen().vpos(), VBI_CAV_PICTURE(line1718));
else
@@ -340,8 +340,8 @@ void pioneer_pr8210_device::device_timer(emu_timer &timer, device_timer_id id, i
m_pia.vbi2 = 0xff;
if (focus_on() && laser_on())
{
- uint32_t line16 = get_field_code(LASERDISC_CODE_LINE16, FALSE);
- uint32_t line1718 = get_field_code(LASERDISC_CODE_LINE1718, FALSE);
+ uint32_t line16 = get_field_code(LASERDISC_CODE_LINE16, false);
+ uint32_t line1718 = get_field_code(LASERDISC_CODE_LINE1718, false);
if (line1718 == VBI_CODE_LEADIN)
m_pia.vbi1 &= ~0x01;
if (line1718 == VBI_CODE_LEADOUT)
diff --git a/src/devices/machine/ldvp931.cpp b/src/devices/machine/ldvp931.cpp
index d2d445f3336..258b049da00 100644
--- a/src/devices/machine/ldvp931.cpp
+++ b/src/devices/machine/ldvp931.cpp
@@ -494,7 +494,7 @@ READ8_MEMBER( phillips_22vp931_device::i8049_from_controller_r )
WRITE8_MEMBER( phillips_22vp931_device::i8049_to_controller_w )
{
// set the pending flag and stash the data
- m_tocontroller_pending = TRUE;
+ m_tocontroller_pending = true;
m_tocontroller = data;
// signal to the callback if provided
diff --git a/src/devices/machine/mos6551.cpp b/src/devices/machine/mos6551.cpp
index 3bfc22219e5..43201fb1d2b 100644
--- a/src/devices/machine/mos6551.cpp
+++ b/src/devices/machine/mos6551.cpp
@@ -573,7 +573,7 @@ WRITE_LINE_MEMBER(mos6551_device::receiver_clock)
{
m_rx_counter = 0;
- if (LOG) logerror("MOS6551 '%s': RX FALSE START BIT\n", tag());
+ if (LOG) logerror("MOS6551 '%s': RX false START BIT\n", tag());
}
}
break;
diff --git a/src/devices/machine/pcf8593.cpp b/src/devices/machine/pcf8593.cpp
index 4620bbdf6cf..63016320b81 100644
--- a/src/devices/machine/pcf8593.cpp
+++ b/src/devices/machine/pcf8593.cpp
@@ -75,7 +75,7 @@ void pcf8593_device::device_reset()
_logerror( 0, ("pcf8593_reset\n"));
m_pin_scl = 1;
m_pin_sda = 1;
- m_active = FALSE;
+ m_active = false;
m_inp = 0;
m_mode = RTC_MODE_RECV;
m_bits = 0;
@@ -244,7 +244,7 @@ WRITE_LINE_MEMBER(pcf8593_device::sda_w)
if ((!state) && (m_pin_sda))
{
_logerror( 1, ("pcf8593 start condition\n"));
- m_active = TRUE;
+ m_active = true;
m_bits = 0;
m_data_recv_index = 0;
clear_buffer_rx();
@@ -254,7 +254,7 @@ WRITE_LINE_MEMBER(pcf8593_device::sda_w)
if ((state) && (!m_pin_sda))
{
_logerror( 1, ("pcf8593 stop condition\n"));
- m_active = FALSE;
+ m_active = false;
}
}
// save sda
diff --git a/src/devices/machine/ram.cpp b/src/devices/machine/ram.cpp
index 7a0bc2ac08a..f651e10c8bc 100644
--- a/src/devices/machine/ram.cpp
+++ b/src/devices/machine/ram.cpp
@@ -72,7 +72,7 @@ void ram_device::device_start()
void ram_device::device_validity_check(validity_checker &valid) const
{
const char *ramsize_string = nullptr;
- int is_valid = FALSE;
+ int is_valid = false;
uint32_t specified_ram;
const char *gamename_option;
@@ -98,7 +98,7 @@ void ram_device::device_validity_check(validity_checker &valid) const
{
/* compare command line option to default value */
if (default_size() == specified_ram)
- is_valid = TRUE;
+ is_valid = true;
/* verify extra ram options */
if (m_extra_options != nullptr)
@@ -121,7 +121,7 @@ void ram_device::device_validity_check(validity_checker &valid) const
osd_printf_error("Invalid RAM option: %s\n", p);
if (option_ram_size == specified_ram)
- is_valid = TRUE;
+ is_valid = true;
p += strlen(p);
if (p == e)
@@ -134,17 +134,17 @@ void ram_device::device_validity_check(validity_checker &valid) const
} else {
/* if not for this driver then return ok */
- is_valid = TRUE;
+ is_valid = true;
}
}
else
{
/* not specifying the ramsize on the command line is valid as well */
- is_valid = TRUE;
+ is_valid = true;
}
}
else
- is_valid = TRUE;
+ is_valid = true;
if (!is_valid)
{
diff --git a/src/devices/machine/rtc65271.cpp b/src/devices/machine/rtc65271.cpp
index 23367bc7386..edcb44880ba 100644
--- a/src/devices/machine/rtc65271.cpp
+++ b/src/devices/machine/rtc65271.cpp
@@ -208,7 +208,7 @@ void rtc65271_device::nvram_read(emu_file &file)
return;
m_regs[reg_D] |= reg_D_VRT; /* the data was backed up successfully */
- /*m_dirty = FALSE;*/
+ /*m_dirty = false;*/
{
system_time systime;
diff --git a/src/devices/machine/s2636.h b/src/devices/machine/s2636.h
index ce46ee4581d..56c0d8f4b4b 100644
--- a/src/devices/machine/s2636.h
+++ b/src/devices/machine/s2636.h
@@ -10,7 +10,7 @@
#define __S2636_H__
-#define S2636_IS_PIXEL_DRAWN(p) (((p) & 0x08) ? TRUE : FALSE)
+#define S2636_IS_PIXEL_DRAWN(p) (((p) & 0x08) ? true : false)
#define S2636_PIXEL_COLOR(p) ((p) & 0x07)
diff --git a/src/devices/machine/s3c24xx.hxx b/src/devices/machine/s3c24xx.hxx
index 5019f40891f..34c7c8421d4 100644
--- a/src/devices/machine/s3c24xx.hxx
+++ b/src/devices/machine/s3c24xx.hxx
@@ -830,7 +830,7 @@ int S3C24_CLASS_NAME::s3c24xx_lcd_configure_tft()
m_lcd.vpos_min = (vspw + 1) + (vbpd + 1);
m_lcd.vpos_max = m_lcd.vpos_min + (lineval + 1) - 1;
screen->configure( width, height, visarea, HZ_TO_ATTOSECONDS( m_lcd.framerate));
- return TRUE;
+ return true;
}
int S3C24_CLASS_NAME::s3c24xx_lcd_configure_stn()
@@ -853,7 +853,7 @@ int S3C24_CLASS_NAME::s3c24xx_lcd_configure_stn()
verboselog( *this, 3, "LCD - pnrmode %d bppmode %d clkval %d lineval %d wdly %d hozval %d lineblank %d wlh %d hclk %d\n", pnrmode, bppmode, clkval, lineval, wdly, hozval, lineblank, wlh, hclk);
if (clkval == 0)
{
- return FALSE;
+ return false;
}
vclk = (double)(hclk / ((clkval + 0) * 2));
verboselog( *this, 3, "LCD - vclk %f\n", vclk);
@@ -876,7 +876,7 @@ int S3C24_CLASS_NAME::s3c24xx_lcd_configure_stn()
m_lcd.vpos_min = 0;
m_lcd.vpos_max = height - 1;
screen->configure( width, height, visarea, HZ_TO_ATTOSECONDS( m_lcd.framerate));
- return TRUE;
+ return true;
}
int S3C24_CLASS_NAME::s3c24xx_lcd_configure()
diff --git a/src/devices/machine/smartmed.cpp b/src/devices/machine/smartmed.cpp
index 608122981af..202a0bc5e68 100644
--- a/src/devices/machine/smartmed.cpp
+++ b/src/devices/machine/smartmed.cpp
@@ -191,7 +191,7 @@ image_init_result smartmedia_image_device::smartmedia_format_1()
int smartmedia_image_device::detect_geometry( uint8_t id1, uint8_t id2)
{
- int result = FALSE;
+ int result = false;
switch (id1)
{
@@ -199,15 +199,15 @@ int smartmedia_image_device::detect_geometry( uint8_t id1, uint8_t id2)
{
switch (id2)
{
- case 0xA4 : m_page_data_size = 0x0100; m_num_pages = 0x00800; m_page_total_size = 0x0108; m_log2_pages_per_block = 0; result = TRUE; break;
- case 0x6E : m_page_data_size = 0x0100; m_num_pages = 0x01000; m_page_total_size = 0x0108; m_log2_pages_per_block = 0; result = TRUE; break;
- case 0xEA : m_page_data_size = 0x0100; m_num_pages = 0x02000; m_page_total_size = 0x0108; m_log2_pages_per_block = 4; result = TRUE; break;
- case 0xE3 : m_page_data_size = 0x0200; m_num_pages = 0x02000; m_page_total_size = 0x0210; m_log2_pages_per_block = 4; result = TRUE; break;
- case 0xE6 : m_page_data_size = 0x0200; m_num_pages = 0x04000; m_page_total_size = 0x0210; m_log2_pages_per_block = 4; result = TRUE; break;
- case 0x73 : m_page_data_size = 0x0200; m_num_pages = 0x08000; m_page_total_size = 0x0210; m_log2_pages_per_block = 5; result = TRUE; break;
- case 0x75 : m_page_data_size = 0x0200; m_num_pages = 0x10000; m_page_total_size = 0x0210; m_log2_pages_per_block = 5; result = TRUE; break;
- case 0x76 : m_page_data_size = 0x0200; m_num_pages = 0x20000; m_page_total_size = 0x0210; m_log2_pages_per_block = 5; result = TRUE; break;
- case 0x79 : m_page_data_size = 0x0200; m_num_pages = 0x40000; m_page_total_size = 0x0210; m_log2_pages_per_block = 5; result = TRUE; break;
+ case 0xA4 : m_page_data_size = 0x0100; m_num_pages = 0x00800; m_page_total_size = 0x0108; m_log2_pages_per_block = 0; result = true; break;
+ case 0x6E : m_page_data_size = 0x0100; m_num_pages = 0x01000; m_page_total_size = 0x0108; m_log2_pages_per_block = 0; result = true; break;
+ case 0xEA : m_page_data_size = 0x0100; m_num_pages = 0x02000; m_page_total_size = 0x0108; m_log2_pages_per_block = 4; result = true; break;
+ case 0xE3 : m_page_data_size = 0x0200; m_num_pages = 0x02000; m_page_total_size = 0x0210; m_log2_pages_per_block = 4; result = true; break;
+ case 0xE6 : m_page_data_size = 0x0200; m_num_pages = 0x04000; m_page_total_size = 0x0210; m_log2_pages_per_block = 4; result = true; break;
+ case 0x73 : m_page_data_size = 0x0200; m_num_pages = 0x08000; m_page_total_size = 0x0210; m_log2_pages_per_block = 5; result = true; break;
+ case 0x75 : m_page_data_size = 0x0200; m_num_pages = 0x10000; m_page_total_size = 0x0210; m_log2_pages_per_block = 5; result = true; break;
+ case 0x76 : m_page_data_size = 0x0200; m_num_pages = 0x20000; m_page_total_size = 0x0210; m_log2_pages_per_block = 5; result = true; break;
+ case 0x79 : m_page_data_size = 0x0200; m_num_pages = 0x40000; m_page_total_size = 0x0210; m_log2_pages_per_block = 5; result = true; break;
}
}
break;
@@ -215,7 +215,7 @@ int smartmedia_image_device::detect_geometry( uint8_t id1, uint8_t id2)
{
switch (id2)
{
- case 0x75 : m_page_data_size = 0x0200; m_num_pages = 0x10000; m_page_total_size = 0x0210; m_log2_pages_per_block = 5; result = TRUE; break;
+ case 0x75 : m_page_data_size = 0x0200; m_num_pages = 0x10000; m_page_total_size = 0x0210; m_log2_pages_per_block = 5; result = true; break;
}
}
break;
diff --git a/src/devices/machine/upd7002.cpp b/src/devices/machine/upd7002.cpp
index ff5bae792ae..ba7d2e36ade 100644
--- a/src/devices/machine/upd7002.cpp
+++ b/src/devices/machine/upd7002.cpp
@@ -89,7 +89,7 @@ void upd7002_device::device_timer(emu_timer &timer, device_timer_id id, int para
break;
}
default:
- assert_always(FALSE, "Unknown id in upd7002_device::device_timer");
+ assert_always(false, "Unknown id in upd7002_device::device_timer");
}
}
diff --git a/src/devices/machine/vrc4373.cpp b/src/devices/machine/vrc4373.cpp
index 81391b7625c..1c1e3a0721e 100644
--- a/src/devices/machine/vrc4373.cpp
+++ b/src/devices/machine/vrc4373.cpp
@@ -73,7 +73,7 @@ void vrc4373_device::device_start()
m_cpu_space->install_device(0x0f000100, 0x0f0001ff, *static_cast<vrc4373_device *>(this), &vrc4373_device::config_map);
// MIPS drc
- m_cpu->add_fastram(0x1fc00000, 0x1fcfffff, TRUE, m_romRegion->base());
+ m_cpu->add_fastram(0x1fc00000, 0x1fcfffff, true, m_romRegion->base());
// DMA timer
m_dma_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(vrc4373_device::dma_transfer), this));
@@ -114,7 +114,7 @@ void vrc4373_device::map_cpu_space()
m_ram.resize(winSize / 4);
m_cpu_space->install_ram(winStart, winEnd, m_ram.data());
- m_cpu->add_fastram(winStart, winEnd, FALSE, m_ram.data());
+ m_cpu->add_fastram(winStart, winEnd, false, m_ram.data());
if (LOG_NILE)
logerror("map_cpu_space ram_size=%08X ram_base=%08X\n", winSize, winStart);
}
@@ -133,7 +133,7 @@ void vrc4373_device::map_cpu_space()
m_simm[simIndex].resize(winSize / 4);
m_cpu_space->install_ram(winStart, winEnd, m_simm[simIndex].data());
- m_cpu->add_fastram(winStart, winEnd, FALSE, m_simm[simIndex].data());
+ m_cpu->add_fastram(winStart, winEnd, false, m_simm[simIndex].data());
if (LOG_NILE)
logerror("map_cpu_space simm_size[%i]=%08X simm_base=%08X\n", simIndex, winSize, winStart);
}
diff --git a/src/devices/sound/cdda.cpp b/src/devices/sound/cdda.cpp
index f0fc9e4d000..dbb89aa51ac 100644
--- a/src/devices/sound/cdda.cpp
+++ b/src/devices/sound/cdda.cpp
@@ -72,9 +72,9 @@ void cdda_device::set_cdrom(void *file)
void cdda_device::start_audio(uint32_t startlba, uint32_t numblocks)
{
m_stream->update();
- m_audio_playing = TRUE;
- m_audio_pause = FALSE;
- m_audio_ended_normally = FALSE;
+ m_audio_playing = true;
+ m_audio_pause = false;
+ m_audio_ended_normally = false;
m_audio_lba = startlba;
m_audio_length = numblocks;
m_audio_samples = 0;
@@ -89,8 +89,8 @@ void cdda_device::start_audio(uint32_t startlba, uint32_t numblocks)
void cdda_device::stop_audio()
{
m_stream->update();
- m_audio_playing = FALSE;
- m_audio_ended_normally = TRUE;
+ m_audio_playing = false;
+ m_audio_ended_normally = true;
}
@@ -172,8 +172,8 @@ void cdda_device::get_audio_data(stream_sample_t *bufL, stream_sample_t *bufR, u
{
if( m_disc && m_audio_playing && !m_audio_pause && !m_audio_length )
{
- m_audio_playing = FALSE;
- m_audio_ended_normally = TRUE;
+ m_audio_playing = false;
+ m_audio_ended_normally = true;
}
memset(bufL, 0, sizeof(stream_sample_t)*samples_wanted);
diff --git a/src/devices/sound/discrete.h b/src/devices/sound/discrete.h
index 476e89b776e..8c33fcd82c9 100644
--- a/src/devices/sound/discrete.h
+++ b/src/devices/sound/discrete.h
@@ -488,7 +488,7 @@
*
* DISCRETE_COUNTER(name of node,
* enable node or static value,
- * reset node or static value, (reset when TRUE)
+ * reset node or static value, (reset when true)
* clock node or static value,
* min count static value,
* max count static value,
diff --git a/src/devices/sound/hc55516.cpp b/src/devices/sound/hc55516.cpp
index 2bfbd6342ec..890a9c8b0fc 100644
--- a/src/devices/sound/hc55516.cpp
+++ b/src/devices/sound/hc55516.cpp
@@ -82,7 +82,7 @@ void hc55516_device::device_config_complete()
void hc55516_device::device_start()
{
- start_common(0x07, TRUE);
+ start_common(0x07, true);
}
//-------------------------------------------------
@@ -107,7 +107,7 @@ mc3417_device::mc3417_device(const machine_config &mconfig, const char *tag, dev
void mc3417_device::device_start()
{
- start_common(0x07, FALSE);
+ start_common(0x07, false);
}
@@ -124,7 +124,7 @@ mc3418_device::mc3418_device(const machine_config &mconfig, const char *tag, dev
void mc3418_device::device_start()
{
- start_common(0x0f, FALSE);
+ start_common(0x0f, false);
}
@@ -220,7 +220,7 @@ void hc55516_device::process_digit()
void hc55516_device::clock_w(int state)
{
- uint8_t clock_state = state ? TRUE : FALSE;
+ uint8_t clock_state = state ? true : false;
/* only makes sense for setups with a software driven clock */
assert(!is_external_oscillator());
diff --git a/src/devices/sound/pokey.cpp b/src/devices/sound/pokey.cpp
index 97ac8fb6258..f7907d04531 100644
--- a/src/devices/sound/pokey.cpp
+++ b/src/devices/sound/pokey.cpp
@@ -439,7 +439,7 @@ void pokey_device::device_timer(emu_timer &timer, device_timer_id id, int param,
m_IRQST |= (param & 0xff);
break;
default:
- assert_always(FALSE, "Unknown id in pokey_device::device_timer");
+ assert_always(false, "Unknown id in pokey_device::device_timer");
}
}
diff --git a/src/devices/sound/sid.cpp b/src/devices/sound/sid.cpp
index 0f36c54e179..d39bc0ed037 100644
--- a/src/devices/sound/sid.cpp
+++ b/src/devices/sound/sid.cpp
@@ -147,7 +147,7 @@ int sidEmuReset(SID6581_t *This)
sidEmuSet2( &This->optr2 );
sidEmuSet2( &This->optr3 );
- return TRUE;
+ return true;
}
@@ -233,14 +233,14 @@ void sid6581_init (SID6581_t *This)
This->PCMsid = (uint32_t)(This->PCMfreq * (16777216.0 / This->clock));
This->PCMsidNoise = (uint32_t)((This->clock*256.0)/This->PCMfreq);
- This->filter.Enabled = TRUE;
+ This->filter.Enabled = true;
sidInitMixerEngine(This->device->machine());
filterTableInit(This->device->machine());
sidInitWaveformTables(This->type);
- enveEmuInit(This->PCMfreq, TRUE);
+ enveEmuInit(This->PCMfreq, true);
MixerInit(0);
diff --git a/src/devices/sound/sidvoice.cpp b/src/devices/sound/sidvoice.cpp
index 636dca3ccba..de521a63e2f 100644
--- a/src/devices/sound/sidvoice.cpp
+++ b/src/devices/sound/sidvoice.cpp
@@ -212,7 +212,7 @@ static void sidMode80hp(sidOperator* pVoice) {
static void sidModeLock(sidOperator* pVoice)
{
- pVoice->noiseIsLocked = TRUE;
+ pVoice->noiseIsLocked = true;
pVoice->output = (pVoice->filtIO-0x80);
waveAdvance(pVoice);
}
@@ -570,7 +570,7 @@ void sidClearOperator( sidOperator* pVoice )
pVoice->SIDAD = 0;
pVoice->SIDSR = 0;
- pVoice->sync = FALSE;
+ pVoice->sync = false;
pVoice->pulseIndex = (pVoice->newPulseIndex = (pVoice->SIDpulseWidth = 0));
pVoice->curSIDfreq = (pVoice->curNoiseFreq = 0);
@@ -578,7 +578,7 @@ void sidClearOperator( sidOperator* pVoice )
pVoice->output = (pVoice->noiseOutput = 0);
pVoice->filtIO = 0;
- pVoice->filtEnabled = FALSE;
+ pVoice->filtEnabled = false;
pVoice->filtLow = (pVoice->filtRef = 0);
pVoice->cycleLenCount = 0;
@@ -611,13 +611,13 @@ void sidClearOperator( sidOperator* pVoice )
pVoice->noiseReg = noiseSeed;
#endif
pVoice->noiseStepAdd = (pVoice->noiseStep = 0);
- pVoice->noiseIsLocked = FALSE;
+ pVoice->noiseIsLocked = false;
}
void sidEmuSet2(sidOperator* pVoice)
{
pVoice->outProc = &sidWaveCalcNormal;
- pVoice->sync = FALSE;
+ pVoice->sync = false;
if ( (pVoice->SIDfreq < 16) || ((pVoice->SIDctrl & 8) != 0) )
// if ( /*(pVoice->SIDfreq < 16) || */((pVoice->SIDctrl & 8) != 0) )
@@ -642,7 +642,7 @@ void sidEmuSet2(sidOperator* pVoice)
{
if (pVoice->noiseIsLocked)
{
- pVoice->noiseIsLocked = FALSE;
+ pVoice->noiseIsLocked = false;
#if defined(DIRECT_FIXPOINT)
pVoice->noiseReg.l = noiseSeed;
#else
@@ -699,7 +699,7 @@ void sidEmuSet2(sidOperator* pVoice)
}
else
{
- pVoice->sync = TRUE;
+ pVoice->sync = true;
}
}
diff --git a/src/devices/sound/t6w28.cpp b/src/devices/sound/t6w28.cpp
index 7fe2260516b..4dc7174b99a 100644
--- a/src/devices/sound/t6w28.cpp
+++ b/src/devices/sound/t6w28.cpp
@@ -328,7 +328,7 @@ void t6w28_device::device_start()
/* values from sn76489a */
m_feedback_mask = 0x8000;
m_whitenoise_taps = 0x06;
- m_whitenoise_invert = FALSE;
+ m_whitenoise_invert = false;
save_item(NAME(m_register));
save_item(NAME(m_last_register));
diff --git a/src/devices/sound/tms5110.cpp b/src/devices/sound/tms5110.cpp
index 3112e80076b..84e36322477 100644
--- a/src/devices/sound/tms5110.cpp
+++ b/src/devices/sound/tms5110.cpp
@@ -335,7 +335,7 @@ void tms5110_device::perform_dummy_read()
{
int data = new_int_read();
if (DEBUG_5110) logerror("TMS5110 performing dummy read; value read = %1i\n", data & 1);
- m_schedule_dummy_read = FALSE;
+ m_schedule_dummy_read = false;
}
}
@@ -814,10 +814,10 @@ void tms5110_device::PDC_set(int data)
#ifdef DEBUG_COMMAND_DUMP
fprintf(stderr,"Loading address nybble %02x to VSMs\n", m_CTL_pins);
#endif
- m_next_is_address = FALSE;
+ m_next_is_address = false;
m_address = m_address | ((m_CTL_pins & 0x0F)<<m_addr_bit);
m_addr_bit = (m_addr_bit + 4) % 12;
- m_schedule_dummy_read = TRUE;
+ m_schedule_dummy_read = true;
new_int_write_addr(m_CTL_pins & 0x0F);
}
else
@@ -839,7 +839,7 @@ void tms5110_device::PDC_set(int data)
#ifdef DEBUG_COMMAND_DUMP
fprintf(stderr,"LOAD ADDRESS\n");
#endif
- m_next_is_address = TRUE;
+ m_next_is_address = true;
break;
case TMS5110_CMD_OUTPUT:
@@ -918,7 +918,7 @@ void tms5110_device::PDC_set(int data)
new_int_write(0,0,0,0);
new_int_write(1,0,0,0);
new_int_write(0,0,0,0);
- m_schedule_dummy_read = FALSE;
+ m_schedule_dummy_read = false;
break;
case TMS5110_CMD_TEST_TALK:
@@ -1187,16 +1187,16 @@ void tms5110_device::device_reset()
if (m_table.found())
{
/* legacy interface */
- m_schedule_dummy_read = TRUE;
+ m_schedule_dummy_read = true;
}
else
{
/* no dummy read! This makes bagman and ad2083 speech fail
* with the new cycle and transition exact interfaces
*/
- m_schedule_dummy_read = FALSE;
+ m_schedule_dummy_read = false;
}
- m_next_is_address = FALSE;
+ m_next_is_address = false;
m_address = 0;
m_addr_bit = 0;
}
@@ -1297,7 +1297,7 @@ READ8_MEMBER( tms5110_device::romclk_hack_r )
/* create and start timer if necessary */
if (!m_romclk_hack_timer_started)
{
- m_romclk_hack_timer_started = TRUE;
+ m_romclk_hack_timer_started = true;
m_romclk_hack_timer->adjust(attotime::from_hz(clock() / 40), 0, attotime::from_hz(clock() / 40));
}
return m_romclk_hack_state;
diff --git a/src/devices/sound/tms5220.cpp b/src/devices/sound/tms5220.cpp
index 4bab38b52bd..b1a9b8aa325 100644
--- a/src/devices/sound/tms5220.cpp
+++ b/src/devices/sound/tms5220.cpp
@@ -803,7 +803,7 @@ void tms5220_device::perform_dummy_read()
#else
new_int_read();
#endif
- m_schedule_dummy_read = FALSE;
+ m_schedule_dummy_read = false;
}
}
@@ -817,7 +817,7 @@ int tms5220_device::status_read()
{
if (m_RDB_flag)
{ /* if last command was read, return data register */
- m_RDB_flag = FALSE;
+ m_RDB_flag = false;
return(m_data_register);
}
else
@@ -1358,13 +1358,13 @@ void tms5220_device::process_command(unsigned char cmd)
{
if (m_schedule_dummy_read)
{
- m_schedule_dummy_read = FALSE;
+ m_schedule_dummy_read = false;
if (m_speechrom)
m_speechrom->read(1);
}
if (m_speechrom)
m_data_register = m_speechrom->read(8); /* read one byte from speech ROM... */
- m_RDB_flag = TRUE;
+ m_RDB_flag = true;
}
break;
@@ -1381,7 +1381,7 @@ void tms5220_device::process_command(unsigned char cmd)
#ifdef VERBOSE
logerror("read and branch command received\n");
#endif
- m_RDB_flag = FALSE;
+ m_RDB_flag = false;
if (m_speechrom)
m_speechrom->read_and_branch();
}
@@ -1394,14 +1394,14 @@ void tms5220_device::process_command(unsigned char cmd)
This code does not care about this. */
if (m_speechrom)
m_speechrom->load_address(cmd & 0x0f);
- m_schedule_dummy_read = TRUE;
+ m_schedule_dummy_read = true;
}
break;
case 0x50 : /* speak */
if (m_schedule_dummy_read)
{
- m_schedule_dummy_read = FALSE;
+ m_schedule_dummy_read = false;
if (m_speechrom)
m_speechrom->read(1);
}
@@ -1451,13 +1451,13 @@ void tms5220_device::process_command(unsigned char cmd)
m_new_frame_k_idx[i] = 0xF;
for (i = 7; i < m_coeff->num_k; i++)
m_new_frame_k_idx[i] = 0x7;
- m_RDB_flag = FALSE;
+ m_RDB_flag = false;
break;
case 0x70 : /* reset */
if (m_schedule_dummy_read)
{
- m_schedule_dummy_read = FALSE;
+ m_schedule_dummy_read = false;
if (m_speechrom)
m_speechrom->read(1);
}
@@ -1724,7 +1724,7 @@ void tms5220_device::device_reset()
update_ready_state();
m_buffer_empty = m_buffer_low = 1;
- m_RDB_flag = FALSE;
+ m_RDB_flag = false;
/* initialize the energy/pitch/k states */
#ifdef PERFECT_INTERPOLATION_HACK
@@ -1757,7 +1757,7 @@ void tms5220_device::device_reset()
// load_address, no dummy read will occur, hence the address will be
// falsely shifted.
m_speechrom->read(1);
- m_schedule_dummy_read = FALSE;
+ m_schedule_dummy_read = false;
}
// 5110 specific stuff
@@ -1765,7 +1765,7 @@ void tms5220_device::device_reset()
m_CTL_pins = 0;
m_state = 0;
m_address = 0;
- m_next_is_address = FALSE;
+ m_next_is_address = false;
m_addr_bit = 0;
m_CTL_buffer = 0;
diff --git a/src/devices/sound/upd7759.cpp b/src/devices/sound/upd7759.cpp
index e3f3ae10253..aedd8dd1331 100644
--- a/src/devices/sound/upd7759.cpp
+++ b/src/devices/sound/upd7759.cpp
@@ -719,7 +719,7 @@ void upd7759_device::device_timer(emu_timer &timer, device_timer_id id, int para
break;
default:
- assert_always(FALSE, "Unknown id in upd7759_device::device_timer");
+ assert_always(false, "Unknown id in upd7759_device::device_timer");
}
}
diff --git a/src/devices/sound/ymf271.cpp b/src/devices/sound/ymf271.cpp
index ed58c45d316..1de2cbb4363 100644
--- a/src/devices/sound/ymf271.cpp
+++ b/src/devices/sound/ymf271.cpp
@@ -1296,7 +1296,7 @@ void ymf271_device::device_timer(emu_timer &timer, device_timer_id id, int param
break;
default:
- assert_always(FALSE, "Unknown id in ymf271_device::device_timer");
+ assert_always(false, "Unknown id in ymf271_device::device_timer");
break;
}
}
diff --git a/src/devices/sound/ymz280b.cpp b/src/devices/sound/ymz280b.cpp
index dd3e45e4529..d366613b6a6 100644
--- a/src/devices/sound/ymz280b.cpp
+++ b/src/devices/sound/ymz280b.cpp
@@ -683,7 +683,7 @@ void ymz280b_device::device_timer(emu_timer &timer, device_timer_id id, int para
if (id < 8)
update_irq_state_timer_common( id );
else
- assert_always(FALSE, "Unknown id in ymz280b_device::device_timer");
+ assert_always(false, "Unknown id in ymz280b_device::device_timer");
}
diff --git a/src/devices/video/crtc_ega.cpp b/src/devices/video/crtc_ega.cpp
index 83d34a5cf3a..eab4c2c5bfe 100644
--- a/src/devices/video/crtc_ega.cpp
+++ b/src/devices/video/crtc_ega.cpp
@@ -58,8 +58,8 @@ READ8_MEMBER( crtc_ega_device::register_r )
case 0x0d: ret = (m_disp_start_addr >> 0) & 0xff; break;
case 0x0e: ret = (m_cursor_addr >> 8) & 0xff; break;
case 0x0f: ret = (m_cursor_addr >> 0) & 0xff; break;
- case 0x10: ret = (m_light_pen_addr >> 8) & 0xff; m_light_pen_latched = FALSE; break;
- case 0x11: ret = (m_light_pen_addr >> 0) & 0xff; m_light_pen_latched = FALSE; break;
+ case 0x10: ret = (m_light_pen_addr >> 8) & 0xff; m_light_pen_latched = false; break;
+ case 0x11: ret = (m_light_pen_addr >> 0) & 0xff; m_light_pen_latched = false; break;
/* all other registers are write only and return 0 */
default: break;
@@ -305,7 +305,7 @@ void crtc_ega_device::handle_line_timer()
{
m_vsync_ff = 0;
- new_vsync = FALSE;
+ new_vsync = false;
}
}
@@ -333,7 +333,7 @@ void crtc_ega_device::handle_line_timer()
m_vsync_width_counter = 0;
m_vsync_ff = 1;
- new_vsync = TRUE;
+ new_vsync = true;
}
/* Check if we have reached the end of the vertical area */
@@ -342,7 +342,7 @@ void crtc_ega_device::handle_line_timer()
m_line_counter = 0;
m_line_address = m_disp_start_addr;
m_line_enable_ff = true;
- set_vblank( FALSE );
+ set_vblank( false );
/* also update the cursor state now */
update_cursor_state();
@@ -375,7 +375,7 @@ void crtc_ega_device::handle_line_timer()
/* Set VBlank signal */
if ( m_line_counter == m_vert_disp_end + 1 )
{
- set_vblank( TRUE );
+ set_vblank( true );
}
/* Schedule our next callback */
@@ -383,7 +383,7 @@ void crtc_ega_device::handle_line_timer()
/* Set VSYNC and DE signals */
set_vsync( new_vsync );
- set_de( m_line_enable_ff ? TRUE : FALSE );
+ set_de( m_line_enable_ff ? true : false );
}
@@ -396,18 +396,18 @@ void crtc_ega_device::device_timer(emu_timer &timer, device_timer_id id, int par
break;
case TIMER_DE_OFF:
- set_de( FALSE );
+ set_de( false );
break;
case TIMER_CUR_ON:
- set_cur( TRUE );
+ set_cur( true );
/* Schedule CURSOR off signal */
m_cur_off_timer->adjust( attotime::from_ticks( 1, m_clock ) );
break;
case TIMER_CUR_OFF:
- set_cur( FALSE );
+ set_cur( false );
break;
case TIMER_HSYNC_ON:
@@ -420,7 +420,7 @@ void crtc_ega_device::device_timer(emu_timer &timer, device_timer_id id, int par
}
m_hsync_width_counter = 0;
- set_hsync( TRUE );
+ set_hsync( true );
/* Schedule HSYNC off signal */
m_hsync_off_timer->adjust( attotime::from_ticks( hsync_width, m_clock ) );
@@ -428,7 +428,7 @@ void crtc_ega_device::device_timer(emu_timer &timer, device_timer_id id, int par
break;
case TIMER_HSYNC_OFF:
- set_hsync( FALSE );
+ set_hsync( false );
break;
case TIMER_LIGHT_PEN_LATCH:
@@ -646,7 +646,7 @@ void crtc_ega_device::device_start()
m_adjust_active = 0;
m_current_disp_addr = 0;
- m_light_pen_latched = FALSE;
+ m_light_pen_latched = false;
m_has_valid_parameters = false;
/* register for state saving */
diff --git a/src/devices/video/dl1416.cpp b/src/devices/video/dl1416.cpp
index 63ec3300a22..7bec9bc693f 100644
--- a/src/devices/video/dl1416.cpp
+++ b/src/devices/video/dl1416.cpp
@@ -98,9 +98,9 @@ static const uint16_t dl1416t_segments[128] = {
dl1416_device::dl1416_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source)
: device_t(mconfig, type, name, tag, owner, clock, shortname, source),
- m_write_enable(FALSE),
- m_chip_enable(FALSE),
- m_cursor_enable(FALSE),
+ m_write_enable(false),
+ m_chip_enable(false),
+ m_cursor_enable(false),
m_update(*this)
{
for (int i = 0; i < 4; i++)
@@ -134,9 +134,9 @@ void dl1416_device::device_reset()
int i;
uint16_t pattern;
/* disable all lines */
- m_chip_enable = FALSE;
- m_write_enable = FALSE;
- m_cursor_enable = FALSE;
+ m_chip_enable = false;
+ m_write_enable = false;
+ m_cursor_enable = false;
/* randomize digit and cursor memory */
for (i = 0; i < 4; i++)
diff --git a/src/devices/video/ef9365.cpp b/src/devices/video/ef9365.cpp
index bdad2330743..90cc08e51fb 100644
--- a/src/devices/video/ef9365.cpp
+++ b/src/devices/video/ef9365.cpp
@@ -349,7 +349,7 @@ void ef9365_device::device_reset()
set_video_mode();
- m_irq_handler(FALSE);
+ m_irq_handler(false);
}
//-------------------------------------------------
diff --git a/src/devices/video/mc6845.cpp b/src/devices/video/mc6845.cpp
index 2830bc8d4b1..932f71d0bee 100644
--- a/src/devices/video/mc6845.cpp
+++ b/src/devices/video/mc6845.cpp
@@ -638,7 +638,7 @@ void mc6845_device::update_upd_adr_timer()
void mc6845_device::handle_line_timer()
{
- int new_vsync = m_vsync;
+ bool new_vsync = m_vsync;
m_character_counter = 0;
m_cursor_x = -1;
@@ -655,7 +655,7 @@ void mc6845_device::handle_line_timer()
{
m_vsync_ff = 0;
- new_vsync = FALSE;
+ new_vsync = false;
}
}
@@ -688,7 +688,7 @@ void mc6845_device::handle_line_timer()
m_vsync_width_counter = 0;
m_vsync_ff = 1;
- new_vsync = TRUE;
+ new_vsync = true;
}
}
else
@@ -747,7 +747,7 @@ void mc6845_device::handle_line_timer()
/* Set VSYNC and DE signals */
set_vsync( new_vsync );
- set_de( m_line_enable_ff ? TRUE : FALSE );
+ set_de( m_line_enable_ff ? true : false );
}
@@ -760,18 +760,18 @@ void mc6845_device::device_timer(emu_timer &timer, device_timer_id id, int param
break;
case TIMER_DE_OFF:
- set_de( FALSE );
+ set_de( false );
break;
case TIMER_CUR_ON:
- set_cur( TRUE );
+ set_cur( true );
/* Schedule CURSOR off signal */
m_cur_off_timer->adjust( attotime::from_ticks( 1, m_clock ) );
break;
case TIMER_CUR_OFF:
- set_cur( FALSE );
+ set_cur( false );
break;
case TIMER_HSYNC_ON:
@@ -779,7 +779,7 @@ void mc6845_device::device_timer(emu_timer &timer, device_timer_id id, int param
uint8_t hsync_width = ( m_sync_width & 0x0f ) ? ( m_sync_width & 0x0f ) : 0x10;
m_hsync_width_counter = 0;
- set_hsync( TRUE );
+ set_hsync( true );
/* Schedule HSYNC off signal */
m_hsync_off_timer->adjust( attotime::from_ticks( hsync_width, m_clock ) );
@@ -787,7 +787,7 @@ void mc6845_device::device_timer(emu_timer &timer, device_timer_id id, int param
break;
case TIMER_HSYNC_OFF:
- set_hsync( FALSE );
+ set_hsync( false );
break;
case TIMER_LIGHT_PEN_LATCH:
diff --git a/src/devices/video/tms9927.cpp b/src/devices/video/tms9927.cpp
index 08a4efd8ef5..4c5d038be70 100644
--- a/src/devices/video/tms9927.cpp
+++ b/src/devices/video/tms9927.cpp
@@ -145,7 +145,7 @@ void tms9927_device::device_timer(emu_timer &timer, device_timer_id id, int para
void tms9927_device::state_postload()
{
- recompute_parameters(TRUE);
+ recompute_parameters(true);
}
@@ -174,7 +174,7 @@ void tms9927_device::generic_access(address_space &space, offs_t offset)
if (!m_reset)
{
m_screen->update_now();
- m_reset = TRUE;
+ m_reset = true;
}
break;
@@ -188,8 +188,8 @@ osd_printf_debug("Up scroll\n");
if (m_reset)
{
m_screen->update_now();
- m_reset = FALSE;
- recompute_parameters(FALSE);
+ m_reset = false;
+ recompute_parameters(false);
}
break;
}
@@ -208,14 +208,14 @@ WRITE8_MEMBER( tms9927_device::write )
case 0x05: /* VERTICAL DATA START */
case 0x06: /* LAST DISPLAYED DATA ROW */
m_reg[offset] = data;
- recompute_parameters(FALSE);
+ recompute_parameters(false);
break;
case 0x0c: /* LOAD CURSOR CHARACTER ADDRESS */
case 0x0d: /* LOAD CURSOR ROW ADDRESS */
osd_printf_debug("Cursor address changed\n");
m_reg[offset - 0x0c + 7] = data;
- recompute_parameters(FALSE);
+ recompute_parameters(false);
break;
default:
@@ -267,7 +267,7 @@ int tms9927_device::cursor_bounds(rectangle &bounds)
}
-void tms9927_device::recompute_parameters(int postload)
+void tms9927_device::recompute_parameters(bool postload)
{
uint16_t offset_hpix, offset_vpix;
attoseconds_t refresh;
@@ -292,16 +292,16 @@ void tms9927_device::recompute_parameters(int postload)
osd_printf_debug("TMS9937: Total = %dx%d, Visible = %dx%d, Offset=%dx%d, Skew=%d, Upscroll=%d\n", m_total_hpix, m_total_vpix, m_visible_hpix, m_visible_vpix, offset_hpix, offset_vpix, SKEW_BITS, m_start_datarow);
/* see if it all makes sense */
- m_valid_config = TRUE;
+ m_valid_config = true;
if ( (m_visible_hpix > m_total_hpix || m_visible_vpix > m_total_vpix) || (((m_visible_hpix-1)<=0) || ((m_visible_vpix-1)<=0)) || ((m_total_hpix * m_total_vpix) == 0) )
{
- m_valid_config = FALSE;
+ m_valid_config = false;
logerror("tms9927: invalid visible size (%dx%d) versus total size (%dx%d)\n", m_visible_hpix, m_visible_vpix, m_total_hpix, m_total_vpix);
}
if (m_clock == 0)
{
- m_valid_config = FALSE;
+ m_valid_config = false;
// TODO: make the screen refresh never, and disable the vblank and odd/even interrupts here!
logerror("tms9927: invalid clock rate of zero defined!\n");
}
diff --git a/src/devices/video/tms9927.h b/src/devices/video/tms9927.h
index cc5d55ada2c..eac4fdc8463 100644
--- a/src/devices/video/tms9927.h
+++ b/src/devices/video/tms9927.h
@@ -54,7 +54,7 @@ private:
};
void state_postload();
- void recompute_parameters(int postload);
+ void recompute_parameters(bool postload);
void generic_access(address_space &space, offs_t offset);
devcb_write_line m_write_vsyn;
diff --git a/src/devices/video/vooddefs.h b/src/devices/video/vooddefs.h
index f579d7454db..0840f80eaf4 100644
--- a/src/devices/video/vooddefs.h
+++ b/src/devices/video/vooddefs.h
@@ -138,14 +138,14 @@ static inline int32_t fast_reciplog(int64_t value, int32_t *log2)
uint32_t temp, recip, rlog;
uint32_t interp;
uint32_t *table;
- int neg = FALSE;
+ int neg = false;
int lz, exp = 0;
/* always work with unsigned numbers */
if (value < 0)
{
value = -value;
- neg = TRUE;
+ neg = true;
}
/* if we've spilled out of 32 bits, push it down under 32 */
diff --git a/src/devices/video/voodoo.cpp b/src/devices/video/voodoo.cpp
index 4982a227dfd..8977bfd5ff1 100644
--- a/src/devices/video/voodoo.cpp
+++ b/src/devices/video/voodoo.cpp
@@ -218,7 +218,7 @@ uint32_t voodoo_reciplog[(2 << RECIPLOG_LOOKUP_BITS) + 2];
*************************************/
#define RASTERIZER_ENTRY(fbzcp, alpha, fog, fbz, tex0, tex1) \
- { nullptr, voodoo_device::raster_##fbzcp##_##alpha##_##fog##_##fbz##_##tex0##_##tex1, FALSE, 0, 0, 0, fbzcp, alpha, fog, fbz, tex0, tex1 },
+ { nullptr, voodoo_device::raster_##fbzcp##_##alpha##_##fog##_##fbz##_##tex0##_##tex1, false, 0, 0, 0, fbzcp, alpha, fog, fbz, tex0, tex1 },
static const raster_info predef_raster_table[] =
{
@@ -248,7 +248,7 @@ int voodoo_device::voodoo_update(bitmap_rgb32 &bitmap, const rectangle &cliprect
int x, y;
/* reset the video changed flag */
- fbi.video_changed = FALSE;
+ fbi.video_changed = false;
/* if we are blank, just fill with black */
if (vd_type <= TYPE_VOODOO_2 && FBIINIT1_SOFTWARE_BLANK(reg[fbiInit1].u))
@@ -325,8 +325,8 @@ int voodoo_device::voodoo_update(bitmap_rgb32 &bitmap, const rectangle &cliprect
}
/* no longer dirty */
- fbi.clut_dirty = FALSE;
- changed = TRUE;
+ fbi.clut_dirty = false;
+ changed = true;
}
/* debugging! */
@@ -424,7 +424,7 @@ void voodoo_device::init_fbi(voodoo_device* vd,fbi_state *f, void *memory, int f
f->height = 384;
/* init the pens */
- f->clut_dirty = TRUE;
+ f->clut_dirty = true;
if (vd->vd_type <= TYPE_VOODOO_2)
{
for (pen = 0; pen < 32; pen++)
@@ -439,7 +439,7 @@ void voodoo_device::init_fbi(voodoo_device* vd,fbi_state *f, void *memory, int f
/* allocate a VBLANK timer */
f->vblank_timer = vd->device->machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(voodoo_device::vblank_callback),vd), vd);
- f->vblank = FALSE;
+ f->vblank = false;
/* initialize the memory FIFO */
f->fifo.base = nullptr;
@@ -501,11 +501,11 @@ void voodoo_device::init_tmu(voodoo_device* vd, tmu_state *t, voodoo_reg *reg, v
t->ram = (uint8_t *)memory;
t->mask = tmem - 1;
t->reg = reg;
- t->regdirty = TRUE;
+ t->regdirty = true;
t->bilinear_mask = (vd->vd_type >= TYPE_VOODOO_2) ? 0xff : 0xf0;
/* mark the NCC tables dirty and configure their registers */
- t->ncc[0].dirty = t->ncc[1].dirty = TRUE;
+ t->ncc[0].dirty = t->ncc[1].dirty = true;
t->ncc[0].reg = &t->reg[nccTable+0];
t->ncc[1].reg = &t->reg[nccTable+12];
@@ -551,12 +551,12 @@ void voodoo_device::voodoo_postload(voodoo_device *vd)
{
int index, subindex;
- vd->fbi.clut_dirty = TRUE;
+ vd->fbi.clut_dirty = true;
for (index = 0; index < ARRAY_LENGTH(vd->tmu); index++)
{
- vd->tmu[index].regdirty = TRUE;
+ vd->tmu[index].regdirty = true;
for (subindex = 0; subindex < ARRAY_LENGTH(vd->tmu[index].ncc); subindex++)
- vd->tmu[index].ncc[subindex].dirty = TRUE;
+ vd->tmu[index].ncc[subindex].dirty = true;
}
/* recompute video memory to get the FBI FIFO base recomputed */
@@ -786,7 +786,7 @@ void voodoo_device::swap_buffers(voodoo_device *vd)
/* force a partial update */
vd->screen->update_partial(vd->screen->vpos());
- vd->fbi.video_changed = TRUE;
+ vd->fbi.video_changed = true;
/* keep a history of swap intervals */
count = vd->fbi.vblank_count;
@@ -818,7 +818,7 @@ void voodoo_device::swap_buffers(voodoo_device *vd)
if (vd->fbi.swaps_pending)
vd->fbi.swaps_pending--;
vd->fbi.vblank_count = 0;
- vd->fbi.vblank_swap_pending = FALSE;
+ vd->fbi.vblank_swap_pending = false;
/* reset the last_op_time to now and start processing the next command */
if (vd->pci.op_pending)
@@ -845,7 +845,7 @@ void voodoo_device::swap_buffers(voodoo_device *vd)
int pixelcount;
int i;
- update_statistics(vd, TRUE);
+ update_statistics(vd, true);
pixelcount = vd->stats.total_pixels_out;
statsptr += sprintf(statsptr, "Swap:%6d\n", vd->stats.swaps);
@@ -907,7 +907,7 @@ TIMER_CALLBACK_MEMBER( voodoo_device::vblank_off_callback )
if (LOG_VBLANK_SWAP) device->logerror("--- vblank end\n");
/* set internal state and call the client */
- fbi.vblank = FALSE;
+ fbi.vblank = false;
// TODO: Vblank IRQ enable is VOODOO3 only?
if (vd_type >= TYPE_VOODOO_3)
@@ -917,14 +917,14 @@ TIMER_CALLBACK_MEMBER( voodoo_device::vblank_off_callback )
reg[intrCtrl].u |= 0x200; // VSYNC int (falling) active
if (!device->m_vblank.isnull())
- device->m_vblank(FALSE);
+ device->m_vblank(false);
}
}
else
{
if (!device->m_vblank.isnull())
- device->m_vblank(FALSE);
+ device->m_vblank(false);
}
/* go to the end of the next frame */
@@ -963,7 +963,7 @@ TIMER_CALLBACK_MEMBER( voodoo_device::vblank_callback )
/* set internal state and call the client */
- fbi.vblank = TRUE;
+ fbi.vblank = true;
// TODO: Vblank IRQ enable is VOODOO3 only?
if (vd_type >= TYPE_VOODOO_3)
@@ -973,13 +973,13 @@ TIMER_CALLBACK_MEMBER( voodoo_device::vblank_callback )
reg[intrCtrl].u |= 0x100; // VSYNC int (rising) active
if (!device->m_vblank.isnull())
- device->m_vblank(TRUE);
+ device->m_vblank(true);
}
}
else
{
if (!device->m_vblank.isnull())
- device->m_vblank(TRUE);
+ device->m_vblank(true);
}
}
@@ -993,7 +993,7 @@ TIMER_CALLBACK_MEMBER( voodoo_device::vblank_callback )
static void reset_counters(voodoo_device *vd)
{
- update_statistics(vd, FALSE);
+ update_statistics(vd, false);
vd->reg[fbiPixelsIn].u = 0;
vd->reg[fbiChromaFail].u = 0;
vd->reg[fbiZfuncFail].u = 0;
@@ -1184,7 +1184,7 @@ static void ncc_table_write(ncc_table *n, offs_t regnum, uint32_t data)
}
/* mark the table dirty */
- n->dirty = TRUE;
+ n->dirty = true;
}
@@ -1216,7 +1216,7 @@ static void ncc_table_update(ncc_table *n)
}
/* no longer dirty */
- n->dirty = FALSE;
+ n->dirty = false;
}
@@ -1363,7 +1363,7 @@ static void recompute_texture_params(tmu_state *t)
}
/* no longer dirty */
- t->regdirty = FALSE;
+ t->regdirty = false;
/* check for separate RGBA filtering */
if (TEXDETAIL_SEPARATE_RGBA_FILTER(t->reg[tDetail].u))
@@ -2027,7 +2027,7 @@ void voodoo_device::cmdfifo_w(voodoo_device *vd, cmdfifo_info *f, offs_t offset,
int32_t cycles = cmdfifo_execute_if_ready(vd, f);
if (cycles > 0)
{
- vd->pci.op_pending = TRUE;
+ vd->pci.op_pending = true;
vd->pci.op_end_time = vd->device->machine().time() + attotime(0, (attoseconds_t)cycles * vd->attoseconds_per_cycle);
if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:direct write start at %d.%08X%08X end at %d.%08X%08X\n", vd->index,
@@ -2054,7 +2054,7 @@ TIMER_CALLBACK_MEMBER( voodoo_device::stall_cpu_callback )
void voodoo_device::check_stalled_cpu(voodoo_device* vd, attotime current_time)
{
- int resume = FALSE;
+ int resume = false;
/* flush anything we can */
if (vd->pci.op_pending)
@@ -2067,10 +2067,10 @@ void voodoo_device::check_stalled_cpu(voodoo_device* vd, attotime current_time)
if (FBIINIT0_ENABLE_MEMORY_FIFO(vd->reg[fbiInit0].u))
{
if (fifo_items(&vd->fbi.fifo) < 2 * 32 * FBIINIT0_MEMORY_FIFO_HWM(vd->reg[fbiInit0].u))
- resume = TRUE;
+ resume = true;
}
else if (fifo_space(&vd->pci.fifo) > 2 * FBIINIT0_PCI_FIFO_LWM(vd->reg[fbiInit0].u))
- resume = TRUE;
+ resume = true;
}
/* if we're stalled until the FIFOs are empty, check now */
@@ -2079,10 +2079,10 @@ void voodoo_device::check_stalled_cpu(voodoo_device* vd, attotime current_time)
if (FBIINIT0_ENABLE_MEMORY_FIFO(vd->reg[fbiInit0].u))
{
if (fifo_empty(&vd->fbi.fifo) && fifo_empty(&vd->pci.fifo))
- resume = TRUE;
+ resume = true;
}
else if (fifo_empty(&vd->pci.fifo))
- resume = TRUE;
+ resume = true;
}
/* resume if necessary */
@@ -2093,7 +2093,7 @@ void voodoo_device::check_stalled_cpu(voodoo_device* vd, attotime current_time)
/* either call the callback, or trigger the trigger */
if (!vd->device->m_stall.isnull())
- vd->device->m_stall(FALSE);
+ vd->device->m_stall(false);
else
vd->device->machine().scheduler().trigger(vd->trigger);
}
@@ -2117,7 +2117,7 @@ void voodoo_device::stall_cpu(voodoo_device *vd, int state, attotime current_tim
/* either call the callback, or spin the CPU */
if (!vd->device->m_stall.isnull())
- vd->device->m_stall(TRUE);
+ vd->device->m_stall(true);
else
vd->cpu->execute().spin_until_trigger(vd->trigger);
@@ -2435,7 +2435,7 @@ int32_t voodoo_device::register_w(voodoo_device *vd, offs_t offset, uint32_t dat
break;
case ftriangleCMD:
- vd->fbi.cheating_allowed = TRUE;
+ vd->fbi.cheating_allowed = true;
vd->fbi.sign = data;
cycles = triangle(vd);
break;
@@ -2475,7 +2475,7 @@ int32_t voodoo_device::register_w(voodoo_device *vd, offs_t offset, uint32_t dat
// TODO: rename vblank_client for less confusion?
if (!vd->device->m_vblank.isnull())
- vd->device->m_vblank(TRUE);
+ vd->device->m_vblank(true);
break;
/* gamma table access -- Voodoo/Voodoo2 only */
@@ -2489,7 +2489,7 @@ int32_t voodoo_device::register_w(voodoo_device *vd, offs_t offset, uint32_t dat
if (index <= 32)
{
vd->fbi.clut[index] = data;
- vd->fbi.clut_dirty = TRUE;
+ vd->fbi.clut_dirty = true;
}
}
else
@@ -2634,7 +2634,7 @@ int32_t voodoo_device::register_w(voodoo_device *vd, offs_t offset, uint32_t dat
{
vd->reg[regnum].u = data;
recompute_video_memory(vd);
- vd->fbi.video_changed = TRUE;
+ vd->fbi.video_changed = true;
}
break;
@@ -2820,12 +2820,12 @@ int32_t voodoo_device::register_w(voodoo_device *vd, offs_t offset, uint32_t dat
if (chips & 2)
{
vd->tmu[0].reg[regnum].u = data;
- vd->tmu[0].regdirty = TRUE;
+ vd->tmu[0].regdirty = true;
}
if (chips & 4)
{
vd->tmu[1].reg[regnum].u = data;
- vd->tmu[1].regdirty = TRUE;
+ vd->tmu[1].regdirty = true;
}
break;
@@ -3139,7 +3139,7 @@ int32_t voodoo_device::lfb_w(voodoo_device* vd, offs_t offset, uint32_t data, ui
case 0: /* front buffer */
dest = (uint16_t *)(vd->fbi.ram + vd->fbi.rgboffs[vd->fbi.frontbuf]);
destmax = (vd->fbi.mask + 1 - vd->fbi.rgboffs[vd->fbi.frontbuf]) / 2;
- vd->fbi.video_changed = TRUE;
+ vd->fbi.video_changed = true;
break;
case 1: /* back buffer */
@@ -3483,7 +3483,7 @@ void voodoo_device::flush_fifos(voodoo_device *vd, attotime current_time)
/* check for recursive calls */
if (in_flush)
return;
- in_flush = TRUE;
+ in_flush = true;
if (!vd->pci.op_pending) fatalerror("flush_fifos called with no pending operation\n");
@@ -3511,8 +3511,8 @@ void voodoo_device::flush_fifos(voodoo_device *vd, attotime current_time)
cycles = cmdfifo_execute_if_ready(vd, &vd->fbi.cmdfifo[0]);
if (cycles == -1)
{
- vd->pci.op_pending = FALSE;
- in_flush = FALSE;
+ vd->pci.op_pending = false;
+ in_flush = false;
if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- CMDFIFO empty\n", vd->index);
return;
}
@@ -3523,8 +3523,8 @@ void voodoo_device::flush_fifos(voodoo_device *vd, attotime current_time)
cycles = cmdfifo_execute_if_ready(vd, &vd->fbi.cmdfifo[1]);
if (cycles == -1)
{
- vd->pci.op_pending = FALSE;
- in_flush = FALSE;
+ vd->pci.op_pending = false;
+ in_flush = false;
if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- CMDFIFO empty\n", vd->index);
return;
}
@@ -3540,8 +3540,8 @@ void voodoo_device::flush_fifos(voodoo_device *vd, attotime current_time)
fifo = &vd->pci.fifo;
else
{
- vd->pci.op_pending = FALSE;
- in_flush = FALSE;
+ vd->pci.op_pending = false;
+ in_flush = false;
if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- FIFOs empty\n", vd->index);
return;
}
@@ -3593,7 +3593,7 @@ void voodoo_device::flush_fifos(voodoo_device *vd, attotime current_time)
if (LOG_FIFO_VERBOSE) vd->device->logerror("VOODOO.%d.FIFO:flush_fifos end -- pending command complete at %d.%08X%08X\n", vd->index,
vd->pci.op_end_time.seconds(), (uint32_t)(vd->pci.op_end_time.attoseconds() >> 32), (uint32_t)vd->pci.op_end_time.attoseconds());
- in_flush = FALSE;
+ in_flush = false;
}
@@ -3607,7 +3607,7 @@ void voodoo_device::flush_fifos(voodoo_device *vd, attotime current_time)
WRITE32_MEMBER( voodoo_device::voodoo_w )
{
- int stall = FALSE;
+ int stall = false;
g_profiler.start(PROFILER_USER1);
@@ -3699,7 +3699,7 @@ WRITE32_MEMBER( voodoo_device::voodoo_w )
/* if we ended up with cycles, mark the operation pending */
if (cycles)
{
- pci.op_pending = TRUE;
+ pci.op_pending = true;
pci.op_end_time = machine().time() + attotime(0, (attoseconds_t)cycles * attoseconds_per_cycle);
if (LOG_FIFO_VERBOSE) logerror("VOODOO.%d.FIFO:direct write start at %d.%08X%08X end at %d.%08X%08X\n", index,
@@ -3736,7 +3736,7 @@ WRITE32_MEMBER( voodoo_device::voodoo_w )
uint8_t valid[4];
/* determine which types of data can go to the memory FIFO */
- valid[0] = TRUE;
+ valid[0] = true;
valid[1] = FBIINIT0_LFB_TO_MEMORY_FIFO(reg[fbiInit0].u);
valid[2] = valid[3] = FBIINIT0_TEXMEM_TO_MEMORY_FIFO(reg[fbiInit0].u);
@@ -3927,7 +3927,7 @@ static uint32_t register_r(voodoo_device *vd, offs_t offset)
case fbiZfuncFail:
case fbiAfuncFail:
case fbiPixelsOut:
- update_statistics(vd, TRUE);
+ update_statistics(vd, true);
case fbiTrianglesOut:
result = vd->reg[regnum].u & 0xffffff;
break;
@@ -3935,19 +3935,19 @@ static uint32_t register_r(voodoo_device *vd, offs_t offset)
if (LOG_REGISTERS)
{
- int logit = TRUE;
+ int logit = true;
/* don't log multiple identical status reads from the same address */
if (regnum == vdstatus)
{
offs_t pc = vd->cpu->safe_pc();
if (pc == vd->last_status_pc && result == vd->last_status_value)
- logit = FALSE;
+ logit = false;
vd->last_status_pc = pc;
vd->last_status_value = result;
}
if (regnum == cmdFifoRdPtr)
- logit = FALSE;
+ logit = false;
if (logit)
vd->device->logerror("VOODOO.%d.REG:%s read = %08X\n", vd->index, vd->regnames[regnum], result);
@@ -4830,7 +4830,7 @@ WRITE32_MEMBER( voodoo_banshee_device::banshee_io_w )
case io_vidProcCfg:
COMBINE_DATA(&banshee.io[offset]);
if ((banshee.io[offset] ^ old) & 0x2800)
- fbi.clut_dirty = TRUE;
+ fbi.clut_dirty = true;
if (LOG_REGISTERS)
logerror("%s:banshee_io_w(%s) = %08X & %08X\n", machine().describe_context(), banshee_io_reg_name[offset], data, mem_mask);
break;
@@ -4840,7 +4840,7 @@ WRITE32_MEMBER( voodoo_banshee_device::banshee_io_w )
if (banshee.io[offset] != fbi.clut[banshee.io[io_dacAddr] & 0x1ff])
{
fbi.clut[banshee.io[io_dacAddr] & 0x1ff] = banshee.io[offset];
- fbi.clut_dirty = TRUE;
+ fbi.clut_dirty = true;
}
if (LOG_REGISTERS)
logerror("%s:banshee_dac_w(%X) = %08X & %08X\n", machine().describe_context(), banshee.io[io_dacAddr] & 0x1ff, data, mem_mask);
@@ -5201,7 +5201,7 @@ int32_t voodoo_device::fastfill(voodoo_device *vd)
int32_t voodoo_device::swapbuffer(voodoo_device* vd, uint32_t data)
{
/* set the don't swap value for Voodoo 2 */
- vd->fbi.vblank_swap_pending = TRUE;
+ vd->fbi.vblank_swap_pending = true;
vd->fbi.vblank_swap = (data >> 1) & 0xff;
vd->fbi.vblank_dont_swap = (data >> 9) & 1;
@@ -5281,7 +5281,7 @@ int32_t voodoo_device::triangle(voodoo_device *vd)
{
case 0: /* front buffer */
drawbuf = (uint16_t *)(vd->fbi.ram + vd->fbi.rgboffs[vd->fbi.frontbuf]);
- vd->fbi.video_changed = TRUE;
+ vd->fbi.video_changed = true;
break;
case 1: /* back buffer */
@@ -5686,7 +5686,7 @@ raster_info *voodoo_device::find_rasterizer(voodoo_device *vd, int texcount)
/* generate a new one using the generic entry */
curinfo.callback = (texcount == 0) ? raster_generic_0tmu : (texcount == 1) ? raster_generic_1tmu : raster_generic_2tmu;
- curinfo.is_generic = TRUE;
+ curinfo.is_generic = true;
curinfo.display = 0;
curinfo.polys = 0;
curinfo.hits = 0;
diff --git a/src/devices/video/voodoo.h b/src/devices/video/voodoo.h
index 0dc3e1d4fbf..30e251c8fcc 100644
--- a/src/devices/video/voodoo.h
+++ b/src/devices/video/voodoo.h
@@ -1614,7 +1614,7 @@ struct raster_info
{
raster_info * next; /* pointer to next entry with the same hash */
poly_draw_scanline_func callback; /* callback pointer */
- uint8_t is_generic; /* TRUE if this is one of the generic rasterizers */
+ bool is_generic; /* true if this is one of the generic rasterizers */
uint8_t display; /* display index */
uint32_t hits; /* how many hits (pixels) we've used this for */
uint32_t polys; /* how many polys we've used this for */
diff --git a/src/devices/video/zeus2.cpp b/src/devices/video/zeus2.cpp
index f7229f96123..020a882d598 100644
--- a/src/devices/video/zeus2.cpp
+++ b/src/devices/video/zeus2.cpp
@@ -826,7 +826,7 @@ if (subregdata_count[which] < 256)
* Process the FIFO
*************************************/
-int zeus2_device::zeus2_fifo_process(const uint32_t *data, int numwords)
+bool zeus2_device::zeus2_fifo_process(const uint32_t *data, int numwords)
{
int dataoffs = 0;
@@ -839,13 +839,13 @@ int zeus2_device::zeus2_fifo_process(const uint32_t *data, int numwords)
if (((data[0] >> 16) & 0x7f) == 0x0) {
if (log_fifo && (data[0] & 0xfff) != 0x2c0)
log_fifo_command(data, numwords, " -- ignored\n");
- return TRUE;
+ return true;
}
// Drop through to 0x05 command
/* 0x05: write 32-bit value to low registers */
case 0x05:
if (numwords < 2)
- return FALSE;
+ return false;
if (log_fifo)
log_fifo_command(data, numwords, " -- reg32");
if (((data[0] >> 16) & 0x7f) != 0x08)
@@ -855,13 +855,13 @@ int zeus2_device::zeus2_fifo_process(const uint32_t *data, int numwords)
/* 0x08: set matrix and point (thegrid) */
case 0x08:
if (numwords < 14)
- return FALSE;
+ return false;
dataoffs = 1;
/* 0x07: set matrix and point (crusnexo) */
case 0x07:
if (numwords < 13)
- return FALSE;
+ return false;
/* extract the matrix from the raw data */
zeus_matrix[0][0] = convert_float(data[dataoffs + 1]);
@@ -899,7 +899,7 @@ int zeus2_device::zeus2_fifo_process(const uint32_t *data, int numwords)
case 0x15:
case 0x16:
if (numwords < 4)
- return FALSE;
+ return false;
/* extract the translation point from the raw data */
zeus_point[0] = convert_float(data[1]);
@@ -920,7 +920,7 @@ int zeus2_device::zeus2_fifo_process(const uint32_t *data, int numwords)
case 0x1c:
if (m_thegrid) {
if (numwords < 3)
- return FALSE;
+ return false;
if (log_fifo)
log_fifo_command(data, numwords, " -- unknown control\n");
break;
@@ -931,7 +931,7 @@ int zeus2_device::zeus2_fifo_process(const uint32_t *data, int numwords)
case 0x10:
case 0x1b:
if (numwords < 4)
- return FALSE;
+ return false;
if (log_fifo)
{
log_fifo_command(data, numwords, " -- unknown control + happens after clear screen\n");
@@ -950,7 +950,7 @@ int zeus2_device::zeus2_fifo_process(const uint32_t *data, int numwords)
// thegrid ???
case 0x1d:
if (numwords < 2)
- return FALSE;
+ return false;
if (log_fifo)
{
log_fifo_command(data, numwords, " -- unknown\n");
@@ -966,7 +966,7 @@ int zeus2_device::zeus2_fifo_process(const uint32_t *data, int numwords)
case 0x23:
case 0x24:
if (numwords < 2)
- return FALSE;
+ return false;
if (log_fifo)
log_fifo_command(data, numwords, "");
zeus2_draw_model(data[1], data[0] & 0xffff, log_fifo);
@@ -975,7 +975,7 @@ int zeus2_device::zeus2_fifo_process(const uint32_t *data, int numwords)
// 0x2d; set direct render pixels location (atlantis)
case 0x2d:
if (numwords < 2)
- return FALSE;
+ return false;
if (log_fifo)
log_fifo_command(data, numwords, "\n");
m_renderAddr = frame_addr_from_phys_addr(data[1]);
@@ -997,14 +997,14 @@ int zeus2_device::zeus2_fifo_process(const uint32_t *data, int numwords)
case 0x38:
if (data[0] == 0x38000000) {
if (numwords < 3)
- return FALSE;
+ return false;
// Direct write to frame buffer
m_frameColor[m_renderAddr++] = conv_rgb555_to_rgb32((uint16_t)data[1]);
m_frameColor[m_renderAddr++] = conv_rgb555_to_rgb32((uint16_t)(data[1] >> 16));
m_frameColor[m_renderAddr++] = conv_rgb555_to_rgb32((uint16_t)data[2]);
m_frameColor[m_renderAddr++] = conv_rgb555_to_rgb32((uint16_t)(data[2] >> 16));
} else if (numwords < 12)
- return FALSE;
+ return false;
//print_fifo_command(data, numwords, "\n");
if (log_fifo)
log_fifo_command(data, numwords, "\n");
@@ -1019,7 +1019,7 @@ int zeus2_device::zeus2_fifo_process(const uint32_t *data, int numwords)
}
break;
}
- return TRUE;
+ return true;
}
/*************************************
@@ -1030,7 +1030,7 @@ void zeus2_device::zeus2_draw_model(uint32_t baseaddr, uint16_t count, int logit
{
uint32_t databuffer[32];
int databufcount = 0;
- int model_done = FALSE;
+ int model_done = false;
uint32_t texdata = 0;
if (logit)
diff --git a/src/devices/video/zeus2.h b/src/devices/video/zeus2.h
index 9df29cfc830..4415329c0a9 100644
--- a/src/devices/video/zeus2.h
+++ b/src/devices/video/zeus2.h
@@ -158,7 +158,7 @@ private:
TIMER_CALLBACK_MEMBER(int_timer_callback);
void zeus2_register32_w(offs_t offset, uint32_t data, int logit);
void zeus2_register_update(offs_t offset, uint32_t oldval, int logit);
- int zeus2_fifo_process(const uint32_t *data, int numwords);
+ bool zeus2_fifo_process(const uint32_t *data, int numwords);
void zeus2_pointer_write(uint8_t which, uint32_t value, int logit);
void load_pal_table(void *wavePtr, uint32_t ctrl, int logit);
void zeus2_draw_model(uint32_t baseaddr, uint16_t count, int logit);