summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/cpu/mn1880/mn1880.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'src/devices/cpu/mn1880/mn1880.cpp')
-rw-r--r--src/devices/cpu/mn1880/mn1880.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/devices/cpu/mn1880/mn1880.cpp b/src/devices/cpu/mn1880/mn1880.cpp
index 0a23b988918..0843947a480 100644
--- a/src/devices/cpu/mn1880/mn1880.cpp
+++ b/src/devices/cpu/mn1880/mn1880.cpp
@@ -66,7 +66,7 @@
incorrectly reported for writes.
* Due to the pipelining of writes, an interrupt may be accepted during
an instruction which attempts to disable interrupts by setting the
- IEMASK bit, which may be cleared insted when control reaches the next
+ IEMASK bit, which may be cleared instead when control reaches the next
sequential instruction from a RETI. This sequencing glitch is
documented in the MN187XX23 user's manual, along with a failsafe way
of setting IEMASK, and similar workarounds in extant program code