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author Vas Crabb <vas@vastheman.com>2022-10-04 12:48:26 +1100
committer Vas Crabb <vas@vastheman.com>2022-10-04 12:51:33 +1100
commitf4b23f173771db595251ea3e1117445f28a8baf0 (patch)
tree54e9fc734a7b30736519ffe075ba15311a757999 /src/devices/cpu/mn1880/mn1880.cpp
parenta272716bce69c16816088fb1f1fb808d7b94c66f (diff)
bus/gameboy: Moved MBC3/MBC30 to their own file as separate devices.
New working software list additions ----------------------------------- gbcolor.xml: Juéduì Wǔlì (China), Wàixīng Tànxiǎn zhī Xīngqiú Dàzhàn (China) [Robyn A1200, taizou]
Diffstat (limited to 'src/devices/cpu/mn1880/mn1880.cpp')
-rw-r--r--src/devices/cpu/mn1880/mn1880.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/devices/cpu/mn1880/mn1880.cpp b/src/devices/cpu/mn1880/mn1880.cpp
index 0a23b988918..0843947a480 100644
--- a/src/devices/cpu/mn1880/mn1880.cpp
+++ b/src/devices/cpu/mn1880/mn1880.cpp
@@ -66,7 +66,7 @@
incorrectly reported for writes.
* Due to the pipelining of writes, an interrupt may be accepted during
an instruction which attempts to disable interrupts by setting the
- IEMASK bit, which may be cleared insted when control reaches the next
+ IEMASK bit, which may be cleared instead when control reaches the next
sequential instruction from a RETI. This sequencing glitch is
documented in the MN187XX23 user's manual, along with a failsafe way
of setting IEMASK, and similar workarounds in extant program code