diff options
Diffstat (limited to 'src/devices/cpu/h8/h8_timer16.cpp')
-rw-r--r-- | src/devices/cpu/h8/h8_timer16.cpp | 360 |
1 files changed, 258 insertions, 102 deletions
diff --git a/src/devices/cpu/h8/h8_timer16.cpp b/src/devices/cpu/h8/h8_timer16.cpp index 81bce7a49a6..263168909d6 100644 --- a/src/devices/cpu/h8/h8_timer16.cpp +++ b/src/devices/cpu/h8/h8_timer16.cpp @@ -1,5 +1,30 @@ // license:BSD-3-Clause // copyright-holders:Olivier Galibert +/*************************************************************************** + + h8_timer16.cpp + + H8 16 bits timer + + TODO: + - IRQs are level triggered? eg. when an interrupt enable flag gets set + while an overflow or compare match flag is 1, will it trigger an IRQ? + Or if it's edge triggered, will it trigger an IRQ on rising edge of + (irq_enable & flag)? Note that mu100 will lock up at boot if it's + triggered at rising edge of (flag) or (irq_enable & flag). + - When writing 0 to the status register(s), the overflow/compare match + flags will only be cleared after a read access was done while they + were set? It's how the databook explains it, similar to HD6301. + - H8/325 16-bit timer is shoehorned in and may have a bug lurking? + It doesn't have TGR registers, but functionally equivalent OCR/ICR. + - Make the base class more generic, and derive the devices from that, + so they don't have to jumble so much with the IRQ/flag bits. The + overflow IRQ/flag being hardcoded on bit 4 is also problematic. + - Proper support for input capture registers. + - Add support for chained timers. + +***************************************************************************/ + #include "emu.h" #include "h8_timer16.h" @@ -8,17 +33,18 @@ // 1 = everything static constexpr int V = 0; -DEFINE_DEVICE_TYPE(H8_TIMER16, h8_timer16_device, "h8_timer16", "H8 16-bit timer") -DEFINE_DEVICE_TYPE(H8_TIMER16_CHANNEL, h8_timer16_channel_device, "h8_timer16_channel", "H8 16-bit timer channel") -DEFINE_DEVICE_TYPE(H8H_TIMER16_CHANNEL, h8h_timer16_channel_device, "h8h_timer16_channel", "H8H 16-bit timer channel") -DEFINE_DEVICE_TYPE(H8S_TIMER16_CHANNEL, h8s_timer16_channel_device, "h8s_timer16_channel", "H8S 16-bit timer channel") +DEFINE_DEVICE_TYPE(H8_TIMER16, h8_timer16_device, "h8_timer16", "H8 16-bit timer") +DEFINE_DEVICE_TYPE(H8_TIMER16_CHANNEL, h8_timer16_channel_device, "h8_timer16_channel", "H8 16-bit timer channel") +DEFINE_DEVICE_TYPE(H8325_TIMER16_CHANNEL, h8325_timer16_channel_device, "h8325_timer16_channel", "H8/325 16-bit timer channel") +DEFINE_DEVICE_TYPE(H8H_TIMER16_CHANNEL, h8h_timer16_channel_device, "h8h_timer16_channel", "H8H 16-bit timer channel") +DEFINE_DEVICE_TYPE(H8S_TIMER16_CHANNEL, h8s_timer16_channel_device, "h8s_timer16_channel", "H8S 16-bit timer channel") -h8_timer16_channel_device::h8_timer16_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : +h8_timer16_channel_device::h8_timer16_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : h8_timer16_channel_device(mconfig, H8_TIMER16_CHANNEL, tag, owner, clock) { } -h8_timer16_channel_device::h8_timer16_channel_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) : +h8_timer16_channel_device::h8_timer16_channel_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock) : device_t(mconfig, type, tag, owner, clock), m_cpu(*this, finder_base::DUMMY_TAG), m_intc(*this, finder_base::DUMMY_TAG), @@ -28,12 +54,12 @@ h8_timer16_channel_device::h8_timer16_channel_device(const machine_config &mconf { } -uint8_t h8_timer16_channel_device::tcr_r() +u8 h8_timer16_channel_device::tcr_r() { return m_tcr; } -void h8_timer16_channel_device::tcr_w(uint8_t data) +void h8_timer16_channel_device::tcr_w(u8 data) { update_counter(); m_tcr = data; @@ -42,27 +68,27 @@ void h8_timer16_channel_device::tcr_w(uint8_t data) recalc_event(); } -uint8_t h8_timer16_channel_device::tmdr_r() +u8 h8_timer16_channel_device::tmdr_r() { return 0x00; } -void h8_timer16_channel_device::tmdr_w(uint8_t data) +void h8_timer16_channel_device::tmdr_w(u8 data) { if(V>=1) logerror("tmdr_w %02x\n", data); } -uint8_t h8_timer16_channel_device::tior_r() +u8 h8_timer16_channel_device::tior_r() { return 0x00; } -void h8_timer16_channel_device::tior_w(offs_t offset, uint8_t data) +void h8_timer16_channel_device::tior_w(offs_t offset, u8 data) { if(V>=1) logerror("tior_w %d, %02x\n", offset, data); } -void h8_timer16_channel_device::set_ier(uint8_t value) +void h8_timer16_channel_device::set_ier(u8 value) { update_counter(); m_ier = value; @@ -76,12 +102,12 @@ void h8_timer16_channel_device::set_enable(bool enable) recalc_event(); } -uint8_t h8_timer16_channel_device::tier_r() +u8 h8_timer16_channel_device::tier_r() { return m_tier; } -void h8_timer16_channel_device::tier_w(uint8_t data) +void h8_timer16_channel_device::tier_w(u8 data) { update_counter(); if(V>=1) logerror("tier_w %02x\n", data); @@ -98,24 +124,29 @@ void h8_timer16_channel_device::tier_w(uint8_t data) recalc_event(); } -uint8_t h8_timer16_channel_device::tsr_r() +u8 h8_timer16_channel_device::tsr_r() { + if(!machine().side_effects_disabled()) + update_counter(); return isr_to_sr(); } -void h8_timer16_channel_device::tsr_w(uint8_t data) +void h8_timer16_channel_device::tsr_w(u8 data) { + update_counter(); if(V>=1) logerror("tsr_w %02x\n", data); isr_update(data); + recalc_event(); } -uint16_t h8_timer16_channel_device::tcnt_r() +u16 h8_timer16_channel_device::tcnt_r() { - update_counter(); + if(!machine().side_effects_disabled()) + update_counter(); return m_tcnt; } -void h8_timer16_channel_device::tcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask) +void h8_timer16_channel_device::tcnt_w(offs_t offset, u16 data, u16 mem_mask) { update_counter(); COMBINE_DATA(&m_tcnt); @@ -123,12 +154,12 @@ void h8_timer16_channel_device::tcnt_w(offs_t offset, uint16_t data, uint16_t me recalc_event(); } -uint16_t h8_timer16_channel_device::tgr_r(offs_t offset) +u16 h8_timer16_channel_device::tgr_r(offs_t offset) { return m_tgr[offset]; } -void h8_timer16_channel_device::tgr_w(offs_t offset, uint16_t data, uint16_t mem_mask) +void h8_timer16_channel_device::tgr_w(offs_t offset, u16 data, u16 mem_mask) { update_counter(); COMBINE_DATA(m_tgr + offset); @@ -136,15 +167,15 @@ void h8_timer16_channel_device::tgr_w(offs_t offset, uint16_t data, uint16_t mem recalc_event(); } -uint16_t h8_timer16_channel_device::tbr_r(offs_t offset) +u16 h8_timer16_channel_device::tbr_r(offs_t offset) { - return m_tgr[offset+m_tgr_count]; + return m_tgr[offset + m_tgr_count]; } -void h8_timer16_channel_device::tbr_w(offs_t offset, uint16_t data, uint16_t mem_mask) +void h8_timer16_channel_device::tbr_w(offs_t offset, u16 data, u16 mem_mask) { COMBINE_DATA(m_tgr + offset + m_tgr_count); - if(V>=1) logerror("tbr%c_w %04x\n", 'a'+offset, m_tgr[offset]); + if(V>=1) logerror("tbr%c_w %04x\n", 'a'+offset, m_tgr[offset + m_tgr_count]); } void h8_timer16_channel_device::device_start() @@ -171,7 +202,7 @@ void h8_timer16_channel_device::device_start() void h8_timer16_channel_device::device_reset() { - // Don't touch channel_active here, top level device handles it + // Don't touch channel_active here, top level device handles it. m_tcr = 0; m_tcnt = 0; memset(m_tgr, 0xff, sizeof(m_tgr)); @@ -188,17 +219,26 @@ void h8_timer16_channel_device::device_reset() m_counter_incrementing = true; } -uint64_t h8_timer16_channel_device::internal_update(uint64_t current_time) +u64 h8_timer16_channel_device::internal_update(u64 current_time) { - if(m_event_time && current_time >= m_event_time) { - update_counter(current_time); - recalc_event(current_time); + while(m_event_time && current_time >= m_event_time) { + update_counter(m_event_time); + recalc_event(m_event_time); } return m_event_time; } -void h8_timer16_channel_device::update_counter(uint64_t cur_time) +void h8_timer16_channel_device::notify_standby(int state) +{ + if(!state && m_event_time) { + u64 delta = m_cpu->total_cycles() - m_cpu->standby_time(); + m_event_time += delta; + m_last_clock_update += delta; + } +} + +void h8_timer16_channel_device::update_counter(u64 cur_time) { if(m_clock_type != DIV_1) return; @@ -211,31 +251,61 @@ void h8_timer16_channel_device::update_counter(uint64_t cur_time) return; } - uint64_t base_time = m_last_clock_update; - uint64_t new_time = cur_time; + u64 base_time = m_last_clock_update; + m_last_clock_update = cur_time; + u64 new_time = cur_time; if(m_clock_divider) { base_time = (base_time + m_phase) >> m_clock_divider; new_time = (new_time + m_phase) >> m_clock_divider; } + if(new_time == base_time) + return; + if(m_counter_incrementing) { - int tt = m_tcnt + new_time - base_time; - m_tcnt = tt % m_counter_cycle; + u16 prev = m_tcnt; + u64 delta = new_time - base_time; + u64 tt = m_tcnt + delta; + + if(prev >= m_counter_cycle) { + if(tt >= 0x10000) + m_tcnt = (tt - 0x10000) % m_counter_cycle; + else + m_tcnt = tt; + } else + m_tcnt = tt % m_counter_cycle; + + for(int i = 0; i < m_tgr_count; i++) { + u16 cmp = m_tgr[i] + 1; + bool match = m_tcnt == cmp || (tt == cmp && tt == m_counter_cycle); + if(!match) { + // Need to do additional checks here for software that polls the flags with interrupts disabled, since recalc_event only schedules IRQ events. + if(prev >= m_counter_cycle) + match = (cmp > prev && tt >= cmp) || (cmp <= m_counter_cycle && m_tcnt < m_counter_cycle && (delta - (0x10000 - prev)) >= cmp); + else if(cmp <= m_counter_cycle) + match = delta >= m_counter_cycle || (prev < cmp && tt >= cmp) || (m_tcnt <= prev && m_tcnt >= cmp); + + if(match && BIT(m_ier, i) && m_interrupt[i] != -1) + logerror("update_counter unexpected TGR %d IRQ\n, i"); + } - for(int i=0; i<m_tgr_count; i++) - if((m_ier & (1 << i)) && (tt == m_tgr[i] || m_tcnt == m_tgr[i]) && m_interrupt[i] != -1) { + if(match) { m_isr |= 1 << i; - m_intc->internal_interrupt(m_interrupt[i]); + if(BIT(m_ier, i) && m_interrupt[i] != -1) + m_intc->internal_interrupt(m_interrupt[i]); } - if(tt >= 0x10000 && (m_ier & IRQ_V) && m_interrupt[4] != -1) { + } + if(tt >= 0x10000 && (m_counter_cycle == 0x10000 || prev >= m_counter_cycle)) { m_isr |= IRQ_V; - m_intc->internal_interrupt(m_interrupt[4]); + if(m_ier & IRQ_V && m_interrupt[4] != -1) + m_intc->internal_interrupt(m_interrupt[4]); } - } else - m_tcnt = (((m_tcnt ^ 0xffff) + new_time - base_time) % m_counter_cycle) ^ 0xffff; - m_last_clock_update = cur_time; + } else { + logerror("decrementing counter\n"); + exit(1); + } } -void h8_timer16_channel_device::recalc_event(uint64_t cur_time) +void h8_timer16_channel_device::recalc_event(u64 cur_time) { if(!m_channel_active) { m_event_time = 0; @@ -243,7 +313,7 @@ void h8_timer16_channel_device::recalc_event(uint64_t cur_time) } bool update_cpu = cur_time == 0; - uint64_t old_event_time = m_event_time; + u64 old_event_time = m_event_time; if(m_clock_type != DIV_1) { m_event_time = 0; @@ -257,28 +327,26 @@ void h8_timer16_channel_device::recalc_event(uint64_t cur_time) cur_time = m_cpu->total_cycles(); if(m_counter_incrementing) { - uint32_t event_delay = 0xffffffff; - if(m_tgr_clearing >= 0 && m_tgr[m_tgr_clearing]) - m_counter_cycle = m_tgr[m_tgr_clearing]; - else { + u32 event_delay = 0xffffffff; + if(m_tgr_clearing >= 0) + m_counter_cycle = m_tgr[m_tgr_clearing] + 1; + else m_counter_cycle = 0x10000; - if(m_ier & IRQ_V) { - event_delay = m_counter_cycle - m_tcnt; - if(!event_delay) - event_delay = m_counter_cycle; - } - } - for(int i=0; i<m_tgr_count; i++) - if(m_ier & (1 << i)) { - uint32_t new_delay = 0xffffffff; - if(m_tgr[i] > m_tcnt) { - if(m_tcnt >= m_counter_cycle || m_tgr[i] <= m_counter_cycle) - new_delay = m_tgr[i] - m_tcnt; - } else if(m_tgr[i] <= m_counter_cycle) { + if((m_ier & IRQ_V && m_interrupt[4] != -1) && (m_counter_cycle == 0x10000 || m_tcnt >= m_counter_cycle)) + event_delay = 0x10000 - m_tcnt; + + for(int i = 0; i < m_tgr_count; i++) + if(BIT(m_ier, i) && m_interrupt[i] != -1) { + u32 new_delay = 0xffffffff; + u16 cmp = m_tgr[i] + 1; + if(cmp > m_tcnt) { + if(m_tcnt >= m_counter_cycle || cmp <= m_counter_cycle) + new_delay = cmp - m_tcnt; + } else if(cmp <= m_counter_cycle) { if(m_tcnt < m_counter_cycle) - new_delay = (m_counter_cycle - m_tcnt) + m_tgr[i]; + new_delay = (m_counter_cycle - m_tcnt) + cmp; else - new_delay = (0x10000 - m_tcnt) + m_tgr[i]; + new_delay = (0x10000 - m_tcnt) + cmp; } if(event_delay > new_delay) @@ -289,7 +357,6 @@ void h8_timer16_channel_device::recalc_event(uint64_t cur_time) m_event_time = ((((cur_time + (1ULL << m_clock_divider) - m_phase) >> m_clock_divider) + event_delay - 1) << m_clock_divider) + m_phase; else m_event_time = 0; - } else { logerror("decrementing counter\n"); exit(1); @@ -299,7 +366,8 @@ void h8_timer16_channel_device::recalc_event(uint64_t cur_time) m_cpu->internal_update(); } -h8_timer16_device::h8_timer16_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + +h8_timer16_device::h8_timer16_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : device_t(mconfig, H8_TIMER16, tag, owner, clock), m_cpu(*this, finder_base::DUMMY_TAG), m_timer_channel(*this, "%u", 0) @@ -311,83 +379,83 @@ void h8_timer16_device::device_start() save_item(NAME(m_tstr)); } -void h8_timer16_device::device_reset() +void h8_timer16_device::device_reset_after_children() { m_tstr = m_default_tstr; - for(int i=0; i<m_timer_count; i++) + for(int i = 0; i < m_timer_count; i++) m_timer_channel[i]->set_enable((m_tstr >> i) & 1); } -uint8_t h8_timer16_device::tstr_r() +u8 h8_timer16_device::tstr_r() { return m_tstr; } -void h8_timer16_device::tstr_w(uint8_t data) +void h8_timer16_device::tstr_w(u8 data) { if(V>=1) logerror("tstr_w %02x\n", data); m_tstr = data; - for(int i=0; i<m_timer_count; i++) + for(int i = 0; i < m_timer_count; i++) m_timer_channel[i]->set_enable((m_tstr >> i) & 1); } -uint8_t h8_timer16_device::tsyr_r() +u8 h8_timer16_device::tsyr_r() { return 0x00; } -void h8_timer16_device::tsyr_w(uint8_t data) +void h8_timer16_device::tsyr_w(u8 data) { if(V>=1) logerror("tsyr_w %02x\n", data); } -uint8_t h8_timer16_device::tmdr_r() +u8 h8_timer16_device::tmdr_r() { return 0x00; } -void h8_timer16_device::tmdr_w(uint8_t data) +void h8_timer16_device::tmdr_w(u8 data) { if(V>=1) logerror("tmdr_w %02x\n", data); } -uint8_t h8_timer16_device::tfcr_r() +u8 h8_timer16_device::tfcr_r() { return 0x00; } -void h8_timer16_device::tfcr_w(uint8_t data) +void h8_timer16_device::tfcr_w(u8 data) { if(V>=1) logerror("tfcr_w %02x\n", data); } -uint8_t h8_timer16_device::toer_r() +u8 h8_timer16_device::toer_r() { return 0x00; } -void h8_timer16_device::toer_w(uint8_t data) +void h8_timer16_device::toer_w(u8 data) { if(V>=1) logerror("toer_w %02x\n", data); } -uint8_t h8_timer16_device::tocr_r() +u8 h8_timer16_device::tocr_r() { return 0x00; } -void h8_timer16_device::tocr_w(uint8_t data) +void h8_timer16_device::tocr_w(u8 data) { if(V>=1) logerror("tocr_w %02x\n", data); } -uint8_t h8_timer16_device::tisr_r(offs_t offset) +u8 h8_timer16_device::tisr_r(offs_t offset) { - uint8_t r = 0; - for(int i=0; i<m_timer_count; i++) + u8 r = 0; + for(int i = 0; i < m_timer_count; i++) r |= m_timer_channel[i]->tisr_r(offset) << i; - for(int i=m_timer_count; i<4; i++) + for(int i = m_timer_count; i < 4; i++) r |= 0x11 <<i; if(V>=1) logerror("tisr%c_r %02x\n", 'a'+offset, r); @@ -395,39 +463,38 @@ uint8_t h8_timer16_device::tisr_r(offs_t offset) return r; } -void h8_timer16_device::tisr_w(offs_t offset, uint8_t data) +void h8_timer16_device::tisr_w(offs_t offset, u8 data) { if(V>=1) logerror("tisr%c_w %02x\n", 'a'+offset, data); - for(int i=0; i<m_timer_count; i++) + for(int i = 0; i < m_timer_count; i++) m_timer_channel[i]->tisr_w(offset, data >> i); } -uint8_t h8_timer16_device::tisrc_r() +u8 h8_timer16_device::tisrc_r() { return tisr_r(2); } -void h8_timer16_device::tisrc_w(uint8_t data) +void h8_timer16_device::tisrc_w(u8 data) { tisr_w(2, data); } -void h8_timer16_device::tolr_w(uint8_t data) +void h8_timer16_device::tolr_w(u8 data) { if(V>=1) logerror("tocr_w %02x\n", data); } - void h8_timer16_channel_device::tier_update() { } -void h8_timer16_channel_device::isr_update(uint8_t val) +void h8_timer16_channel_device::isr_update(u8 val) { } -uint8_t h8_timer16_channel_device::isr_to_sr() const +u8 h8_timer16_channel_device::isr_to_sr() const { return 0x00; } @@ -436,7 +503,7 @@ void h8_timer16_channel_device::tcr_update() { } -void h8_timer16_channel_device::tisr_w(int offset, uint8_t value) +void h8_timer16_channel_device::tisr_w(int offset, u8 value) { update_counter(); if(!(value & 0x01)) { @@ -480,7 +547,7 @@ void h8_timer16_channel_device::tisr_w(int offset, uint8_t value) recalc_event(); } -uint8_t h8_timer16_channel_device::tisr_r(int offset) const +u8 h8_timer16_channel_device::tisr_r(int offset) const { switch(offset) { case 0: @@ -493,7 +560,93 @@ uint8_t h8_timer16_channel_device::tisr_r(int offset) const return 0x00; } -h8h_timer16_channel_device::h8h_timer16_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + +// H8/325 + +h8325_timer16_channel_device::h8325_timer16_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : + h8_timer16_channel_device(mconfig, H8325_TIMER16_CHANNEL, tag, owner, clock), + m_tcsr(0) +{ +} + +h8325_timer16_channel_device::~h8325_timer16_channel_device() +{ +} + +void h8325_timer16_channel_device::device_start() +{ + h8_timer16_channel_device::device_start(); + + save_item(NAME(m_tcsr)); +} + +void h8325_timer16_channel_device::device_reset() +{ + h8_timer16_channel_device::device_reset(); + + m_tcsr = 0; + m_clock_divider = 1; +} + +void h8325_timer16_channel_device::tcr_update() +{ + m_ier = + (m_tcr & 0x10 ? IRQ_V : 0) | + (m_tcr & 0x20 ? IRQ_A : 0) | + (m_tcr & 0x40 ? IRQ_B : 0) | + (m_tcr & 0x80 ? IRQ_C : 0); + + m_clock_type = DIV_1; + m_clock_divider = 0; + + switch (m_tcr & 3) { + case 0: // /2 + m_clock_divider = 1; + break; + case 1: // /8 + m_clock_divider = 3; + break; + case 2: // /32 + m_clock_divider = 5; + break; + case 3: // TODO: external + m_clock_type = -1; + break; + } +} + +void h8325_timer16_channel_device::isr_update(u8 val) +{ + m_tcsr = val; + + if(val & 1) + m_tgr_clearing = 0; + else + m_tgr_clearing = TGR_CLEAR_NONE; + + if(!(val & 0x10)) + m_isr &= ~IRQ_V; + if(!(val & 0x20)) + m_isr &= ~IRQ_A; + if(!(val & 0x40)) + m_isr &= ~IRQ_B; + if(!(val & 0x80)) + m_isr &= ~IRQ_C; +} + +u8 h8325_timer16_channel_device::isr_to_sr() const +{ + return (m_tcsr & 0x0f) | + (m_isr & IRQ_V ? 0x10 : 0) | + (m_isr & IRQ_A ? 0x20 : 0) | + (m_isr & IRQ_B ? 0x40 : 0) | + (m_isr & IRQ_C ? 0x80 : 0); +} + + +// H8H + +h8h_timer16_channel_device::h8h_timer16_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : h8_timer16_channel_device(mconfig, H8H_TIMER16_CHANNEL, tag, owner, clock) { } @@ -511,7 +664,7 @@ void h8h_timer16_channel_device::tier_update() (m_tier & 0x04 ? IRQ_V : 0); } -void h8h_timer16_channel_device::isr_update(uint8_t val) +void h8h_timer16_channel_device::isr_update(u8 val) { if(!(val & 1)) m_isr &= ~IRQ_A; @@ -521,7 +674,7 @@ void h8h_timer16_channel_device::isr_update(uint8_t val) m_isr &= ~IRQ_V; } -uint8_t h8h_timer16_channel_device::isr_to_sr() const +u8 h8h_timer16_channel_device::isr_to_sr() const { return 0xf8 | (m_isr & IRQ_V ? 4 : 0) | (m_isr & IRQ_B ? 2 : 0) | (m_isr & IRQ_A ? 1 : 0); } @@ -577,7 +730,10 @@ void h8h_timer16_channel_device::tcr_update() } } -h8s_timer16_channel_device::h8s_timer16_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + +// H8S + +h8s_timer16_channel_device::h8s_timer16_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : h8_timer16_channel_device(mconfig, H8S_TIMER16_CHANNEL, tag, owner, clock) { } @@ -599,12 +755,12 @@ void h8s_timer16_channel_device::tier_update() (m_tier & 0x80 ? IRQ_TRIG : 0); } -void h8s_timer16_channel_device::isr_update(uint8_t val) +void h8s_timer16_channel_device::isr_update(u8 val) { m_isr &= (val | m_tier_mask | 0xc0); } -uint8_t h8s_timer16_channel_device::isr_to_sr() const +u8 h8s_timer16_channel_device::isr_to_sr() const { return 0xc0 | m_isr; } |