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-rw-r--r--src/devices/cpu/xtensa/xtensa.cpp94
-rw-r--r--src/devices/cpu/xtensa/xtensa.h3
-rw-r--r--src/devices/cpu/xtensa/xtensa_helper.cpp40
-rw-r--r--src/devices/cpu/xtensa/xtensa_helper.h42
-rw-r--r--src/devices/cpu/xtensa/xtensad.cpp100
-rw-r--r--src/devices/cpu/xtensa/xtensad.h4
6 files changed, 136 insertions, 147 deletions
diff --git a/src/devices/cpu/xtensa/xtensa.cpp b/src/devices/cpu/xtensa/xtensa.cpp
index 42967c6ed74..67a5d37991b 100644
--- a/src/devices/cpu/xtensa/xtensa.cpp
+++ b/src/devices/cpu/xtensa/xtensa.cpp
@@ -906,15 +906,15 @@ void xtensa_device::getop_and_execute()
}
case 0b0110: // RER - Read External Register
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d\n", m_helper.s_st1_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d\n", xtensa_helper::s_st1_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4));
break;
case 0b0111: // WER - Write External Register
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d\n", m_helper.s_st1_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d\n", xtensa_helper::s_st1_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4));
break;
case 0b1110: // NSA (with Miscellaneous Operations Option) - Normalization Shift Amount
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d\n", m_helper.s_st1_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d\n", xtensa_helper::s_st1_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4));
break;
case 0b1111: // NSAU (with Miscellaneous Operations Option) - Normalization Shift Amount Unsigned
@@ -954,11 +954,11 @@ void xtensa_device::getop_and_execute()
{
case 0b0011: case 0b0101: case 0b0110: case 0b0111: // RITLB0, PITLB, WITLB, RITLB1
case 0b1011: case 0b1101: case 0b1110: case 0b1111: // RDTLB0, PDTLB, WDTLB, RDTLB1
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d\n", m_helper.s_tlb_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d\n", xtensa_helper::s_tlb_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4));
break;
case 0b0100: case 0b1100: // IITLB, IDTLB
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d\n", m_helper.s_tlb_ops[BIT(inst, 12, 4)], BIT(inst, 8, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d\n", xtensa_helper::s_tlb_ops[BIT(inst, 12, 4)], BIT(inst, 8, 4));
break;
default:
@@ -1220,12 +1220,12 @@ void xtensa_device::getop_and_execute()
switch (BIT(inst, 20, 4))
{
case 0b0000: case 0b0001: case 0b0010: case 0b0011: case 0b0100: // ANDB, ANDBC, ORB, ORBC, XORB (with Boolean Option)
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sb%d, b%d, b%d\n", m_helper.s_rst2_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sb%d, b%d, b%d\n", xtensa_helper::s_rst2_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b1000: case 0b1010: case 0b1011: // MULL, MULUH, MULSH (with 32-bit Integer Multiply Option)
case 0b1100: case 0b1101: case 0b1110: case 0b1111: // QUOU, QUOS, REMU, REMS (with 32-bit Integer Divide Option)
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, a%d\n", m_helper.s_rst2_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, a%d\n", xtensa_helper::s_rst2_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
default:
@@ -1241,7 +1241,7 @@ void xtensa_device::getop_and_execute()
{
const u8 spcreg = BIT(inst, 8, 8);
const u8 reg = BIT(inst, 4, 4);
- LOGMASKED(LOG_EXTREG_OPS, "%s.%-3d a%d\n", "rsr", m_helper.special_reg(spcreg, BIT(inst, 20)), reg);
+ LOGMASKED(LOG_EXTREG_OPS, "%s.%-3d a%d\n", "rsr", xtensa_helper::special_reg(spcreg, BIT(inst, 20)), reg);
set_reg(reg, space(AS_EXTREGS).read_dword(spcreg));
break;
}
@@ -1250,7 +1250,7 @@ void xtensa_device::getop_and_execute()
{
const u8 spcreg = BIT(inst, 8, 8);
const u8 reg = BIT(inst, 4, 4);
- LOGMASKED(LOG_EXTREG_OPS, "%s.%-3d a%d\n", "wsr", m_helper.special_reg(spcreg, BIT(inst, 20)), reg);
+ LOGMASKED(LOG_EXTREG_OPS, "%s.%-3d a%d\n", "wsr", xtensa_helper::special_reg(spcreg, BIT(inst, 20)), reg);
space(AS_EXTREGS).write_dword(spcreg, get_reg(reg));
break;
}
@@ -1265,15 +1265,15 @@ void xtensa_device::getop_and_execute()
}
case 0b0011: // CLAMPS (with Miscellaneous Operations Option)
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, %d\n", m_helper.s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4) + 7);
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, %d\n", xtensa_helper::s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4) + 7);
break;
case 0b0100: // MIN (with Miscellaneous Operations Option)
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, a%d\n", m_helper.s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, a%d\n", xtensa_helper::s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b0101: // MAX (with Miscellaneous Operations Option)
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, a%d\n", m_helper.s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, a%d\n", xtensa_helper::s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b0110: // MINU (with Miscellaneous Operations Option) - Minimum Value Unsigned
@@ -1291,7 +1291,7 @@ void xtensa_device::getop_and_execute()
}
case 0b0111: // MAXU (with Miscellaneous Operations Option)
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, a%d\n", m_helper.s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, a%d\n", xtensa_helper::s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b1000: // MOVEQZ
@@ -1342,11 +1342,11 @@ void xtensa_device::getop_and_execute()
}
case 0b1100: case 0b1101: // MOVF, MOVT (with Boolean Option)
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, b%d\n", m_helper.s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, b%d\n", xtensa_helper::s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b1110: case 0b1111: // RUR, WUR (TODO: TIE user_register names)
- LOGMASKED(LOG_UNHANDLED_OPS, "%s.u%-2d a%d\n", m_helper.s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 4, 8), BIT(inst, 12, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%s.u%-2d a%d\n", xtensa_helper::s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 4, 8), BIT(inst, 12, 4));
break;
}
break;
@@ -1395,11 +1395,11 @@ void xtensa_device::getop_and_execute()
switch (BIT(inst, 20, 4))
{
case 0b0000: // L32E
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, %s\n", "l32e", BIT(inst, 4, 4), BIT(inst, 8, 4), m_helper.format_imm(int(BIT(inst, 12, 4)) * 4 - 64));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, %s\n", "l32e", BIT(inst, 4, 4), BIT(inst, 8, 4), xtensa_helper::format_imm(int(BIT(inst, 12, 4)) * 4 - 64));
break;
case 0b0100: // S32E
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, %s\n", "s32e", BIT(inst, 4, 4), BIT(inst, 8, 4), m_helper.format_imm(int(BIT(inst, 12, 4)) * 4 - 64));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, %s\n", "s32e", BIT(inst, 4, 4), BIT(inst, 8, 4), xtensa_helper::format_imm(int(BIT(inst, 12, 4)) * 4 - 64));
break;
default:
@@ -1412,15 +1412,15 @@ void xtensa_device::getop_and_execute()
switch (BIT(inst, 20, 4))
{
case 0b0000: case 0b0001: case 0b0010: case 0b0100: case 0b0101: // ADD.S, SUB.S, MUL.S, MADD.S, MSUB.S
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sf%d, f%d, f%d\n", m_helper.s_fp0_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sf%d, f%d, f%d\n", xtensa_helper::s_fp0_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b1000: case 0b1001: case 0b1010: case 0b1011: case 0b1110: // ROUND.S, TRUNC.S, FLOOR.S, CEIL.S, UTRUNC.S
- LOGMASKED(LOG_UNHANDLED_OPS, "%-7s a%d, f%d, %d\n", m_helper.s_fp0_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-7s a%d, f%d, %d\n", xtensa_helper::s_fp0_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b1100: case 0b1101: // FLOAT.S, UFLOAT.S
- LOGMASKED(LOG_UNHANDLED_OPS, "%-7s f%d, a%d, %d\n", m_helper.s_fp0_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-7s f%d, a%d, %d\n", xtensa_helper::s_fp0_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b1111: // FP1OP
@@ -1462,15 +1462,15 @@ void xtensa_device::getop_and_execute()
switch (BIT(inst, 20, 4))
{
case 0b0001: case 0b0010: case 0b0011: case 0b0100: case 0b0101: case 0b0110: case 0b0111: // UN.S, OEQ.S, UEQ.S, OLT.S, ULT.S, OLE.S, ULE.S
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sb%d, f%d, f%d\n", m_helper.s_fp1_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sb%d, f%d, f%d\n", xtensa_helper::s_fp1_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b1000: case 0b1001: case 0b1010: case 0b1011: // MOVEQZ.S, MOVNEZ.S, MOVLTZ.S, MOVGEZ.S
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sf%d, f%d, a%d\n", m_helper.s_fp1_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sf%d, f%d, a%d\n", xtensa_helper::s_fp1_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b1100: case 0b1101: // MOVF.S, MOVT.S
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sf%d, f%d, b%d\n", m_helper.s_fp1_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sf%d, f%d, b%d\n", xtensa_helper::s_fp1_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
default:
@@ -1565,15 +1565,15 @@ void xtensa_device::getop_and_execute()
}
case 0b1011: // L32AI (with Multiprocessor Synchronization Option)
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, %s\n", m_helper.s_lsai_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4), m_helper.format_imm((inst >> 16) * 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, %s\n", xtensa_helper::s_lsai_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 16) * 4));
break;
case 0b1111: // S32RI (with Multiprocessor Synchronization Option)
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, %s\n", m_helper.s_lsai_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4), m_helper.format_imm((inst >> 16) * 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, %s\n", xtensa_helper::s_lsai_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 16) * 4));
break;
case 0b1110: // S32C1I (with Conditional Store Option)
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, %s\n", m_helper.s_lsai_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4), m_helper.format_imm((inst >> 16) * 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sa%d, a%d, %s\n", xtensa_helper::s_lsai_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 16) * 4));
break;
case 0b0111: // CACHE
@@ -1582,30 +1582,30 @@ void xtensa_device::getop_and_execute()
case 0b0000: case 0b0001: case 0b0010: case 0b0011: // DPFR, DPFW, DPFRO, DPFWO (with Data Cache Option)
case 0b0100: case 0b0101: case 0b0110: case 0b0111: // DHWB, DHWBI, DHI, DII (with Data Cache Option)
case 0b1100: case 0b1110: case 0b1111: // IPF, IHI, III (with Instruction Cache Option)
- LOGMASKED(LOG_UNHANDLED_CACHE_OPS, "%-8sa%d, %s\n", m_helper.s_cache_ops[BIT(inst, 4, 4)], BIT(inst, 8, 4), m_helper.format_imm((inst >> 16) * 4));
+ LOGMASKED(LOG_UNHANDLED_CACHE_OPS, "%-8sa%d, %s\n", xtensa_helper::s_cache_ops[BIT(inst, 4, 4)], BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 16) * 4));
break;
case 0b1000: // DCE (with Data Cache Option)
switch (BIT(inst, 16, 4))
{
case 0b0000: // DPFL (with Data Cache Index Lock Option)
- LOGMASKED(LOG_UNHANDLED_CACHE_OPS, "%-8sa%d, %s\n", "dpfl", BIT(inst, 8, 4), m_helper.format_imm((inst >> 20) * 4));
+ LOGMASKED(LOG_UNHANDLED_CACHE_OPS, "%-8sa%d, %s\n", "dpfl", BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 20) * 4));
break;
case 0b0010: // DHU (with Data Cache Index Lock Option)
- LOGMASKED(LOG_UNHANDLED_CACHE_OPS, "%-8sa%d, %s\n", "dhu", BIT(inst, 8, 4), m_helper.format_imm((inst >> 20) * 4));
+ LOGMASKED(LOG_UNHANDLED_CACHE_OPS, "%-8sa%d, %s\n", "dhu", BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 20) * 4));
break;
case 0b0011: // DIU (with Data Cache Index Lock Option)
- LOGMASKED(LOG_UNHANDLED_CACHE_OPS, "%-8sa%d, %s\n", "diu", BIT(inst, 8, 4), m_helper.format_imm((inst >> 20) * 4));
+ LOGMASKED(LOG_UNHANDLED_CACHE_OPS, "%-8sa%d, %s\n", "diu", BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 20) * 4));
break;
case 0b0100: // DIWB (added in T1050)
- LOGMASKED(LOG_UNHANDLED_CACHE_OPS, "%-8sa%d, %s\n", "diwb", BIT(inst, 8, 4), m_helper.format_imm((inst >> 20) * 4));
+ LOGMASKED(LOG_UNHANDLED_CACHE_OPS, "%-8sa%d, %s\n", "diwb", BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 20) * 4));
break;
case 0b0101: // DIWBI (added in T1050)
- LOGMASKED(LOG_UNHANDLED_CACHE_OPS, "%-8sa%d, %s\n", "diwbi", BIT(inst, 8, 4), m_helper.format_imm((inst >> 20) * 4));
+ LOGMASKED(LOG_UNHANDLED_CACHE_OPS, "%-8sa%d, %s\n", "diwbi", BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 20) * 4));
break;
}
break;
@@ -1614,15 +1614,15 @@ void xtensa_device::getop_and_execute()
switch (BIT(inst, 16, 4))
{
case 0b0000: // IPFL
- LOGMASKED(LOG_UNHANDLED_CACHE_OPS, "%-8sa%d, %s\n", "ipfl", BIT(inst, 8, 4), m_helper.format_imm((inst >> 20) * 4));
+ LOGMASKED(LOG_UNHANDLED_CACHE_OPS, "%-8sa%d, %s\n", "ipfl", BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 20) * 4));
break;
case 0b0010: // IHU
- LOGMASKED(LOG_UNHANDLED_CACHE_OPS, "%-8sa%d, %s\n", "ihu", BIT(inst, 8, 4), m_helper.format_imm((inst >> 20) * 4));
+ LOGMASKED(LOG_UNHANDLED_CACHE_OPS, "%-8sa%d, %s\n", "ihu", BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 20) * 4));
break;
case 0b0011: // IIU
- LOGMASKED(LOG_UNHANDLED_CACHE_OPS, "%-8sa%d, %s\n", "iiu", BIT(inst, 8, 4), m_helper.format_imm((inst >> 20) * 4));
+ LOGMASKED(LOG_UNHANDLED_CACHE_OPS, "%-8sa%d, %s\n", "iiu", BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 20) * 4));
break;
default:
@@ -1673,7 +1673,7 @@ void xtensa_device::getop_and_execute()
if (BIT(inst, 12, 2) == 0)
{
// LSI, SSI, LSIU, SSIU
- LOGMASKED(LOG_UNHANDLED_OPS, "%-8sf%d, a%d, %s\n", m_helper.s_lsci_ops[BIT(inst, 14, 2)], BIT(inst, 4, 4), BIT(inst, 8, 4), m_helper.format_imm(BIT(inst, 16, 8) * 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%-8sf%d, a%d, %s\n", xtensa_helper::s_lsci_ops[BIT(inst, 14, 2)], BIT(inst, 4, 4), BIT(inst, 8, 4), xtensa_helper::format_imm(BIT(inst, 16, 8) * 4));
break;
}
else
@@ -1688,8 +1688,8 @@ void xtensa_device::getop_and_execute()
case 0b0000: case 0b0001: // MACID, MACCD
if (BIT(inst, 18, 2) == 0b10)
{
- LOGMASKED(LOG_UNHANDLED_OPS, "%s.dd.%s.%s m%d, a%d, m%d, m%d\n", m_helper.s_mac16_ops[BIT(inst, 18, 2)],
- m_helper.s_mac16_half[BIT(inst, 16, 2)],
+ LOGMASKED(LOG_UNHANDLED_OPS, "%s.dd.%s.%s m%d, a%d, m%d, m%d\n", xtensa_helper::s_mac16_ops[BIT(inst, 18, 2)],
+ xtensa_helper::s_mac16_half[BIT(inst, 16, 2)],
BIT(inst, 20) ? "lddec" : "ldinc",
BIT(inst, 12, 2), BIT(inst, 8, 4),
BIT(inst, 14), BIT(inst, 6) + 2);
@@ -1704,8 +1704,8 @@ void xtensa_device::getop_and_execute()
case 0b0100: case 0b0101: // MACIA, MACCA
if (BIT(inst, 18, 2) == 0b10)
{
- LOGMASKED(LOG_UNHANDLED_OPS, "%s.da.%s.%s m%d, a%d, m%d, a%d\n", m_helper.s_mac16_ops[BIT(inst, 18, 2)],
- m_helper.s_mac16_half[BIT(inst, 16, 2)],
+ LOGMASKED(LOG_UNHANDLED_OPS, "%s.da.%s.%s m%d, a%d, m%d, a%d\n", xtensa_helper::s_mac16_ops[BIT(inst, 18, 2)],
+ xtensa_helper::s_mac16_half[BIT(inst, 16, 2)],
BIT(inst, 20) ? "lddec" : "ldinc",
BIT(inst, 12, 2), BIT(inst, 8, 4),
BIT(inst, 14), BIT(inst, 4, 4));
@@ -1720,7 +1720,7 @@ void xtensa_device::getop_and_execute()
case 0b0010: // MACDD
if (BIT(inst, 18, 2) != 0b00)
{
- LOGMASKED(LOG_UNHANDLED_OPS, "%s.dd.%s m%d, m%d\n", m_helper.s_mac16_ops[BIT(inst, 18, 2)], m_helper.s_mac16_half[BIT(inst, 16, 2)], BIT(inst, 14), BIT(inst, 6) + 2);
+ LOGMASKED(LOG_UNHANDLED_OPS, "%s.dd.%s m%d, m%d\n", xtensa_helper::s_mac16_ops[BIT(inst, 18, 2)], xtensa_helper::s_mac16_half[BIT(inst, 16, 2)], BIT(inst, 14), BIT(inst, 6) + 2);
}
else
{
@@ -1732,7 +1732,7 @@ void xtensa_device::getop_and_execute()
case 0b0011: // MACAD
if (BIT(inst, 18, 2) != 0b00)
{
- LOGMASKED(LOG_UNHANDLED_OPS, "%s.ad.%s a%d, m%d\n", m_helper.s_mac16_ops[BIT(inst, 18, 2)], m_helper.s_mac16_half[BIT(inst, 16, 2)], BIT(inst, 8, 4), BIT(inst, 6) + 2);
+ LOGMASKED(LOG_UNHANDLED_OPS, "%s.ad.%s a%d, m%d\n", xtensa_helper::s_mac16_ops[BIT(inst, 18, 2)], xtensa_helper::s_mac16_half[BIT(inst, 16, 2)], BIT(inst, 8, 4), BIT(inst, 6) + 2);
}
else
{
@@ -1744,7 +1744,7 @@ void xtensa_device::getop_and_execute()
case 0b0110: // MACDA
if (BIT(inst, 18, 2) != 0b00)
{
- LOGMASKED(LOG_UNHANDLED_OPS, "%s.da.%s m%d, a%d\n", m_helper.s_mac16_ops[BIT(inst, 18, 2)], m_helper.s_mac16_half[BIT(inst, 16, 2)], BIT(inst, 14), BIT(inst, 4, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%s.da.%s m%d, a%d\n", xtensa_helper::s_mac16_ops[BIT(inst, 18, 2)], xtensa_helper::s_mac16_half[BIT(inst, 16, 2)], BIT(inst, 14), BIT(inst, 4, 4));
}
else
{
@@ -1754,7 +1754,7 @@ void xtensa_device::getop_and_execute()
break;
case 0b0111: // MACAA
- LOGMASKED(LOG_UNHANDLED_OPS, "%s.aa.%s a%d, a%d\n", m_helper.s_mac16_ops[BIT(inst, 18, 2)], m_helper.s_mac16_half[BIT(inst, 16, 2)], BIT(inst, 8, 4), BIT(inst, 4, 4));
+ LOGMASKED(LOG_UNHANDLED_OPS, "%s.aa.%s a%d, a%d\n", xtensa_helper::s_mac16_ops[BIT(inst, 18, 2)], xtensa_helper::s_mac16_half[BIT(inst, 16, 2)], BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b1000: case 0b1001: // MACI, MACC
@@ -1830,7 +1830,7 @@ void xtensa_device::getop_and_execute()
case 0b10: // BI0
{
const u8 reg = BIT(inst, 8, 4);
- const u32 imm = m_helper.s_b4const[BIT(inst, 12, 4)];
+ const u32 imm = xtensa_helper::s_b4const[BIT(inst, 12, 4)];
const u32 addr = m_pc + 4 + s8(u8(inst >> 16));
const u8 optype = BIT(inst, 6, 2);
switch (optype)
@@ -1931,7 +1931,7 @@ void xtensa_device::getop_and_execute()
case 0b10: // BLTUI - Branch if Less Than Unsigned Immediate
{
const u8 reg = BIT(inst, 8, 4);
- const u32 imm = m_helper.s_b4constu[BIT(inst, 12, 4)];
+ const u32 imm = xtensa_helper::s_b4constu[BIT(inst, 12, 4)];
const u32 addr = m_pc + 4 + s8(u8(inst >> 16));
if (get_reg(reg) < imm)
{
@@ -1944,7 +1944,7 @@ void xtensa_device::getop_and_execute()
case 0b11: // BGEUI - Branch if Greater Than or Eq Unsigned Immediate
{
const u8 reg = BIT(inst, 8, 4);
- const u32 imm = m_helper.s_b4constu[BIT(inst, 12, 4)];
+ const u32 imm = xtensa_helper::s_b4constu[BIT(inst, 12, 4)];
const u32 addr = m_pc + 4 + s8(u8(inst >> 16));
if (get_reg(reg) >= imm)
{
diff --git a/src/devices/cpu/xtensa/xtensa.h b/src/devices/cpu/xtensa/xtensa.h
index cd5903bfcdb..fc0e1d46c26 100644
--- a/src/devices/cpu/xtensa/xtensa.h
+++ b/src/devices/cpu/xtensa/xtensa.h
@@ -6,7 +6,6 @@
#pragma once
-#include "xtensa_helper.h"
class xtensa_device : public cpu_device
{
@@ -204,8 +203,6 @@ private:
u32 m_irq_vectors[32];
u32 m_startupvector;
-
- xtensa_helper m_helper;
};
DECLARE_DEVICE_TYPE(XTENSA, xtensa_device)
diff --git a/src/devices/cpu/xtensa/xtensa_helper.cpp b/src/devices/cpu/xtensa/xtensa_helper.cpp
index a49ef5511a1..fc8449a4382 100644
--- a/src/devices/cpu/xtensa/xtensa_helper.cpp
+++ b/src/devices/cpu/xtensa/xtensa_helper.cpp
@@ -188,43 +188,3 @@ const char *const xtensa_helper::s_b_ops[16] =
"bnone", "beq", "blt", "bltu", "ball", "bbc", "bbci", "bbci",
"bany", "bne", "bge", "bgeu", "bnall", "bbs", "bbsi", "bbsih"
};
-
-std::string xtensa_helper::format_imm(uint32_t imm)
-{
- if (s32(imm) < 0)
- {
- if (s32(imm < -9))
- {
- return util::string_format("-0x%X", -imm);
- }
- else
- {
- return util::string_format("-%X", -imm);
- }
- }
- else
- {
- if (imm > 9)
- {
- return util::string_format("0x%X", imm);
- }
- else
- {
- return util::string_format("%X", imm);
- }
- }
-}
-
-
-std::string xtensa_helper::special_reg(uint8_t n, bool wsr)
-{
- if (n == 226 && !wsr)
- return "interrupt";
-
- const char *s = xtensa_helper::special_regs[n];
- if (s[0] == '\0')
- return util::string_format("s%u", n);
- else
- return s;
-}
-
diff --git a/src/devices/cpu/xtensa/xtensa_helper.h b/src/devices/cpu/xtensa/xtensa_helper.h
index 14d32eafaca..91ba66cddfc 100644
--- a/src/devices/cpu/xtensa/xtensa_helper.h
+++ b/src/devices/cpu/xtensa/xtensa_helper.h
@@ -26,8 +26,44 @@ public:
static const int32_t s_b4const[16];
static const uint32_t s_b4constu[16];
static const char *const s_b_ops[16];
- std::string format_imm(uint32_t imm);
- std::string special_reg(uint8_t n, bool wsr);
+
+ static std::string format_imm(uint32_t imm)
+ {
+ if (s32(imm) < 0)
+ {
+ if (s32(imm < -9))
+ {
+ return util::string_format("-0x%X", -imm);
+ }
+ else
+ {
+ return util::string_format("-%X", -imm);
+ }
+ }
+ else
+ {
+ if (imm > 9)
+ {
+ return util::string_format("0x%X", imm);
+ }
+ else
+ {
+ return util::string_format("%X", imm);
+ }
+ }
+ }
+
+ static std::string special_reg(uint8_t n, bool wsr)
+ {
+ if (n == 226 && !wsr)
+ return "interrupt";
+
+ const char *s = xtensa_helper::special_regs[n];
+ if (s[0] == '\0')
+ return util::string_format("s%u", n);
+ else
+ return s;
+ }
};
-#endif
+#endif // MAME_CPU_XTENSA_XTENSA_HELPER_H
diff --git a/src/devices/cpu/xtensa/xtensad.cpp b/src/devices/cpu/xtensa/xtensad.cpp
index c42219d0428..e02a1ce0cee 100644
--- a/src/devices/cpu/xtensa/xtensad.cpp
+++ b/src/devices/cpu/xtensa/xtensad.cpp
@@ -226,7 +226,7 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
switch (BIT(inst, 12, 4))
{
case 0b0000: case 0b0001: case 0b0010: case 0b0011: // SSR, SSL, SSA8L, SSA8B
- util::stream_format(stream, "%-8sa%d", m_helper.s_st1_ops[BIT(inst, 12, 4)], BIT(inst, 8, 4));
+ util::stream_format(stream, "%-8sa%d", xtensa_helper::s_st1_ops[BIT(inst, 12, 4)], BIT(inst, 8, 4));
break;
case 0b0100: // SSAI
@@ -235,7 +235,7 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
case 0b0110: case 0b0111: // RER, WER
case 0b1110: case 0b1111: // NSA, NSAU (with Miscellaneous Operations Option)
- util::stream_format(stream, "%-8sa%d, a%d", m_helper.s_st1_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4));
+ util::stream_format(stream, "%-8sa%d, a%d", xtensa_helper::s_st1_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4));
break;
case 0b1000: // ROTW (with Windowed Register Option)
@@ -253,11 +253,11 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
{
case 0b0011: case 0b0101: case 0b0110: case 0b0111: // RITLB0, PITLB, WITLB, RITLB1
case 0b1011: case 0b1101: case 0b1110: case 0b1111: // RDTLB0, PDTLB, WDTLB, RDTLB1
- util::stream_format(stream, "%-8sa%d, a%d", m_helper.s_tlb_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4));
+ util::stream_format(stream, "%-8sa%d, a%d", xtensa_helper::s_tlb_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4));
break;
case 0b0100: case 0b1100: // IITLB, IDTLB
- util::stream_format(stream, "%-8sa%d", m_helper.s_tlb_ops[BIT(inst, 12, 4)], BIT(inst, 8, 4));
+ util::stream_format(stream, "%-8sa%d", xtensa_helper::s_tlb_ops[BIT(inst, 12, 4)], BIT(inst, 8, 4));
break;
default:
@@ -314,7 +314,7 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
break;
case 0b0110: // XSR (added in T1040)
- util::stream_format(stream, "xsr.%-3s a%d", m_helper.special_reg(BIT(inst, 8, 8), true), BIT(inst, 4, 4));
+ util::stream_format(stream, "xsr.%-3s a%d", xtensa_helper::special_reg(BIT(inst, 8, 8), true), BIT(inst, 4, 4));
break;
case 0b0111: // ACCER (added in RC-2009.0)
@@ -418,12 +418,12 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
switch (BIT(inst, 20, 4))
{
case 0b0000: case 0b0001: case 0b0010: case 0b0011: case 0b0100: // ANDB, ANDBC, ORB, ORBC, XORB (with Boolean Option)
- util::stream_format(stream, "%-8sb%d, b%d, b%d", m_helper.s_rst2_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ util::stream_format(stream, "%-8sb%d, b%d, b%d", xtensa_helper::s_rst2_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b1000: case 0b1010: case 0b1011: // MULL, MULUH, MULSH (with 32-bit Integer Multiply Option)
case 0b1100: case 0b1101: case 0b1110: case 0b1111: // QUOU, QUOS, REMU, REMS (with 32-bit Integer Divide Option)
- util::stream_format(stream, "%-8sa%d, a%d, a%d", m_helper.s_rst2_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ util::stream_format(stream, "%-8sa%d, a%d, a%d", xtensa_helper::s_rst2_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
default:
@@ -436,24 +436,24 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
switch (BIT(inst, 20, 4))
{
case 0b0000: case 0b0001: // RSR, WSR
- util::stream_format(stream, "%s.%-3d a%d", m_helper.s_rst3_ops[BIT(inst, 20, 4)], m_helper.special_reg(BIT(inst, 8, 8), BIT(inst, 20)), BIT(inst, 4, 4));
+ util::stream_format(stream, "%s.%-3d a%d", xtensa_helper::s_rst3_ops[BIT(inst, 20, 4)], xtensa_helper::special_reg(BIT(inst, 8, 8), BIT(inst, 20)), BIT(inst, 4, 4));
break;
case 0b0010: case 0b0011: // SEXT, CLAMPS (with Miscellaneous Operations Option)
- util::stream_format(stream, "%-8sa%d, a%d, %d", m_helper.s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4) + 7);
+ util::stream_format(stream, "%-8sa%d, a%d, %d", xtensa_helper::s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4) + 7);
break;
case 0b0100: case 0b0101: case 0b0110: case 0b0111: // MIN, MAX, MINU, MAXU (with Miscellaneous Operations Option)
case 0b1000: case 0b1001: case 0b1010: case 0b1011: // MOVEQZ, MOVNEZ, MOVLTZ, MOVGEZ
- util::stream_format(stream, "%-8sa%d, a%d, a%d", m_helper.s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ util::stream_format(stream, "%-8sa%d, a%d, a%d", xtensa_helper::s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b1100: case 0b1101: // MOVF, MOVT (with Boolean Option)
- util::stream_format(stream, "%-8sa%d, a%d, b%d", m_helper.s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ util::stream_format(stream, "%-8sa%d, a%d, b%d", xtensa_helper::s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b1110: case 0b1111: // RUR, WUR (TODO: TIE user_register names)
- util::stream_format(stream, "%s.u%-2d a%d", m_helper.s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 4, 8), BIT(inst, 12, 4));
+ util::stream_format(stream, "%s.u%-2d a%d", xtensa_helper::s_rst3_ops[BIT(inst, 20, 4)], BIT(inst, 4, 8), BIT(inst, 12, 4));
break;
}
break;
@@ -495,11 +495,11 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
switch (BIT(inst, 20, 4))
{
case 0b0000: // L32E
- util::stream_format(stream, "%-8sa%d, a%d, %s", "l32e", BIT(inst, 4, 4), BIT(inst, 8, 4), m_helper.format_imm(int(BIT(inst, 12, 4)) * 4 - 64));
+ util::stream_format(stream, "%-8sa%d, a%d, %s", "l32e", BIT(inst, 4, 4), BIT(inst, 8, 4), xtensa_helper::format_imm(int(BIT(inst, 12, 4)) * 4 - 64));
break;
case 0b0100: // S32E
- util::stream_format(stream, "%-8sa%d, a%d, %s", "s32e", BIT(inst, 4, 4), BIT(inst, 8, 4), m_helper.format_imm(int(BIT(inst, 12, 4)) * 4 - 64));
+ util::stream_format(stream, "%-8sa%d, a%d, %s", "s32e", BIT(inst, 4, 4), BIT(inst, 8, 4), xtensa_helper::format_imm(int(BIT(inst, 12, 4)) * 4 - 64));
break;
default:
@@ -512,15 +512,15 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
switch (BIT(inst, 20, 4))
{
case 0b0000: case 0b0001: case 0b0010: case 0b0100: case 0b0101: // ADD.S, SUB.S, MUL.S, MADD.S, MSUB.S
- util::stream_format(stream, "%-8sf%d, f%d, f%d", m_helper.s_fp0_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ util::stream_format(stream, "%-8sf%d, f%d, f%d", xtensa_helper::s_fp0_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b1000: case 0b1001: case 0b1010: case 0b1011: case 0b1110: // ROUND.S, TRUNC.S, FLOOR.S, CEIL.S, UTRUNC.S
- util::stream_format(stream, "%-7s a%d, f%d, %d", m_helper.s_fp0_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ util::stream_format(stream, "%-7s a%d, f%d, %d", xtensa_helper::s_fp0_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b1100: case 0b1101: // FLOAT.S, UFLOAT.S
- util::stream_format(stream, "%-7s f%d, a%d, %d", m_helper.s_fp0_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ util::stream_format(stream, "%-7s f%d, a%d, %d", xtensa_helper::s_fp0_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b1111: // FP1OP
@@ -562,15 +562,15 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
switch (BIT(inst, 20, 4))
{
case 0b0001: case 0b0010: case 0b0011: case 0b0100: case 0b0101: case 0b0110: case 0b0111: // UN.S, OEQ.S, UEQ.S, OLT.S, ULT.S, OLE.S, ULE.S
- util::stream_format(stream, "%-8sb%d, f%d, f%d", m_helper.s_fp1_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ util::stream_format(stream, "%-8sb%d, f%d, f%d", xtensa_helper::s_fp1_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b1000: case 0b1001: case 0b1010: case 0b1011: // MOVEQZ.S, MOVNEZ.S, MOVLTZ.S, MOVGEZ.S
- util::stream_format(stream, "%-8sf%d, f%d, a%d", m_helper.s_fp1_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ util::stream_format(stream, "%-8sf%d, f%d, a%d", xtensa_helper::s_fp1_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b1100: case 0b1101: // MOVF.S, MOVT.S
- util::stream_format(stream, "%-8sf%d, f%d, b%d", m_helper.s_fp1_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
+ util::stream_format(stream, "%-8sf%d, f%d, b%d", xtensa_helper::s_fp1_ops[BIT(inst, 20, 4)], BIT(inst, 12, 4), BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
default:
@@ -593,17 +593,17 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
switch (BIT(inst, 12, 4))
{
case 0b0000: case 0b0100: // L8UI, S8I
- util::stream_format(stream, "%-8sa%d, a%d, %s", m_helper.s_lsai_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4), m_helper.format_imm(inst >> 16));
+ util::stream_format(stream, "%-8sa%d, a%d, %s", xtensa_helper::s_lsai_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4), xtensa_helper::format_imm(inst >> 16));
break;
case 0b0001: case 0b0101: case 0b1001: // L16UI, S16I, L16SI
- util::stream_format(stream, "%-8sa%d, a%d, %s", m_helper.s_lsai_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4), m_helper.format_imm((inst >> 16) * 2));
+ util::stream_format(stream, "%-8sa%d, a%d, %s", xtensa_helper::s_lsai_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 16) * 2));
break;
case 0b0010: case 0b0110: // L32I, S32I
case 0b1011: case 0b1111: // L32AI, S32RI (with Multiprocessor Synchronization Option)
case 0b1110: // S32C1I (with Conditional Store Option)
- util::stream_format(stream, "%-8sa%d, a%d, %s", m_helper.s_lsai_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4), m_helper.format_imm((inst >> 16) * 4));
+ util::stream_format(stream, "%-8sa%d, a%d, %s", xtensa_helper::s_lsai_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 16) * 4));
break;
case 0b0111: // CACHE
@@ -612,30 +612,30 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
case 0b0000: case 0b0001: case 0b0010: case 0b0011: // DPFR, DPFW, DPFRO, DPFWO (with Data Cache Option)
case 0b0100: case 0b0101: case 0b0110: case 0b0111: // DHWB, DHWBI, DHI, DII (with Data Cache Option)
case 0b1100: case 0b1110: case 0b1111: // IPF, IHI, III (with Instruction Cache Option)
- util::stream_format(stream, "%-8sa%d, %s", m_helper.s_cache_ops[BIT(inst, 4, 4)], BIT(inst, 8, 4), m_helper.format_imm((inst >> 16) * 4));
+ util::stream_format(stream, "%-8sa%d, %s", xtensa_helper::s_cache_ops[BIT(inst, 4, 4)], BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 16) * 4));
break;
case 0b1000: // DCE (with Data Cache Option)
switch (BIT(inst, 16, 4))
{
case 0b0000: // DPFL (with Data Cache Index Lock Option)
- util::stream_format(stream, "%-8sa%d, %s", "dpfl", BIT(inst, 8, 4), m_helper.format_imm((inst >> 20) * 4));
+ util::stream_format(stream, "%-8sa%d, %s", "dpfl", BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 20) * 4));
break;
case 0b0010: // DHU (with Data Cache Index Lock Option)
- util::stream_format(stream, "%-8sa%d, %s", "dhu", BIT(inst, 8, 4), m_helper.format_imm((inst >> 20) * 4));
+ util::stream_format(stream, "%-8sa%d, %s", "dhu", BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 20) * 4));
break;
case 0b0011: // DIU (with Data Cache Index Lock Option)
- util::stream_format(stream, "%-8sa%d, %s", "diu", BIT(inst, 8, 4), m_helper.format_imm((inst >> 20) * 4));
+ util::stream_format(stream, "%-8sa%d, %s", "diu", BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 20) * 4));
break;
case 0b0100: // DIWB (added in T1050)
- util::stream_format(stream, "%-8sa%d, %s", "diwb", BIT(inst, 8, 4), m_helper.format_imm((inst >> 20) * 4));
+ util::stream_format(stream, "%-8sa%d, %s", "diwb", BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 20) * 4));
break;
case 0b0101: // DIWBI (added in T1050)
- util::stream_format(stream, "%-8sa%d, %s", "diwbi", BIT(inst, 8, 4), m_helper.format_imm((inst >> 20) * 4));
+ util::stream_format(stream, "%-8sa%d, %s", "diwbi", BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 20) * 4));
break;
}
break;
@@ -644,15 +644,15 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
switch (BIT(inst, 16, 4))
{
case 0b0000: // IPFL
- util::stream_format(stream, "%-8sa%d, %s", "ipfl", BIT(inst, 8, 4), m_helper.format_imm((inst >> 20) * 4));
+ util::stream_format(stream, "%-8sa%d, %s", "ipfl", BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 20) * 4));
break;
case 0b0010: // IHU
- util::stream_format(stream, "%-8sa%d, %s", "ihu", BIT(inst, 8, 4), m_helper.format_imm((inst >> 20) * 4));
+ util::stream_format(stream, "%-8sa%d, %s", "ihu", BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 20) * 4));
break;
case 0b0011: // IIU
- util::stream_format(stream, "%-8sa%d, %s", "iiu", BIT(inst, 8, 4), m_helper.format_imm((inst >> 20) * 4));
+ util::stream_format(stream, "%-8sa%d, %s", "iiu", BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 20) * 4));
break;
default:
@@ -668,11 +668,11 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
break;
case 0b1010: // MOVI
- util::stream_format(stream, "%-8sa%d, %s", "movi", BIT(inst, 4, 4), m_helper.format_imm(util::sext((inst & 0x000f00) + (inst >> 16), 12)));
+ util::stream_format(stream, "%-8sa%d, %s", "movi", BIT(inst, 4, 4), xtensa_helper::format_imm(util::sext((inst & 0x000f00) + (inst >> 16), 12)));
break;
case 0b1100: case 0b1101: // ADDI, ADDMI
- util::stream_format(stream, "%-8sa%d, a%d, %s", m_helper.s_lsai_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4), m_helper.format_imm(s8(u8(inst >> 16)) * (BIT(inst, 12) ? 256 : 1)));
+ util::stream_format(stream, "%-8sa%d, a%d, %s", xtensa_helper::s_lsai_ops[BIT(inst, 12, 4)], BIT(inst, 4, 4), BIT(inst, 8, 4), xtensa_helper::format_imm(s8(u8(inst >> 16)) * (BIT(inst, 12) ? 256 : 1)));
break;
default:
@@ -685,7 +685,7 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
if (BIT(inst, 12, 2) == 0)
{
// LSI, SSI, LSIU, SSIU
- util::stream_format(stream, "%-8sf%d, a%d, %s", m_helper.s_lsci_ops[BIT(inst, 14, 2)], BIT(inst, 4, 4), BIT(inst, 8, 4), m_helper.format_imm(BIT(inst, 16, 8) * 4));
+ util::stream_format(stream, "%-8sf%d, a%d, %s", xtensa_helper::s_lsci_ops[BIT(inst, 14, 2)], BIT(inst, 4, 4), BIT(inst, 8, 4), xtensa_helper::format_imm(BIT(inst, 16, 8) * 4));
return 3 | SUPPORTED;
}
else
@@ -699,8 +699,8 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
{
case 0b0000: case 0b0001: // MACID, MACCD
if (BIT(inst, 18, 2) == 0b10)
- util::stream_format(stream, "%s.dd.%s.%s m%d, a%d, m%d, m%d", m_helper.s_mac16_ops[BIT(inst, 18, 2)],
- m_helper.s_mac16_half[BIT(inst, 16, 2)],
+ util::stream_format(stream, "%s.dd.%s.%s m%d, a%d, m%d, m%d", xtensa_helper::s_mac16_ops[BIT(inst, 18, 2)],
+ xtensa_helper::s_mac16_half[BIT(inst, 16, 2)],
BIT(inst, 20) ? "lddec" : "ldinc",
BIT(inst, 12, 2), BIT(inst, 8, 4),
BIT(inst, 14), BIT(inst, 6) + 2);
@@ -713,8 +713,8 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
case 0b0100: case 0b0101: // MACIA, MACCA
if (BIT(inst, 18, 2) == 0b10)
- util::stream_format(stream, "%s.da.%s.%s m%d, a%d, m%d, a%d", m_helper.s_mac16_ops[BIT(inst, 18, 2)],
- m_helper.s_mac16_half[BIT(inst, 16, 2)],
+ util::stream_format(stream, "%s.da.%s.%s m%d, a%d, m%d, a%d", xtensa_helper::s_mac16_ops[BIT(inst, 18, 2)],
+ xtensa_helper::s_mac16_half[BIT(inst, 16, 2)],
BIT(inst, 20) ? "lddec" : "ldinc",
BIT(inst, 12, 2), BIT(inst, 8, 4),
BIT(inst, 14), BIT(inst, 4, 4));
@@ -727,7 +727,7 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
case 0b0010: // MACDD
if (BIT(inst, 18, 2) != 0b00)
- util::stream_format(stream, "%s.dd.%s m%d, m%d", m_helper.s_mac16_ops[BIT(inst, 18, 2)], m_helper.s_mac16_half[BIT(inst, 16, 2)], BIT(inst, 14), BIT(inst, 6) + 2);
+ util::stream_format(stream, "%s.dd.%s m%d, m%d", xtensa_helper::s_mac16_ops[BIT(inst, 18, 2)], xtensa_helper::s_mac16_half[BIT(inst, 16, 2)], BIT(inst, 14), BIT(inst, 6) + 2);
else
{
util::stream_format(stream, "%-8s0x%02X ; reserved", "db", inst & 0xff);
@@ -737,7 +737,7 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
case 0b0011: // MACAD
if (BIT(inst, 18, 2) != 0b00)
- util::stream_format(stream, "%s.ad.%s a%d, m%d", m_helper.s_mac16_ops[BIT(inst, 18, 2)], m_helper.s_mac16_half[BIT(inst, 16, 2)], BIT(inst, 8, 4), BIT(inst, 6) + 2);
+ util::stream_format(stream, "%s.ad.%s a%d, m%d", xtensa_helper::s_mac16_ops[BIT(inst, 18, 2)], xtensa_helper::s_mac16_half[BIT(inst, 16, 2)], BIT(inst, 8, 4), BIT(inst, 6) + 2);
else
{
util::stream_format(stream, "%-8s0x%02X ; reserved", "db", inst & 0xff);
@@ -747,7 +747,7 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
case 0b0110: // MACDA
if (BIT(inst, 18, 2) != 0b00)
- util::stream_format(stream, "%s.da.%s m%d, a%d", m_helper.s_mac16_ops[BIT(inst, 18, 2)], m_helper.s_mac16_half[BIT(inst, 16, 2)], BIT(inst, 14), BIT(inst, 4, 4));
+ util::stream_format(stream, "%s.da.%s m%d, a%d", xtensa_helper::s_mac16_ops[BIT(inst, 18, 2)], xtensa_helper::s_mac16_half[BIT(inst, 16, 2)], BIT(inst, 14), BIT(inst, 4, 4));
else
{
util::stream_format(stream, "%-8s0x%02X ; reserved", "db", inst & 0xff);
@@ -756,7 +756,7 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
break;
case 0b0111: // MACAA
- util::stream_format(stream, "%s.aa.%s a%d, a%d", m_helper.s_mac16_ops[BIT(inst, 18, 2)], m_helper.s_mac16_half[BIT(inst, 16, 2)], BIT(inst, 8, 4), BIT(inst, 4, 4));
+ util::stream_format(stream, "%s.aa.%s a%d, a%d", xtensa_helper::s_mac16_ops[BIT(inst, 18, 2)], xtensa_helper::s_mac16_half[BIT(inst, 16, 2)], BIT(inst, 8, 4), BIT(inst, 4, 4));
break;
case 0b1000: case 0b1001: // MACI, MACC
@@ -796,18 +796,18 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
break;
case 0b01: // BZ
- util::stream_format(stream, "%-8sa%d, 0x%08X", m_helper.s_bz_ops[BIT(inst, 6, 2)], BIT(inst, 8, 4), pc + 4 + util::sext(inst >> 12, 12));
+ util::stream_format(stream, "%-8sa%d, 0x%08X", xtensa_helper::s_bz_ops[BIT(inst, 6, 2)], BIT(inst, 8, 4), pc + 4 + util::sext(inst >> 12, 12));
return 3 | STEP_COND | SUPPORTED;
case 0b10: // BI0
- util::stream_format(stream, "%-8sa%d, %s, 0x%08X", m_helper.s_bi0_ops[BIT(inst, 6, 2)], BIT(inst, 8, 4), m_helper.format_imm(m_helper.s_b4const[BIT(inst, 12, 4)]), pc + 4 + s8(u8(inst >> 16)));
+ util::stream_format(stream, "%-8sa%d, %s, 0x%08X", xtensa_helper::s_bi0_ops[BIT(inst, 6, 2)], BIT(inst, 8, 4), xtensa_helper::format_imm(xtensa_helper::s_b4const[BIT(inst, 12, 4)]), pc + 4 + s8(u8(inst >> 16)));
return 3 | STEP_COND | SUPPORTED;
case 0b11: // BI1
switch (BIT(inst, 6, 2))
{
case 0b00: // ENTRY
- util::stream_format(stream, "%-8sa%d, %s", "entry", BIT(inst, 8, 4), m_helper.format_imm((inst >> 12) * 4));
+ util::stream_format(stream, "%-8sa%d, %s", "entry", BIT(inst, 8, 4), xtensa_helper::format_imm((inst >> 12) * 4));
break;
case 0b01: // B1
@@ -836,7 +836,7 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
break;
case 0b10: case 0b11: // BLTUI, BGEUI
- util::stream_format(stream, "%-8sa%d, %s, 0x%08X", BIT(inst, 6) ? "bgeui" : "bltui", BIT(inst, 8, 4), m_helper.format_imm(m_helper.s_b4constu[BIT(inst, 12, 4)]), pc + 4 + s8(u8(inst >> 16)));
+ util::stream_format(stream, "%-8sa%d, %s, 0x%08X", BIT(inst, 6) ? "bgeui" : "bltui", BIT(inst, 8, 4), xtensa_helper::format_imm(xtensa_helper::s_b4constu[BIT(inst, 12, 4)]), pc + 4 + s8(u8(inst >> 16)));
return 3 | STEP_COND | SUPPORTED;
}
break;
@@ -852,12 +852,12 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
else
{
// BNONE, BEQ, BLT, BLTU, BALL, BBC, BBCI, BANY, BNE, BGE, BGEU, BNALL, BBS
- util::stream_format(stream, "%-8sa%d, a%d, 0x%08X", m_helper.s_b_ops[BIT(inst, 12, 4)], BIT(inst, 8, 4), BIT(inst, 4, 4), pc + 4 + s8(u8(inst >> 16)));
+ util::stream_format(stream, "%-8sa%d, a%d, 0x%08X", xtensa_helper::s_b_ops[BIT(inst, 12, 4)], BIT(inst, 8, 4), BIT(inst, 4, 4), pc + 4 + s8(u8(inst >> 16)));
}
return 3 | STEP_COND | SUPPORTED;
case 0b1000: case 0b1001: // L32I.N (with Code Density Option)
- util::stream_format(stream, "%-8sa%d, a%d, %s", BIT(inst, 0) ? "s32i.n" : "l32i.n", BIT(inst, 4, 4), BIT(inst, 8, 4), m_helper.format_imm(BIT(inst, 12, 4) * 4));
+ util::stream_format(stream, "%-8sa%d, a%d, %s", BIT(inst, 0) ? "s32i.n" : "l32i.n", BIT(inst, 4, 4), BIT(inst, 8, 4), xtensa_helper::format_imm(BIT(inst, 12, 4) * 4));
return 2 | SUPPORTED;
case 0b1010: // ADD.N (with Code Density Option)
@@ -872,7 +872,7 @@ offs_t xtensa_disassembler::disassemble(std::ostream &stream, offs_t pc, const x
if (!BIT(inst, 7))
{
// 7-bit immediate field uses asymmetric sign extension (range is -32..95)
- util::stream_format(stream, "%-8sa%d, %s", "movi.n", BIT(inst, 8, 4), m_helper.format_imm(int((inst & 0x0070) + BIT(inst, 12, 4) - (BIT(inst, 5, 2) == 0b11 ? 128 : 0))));
+ util::stream_format(stream, "%-8sa%d, %s", "movi.n", BIT(inst, 8, 4), xtensa_helper::format_imm(int((inst & 0x0070) + BIT(inst, 12, 4) - (BIT(inst, 5, 2) == 0b11 ? 128 : 0))));
return 2 | SUPPORTED;
}
else
diff --git a/src/devices/cpu/xtensa/xtensad.h b/src/devices/cpu/xtensa/xtensad.h
index e2551208e97..a34031ceec7 100644
--- a/src/devices/cpu/xtensa/xtensad.h
+++ b/src/devices/cpu/xtensa/xtensad.h
@@ -6,7 +6,6 @@
#pragma once
-#include "xtensa_helper.h"
class xtensa_disassembler : public util::disasm_interface
{
@@ -18,9 +17,6 @@ protected:
// disassembler overrides
virtual u32 opcode_alignment() const override;
virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params) override;
-
-private:
- xtensa_helper m_helper;
};
#endif // MAME_CPU_XTENSA_XTENSAD_H