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-rw-r--r--scripts/src/cpu.lua6
-rw-r--r--src/devices/cpu/h8/h83217.cpp261
-rw-r--r--src/devices/cpu/h8/h83217.h118
-rw-r--r--src/devices/cpu/h8/h8325.cpp8
-rw-r--r--src/devices/cpu/h8/h8325.h3
-rw-r--r--src/devices/cpu/h8/h83337.cpp7
-rw-r--r--src/devices/cpu/h8/h83337.h1
-rw-r--r--src/devices/cpu/h8/h8_port.cpp8
-rw-r--r--src/devices/cpu/h8/h8_watchdog.cpp6
-rw-r--r--src/mame/saitek/gk2000.cpp1
-rw-r--r--src/mame/saitek/prisma.cpp1
11 files changed, 402 insertions, 18 deletions
diff --git a/scripts/src/cpu.lua b/scripts/src/cpu.lua
index 881e4ca7338..23f66cd7d5c 100644
--- a/scripts/src/cpu.lua
+++ b/scripts/src/cpu.lua
@@ -701,8 +701,6 @@ if CPUS["H8"] then
MAME_DIR .. "src/devices/cpu/h8/h8s2600.h",
MAME_DIR .. "src/devices/cpu/h8/h8325.cpp",
MAME_DIR .. "src/devices/cpu/h8/h8325.h",
- MAME_DIR .. "src/devices/cpu/h8/h83337.cpp",
- MAME_DIR .. "src/devices/cpu/h8/h83337.h",
MAME_DIR .. "src/devices/cpu/h8/h83002.cpp",
MAME_DIR .. "src/devices/cpu/h8/h83002.h",
MAME_DIR .. "src/devices/cpu/h8/h83003.cpp",
@@ -717,6 +715,10 @@ if CPUS["H8"] then
MAME_DIR .. "src/devices/cpu/h8/h83042.h",
MAME_DIR .. "src/devices/cpu/h8/h83048.cpp",
MAME_DIR .. "src/devices/cpu/h8/h83048.h",
+ MAME_DIR .. "src/devices/cpu/h8/h83217.cpp",
+ MAME_DIR .. "src/devices/cpu/h8/h83217.h",
+ MAME_DIR .. "src/devices/cpu/h8/h83337.cpp",
+ MAME_DIR .. "src/devices/cpu/h8/h83337.h",
MAME_DIR .. "src/devices/cpu/h8/h8s2245.cpp",
MAME_DIR .. "src/devices/cpu/h8/h8s2245.h",
MAME_DIR .. "src/devices/cpu/h8/h8s2320.cpp",
diff --git a/src/devices/cpu/h8/h83217.cpp b/src/devices/cpu/h8/h83217.cpp
new file mode 100644
index 00000000000..45d66228eec
--- /dev/null
+++ b/src/devices/cpu/h8/h83217.cpp
@@ -0,0 +1,261 @@
+// license:BSD-3-Clause
+// copyright-holders:Olivier Galibert, hap
+/***************************************************************************
+
+ h83217.cpp
+
+ H8/3217 family emulation
+
+ TODO:
+ - H8/3212 and H8/3202 have less internal modules
+ - PWM timer module
+ - Host Interface module
+ - optional I2C bus module
+ - keyboard matrix interrupt
+ - TCONR @ 0xff9f (timer connection)
+ - SEDGR @ 0xffa8 (edge sense)
+ - WSCR @ 0xffc2 (waitstate control)
+ - finish STCR emulation
+ - finish SYSCR emulation
+
+***************************************************************************/
+
+#include "emu.h"
+#include "h83217.h"
+
+DEFINE_DEVICE_TYPE(H83217, h83217_device, "h83217", "Hitachi H8/3217")
+DEFINE_DEVICE_TYPE(H83216, h83216_device, "h83216", "Hitachi H8/3216")
+DEFINE_DEVICE_TYPE(H83214, h83214_device, "h83214", "Hitachi H8/3214")
+DEFINE_DEVICE_TYPE(H83212, h83212_device, "h83212", "Hitachi H8/3212")
+DEFINE_DEVICE_TYPE(H83202, h83202_device, "h83202", "Hitachi H8/3202")
+
+
+h83217_device::h83217_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u32 start) :
+ h8_device(mconfig, type, tag, owner, clock, address_map_constructor(FUNC(h83217_device::map), this)),
+ m_intc(*this, "intc"),
+ m_port(*this, "port%u", 1),
+ m_timer8(*this, "timer8_%u", 0),
+ m_timer16(*this, "timer16"),
+ m_timer16_0(*this, "timer16:0"),
+ m_watchdog(*this, "watchdog"),
+ m_ram_view(*this, "ram_view"),
+ m_ram_start(start),
+ m_md(3)
+{
+}
+
+h83217_device::h83217_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
+ h83217_device(mconfig, H83217, tag, owner, clock, 0xf780)
+{
+}
+
+h83216_device::h83216_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
+ h83217_device(mconfig, H83216, tag, owner, clock, 0xf780)
+{
+}
+
+h83214_device::h83214_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
+ h83217_device(mconfig, H83214, tag, owner, clock, 0xfb80)
+{
+}
+
+h83212_device::h83212_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
+ h83217_device(mconfig, H83212, tag, owner, clock, 0xfd80)
+{
+}
+
+h83202_device::h83202_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
+ h83217_device(mconfig, H83202, tag, owner, clock, 0xfd80)
+{
+}
+
+void h83217_device::map(address_map &map)
+{
+ map(m_ram_start, 0xff7f).view(m_ram_view);
+ m_ram_view[0](m_ram_start, 0xff7f).ram().share(m_internal_ram);
+
+ map(0xff90, 0xff90).rw(m_timer16_0, FUNC(h8325_timer16_channel_device::tcr_r), FUNC(h8325_timer16_channel_device::tcr_w));
+ map(0xff91, 0xff91).rw(m_timer16_0, FUNC(h8325_timer16_channel_device::tsr_r), FUNC(h8325_timer16_channel_device::tsr_w));
+ map(0xff92, 0xff93).rw(m_timer16_0, FUNC(h8325_timer16_channel_device::tcnt_r), FUNC(h8325_timer16_channel_device::tcnt_w));
+ map(0xff94, 0xff95).rw(m_timer16_0, FUNC(h8325_timer16_channel_device::ocra_r), FUNC(h8325_timer16_channel_device::ocra_w));
+ map(0xff96, 0xff97).rw(m_timer16_0, FUNC(h8325_timer16_channel_device::ocrb_r), FUNC(h8325_timer16_channel_device::ocrb_w));
+ map(0xff98, 0xff99).r(m_timer16_0, FUNC(h8325_timer16_channel_device::icr_r));
+
+ map(0xff9a, 0xff9a).rw(m_timer8[2], FUNC(h8_timer8_channel_device::tcr_r), FUNC(h8_timer8_channel_device::tcr_w));
+ map(0xff9b, 0xff9b).rw(m_timer8[2], FUNC(h8_timer8_channel_device::tcsr_r), FUNC(h8_timer8_channel_device::tcsr_w));
+ map(0xff9c, 0xff9d).rw(m_timer8[2], FUNC(h8_timer8_channel_device::tcor_r), FUNC(h8_timer8_channel_device::tcor_w));
+ map(0xff9e, 0xff9e).rw(m_timer8[2], FUNC(h8_timer8_channel_device::tcnt_r), FUNC(h8_timer8_channel_device::tcnt_w));
+
+ map(0xffaa, 0xffab).rw(m_watchdog, FUNC(h8_watchdog_device::wd_r), FUNC(h8_watchdog_device::wd_w));
+
+ map(0xffb0, 0xffb0).w(m_port[0], FUNC(h8_port_device::ddr_w));
+ map(0xffb1, 0xffb1).w(m_port[1], FUNC(h8_port_device::ddr_w));
+ map(0xffb2, 0xffb2).rw(m_port[0], FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w));
+ map(0xffb3, 0xffb3).rw(m_port[1], FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w));
+ map(0xffb4, 0xffb4).w(m_port[2], FUNC(h8_port_device::ddr_w));
+ map(0xffb5, 0xffb5).w(m_port[3], FUNC(h8_port_device::ddr_w));
+ map(0xffb6, 0xffb6).rw(m_port[2], FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w));
+ map(0xffb7, 0xffb7).rw(m_port[3], FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w));
+ map(0xffb8, 0xffb8).w(m_port[4], FUNC(h8_port_device::ddr_w));
+ map(0xffb9, 0xffb9).w(m_port[5], FUNC(h8_port_device::ddr_w));
+ map(0xffba, 0xffba).rw(m_port[4], FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w));
+ map(0xffbb, 0xffbb).rw(m_port[5], FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w));
+ map(0xffbc, 0xffbc).w(m_port[6], FUNC(h8_port_device::ddr_w));
+ map(0xffbe, 0xffbe).rw(m_port[6], FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w));
+
+ map(0xffc3, 0xffc3).rw(FUNC(h83217_device::stcr_r), FUNC(h83217_device::stcr_w));
+ map(0xffc4, 0xffc4).rw(FUNC(h83217_device::syscr_r), FUNC(h83217_device::syscr_w));
+ map(0xffc5, 0xffc5).r(FUNC(h83217_device::mdcr_r));
+ map(0xffc6, 0xffc6).lr8(NAME([this]() { return m_intc->iscr_r() | ~0x47; }));
+ map(0xffc6, 0xffc6).lw8(NAME([this](u8 data) { m_intc->iscr_w(data & 0x47); }));
+ map(0xffc7, 0xffc7).lr8(NAME([this]() { return m_intc->ier_r() | ~0x47; }));
+ map(0xffc7, 0xffc7).lw8(NAME([this](u8 data) { m_intc->ier_w(data & 0x47); }));
+
+ map(0xffc8, 0xffc8).rw(m_timer8[0], FUNC(h8_timer8_channel_device::tcr_r), FUNC(h8_timer8_channel_device::tcr_w));
+ map(0xffc9, 0xffc9).rw(m_timer8[0], FUNC(h8_timer8_channel_device::tcsr_r), FUNC(h8_timer8_channel_device::tcsr_w));
+ map(0xffca, 0xffcb).rw(m_timer8[0], FUNC(h8_timer8_channel_device::tcor_r), FUNC(h8_timer8_channel_device::tcor_w));
+ map(0xffcc, 0xffcc).rw(m_timer8[0], FUNC(h8_timer8_channel_device::tcnt_r), FUNC(h8_timer8_channel_device::tcnt_w));
+ map(0xffd0, 0xffd0).rw(m_timer8[1], FUNC(h8_timer8_channel_device::tcr_r), FUNC(h8_timer8_channel_device::tcr_w));
+ map(0xffd1, 0xffd1).rw(m_timer8[1], FUNC(h8_timer8_channel_device::tcsr_r), FUNC(h8_timer8_channel_device::tcsr_w));
+ map(0xffd2, 0xffd3).rw(m_timer8[1], FUNC(h8_timer8_channel_device::tcor_r), FUNC(h8_timer8_channel_device::tcor_w));
+ map(0xffd4, 0xffd4).rw(m_timer8[1], FUNC(h8_timer8_channel_device::tcnt_r), FUNC(h8_timer8_channel_device::tcnt_w));
+
+ map(0xffd8, 0xffd8).rw(m_sci[0], FUNC(h8_sci_device::smr_r), FUNC(h8_sci_device::smr_w));
+ map(0xffd9, 0xffd9).rw(m_sci[0], FUNC(h8_sci_device::brr_r), FUNC(h8_sci_device::brr_w));
+ map(0xffda, 0xffda).rw(m_sci[0], FUNC(h8_sci_device::scr_r), FUNC(h8_sci_device::scr_w));
+ map(0xffdb, 0xffdb).rw(m_sci[0], FUNC(h8_sci_device::tdr_r), FUNC(h8_sci_device::tdr_w));
+ map(0xffdc, 0xffdc).rw(m_sci[0], FUNC(h8_sci_device::ssr_r), FUNC(h8_sci_device::ssr_w));
+ map(0xffdd, 0xffdd).r(m_sci[0], FUNC(h8_sci_device::rdr_r));
+ map(0xffe0, 0xffe0).rw(m_sci[1], FUNC(h8_sci_device::smr_r), FUNC(h8_sci_device::smr_w));
+ map(0xffe1, 0xffe1).rw(m_sci[1], FUNC(h8_sci_device::brr_r), FUNC(h8_sci_device::brr_w));
+ map(0xffe2, 0xffe2).rw(m_sci[1], FUNC(h8_sci_device::scr_r), FUNC(h8_sci_device::scr_w));
+ map(0xffe3, 0xffe3).rw(m_sci[1], FUNC(h8_sci_device::tdr_r), FUNC(h8_sci_device::tdr_w));
+ map(0xffe4, 0xffe4).rw(m_sci[1], FUNC(h8_sci_device::ssr_r), FUNC(h8_sci_device::ssr_w));
+ map(0xffe5, 0xffe5).r(m_sci[1], FUNC(h8_sci_device::rdr_r));
+}
+
+void h83217_device::device_add_mconfig(machine_config &config)
+{
+ H8_INTC(config, m_intc, *this);
+ H8_PORT(config, m_port[0], *this, h8_device::PORT_1, 0x00, 0x00);
+ H8_PORT(config, m_port[1], *this, h8_device::PORT_2, 0x00, 0x00);
+ H8_PORT(config, m_port[2], *this, h8_device::PORT_3, 0x00, 0x00);
+ H8_PORT(config, m_port[3], *this, h8_device::PORT_4, 0x00, 0x00);
+ H8_PORT(config, m_port[4], *this, h8_device::PORT_5, 0x00, 0xc0);
+ H8_PORT(config, m_port[5], *this, h8_device::PORT_6, 0x00, 0x80);
+ H8_PORT(config, m_port[6], *this, h8_device::PORT_7, 0x00, 0x00);
+ H8_TIMER8_CHANNEL(config, m_timer8[0], *this, m_intc, 23, 24, 25, 8, 2, 64, 32, 1024, 256);
+ H8_TIMER8_CHANNEL(config, m_timer8[1], *this, m_intc, 26, 27, 28, 8, 2, 64, 128, 1024, 2048);
+ H8_TIMER8_CHANNEL(config, m_timer8[2], *this, m_intc, 47, 48, 49, 1, 1, 2, 2, 512, 512);
+ H8_TIMER16(config, m_timer16, *this, 1, 0xff);
+ H8325_TIMER16_CHANNEL(config, m_timer16_0, *this, m_intc, 19);
+ H8_SCI(config, m_sci[0], 0, *this, m_intc, 29, 30, 31, 32);
+ H8_SCI(config, m_sci[1], 1, *this, m_intc, 33, 34, 35, 36);
+ H8_WATCHDOG(config, m_watchdog, *this, m_intc, 44, h8_watchdog_device::B);
+}
+
+void h83217_device::execute_set_input(int inputnum, int state)
+{
+ m_intc->set_input(inputnum, state);
+}
+
+void h83217_device::irq_setup()
+{
+ m_CCR |= F_I;
+}
+
+void h83217_device::update_irq_filter()
+{
+ if(m_CCR & F_I)
+ m_intc->set_filter(2, -1);
+ else
+ m_intc->set_filter(0, -1);
+}
+
+void h83217_device::interrupt_taken()
+{
+ standard_irq_callback(m_intc->interrupt_taken(m_taken_irq_vector), m_NPC);
+}
+
+void h83217_device::internal_update(u64 current_time)
+{
+ u64 event_time = 0;
+
+ add_event(event_time, m_sci[0]->internal_update(current_time));
+ add_event(event_time, m_sci[1]->internal_update(current_time));
+ add_event(event_time, m_timer8[0]->internal_update(current_time));
+ add_event(event_time, m_timer8[1]->internal_update(current_time));
+ add_event(event_time, m_timer8[2]->internal_update(current_time));
+ add_event(event_time, m_timer16_0->internal_update(current_time));
+ add_event(event_time, m_watchdog->internal_update(current_time));
+
+ recompute_bcount(event_time);
+}
+
+void h83217_device::device_start()
+{
+ h8_device::device_start();
+
+ m_stcr = 0;
+ m_syscr = 0;
+
+ save_item(NAME(m_md));
+ save_item(NAME(m_stcr));
+ save_item(NAME(m_syscr));
+}
+
+void h83217_device::device_reset()
+{
+ h8_device::device_reset();
+
+ m_stcr = 0x00;
+ m_syscr = 0x09;
+ m_ram_view.select(0);
+}
+
+u8 h83217_device::stcr_r()
+{
+ return m_stcr;
+}
+
+void h83217_device::stcr_w(u8 data)
+{
+ logerror("stcr = %02x\n", data);
+
+ // ICKS0/1
+ m_timer8[0]->set_extra_clock_bit(BIT(data, 0));
+ m_timer8[1]->set_extra_clock_bit(BIT(data, 1));
+
+ m_stcr = data;
+}
+
+u8 h83217_device::syscr_r()
+{
+ return m_syscr;
+}
+
+void h83217_device::syscr_w(u8 data)
+{
+ logerror("syscr = %02x\n", data);
+
+ // RAME
+ if (data & 1)
+ m_ram_view.select(0);
+ else
+ m_ram_view.disable();
+
+ // NMIEG
+ m_intc->set_nmi_edge(BIT(data, 2));
+
+ // SSBY
+ m_standby_pending = bool(data & 0x80);
+
+ m_syscr = (m_syscr & 0x08) | (data & 0xf7);
+}
+
+u8 h83217_device::mdcr_r()
+{
+ if(!machine().side_effects_disabled())
+ logerror("mdcr_r\n");
+ return (m_md & 0x03) | 0xe4;
+}
diff --git a/src/devices/cpu/h8/h83217.h b/src/devices/cpu/h8/h83217.h
new file mode 100644
index 00000000000..9a6195aaf50
--- /dev/null
+++ b/src/devices/cpu/h8/h83217.h
@@ -0,0 +1,118 @@
+// license:BSD-3-Clause
+// copyright-holders:Olivier Galibert, hap
+/***************************************************************************
+
+ h83217.h
+
+ H8/3217 family emulation
+
+ H8-300-based mcus.
+
+ Variant ROM RAM
+ H8/3217 60K 2K
+ H8/3216 48K 2K
+ H8/3214 32K 1K
+ H8/3212 16K 512B
+ H8/3202 16K 512B
+
+***************************************************************************/
+
+#ifndef MAME_CPU_H8_H83217_H
+#define MAME_CPU_H8_H83217_H
+
+#pragma once
+
+#include "h8.h"
+
+#include "h8_intc.h"
+#include "h8_port.h"
+#include "h8_timer8.h"
+#include "h8_timer16.h"
+#include "h8_sci.h"
+#include "h8_watchdog.h"
+
+class h83217_device : public h8_device {
+public:
+ h83217_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
+
+ // I/O ports
+ auto read_port1() { return m_read_port [PORT_1].bind(); }
+ auto write_port1() { return m_write_port[PORT_1].bind(); }
+ auto read_port2() { return m_read_port [PORT_2].bind(); }
+ auto write_port2() { return m_write_port[PORT_2].bind(); }
+ auto read_port3() { return m_read_port [PORT_3].bind(); }
+ auto write_port3() { return m_write_port[PORT_3].bind(); }
+ auto read_port4() { return m_read_port [PORT_4].bind(); }
+ auto write_port4() { return m_write_port[PORT_4].bind(); }
+ auto read_port5() { return m_read_port [PORT_5].bind(); }
+ auto write_port5() { return m_write_port[PORT_5].bind(); }
+ auto read_port6() { return m_read_port [PORT_6].bind(); }
+ auto write_port6() { return m_write_port[PORT_6].bind(); }
+ auto read_port7() { return m_read_port [PORT_7].bind(); }
+ auto write_port7() { return m_write_port[PORT_7].bind(); }
+
+ // MD pins, default mode 3 (single chip)
+ void set_mode(u8 mode) { m_md = mode & 3; }
+
+ u8 stcr_r();
+ void stcr_w(u8 data);
+ u8 syscr_r();
+ void syscr_w(u8 data);
+ u8 mdcr_r();
+
+protected:
+ h83217_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u32 start);
+
+ required_device<h8_intc_device> m_intc;
+ required_device_array<h8_port_device, 7> m_port;
+ required_device_array<h8_timer8_channel_device, 3> m_timer8;
+ required_device<h8_timer16_device> m_timer16;
+ required_device<h8325_timer16_channel_device> m_timer16_0;
+ required_device<h8_watchdog_device> m_watchdog;
+
+ memory_view m_ram_view;
+
+ u32 m_ram_start;
+ u8 m_md;
+ u8 m_stcr;
+ u8 m_syscr;
+
+ virtual void update_irq_filter() override;
+ virtual void interrupt_taken() override;
+ virtual void irq_setup() override;
+ virtual void internal_update(u64 current_time) override;
+ virtual void device_add_mconfig(machine_config &config) override;
+ void map(address_map &map);
+
+ virtual void device_start() override;
+ virtual void device_reset() override;
+ virtual void execute_set_input(int inputnum, int state) override;
+};
+
+class h83216_device : public h83217_device {
+public:
+ h83216_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
+};
+
+class h83214_device : public h83217_device {
+public:
+ h83214_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
+};
+
+class h83212_device : public h83217_device {
+public:
+ h83212_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
+};
+
+class h83202_device : public h83217_device {
+public:
+ h83202_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
+};
+
+DECLARE_DEVICE_TYPE(H83217, h83217_device)
+DECLARE_DEVICE_TYPE(H83216, h83216_device)
+DECLARE_DEVICE_TYPE(H83214, h83214_device)
+DECLARE_DEVICE_TYPE(H83212, h83212_device)
+DECLARE_DEVICE_TYPE(H83202, h83202_device)
+
+#endif // MAME_CPU_H8_H83217_H
diff --git a/src/devices/cpu/h8/h8325.cpp b/src/devices/cpu/h8/h8325.cpp
index 194f9557a9a..cbed3c0321f 100644
--- a/src/devices/cpu/h8/h8325.cpp
+++ b/src/devices/cpu/h8/h8325.cpp
@@ -9,8 +9,8 @@
TODO:
- serial controllers are slightly different, has 3 interrupt sources
instead of 4
- - HCSR register @ 0xfffe (port 3 handshake)
- - FNCR register @ 0xffff (16-bit timer noise canceler)
+ - HCSR @ 0xfffe (port 3 handshake)
+ - FNCR @ 0xffff (16-bit timer noise canceler)
***************************************************************************/
@@ -197,7 +197,7 @@ void h8325_device::device_reset()
m_ram_view.select(0);
// MD pins are latched at reset
- m_mds = m_md & 3;
+ m_mds = m_md;
}
u8 h8325_device::syscr_r()
@@ -228,5 +228,5 @@ u8 h8325_device::mdcr_r()
{
if(!machine().side_effects_disabled())
logerror("mdcr_r\n");
- return m_mds | 0xe4;
+ return (m_mds & 0x03) | 0xe4;
}
diff --git a/src/devices/cpu/h8/h8325.h b/src/devices/cpu/h8/h8325.h
index c6ba5b2672b..c046208b014 100644
--- a/src/devices/cpu/h8/h8325.h
+++ b/src/devices/cpu/h8/h8325.h
@@ -24,6 +24,7 @@
#pragma once
#include "h8.h"
+
#include "h8_intc.h"
#include "h8_port.h"
#include "h8_timer8.h"
@@ -51,7 +52,7 @@ public:
auto write_port7() { return m_write_port[PORT_7].bind(); }
// MD pins, default mode 3 (single chip)
- void set_mode(u8 mode) { m_md = mode; }
+ void set_mode(u8 mode) { m_md = mode & 3; }
u8 syscr_r();
void syscr_w(u8 data);
diff --git a/src/devices/cpu/h8/h83337.cpp b/src/devices/cpu/h8/h83337.cpp
index 5fd3101dd13..9ff1c5ce11d 100644
--- a/src/devices/cpu/h8/h83337.cpp
+++ b/src/devices/cpu/h8/h83337.cpp
@@ -7,7 +7,8 @@
H8-3337 family emulation
TODO:
- - 16-bit timer module is different
+ - 16-bit timer module is different from how it's implemented in h8_timer16.cpp
+ - finish WSCR emulation, CKDBL flag would need support in peripherals
***************************************************************************/
@@ -230,8 +231,8 @@ u8 h83337_device::stcr_r()
void h83337_device::stcr_w(u8 data)
{
logerror("stcr = %02x\n", data);
- m_timer8_0->set_extra_clock_bit(data & 0x01);
- m_timer8_1->set_extra_clock_bit(data & 0x02);
+ m_timer8_0->set_extra_clock_bit(BIT(data, 0));
+ m_timer8_1->set_extra_clock_bit(BIT(data, 1));
}
u8 h83337_device::mdcr_r()
diff --git a/src/devices/cpu/h8/h83337.h b/src/devices/cpu/h8/h83337.h
index ee4b349ae7b..b3b17ab97b3 100644
--- a/src/devices/cpu/h8/h83337.h
+++ b/src/devices/cpu/h8/h83337.h
@@ -23,6 +23,7 @@
#pragma once
#include "h8.h"
+
#include "h8_intc.h"
#include "h8_adc.h"
#include "h8_port.h"
diff --git a/src/devices/cpu/h8/h8_port.cpp b/src/devices/cpu/h8/h8_port.cpp
index 3ba9c56a494..521cc29dedd 100644
--- a/src/devices/cpu/h8/h8_port.cpp
+++ b/src/devices/cpu/h8/h8_port.cpp
@@ -26,7 +26,7 @@ h8_port_device::h8_port_device(const machine_config &mconfig, const char *tag, d
void h8_port_device::ddr_w(u8 data)
{
- // logerror("ddr_w %02x\n", data);
+ //logerror("ddr_w %02x\n", data);
m_ddr = data;
update_output();
}
@@ -38,14 +38,14 @@ u8 h8_port_device::ddr_r()
void h8_port_device::dr_w(u8 data)
{
- // logerror("dr_w %02x\n", data);
+ //logerror("dr_w %02x\n", data);
m_dr = data;
update_output();
}
u8 h8_port_device::dr_r()
{
- // logerror("dr_r %02x\n", (dr | mask) & 0xff);
+ //logerror("dr_r %02x\n", (dr | mask) & 0xff);
return m_dr | m_mask;
}
@@ -55,7 +55,7 @@ u8 h8_port_device::port_r()
if((m_ddr & ~m_mask) != u8(~m_mask))
res |= m_cpu->do_read_port(m_address) & ~m_ddr;
- // logerror("port_r %02x (%02x %02x)\n", res, ddr & ~mask, u8(~mask));
+ //logerror("port_r %02x (%02x %02x)\n", res, ddr & ~mask, u8(~mask));
return res;
}
diff --git a/src/devices/cpu/h8/h8_watchdog.cpp b/src/devices/cpu/h8/h8_watchdog.cpp
index cecc47bb579..76abcc68369 100644
--- a/src/devices/cpu/h8/h8_watchdog.cpp
+++ b/src/devices/cpu/h8/h8_watchdog.cpp
@@ -6,8 +6,8 @@
DEFINE_DEVICE_TYPE(H8_WATCHDOG, h8_watchdog_device, "h8_watchdog", "H8 watchdog")
-const int h8_watchdog_device::div_bh[8] = { 1, 6, 7, 9, 11, 13, 15, 17 };
-const int h8_watchdog_device::div_s [8] = { 1, 5, 6, 7, 8, 9, 11, 12 };
+const int h8_watchdog_device::div_bh[8] = { 1, 5, 6, 7, 8, 9, 11, 12 };
+const int h8_watchdog_device::div_s [8] = { 1, 6, 7, 9, 11, 13, 15, 17 };
h8_watchdog_device::h8_watchdog_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
device_t(mconfig, H8_WATCHDOG, tag, owner, clock),
@@ -24,7 +24,6 @@ u64 h8_watchdog_device::internal_update(u64 current_time)
int shift = (m_type == S ? div_s : div_bh)[m_tcsr & TCSR_CKS];
u64 spos = m_tcnt_cycle_base >> shift;
return (spos + 0x100 - m_tcnt) << shift;
-
} else
return 0;
}
@@ -59,7 +58,6 @@ void h8_watchdog_device::tcnt_update(u64 cur_time)
}
} else
m_tcnt = 0;
-
}
u16 h8_watchdog_device::wd_r()
diff --git a/src/mame/saitek/gk2000.cpp b/src/mame/saitek/gk2000.cpp
index 621f3e868e6..92916db5120 100644
--- a/src/mame/saitek/gk2000.cpp
+++ b/src/mame/saitek/gk2000.cpp
@@ -264,6 +264,7 @@ void gk2000_state::gk2000(machine_config &config)
m_maincpu->write_port2().set(FUNC(gk2000_state::p2_w));
m_maincpu->write_port3().set(FUNC(gk2000_state::lcd_segs_w<1>));
m_maincpu->read_port4().set(FUNC(gk2000_state::p4_r));
+ m_maincpu->read_port5().set_constant(0xff);
m_maincpu->write_port5().set(FUNC(gk2000_state::p5_w));
m_maincpu->read_port6().set_ioport("IN.3").invert();
m_maincpu->write_port6().set(FUNC(gk2000_state::lcd_com_w));
diff --git a/src/mame/saitek/prisma.cpp b/src/mame/saitek/prisma.cpp
index 0a4867903c2..ede54634a5d 100644
--- a/src/mame/saitek/prisma.cpp
+++ b/src/mame/saitek/prisma.cpp
@@ -322,6 +322,7 @@ void prisma_state::prisma(machine_config &config)
m_maincpu->write_port1().set(FUNC(prisma_state::p1_w));
m_maincpu->write_port2().set(FUNC(prisma_state::p2_w));
m_maincpu->write_port3().set(FUNC(prisma_state::p3_w));
+ m_maincpu->read_port4().set_constant(0xff);
m_maincpu->write_port4().set(FUNC(prisma_state::p4_w));
m_maincpu->read_port5().set(FUNC(prisma_state::p5_r));
m_maincpu->write_port5().set(FUNC(prisma_state::p5_w));