diff options
-rw-r--r-- | src/emu/cpu/mips/mips3.c | 1924 | ||||
-rw-r--r-- | src/emu/cpu/mips/mips3.h | 565 | ||||
-rw-r--r-- | src/emu/cpu/mips/mips3com.c | 732 | ||||
-rw-r--r-- | src/emu/cpu/mips/mips3com.h | 172 | ||||
-rw-r--r-- | src/emu/cpu/mips/mips3drc.c | 1832 | ||||
-rw-r--r-- | src/emu/cpu/mips/mips3fe.c | 26 | ||||
-rw-r--r-- | src/emu/cpu/mips/mips3fe.h | 33 | ||||
-rw-r--r-- | src/mame/drivers/aleck64.c | 11 | ||||
-rw-r--r-- | src/mame/drivers/atlantis.c | 13 | ||||
-rw-r--r-- | src/mame/drivers/hng64.c | 18 | ||||
-rw-r--r-- | src/mame/drivers/iteagle.c | 13 | ||||
-rw-r--r-- | src/mame/drivers/kinst.c | 19 | ||||
-rw-r--r-- | src/mame/drivers/namcops2.c | 9 | ||||
-rw-r--r-- | src/mame/drivers/namcos23.c | 21 | ||||
-rw-r--r-- | src/mame/drivers/pyson.c | 9 | ||||
-rw-r--r-- | src/mame/drivers/seattle.c | 89 | ||||
-rw-r--r-- | src/mame/drivers/vegas.c | 53 | ||||
-rw-r--r-- | src/mame/drivers/vp101.c | 12 | ||||
-rw-r--r-- | src/mame/includes/hng64.h | 3 | ||||
-rw-r--r-- | src/mame/machine/n64.c | 4 | ||||
-rw-r--r-- | src/mess/drivers/ip22.c | 4 |
21 files changed, 2333 insertions, 3229 deletions
diff --git a/src/emu/cpu/mips/mips3.c b/src/emu/cpu/mips/mips3.c index f8e597b16ca..ccd1427f957 100644 --- a/src/emu/cpu/mips/mips3.c +++ b/src/emu/cpu/mips/mips3.c @@ -23,132 +23,77 @@ HELPER MACROS ***************************************************************************/ -#define RSVAL32 ((UINT32)mips3.core.r[RSREG]) -#define RTVAL32 ((UINT32)mips3.core.r[RTREG]) -#define RDVAL32 ((UINT32)mips3.core.r[RDREG]) - -#define RSVAL64 (mips3.core.r[RSREG]) -#define RTVAL64 (mips3.core.r[RTREG]) -#define RDVAL64 (mips3.core.r[RDREG]) - -#define FRVALS_FR0 (((float *)&mips3.core.cpr[1][0])[FRREG]) -#define FTVALS_FR0 (((float *)&mips3.core.cpr[1][0])[FTREG]) -#define FSVALS_FR0 (((float *)&mips3.core.cpr[1][0])[FSREG]) -#define FDVALS_FR0 (((float *)&mips3.core.cpr[1][0])[FDREG]) -#define FSVALW_FR0 (((UINT32 *)&mips3.core.cpr[1][0])[FSREG]) -#define FDVALW_FR0 (((UINT32 *)&mips3.core.cpr[1][0])[FDREG]) - -#define FRVALD_FR0 (*(double *)&mips3.core.cpr[1][FRREG/2]) -#define FTVALD_FR0 (*(double *)&mips3.core.cpr[1][FTREG/2]) -#define FSVALD_FR0 (*(double *)&mips3.core.cpr[1][FSREG/2]) -#define FDVALD_FR0 (*(double *)&mips3.core.cpr[1][FDREG/2]) -#define FSVALL_FR0 (((UINT64 *)&mips3.core.cpr[1][0])[FSREG/2]) -#define FDVALL_FR0 (((UINT64 *)&mips3.core.cpr[1][0])[FDREG/2]) - -#define FRVALS_FR1 (((float *)&mips3.core.cpr[1][FRREG])[BYTE_XOR_LE(0)]) -#define FTVALS_FR1 (((float *)&mips3.core.cpr[1][FTREG])[BYTE_XOR_LE(0)]) -#define FSVALS_FR1 (((float *)&mips3.core.cpr[1][FSREG])[BYTE_XOR_LE(0)]) -#define FDVALS_FR1 (((float *)&mips3.core.cpr[1][FDREG])[BYTE_XOR_LE(0)]) -#define FSVALW_FR1 (((UINT32 *)&mips3.core.cpr[1][FSREG])[BYTE_XOR_LE(0)]) -#define FDVALW_FR1 (((UINT32 *)&mips3.core.cpr[1][FDREG])[BYTE_XOR_LE(0)]) - -#define FRVALD_FR1 (*(double *)&mips3.core.cpr[1][FRREG]) -#define FTVALD_FR1 (*(double *)&mips3.core.cpr[1][FTREG]) -#define FSVALD_FR1 (*(double *)&mips3.core.cpr[1][FSREG]) -#define FDVALD_FR1 (*(double *)&mips3.core.cpr[1][FDREG]) -#define FSVALL_FR1 (*(UINT64 *)&mips3.core.cpr[1][FSREG]) -#define FDVALL_FR1 (*(UINT64 *)&mips3.core.cpr[1][FDREG]) - -#define ADDPC(x) mips3.nextpc = mips3.core.pc + ((x) << 2) -#define ADDPCL(x,l) { mips3.nextpc = mips3.core.pc + ((x) << 2); mips3.core.r[l] = (INT32)(mips3.core.pc + 4); } -#define ABSPC(x) mips3.nextpc = (mips3.core.pc & 0xf0000000) | ((x) << 2) -#define ABSPCL(x,l) { mips3.nextpc = (mips3.core.pc & 0xf0000000) | ((x) << 2); mips3.core.r[l] = (INT32)(mips3.core.pc + 4); } -#define SETPC(x) mips3.nextpc = (x) -#define SETPCL(x,l) { mips3.nextpc = (x); mips3.core.r[l] = (INT32)(mips3.core.pc + 4); } - -#define HIVAL (UINT32)mips3.core.r[REG_HI] -#define LOVAL (UINT32)mips3.core.r[REG_LO] -#define HIVAL64 mips3.core.r[REG_HI] -#define LOVAL64 mips3.core.r[REG_LO] -#define SR mips3.core.cpr[0][COP0_Status] -#define CAUSE mips3.core.cpr[0][COP0_Cause] - -#define GET_FCC(n) (mips3.cf[1][n]) -#define SET_FCC(n,v) (mips3.cf[1][n] = (v)) +#define RSVAL32 ((UINT32)m_core->r[RSREG]) +#define RTVAL32 ((UINT32)m_core->r[RTREG]) +#define RDVAL32 ((UINT32)m_core->r[RDREG]) + +#define RSVAL64 (m_core->r[RSREG]) +#define RTVAL64 (m_core->r[RTREG]) +#define RDVAL64 (m_core->r[RDREG]) + +#define FRVALS_FR0 (((float *)&m_core->cpr[1][0])[FRREG]) +#define FTVALS_FR0 (((float *)&m_core->cpr[1][0])[FTREG]) +#define FSVALS_FR0 (((float *)&m_core->cpr[1][0])[FSREG]) +#define FDVALS_FR0 (((float *)&m_core->cpr[1][0])[FDREG]) +#define FSVALW_FR0 (((UINT32 *)&m_core->cpr[1][0])[FSREG]) +#define FDVALW_FR0 (((UINT32 *)&m_core->cpr[1][0])[FDREG]) + +#define FRVALD_FR0 (*(double *)&m_core->cpr[1][FRREG/2]) +#define FTVALD_FR0 (*(double *)&m_core->cpr[1][FTREG/2]) +#define FSVALD_FR0 (*(double *)&m_core->cpr[1][FSREG/2]) +#define FDVALD_FR0 (*(double *)&m_core->cpr[1][FDREG/2]) +#define FSVALL_FR0 (((UINT64 *)&m_core->cpr[1][0])[FSREG/2]) +#define FDVALL_FR0 (((UINT64 *)&m_core->cpr[1][0])[FDREG/2]) + +#define FRVALS_FR1 (((float *)&m_core->cpr[1][FRREG])[BYTE_XOR_LE(0)]) +#define FTVALS_FR1 (((float *)&m_core->cpr[1][FTREG])[BYTE_XOR_LE(0)]) +#define FSVALS_FR1 (((float *)&m_core->cpr[1][FSREG])[BYTE_XOR_LE(0)]) +#define FDVALS_FR1 (((float *)&m_core->cpr[1][FDREG])[BYTE_XOR_LE(0)]) +#define FSVALW_FR1 (((UINT32 *)&m_core->cpr[1][FSREG])[BYTE_XOR_LE(0)]) +#define FDVALW_FR1 (((UINT32 *)&m_core->cpr[1][FDREG])[BYTE_XOR_LE(0)]) + +#define FRVALD_FR1 (*(double *)&m_core->cpr[1][FRREG]) +#define FTVALD_FR1 (*(double *)&m_core->cpr[1][FTREG]) +#define FSVALD_FR1 (*(double *)&m_core->cpr[1][FSREG]) +#define FDVALD_FR1 (*(double *)&m_core->cpr[1][FDREG]) +#define FSVALL_FR1 (*(UINT64 *)&m_core->cpr[1][FSREG]) +#define FDVALL_FR1 (*(UINT64 *)&m_core->cpr[1][FDREG]) + +#define ADDPC(x) m_nextpc = m_core->pc + ((x) << 2) +#define ADDPCL(x,l) { m_nextpc = m_core->pc + ((x) << 2); m_core->r[l] = (INT32)(m_core->pc + 4); } +#define ABSPC(x) m_nextpc = (m_core->pc & 0xf0000000) | ((x) << 2) +#define ABSPCL(x,l) { m_nextpc = (m_core->pc & 0xf0000000) | ((x) << 2); m_core->r[l] = (INT32)(m_core->pc + 4); } +#define SETPC(x) m_nextpc = (x) +#define SETPCL(x,l) { m_nextpc = (x); m_core->r[l] = (INT32)(m_core->pc + 4); } + +#define HIVAL (UINT32)m_core->r[REG_HI] +#define LOVAL (UINT32)m_core->r[REG_LO] +#define HIVAL64 m_core->r[REG_HI] +#define LOVAL64 m_core->r[REG_LO] +#define SR m_core->cpr[0][COP0_Status] +#define CAUSE m_core->cpr[0][COP0_Cause] + +#define GET_FCC(n) (m_cf[1][n]) +#define SET_FCC(n,v) (m_cf[1][n] = (v)) #define IS_FR0 (!(SR & SR_FR)) #define IS_FR1 (SR & SR_FR) +/* size of the execution code cache */ +#define CACHE_SIZE (32 * 1024 * 1024) -/*************************************************************************** - STRUCTURES & TYPEDEFS -***************************************************************************/ - -/* MIPS3 Registers */ -struct mips3_regs -{ - /* core state */ - mips3_state core; - - /* internal stuff */ - UINT32 ppc; - UINT32 nextpc; - UINT32 pcbase; - UINT8 cf[4][8]; - int op; - int interrupt_cycles; - UINT32 ll_value; - UINT64 lld_value; - UINT32 badcop_value; - const vtlb_entry *tlb_table; - - /* endian-dependent load/store */ - void (*lwl)(UINT32 op); - void (*lwr)(UINT32 op); - void (*swl)(UINT32 op); - void (*swr)(UINT32 op); - void (*ldl)(UINT32 op); - void (*ldr)(UINT32 op); - void (*sdl)(UINT32 op); - void (*sdr)(UINT32 op); -}; - - - -/*************************************************************************** - FUNCTION PROTOTYPES -***************************************************************************/ - -static void lwl_be(UINT32 op); -static void lwr_be(UINT32 op); -static void swl_be(UINT32 op); -static void swr_be(UINT32 op); - -static void lwl_le(UINT32 op); -static void lwr_le(UINT32 op); -static void swl_le(UINT32 op); -static void swr_le(UINT32 op); - -static void ldl_be(UINT32 op); -static void ldr_be(UINT32 op); -static void sdl_be(UINT32 op); -static void sdr_be(UINT32 op); - -static void ldl_le(UINT32 op); -static void ldr_le(UINT32 op); -static void sdl_le(UINT32 op); -static void sdr_le(UINT32 op); static const UINT8 fcc_shift[8] = { 23, 25, 26, 27, 28, 29, 30, 31 }; - - -/*************************************************************************** - PRIVATE GLOBAL VARIABLES -***************************************************************************/ - -static mips3_regs mips3; +/* lookup table for FP modes */ +static const UINT8 fpmode_source[4] = +{ + uml::ROUND_ROUND, + uml::ROUND_TRUNC, + uml::ROUND_CEIL, + uml::ROUND_FLOOR +}; @@ -156,14 +101,124 @@ static mips3_regs mips3; MEMORY ACCESSORS ***************************************************************************/ -#define ROPCODE(pc) mips3.core.direct->read_decrypted_dword(pc) - +#define ROPCODE(pc) direct->read_decrypted_dword(pc) + + +const device_type VR4300BE = &device_creator<vr4300be_device>; +const device_type VR4300LE = &device_creator<vr4300le_device>; +const device_type VR4310BE = &device_creator<vr4310be_device>; +const device_type VR4310LE = &device_creator<vr4310le_device>; +const device_type R4600BE = &device_creator<r4600be_device>; +const device_type R4600LE = &device_creator<r4600le_device>; +const device_type R4650BE = &device_creator<r4650be_device>; +const device_type R4650LE = &device_creator<r4650le_device>; +const device_type R4700BE = &device_creator<r4700be_device>; +const device_type R4700LE = &device_creator<r4700le_device>; +const device_type R5000BE = &device_creator<r5000be_device>; +const device_type R5000LE = &device_creator<r5000le_device>; +const device_type QED5271BE = &device_creator<qed5271be_device>; +const device_type QED5271LE = &device_creator<qed5271le_device>; +const device_type RM7000BE = &device_creator<rm7000be_device>; +const device_type RM7000LE = &device_creator<rm7000le_device>; + + +mips3_device::mips3_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, mips3_flavor flavor, endianness_t endianness) + : cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__) + , m_program_config("program", endianness, 32, 32, 0, 32, MIPS3_MIN_PAGE_SHIFT) + , m_flavor(flavor) + , m_core(NULL) + , m_ppc(0) + , m_nextpc(0) + , m_pcbase(0) + , m_op(0) + , m_interrupt_cycles(0) + , m_ll_value(0) + , m_lld_value(0) + , m_badcop_value(0) + , m_tlb_table(NULL) + , m_lwl(endianness == ENDIANNESS_BIG ? &mips3_device::lwl_be : &mips3_device::lwl_le) + , m_lwr(endianness == ENDIANNESS_BIG ? &mips3_device::lwr_be : &mips3_device::lwr_le) + , m_swl(endianness == ENDIANNESS_BIG ? &mips3_device::swl_be : &mips3_device::swl_le) + , m_swr(endianness == ENDIANNESS_BIG ? &mips3_device::swr_be : &mips3_device::swr_le) + , m_ldl(endianness == ENDIANNESS_BIG ? &mips3_device::ldl_be : &mips3_device::ldl_le) + , m_ldr(endianness == ENDIANNESS_BIG ? &mips3_device::ldr_be : &mips3_device::ldr_le) + , m_sdl(endianness == ENDIANNESS_BIG ? &mips3_device::sdl_be : &mips3_device::sdl_le) + , m_sdr(endianness == ENDIANNESS_BIG ? &mips3_device::sdr_be : &mips3_device::sdr_le) + , c_system_clock(0) + , m_pfnmask(0) + , m_tlbentries(0) + , m_bigendian(endianness == ENDIANNESS_BIG) + , c_icache_size(0) + , c_dcache_size(0) + , m_vtlb(NULL) + , m_debugger_temp(0) + , m_cache(CACHE_SIZE + sizeof(internal_mips3_state)) + , m_drcuml(NULL) + , m_drcfe(NULL) + , m_drcoptions(0) + , m_cache_dirty(0) + , m_entry(NULL) + , m_nocode(NULL) + , m_out_of_cycles(NULL) + , m_tlb_mismatch(NULL) + , m_fastram_select(0) + , m_hotspot_select(0) +{ + memset(m_fpmode, 0, sizeof(m_fpmode)); + + for (int i = 0; i < 3; i++) + { + m_read8[i] = NULL; + m_write8[i] = NULL; + m_read16[i] = NULL; + m_write16[i] = NULL; + m_read32[i] = NULL; + m_read32mask[i] = NULL; + m_write32[i] = NULL; + m_write32mask[i] = NULL; + m_read64[i] = NULL; + m_read64mask[i] = NULL; + m_write64[i] = NULL; + m_write64mask[i] = NULL; + } + + for (int i = 0; i < 18; i++) + { + m_exception[i] = NULL; + m_exception_norecover[i] = NULL; + } + memset(m_fastram, 0, sizeof(m_fastram)); + memset(m_hotspot, 0, sizeof(m_hotspot)); + + m_isdrc = mconfig.options().drc() ? true : false; +} + + +void mips3_device::device_stop() +{ + if (m_vtlb != NULL) + { + vtlb_free(m_vtlb); + m_vtlb = NULL; + } + + if (m_drcfe != NULL) + { + auto_free(machine(), m_drcfe); + m_drcfe = NULL; + } + if (m_drcuml != NULL) + { + auto_free(machine(), m_drcuml); + m_drcuml = NULL; + } +} /*************************************************************************** EXECEPTION HANDLING ***************************************************************************/ -INLINE void generate_exception(int exception, int backup) +void mips3_device::generate_exception(int exception, int backup) { UINT32 offset = 0x180; /* @@ -171,14 +226,14 @@ INLINE void generate_exception(int exception, int backup) if (exception != 0) { - fprintf(stderr, "Exception: PC=%08X, PPC=%08X\n", mips3.core.pc, mips3.ppc); - debugger_break(Machine); + fprintf(stderr, "Exception: PC=%08X, PPC=%08X\n", m_core->pc, m_ppc); + debugger_break(machine()); } */ /* back up if necessary */ if (backup) - mips3.core.pc = mips3.ppc; + m_core->pc = m_ppc; /* translate our fake fill exceptions into real exceptions */ if (exception == EXCEPTION_TLBLOAD_FILL || exception == EXCEPTION_TLBSTORE_FILL) @@ -188,7 +243,7 @@ INLINE void generate_exception(int exception, int backup) } /* set the exception PC */ - mips3.core.cpr[0][COP0_EPC] = mips3.core.pc; + m_core->cpr[0][COP0_EPC] = m_core->pc; /* put the cause in the low 8 bits and clear the branch delay flag */ CAUSE = (CAUSE & ~0x800000ff) | (exception << 2); @@ -196,14 +251,14 @@ INLINE void generate_exception(int exception, int backup) /* set the appropriate bits for coprocessor exceptions */ if(exception == EXCEPTION_BADCOP) { - CAUSE |= mips3.badcop_value << 28; + CAUSE |= m_badcop_value << 28; } /* if we were in a branch delay slot, adjust */ - if (mips3.nextpc != ~0) + if (m_nextpc != ~0) { - mips3.nextpc = ~0; - mips3.core.cpr[0][COP0_EPC] -= 4; + m_nextpc = ~0; + m_core->cpr[0][COP0_EPC] -= 4; CAUSE |= 0x80000000; } @@ -211,37 +266,37 @@ INLINE void generate_exception(int exception, int backup) SR |= SR_EXL; /* based on the BEV bit, we either go to ROM or RAM */ - mips3.core.pc = (SR & SR_BEV) ? 0xbfc00200 : 0x80000000; + m_core->pc = (SR & SR_BEV) ? 0xbfc00200 : 0x80000000; /* most exceptions go to offset 0x180, except for TLB stuff */ if (exception >= EXCEPTION_TLBMOD && exception <= EXCEPTION_TLBSTORE) { - osd_printf_debug("TLB miss @ %08X\n", (UINT32)mips3.core.cpr[0][COP0_BadVAddr]); + osd_printf_debug("TLB miss @ %08X\n", (UINT32)m_core->cpr[0][COP0_BadVAddr]); } - mips3.core.pc += offset; + m_core->pc += offset; /* useful for tracking interrupts if ((CAUSE & 0x7f) == 0) - logerror("Took interrupt -- Cause = %08X, PC = %08X\n", (UINT32)CAUSE, mips3.core.pc); + logerror("Took interrupt -- Cause = %08X, PC = %08X\n", (UINT32)CAUSE, m_core->pc); */ } -static void generate_tlb_exception(int exception, offs_t address) +void mips3_device::generate_tlb_exception(int exception, offs_t address) { - mips3.core.cpr[0][COP0_BadVAddr] = address; + m_core->cpr[0][COP0_BadVAddr] = address; if(exception == EXCEPTION_TLBLOAD || exception == EXCEPTION_TLBSTORE || exception == EXCEPTION_TLBLOAD_FILL || exception == EXCEPTION_TLBSTORE_FILL) { - mips3.core.cpr[0][COP0_Context] = (mips3.core.cpr[0][COP0_Context] & 0xff800000) | ((address >> 9) & 0x007ffff0); - mips3.core.cpr[0][COP0_EntryHi] = (address & 0xffffe000) | (mips3.core.cpr[0][COP0_EntryHi] & 0xff); + m_core->cpr[0][COP0_Context] = (m_core->cpr[0][COP0_Context] & 0xff800000) | ((address >> 9) & 0x007ffff0); + m_core->cpr[0][COP0_EntryHi] = (address & 0xffffe000) | (m_core->cpr[0][COP0_EntryHi] & 0xff); } generate_exception(exception, 1); } -INLINE void invalid_instruction(UINT32 op) +void mips3_device::invalid_instruction(UINT32 op) { generate_exception(EXCEPTION_INVALIDOP, 1); } @@ -252,7 +307,7 @@ INLINE void invalid_instruction(UINT32 op) IRQ HANDLING ***************************************************************************/ -static void check_irqs(void) +void mips3_device::check_irqs() { if ((CAUSE & SR & 0xfc00) && (SR & SR_IE) && !(SR & SR_EXL) && !(SR & SR_ERL)) generate_exception(EXCEPTION_INTERRUPT, 0); @@ -264,50 +319,679 @@ static void check_irqs(void) CORE CALLBACKS ***************************************************************************/ -static CPU_RESET( mips3 ) +void mips3_device::device_start() { - /* common reset */ - mips3com_reset(&mips3.core); - mips3.nextpc = ~0; - memset(mips3.cf, 0, sizeof(mips3.cf)); + /* allocate the implementation-specific state from the full cache */ + m_core = (internal_mips3_state *)m_cache.alloc_near(sizeof(internal_mips3_state)); + + /* initialize based on the config */ + memset(m_core, 0, sizeof(internal_mips3_state)); + + m_cpu_clock = clock(); + m_program = &space(AS_PROGRAM); + m_direct = &m_program->direct(); + + /* configure flavor-specific parameters */ + m_pfnmask = 0x00ffffff; + m_tlbentries = MIPS3_MAX_TLB_ENTRIES; + + /* VR4300 and VR5432 have 4 fewer PFN bits, and only 32 TLB entries */ + if (m_flavor == MIPS3_TYPE_VR4300) + { + m_pfnmask = 0x000fffff; + m_tlbentries = 32; + } /* set up the endianness */ - if (mips3.core.bigendian) + m_program->accessors(m_memory); + + /* allocate the virtual TLB */ + m_vtlb = vtlb_alloc(this, AS_PROGRAM, 2 * m_tlbentries + 2, 0); + + /* allocate a timer for the compare interrupt */ + m_compare_int_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mips3_device::compare_int_callback), this)); + + m_tlb_table = vtlb_table(m_vtlb); + + UINT32 flags = 0; + /* initialize the UML generator */ + if (LOG_UML) + flags |= DRCUML_OPTION_LOG_UML; + if (LOG_NATIVE) + flags |= DRCUML_OPTION_LOG_NATIVE; + m_drcuml = auto_alloc(machine(), drcuml_state(*this, m_cache, flags, 8, 32, 2)); + + /* add symbols for our stuff */ + m_drcuml->symbol_add(&m_core->pc, sizeof(m_core->pc), "pc"); + m_drcuml->symbol_add(&m_core->icount, sizeof(m_core->icount), "icount"); + for (int regnum = 0; regnum < 32; regnum++) + { + char buf[10]; + sprintf(buf, "r%d", regnum); + m_drcuml->symbol_add(&m_core->r[regnum], sizeof(m_core->r[regnum]), buf); + sprintf(buf, "f%d", regnum); + m_drcuml->symbol_add(&m_core->cpr[1][regnum], sizeof(m_core->cpr[1][regnum]), buf); + } + m_drcuml->symbol_add(&m_core->r[REG_LO], sizeof(m_core->r[REG_LO]), "lo"); + m_drcuml->symbol_add(&m_core->r[REG_HI], sizeof(m_core->r[REG_LO]), "hi"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_Index], sizeof(m_core->cpr[0][COP0_Index]), "Index"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_Random], sizeof(m_core->cpr[0][COP0_Random]), "Random"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_EntryLo0], sizeof(m_core->cpr[0][COP0_EntryLo0]), "EntryLo0"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_EntryLo1], sizeof(m_core->cpr[0][COP0_EntryLo1]), "EntryLo1"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_Context], sizeof(m_core->cpr[0][COP0_Context]), "Context"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_PageMask], sizeof(m_core->cpr[0][COP0_PageMask]), "PageMask"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_Wired], sizeof(m_core->cpr[0][COP0_Wired]), "Wired"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_BadVAddr], sizeof(m_core->cpr[0][COP0_BadVAddr]), "BadVAddr"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_Count], sizeof(m_core->cpr[0][COP0_Count]), "Count"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_EntryHi], sizeof(m_core->cpr[0][COP0_EntryHi]), "EntryHi"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_Compare], sizeof(m_core->cpr[0][COP0_Compare]), "Compare"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_Status], sizeof(m_core->cpr[0][COP0_Status]), "Status"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_Cause], sizeof(m_core->cpr[0][COP0_Cause]), "Cause"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_EPC], sizeof(m_core->cpr[0][COP0_EPC]), "EPC"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_PRId], sizeof(m_core->cpr[0][COP0_PRId]), "PRId"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_Config], sizeof(m_core->cpr[0][COP0_Config]), "Config"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_LLAddr], sizeof(m_core->cpr[0][COP0_LLAddr]), "LLAddr"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_XContext], sizeof(m_core->cpr[0][COP0_XContext]), "XContext"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_ECC], sizeof(m_core->cpr[0][COP0_ECC]), "ECC"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_CacheErr], sizeof(m_core->cpr[0][COP0_CacheErr]), "CacheErr"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_TagLo], sizeof(m_core->cpr[0][COP0_TagLo]), "TagLo"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_TagHi], sizeof(m_core->cpr[0][COP0_TagHi]), "TagHi"); + m_drcuml->symbol_add(&m_core->cpr[0][COP0_ErrorPC], sizeof(m_core->cpr[0][COP0_ErrorPC]), "ErrorPC"); + m_drcuml->symbol_add(&m_core->ccr[1][31], sizeof(m_core->cpr[1][31]), "fcr31"); + m_drcuml->symbol_add(&m_core->mode, sizeof(m_core->mode), "mode"); + m_drcuml->symbol_add(&m_core->arg0, sizeof(m_core->arg0), "arg0"); + m_drcuml->symbol_add(&m_core->arg1, sizeof(m_core->arg1), "arg1"); + m_drcuml->symbol_add(&m_core->numcycles, sizeof(m_core->numcycles), "numcycles"); + m_drcuml->symbol_add(&m_fpmode, sizeof(m_fpmode), "fpmode"); + + /* initialize the front-end helper */ + m_drcfe = auto_alloc(machine(), mips3_frontend(this, COMPILE_BACKWARDS_BYTES, COMPILE_FORWARDS_BYTES, SINGLE_INSTRUCTION_MODE ? 1 : COMPILE_MAX_SEQUENCE)); + + /* allocate memory for cache-local state and initialize it */ + memcpy(m_fpmode, fpmode_source, sizeof(fpmode_source)); + + /* compute the register parameters */ + for (int regnum = 0; regnum < 34; regnum++) + { + m_regmap[regnum] = (regnum == 0) ? uml::parameter(0) : uml::parameter::make_memory(&m_core->r[regnum]); + m_regmaplo[regnum] = (regnum == 0) ? uml::parameter(0) : uml::parameter::make_memory(LOPTR(&m_core->r[regnum])); + } + + /* if we have registers to spare, assign r2, r3, r4 to leftovers */ + if (!DISABLE_FAST_REGISTERS) + { + drcbe_info beinfo; + + m_drcuml->get_backend_info(beinfo); + if (beinfo.direct_iregs > 4) + { + m_regmap[2] = uml::I4; + m_regmaplo[2] = uml::I4; + } + if (beinfo.direct_iregs > 5) + { + m_regmap[3] = uml::I5; + m_regmaplo[3] = uml::I5; + } + if (beinfo.direct_iregs > 6) + { + m_regmap[4] = uml::I6; + m_regmaplo[4] = uml::I6; + } + } + + /* mark the cache dirty so it is updated on next execute */ + m_cache_dirty = TRUE; + + + /* register for save states */ + save_item(NAME(m_core->pc)); + save_item(NAME(m_core->r)); + save_item(NAME(m_core->cpr)); + save_item(NAME(m_core->ccr)); + save_item(NAME(m_core->llbit)); + save_item(NAME(m_core->count_zero_time)); + for (int tlbindex = 0; tlbindex < m_tlbentries; tlbindex++) + { + save_item(NAME(m_tlb[tlbindex].page_mask), tlbindex); + save_item(NAME(m_tlb[tlbindex].entry_hi), tlbindex); + save_item(NAME(m_tlb[tlbindex].entry_lo), tlbindex); + } + + // Register state with debugger + state_add( MIPS3_PC, "PC", m_core->pc).formatstr("%08X"); + +#if USE_ABI_REG_NAMES + state_add( MIPS3_R0, "zero", m_core->r[0]).callimport().formatstr("%016X"); // Can't change R0 + state_add( MIPS3_R1, "at", m_core->r[1]).formatstr("%016X"); + state_add( MIPS3_R2, "v0", m_core->r[2]).formatstr("%016X"); + state_add( MIPS3_R3, "v1", m_core->r[3]).formatstr("%016X"); + state_add( MIPS3_R4, "a0", m_core->r[4]).formatstr("%016X"); + state_add( MIPS3_R5, "a1", m_core->r[5]).formatstr("%016X"); + state_add( MIPS3_R6, "a2", m_core->r[6]).formatstr("%016X"); + state_add( MIPS3_R7, "a3", m_core->r[7]).formatstr("%016X"); + state_add( MIPS3_R8, "t0", m_core->r[8]).formatstr("%016X"); + state_add( MIPS3_R9, "t1", m_core->r[9]).formatstr("%016X"); + state_add( MIPS3_R10, "t2", m_core->r[10]).formatstr("%016X"); + state_add( MIPS3_R11, "t3", m_core->r[11]).formatstr("%016X"); + state_add( MIPS3_R12, "t4", m_core->r[12]).formatstr("%016X"); + state_add( MIPS3_R13, "t5", m_core->r[13]).formatstr("%016X"); + state_add( MIPS3_R14, "t6", m_core->r[14]).formatstr("%016X"); + state_add( MIPS3_R15, "t7", m_core->r[15]).formatstr("%016X"); + state_add( MIPS3_R16, "s0", m_core->r[16]).formatstr("%016X"); + state_add( MIPS3_R17, "s1", m_core->r[17]).formatstr("%016X"); + state_add( MIPS3_R18, "s2", m_core->r[18]).formatstr("%016X"); + state_add( MIPS3_R19, "s3", m_core->r[19]).formatstr("%016X"); + state_add( MIPS3_R20, "s4", m_core->r[20]).formatstr("%016X"); + state_add( MIPS3_R21, "s5", m_core->r[21]).formatstr("%016X"); + state_add( MIPS3_R22, "s6", m_core->r[22]).formatstr("%016X"); + state_add( MIPS3_R23, "s7", m_core->r[23]).formatstr("%016X"); + state_add( MIPS3_R24, "t8", m_core->r[24]).formatstr("%016X"); + state_add( MIPS3_R25, "t9", m_core->r[25]).formatstr("%016X"); + state_add( MIPS3_R26, "k0", m_core->r[26]).formatstr("%016X"); + state_add( MIPS3_R27, "k1", m_core->r[27]).formatstr("%016X"); + state_add( MIPS3_R28, "gp", m_core->r[28]).formatstr("%016X"); + state_add( MIPS3_R29, "sp", m_core->r[29]).formatstr("%016X"); + state_add( MIPS3_R30, "fp", m_core->r[30]).formatstr("%016X"); + state_add( MIPS3_R31, "ra", m_core->r[31]).formatstr("%016X"); +#else + state_add( MIPS3_R0, "R0", m_core->r[0]).callimport().formatstr("%016X"); // Can't change R0 + state_add( MIPS3_R1, "R1", m_core->r[1]).formatstr("%016X"); + state_add( MIPS3_R2, "R2", m_core->r[2]).formatstr("%016X"); + state_add( MIPS3_R3, "R3", m_core->r[3]).formatstr("%016X"); + state_add( MIPS3_R4, "R4", m_core->r[4]).formatstr("%016X"); + state_add( MIPS3_R5, "R5", m_core->r[5]).formatstr("%016X"); + state_add( MIPS3_R6, "R6", m_core->r[6]).formatstr("%016X"); + state_add( MIPS3_R7, "R7", m_core->r[7]).formatstr("%016X"); + state_add( MIPS3_R8, "R8", m_core->r[8]).formatstr("%016X"); + state_add( MIPS3_R9, "R9", m_core->r[9]).formatstr("%016X"); + state_add( MIPS3_R10, "R10", m_core->r[10]).formatstr("%016X"); + state_add( MIPS3_R11, "R11", m_core->r[11]).formatstr("%016X"); + state_add( MIPS3_R12, "R12", m_core->r[12]).formatstr("%016X"); + state_add( MIPS3_R13, "R13", m_core->r[13]).formatstr("%016X"); + state_add( MIPS3_R14, "R14", m_core->r[14]).formatstr("%016X"); + state_add( MIPS3_R15, "R15", m_core->r[15]).formatstr("%016X"); + state_add( MIPS3_R16, "R16", m_core->r[16]).formatstr("%016X"); + state_add( MIPS3_R17, "R17", m_core->r[17]).formatstr("%016X"); + state_add( MIPS3_R18, "R18", m_core->r[18]).formatstr("%016X"); + state_add( MIPS3_R19, "R19", m_core->r[19]).formatstr("%016X"); + state_add( MIPS3_R20, "R20", m_core->r[20]).formatstr("%016X"); + state_add( MIPS3_R21, "R21", m_core->r[21]).formatstr("%016X"); + state_add( MIPS3_R22, "R22", m_core->r[22]).formatstr("%016X"); + state_add( MIPS3_R23, "R23", m_core->r[23]).formatstr("%016X"); + state_add( MIPS3_R24, "R24", m_core->r[24]).formatstr("%016X"); + state_add( MIPS3_R25, "R25", m_core->r[25]).formatstr("%016X"); + state_add( MIPS3_R26, "R26", m_core->r[26]).formatstr("%016X"); + state_add( MIPS3_R27, "R27", m_core->r[27]).formatstr("%016X"); + state_add( MIPS3_R28, "R28", m_core->r[28]).formatstr("%016X"); + state_add( MIPS3_R29, "R29", m_core->r[29]).formatstr("%016X"); + state_add( MIPS3_R30, "R30", m_core->r[30]).formatstr("%016X"); + state_add( MIPS3_R31, "R31", m_core->r[31]).formatstr("%016X"); +#endif + state_add( MIPS3_HI, "HI", m_core->r[REG_HI]).formatstr("%016X"); + state_add( MIPS3_LO, "LO", m_core->r[REG_LO]).formatstr("%016X"); + + state_add( MIPS3_CCR1_31, "CCR31", m_core->ccr[1][31]).formatstr("%08X"); + + state_add( MIPS3_FPR0, "FPR0", m_core->cpr[1][0]).formatstr("%016X"); + state_add( MIPS3_FPS0, "FPS0", m_core->cpr[1][0]).formatstr("%17s"); + state_add( MIPS3_FPD0, "FPD0", m_core->cpr[1][0]).formatstr("%17s"); + state_add( MIPS3_FPR1, "FPR1", m_core->cpr[1][1]).formatstr("%016X"); + state_add( MIPS3_FPS1, "FPS1", m_core->cpr[1][1]).formatstr("%17s"); + state_add( MIPS3_FPD1, "FPD1", m_core->cpr[1][1]).formatstr("%17s"); + state_add( MIPS3_FPR2, "FPR2", m_core->cpr[1][2]).formatstr("%016X"); + state_add( MIPS3_FPS2, "FPS2", m_core->cpr[1][2]).formatstr("%17s"); + state_add( MIPS3_FPD2, "FPD2", m_core->cpr[1][2]).formatstr("%17s"); + state_add( MIPS3_FPR3, "FPR3", m_core->cpr[1][3]).formatstr("%016X"); + state_add( MIPS3_FPS3, "FPS3", m_core->cpr[1][3]).formatstr("%17s"); + state_add( MIPS3_FPD3, "FPD3", m_core->cpr[1][3]).formatstr("%17s"); + state_add( MIPS3_FPR4, "FPR4", m_core->cpr[1][4]).formatstr("%016X"); + state_add( MIPS3_FPS4, "FPS4", m_core->cpr[1][4]).formatstr("%17s"); + state_add( MIPS3_FPD4, "FPD4", m_core->cpr[1][4]).formatstr("%17s"); + state_add( MIPS3_FPR5, "FPR5", m_core->cpr[1][5]).formatstr("%016X"); + state_add( MIPS3_FPS5, "FPS5", m_core->cpr[1][5]).formatstr("%17s"); + state_add( MIPS3_FPD5, "FPD5", m_core->cpr[1][5]).formatstr("%17s"); + state_add( MIPS3_FPR6, "FPR6", m_core->cpr[1][6]).formatstr("%016X"); + state_add( MIPS3_FPS6, "FPS6", m_core->cpr[1][6]).formatstr("%17s"); + state_add( MIPS3_FPD6, "FPD6", m_core->cpr[1][6]).formatstr("%17s"); + state_add( MIPS3_FPR7, "FPR7", m_core->cpr[1][7]).formatstr("%016X"); + state_add( MIPS3_FPS7, "FPS7", m_core->cpr[1][7]).formatstr("%17s"); + state_add( MIPS3_FPD7, "FPD7", m_core->cpr[1][7]).formatstr("%17s"); + state_add( MIPS3_FPR8, "FPR8", m_core->cpr[1][8]).formatstr("%016X"); + state_add( MIPS3_FPS8, "FPS8", m_core->cpr[1][8]).formatstr("%17s"); + state_add( MIPS3_FPD8, "FPD8", m_core->cpr[1][8]).formatstr("%17s"); + state_add( MIPS3_FPR9, "FPR9", m_core->cpr[1][9]).formatstr("%016X"); + state_add( MIPS3_FPS9, "FPS9", m_core->cpr[1][9]).formatstr("%17s"); + state_add( MIPS3_FPD9, "FPD9", m_core->cpr[1][9]).formatstr("%17s"); + state_add( MIPS3_FPR10, "FPR10", m_core->cpr[1][10]).formatstr("%016X"); + state_add( MIPS3_FPS10, "FPS10", m_core->cpr[1][10]).formatstr("%17s"); + state_add( MIPS3_FPD10, "FPD10", m_core->cpr[1][10]).formatstr("%17s"); + state_add( MIPS3_FPR11, "FPR11", m_core->cpr[1][11]).formatstr("%016X"); + state_add( MIPS3_FPS11, "FPS11", m_core->cpr[1][11]).formatstr("%17s"); + state_add( MIPS3_FPD11, "FPD11", m_core->cpr[1][11]).formatstr("%17s"); + state_add( MIPS3_FPR12, "FPR12", m_core->cpr[1][12]).formatstr("%016X"); + state_add( MIPS3_FPS12, "FPS12", m_core->cpr[1][12]).formatstr("%17s"); + state_add( MIPS3_FPD12, "FPD12", m_core->cpr[1][12]).formatstr("%17s"); + state_add( MIPS3_FPR13, "FPR13", m_core->cpr[1][13]).formatstr("%016X"); + state_add( MIPS3_FPS13, "FPS13", m_core->cpr[1][13]).formatstr("%17s"); + state_add( MIPS3_FPD13, "FPD13", m_core->cpr[1][13]).formatstr("%17s"); + state_add( MIPS3_FPR14, "FPR14", m_core->cpr[1][14]).formatstr("%016X"); + state_add( MIPS3_FPS14, "FPS14", m_core->cpr[1][14]).formatstr("%17s"); + state_add( MIPS3_FPD14, "FPD14", m_core->cpr[1][14]).formatstr("%17s"); + state_add( MIPS3_FPR15, "FPR15", m_core->cpr[1][15]).formatstr("%016X"); + state_add( MIPS3_FPS15, "FPS15", m_core->cpr[1][15]).formatstr("%17s"); + state_add( MIPS3_FPD15, "FPD15", m_core->cpr[1][15]).formatstr("%17s"); + state_add( MIPS3_FPR16, "FPR16", m_core->cpr[1][16]).formatstr("%016X"); + state_add( MIPS3_FPS16, "FPS16", m_core->cpr[1][16]).formatstr("%17s"); + state_add( MIPS3_FPD16, "FPD16", m_core->cpr[1][16]).formatstr("%17s"); + state_add( MIPS3_FPR17, "FPR17", m_core->cpr[1][17]).formatstr("%016X"); + state_add( MIPS3_FPS17, "FPS17", m_core->cpr[1][17]).formatstr("%17s"); + state_add( MIPS3_FPD17, "FPD17", m_core->cpr[1][17]).formatstr("%17s"); + state_add( MIPS3_FPR18, "FPR18", m_core->cpr[1][18]).formatstr("%016X"); + state_add( MIPS3_FPS18, "FPS18", m_core->cpr[1][18]).formatstr("%17s"); + state_add( MIPS3_FPD18, "FPD18", m_core->cpr[1][18]).formatstr("%17s"); + state_add( MIPS3_FPR19, "FPR19", m_core->cpr[1][19]).formatstr("%016X"); + state_add( MIPS3_FPS19, "FPS19", m_core->cpr[1][19]).formatstr("%17s"); + state_add( MIPS3_FPD19, "FPD19", m_core->cpr[1][19]).formatstr("%17s"); + state_add( MIPS3_FPR20, "FPR20", m_core->cpr[1][20]).formatstr("%016X"); + state_add( MIPS3_FPS20, "FPS20", m_core->cpr[1][20]).formatstr("%17s"); + state_add( MIPS3_FPD20, "FPD20", m_core->cpr[1][20]).formatstr("%17s"); + state_add( MIPS3_FPR21, "FPR21", m_core->cpr[1][21]).formatstr("%016X"); + state_add( MIPS3_FPS21, "FPS21", m_core->cpr[1][21]).formatstr("%17s"); + state_add( MIPS3_FPD21, "FPD21", m_core->cpr[1][21]).formatstr("%17s"); + state_add( MIPS3_FPR22, "FPR22", m_core->cpr[1][22]).formatstr("%016X"); + state_add( MIPS3_FPS22, "FPS22", m_core->cpr[1][22]).formatstr("%17s"); + state_add( MIPS3_FPD22, "FPD22", m_core->cpr[1][22]).formatstr("%17s"); + state_add( MIPS3_FPR23, "FPR23", m_core->cpr[1][23]).formatstr("%016X"); + state_add( MIPS3_FPS23, "FPS23", m_core->cpr[1][23]).formatstr("%17s"); + state_add( MIPS3_FPD23, "FPD23", m_core->cpr[1][23]).formatstr("%17s"); + state_add( MIPS3_FPR24, "FPR24", m_core->cpr[1][24]).formatstr("%016X"); + state_add( MIPS3_FPS24, "FPS24", m_core->cpr[1][24]).formatstr("%17s"); + state_add( MIPS3_FPD24, "FPD24", m_core->cpr[1][24]).formatstr("%17s"); + state_add( MIPS3_FPR25, "FPR25", m_core->cpr[1][25]).formatstr("%016X"); + state_add( MIPS3_FPS25, "FPS25", m_core->cpr[1][25]).formatstr("%17s"); + state_add( MIPS3_FPD25, "FPD25", m_core->cpr[1][25]).formatstr("%17s"); + state_add( MIPS3_FPR26, "FPR26", m_core->cpr[1][26]).formatstr("%016X"); + state_add( MIPS3_FPS26, "FPS26", m_core->cpr[1][26]).formatstr("%17s"); + state_add( MIPS3_FPD26, "FPD26", m_core->cpr[1][26]).formatstr("%17s"); + state_add( MIPS3_FPR27, "FPR27", m_core->cpr[1][27]).formatstr("%016X"); + state_add( MIPS3_FPS27, "FPS27", m_core->cpr[1][27]).formatstr("%17s"); + state_add( MIPS3_FPD27, "FPD27", m_core->cpr[1][27]).formatstr("%17s"); + state_add( MIPS3_FPR28, "FPR28", m_core->cpr[1][28]).formatstr("%016X"); + state_add( MIPS3_FPS28, "FPS28", m_core->cpr[1][28]).formatstr("%17s"); + state_add( MIPS3_FPD28, "FPD28", m_core->cpr[1][28]).formatstr("%17s"); + state_add( MIPS3_FPR29, "FPR29", m_core->cpr[1][29]).formatstr("%016X"); + state_add( MIPS3_FPS29, "FPS29", m_core->cpr[1][29]).formatstr("%17s"); + state_add( MIPS3_FPD29, "FPD29", m_core->cpr[1][29]).formatstr("%17s"); + state_add( MIPS3_FPR30, "FPR30", m_core->cpr[1][30]).formatstr("%016X"); + state_add( MIPS3_FPS30, "FPS30", m_core->cpr[1][30]).formatstr("%17s"); + state_add( MIPS3_FPD30, "FPD30", m_core->cpr[1][30]).formatstr("%17s"); + state_add( MIPS3_FPR31, "FPR31", m_core->cpr[1][31]).formatstr("%016X"); + state_add( MIPS3_FPS31, "FPS31", m_core->cpr[1][31]).formatstr("%17s"); + state_add( MIPS3_FPD31, "FPD31", m_core->cpr[1][31]).formatstr("%17s"); + + state_add( MIPS3_SR, "SR", m_core->cpr[0][COP0_Status]).formatstr("%08X"); + state_add( MIPS3_EPC, "EPC", m_core->cpr[0][COP0_EPC]).formatstr("%08X"); + state_add( MIPS3_CAUSE, "Cause", m_core->cpr[0][COP0_Cause]).formatstr("%08X"); + state_add( MIPS3_COUNT, "Count", m_debugger_temp).callexport().formatstr("%08X"); + state_add( MIPS3_COMPARE, "Compare", m_core->cpr[0][COP0_Compare]).formatstr("%08X"); + state_add( MIPS3_INDEX, "Index", m_core->cpr[0][COP0_Index]).formatstr("%08X"); + state_add( MIPS3_RANDOM, "Random", m_core->cpr[0][COP0_Random]).formatstr("%08X"); + state_add( MIPS3_ENTRYHI, "EntryHi", m_core->cpr[0][COP0_EntryHi]).formatstr("%016X"); + state_add( MIPS3_ENTRYLO0, "EntryLo0", m_core->cpr[0][COP0_EntryLo0]).formatstr("%016X"); + state_add( MIPS3_ENTRYLO1, "EntryLo1", m_core->cpr[0][COP0_EntryLo1]).formatstr("%016X"); + state_add( MIPS3_PAGEMASK, "PageMask", m_core->cpr[0][COP0_PageMask]).formatstr("%016X"); + state_add( MIPS3_WIRED, "Wired", m_core->cpr[0][COP0_Wired]).formatstr("%08X"); + state_add( MIPS3_BADVADDR, "BadVAddr", m_core->cpr[0][COP0_BadVAddr]).formatstr("%08X"); + + state_add( STATE_GENPC, "GENPC", m_core->pc).noshow(); + state_add( STATE_GENSP, "GENSP", m_core->r[31]).noshow(); + state_add( STATE_GENFLAGS, "GENFLAGS", m_debugger_temp).formatstr("%1s").noshow(); + + m_icountptr = &m_core->icount; +} + + +void mips3_device::state_export(const device_state_entry &entry) +{ + switch (entry.index()) + { + case MIPS3_COUNT: + m_debugger_temp = (total_cycles() - m_core->count_zero_time) / 2; + break; + } +} + + +void mips3_device::state_string_export(const device_state_entry &entry, astring &string) +{ + switch (entry.index()) { - mips3.lwl = lwl_be; - mips3.lwr = lwr_be; - mips3.swl = swl_be; - mips3.swr = swr_be; - mips3.ldl = ldl_be; - mips3.ldr = ldr_be; - mips3.sdl = sdl_be; - mips3.sdr = sdr_be; + case MIPS3_FPS0: + string.printf("!%16g", *(float *)&m_core->cpr[1][0]); + break; + + case MIPS3_FPD0: + string.printf("!%16g", *(double *)&m_core->cpr[1][0]); + break; + + case MIPS3_FPS1: + string.printf("!%16g", *(float *)&m_core->cpr[1][1]); + break; + + case MIPS3_FPD1: + string.printf("!%16g", *(double *)&m_core->cpr[1][1]); + break; + + case MIPS3_FPS2: + string.printf("!%16g", *(float *)&m_core->cpr[1][2]); + break; + + case MIPS3_FPD2: + string.printf("!%16g", *(double *)&m_core->cpr[1][2]); + break; + + case MIPS3_FPS3: + string.printf("!%16g", *(float *)&m_core->cpr[1][3]); + break; + + case MIPS3_FPD3: + string.printf("!%16g", *(double *)&m_core->cpr[1][3]); + break; + + case MIPS3_FPS4: + string.printf("!%16g", *(float *)&m_core->cpr[1][4]); + break; + + case MIPS3_FPD4: + string.printf("!%16g", *(double *)&m_core->cpr[1][4]); + break; + + case MIPS3_FPS5: + string.printf("!%16g", *(float *)&m_core->cpr[1][5]); + break; + + case MIPS3_FPD5: + string.printf("!%16g", *(double *)&m_core->cpr[1][5]); + break; + + case MIPS3_FPS6: + string.printf("!%16g", *(float *)&m_core->cpr[1][6]); + break; + + case MIPS3_FPD6: + string.printf("!%16g", *(double *)&m_core->cpr[1][6]); + break; + + case MIPS3_FPS7: + string.printf("!%16g", *(float *)&m_core->cpr[1][7]); + break; + + case MIPS3_FPD7: + string.printf("!%16g", *(double *)&m_core->cpr[1][7]); + break; + + case MIPS3_FPS8: + string.printf("!%16g", *(float *)&m_core->cpr[1][8]); + break; + + case MIPS3_FPD8: + string.printf("!%16g", *(double *)&m_core->cpr[1][8]); + break; + + case MIPS3_FPS9: + string.printf("!%16g", *(float *)&m_core->cpr[1][9]); + break; + + case MIPS3_FPD9: + string.printf("!%16g", *(double *)&m_core->cpr[1][9]); + break; + + case MIPS3_FPS10: + string.printf("!%16g", *(float *)&m_core->cpr[1][10]); + break; + + case MIPS3_FPD10: + string.printf("!%16g", *(double *)&m_core->cpr[1][10]); + break; + + case MIPS3_FPS11: + string.printf("!%16g", *(float *)&m_core->cpr[1][11]); + break; + + case MIPS3_FPD11: + string.printf("!%16g", *(double *)&m_core->cpr[1][11]); + break; + + case MIPS3_FPS12: + string.printf("!%16g", *(float *)&m_core->cpr[1][12]); + break; + + case MIPS3_FPD12: + string.printf("!%16g", *(double *)&m_core->cpr[1][12]); + break; + + case MIPS3_FPS13: + string.printf("!%16g", *(float *)&m_core->cpr[1][13]); + break; + + case MIPS3_FPD13: + string.printf("!%16g", *(double *)&m_core->cpr[1][13]); + break; + + case MIPS3_FPS14: + string.printf("!%16g", *(float *)&m_core->cpr[1][14]); + break; + + case MIPS3_FPD14: + string.printf("!%16g", *(double *)&m_core->cpr[1][14]); + break; + + case MIPS3_FPS15: + string.printf("!%16g", *(float *)&m_core->cpr[1][15]); + break; + + case MIPS3_FPD15: + string.printf("!%16g", *(double *)&m_core->cpr[1][15]); + break; + + case MIPS3_FPS16: + string.printf("!%16g", *(float *)&m_core->cpr[1][16]); + break; + + case MIPS3_FPD16: + string.printf("!%16g", *(double *)&m_core->cpr[1][16]); + break; + + case MIPS3_FPS17: + string.printf("!%16g", *(float *)&m_core->cpr[1][17]); + break; + + case MIPS3_FPD17: + string.printf("!%16g", *(double *)&m_core->cpr[1][17]); + break; + + case MIPS3_FPS18: + string.printf("!%16g", *(float *)&m_core->cpr[1][18]); + break; + + case MIPS3_FPD18: + string.printf("!%16g", *(double *)&m_core->cpr[1][18]); + break; + + case MIPS3_FPS19: + string.printf("!%16g", *(float *)&m_core->cpr[1][19]); + break; + + case MIPS3_FPD19: + string.printf("!%16g", *(double *)&m_core->cpr[1][19]); + break; + + case MIPS3_FPS20: + string.printf("!%16g", *(float *)&m_core->cpr[1][20]); + break; + + case MIPS3_FPD20: + string.printf("!%16g", *(double *)&m_core->cpr[1][20]); + break; + + case MIPS3_FPS21: + string.printf("!%16g", *(float *)&m_core->cpr[1][21]); + break; + + case MIPS3_FPD21: + string.printf("!%16g", *(double *)&m_core->cpr[1][21]); + break; + + case MIPS3_FPS22: + string.printf("!%16g", *(float *)&m_core->cpr[1][22]); + break; + + case MIPS3_FPD22: + string.printf("!%16g", *(double *)&m_core->cpr[1][22]); + break; + + case MIPS3_FPS23: + string.printf("!%16g", *(float *)&m_core->cpr[1][23]); + break; + + case MIPS3_FPD23: + string.printf("!%16g", *(double *)&m_core->cpr[1][23]); + break; + + case MIPS3_FPS24: + string.printf("!%16g", *(float *)&m_core->cpr[1][24]); + break; + + case MIPS3_FPD24: + string.printf("!%16g", *(double *)&m_core->cpr[1][24]); + break; + + case MIPS3_FPS25: + string.printf("!%16g", *(float *)&m_core->cpr[1][25]); + break; + + case MIPS3_FPD25: + string.printf("!%16g", *(double *)&m_core->cpr[1][25]); + break; + + case MIPS3_FPS26: + string.printf("!%16g", *(float *)&m_core->cpr[1][26]); + break; + + case MIPS3_FPD26: + string.printf("!%16g", *(double *)&m_core->cpr[1][26]); + break; + + case MIPS3_FPS27: + string.printf("!%16g", *(float *)&m_core->cpr[1][27]); + break; + + case MIPS3_FPD27: + string.printf("!%16g", *(double *)&m_core->cpr[1][27]); + break; + + case MIPS3_FPS28: + string.printf("!%16g", *(float *)&m_core->cpr[1][28]); + break; + + case MIPS3_FPD28: + string.printf("!%16g", *(double *)&m_core->cpr[1][28]); + break; + + case MIPS3_FPS29: + string.printf("!%16g", *(float *)&m_core->cpr[1][29]); + break; + + case MIPS3_FPD29: + string.printf("!%16g", *(double *)&m_core->cpr[1][29]); + break; + + case MIPS3_FPS30: + string.printf("!%16g", *(float *)&m_core->cpr[1][30]); + break; + + case MIPS3_FPD30: + string.printf("!%16g", *(double *)&m_core->cpr[1][30]); + break; + + case MIPS3_FPS31: + string.printf("!%16g", *(float *)&m_core->cpr[1][31]); + break; + + case MIPS3_FPD31: + string.printf("!%16g", *(double *)&m_core->cpr[1][31]); + break; + + case STATE_GENFLAGS: + string.printf(" "); + break; } - else +} + + +void mips3_device::device_reset() +{ + /* common reset */ + m_nextpc = ~0; + memset(m_cf, 0, sizeof(m_cf)); + + /* initialize the state */ + m_core->pc = 0xbfc00000; + m_core->cpr[0][COP0_Status] = SR_BEV | SR_ERL; + m_core->cpr[0][COP0_Wired] = 0; + m_core->cpr[0][COP0_Compare] = 0xffffffff; + m_core->cpr[0][COP0_Count] = 0; + m_core->cpr[0][COP0_Config] = compute_config_register(); + m_core->cpr[0][COP0_PRId] = compute_prid_register(); + m_core->count_zero_time = total_cycles(); + + /* initialize the TLB state */ + for (int tlbindex = 0; tlbindex < m_tlbentries; tlbindex++) { - mips3.lwl = lwl_le; - mips3.lwr = lwr_le; - mips3.swl = swl_le; - mips3.swr = swr_le; - mips3.ldl = ldl_le; - mips3.ldr = ldr_le; - mips3.sdl = sdl_le; - mips3.sdr = sdr_le; + mips3_tlb_entry *entry = &m_tlb[tlbindex]; + entry->page_mask = 0; + entry->entry_hi = 0xffffffff; + entry->entry_lo[0] = 0xfffffff8; + entry->entry_lo[1] = 0xfffffff8; + vtlb_load(m_vtlb, 2 * tlbindex + 0, 0, 0, 0); + vtlb_load(m_vtlb, 2 * tlbindex + 1, 0, 0, 0); } + + /* load the fixed TLB range */ + vtlb_load(m_vtlb, 2 * m_tlbentries + 0, (0xa0000000 - 0x80000000) >> MIPS3_MIN_PAGE_SHIFT, 0x80000000, 0x00000000 | VTLB_READ_ALLOWED | VTLB_WRITE_ALLOWED | VTLB_FETCH_ALLOWED | VTLB_FLAG_VALID); + vtlb_load(m_vtlb, 2 * m_tlbentries + 1, (0xc0000000 - 0xa0000000) >> MIPS3_MIN_PAGE_SHIFT, 0xa0000000, 0x00000000 | VTLB_READ_ALLOWED | VTLB_WRITE_ALLOWED | VTLB_FETCH_ALLOWED | VTLB_FLAG_VALID); + + m_core->mode = (MODE_KERNEL << 1) | 0; + m_cache_dirty = TRUE; + m_interrupt_cycles = 0; } -static CPU_TRANSLATE( mips3 ) +bool mips3_device::memory_translate(address_spacenum spacenum, int intention, offs_t &address) { - /* common translate */ - return mips3com_translate_address(&mips3.core, space, intention, address); + /* only applies to the program address space */ + if (spacenum == AS_PROGRAM) + { + const vtlb_entry *table = vtlb_table(m_vtlb); + vtlb_entry entry = table[address >> MIPS3_MIN_PAGE_SHIFT]; + if ((entry & (1 << (intention & (TRANSLATE_TYPE_MASK | TRANSLATE_USER_MASK)))) == 0) + return false; + address = (entry & ~MIPS3_MIN_PAGE_MASK) | (address & MIPS3_MIN_PAGE_MASK); + } + return true; } -CPU_DISASSEMBLE( mips3 ) +offs_t mips3_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { - /* common disassemble */ - return mips3com_dasm(&mips3.core, buffer, pc, oprom, opram); + extern unsigned dasmmips3(char *, unsigned, UINT32); + UINT32 op = *(UINT32 *)oprom; + if (m_bigendian) + op = BIG_ENDIANIZE_INT32(op); + else + op = LITTLE_ENDIANIZE_INT32(op); + return dasmmips3(buffer, pc, op); } @@ -316,12 +1000,12 @@ CPU_DISASSEMBLE( mips3 ) TLB HANDLING ***************************************************************************/ -INLINE int RBYTE(offs_t address, UINT32 *result) +inline int mips3_device::RBYTE(offs_t address, UINT32 *result) { - UINT32 tlbval = mips3.tlb_table[address >> 12]; + UINT32 tlbval = m_tlb_table[address >> 12]; if (tlbval & VTLB_READ_ALLOWED) { - *result = (*mips3.core.memory.read_byte)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff)); + *result = (*m_memory.read_byte)(*m_program, (tlbval & ~0xfff) | (address & 0xfff)); } else { @@ -340,12 +1024,12 @@ INLINE int RBYTE(offs_t address, UINT32 *result) } -INLINE int RHALF(offs_t address, UINT32 *result) +inline int mips3_device::RHALF(offs_t address, UINT32 *result) { - UINT32 tlbval = mips3.tlb_table[address >> 12]; + UINT32 tlbval = m_tlb_table[address >> 12]; if (tlbval & VTLB_READ_ALLOWED) { - *result = (*mips3.core.memory.read_word)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff)); + *result = (*m_memory.read_word)(*m_program, (tlbval & ~0xfff) | (address & 0xfff)); } else { @@ -364,12 +1048,12 @@ INLINE int RHALF(offs_t address, UINT32 *result) } -INLINE int RWORD(offs_t address, UINT32 *result) +inline int mips3_device::RWORD(offs_t address, UINT32 *result) { - UINT32 tlbval = mips3.tlb_table[address >> 12]; + UINT32 tlbval = m_tlb_table[address >> 12]; if (tlbval & VTLB_READ_ALLOWED) { - *result = (*mips3.core.memory.read_dword)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff)); + *result = (*m_memory.read_dword)(*m_program, (tlbval & ~0xfff) | (address & 0xfff)); } else { @@ -388,12 +1072,12 @@ INLINE int RWORD(offs_t address, UINT32 *result) } -INLINE int RWORD_MASKED(offs_t address, UINT32 *result, UINT32 mem_mask) +inline int mips3_device::RWORD_MASKED(offs_t address, UINT32 *result, UINT32 mem_mask) { - UINT32 tlbval = mips3.tlb_table[address >> 12]; + UINT32 tlbval = m_tlb_table[address >> 12]; if (tlbval & VTLB_READ_ALLOWED) { - *result = (*mips3.core.memory.read_dword_masked)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff), mem_mask); + *result = (*m_memory.read_dword_masked)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), mem_mask); } else { @@ -412,12 +1096,12 @@ INLINE int RWORD_MASKED(offs_t address, UINT32 *result, UINT32 mem_mask) } -INLINE int RDOUBLE(offs_t address, UINT64 *result) +inline int mips3_device::RDOUBLE(offs_t address, UINT64 *result) { - UINT32 tlbval = mips3.tlb_table[address >> 12]; + UINT32 tlbval = m_tlb_table[address >> 12]; if (tlbval & VTLB_READ_ALLOWED) { - *result = (*mips3.core.memory.read_qword)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff)); + *result = (*m_memory.read_qword)(*m_program, (tlbval & ~0xfff) | (address & 0xfff)); } else { @@ -436,12 +1120,12 @@ INLINE int RDOUBLE(offs_t address, UINT64 *result) } -INLINE int RDOUBLE_MASKED(offs_t address, UINT64 *result, UINT64 mem_mask) +inline int mips3_device::RDOUBLE_MASKED(offs_t address, UINT64 *result, UINT64 mem_mask) { - UINT32 tlbval = mips3.tlb_table[address >> 12]; + UINT32 tlbval = m_tlb_table[address >> 12]; if (tlbval & VTLB_READ_ALLOWED) { - *result = (*mips3.core.memory.read_qword_masked)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff), mem_mask); + *result = (*m_memory.read_qword_masked)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), mem_mask); } else { @@ -460,12 +1144,12 @@ INLINE int RDOUBLE_MASKED(offs_t address, UINT64 *result, UINT64 mem_mask) } -INLINE void WBYTE(offs_t address, UINT8 data) +inline void mips3_device::WBYTE(offs_t address, UINT8 data) { - UINT32 tlbval = mips3.tlb_table[address >> 12]; + UINT32 tlbval = m_tlb_table[address >> 12]; if (tlbval & VTLB_WRITE_ALLOWED) { - (*mips3.core.memory.write_byte)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff), data); + (*m_memory.write_byte)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data); } else { @@ -485,12 +1169,12 @@ INLINE void WBYTE(offs_t address, UINT8 data) } -INLINE void WHALF(offs_t address, UINT16 data) +inline void mips3_device::WHALF(offs_t address, UINT16 data) { - UINT32 tlbval = mips3.tlb_table[address >> 12]; + UINT32 tlbval = m_tlb_table[address >> 12]; if (tlbval & VTLB_WRITE_ALLOWED) { - (*mips3.core.memory.write_word)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff), data); + (*m_memory.write_word)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data); } else { @@ -510,12 +1194,12 @@ INLINE void WHALF(offs_t address, UINT16 data) } -INLINE void WWORD(offs_t address, UINT32 data) +inline void mips3_device::WWORD(offs_t address, UINT32 data) { - UINT32 tlbval = mips3.tlb_table[address >> 12]; + UINT32 tlbval = m_tlb_table[address >> 12]; if (tlbval & VTLB_WRITE_ALLOWED) { - (*mips3.core.memory.write_dword)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff), data); + (*m_memory.write_dword)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data); } else { @@ -535,12 +1219,12 @@ INLINE void WWORD(offs_t address, UINT32 data) } -INLINE void WWORD_MASKED(offs_t address, UINT32 data, UINT32 mem_mask) +inline void mips3_device::WWORD_MASKED(offs_t address, UINT32 data, UINT32 mem_mask) { - UINT32 tlbval = mips3.tlb_table[address >> 12]; + UINT32 tlbval = m_tlb_table[address >> 12]; if (tlbval & VTLB_WRITE_ALLOWED) { - (*mips3.core.memory.write_dword_masked)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff), data, mem_mask); + (*m_memory.write_dword_masked)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data, mem_mask); } else { @@ -560,13 +1244,13 @@ INLINE void WWORD_MASKED(offs_t address, UINT32 data, UINT32 mem_mask) } -INLINE void WDOUBLE(offs_t address, UINT64 data) +inline void mips3_device::WDOUBLE(offs_t address, UINT64 data) { - UINT32 tlbval = mips3.tlb_table[address >> 12]; + UINT32 tlbval = m_tlb_table[address >> 12]; //printf("%08x: %08x\n", (UINT32)address, (UINT32)tlbval); if (tlbval & VTLB_WRITE_ALLOWED) { - (*mips3.core.memory.write_qword)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff), data); + (*m_memory.write_qword)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data); } else { @@ -586,12 +1270,12 @@ INLINE void WDOUBLE(offs_t address, UINT64 data) } -INLINE void WDOUBLE_MASKED(offs_t address, UINT64 data, UINT64 mem_mask) +inline void mips3_device::WDOUBLE_MASKED(offs_t address, UINT64 data, UINT64 mem_mask) { - UINT32 tlbval = mips3.tlb_table[address >> 12]; + UINT32 tlbval = m_tlb_table[address >> 12]; if (tlbval & VTLB_WRITE_ALLOWED) { - (*mips3.core.memory.write_qword_masked)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff), data, mem_mask); + (*m_memory.write_qword_masked)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data, mem_mask); } else { @@ -616,40 +1300,40 @@ INLINE void WDOUBLE_MASKED(offs_t address, UINT64 data, UINT64 mem_mask) COP0 (SYSTEM) EXECUTION HANDLING ***************************************************************************/ -INLINE UINT64 get_cop0_reg(int idx) +inline UINT64 mips3_device::get_cop0_reg(int idx) { if (idx == COP0_Count) { /* it doesn't really take 250 cycles to read this register, but it helps speed */ /* up loops that hammer on it */ - if (mips3.core.icount >= MIPS3_COUNT_READ_CYCLES) - mips3.core.icount -= MIPS3_COUNT_READ_CYCLES; + if (m_core->icount >= MIPS3_COUNT_READ_CYCLES) + m_core->icount -= MIPS3_COUNT_READ_CYCLES; else - mips3.core.icount = 0; - return (UINT32)((mips3.core.device->total_cycles() - mips3.core.count_zero_time) / 2); + m_core->icount = 0; + return (UINT32)((total_cycles() - m_core->count_zero_time) / 2); } else if (idx == COP0_Cause) { /* it doesn't really take 250 cycles to read this register, but it helps speed */ /* up loops that hammer on it */ - if (mips3.core.icount >= MIPS3_CAUSE_READ_CYCLES) - mips3.core.icount -= MIPS3_CAUSE_READ_CYCLES; + if (m_core->icount >= MIPS3_CAUSE_READ_CYCLES) + m_core->icount -= MIPS3_CAUSE_READ_CYCLES; else - mips3.core.icount = 0; + m_core->icount = 0; } else if (idx == COP0_Random) { - int wired = mips3.core.cpr[0][COP0_Wired] & 0x3f; + int wired = m_core->cpr[0][COP0_Wired] & 0x3f; int range = 48 - wired; if (range > 0) - return ((mips3.core.device->total_cycles() - mips3.core.count_zero_time) % range + wired) & 0x3f; + return ((total_cycles() - m_core->count_zero_time) % range + wired) & 0x3f; else return 47; } - return mips3.core.cpr[0][idx]; + return m_core->cpr[0][idx]; } -INLINE void set_cop0_reg(int idx, UINT64 val) +inline void mips3_device::set_cop0_reg(int idx, UINT64 val) { switch (idx) { @@ -658,10 +1342,10 @@ INLINE void set_cop0_reg(int idx, UINT64 val) if (CAUSE & 0x300) { /* if we're in a delay slot, propogate the target PC before generating the exception */ - if (mips3.nextpc != ~0) + if (m_nextpc != ~0) { - mips3.core.pc = mips3.nextpc; - mips3.nextpc = ~0; + m_core->pc = m_nextpc; + m_nextpc = ~0; } generate_exception(EXCEPTION_INTERRUPT, 0); } @@ -670,67 +1354,67 @@ INLINE void set_cop0_reg(int idx, UINT64 val) case COP0_Status: { /* update interrupts and cycle counting */ - UINT32 diff = mips3.core.cpr[0][idx] ^ val; + UINT32 diff = m_core->cpr[0][idx] ^ val; // if (val & 0xe0) // fatalerror("System set 64-bit addressing mode, SR=%08X\n", val); - mips3.core.cpr[0][idx] = val; + m_core->cpr[0][idx] = val; if (diff & 0x8000) - mips3com_update_cycle_counting(&mips3.core); + mips3com_update_cycle_counting(); check_irqs(); break; } case COP0_Count: - mips3.core.cpr[0][idx] = val; - mips3.core.count_zero_time = mips3.core.device->total_cycles() - ((UINT64)(UINT32)val * 2); - mips3com_update_cycle_counting(&mips3.core); + m_core->cpr[0][idx] = val; + m_core->count_zero_time = total_cycles() - ((UINT64)(UINT32)val * 2); + mips3com_update_cycle_counting(); break; case COP0_Compare: - mips3.core.compare_armed = 1; + m_core->compare_armed = 1; CAUSE &= ~0x8000; - mips3.core.cpr[0][idx] = val & 0xffffffff; - mips3com_update_cycle_counting(&mips3.core); + m_core->cpr[0][idx] = val & 0xffffffff; + mips3com_update_cycle_counting(); break; case COP0_PRId: break; case COP0_Config: - mips3.core.cpr[0][idx] = (mips3.core.cpr[0][idx] & ~7) | (val & 7); + m_core->cpr[0][idx] = (m_core->cpr[0][idx] & ~7) | (val & 7); break; case COP0_EntryHi: /* if the ASID changes, remap */ - if ((mips3.core.cpr[0][idx] ^ val) & 0xff) + if ((m_core->cpr[0][idx] ^ val) & 0xff) { - mips3.core.cpr[0][idx] = val; - mips3com_asid_changed(&mips3.core); + m_core->cpr[0][idx] = val; + mips3com_asid_changed(); } - mips3.core.cpr[0][idx] = val; + m_core->cpr[0][idx] = val; break; default: - mips3.core.cpr[0][idx] = val; + m_core->cpr[0][idx] = val; break; } } -INLINE UINT64 get_cop0_creg(int idx) +inline UINT64 mips3_device::get_cop0_creg(int idx) { - return mips3.core.ccr[0][idx]; + return m_core->ccr[0][idx]; } -INLINE void set_cop0_creg(int idx, UINT64 val) +inline void mips3_device::set_cop0_creg(int idx, UINT64 val) { - mips3.core.ccr[0][idx] = val; + m_core->ccr[0][idx] = val; } -INLINE void handle_cop0(UINT32 op) +inline void mips3_device::handle_cop0(UINT32 op) { if ((SR & SR_KSU_MASK) != SR_KSU_KERNEL && !(SR & SR_COP0)) { - mips3.badcop_value = 0; + m_badcop_value = 0; generate_exception(EXCEPTION_BADCOP, 1); } @@ -745,8 +1429,8 @@ INLINE void handle_cop0(UINT32 op) case 0x08: /* BC */ switch (RTREG) { - case 0x00: /* BCzF */ if (!mips3.cf[0]) ADDPC(SIMMVAL); break; - case 0x01: /* BCzF */ if (mips3.cf[0]) ADDPC(SIMMVAL); break; + case 0x00: /* BCzF */ if (!m_cf[0]) ADDPC(SIMMVAL); break; + case 0x01: /* BCzF */ if (m_cf[0]) ADDPC(SIMMVAL); break; case 0x02: /* BCzFL */ invalid_instruction(op); break; case 0x03: /* BCzTL */ invalid_instruction(op); break; default: invalid_instruction(op); break; @@ -771,23 +1455,23 @@ INLINE void handle_cop0(UINT32 op) switch (op & 0x01ffffff) { case 0x01: /* TLBR */ - mips3com_tlbr(&mips3.core); + mips3com_tlbr(); break; case 0x02: /* TLBWI */ - mips3com_tlbwi(&mips3.core); + mips3com_tlbwi(); break; case 0x06: /* TLBWR */ - mips3com_tlbwr(&mips3.core); + mips3com_tlbwr(); break; case 0x08: /* TLBP */ - mips3com_tlbp(&mips3.core); + mips3com_tlbp(); break; case 0x10: /* RFE */ invalid_instruction(op); break; - case 0x18: /* ERET */ logerror("ERET\n"); mips3.core.pc = mips3.core.cpr[0][COP0_EPC]; SR &= ~SR_EXL; check_irqs(); mips3.lld_value ^= 0xffffffff; mips3.ll_value ^= 0xffffffff; break; + case 0x18: /* ERET */ logerror("ERET\n"); m_core->pc = m_core->cpr[0][COP0_EPC]; SR &= ~SR_EXL; check_irqs(); m_lld_value ^= 0xffffffff; m_ll_value ^= 0xffffffff; break; case 0x20: /* WAIT */ break; default: invalid_instruction(op); break; } @@ -802,66 +1486,66 @@ INLINE void handle_cop0(UINT32 op) COP1 (FPU) EXECUTION HANDLING ***************************************************************************/ -INLINE UINT32 get_cop1_reg32(int idx) +inline UINT32 mips3_device::get_cop1_reg32(int idx) { if (IS_FR0) - return ((UINT32 *)&mips3.core.cpr[1][0])[idx]; + return ((UINT32 *)&m_core->cpr[1][0])[idx]; else - return mips3.core.cpr[1][idx]; + return m_core->cpr[1][idx]; } -INLINE UINT64 get_cop1_reg64(int idx) +inline UINT64 mips3_device::get_cop1_reg64(int idx) { if (IS_FR0) - return ((UINT64 *)&mips3.core.cpr[1][0])[idx/2]; + return ((UINT64 *)&m_core->cpr[1][0])[idx/2]; else - return mips3.core.cpr[1][idx]; + return m_core->cpr[1][idx]; } -INLINE void set_cop1_reg32(int idx, UINT32 val) +inline void mips3_device::set_cop1_reg32(int idx, UINT32 val) { if (IS_FR0) - ((UINT32 *)&mips3.core.cpr[1][0])[idx] = val; + ((UINT32 *)&m_core->cpr[1][0])[idx] = val; else - mips3.core.cpr[1][idx] = val; + m_core->cpr[1][idx] = val; } -INLINE void set_cop1_reg64(int idx, UINT64 val) +inline void mips3_device::set_cop1_reg64(int idx, UINT64 val) { if (IS_FR0) - ((UINT64 *)&mips3.core.cpr[1][0])[idx/2] = val; + ((UINT64 *)&m_core->cpr[1][0])[idx/2] = val; else - mips3.core.cpr[1][idx] = val; + m_core->cpr[1][idx] = val; } -INLINE UINT64 get_cop1_creg(int idx) +inline UINT64 mips3_device::get_cop1_creg(int idx) { if (idx == 31) { - UINT32 result = mips3.core.ccr[1][31] & ~0xfe800000; + UINT32 result = m_core->ccr[1][31] & ~0xfe800000; int i; for (i = 0; i < 8; i++) - if (mips3.cf[1][i]) + if (m_cf[1][i]) result |= 1 << fcc_shift[i]; return result; } - return mips3.core.ccr[1][idx]; + return m_core->ccr[1][idx]; } -INLINE void set_cop1_creg(int idx, UINT64 val) +inline void mips3_device::set_cop1_creg(int idx, UINT64 val) { - mips3.core.ccr[1][idx] = val; + m_core->ccr[1][idx] = val; if (idx == 31) { int i; for (i = 0; i < 8; i++) - mips3.cf[1][i] = (val >> fcc_shift[i]) & 1; + m_cf[1][i] = (val >> fcc_shift[i]) & 1; } } -INLINE void handle_cop1_fr0(UINT32 op) +inline void mips3_device::handle_cop1_fr0(UINT32 op) { double dtemp; @@ -869,7 +1553,7 @@ INLINE void handle_cop1_fr0(UINT32 op) if (!(SR & SR_COP1)) { - mips3.badcop_value = 1; + m_badcop_value = 1; generate_exception(EXCEPTION_BADCOP, 1); } @@ -886,8 +1570,8 @@ INLINE void handle_cop1_fr0(UINT32 op) { case 0x00: /* BCzF */ if (!GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); break; case 0x01: /* BCzT */ if (GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); break; - case 0x02: /* BCzFL */ if (!GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); else mips3.core.pc += 4; break; - case 0x03: /* BCzTL */ if (GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); else mips3.core.pc += 4; break; + case 0x02: /* BCzFL */ if (!GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); else m_core->pc += 4; break; + case 0x03: /* BCzTL */ if (GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); else m_core->pc += 4; break; } break; default: @@ -1220,7 +1904,7 @@ INLINE void handle_cop1_fr0(UINT32 op) } -INLINE void handle_cop1_fr1(UINT32 op) +inline void mips3_device::handle_cop1_fr1(UINT32 op) { double dtemp; @@ -1228,7 +1912,7 @@ INLINE void handle_cop1_fr1(UINT32 op) if (!(SR & SR_COP1)) { - mips3.badcop_value = 1; + m_badcop_value = 1; generate_exception(EXCEPTION_BADCOP, 1); } @@ -1245,8 +1929,8 @@ INLINE void handle_cop1_fr1(UINT32 op) { case 0x00: /* BCzF */ if (!GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); break; case 0x01: /* BCzT */ if (GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); break; - case 0x02: /* BCzFL */ if (!GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); else mips3.core.pc += 4; break; - case 0x03: /* BCzTL */ if (GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); else mips3.core.pc += 4; break; + case 0x02: /* BCzFL */ if (!GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); else m_core->pc += 4; break; + case 0x03: /* BCzTL */ if (GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); else m_core->pc += 4; break; } break; default: @@ -1584,14 +2268,14 @@ INLINE void handle_cop1_fr1(UINT32 op) COP1X (FPU EXTRA) EXECUTION HANDLING ***************************************************************************/ -INLINE void handle_cop1x_fr0(UINT32 op) +inline void mips3_device::handle_cop1x_fr0(UINT32 op) { UINT64 temp64; UINT32 temp; if (!(SR & SR_COP1)) { - mips3.badcop_value = 1; + m_badcop_value = 1; generate_exception(EXCEPTION_BADCOP, 1); } @@ -1663,14 +2347,14 @@ INLINE void handle_cop1x_fr0(UINT32 op) } -INLINE void handle_cop1x_fr1(UINT32 op) +inline void mips3_device::handle_cop1x_fr1(UINT32 op) { UINT64 temp64; UINT32 temp; if (!(SR & SR_COP1)) { - mips3.badcop_value = 1; + m_badcop_value = 1; generate_exception(EXCEPTION_BADCOP, 1); } @@ -1747,31 +2431,31 @@ INLINE void handle_cop1x_fr1(UINT32 op) COP2 (CUSTOM) EXECUTION HANDLING ***************************************************************************/ -INLINE UINT64 get_cop2_reg(int idx) +inline UINT64 mips3_device::get_cop2_reg(int idx) { - return mips3.core.cpr[2][idx]; + return m_core->cpr[2][idx]; } -INLINE void set_cop2_reg(int idx, UINT64 val) +inline void mips3_device::set_cop2_reg(int idx, UINT64 val) { - mips3.core.cpr[2][idx] = val; + m_core->cpr[2][idx] = val; } -INLINE UINT64 get_cop2_creg(int idx) +inline UINT64 mips3_device::get_cop2_creg(int idx) { - return mips3.core.ccr[2][idx]; + return m_core->ccr[2][idx]; } -INLINE void set_cop2_creg(int idx, UINT64 val) +inline void mips3_device::set_cop2_creg(int idx, UINT64 val) { - mips3.core.ccr[2][idx] = val; + m_core->ccr[2][idx] = val; } -INLINE void handle_cop2(UINT32 op) +inline void mips3_device::handle_cop2(UINT32 op) { if (!(SR & SR_COP2)) { - mips3.badcop_value = 2; + m_badcop_value = 2; generate_exception(EXCEPTION_BADCOP, 1); } @@ -1786,8 +2470,8 @@ INLINE void handle_cop2(UINT32 op) case 0x08: /* BC */ switch (RTREG) { - case 0x00: /* BCzF */ if (!mips3.cf[2]) ADDPC(SIMMVAL); break; - case 0x01: /* BCzF */ if (mips3.cf[2]) ADDPC(SIMMVAL); break; + case 0x00: /* BCzF */ if (!m_cf[2]) ADDPC(SIMMVAL); break; + case 0x01: /* BCzF */ if (m_cf[2]) ADDPC(SIMMVAL); break; case 0x02: /* BCzFL */ invalid_instruction(op); break; case 0x03: /* BCzTL */ invalid_instruction(op); break; default: invalid_instruction(op); break; @@ -1819,14 +2503,48 @@ INLINE void handle_cop2(UINT32 op) CORE EXECUTION LOOP ***************************************************************************/ -CPU_EXECUTE( mips3 ) +void mips3_device::execute_run() { + if (m_isdrc) + { + int execute_result; + + /* reset the cache if dirty */ + if (m_cache_dirty) + code_flush_cache(); + m_cache_dirty = FALSE; + + /* execute */ + do + { + /* run as much as we can */ + execute_result = m_drcuml->execute(*m_entry); + + /* if we need to recompile, do it */ + if (execute_result == EXECUTE_MISSING_CODE) + { + code_compile_block(m_core->mode, m_core->pc); + } + else if (execute_result == EXECUTE_UNMAPPED_CODE) + { + fatalerror("Attempted to execute unmapped code at PC=%08X\n", m_core->pc); + } + else if (execute_result == EXECUTE_RESET_CACHE) + { + code_flush_cache(); + } + + } while (execute_result != EXECUTE_OUT_OF_CYCLES); + + return; + } + /* count cycles and interrupt cycles */ - mips3.core.icount -= mips3.interrupt_cycles; - mips3.interrupt_cycles = 0; + m_core->icount -= m_interrupt_cycles; + m_interrupt_cycles = 0; /* update timers & such */ - mips3com_update_cycle_counting(&mips3.core); + mips3com_update_cycle_counting(); /* check for IRQs */ check_irqs(); @@ -1839,23 +2557,23 @@ CPU_EXECUTE( mips3 ) UINT32 temp; /* debugging */ - mips3.ppc = mips3.core.pc; - debugger_instruction_hook(device, mips3.core.pc); + m_ppc = m_core->pc; + debugger_instruction_hook(this, m_core->pc); /* instruction fetch */ - if(!RWORD(mips3.core.pc, &op)) + if(!RWORD(m_core->pc, &op)) { continue; } /* adjust for next PC */ - if (mips3.nextpc != ~0) + if (m_nextpc != ~0) { - mips3.core.pc = mips3.nextpc; - mips3.nextpc = ~0; + m_core->pc = m_nextpc; + m_nextpc = ~0; } else - mips3.core.pc += 4; + m_core->pc += 4; /* parse the instruction */ switch (op >> 26) @@ -1888,13 +2606,13 @@ CPU_EXECUTE( mips3 ) temp64 = (INT64)(INT32)RSVAL32 * (INT64)(INT32)RTVAL32; LOVAL64 = (INT32)temp64; HIVAL64 = (INT32)(temp64 >> 32); - mips3.core.icount -= 3; + m_core->icount -= 3; break; case 0x19: /* MULTU */ temp64 = (UINT64)RSVAL32 * (UINT64)RTVAL32; LOVAL64 = (INT32)temp64; HIVAL64 = (INT32)(temp64 >> 32); - mips3.core.icount -= 3; + m_core->icount -= 3; break; case 0x1a: /* DIV */ if (RTVAL32) @@ -1902,7 +2620,7 @@ CPU_EXECUTE( mips3 ) LOVAL64 = (INT32)((INT32)RSVAL32 / (INT32)RTVAL32); HIVAL64 = (INT32)((INT32)RSVAL32 % (INT32)RTVAL32); } - mips3.core.icount -= 35; + m_core->icount -= 35; break; case 0x1b: /* DIVU */ if (RTVAL32) @@ -1910,19 +2628,19 @@ CPU_EXECUTE( mips3 ) LOVAL64 = (INT32)(RSVAL32 / RTVAL32); HIVAL64 = (INT32)(RSVAL32 % RTVAL32); } - mips3.core.icount -= 35; + m_core->icount -= 35; break; case 0x1c: /* DMULT */ temp64 = (INT64)RSVAL64 * (INT64)RTVAL64; LOVAL64 = temp64; HIVAL64 = (INT64)temp64 >> 63; - mips3.core.icount -= 7; + m_core->icount -= 7; break; case 0x1d: /* DMULTU */ temp64 = (UINT64)RSVAL64 * (UINT64)RTVAL64; LOVAL64 = temp64; HIVAL64 = 0; - mips3.core.icount -= 7; + m_core->icount -= 7; break; case 0x1e: /* DDIV */ if (RTVAL64) @@ -1930,7 +2648,7 @@ CPU_EXECUTE( mips3 ) LOVAL64 = (INT64)RSVAL64 / (INT64)RTVAL64; HIVAL64 = (INT64)RSVAL64 % (INT64)RTVAL64; } - mips3.core.icount -= 67; + m_core->icount -= 67; break; case 0x1f: /* DDIVU */ if (RTVAL64) @@ -1938,7 +2656,7 @@ CPU_EXECUTE( mips3 ) LOVAL64 = RSVAL64 / RTVAL64; HIVAL64 = RSVAL64 % RTVAL64; } - mips3.core.icount -= 67; + m_core->icount -= 67; break; case 0x20: /* ADD */ if (ENABLE_OVERFLOWS && RSVAL32 > ~RTVAL32) generate_exception(EXCEPTION_OVERFLOW, 1); @@ -1987,8 +2705,8 @@ CPU_EXECUTE( mips3 ) { case 0x00: /* BLTZ */ if ((INT64)RSVAL64 < 0) ADDPC(SIMMVAL); break; case 0x01: /* BGEZ */ if ((INT64)RSVAL64 >= 0) ADDPC(SIMMVAL); break; - case 0x02: /* BLTZL */ if ((INT64)RSVAL64 < 0) ADDPC(SIMMVAL); else mips3.core.pc += 4; break; - case 0x03: /* BGEZL */ if ((INT64)RSVAL64 >= 0) ADDPC(SIMMVAL); else mips3.core.pc += 4; break; + case 0x02: /* BLTZL */ if ((INT64)RSVAL64 < 0) ADDPC(SIMMVAL); else m_core->pc += 4; break; + case 0x03: /* BGEZL */ if ((INT64)RSVAL64 >= 0) ADDPC(SIMMVAL); else m_core->pc += 4; break; case 0x08: /* TGEI */ if ((INT64)RSVAL64 >= SIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break; case 0x09: /* TGEIU */ if (RSVAL64 >= UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break; case 0x0a: /* TLTI */ if ((INT64)RSVAL64 < SIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break; @@ -1997,8 +2715,8 @@ CPU_EXECUTE( mips3 ) case 0x0e: /* TNEI */ if (RSVAL64 != UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break; case 0x10: /* BLTZAL */ if ((INT64)RSVAL64 < 0) ADDPCL(SIMMVAL,31); break; case 0x11: /* BGEZAL */ if ((INT64)RSVAL64 >= 0) ADDPCL(SIMMVAL,31); break; - case 0x12: /* BLTZALL */ if ((INT64)RSVAL64 < 0) ADDPCL(SIMMVAL,31) else mips3.core.pc += 4; break; - case 0x13: /* BGEZALL */ if ((INT64)RSVAL64 >= 0) ADDPCL(SIMMVAL,31) else mips3.core.pc += 4; break; + case 0x12: /* BLTZALL */ if ((INT64)RSVAL64 < 0) ADDPCL(SIMMVAL,31) else m_core->pc += 4; break; + case 0x13: /* BGEZALL */ if ((INT64)RSVAL64 >= 0) ADDPCL(SIMMVAL,31) else m_core->pc += 4; break; default: /* ??? */ invalid_instruction(op); break; } break; @@ -2024,54 +2742,54 @@ CPU_EXECUTE( mips3 ) case 0x11: /* COP1 */ if (IS_FR0) handle_cop1_fr0(op); else handle_cop1_fr1(op); break; case 0x12: /* COP2 */ handle_cop2(op); break; case 0x13: /* COP1X - R5000 */if (IS_FR0) handle_cop1x_fr0(op); else handle_cop1x_fr1(op); break; - case 0x14: /* BEQL */ if (RSVAL64 == RTVAL64) ADDPC(SIMMVAL); else mips3.core.pc += 4; break; - case 0x15: /* BNEL */ if (RSVAL64 != RTVAL64) ADDPC(SIMMVAL); else mips3.core.pc += 4; break; - case 0x16: /* BLEZL */ if ((INT64)RSVAL64 <= 0) ADDPC(SIMMVAL); else mips3.core.pc += 4; break; - case 0x17: /* BGTZL */ if ((INT64)RSVAL64 > 0) ADDPC(SIMMVAL); else mips3.core.pc += 4; break; + case 0x14: /* BEQL */ if (RSVAL64 == RTVAL64) ADDPC(SIMMVAL); else m_core->pc += 4; break; + case 0x15: /* BNEL */ if (RSVAL64 != RTVAL64) ADDPC(SIMMVAL); else m_core->pc += 4; break; + case 0x16: /* BLEZL */ if ((INT64)RSVAL64 <= 0) ADDPC(SIMMVAL); else m_core->pc += 4; break; + case 0x17: /* BGTZL */ if ((INT64)RSVAL64 > 0) ADDPC(SIMMVAL); else m_core->pc += 4; break; case 0x18: /* DADDI */ if (ENABLE_OVERFLOWS && (INT64)RSVAL64 > ~SIMMVAL) generate_exception(EXCEPTION_OVERFLOW, 1); else if (RTREG) RTVAL64 = RSVAL64 + (INT64)SIMMVAL; break; case 0x19: /* DADDIU */ if (RTREG) RTVAL64 = RSVAL64 + (UINT64)SIMMVAL; break; - case 0x1a: /* LDL */ (*mips3.ldl)(op); break; - case 0x1b: /* LDR */ (*mips3.ldr)(op); break; + case 0x1a: /* LDL */ (this->*m_ldl)(op); break; + case 0x1b: /* LDR */ (this->*m_ldr)(op); break; case 0x1c: /* IDT-specific opcodes: mad/madu/mul on R4640/4650, msub on RC32364 */ switch (op & 0x1f) { case 2: /* MUL */ RDVAL64 = (INT32)((INT32)RSVAL32 * (INT32)RTVAL32); - mips3.core.icount -= 3; + m_core->icount -= 3; break; default: invalid_instruction(op); } break; case 0x20: /* LB */ if (RBYTE(SIMMVAL+RSVAL32, &temp) && RTREG) RTVAL64 = (INT8)temp; break; case 0x21: /* LH */ if (RHALF(SIMMVAL+RSVAL32, &temp) && RTREG) RTVAL64 = (INT16)temp; break; - case 0x22: /* LWL */ (*mips3.lwl)(op); break; + case 0x22: /* LWL */ (this->*m_lwl)(op); break; case 0x23: /* LW */ if (RWORD(SIMMVAL+RSVAL32, &temp) && RTREG) RTVAL64 = (INT32)temp; break; case 0x24: /* LBU */ if (RBYTE(SIMMVAL+RSVAL32, &temp) && RTREG) RTVAL64 = (UINT8)temp; break; case 0x25: /* LHU */ if (RHALF(SIMMVAL+RSVAL32, &temp) && RTREG) RTVAL64 = (UINT16)temp; break; - case 0x26: /* LWR */ (*mips3.lwr)(op); break; + case 0x26: /* LWR */ (this->*m_lwr)(op); break; case 0x27: /* LWU */ if (RWORD(SIMMVAL+RSVAL32, &temp) && RTREG) RTVAL64 = (UINT32)temp; break; case 0x28: /* SB */ WBYTE(SIMMVAL+RSVAL32, RTVAL32); break; case 0x29: /* SH */ WHALF(SIMMVAL+RSVAL32, RTVAL32); break; - case 0x2a: /* SWL */ (*mips3.swl)(op); break; + case 0x2a: /* SWL */ (this->*m_swl)(op); break; case 0x2b: /* SW */ WWORD(SIMMVAL+RSVAL32, RTVAL32); break; - case 0x2c: /* SDL */ (*mips3.sdl)(op); break; - case 0x2d: /* SDR */ (*mips3.sdr)(op); break; - case 0x2e: /* SWR */ (*mips3.swr)(op); break; + case 0x2c: /* SDL */ (this->*m_sdl)(op); break; + case 0x2d: /* SDR */ (this->*m_sdr)(op); break; + case 0x2e: /* SWR */ (this->*m_swr)(op); break; case 0x2f: /* CACHE */ /* effective no-op */ break; - case 0x30: /* LL */ if (RWORD(SIMMVAL+RSVAL32, &temp) && RTREG) RTVAL64 = (UINT32)temp; mips3.ll_value = RTVAL32; break; + case 0x30: /* LL */ if (RWORD(SIMMVAL+RSVAL32, &temp) && RTREG) RTVAL64 = (UINT32)temp; m_ll_value = RTVAL32; break; case 0x31: /* LWC1 */ if (RWORD(SIMMVAL+RSVAL32, &temp)) set_cop1_reg32(RTREG, temp); break; case 0x32: /* LWC2 */ if (RWORD(SIMMVAL+RSVAL32, &temp)) set_cop2_reg(RTREG, temp); break; case 0x33: /* PREF */ /* effective no-op */ break; - case 0x34: /* LLD */ if (RDOUBLE(SIMMVAL+RSVAL32, &temp64) && RTREG) RTVAL64 = temp64; mips3.lld_value = temp64; break; + case 0x34: /* LLD */ if (RDOUBLE(SIMMVAL+RSVAL32, &temp64) && RTREG) RTVAL64 = temp64; m_lld_value = temp64; break; case 0x35: /* LDC1 */ if (RDOUBLE(SIMMVAL+RSVAL32, &temp64)) set_cop1_reg64(RTREG, temp64); break; case 0x36: /* LDC2 */ if (RDOUBLE(SIMMVAL+RSVAL32, &temp64)) set_cop2_reg(RTREG, temp64); break; case 0x37: /* LD */ if (RDOUBLE(SIMMVAL+RSVAL32, &temp64) && RTREG) RTVAL64 = temp64; break; case 0x38: /* SC */ if (RWORD(SIMMVAL+RSVAL32, &temp) && RTREG) { - if (temp == mips3.ll_value) + if (temp == m_ll_value) { WWORD(SIMMVAL+RSVAL32, RTVAL32); RTVAL64 = (UINT32)1; @@ -2087,7 +2805,7 @@ CPU_EXECUTE( mips3 ) case 0x3b: /* SWC3 */ invalid_instruction(op); break; case 0x3c: /* SCD */ if (RDOUBLE(SIMMVAL+RSVAL32, &temp64) && RTREG) { - if (temp64 == mips3.lld_value) + if (temp64 == m_lld_value) { WDOUBLE(SIMMVAL+RSVAL32, RTVAL64); RTVAL64 = 1; @@ -2103,12 +2821,12 @@ CPU_EXECUTE( mips3 ) case 0x3f: /* SD */ WDOUBLE(SIMMVAL+RSVAL32, RTVAL64); break; default: /* ??? */ invalid_instruction(op); break; } - mips3.core.icount--; + m_core->icount--; - } while (mips3.core.icount > 0 || mips3.nextpc != ~0); + } while (m_core->icount > 0 || m_nextpc != ~0); - mips3.core.icount -= mips3.interrupt_cycles; - mips3.interrupt_cycles = 0; + m_core->icount -= m_interrupt_cycles; + m_interrupt_cycles = 0; } @@ -2117,7 +2835,7 @@ CPU_EXECUTE( mips3 ) COMPLEX OPCODE IMPLEMENTATIONS ***************************************************************************/ -static void lwl_be(UINT32 op) +void mips3_device::lwl_be(UINT32 op) { offs_t offs = SIMMVAL + RSVAL32; int shift = 8 * (offs & 3); @@ -2128,7 +2846,7 @@ static void lwl_be(UINT32 op) RTVAL64 = (INT32)((RTVAL32 & ~mask) | (temp << shift)); } -static void lwr_be(UINT32 op) +void mips3_device::lwr_be(UINT32 op) { offs_t offs = SIMMVAL + RSVAL32; int shift = 8 * (~offs & 3); @@ -2139,7 +2857,7 @@ static void lwr_be(UINT32 op) RTVAL64 = (INT32)((RTVAL32 & ~mask) | (temp >> shift)); } -static void ldl_be(UINT32 op) +void mips3_device::ldl_be(UINT32 op) { offs_t offs = SIMMVAL + RSVAL32; int shift = 8 * (offs & 7); @@ -2150,7 +2868,7 @@ static void ldl_be(UINT32 op) RTVAL64 = (RTVAL64 & ~mask) | (temp << shift); } -static void ldr_be(UINT32 op) +void mips3_device::ldr_be(UINT32 op) { offs_t offs = SIMMVAL + RSVAL32; int shift = 8 * (~offs & 7); @@ -2161,7 +2879,7 @@ static void ldr_be(UINT32 op) RTVAL64 = (RTVAL64 & ~mask) | (temp >> shift); } -static void swl_be(UINT32 op) +void mips3_device::swl_be(UINT32 op) { offs_t offs = SIMMVAL + RSVAL32; int shift = 8 * (offs & 3); @@ -2169,7 +2887,7 @@ static void swl_be(UINT32 op) WWORD_MASKED(offs & ~3, RTVAL32 >> shift, mask); } -static void swr_be(UINT32 op) +void mips3_device::swr_be(UINT32 op) { offs_t offs = SIMMVAL + RSVAL32; int shift = 8 * (~offs & 3); @@ -2177,7 +2895,7 @@ static void swr_be(UINT32 op) WWORD_MASKED(offs & ~3, RTVAL32 << shift, mask); } -static void sdl_be(UINT32 op) +void mips3_device::sdl_be(UINT32 op) { offs_t offs = SIMMVAL + RSVAL32; int shift = 8 * (offs & 7); @@ -2185,7 +2903,7 @@ static void sdl_be(UINT32 op) WDOUBLE_MASKED(offs & ~7, RTVAL64 >> shift, mask); } -static void sdr_be(UINT32 op) +void mips3_device::sdr_be(UINT32 op) { offs_t offs = SIMMVAL + RSVAL32; int shift = 8 * (~offs & 7); @@ -2195,7 +2913,7 @@ static void sdr_be(UINT32 op) -static void lwl_le(UINT32 op) +void mips3_device::lwl_le(UINT32 op) { offs_t offs = SIMMVAL + RSVAL32; int shift = 8 * (~offs & 3); @@ -2206,7 +2924,7 @@ static void lwl_le(UINT32 op) RTVAL64 = (INT32)((RTVAL32 & ~mask) | (temp << shift)); } -static void lwr_le(UINT32 op) +void mips3_device::lwr_le(UINT32 op) { offs_t offs = SIMMVAL + RSVAL32; int shift = 8 * (offs & 3); @@ -2217,7 +2935,7 @@ static void lwr_le(UINT32 op) RTVAL64 = (INT32)((RTVAL32 & ~mask) | (temp >> shift)); } -static void ldl_le(UINT32 op) +void mips3_device::ldl_le(UINT32 op) { offs_t offs = SIMMVAL + RSVAL32; int shift = 8 * (~offs & 7); @@ -2228,7 +2946,7 @@ static void ldl_le(UINT32 op) RTVAL64 = (RTVAL64 & ~mask) | (temp << shift); } -static void ldr_le(UINT32 op) +void mips3_device::ldr_le(UINT32 op) { offs_t offs = SIMMVAL + RSVAL32; int shift = 8 * (offs & 7); @@ -2239,7 +2957,7 @@ static void ldr_le(UINT32 op) RTVAL64 = (RTVAL64 & ~mask) | (temp >> shift); } -static void swl_le(UINT32 op) +void mips3_device::swl_le(UINT32 op) { offs_t offs = SIMMVAL + RSVAL32; int shift = 8 * (~offs & 3); @@ -2247,7 +2965,7 @@ static void swl_le(UINT32 op) WWORD_MASKED(offs & ~3, RTVAL32 >> shift, mask); } -static void swr_le(UINT32 op) +void mips3_device::swr_le(UINT32 op) { offs_t offs = SIMMVAL + RSVAL32; int shift = 8 * (offs & 3); @@ -2255,7 +2973,7 @@ static void swr_le(UINT32 op) WWORD_MASKED(offs & ~3, RTVAL32 << shift, mask); } -static void sdl_le(UINT32 op) +void mips3_device::sdl_le(UINT32 op) { offs_t offs = SIMMVAL + RSVAL32; int shift = 8 * (~offs & 7); @@ -2263,7 +2981,7 @@ static void sdl_le(UINT32 op) WDOUBLE_MASKED(offs & ~7, RTVAL64 >> shift, mask); } -static void sdr_le(UINT32 op) +void mips3_device::sdr_le(UINT32 op) { offs_t offs = SIMMVAL + RSVAL32; int shift = 8 * (offs & 7); @@ -2271,511 +2989,3 @@ static void sdr_le(UINT32 op) WDOUBLE_MASKED(offs & ~7, RTVAL64 << shift, mask); } - - -/*************************************************************************** - GENERIC GET/SET INFO -***************************************************************************/ - -static CPU_SET_INFO( mips3 ) -{ - /* everything is handled generically here */ - mips3com_set_info(&mips3.core, state, info); -} - - -static CPU_GET_INFO( mips3 ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(mips3); break; - case CPUINFO_INT_PREVIOUSPC: info->i = mips3.ppc; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(mips3); break; - case CPUINFO_FCT_INIT: /* provided per-CPU */ break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(mips3); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(mips3); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(mips3); break; - case CPUINFO_FCT_TRANSLATE: info->translate = CPU_TRANSLATE_NAME(mips3); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - - /* --- everything else is handled generically --- */ - default: mips3com_get_info(&mips3.core, state, info); break; - } -} - - - -/*************************************************************************** - NEC VR4300 VARIANTS -***************************************************************************/ - -// NEC VR4300 series is MIPS III with 32-bit address bus and slightly custom COP0/TLB -static CPU_INIT( vr4300be ) -{ - mips3com_init(&mips3.core, MIPS3_TYPE_VR4300, TRUE, device, irqcallback); - mips3.tlb_table = vtlb_table(mips3.core.vtlb); -} - -static CPU_INIT( vr4300le ) -{ - mips3com_init(&mips3.core, MIPS3_TYPE_VR4300, FALSE, device, irqcallback); - mips3.tlb_table = vtlb_table(mips3.core.vtlb); -} - -CPU_GET_INFO( vr4300be_int ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(vr4300be); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "VR4300 (big)"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "vr4300be"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -CPU_GET_INFO( vr4300le_int ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(vr4300le); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "VR4300 (little)"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "vr4300le"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -// VR4310 = VR4300 with different speed bin -CPU_GET_INFO( vr4310be_int ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(vr4300be); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "VR4310 (big)"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "vr4310be"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -CPU_GET_INFO( vr4310le_int ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(vr4300le); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "VR4310 (little)"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "vr4310le"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - - -/*************************************************************************** - R4600 VARIANTS -***************************************************************************/ - -static CPU_INIT( r4600be ) -{ - mips3com_init(&mips3.core, MIPS3_TYPE_R4600, TRUE, device, irqcallback); - mips3.tlb_table = vtlb_table(mips3.core.vtlb); -} - -static CPU_INIT( r4600le ) -{ - mips3com_init(&mips3.core, MIPS3_TYPE_R4600, FALSE, device, irqcallback); - mips3.tlb_table = vtlb_table(mips3.core.vtlb); -} - -CPU_GET_INFO( r4600be_int ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(r4600be); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "R4600 (big)"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "r4600be"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -CPU_GET_INFO( r4600le_int ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(r4600le); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "R4600 (little)"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "r4600le"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - - - -/*************************************************************************** - R4650 VARIANTS -***************************************************************************/ - -static CPU_INIT( r4650be ) -{ - mips3com_init(&mips3.core, MIPS3_TYPE_R4650, TRUE, device, irqcallback); - mips3.tlb_table = vtlb_table(mips3.core.vtlb); -} - -static CPU_INIT( r4650le ) -{ - mips3com_init(&mips3.core, MIPS3_TYPE_R4650, FALSE, device, irqcallback); - mips3.tlb_table = vtlb_table(mips3.core.vtlb); -} - -CPU_GET_INFO( r4650be_int ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(r4650be); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "IDT R4650 (big)"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "r4650be"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -CPU_GET_INFO( r4650le_int ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(r4650le); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "IDT R4650 (little)"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "r4650le"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - - - -/*************************************************************************** - R4700 VARIANTS -***************************************************************************/ - -static CPU_INIT( r4700be ) -{ - mips3com_init(&mips3.core, MIPS3_TYPE_R4700, TRUE, device, irqcallback); - mips3.tlb_table = vtlb_table(mips3.core.vtlb); -} - -static CPU_INIT( r4700le ) -{ - mips3com_init(&mips3.core, MIPS3_TYPE_R4700, FALSE, device, irqcallback); - mips3.tlb_table = vtlb_table(mips3.core.vtlb); -} - -CPU_GET_INFO( r4700be_int ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(r4700be); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "R4700 (big)"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "r4700be"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - - -CPU_GET_INFO( r4700le_int ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(r4700le); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "R4700 (little)"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "r4700le"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - - - -/*************************************************************************** - R5000 VARIANTS -***************************************************************************/ - -static CPU_INIT( r5000be ) -{ - mips3com_init(&mips3.core, MIPS3_TYPE_R5000, TRUE, device, irqcallback); - mips3.tlb_table = vtlb_table(mips3.core.vtlb); -} - -static CPU_INIT( r5000le ) -{ - mips3com_init(&mips3.core, MIPS3_TYPE_R5000, FALSE, device, irqcallback); - mips3.tlb_table = vtlb_table(mips3.core.vtlb); -} - -CPU_GET_INFO( r5000be_int ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(r5000be); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "R5000 (big)"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "r5000be"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -CPU_GET_INFO( r5000le_int ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(r5000le); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "R5000 (little)"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "r5000le"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - - - -/*************************************************************************** - QED5271 VARIANTS -***************************************************************************/ - -static CPU_INIT( qed5271be ) -{ - mips3com_init(&mips3.core, MIPS3_TYPE_QED5271, TRUE, device, irqcallback); - mips3.tlb_table = vtlb_table(mips3.core.vtlb); -} - -static CPU_INIT( qed5271le ) -{ - mips3com_init(&mips3.core, MIPS3_TYPE_QED5271, FALSE, device, irqcallback); - mips3.tlb_table = vtlb_table(mips3.core.vtlb); -} - -CPU_GET_INFO( qed5271be_int ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(qed5271be); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "QED5271 (big)"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "qed5271be"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -CPU_GET_INFO( qed5271le_int ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(qed5271le); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "QED5271 (little)"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "qed5271le"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - - - -/*************************************************************************** - RM7000 VARIANTS -***************************************************************************/ - -static CPU_INIT( rm7000be ) -{ - mips3com_init(&mips3.core, MIPS3_TYPE_RM7000, TRUE, device, irqcallback); - mips3.tlb_table = vtlb_table(mips3.core.vtlb); -} - -static CPU_INIT( rm7000le ) -{ - mips3com_init(&mips3.core, MIPS3_TYPE_RM7000, FALSE, device, irqcallback); - mips3.tlb_table = vtlb_table(mips3.core.vtlb); -} - -CPU_GET_INFO( rm7000be_int ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(rm7000be); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "RM7000 (big)"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "rm7000be"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -CPU_GET_INFO( rm7000le_int ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(rm7000le); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "RM7000 (little)"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "rm7000le"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -DEFINE_LEGACY_CPU_DEVICE(VR4300BE_INT, vr4300be_int); -DEFINE_LEGACY_CPU_DEVICE(VR4300LE_INT, vr4300le_int); -DEFINE_LEGACY_CPU_DEVICE(VR4310BE_INT, vr4310be_int); -DEFINE_LEGACY_CPU_DEVICE(VR4310LE_INT, vr4310le_int); - -DEFINE_LEGACY_CPU_DEVICE(R4600BE_INT, r4600be_int); -DEFINE_LEGACY_CPU_DEVICE(R4600LE_INT, r4600le_int); - -DEFINE_LEGACY_CPU_DEVICE(R4650BE_INT, r4650be_int); -DEFINE_LEGACY_CPU_DEVICE(R4650LE_INT, r4650le_int); - -DEFINE_LEGACY_CPU_DEVICE(R4700BE_INT, r4700be_int); -DEFINE_LEGACY_CPU_DEVICE(R4700LE_INT, r4700le_int); - -DEFINE_LEGACY_CPU_DEVICE(R5000BE_INT, r5000be_int); -DEFINE_LEGACY_CPU_DEVICE(R5000LE_INT, r5000le_int); - -DEFINE_LEGACY_CPU_DEVICE(QED5271BE_INT, qed5271be_int); -DEFINE_LEGACY_CPU_DEVICE(QED5271LE_INT, qed5271le_int); - -DEFINE_LEGACY_CPU_DEVICE(RM7000BE_INT, rm7000be_int); -DEFINE_LEGACY_CPU_DEVICE(RM7000LE_INT, rm7000le_int); - -const device_type VR4300BE = &legacy_device_creator_drc<vr4300be_int_device, vr4300be_drc_device>; -const device_type VR4300LE = &legacy_device_creator_drc<vr4300le_int_device, vr4300le_drc_device>; -const device_type VR4310BE = &legacy_device_creator_drc<vr4310be_int_device, vr4310be_drc_device>; -const device_type VR4310LE = &legacy_device_creator_drc<vr4310le_int_device, vr4310le_drc_device>; -const device_type R4600BE = &legacy_device_creator_drc<r4600be_int_device, r4600be_drc_device>; -const device_type R4600LE = &legacy_device_creator_drc<r4600le_int_device, r4600le_drc_device>; -const device_type R4650BE = &legacy_device_creator_drc<r4650be_int_device, r4650be_drc_device>; -const device_type R4650LE = &legacy_device_creator_drc<r4650le_int_device, r4650le_drc_device>; -const device_type R4700BE = &legacy_device_creator_drc<r4700be_int_device, r4700be_drc_device>; -const device_type R4700LE = &legacy_device_creator_drc<r4700le_int_device, r4700le_drc_device>; -const device_type R5000BE = &legacy_device_creator_drc<r5000be_int_device, r5000be_drc_device>; -const device_type R5000LE = &legacy_device_creator_drc<r5000le_int_device, r5000le_drc_device>; -const device_type QED5271BE = &legacy_device_creator_drc<qed5271be_int_device, qed5271be_drc_device>; -const device_type QED5271LE = &legacy_device_creator_drc<qed5271le_int_device, qed5271le_drc_device>; -const device_type RM7000BE = &legacy_device_creator_drc<rm7000be_int_device, rm7000be_drc_device>; -const device_type RM7000LE = &legacy_device_creator_drc<rm7000le_int_device, rm7000le_drc_device>; diff --git a/src/emu/cpu/mips/mips3.h b/src/emu/cpu/mips/mips3.h index c72f8f71ee6..3f4826ef54c 100644 --- a/src/emu/cpu/mips/mips3.h +++ b/src/emu/cpu/mips/mips3.h @@ -15,6 +15,31 @@ #define __MIPS3_H__ +#include "cpu/vtlb.h" +#include "cpu/drcfe.h" +#include "cpu/drcuml.h" +#include "cpu/drcumlsh.h" + + +// NEC VR4300 series is MIPS III with 32-bit address bus and slightly custom COP0/TLB +extern const device_type VR4300BE; +extern const device_type VR4300LE; +// VR4310 = VR4300 with different speed bin +extern const device_type VR4310BE; +extern const device_type VR4310LE; +extern const device_type R4600BE; +extern const device_type R4600LE; +extern const device_type R4650BE; +extern const device_type R4650LE; +extern const device_type R4700BE; +extern const device_type R4700LE; +extern const device_type R5000BE; +extern const device_type R5000LE; +extern const device_type QED5271BE; +extern const device_type QED5271LE; +extern const device_type RM7000BE; +extern const device_type RM7000LE; + /*************************************************************************** REGISTER ENUMERATION @@ -208,85 +233,508 @@ enum STRUCTURES ***************************************************************************/ -struct mips3_config +/* MIPS3 TLB entry */ +struct mips3_tlb_entry { - size_t icache; /* code cache size */ - size_t dcache; /* data cache size */ - UINT32 system_clock; /* system clock rate */ + UINT64 page_mask; + UINT64 entry_hi; + UINT64 entry_lo[2]; }; +/* internal compiler state */ +struct compiler_state +{ + UINT32 cycles; /* accumulated cycles */ + UINT8 checkints; /* need to check interrupts before next instruction */ + UINT8 checksoftints; /* need to check software interrupts before next instruction */ + uml::code_label labelnum; /* index for local labels */ +}; +#define MIPS3_MAX_TLB_ENTRIES 48 -/*************************************************************************** - PUBLIC FUNCTIONS -***************************************************************************/ +#define MCFG_MIPS3_ICACHE_SIZE(_size) \ + mips3_device::set_icache_size(*device, _size); -void mips3drc_set_options(device_t *device, UINT32 options); -void mips3drc_add_fastram(device_t *device, offs_t start, offs_t end, UINT8 readonly, void *base); -void mips3drc_add_hotspot(device_t *device, offs_t pc, UINT32 opcode, UINT32 cycles); +#define MCFG_MIPS3_DCACHE_SIZE(_size) \ + mips3_device::set_dcache_size(*device, _size); -DECLARE_LEGACY_CPU_DEVICE(VR4300BE_INT, vr4300be_int); -DECLARE_LEGACY_CPU_DEVICE(VR4300LE_INT, vr4300le_int); -DECLARE_LEGACY_CPU_DEVICE(VR4310BE_INT, vr4310be_int); -DECLARE_LEGACY_CPU_DEVICE(VR4310LE_INT, vr4310le_int); +#define MCFG_MIPS3_SYSTEM_CLOCK(_clock) \ + mips3_device::set_system_clock(*device, _clock); -DECLARE_LEGACY_CPU_DEVICE(R4600BE_INT, r4600be_int); -DECLARE_LEGACY_CPU_DEVICE(R4600LE_INT, r4600le_int); -DECLARE_LEGACY_CPU_DEVICE(R4650BE_INT, r4650be_int); -DECLARE_LEGACY_CPU_DEVICE(R4650LE_INT, r4650le_int); +class mips3_frontend; -DECLARE_LEGACY_CPU_DEVICE(R4700BE_INT, r4700be_int); -DECLARE_LEGACY_CPU_DEVICE(R4700LE_INT, r4700le_int); +class mips3_device : public cpu_device +{ + friend class mips3_frontend; + +protected: + /* MIPS flavors */ + enum mips3_flavor + { + /* MIPS III variants */ + MIPS3_TYPE_MIPS_III, + MIPS3_TYPE_VR4300, + MIPS3_TYPE_R4600, + MIPS3_TYPE_R4650, + MIPS3_TYPE_R4700, + + /* MIPS IV variants */ + MIPS3_TYPE_MIPS_IV, + MIPS3_TYPE_R5000, + MIPS3_TYPE_QED5271, + MIPS3_TYPE_RM7000 + }; + +public: + // construction/destruction + mips3_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, mips3_flavor flavor, endianness_t endiannes); + + static void set_icache_size(device_t &device, size_t icache_size) { downcast<mips3_device &>(device).c_icache_size = icache_size; } + static void set_dcache_size(device_t &device, size_t dcache_size) { downcast<mips3_device &>(device).c_dcache_size = dcache_size; } + static void set_system_clock(device_t &device, UINT32 system_clock) { downcast<mips3_device &>(device).c_system_clock = system_clock; } + + TIMER_CALLBACK_MEMBER(compare_int_callback); + + void mips3drc_set_options(UINT32 options); + void mips3drc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base); + void mips3drc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles); + +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + virtual void device_stop(); + + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const { return 1; } + virtual UINT32 execute_max_cycles() const { return 40; } + virtual UINT32 execute_input_lines() const { return 6; } + virtual void execute_run(); + virtual void execute_set_input(int inputnum, int state); + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; } + virtual bool memory_translate(address_spacenum spacenum, int intention, offs_t &address); + + // device_state_interface overrides + virtual void state_export(const device_state_entry &entry); + void state_string_export(const device_state_entry &entry, astring &string); + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const { return 4; } + virtual UINT32 disasm_max_opcode_bytes() const { return 4; } + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + +private: + struct internal_mips3_state + { + /* core registers */ + UINT32 pc; + int icount; + UINT64 r[35]; + + /* COP registers */ + UINT64 cpr[3][32]; + UINT64 ccr[3][32]; + UINT32 llbit; + + UINT32 mode; /* current global mode */ + + /* parameters for subroutines */ + UINT64 numcycles; /* return value from gettotalcycles */ + const char * format; /* format string for print_debug */ + UINT32 arg0; /* print_debug argument 1 */ + UINT32 arg1; /* print_debug argument 2 */ + + UINT64 count_zero_time; + UINT32 compare_armed; + UINT32 jmpdest; /* destination jump target */ + + }; + + address_space_config m_program_config; + mips3_flavor m_flavor; + + /* core state */ + internal_mips3_state *m_core; + + /* internal stuff */ + UINT32 m_ppc; + UINT32 m_nextpc; + UINT32 m_pcbase; + UINT8 m_cf[4][8]; + int m_op; + int m_interrupt_cycles; + UINT32 m_ll_value; + UINT64 m_lld_value; + UINT32 m_badcop_value; + const vtlb_entry *m_tlb_table; + + /* endian-dependent load/store */ + typedef void (mips3_device::*loadstore_func)(UINT32 op); + loadstore_func m_lwl; + loadstore_func m_lwr; + loadstore_func m_swl; + loadstore_func m_swr; + loadstore_func m_ldl; + loadstore_func m_ldr; + loadstore_func m_sdl; + loadstore_func m_sdr; + + address_space *m_program; + direct_read_data *m_direct; + UINT32 c_system_clock; + UINT32 m_cpu_clock; + emu_timer * m_compare_int_timer; + + /* derived info based on flavor */ + UINT32 m_pfnmask; + UINT8 m_tlbentries; + + /* memory accesses */ + bool m_bigendian; + data_accessors m_memory; + + /* cache memory */ + size_t c_icache_size; + size_t c_dcache_size; + + /* MMU */ + vtlb_state * m_vtlb; + mips3_tlb_entry m_tlb[MIPS3_MAX_TLB_ENTRIES]; + + UINT64 m_debugger_temp; + + /* core state */ + drc_cache m_cache; /* pointer to the DRC code cache */ + drcuml_state * m_drcuml; /* DRC UML generator state */ + mips3_frontend * m_drcfe; /* pointer to the DRC front-end state */ + UINT32 m_drcoptions; /* configurable DRC options */ + + /* internal stuff */ + UINT8 m_cache_dirty; /* true if we need to flush the cache */ + + /* tables */ + UINT8 m_fpmode[4]; /* FPU mode table */ + + /* register mappings */ + uml::parameter m_regmap[34]; /* parameter to register mappings for all 32 integer registers */ + uml::parameter m_regmaplo[34]; /* parameter to register mappings for all 32 integer registers */ + + /* subroutines */ + uml::code_handle * m_entry; /* entry point */ + uml::code_handle * m_nocode; /* nocode exception handler */ + uml::code_handle * m_out_of_cycles; /* out of cycles exception handler */ + uml::code_handle * m_tlb_mismatch; /* tlb mismatch handler */ + uml::code_handle * m_read8[3]; /* read byte */ + uml::code_handle * m_write8[3]; /* write byte */ + uml::code_handle * m_read16[3]; /* read half */ + uml::code_handle * m_write16[3]; /* write half */ + uml::code_handle * m_read32[3]; /* read word */ + uml::code_handle * m_read32mask[3]; /* read word masked */ + uml::code_handle * m_write32[3]; /* write word */ + uml::code_handle * m_write32mask[3]; /* write word masked */ + uml::code_handle * m_read64[3]; /* read double */ + uml::code_handle * m_read64mask[3]; /* read double masked */ + uml::code_handle * m_write64[3]; /* write double */ + uml::code_handle * m_write64mask[3]; /* write double masked */ + uml::code_handle * m_exception[18/*EXCEPTION_COUNT*/]; /* array of exception handlers */ + uml::code_handle * m_exception_norecover[18/*EXCEPTION_COUNT*/]; /* array of no-recover exception handlers */ + + /* fast RAM */ + UINT32 m_fastram_select; + struct + { + offs_t start; /* start of the RAM block */ + offs_t end; /* end of the RAM block */ + UINT8 readonly; /* TRUE if read-only */ + void * base; /* base in memory where the RAM lives */ + } m_fastram[MIPS3_MAX_FASTRAM]; + + /* hotspots */ + UINT32 m_hotspot_select; + struct + { + offs_t pc; /* PC to consider */ + UINT32 opcode; /* required opcode at that PC */ + UINT32 cycles; /* number of cycles to eat when hit */ + } m_hotspot[MIPS3_MAX_HOTSPOTS]; + bool m_isdrc; + + + void generate_exception(int exception, int backup); + void generate_tlb_exception(int exception, offs_t address); + void invalid_instruction(UINT32 op); + void check_irqs(); +public: + void mips3com_update_cycle_counting(); + void mips3com_asid_changed(); + void mips3com_tlbr(); + void mips3com_tlbwi(); + void mips3com_tlbwr(); + void mips3com_tlbp(); +private: + UINT32 compute_config_register(); + UINT32 compute_prid_register(); + void tlb_map_entry(int tlbindex); + void tlb_write_common(int tlbindex); + int RBYTE(offs_t address, UINT32 *result); + int RHALF(offs_t address, UINT32 *result); + int RWORD(offs_t address, UINT32 *result); + int RWORD_MASKED(offs_t address, UINT32 *result, UINT32 mem_mask); + int RDOUBLE(offs_t address, UINT64 *result); + int RDOUBLE_MASKED(offs_t address, UINT64 *result, UINT64 mem_mask); + void WBYTE(offs_t address, UINT8 data); + void WHALF(offs_t address, UINT16 data); + void WWORD(offs_t address, UINT32 data); + void WWORD_MASKED(offs_t address, UINT32 data, UINT32 mem_mask); + void WDOUBLE(offs_t address, UINT64 data); + void WDOUBLE_MASKED(offs_t address, UINT64 data, UINT64 mem_mask); + UINT64 get_cop0_reg(int idx); + void set_cop0_reg(int idx, UINT64 val); + UINT64 get_cop0_creg(int idx); + void set_cop0_creg(int idx, UINT64 val); + void handle_cop0(UINT32 op); + UINT32 get_cop1_reg32(int idx); + UINT64 get_cop1_reg64(int idx); + void set_cop1_reg32(int idx, UINT32 val); + void set_cop1_reg64(int idx, UINT64 val); + UINT64 get_cop1_creg(int idx); + void set_cop1_creg(int idx, UINT64 val); + void handle_cop1_fr0(UINT32 op); + void handle_cop1_fr1(UINT32 op); + void handle_cop1x_fr0(UINT32 op); + void handle_cop1x_fr1(UINT32 op); + UINT64 get_cop2_reg(int idx); + void set_cop2_reg(int idx, UINT64 val); + UINT64 get_cop2_creg(int idx); + void set_cop2_creg(int idx, UINT64 val); + void handle_cop2(UINT32 op); + void lwl_be(UINT32 op); + void lwr_be(UINT32 op); + void ldl_be(UINT32 op); + void ldr_be(UINT32 op); + void swl_be(UINT32 op); + void swr_be(UINT32 op); + void sdl_be(UINT32 op); + void sdr_be(UINT32 op); + void lwl_le(UINT32 op); + void lwr_le(UINT32 op); + void ldl_le(UINT32 op); + void ldr_le(UINT32 op); + void swl_le(UINT32 op); + void swr_le(UINT32 op); + void sdl_le(UINT32 op); + void sdr_le(UINT32 op); + void load_fast_iregs(drcuml_block *block); + void save_fast_iregs(drcuml_block *block); + void code_flush_cache(); + void code_compile_block(UINT8 mode, offs_t pc); +public: + void func_get_cycles(); + void func_printf_exception(); + void func_printf_debug(); + void func_printf_probe(); + void func_unimplemented(); +private: + void static_generate_entry_point(); + void static_generate_nocode_handler(); + void static_generate_out_of_cycles(); + void static_generate_tlb_mismatch(); + void static_generate_exception(UINT8 exception, int recover, const char *name); + void static_generate_memory_accessor(int mode, int size, int iswrite, int ismasked, const char *name, uml::code_handle **handleptr); + void generate_update_mode(drcuml_block *block); + void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception); + void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast); + void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); + void generate_delay_slot_and_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 linkreg); + int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); + int generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); + int generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); + int generate_idt(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); + int generate_set_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 reg); + int generate_get_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 reg); + int generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); + int generate_cop1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); + int generate_cop1x(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); + void log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op); + const char *log_desc_flags_to_string(UINT32 flags); + void log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist); + void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent); -DECLARE_LEGACY_CPU_DEVICE(R5000BE_INT, r5000be_int); -DECLARE_LEGACY_CPU_DEVICE(R5000LE_INT, r5000le_int); +}; -DECLARE_LEGACY_CPU_DEVICE(QED5271BE_INT, qed5271be_int); -DECLARE_LEGACY_CPU_DEVICE(QED5271LE_INT, qed5271le_int); -DECLARE_LEGACY_CPU_DEVICE(RM7000BE_INT, rm7000be_int); -DECLARE_LEGACY_CPU_DEVICE(RM7000LE_INT, rm7000le_int); +class vr4300be_device : public mips3_device +{ +public: + // construction/destruction + vr4300be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mips3_device(mconfig, VR4300BE, "VR4300 (big)", tag, owner, clock, "vr4300be", MIPS3_TYPE_VR4300, ENDIANNESS_BIG) + { } +}; -DECLARE_LEGACY_CPU_DEVICE(VR4300BE_DRC, vr4300be_drc); -DECLARE_LEGACY_CPU_DEVICE(VR4300LE_DRC, vr4300le_drc); -DECLARE_LEGACY_CPU_DEVICE(VR4310BE_DRC, vr4310be_drc); -DECLARE_LEGACY_CPU_DEVICE(VR4310LE_DRC, vr4310le_drc); +class vr4300le_device : public mips3_device +{ +public: + // construction/destruction + vr4300le_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mips3_device(mconfig, VR4300LE, "VR4300 (little)", tag, owner, clock, "vr4300le", MIPS3_TYPE_VR4300, ENDIANNESS_LITTLE) + { } +}; -DECLARE_LEGACY_CPU_DEVICE(R4600BE_DRC, r4600be_drc); -DECLARE_LEGACY_CPU_DEVICE(R4600LE_DRC, r4600le_drc); +class vr4310be_device : public mips3_device +{ +public: + // construction/destruction + vr4310be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mips3_device(mconfig, VR4310BE, "VR4310 (big)", tag, owner, clock, "vr4310be", MIPS3_TYPE_VR4300, ENDIANNESS_BIG) + { } +}; -DECLARE_LEGACY_CPU_DEVICE(R4650BE_DRC, r4650be_drc); -DECLARE_LEGACY_CPU_DEVICE(R4650LE_DRC, r4650le_drc); +class vr4310le_device : public mips3_device +{ +public: + // construction/destruction + vr4310le_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mips3_device(mconfig, VR4310LE, "VR4310 (little)", tag, owner, clock, "vr4310le", MIPS3_TYPE_VR4300, ENDIANNESS_LITTLE) + { } +}; -DECLARE_LEGACY_CPU_DEVICE(R4700BE_DRC, r4700be_drc); -DECLARE_LEGACY_CPU_DEVICE(R4700LE_DRC, r4700le_drc); +class r4600be_device : public mips3_device +{ +public: + // construction/destruction + r4600be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mips3_device(mconfig, R4600BE, "R4600 (big)", tag, owner, clock, "r4600be", MIPS3_TYPE_R4600, ENDIANNESS_BIG) + { } +}; -DECLARE_LEGACY_CPU_DEVICE(R5000BE_DRC, r5000be_drc); -DECLARE_LEGACY_CPU_DEVICE(R5000LE_DRC, r5000le_drc); +class r4600le_device : public mips3_device +{ +public: + // construction/destruction + r4600le_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mips3_device(mconfig, R4600LE, "R4600 (little)", tag, owner, clock, "r4600le", MIPS3_TYPE_R4600, ENDIANNESS_LITTLE) + { } +}; -DECLARE_LEGACY_CPU_DEVICE(QED5271BE_DRC, qed5271be_drc); -DECLARE_LEGACY_CPU_DEVICE(QED5271LE_DRC, qed5271le_drc); +class r4650be_device : public mips3_device +{ +public: + // construction/destruction + r4650be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mips3_device(mconfig, R4650BE, "IDT R4650 (big)", tag, owner, clock, "r4650be", MIPS3_TYPE_R4650, ENDIANNESS_BIG) + { } +}; -DECLARE_LEGACY_CPU_DEVICE(RM7000BE_DRC, rm7000be_drc); -DECLARE_LEGACY_CPU_DEVICE(RM7000LE_DRC, rm7000le_drc); +class r4650le_device : public mips3_device +{ +public: + // construction/destruction + r4650le_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mips3_device(mconfig, R4650LE, "IDT R4650 (little)", tag, owner, clock, "r4650le", MIPS3_TYPE_R4650, ENDIANNESS_LITTLE) + { } +}; -extern const device_type VR4300BE; -extern const device_type VR4300LE; -extern const device_type VR4310BE; -extern const device_type VR4310LE; -extern const device_type R4600BE; -extern const device_type R4600LE; -extern const device_type R4650BE; -extern const device_type R4650LE; -extern const device_type R4700BE; -extern const device_type R4700LE; -extern const device_type R5000BE; -extern const device_type R5000LE; -extern const device_type QED5271BE; -extern const device_type QED5271LE; -extern const device_type RM7000BE; -extern const device_type RM7000LE; +class r4700be_device : public mips3_device +{ +public: + // construction/destruction + r4700be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mips3_device(mconfig, R4700BE, "R4700 (big)", tag, owner, clock, "r4700be", MIPS3_TYPE_R4700, ENDIANNESS_BIG) + { } +}; + +class r4700le_device : public mips3_device +{ +public: + // construction/destruction + r4700le_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mips3_device(mconfig, R4700LE, "R4700 (little)", tag, owner, clock, "r4700le", MIPS3_TYPE_R4700, ENDIANNESS_LITTLE) + { } +}; + +class r5000be_device : public mips3_device +{ +public: + // construction/destruction + r5000be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mips3_device(mconfig, R5000BE, "R5000 (big)", tag, owner, clock, "r5000be", MIPS3_TYPE_R5000, ENDIANNESS_BIG) + { } +}; + +class r5000le_device : public mips3_device +{ +public: + // construction/destruction + r5000le_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mips3_device(mconfig, R5000LE, "R5000 (little)", tag, owner, clock, "r5000le", MIPS3_TYPE_R5000, ENDIANNESS_LITTLE) + { } +}; + +class qed5271be_device : public mips3_device +{ +public: + // construction/destruction + qed5271be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mips3_device(mconfig, QED5271BE, "QED5271 (big)", tag, owner, clock, "qed5271be", MIPS3_TYPE_QED5271, ENDIANNESS_BIG) + { } +}; + +class qed5271le_device : public mips3_device +{ +public: + // construction/destruction + qed5271le_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mips3_device(mconfig, QED5271LE, "QED5271 (little)", tag, owner, clock, "qed5271le", MIPS3_TYPE_QED5271, ENDIANNESS_LITTLE) + { } +}; + +class rm7000be_device : public mips3_device +{ +public: + // construction/destruction + rm7000be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mips3_device(mconfig, RM7000BE, "RM7000 (big)", tag, owner, clock, "rm7000be", MIPS3_TYPE_RM7000, ENDIANNESS_BIG) + { } +}; + +class rm7000le_device : public mips3_device +{ +public: + // construction/destruction + rm7000le_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : mips3_device(mconfig, RM7000LE, "RM7000 (little)", tag, owner, clock, "rm7000le", MIPS3_TYPE_RM7000, ENDIANNESS_LITTLE) + { } +}; + + + +class mips3_frontend : public drc_frontend +{ +public: + // construction/destruction + mips3_frontend(mips3_device *mips3, UINT32 window_start, UINT32 window_end, UINT32 max_sequence); + +protected: + // required overrides + virtual bool describe(opcode_desc &desc, const opcode_desc *prev); + +private: + // internal helpers + bool describe_special(UINT32 op, opcode_desc &desc); + bool describe_regimm(UINT32 op, opcode_desc &desc); + bool describe_idt(UINT32 op, opcode_desc &desc); + bool describe_cop0(UINT32 op, opcode_desc &desc); + bool describe_cop1(UINT32 op, opcode_desc &desc); + bool describe_cop1x(UINT32 op, opcode_desc &desc); + bool describe_cop2(UINT32 op, opcode_desc &desc); + + // internal state + mips3_device *m_mips3; +}; /*************************************************************************** @@ -304,5 +752,4 @@ extern const device_type RM7000LE; #define MIPS3DRC_FASTEST_OPTIONS (0) - #endif /* __MIPS3_H__ */ diff --git a/src/emu/cpu/mips/mips3com.c b/src/emu/cpu/mips/mips3com.c index 106ce6d0b7e..15ac46f55f3 100644 --- a/src/emu/cpu/mips/mips3com.c +++ b/src/emu/cpu/mips/mips3com.c @@ -13,24 +13,9 @@ /*************************************************************************** - DEBUGGING -***************************************************************************/ - -#define PRINTF_TLB (0) -#define USE_ABI_REG_NAMES (1) - - -/*************************************************************************** FUNCTION PROTOTYPES ***************************************************************************/ -static TIMER_CALLBACK( compare_int_callback ); - -static UINT32 compute_config_register(const mips3_state *mips); -static UINT32 compute_prid_register(const mips3_state *mips); - -static void tlb_map_entry(mips3_state *mips, int tlbindex); -static void tlb_write_common(mips3_state *mips, int tlbindex); static void tlb_entry_log_half(mips3_tlb_entry *entry, int tlbindex, int which); @@ -61,156 +46,40 @@ INLINE int tlb_entry_is_global(const mips3_tlb_entry *entry) } - -/*************************************************************************** - INITIALIZATION AND SHUTDOWN -***************************************************************************/ - -/*------------------------------------------------- - mips3com_init - initialize the mips3_state - structure based on the configured type --------------------------------------------------*/ - -void mips3com_init(mips3_state *mips, mips3_flavor flavor, int bigendian, legacy_cpu_device *device, device_irq_acknowledge_delegate irqcallback) -{ - const mips3_config *config = (const mips3_config *)device->static_config(); - int tlbindex; - - /* initialize based on the config */ - memset(mips, 0, sizeof(*mips)); - mips->flavor = flavor; - mips->bigendian = bigendian; - mips->cpu_clock = device->clock(); - mips->irq_callback = irqcallback; - mips->device = device; - mips->program = &device->space(AS_PROGRAM); - mips->direct = &mips->program->direct(); - mips->icache_size = config->icache; - mips->dcache_size = config->dcache; - mips->system_clock = config->system_clock; - - /* configure flavor-specific parameters */ - mips->pfnmask = 0x00ffffff; - mips->tlbentries = MIPS3_MAX_TLB_ENTRIES; - - /* VR4300 and VR5432 have 4 fewer PFN bits, and only 32 TLB entries */ - if (flavor == MIPS3_TYPE_VR4300) - { - mips->pfnmask = 0x000fffff; - mips->tlbentries = 32; - } - - /* set up the endianness */ - mips->program->accessors(mips->memory); - - /* allocate the virtual TLB */ - mips->vtlb = vtlb_alloc(device, AS_PROGRAM, 2 * mips->tlbentries + 2, 0); - - /* allocate a timer for the compare interrupt */ - mips->compare_int_timer = device->machine().scheduler().timer_alloc(FUNC(compare_int_callback), (void *)device); - - /* reset the state */ - mips3com_reset(mips); - - /* register for save states */ - device->save_item(NAME(mips->pc)); - device->save_item(NAME(mips->r)); - device->save_item(NAME(mips->cpr)); - device->save_item(NAME(mips->ccr)); - device->save_item(NAME(mips->llbit)); - device->save_item(NAME(mips->count_zero_time)); - for (tlbindex = 0; tlbindex < mips->tlbentries; tlbindex++) - { - device->save_item(NAME(mips->tlb[tlbindex].page_mask), tlbindex); - device->save_item(NAME(mips->tlb[tlbindex].entry_hi), tlbindex); - device->save_item(NAME(mips->tlb[tlbindex].entry_lo), tlbindex); - } -} - - -/*------------------------------------------------- - mips3com_exit - common cleanup/exit --------------------------------------------------*/ - -void mips3com_exit(mips3_state *mips) -{ - if (mips->vtlb != NULL) - vtlb_free(mips->vtlb); -} - - -/*------------------------------------------------- - mips3com_reset - reset the state of all the - registers --------------------------------------------------*/ - -void mips3com_reset(mips3_state *mips) +void mips3_device::execute_set_input(int inputnum, int state) { - int tlbindex; - - /* initialize the state */ - mips->pc = 0xbfc00000; - mips->cpr[0][COP0_Status] = SR_BEV | SR_ERL; - mips->cpr[0][COP0_Wired] = 0; - mips->cpr[0][COP0_Compare] = 0xffffffff; - mips->cpr[0][COP0_Count] = 0; - mips->cpr[0][COP0_Config] = compute_config_register(mips); - mips->cpr[0][COP0_PRId] = compute_prid_register(mips); - mips->count_zero_time = mips->device->total_cycles(); - - /* initialize the TLB state */ - for (tlbindex = 0; tlbindex < mips->tlbentries; tlbindex++) + if (inputnum >= MIPS3_IRQ0 && inputnum <= MIPS3_IRQ5) { - mips3_tlb_entry *entry = &mips->tlb[tlbindex]; - entry->page_mask = 0; - entry->entry_hi = 0xffffffff; - entry->entry_lo[0] = 0xfffffff8; - entry->entry_lo[1] = 0xfffffff8; - vtlb_load(mips->vtlb, 2 * tlbindex + 0, 0, 0, 0); - vtlb_load(mips->vtlb, 2 * tlbindex + 1, 0, 0, 0); + if (state != CLEAR_LINE) + m_core->cpr[0][COP0_Cause] |= 0x400 << inputnum; + else + m_core->cpr[0][COP0_Cause] &= ~(0x400 << inputnum); } - - /* load the fixed TLB range */ - vtlb_load(mips->vtlb, 2 * mips->tlbentries + 0, (0xa0000000 - 0x80000000) >> MIPS3_MIN_PAGE_SHIFT, 0x80000000, 0x00000000 | VTLB_READ_ALLOWED | VTLB_WRITE_ALLOWED | VTLB_FETCH_ALLOWED | VTLB_FLAG_VALID); - vtlb_load(mips->vtlb, 2 * mips->tlbentries + 1, (0xc0000000 - 0xa0000000) >> MIPS3_MIN_PAGE_SHIFT, 0xa0000000, 0x00000000 | VTLB_READ_ALLOWED | VTLB_WRITE_ALLOWED | VTLB_FETCH_ALLOWED | VTLB_FLAG_VALID); } -/*------------------------------------------------- - mips3com_dasm - handle disassembly for a - CPU --------------------------------------------------*/ - -offs_t mips3com_dasm(mips3_state *mips, char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram) -{ - extern unsigned dasmmips3(char *, unsigned, UINT32); - UINT32 op = *(UINT32 *)oprom; - if (mips->bigendian) - op = BIG_ENDIANIZE_INT32(op); - else - op = LITTLE_ENDIANIZE_INT32(op); - return dasmmips3(buffer, pc, op); -} - +/*************************************************************************** + INITIALIZATION AND SHUTDOWN +***************************************************************************/ /*------------------------------------------------- mips3com_update_cycle_counting - update cycle counts and the timers -------------------------------------------------*/ -void mips3com_update_cycle_counting(mips3_state *mips) +void mips3_device::mips3com_update_cycle_counting() { /* modify the timer to go off */ - if (mips->compare_armed && (mips->cpr[0][COP0_Status] & SR_IMEX5)) + if (m_core->compare_armed && (m_core->cpr[0][COP0_Status] & SR_IMEX5)) { - UINT32 count = (mips->device->total_cycles() - mips->count_zero_time) / 2; - UINT32 compare = mips->cpr[0][COP0_Compare]; + UINT32 count = (total_cycles() - m_core->count_zero_time) / 2; + UINT32 compare = m_core->cpr[0][COP0_Compare]; UINT32 delta = compare - count; - attotime newtime = mips->device->cycles_to_attotime((UINT64)delta * 2); - mips->compare_int_timer->adjust(newtime); + attotime newtime = cycles_to_attotime((UINT64)delta * 2); + m_compare_int_timer->adjust(newtime); return; } - mips->compare_int_timer->adjust(attotime::never); + m_compare_int_timer->adjust(attotime::never); } @@ -224,34 +93,14 @@ void mips3com_update_cycle_counting(mips3_state *mips) TLB entries -------------------------------------------------*/ -void mips3com_asid_changed(mips3_state *mips) +void mips3_device::mips3com_asid_changed() { int tlbindex; /* iterate over all non-global TLB entries and remap them */ - for (tlbindex = 0; tlbindex < mips->tlbentries; tlbindex++) - if (!tlb_entry_is_global(&mips->tlb[tlbindex])) - tlb_map_entry(mips, tlbindex); -} - - -/*------------------------------------------------- - mips3com_translate_address - translate an address - from logical to physical --------------------------------------------------*/ - -int mips3com_translate_address(mips3_state *mips, address_spacenum space, int intention, offs_t *address) -{ - /* only applies to the program address space */ - if (space == AS_PROGRAM) - { - const vtlb_entry *table = vtlb_table(mips->vtlb); - vtlb_entry entry = table[*address >> MIPS3_MIN_PAGE_SHIFT]; - if ((entry & (1 << (intention & (TRANSLATE_TYPE_MASK | TRANSLATE_USER_MASK)))) == 0) - return FALSE; - *address = (entry & ~MIPS3_MIN_PAGE_MASK) | (*address & MIPS3_MIN_PAGE_MASK); - } - return TRUE; + for (tlbindex = 0; tlbindex < m_tlbentries; tlbindex++) + if (!tlb_entry_is_global(&m_tlb[tlbindex])) + tlb_map_entry(tlbindex); } @@ -259,20 +108,20 @@ int mips3com_translate_address(mips3_state *mips, address_spacenum space, int in mips3com_tlbr - execute the tlbr instruction -------------------------------------------------*/ -void mips3com_tlbr(mips3_state *mips) +void mips3_device::mips3com_tlbr() { - UINT32 tlbindex = mips->cpr[0][COP0_Index] & 0x3f; + UINT32 tlbindex = m_core->cpr[0][COP0_Index] & 0x3f; /* only handle entries within the TLB */ - if (tlbindex < mips->tlbentries) + if (tlbindex < m_tlbentries) { - mips3_tlb_entry *entry = &mips->tlb[tlbindex]; + mips3_tlb_entry *entry = &m_tlb[tlbindex]; /* copy data from the TLB entry into the COP0 registers */ - mips->cpr[0][COP0_PageMask] = entry->page_mask; - mips->cpr[0][COP0_EntryHi] = entry->entry_hi; - mips->cpr[0][COP0_EntryLo0] = entry->entry_lo[0]; - mips->cpr[0][COP0_EntryLo1] = entry->entry_lo[1]; + m_core->cpr[0][COP0_PageMask] = entry->page_mask; + m_core->cpr[0][COP0_EntryHi] = entry->entry_hi; + m_core->cpr[0][COP0_EntryLo0] = entry->entry_lo[0]; + m_core->cpr[0][COP0_EntryLo1] = entry->entry_lo[1]; } } @@ -281,10 +130,10 @@ void mips3com_tlbr(mips3_state *mips) mips3com_tlbwi - execute the tlbwi instruction -------------------------------------------------*/ -void mips3com_tlbwi(mips3_state *mips) +void mips3_device::mips3com_tlbwi() { /* use the common handler and write based off the COP0 Index register */ - tlb_write_common(mips, mips->cpr[0][COP0_Index] & 0x3f); + tlb_write_common(m_core->cpr[0][COP0_Index] & 0x3f); } @@ -292,18 +141,18 @@ void mips3com_tlbwi(mips3_state *mips) mips3com_tlbwr - execute the tlbwr instruction -------------------------------------------------*/ -void mips3com_tlbwr(mips3_state *mips) +void mips3_device::mips3com_tlbwr() { - UINT32 wired = mips->cpr[0][COP0_Wired] & 0x3f; - UINT32 unwired = mips->tlbentries - wired; - UINT32 tlbindex = mips->tlbentries - 1; + UINT32 wired = m_core->cpr[0][COP0_Wired] & 0x3f; + UINT32 unwired = m_tlbentries - wired; + UINT32 tlbindex = m_tlbentries - 1; /* "random" is based off of the current cycle counting through the non-wired pages */ if (unwired > 0) - tlbindex = ((mips->device->total_cycles() - mips->count_zero_time) % unwired + wired) & 0x3f; + tlbindex = ((total_cycles() - m_core->count_zero_time) % unwired + wired) & 0x3f; /* use the common handler to write to this tlbindex */ - tlb_write_common(mips, tlbindex); + tlb_write_common(tlbindex); } @@ -311,439 +160,35 @@ void mips3com_tlbwr(mips3_state *mips) mips3com_tlbp - execute the tlbp instruction -------------------------------------------------*/ -void mips3com_tlbp(mips3_state *mips) +void mips3_device::mips3com_tlbp() { UINT32 tlbindex; -// UINT64 vpn; /* iterate over TLB entries */ - for (tlbindex = 0; tlbindex < mips->tlbentries; tlbindex++) + for (tlbindex = 0; tlbindex < m_tlbentries; tlbindex++) { - mips3_tlb_entry *entry = &mips->tlb[tlbindex]; + mips3_tlb_entry *entry = &m_tlb[tlbindex]; UINT64 mask = ~((entry->page_mask >> 13) & 0xfff) << 13; /* if the relevant bits of EntryHi match the relevant bits of the TLB */ - if ((entry->entry_hi & mask) == (mips->cpr[0][COP0_EntryHi] & mask)) + if ((entry->entry_hi & mask) == (m_core->cpr[0][COP0_EntryHi] & mask)) /* and if we are either global or matching the current ASID, then stop */ - if ((entry->entry_hi & 0xff) == (mips->cpr[0][COP0_EntryHi] & 0xff) || ((entry->entry_lo[0] & entry->entry_lo[1]) & TLB_GLOBAL)) + if ((entry->entry_hi & 0xff) == (m_core->cpr[0][COP0_EntryHi] & 0xff) || ((entry->entry_lo[0] & entry->entry_lo[1]) & TLB_GLOBAL)) break; } /* validate that our tlb_table was in sync */ -// vpn = ((mips->cpr[0][COP0_EntryHi] >> 13) & 0x07ffffff) << 1; - if (tlbindex != mips->tlbentries) - mips->cpr[0][COP0_Index] = tlbindex; +// vpn = ((m_cores->cpr[0][COP0_EntryHi] >> 13) & 0x07ffffff) << 1; + if (tlbindex != m_tlbentries) + m_core->cpr[0][COP0_Index] = tlbindex; else - mips->cpr[0][COP0_Index] = 0x80000000; + m_core->cpr[0][COP0_Index] = 0x80000000; } /*************************************************************************** - COMMON GET/SET INFO -***************************************************************************/ - -/*------------------------------------------------- - mips3com_set_info - set information about - a MIPS 3 CPU --------------------------------------------------*/ - -void mips3com_set_info(mips3_state *mips, UINT32 state, cpuinfo *info) -{ - switch (state) - { - /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ0: mips3com_set_irq_line(mips, MIPS3_IRQ0, info->i); break; - case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ1: mips3com_set_irq_line(mips, MIPS3_IRQ1, info->i); break; - case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ2: mips3com_set_irq_line(mips, MIPS3_IRQ2, info->i); break; - case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ3: mips3com_set_irq_line(mips, MIPS3_IRQ3, info->i); break; - case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ4: mips3com_set_irq_line(mips, MIPS3_IRQ4, info->i); break; - case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ5: mips3com_set_irq_line(mips, MIPS3_IRQ5, info->i); break; - - case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + MIPS3_PC: mips->pc = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_SR: mips->cpr[0][COP0_Status] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_EPC: mips->cpr[0][COP0_EPC] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_CAUSE: mips->cpr[0][COP0_Cause] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_COUNT: mips->cpr[0][COP0_Count] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_COMPARE: mips->cpr[0][COP0_Compare] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_INDEX: mips->cpr[0][COP0_Index] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_RANDOM: mips->cpr[0][COP0_Random] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_ENTRYHI: mips->cpr[0][COP0_EntryHi] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_ENTRYLO0: mips->cpr[0][COP0_EntryLo0] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_ENTRYLO1: mips->cpr[0][COP0_EntryLo1] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_PAGEMASK: mips->cpr[0][COP0_PageMask] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_WIRED: mips->cpr[0][COP0_Wired] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_BADVADDR: mips->cpr[0][COP0_BadVAddr] = info->i; break; - - case CPUINFO_INT_REGISTER + MIPS3_R0: /* can't change R0 */ break; - case CPUINFO_INT_REGISTER + MIPS3_R1: mips->r[1] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R2: mips->r[2] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R3: mips->r[3] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R4: mips->r[4] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R5: mips->r[5] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R6: mips->r[6] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R7: mips->r[7] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R8: mips->r[8] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R9: mips->r[9] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R10: mips->r[10] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R11: mips->r[11] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R12: mips->r[12] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R13: mips->r[13] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R14: mips->r[14] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R15: mips->r[15] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R16: mips->r[16] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R17: mips->r[17] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R18: mips->r[18] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R19: mips->r[19] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R20: mips->r[20] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R21: mips->r[21] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R22: mips->r[22] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R23: mips->r[23] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R24: mips->r[24] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R25: mips->r[25] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R26: mips->r[26] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R27: mips->r[27] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R28: mips->r[28] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R29: mips->r[29] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_R30: mips->r[30] = info->i; break; - case CPUINFO_INT_SP: - case CPUINFO_INT_REGISTER + MIPS3_R31: mips->r[31] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_HI: mips->r[REG_HI] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_LO: mips->r[REG_LO] = info->i; break; - - case CPUINFO_INT_REGISTER + MIPS3_FPR0: mips->cpr[1][0] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR1: mips->cpr[1][1] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR2: mips->cpr[1][2] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR3: mips->cpr[1][3] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR4: mips->cpr[1][4] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR5: mips->cpr[1][5] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR6: mips->cpr[1][6] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR7: mips->cpr[1][7] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR8: mips->cpr[1][8] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR9: mips->cpr[1][9] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR10: mips->cpr[1][10] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR11: mips->cpr[1][11] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR12: mips->cpr[1][12] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR13: mips->cpr[1][13] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR14: mips->cpr[1][14] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR15: mips->cpr[1][15] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR16: mips->cpr[1][16] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR17: mips->cpr[1][17] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR18: mips->cpr[1][18] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR19: mips->cpr[1][19] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR20: mips->cpr[1][20] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR21: mips->cpr[1][21] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR22: mips->cpr[1][22] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR23: mips->cpr[1][23] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR24: mips->cpr[1][24] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR25: mips->cpr[1][25] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR26: mips->cpr[1][26] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR27: mips->cpr[1][27] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR28: mips->cpr[1][28] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR29: mips->cpr[1][29] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR30: mips->cpr[1][30] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS3_FPR31: mips->cpr[1][31] = info->i; break; - } -} - - -/*------------------------------------------------- - mips3com_get_info - get information about - a MIPS 3 CPU --------------------------------------------------*/ - -void mips3com_get_info(mips3_state *mips, UINT32 state, cpuinfo *info) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: /* provided by core */ break; - case CPUINFO_INT_INPUT_LINES: info->i = 6; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = mips->bigendian ? ENDIANNESS_BIG : ENDIANNESS_LITTLE; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 4; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 40; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = MIPS3_MAX_PADDR_SHIFT;break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_LOGADDR_WIDTH_PROGRAM: info->i = 32; break; - case CPUINFO_INT_PAGE_SHIFT_PROGRAM: info->i = MIPS3_MIN_PAGE_SHIFT; break; - - case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ0: info->i = (mips->cpr[0][COP0_Cause] & 0x400) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ1: info->i = (mips->cpr[0][COP0_Cause] & 0x800) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ2: info->i = (mips->cpr[0][COP0_Cause] & 0x1000) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ3: info->i = (mips->cpr[0][COP0_Cause] & 0x2000) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ4: info->i = (mips->cpr[0][COP0_Cause] & 0x4000) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ5: info->i = (mips->cpr[0][COP0_Cause] & 0x8000) ? ASSERT_LINE : CLEAR_LINE; break; - - case CPUINFO_INT_PREVIOUSPC: /* optionally implemented */ break; - - case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + MIPS3_PC: info->i = mips->pc; break; - case CPUINFO_INT_REGISTER + MIPS3_SR: info->i = mips->cpr[0][COP0_Status]; break; - case CPUINFO_INT_REGISTER + MIPS3_EPC: info->i = mips->cpr[0][COP0_EPC]; break; - case CPUINFO_INT_REGISTER + MIPS3_CAUSE: info->i = mips->cpr[0][COP0_Cause]; break; - case CPUINFO_INT_REGISTER + MIPS3_COUNT: info->i = ((mips->device->total_cycles() - mips->count_zero_time) / 2); break; - case CPUINFO_INT_REGISTER + MIPS3_COMPARE: info->i = mips->cpr[0][COP0_Compare]; break; - case CPUINFO_INT_REGISTER + MIPS3_INDEX: info->i = mips->cpr[0][COP0_Index]; break; - case CPUINFO_INT_REGISTER + MIPS3_RANDOM: info->i = mips->cpr[0][COP0_Random]; break; - case CPUINFO_INT_REGISTER + MIPS3_ENTRYHI: info->i = mips->cpr[0][COP0_EntryHi]; break; - case CPUINFO_INT_REGISTER + MIPS3_ENTRYLO0: info->i = mips->cpr[0][COP0_EntryLo0]; break; - case CPUINFO_INT_REGISTER + MIPS3_ENTRYLO1: info->i = mips->cpr[0][COP0_EntryLo1]; break; - case CPUINFO_INT_REGISTER + MIPS3_PAGEMASK: info->i = mips->cpr[0][COP0_PageMask]; break; - case CPUINFO_INT_REGISTER + MIPS3_WIRED: info->i = mips->cpr[0][COP0_Wired]; break; - case CPUINFO_INT_REGISTER + MIPS3_BADVADDR: info->i = mips->cpr[0][COP0_BadVAddr]; break; - - case CPUINFO_INT_REGISTER + MIPS3_R0: info->i = mips->r[0]; break; - case CPUINFO_INT_REGISTER + MIPS3_R1: info->i = mips->r[1]; break; - case CPUINFO_INT_REGISTER + MIPS3_R2: info->i = mips->r[2]; break; - case CPUINFO_INT_REGISTER + MIPS3_R3: info->i = mips->r[3]; break; - case CPUINFO_INT_REGISTER + MIPS3_R4: info->i = mips->r[4]; break; - case CPUINFO_INT_REGISTER + MIPS3_R5: info->i = mips->r[5]; break; - case CPUINFO_INT_REGISTER + MIPS3_R6: info->i = mips->r[6]; break; - case CPUINFO_INT_REGISTER + MIPS3_R7: info->i = mips->r[7]; break; - case CPUINFO_INT_REGISTER + MIPS3_R8: info->i = mips->r[8]; break; - case CPUINFO_INT_REGISTER + MIPS3_R9: info->i = mips->r[9]; break; - case CPUINFO_INT_REGISTER + MIPS3_R10: info->i = mips->r[10]; break; - case CPUINFO_INT_REGISTER + MIPS3_R11: info->i = mips->r[11]; break; - case CPUINFO_INT_REGISTER + MIPS3_R12: info->i = mips->r[12]; break; - case CPUINFO_INT_REGISTER + MIPS3_R13: info->i = mips->r[13]; break; - case CPUINFO_INT_REGISTER + MIPS3_R14: info->i = mips->r[14]; break; - case CPUINFO_INT_REGISTER + MIPS3_R15: info->i = mips->r[15]; break; - case CPUINFO_INT_REGISTER + MIPS3_R16: info->i = mips->r[16]; break; - case CPUINFO_INT_REGISTER + MIPS3_R17: info->i = mips->r[17]; break; - case CPUINFO_INT_REGISTER + MIPS3_R18: info->i = mips->r[18]; break; - case CPUINFO_INT_REGISTER + MIPS3_R19: info->i = mips->r[19]; break; - case CPUINFO_INT_REGISTER + MIPS3_R20: info->i = mips->r[20]; break; - case CPUINFO_INT_REGISTER + MIPS3_R21: info->i = mips->r[21]; break; - case CPUINFO_INT_REGISTER + MIPS3_R22: info->i = mips->r[22]; break; - case CPUINFO_INT_REGISTER + MIPS3_R23: info->i = mips->r[23]; break; - case CPUINFO_INT_REGISTER + MIPS3_R24: info->i = mips->r[24]; break; - case CPUINFO_INT_REGISTER + MIPS3_R25: info->i = mips->r[25]; break; - case CPUINFO_INT_REGISTER + MIPS3_R26: info->i = mips->r[26]; break; - case CPUINFO_INT_REGISTER + MIPS3_R27: info->i = mips->r[27]; break; - case CPUINFO_INT_REGISTER + MIPS3_R28: info->i = mips->r[28]; break; - case CPUINFO_INT_REGISTER + MIPS3_R29: info->i = mips->r[29]; break; - case CPUINFO_INT_REGISTER + MIPS3_R30: info->i = mips->r[30]; break; - case CPUINFO_INT_SP: - case CPUINFO_INT_REGISTER + MIPS3_R31: info->i = mips->r[31]; break; - case CPUINFO_INT_REGISTER + MIPS3_HI: info->i = mips->r[REG_HI]; break; - case CPUINFO_INT_REGISTER + MIPS3_LO: info->i = mips->r[REG_LO]; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: /* provided by core */ break; - case CPUINFO_FCT_INIT: /* provided by core */ break; - case CPUINFO_FCT_RESET: /* provided by core */ break; - case CPUINFO_FCT_EXIT: /* provided by core */ break; - case CPUINFO_FCT_EXECUTE: /* provided by core */ break; - case CPUINFO_FCT_TRANSLATE: /* provided by core */ break; - case CPUINFO_FCT_DISASSEMBLE: /* provided by core */ break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &mips->icount; break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "MIPS III"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "MIPS III"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "3.0"); break; - case CPUINFO_STR_SOURCE_FILE: /* provided by core */ break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Aaron Giles"); break; - - case CPUINFO_STR_FLAGS: strcpy(info->s, " "); break; - - case CPUINFO_STR_REGISTER + MIPS3_PC: sprintf(info->s, "PC:%08X", mips->pc); break; - case CPUINFO_STR_REGISTER + MIPS3_SR: sprintf(info->s, "SR:%08X", (UINT32)mips->cpr[0][COP0_Status]); break; - case CPUINFO_STR_REGISTER + MIPS3_EPC: sprintf(info->s, "EPC:%08X", (UINT32)mips->cpr[0][COP0_EPC]); break; - case CPUINFO_STR_REGISTER + MIPS3_CAUSE: sprintf(info->s, "Cause:%08X", (UINT32)mips->cpr[0][COP0_Cause]); break; - case CPUINFO_STR_REGISTER + MIPS3_COUNT: sprintf(info->s, "Count:%08X", (UINT32)((mips->device->total_cycles() - mips->count_zero_time) / 2)); break; - case CPUINFO_STR_REGISTER + MIPS3_COMPARE: sprintf(info->s, "Compare:%08X", (UINT32)mips->cpr[0][COP0_Compare]); break; - case CPUINFO_STR_REGISTER + MIPS3_INDEX: sprintf(info->s, "Index:%08X", (UINT32)mips->cpr[0][COP0_Index]); break; - case CPUINFO_STR_REGISTER + MIPS3_RANDOM: sprintf(info->s, "Random:%08X", (UINT32)mips->cpr[0][COP0_Random]); break; - case CPUINFO_STR_REGISTER + MIPS3_ENTRYHI: sprintf(info->s, "EntryHi:%08X%08X", (UINT32)(mips->cpr[0][COP0_EntryHi] >> 32), (UINT32)mips->cpr[0][COP0_EntryHi]); break; - case CPUINFO_STR_REGISTER + MIPS3_ENTRYLO0: sprintf(info->s, "EntryLo0:%08X%08X", (UINT32)(mips->cpr[0][COP0_EntryLo0] >> 32), (UINT32)mips->cpr[0][COP0_EntryLo0]); break; - case CPUINFO_STR_REGISTER + MIPS3_ENTRYLO1: sprintf(info->s, "EntryLo1:%08X%08X", (UINT32)(mips->cpr[0][COP0_EntryLo1] >> 32), (UINT32)mips->cpr[0][COP0_EntryLo1]); break; - case CPUINFO_STR_REGISTER + MIPS3_PAGEMASK: sprintf(info->s, "PageMask:%08X%08X", (UINT32)(mips->cpr[0][COP0_PageMask] >> 32), (UINT32)mips->cpr[0][COP0_PageMask]); break; - case CPUINFO_STR_REGISTER + MIPS3_WIRED: sprintf(info->s, "Wired:%08X", (UINT32)mips->cpr[0][COP0_Wired]); break; - case CPUINFO_STR_REGISTER + MIPS3_BADVADDR: sprintf(info->s, "BadVAddr:%08X", (UINT32)mips->cpr[0][COP0_BadVAddr]); break; - -#if USE_ABI_REG_NAMES - case CPUINFO_STR_REGISTER + MIPS3_R0: sprintf(info->s, "zero:%08X%08X", (UINT32)(mips->r[0] >> 32), (UINT32)mips->r[0]); break; - case CPUINFO_STR_REGISTER + MIPS3_R1: sprintf(info->s, "at:%08X%08X", (UINT32)(mips->r[1] >> 32), (UINT32)mips->r[1]); break; - case CPUINFO_STR_REGISTER + MIPS3_R2: sprintf(info->s, "v0:%08X%08X", (UINT32)(mips->r[2] >> 32), (UINT32)mips->r[2]); break; - case CPUINFO_STR_REGISTER + MIPS3_R3: sprintf(info->s, "v1:%08X%08X", (UINT32)(mips->r[3] >> 32), (UINT32)mips->r[3]); break; - case CPUINFO_STR_REGISTER + MIPS3_R4: sprintf(info->s, "a0:%08X%08X", (UINT32)(mips->r[4] >> 32), (UINT32)mips->r[4]); break; - case CPUINFO_STR_REGISTER + MIPS3_R5: sprintf(info->s, "a1:%08X%08X", (UINT32)(mips->r[5] >> 32), (UINT32)mips->r[5]); break; - case CPUINFO_STR_REGISTER + MIPS3_R6: sprintf(info->s, "a2:%08X%08X", (UINT32)(mips->r[6] >> 32), (UINT32)mips->r[6]); break; - case CPUINFO_STR_REGISTER + MIPS3_R7: sprintf(info->s, "a3:%08X%08X", (UINT32)(mips->r[7] >> 32), (UINT32)mips->r[7]); break; - case CPUINFO_STR_REGISTER + MIPS3_R8: sprintf(info->s, "t0:%08X%08X", (UINT32)(mips->r[8] >> 32), (UINT32)mips->r[8]); break; - case CPUINFO_STR_REGISTER + MIPS3_R9: sprintf(info->s, "t1:%08X%08X", (UINT32)(mips->r[9] >> 32), (UINT32)mips->r[9]); break; - case CPUINFO_STR_REGISTER + MIPS3_R10: sprintf(info->s, "t2:%08X%08X", (UINT32)(mips->r[10] >> 32), (UINT32)mips->r[10]); break; - case CPUINFO_STR_REGISTER + MIPS3_R11: sprintf(info->s, "t3:%08X%08X", (UINT32)(mips->r[11] >> 32), (UINT32)mips->r[11]); break; - case CPUINFO_STR_REGISTER + MIPS3_R12: sprintf(info->s, "t4:%08X%08X", (UINT32)(mips->r[12] >> 32), (UINT32)mips->r[12]); break; - case CPUINFO_STR_REGISTER + MIPS3_R13: sprintf(info->s, "t5:%08X%08X", (UINT32)(mips->r[13] >> 32), (UINT32)mips->r[13]); break; - case CPUINFO_STR_REGISTER + MIPS3_R14: sprintf(info->s, "t6:%08X%08X", (UINT32)(mips->r[14] >> 32), (UINT32)mips->r[14]); break; - case CPUINFO_STR_REGISTER + MIPS3_R15: sprintf(info->s, "t7:%08X%08X", (UINT32)(mips->r[15] >> 32), (UINT32)mips->r[15]); break; - case CPUINFO_STR_REGISTER + MIPS3_R16: sprintf(info->s, "s0:%08X%08X", (UINT32)(mips->r[16] >> 32), (UINT32)mips->r[16]); break; - case CPUINFO_STR_REGISTER + MIPS3_R17: sprintf(info->s, "s1:%08X%08X", (UINT32)(mips->r[17] >> 32), (UINT32)mips->r[17]); break; - case CPUINFO_STR_REGISTER + MIPS3_R18: sprintf(info->s, "s2:%08X%08X", (UINT32)(mips->r[18] >> 32), (UINT32)mips->r[18]); break; - case CPUINFO_STR_REGISTER + MIPS3_R19: sprintf(info->s, "s3:%08X%08X", (UINT32)(mips->r[19] >> 32), (UINT32)mips->r[19]); break; - case CPUINFO_STR_REGISTER + MIPS3_R20: sprintf(info->s, "s4:%08X%08X", (UINT32)(mips->r[20] >> 32), (UINT32)mips->r[20]); break; - case CPUINFO_STR_REGISTER + MIPS3_R21: sprintf(info->s, "s5:%08X%08X", (UINT32)(mips->r[21] >> 32), (UINT32)mips->r[21]); break; - case CPUINFO_STR_REGISTER + MIPS3_R22: sprintf(info->s, "s6:%08X%08X", (UINT32)(mips->r[22] >> 32), (UINT32)mips->r[22]); break; - case CPUINFO_STR_REGISTER + MIPS3_R23: sprintf(info->s, "s7:%08X%08X", (UINT32)(mips->r[23] >> 32), (UINT32)mips->r[23]); break; - case CPUINFO_STR_REGISTER + MIPS3_R24: sprintf(info->s, "t8:%08X%08X", (UINT32)(mips->r[24] >> 32), (UINT32)mips->r[24]); break; - case CPUINFO_STR_REGISTER + MIPS3_R25: sprintf(info->s, "t9:%08X%08X", (UINT32)(mips->r[25] >> 32), (UINT32)mips->r[25]); break; - case CPUINFO_STR_REGISTER + MIPS3_R26: sprintf(info->s, "k0:%08X%08X", (UINT32)(mips->r[26] >> 32), (UINT32)mips->r[26]); break; - case CPUINFO_STR_REGISTER + MIPS3_R27: sprintf(info->s, "k1:%08X%08X", (UINT32)(mips->r[27] >> 32), (UINT32)mips->r[27]); break; - case CPUINFO_STR_REGISTER + MIPS3_R28: sprintf(info->s, "gp:%08X%08X", (UINT32)(mips->r[28] >> 32), (UINT32)mips->r[28]); break; - case CPUINFO_STR_REGISTER + MIPS3_R29: sprintf(info->s, "sp:%08X%08X", (UINT32)(mips->r[29] >> 32), (UINT32)mips->r[29]); break; - case CPUINFO_STR_REGISTER + MIPS3_R30: sprintf(info->s, "fp:%08X%08X", (UINT32)(mips->r[30] >> 32), (UINT32)mips->r[30]); break; - case CPUINFO_STR_REGISTER + MIPS3_R31: sprintf(info->s, "ra:%08X%08X", (UINT32)(mips->r[31] >> 32), (UINT32)mips->r[31]); break; -#else - case CPUINFO_STR_REGISTER + MIPS3_R0: sprintf(info->s, "R0:%08X%08X", (UINT32)(mips->r[0] >> 32), (UINT32)mips->r[0]); break; - case CPUINFO_STR_REGISTER + MIPS3_R1: sprintf(info->s, "R1:%08X%08X", (UINT32)(mips->r[1] >> 32), (UINT32)mips->r[1]); break; - case CPUINFO_STR_REGISTER + MIPS3_R2: sprintf(info->s, "R2:%08X%08X", (UINT32)(mips->r[2] >> 32), (UINT32)mips->r[2]); break; - case CPUINFO_STR_REGISTER + MIPS3_R3: sprintf(info->s, "R3:%08X%08X", (UINT32)(mips->r[3] >> 32), (UINT32)mips->r[3]); break; - case CPUINFO_STR_REGISTER + MIPS3_R4: sprintf(info->s, "R4:%08X%08X", (UINT32)(mips->r[4] >> 32), (UINT32)mips->r[4]); break; - case CPUINFO_STR_REGISTER + MIPS3_R5: sprintf(info->s, "R5:%08X%08X", (UINT32)(mips->r[5] >> 32), (UINT32)mips->r[5]); break; - case CPUINFO_STR_REGISTER + MIPS3_R6: sprintf(info->s, "R6:%08X%08X", (UINT32)(mips->r[6] >> 32), (UINT32)mips->r[6]); break; - case CPUINFO_STR_REGISTER + MIPS3_R7: sprintf(info->s, "R7:%08X%08X", (UINT32)(mips->r[7] >> 32), (UINT32)mips->r[7]); break; - case CPUINFO_STR_REGISTER + MIPS3_R8: sprintf(info->s, "R8:%08X%08X", (UINT32)(mips->r[8] >> 32), (UINT32)mips->r[8]); break; - case CPUINFO_STR_REGISTER + MIPS3_R9: sprintf(info->s, "R9:%08X%08X", (UINT32)(mips->r[9] >> 32), (UINT32)mips->r[9]); break; - case CPUINFO_STR_REGISTER + MIPS3_R10: sprintf(info->s, "R10:%08X%08X", (UINT32)(mips->r[10] >> 32), (UINT32)mips->r[10]); break; - case CPUINFO_STR_REGISTER + MIPS3_R11: sprintf(info->s, "R11:%08X%08X", (UINT32)(mips->r[11] >> 32), (UINT32)mips->r[11]); break; - case CPUINFO_STR_REGISTER + MIPS3_R12: sprintf(info->s, "R12:%08X%08X", (UINT32)(mips->r[12] >> 32), (UINT32)mips->r[12]); break; - case CPUINFO_STR_REGISTER + MIPS3_R13: sprintf(info->s, "R13:%08X%08X", (UINT32)(mips->r[13] >> 32), (UINT32)mips->r[13]); break; - case CPUINFO_STR_REGISTER + MIPS3_R14: sprintf(info->s, "R14:%08X%08X", (UINT32)(mips->r[14] >> 32), (UINT32)mips->r[14]); break; - case CPUINFO_STR_REGISTER + MIPS3_R15: sprintf(info->s, "R15:%08X%08X", (UINT32)(mips->r[15] >> 32), (UINT32)mips->r[15]); break; - case CPUINFO_STR_REGISTER + MIPS3_R16: sprintf(info->s, "R16:%08X%08X", (UINT32)(mips->r[16] >> 32), (UINT32)mips->r[16]); break; - case CPUINFO_STR_REGISTER + MIPS3_R17: sprintf(info->s, "R17:%08X%08X", (UINT32)(mips->r[17] >> 32), (UINT32)mips->r[17]); break; - case CPUINFO_STR_REGISTER + MIPS3_R18: sprintf(info->s, "R18:%08X%08X", (UINT32)(mips->r[18] >> 32), (UINT32)mips->r[18]); break; - case CPUINFO_STR_REGISTER + MIPS3_R19: sprintf(info->s, "R19:%08X%08X", (UINT32)(mips->r[19] >> 32), (UINT32)mips->r[19]); break; - case CPUINFO_STR_REGISTER + MIPS3_R20: sprintf(info->s, "R20:%08X%08X", (UINT32)(mips->r[20] >> 32), (UINT32)mips->r[20]); break; - case CPUINFO_STR_REGISTER + MIPS3_R21: sprintf(info->s, "R21:%08X%08X", (UINT32)(mips->r[21] >> 32), (UINT32)mips->r[21]); break; - case CPUINFO_STR_REGISTER + MIPS3_R22: sprintf(info->s, "R22:%08X%08X", (UINT32)(mips->r[22] >> 32), (UINT32)mips->r[22]); break; - case CPUINFO_STR_REGISTER + MIPS3_R23: sprintf(info->s, "R23:%08X%08X", (UINT32)(mips->r[23] >> 32), (UINT32)mips->r[23]); break; - case CPUINFO_STR_REGISTER + MIPS3_R24: sprintf(info->s, "R24:%08X%08X", (UINT32)(mips->r[24] >> 32), (UINT32)mips->r[24]); break; - case CPUINFO_STR_REGISTER + MIPS3_R25: sprintf(info->s, "R25:%08X%08X", (UINT32)(mips->r[25] >> 32), (UINT32)mips->r[25]); break; - case CPUINFO_STR_REGISTER + MIPS3_R26: sprintf(info->s, "R26:%08X%08X", (UINT32)(mips->r[26] >> 32), (UINT32)mips->r[26]); break; - case CPUINFO_STR_REGISTER + MIPS3_R27: sprintf(info->s, "R27:%08X%08X", (UINT32)(mips->r[27] >> 32), (UINT32)mips->r[27]); break; - case CPUINFO_STR_REGISTER + MIPS3_R28: sprintf(info->s, "R28:%08X%08X", (UINT32)(mips->r[28] >> 32), (UINT32)mips->r[28]); break; - case CPUINFO_STR_REGISTER + MIPS3_R29: sprintf(info->s, "R29:%08X%08X", (UINT32)(mips->r[29] >> 32), (UINT32)mips->r[29]); break; - case CPUINFO_STR_REGISTER + MIPS3_R30: sprintf(info->s, "R30:%08X%08X", (UINT32)(mips->r[30] >> 32), (UINT32)mips->r[30]); break; - case CPUINFO_STR_REGISTER + MIPS3_R31: sprintf(info->s, "R31:%08X%08X", (UINT32)(mips->r[31] >> 32), (UINT32)mips->r[31]); break; -#endif - case CPUINFO_STR_REGISTER + MIPS3_HI: sprintf(info->s, "HI:%08X%08X", (UINT32)(mips->r[REG_HI] >> 32), (UINT32)mips->r[REG_HI]); break; - case CPUINFO_STR_REGISTER + MIPS3_LO: sprintf(info->s, "LO:%08X%08X", (UINT32)(mips->r[REG_LO] >> 32), (UINT32)mips->r[REG_LO]); break; - - case CPUINFO_STR_REGISTER + MIPS3_CCR1_31: sprintf(info->s, "CCR31:%08X", (UINT32)mips->ccr[1][31]); break; - - case CPUINFO_STR_REGISTER + MIPS3_FPR0: sprintf(info->s, "FPR0:%08X%08X", (UINT32)(mips->cpr[1][0] >> 32), (UINT32)mips->cpr[1][0]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS0: sprintf(info->s, "FPS0:!%16g", *(float *)&mips->cpr[1][0]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD0: sprintf(info->s, "FPD0:!%16g", *(double *)&mips->cpr[1][0]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR1: sprintf(info->s, "FPR1:%08X%08X", (UINT32)(mips->cpr[1][1] >> 32), (UINT32)mips->cpr[1][1]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS1: sprintf(info->s, "FPS1:!%16g", *(float *)&mips->cpr[1][1]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD1: sprintf(info->s, "FPD1:!%16g", *(double *)&mips->cpr[1][1]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR2: sprintf(info->s, "FPR2:%08X%08X", (UINT32)(mips->cpr[1][2] >> 32), (UINT32)mips->cpr[1][2]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS2: sprintf(info->s, "FPS2:!%16g", *(float *)&mips->cpr[1][2]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD2: sprintf(info->s, "FPD2:!%16g", *(double *)&mips->cpr[1][2]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR3: sprintf(info->s, "FPR3:%08X%08X", (UINT32)(mips->cpr[1][3] >> 32), (UINT32)mips->cpr[1][3]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS3: sprintf(info->s, "FPS3:!%16g", *(float *)&mips->cpr[1][3]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD3: sprintf(info->s, "FPD3:!%16g", *(double *)&mips->cpr[1][3]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR4: sprintf(info->s, "FPR4:%08X%08X", (UINT32)(mips->cpr[1][4] >> 32), (UINT32)mips->cpr[1][4]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS4: sprintf(info->s, "FPS4:!%16g", *(float *)&mips->cpr[1][4]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD4: sprintf(info->s, "FPD4:!%16g", *(double *)&mips->cpr[1][4]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR5: sprintf(info->s, "FPR5:%08X%08X", (UINT32)(mips->cpr[1][5] >> 32), (UINT32)mips->cpr[1][5]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS5: sprintf(info->s, "FPS5:!%16g", *(float *)&mips->cpr[1][5]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD5: sprintf(info->s, "FPD5:!%16g", *(double *)&mips->cpr[1][5]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR6: sprintf(info->s, "FPR6:%08X%08X", (UINT32)(mips->cpr[1][6] >> 32), (UINT32)mips->cpr[1][6]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS6: sprintf(info->s, "FPS6:!%16g", *(float *)&mips->cpr[1][6]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD6: sprintf(info->s, "FPD6:!%16g", *(double *)&mips->cpr[1][6]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR7: sprintf(info->s, "FPR7:%08X%08X", (UINT32)(mips->cpr[1][7] >> 32), (UINT32)mips->cpr[1][7]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS7: sprintf(info->s, "FPS7:!%16g", *(float *)&mips->cpr[1][7]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD7: sprintf(info->s, "FPD7:!%16g", *(double *)&mips->cpr[1][7]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR8: sprintf(info->s, "FPR8:%08X%08X", (UINT32)(mips->cpr[1][8] >> 32), (UINT32)mips->cpr[1][8]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS8: sprintf(info->s, "FPS8:!%16g", *(float *)&mips->cpr[1][8]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD8: sprintf(info->s, "FPD8:!%16g", *(double *)&mips->cpr[1][8]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR9: sprintf(info->s, "FPR9:%08X%08X", (UINT32)(mips->cpr[1][9] >> 32), (UINT32)mips->cpr[1][9]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS9: sprintf(info->s, "FPS9:!%16g", *(float *)&mips->cpr[1][9]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD9: sprintf(info->s, "FPD9:!%16g", *(double *)&mips->cpr[1][9]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR10: sprintf(info->s, "FPR10:%08X%08X", (UINT32)(mips->cpr[1][10] >> 32), (UINT32)mips->cpr[1][10]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS10: sprintf(info->s, "FPS10:!%16g", *(float *)&mips->cpr[1][10]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD10: sprintf(info->s, "FPD10:!%16g", *(double *)&mips->cpr[1][10]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR11: sprintf(info->s, "FPR11:%08X%08X", (UINT32)(mips->cpr[1][11] >> 32), (UINT32)mips->cpr[1][11]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS11: sprintf(info->s, "FPS11:!%16g", *(float *)&mips->cpr[1][11]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD11: sprintf(info->s, "FPD11:!%16g", *(double *)&mips->cpr[1][11]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR12: sprintf(info->s, "FPR12:%08X%08X", (UINT32)(mips->cpr[1][12] >> 32), (UINT32)mips->cpr[1][12]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS12: sprintf(info->s, "FPS12:!%16g", *(float *)&mips->cpr[1][12]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD12: sprintf(info->s, "FPD12:!%16g", *(double *)&mips->cpr[1][12]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR13: sprintf(info->s, "FPR13:%08X%08X", (UINT32)(mips->cpr[1][13] >> 32), (UINT32)mips->cpr[1][13]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS13: sprintf(info->s, "FPS13:!%16g", *(float *)&mips->cpr[1][13]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD13: sprintf(info->s, "FPD13:!%16g", *(double *)&mips->cpr[1][13]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR14: sprintf(info->s, "FPR14:%08X%08X", (UINT32)(mips->cpr[1][14] >> 32), (UINT32)mips->cpr[1][14]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS14: sprintf(info->s, "FPS14:!%16g", *(float *)&mips->cpr[1][14]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD14: sprintf(info->s, "FPD14:!%16g", *(double *)&mips->cpr[1][14]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR15: sprintf(info->s, "FPR15:%08X%08X", (UINT32)(mips->cpr[1][15] >> 32), (UINT32)mips->cpr[1][15]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS15: sprintf(info->s, "FPS15:!%16g", *(float *)&mips->cpr[1][15]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD15: sprintf(info->s, "FPD15:!%16g", *(double *)&mips->cpr[1][15]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR16: sprintf(info->s, "FPR16:%08X%08X", (UINT32)(mips->cpr[1][16] >> 32), (UINT32)mips->cpr[1][16]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS16: sprintf(info->s, "FPS16:!%16g", *(float *)&mips->cpr[1][16]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD16: sprintf(info->s, "FPD16:!%16g", *(double *)&mips->cpr[1][16]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR17: sprintf(info->s, "FPR17:%08X%08X", (UINT32)(mips->cpr[1][17] >> 32), (UINT32)mips->cpr[1][17]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS17: sprintf(info->s, "FPS17:!%16g", *(float *)&mips->cpr[1][17]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD17: sprintf(info->s, "FPD17:!%16g", *(double *)&mips->cpr[1][17]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR18: sprintf(info->s, "FPR18:%08X%08X", (UINT32)(mips->cpr[1][18] >> 32), (UINT32)mips->cpr[1][18]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS18: sprintf(info->s, "FPS18:!%16g", *(float *)&mips->cpr[1][18]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD18: sprintf(info->s, "FPD18:!%16g", *(double *)&mips->cpr[1][18]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR19: sprintf(info->s, "FPR19:%08X%08X", (UINT32)(mips->cpr[1][19] >> 32), (UINT32)mips->cpr[1][19]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS19: sprintf(info->s, "FPS19:!%16g", *(float *)&mips->cpr[1][19]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD19: sprintf(info->s, "FPD19:!%16g", *(double *)&mips->cpr[1][19]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR20: sprintf(info->s, "FPR20:%08X%08X", (UINT32)(mips->cpr[1][20] >> 32), (UINT32)mips->cpr[1][20]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS20: sprintf(info->s, "FPS20:!%16g", *(float *)&mips->cpr[1][20]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD20: sprintf(info->s, "FPD20:!%16g", *(double *)&mips->cpr[1][20]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR21: sprintf(info->s, "FPR21:%08X%08X", (UINT32)(mips->cpr[1][21] >> 32), (UINT32)mips->cpr[1][21]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS21: sprintf(info->s, "FPS21:!%16g", *(float *)&mips->cpr[1][21]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD21: sprintf(info->s, "FPD21:!%16g", *(double *)&mips->cpr[1][21]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR22: sprintf(info->s, "FPR22:%08X%08X", (UINT32)(mips->cpr[1][22] >> 32), (UINT32)mips->cpr[1][22]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS22: sprintf(info->s, "FPS22:!%16g", *(float *)&mips->cpr[1][22]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD22: sprintf(info->s, "FPD22:!%16g", *(double *)&mips->cpr[1][22]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR23: sprintf(info->s, "FPR23:%08X%08X", (UINT32)(mips->cpr[1][23] >> 32), (UINT32)mips->cpr[1][23]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS23: sprintf(info->s, "FPS23:!%16g", *(float *)&mips->cpr[1][23]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD23: sprintf(info->s, "FPD23:!%16g", *(double *)&mips->cpr[1][23]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR24: sprintf(info->s, "FPR24:%08X%08X", (UINT32)(mips->cpr[1][24] >> 32), (UINT32)mips->cpr[1][24]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS24: sprintf(info->s, "FPS24:!%16g", *(float *)&mips->cpr[1][24]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD24: sprintf(info->s, "FPD24:!%16g", *(double *)&mips->cpr[1][24]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR25: sprintf(info->s, "FPR25:%08X%08X", (UINT32)(mips->cpr[1][25] >> 32), (UINT32)mips->cpr[1][25]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS25: sprintf(info->s, "FPS25:!%16g", *(float *)&mips->cpr[1][25]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD25: sprintf(info->s, "FPD25:!%16g", *(double *)&mips->cpr[1][25]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR26: sprintf(info->s, "FPR26:%08X%08X", (UINT32)(mips->cpr[1][26] >> 32), (UINT32)mips->cpr[1][26]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS26: sprintf(info->s, "FPS26:!%16g", *(float *)&mips->cpr[1][26]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD26: sprintf(info->s, "FPD26:!%16g", *(double *)&mips->cpr[1][26]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR27: sprintf(info->s, "FPR27:%08X%08X", (UINT32)(mips->cpr[1][27] >> 32), (UINT32)mips->cpr[1][27]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS27: sprintf(info->s, "FPS27:!%16g", *(float *)&mips->cpr[1][27]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD27: sprintf(info->s, "FPD27:!%16g", *(double *)&mips->cpr[1][27]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR28: sprintf(info->s, "FPR28:%08X%08X", (UINT32)(mips->cpr[1][28] >> 32), (UINT32)mips->cpr[1][28]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS28: sprintf(info->s, "FPS28:!%16g", *(float *)&mips->cpr[1][28]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD28: sprintf(info->s, "FPD28:!%16g", *(double *)&mips->cpr[1][28]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR29: sprintf(info->s, "FPR29:%08X%08X", (UINT32)(mips->cpr[1][29] >> 32), (UINT32)mips->cpr[1][29]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS29: sprintf(info->s, "FPS29:!%16g", *(float *)&mips->cpr[1][29]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD29: sprintf(info->s, "FPD29:!%16g", *(double *)&mips->cpr[1][29]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR30: sprintf(info->s, "FPR30:%08X%08X", (UINT32)(mips->cpr[1][30] >> 32), (UINT32)mips->cpr[1][30]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS30: sprintf(info->s, "FPS30:!%16g", *(float *)&mips->cpr[1][30]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD30: sprintf(info->s, "FPD30:!%16g", *(double *)&mips->cpr[1][30]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPR31: sprintf(info->s, "FPR31:%08X%08X", (UINT32)(mips->cpr[1][31] >> 32), (UINT32)mips->cpr[1][31]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPS31: sprintf(info->s, "FPS31:!%16g", *(float *)&mips->cpr[1][31]); break; - case CPUINFO_STR_REGISTER + MIPS3_FPD31: sprintf(info->s, "FPD31:!%16g", *(double *)&mips->cpr[1][31]); break; - } -} - - -/*************************************************************************** INTERNAL HELPERS ***************************************************************************/ @@ -752,10 +197,9 @@ void mips3com_get_info(mips3_state *mips, UINT32 state, cpuinfo *info) whenever a compare interrupt is generated -------------------------------------------------*/ -static TIMER_CALLBACK( compare_int_callback ) +TIMER_CALLBACK_MEMBER( mips3_device::compare_int_callback ) { - legacy_cpu_device *device = (legacy_cpu_device *)ptr; - device->set_input_line(MIPS3_IRQ5, ASSERT_LINE); + set_input_line(MIPS3_IRQ5, ASSERT_LINE); } @@ -764,14 +208,14 @@ static TIMER_CALLBACK( compare_int_callback ) of the config register -------------------------------------------------*/ -static UINT32 compute_config_register(const mips3_state *mips) +UINT32 mips3_device::compute_config_register() { /* set the cache line size to 32 bytes */ UINT32 configreg = 0x00026030; int divisor; // NEC VR series does not use a 100% compatible COP0/TLB implementation - if (mips->flavor == MIPS3_TYPE_VR4300) + if (m_flavor == MIPS3_TYPE_VR4300) { /* For VR43xx, Config is as follows: @@ -790,42 +234,42 @@ static UINT32 compute_config_register(const mips3_state *mips) else { /* set the data cache size */ - if (mips->icache_size <= 0x01000) configreg |= 0 << 6; - else if (mips->icache_size <= 0x02000) configreg |= 1 << 6; - else if (mips->icache_size <= 0x04000) configreg |= 2 << 6; - else if (mips->icache_size <= 0x08000) configreg |= 3 << 6; - else if (mips->icache_size <= 0x10000) configreg |= 4 << 6; - else if (mips->icache_size <= 0x20000) configreg |= 5 << 6; - else if (mips->icache_size <= 0x40000) configreg |= 6 << 6; + if (c_icache_size <= 0x01000) configreg |= 0 << 6; + else if (c_icache_size <= 0x02000) configreg |= 1 << 6; + else if (c_icache_size <= 0x04000) configreg |= 2 << 6; + else if (c_icache_size <= 0x08000) configreg |= 3 << 6; + else if (c_icache_size <= 0x10000) configreg |= 4 << 6; + else if (c_icache_size <= 0x20000) configreg |= 5 << 6; + else if (c_icache_size <= 0x40000) configreg |= 6 << 6; else configreg |= 7 << 6; /* set the instruction cache size */ - if (mips->icache_size <= 0x01000) configreg |= 0 << 9; - else if (mips->icache_size <= 0x02000) configreg |= 1 << 9; - else if (mips->icache_size <= 0x04000) configreg |= 2 << 9; - else if (mips->icache_size <= 0x08000) configreg |= 3 << 9; - else if (mips->icache_size <= 0x10000) configreg |= 4 << 9; - else if (mips->icache_size <= 0x20000) configreg |= 5 << 9; - else if (mips->icache_size <= 0x40000) configreg |= 6 << 9; + if (c_icache_size <= 0x01000) configreg |= 0 << 9; + else if (c_icache_size <= 0x02000) configreg |= 1 << 9; + else if (c_icache_size <= 0x04000) configreg |= 2 << 9; + else if (c_icache_size <= 0x08000) configreg |= 3 << 9; + else if (c_icache_size <= 0x10000) configreg |= 4 << 9; + else if (c_icache_size <= 0x20000) configreg |= 5 << 9; + else if (c_icache_size <= 0x40000) configreg |= 6 << 9; else configreg |= 7 << 9; /* set the system clock divider */ divisor = 2; - if (mips->system_clock != 0) + if (c_system_clock != 0) { - divisor = mips->cpu_clock / mips->system_clock; - if (mips->system_clock * divisor != mips->cpu_clock) + divisor = m_cpu_clock / c_system_clock; + if (c_system_clock * divisor != m_cpu_clock) { configreg |= 0x80000000; - divisor = mips->cpu_clock * 2 / mips->system_clock; + divisor = m_cpu_clock * 2 / c_system_clock; } } configreg |= (((divisor < 2) ? 2 : (divisor > 8) ? 8 : divisor) - 2) << 28; } /* set the endianness bit */ - if (mips->bigendian) + if (m_bigendian) configreg |= 0x00008000; return configreg; @@ -837,9 +281,9 @@ static UINT32 compute_config_register(const mips3_state *mips) of the PRId register -------------------------------------------------*/ -static UINT32 compute_prid_register(const mips3_state *mips) +UINT32 mips3_device::compute_prid_register() { - switch (mips->flavor) + switch (m_flavor) { case MIPS3_TYPE_VR4300: return 0x0b00; @@ -870,18 +314,18 @@ static UINT32 compute_prid_register(const mips3_state *mips) entry -------------------------------------------------*/ -static void tlb_map_entry(mips3_state *mips, int tlbindex) +void mips3_device::tlb_map_entry(int tlbindex) { - int current_asid = mips->cpr[0][COP0_EntryHi] & 0xff; - mips3_tlb_entry *entry = &mips->tlb[tlbindex]; + int current_asid = m_core->cpr[0][COP0_EntryHi] & 0xff; + mips3_tlb_entry *entry = &m_tlb[tlbindex]; UINT32 count, vpn; int which; /* the ASID doesn't match the current ASID, and if the page isn't global, unmap it from the TLB */ if (!tlb_entry_matches_asid(entry, current_asid) && !tlb_entry_is_global(entry)) { - vtlb_load(mips->vtlb, 2 * tlbindex + 0, 0, 0, 0); - vtlb_load(mips->vtlb, 2 * tlbindex + 1, 0, 0, 0); + vtlb_load(m_vtlb, 2 * tlbindex + 0, 0, 0, 0); + vtlb_load(m_vtlb, 2 * tlbindex + 1, 0, 0, 0); return; } @@ -889,8 +333,8 @@ static void tlb_map_entry(mips3_state *mips, int tlbindex) vpn = ((entry->entry_hi >> 13) & 0x07ffffff) << 1; if (vpn >= (1 << (MIPS3_MAX_PADDR_SHIFT - MIPS3_MIN_PAGE_SHIFT))) { - vtlb_load(mips->vtlb, 2 * tlbindex + 0, 0, 0, 0); - vtlb_load(mips->vtlb, 2 * tlbindex + 1, 0, 0, 0); + vtlb_load(m_vtlb, 2 * tlbindex + 0, 0, 0, 0); + vtlb_load(m_vtlb, 2 * tlbindex + 1, 0, 0, 0); return; } @@ -906,7 +350,7 @@ static void tlb_map_entry(mips3_state *mips, int tlbindex) UINT32 flags = 0; /* compute physical page index */ - pfn = (lo >> 6) & mips->pfnmask; + pfn = (lo >> 6) & m_pfnmask; /* valid? */ if ((lo & 2) != 0) @@ -924,9 +368,9 @@ static void tlb_map_entry(mips3_state *mips, int tlbindex) /* load the virtual TLB with the corresponding entries */ if ((effvpn + count) <= (0x80000000 >> MIPS3_MIN_PAGE_SHIFT) || effvpn >= (0xc0000000 >> MIPS3_MIN_PAGE_SHIFT)) - vtlb_load(mips->vtlb, 2 * tlbindex + which, count, effvpn << MIPS3_MIN_PAGE_SHIFT, (pfn << MIPS3_MIN_PAGE_SHIFT) | flags); + vtlb_load(m_vtlb, 2 * tlbindex + which, count, effvpn << MIPS3_MIN_PAGE_SHIFT, (pfn << MIPS3_MIN_PAGE_SHIFT) | flags); else - vtlb_load(mips->vtlb, 2 * tlbindex + which, 0, 0, 0); + vtlb_load(m_vtlb, 2 * tlbindex + which, 0, 0, 0); } } @@ -936,21 +380,21 @@ static void tlb_map_entry(mips3_state *mips, int tlbindex) a TLB entry -------------------------------------------------*/ -static void tlb_write_common(mips3_state *mips, int tlbindex) +void mips3_device::tlb_write_common(int tlbindex) { /* only handle entries within the TLB */ - if (tlbindex < mips->tlbentries) + if (tlbindex < m_tlbentries) { - mips3_tlb_entry *entry = &mips->tlb[tlbindex]; + mips3_tlb_entry *entry = &m_tlb[tlbindex]; /* fill in the new TLB entry from the COP0 registers */ - entry->page_mask = mips->cpr[0][COP0_PageMask]; - entry->entry_hi = mips->cpr[0][COP0_EntryHi] & ~(entry->page_mask & U64(0x0000000001ffe000)); - entry->entry_lo[0] = mips->cpr[0][COP0_EntryLo0]; - entry->entry_lo[1] = mips->cpr[0][COP0_EntryLo1]; + entry->page_mask = m_core->cpr[0][COP0_PageMask]; + entry->entry_hi = m_core->cpr[0][COP0_EntryHi] & ~(entry->page_mask & U64(0x0000000001ffe000)); + entry->entry_lo[0] = m_core->cpr[0][COP0_EntryLo0]; + entry->entry_lo[1] = m_core->cpr[0][COP0_EntryLo1]; /* remap this TLB entry */ - tlb_map_entry(mips, tlbindex); + tlb_map_entry(tlbindex); /* log the two halves once they are in */ tlb_entry_log_half(entry, tlbindex, 0); diff --git a/src/emu/cpu/mips/mips3com.h b/src/emu/cpu/mips/mips3com.h index ae71bc84a9b..12810f8b9a0 100644 --- a/src/emu/cpu/mips/mips3com.h +++ b/src/emu/cpu/mips/mips3com.h @@ -16,6 +16,55 @@ /*************************************************************************** + DEBUGGING +***************************************************************************/ + +#define PRINTF_TLB (0) +#define USE_ABI_REG_NAMES (1) + +#define LOG_UML (0) +#define LOG_NATIVE (0) + +#define DISABLE_FAST_REGISTERS (0) +#define SINGLE_INSTRUCTION_MODE (0) + +#define PRINTF_EXCEPTIONS (0) +#define PRINTF_MMU (0) + +#define PROBE_ADDRESS ~0 + + +/*************************************************************************** + CONSTANTS +***************************************************************************/ + +/* map variables */ +#define MAPVAR_PC M0 +#define MAPVAR_CYCLES M1 + +/* modes */ +#define MODE_KERNEL 0 +#define MODE_SUPER 1 +#define MODE_USER 2 + +/* compilation boundaries -- how far back/forward does the analysis extend? */ +#define COMPILE_BACKWARDS_BYTES 128 +#define COMPILE_FORWARDS_BYTES 512 +#define COMPILE_MAX_INSTRUCTIONS ((COMPILE_BACKWARDS_BYTES/4) + (COMPILE_FORWARDS_BYTES/4)) +#define COMPILE_MAX_SEQUENCE 64 + +/* exit codes */ +#define EXECUTE_OUT_OF_CYCLES 0 +#define EXECUTE_MISSING_CODE 1 +#define EXECUTE_UNMAPPED_CODE 2 +#define EXECUTE_RESET_CACHE 3 + + + +#define LOPTR(x) ((UINT32 *)(x) + NATIVE_ENDIAN_VALUE_LE_BE(0,1)) + + +/*************************************************************************** CONSTANTS ***************************************************************************/ @@ -24,29 +73,11 @@ #define MIPS3_MIN_PAGE_SIZE (1 << MIPS3_MIN_PAGE_SHIFT) #define MIPS3_MIN_PAGE_MASK (MIPS3_MIN_PAGE_SIZE - 1) #define MIPS3_MAX_PADDR_SHIFT 32 -#define MIPS3_MAX_TLB_ENTRIES 48 /* cycle parameters */ #define MIPS3_COUNT_READ_CYCLES 250 #define MIPS3_CAUSE_READ_CYCLES 250 -/* MIPS flavors */ -enum mips3_flavor -{ - /* MIPS III variants */ - MIPS3_TYPE_MIPS_III, - MIPS3_TYPE_VR4300, - MIPS3_TYPE_R4600, - MIPS3_TYPE_R4650, - MIPS3_TYPE_R4700, - - /* MIPS IV variants */ - MIPS3_TYPE_MIPS_IV, - MIPS3_TYPE_R5000, - MIPS3_TYPE_QED5271, - MIPS3_TYPE_RM7000 -}; - /* TLB bits */ #define TLB_GLOBAL 0x01 #define TLB_VALID 0x02 @@ -158,109 +189,4 @@ enum mips3_flavor #define LIMMVAL (op & 0x03ffffff) - -/*************************************************************************** - STRUCTURES & TYPEDEFS -***************************************************************************/ - -/* MIPS3 TLB entry */ -struct mips3_tlb_entry -{ - UINT64 page_mask; - UINT64 entry_hi; - UINT64 entry_lo[2]; -}; - - -/* forward declaration of implementation-specific state */ -struct mips3imp_state; - - -/* MIPS3 state */ -struct mips3_state -{ - /* core registers */ - UINT32 pc; - int icount; - UINT64 r[35]; - - /* COP registers */ - UINT64 cpr[3][32]; - UINT64 ccr[3][32]; - UINT32 llbit; - - /* internal stuff */ - mips3_flavor flavor; - device_irq_acknowledge_delegate irq_callback; - legacy_cpu_device * device; - address_space *program; - direct_read_data *direct; - UINT32 system_clock; - UINT32 cpu_clock; - UINT64 count_zero_time; - UINT32 compare_armed; - emu_timer * compare_int_timer; - - /* derived info based on flavor */ - UINT32 pfnmask; - UINT8 tlbentries; - - /* memory accesses */ - UINT8 bigendian; - data_accessors memory; - - /* cache memory */ - size_t icache_size; - size_t dcache_size; - - /* MMU */ - vtlb_state * vtlb; - mips3_tlb_entry tlb[MIPS3_MAX_TLB_ENTRIES]; - - /* for use by specific implementations */ - mips3imp_state *impstate; -}; - - - -/*************************************************************************** - FUNCTION PROTOTYPES -***************************************************************************/ - -void mips3com_init(mips3_state *mips, mips3_flavor flavor, int bigendian, legacy_cpu_device *device, device_irq_acknowledge_delegate irqcallback); -void mips3com_exit(mips3_state *mips); - -void mips3com_reset(mips3_state *mips); -offs_t mips3com_dasm(mips3_state *mips, char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram); -void mips3com_update_cycle_counting(mips3_state *mips); - -void mips3com_asid_changed(mips3_state *mips); -int mips3com_translate_address(mips3_state *mips, address_spacenum space, int intention, offs_t *address); -void mips3com_tlbr(mips3_state *mips); -void mips3com_tlbwi(mips3_state *mips); -void mips3com_tlbwr(mips3_state *mips); -void mips3com_tlbp(mips3_state *mips); - -void mips3com_set_info(mips3_state *mips, UINT32 state, cpuinfo *info); -void mips3com_get_info(mips3_state *mips, UINT32 state, cpuinfo *info); - - - -/*************************************************************************** - INLINE FUNCTIONS -***************************************************************************/ - -/*------------------------------------------------- - mips3com_set_irq_line - set or clear the given - IRQ line --------------------------------------------------*/ - -INLINE void mips3com_set_irq_line(mips3_state *mips, int irqline, int state) -{ - if (state != CLEAR_LINE) - mips->cpr[0][COP0_Cause] |= 0x400 << irqline; - else - mips->cpr[0][COP0_Cause] &= ~(0x400 << irqline); -} - #endif /* __MIPS3COM_H__ */ diff --git a/src/emu/cpu/mips/mips3drc.c b/src/emu/cpu/mips/mips3drc.c index ede75fdbb54..6fadf3698f1 100644 --- a/src/emu/cpu/mips/mips3drc.c +++ b/src/emu/cpu/mips/mips3drc.c @@ -35,214 +35,44 @@ extern unsigned dasmmips3(char *buffer, unsigned pc, UINT32 op); using namespace uml; -/*************************************************************************** - DEBUGGING -***************************************************************************/ - -#define LOG_UML (0) -#define LOG_NATIVE (0) - -#define DISABLE_FAST_REGISTERS (0) -#define SINGLE_INSTRUCTION_MODE (0) - -#define PRINTF_EXCEPTIONS (0) -#define PRINTF_MMU (0) - -#define PROBE_ADDRESS ~0 - - - -/*************************************************************************** - CONSTANTS -***************************************************************************/ - -/* map variables */ -#define MAPVAR_PC M0 -#define MAPVAR_CYCLES M1 - -/* modes */ -#define MODE_KERNEL 0 -#define MODE_SUPER 1 -#define MODE_USER 2 - -/* size of the execution code cache */ -#define CACHE_SIZE (32 * 1024 * 1024) - -/* compilation boundaries -- how far back/forward does the analysis extend? */ -#define COMPILE_BACKWARDS_BYTES 128 -#define COMPILE_FORWARDS_BYTES 512 -#define COMPILE_MAX_INSTRUCTIONS ((COMPILE_BACKWARDS_BYTES/4) + (COMPILE_FORWARDS_BYTES/4)) -#define COMPILE_MAX_SEQUENCE 64 - -/* exit codes */ -#define EXECUTE_OUT_OF_CYCLES 0 -#define EXECUTE_MISSING_CODE 1 -#define EXECUTE_UNMAPPED_CODE 2 -#define EXECUTE_RESET_CACHE 3 - - /*************************************************************************** MACROS ***************************************************************************/ -#define LOPTR(x) ((UINT32 *)(x) + NATIVE_ENDIAN_VALUE_LE_BE(0,1)) - -#define R32(reg) mips3->impstate->regmaplo[reg] +#define R32(reg) m_regmaplo[reg] #define LO32 R32(REG_LO) #define HI32 R32(REG_HI) -#define CPR032(reg) mem(LOPTR(&mips3->cpr[0][reg])) -#define CCR032(reg) mem(LOPTR(&mips3->ccr[0][reg])) -#define FPR32(reg) mem(((mips3->impstate->mode & 1) == 0) ? &((float *)&mips3->cpr[1][0])[reg] : (float *)&mips3->cpr[1][reg]) -#define CCR132(reg) mem(LOPTR(&mips3->ccr[1][reg])) -#define CPR232(reg) mem(LOPTR(&mips3->cpr[2][reg])) -#define CCR232(reg) mem(LOPTR(&mips3->ccr[2][reg])) - -#define R64(reg) mips3->impstate->regmap[reg] +#define CPR032(reg) mem(LOPTR(&m_core->cpr[0][reg])) +#define CCR032(reg) mem(LOPTR(&m_core->ccr[0][reg])) +#define FPR32(reg) mem(((m_core->mode & 1) == 0) ? &((float *)&m_core->cpr[1][0])[reg] : (float *)&m_core->cpr[1][reg]) +#define CCR132(reg) mem(LOPTR(&m_core->ccr[1][reg])) +#define CPR232(reg) mem(LOPTR(&m_core->cpr[2][reg])) +#define CCR232(reg) mem(LOPTR(&m_core->ccr[2][reg])) + +#define R64(reg) m_regmap[reg] #define LO64 R64(REG_LO) #define HI64 R64(REG_HI) -#define CPR064(reg) mem(&mips3->cpr[0][reg]) -#define CCR064(reg) mem(&mips3->ccr[0][reg]) -#define FPR64(reg) mem(((mips3->impstate->mode & 1) == 0) ? (double *)&mips3->cpr[1][(reg)/2] : (double *)&mips3->cpr[1][reg]) -#define CCR164(reg) mem(&mips3->ccr[1][reg]) -#define CPR264(reg) mem(&mips3->cpr[2][reg]) -#define CCR264(reg) mem(&mips3->ccr[2][reg]) - -#define FCCSHIFT(which) fcc_shift[(mips3->flavor < MIPS3_TYPE_MIPS_IV) ? 0 : ((which) & 7)] +#define CPR064(reg) mem(&m_core->cpr[0][reg]) +#define CCR064(reg) mem(&m_core->ccr[0][reg]) +#define FPR64(reg) mem(((m_core->mode & 1) == 0) ? (double *)&m_core->cpr[1][(reg)/2] : (double *)&m_core->cpr[1][reg]) +#define CCR164(reg) mem(&m_core->ccr[1][reg]) +#define CPR264(reg) mem(&m_core->cpr[2][reg]) +#define CCR264(reg) mem(&m_core->ccr[2][reg]) + +#define FCCSHIFT(which) fcc_shift[(m_flavor < MIPS3_TYPE_MIPS_IV) ? 0 : ((which) & 7)] #define FCCMASK(which) ((UINT32)(1 << FCCSHIFT(which))) /*************************************************************************** - STRUCTURES & TYPEDEFS -***************************************************************************/ - -/* fast RAM info */ -struct fast_ram_info -{ - offs_t start; /* start of the RAM block */ - offs_t end; /* end of the RAM block */ - UINT8 readonly; /* TRUE if read-only */ - void * base; /* base in memory where the RAM lives */ -}; - - -/* hotspot info */ -struct hotspot_info -{ - offs_t pc; /* PC to consider */ - UINT32 opcode; /* required opcode at that PC */ - UINT32 cycles; /* number of cycles to eat when hit */ -}; - - -/* internal compiler state */ -struct compiler_state -{ - UINT32 cycles; /* accumulated cycles */ - UINT8 checkints; /* need to check interrupts before next instruction */ - UINT8 checksoftints; /* need to check software interrupts before next instruction */ - code_label labelnum; /* index for local labels */ -}; - - -/* MIPS3 registers */ -struct mips3imp_state -{ - /* core state */ - drc_cache * cache; /* pointer to the DRC code cache */ - drcuml_state * drcuml; /* DRC UML generator state */ - mips3_frontend * drcfe; /* pointer to the DRC front-end state */ - UINT32 drcoptions; /* configurable DRC options */ - - /* internal stuff */ - UINT8 cache_dirty; /* true if we need to flush the cache */ - UINT32 jmpdest; /* destination jump target */ - - /* parameters for subroutines */ - UINT64 numcycles; /* return value from gettotalcycles */ - UINT32 mode; /* current global mode */ - const char * format; /* format string for print_debug */ - UINT32 arg0; /* print_debug argument 1 */ - UINT32 arg1; /* print_debug argument 2 */ - - /* tables */ - UINT8 fpmode[4]; /* FPU mode table */ - - /* register mappings */ - parameter regmap[34]; /* parameter to register mappings for all 32 integer registers */ - parameter regmaplo[34]; /* parameter to register mappings for all 32 integer registers */ - - /* subroutines */ - code_handle * entry; /* entry point */ - code_handle * nocode; /* nocode exception handler */ - code_handle * out_of_cycles; /* out of cycles exception handler */ - code_handle * tlb_mismatch; /* tlb mismatch handler */ - code_handle * read8[3]; /* read byte */ - code_handle * write8[3]; /* write byte */ - code_handle * read16[3]; /* read half */ - code_handle * write16[3]; /* write half */ - code_handle * read32[3]; /* read word */ - code_handle * read32mask[3]; /* read word masked */ - code_handle * write32[3]; /* write word */ - code_handle * write32mask[3]; /* write word masked */ - code_handle * read64[3]; /* read double */ - code_handle * read64mask[3]; /* read double masked */ - code_handle * write64[3]; /* write double */ - code_handle * write64mask[3]; /* write double masked */ - code_handle * exception[EXCEPTION_COUNT]; /* array of exception handlers */ - code_handle * exception_norecover[EXCEPTION_COUNT]; /* array of no-recover exception handlers */ - - /* fast RAM */ - UINT32 fastram_select; - fast_ram_info fastram[MIPS3_MAX_FASTRAM]; - - /* hotspots */ - UINT32 hotspot_select; - hotspot_info hotspot[MIPS3_MAX_HOTSPOTS]; -}; - - - -/*************************************************************************** FUNCTION PROTOTYPES ***************************************************************************/ -static void code_flush_cache(mips3_state *mips3); -static void code_compile_block(mips3_state *mips3, UINT8 mode, offs_t pc); - static void cfunc_printf_exception(void *param); static void cfunc_get_cycles(void *param); static void cfunc_printf_probe(void *param); -static void static_generate_entry_point(mips3_state *mips3); -static void static_generate_nocode_handler(mips3_state *mips3); -static void static_generate_out_of_cycles(mips3_state *mips3); -static void static_generate_tlb_mismatch(mips3_state *mips3); -static void static_generate_exception(mips3_state *mips3, UINT8 exception, int recover, const char *name); -static void static_generate_memory_accessor(mips3_state *mips3, int mode, int size, int iswrite, int ismasked, const char *name, code_handle **handleptr); - -static void generate_update_mode(mips3_state *mips3, drcuml_block *block); -static void generate_update_cycles(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, parameter param, int allow_exception); -static void generate_checksum_block(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast); -static void generate_sequence_instruction(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); -static void generate_delay_slot_and_branch(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 linkreg); -static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); -static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); -static int generate_regimm(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); -static int generate_idt(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); -static int generate_set_cop0_reg(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 reg); -static int generate_get_cop0_reg(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 reg); -static int generate_cop0(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); -static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); -static int generate_cop1x(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); - -static void log_add_disasm_comment(mips3_state *mips3, drcuml_block *block, UINT32 pc, UINT32 op); -static const char *log_desc_flags_to_string(UINT32 flags); -static void log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist); -static void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent); - - /*************************************************************************** PRIVATE GLOBAL VARIABLES @@ -251,44 +81,11 @@ static void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, i /* bit indexes for various FCCs */ static const UINT8 fcc_shift[8] = { 23, 25, 26, 27, 28, 29, 30, 31 }; -/* lookup table for FP modes */ -static const UINT8 fpmode_source[4] = -{ - ROUND_ROUND, - ROUND_TRUNC, - ROUND_CEIL, - ROUND_FLOOR -}; - - /*************************************************************************** INLINE FUNCTIONS ***************************************************************************/ -INLINE mips3_state *get_safe_token(device_t *device) -{ - assert(device != NULL); - assert(device->type() == VR4300BE_DRC || - device->type() == VR4300LE_DRC || - device->type() == VR4310BE_DRC || - device->type() == VR4310LE_DRC || - device->type() == R4600BE_DRC || - device->type() == R4600LE_DRC || - device->type() == R4650BE_DRC || - device->type() == R4650LE_DRC || - device->type() == R4700BE_DRC || - device->type() == R4700LE_DRC || - device->type() == R5000BE_DRC || - device->type() == R5000LE_DRC || - device->type() == QED5271BE_DRC || - device->type() == QED5271LE_DRC || - device->type() == RM7000BE_DRC || - device->type() == RM7000LE_DRC); - return *(mips3_state **)downcast<legacy_cpu_device *>(device)->token(); -} - - /*------------------------------------------------- epc - compute the exception PC from a descriptor @@ -317,13 +114,13 @@ INLINE void alloc_handle(drcuml_state *drcuml, code_handle **handleptr, const ch registers -------------------------------------------------*/ -INLINE void load_fast_iregs(mips3_state *mips3, drcuml_block *block) +inline void mips3_device::load_fast_iregs(drcuml_block *block) { int regnum; - for (regnum = 0; regnum < ARRAY_LENGTH(mips3->impstate->regmap); regnum++) - if (mips3->impstate->regmap[regnum].is_int_register()) - UML_DMOV(block, ireg(mips3->impstate->regmap[regnum].ireg() - REG_I0), mem(&mips3->r[regnum])); + for (regnum = 0; regnum < ARRAY_LENGTH(m_regmap); regnum++) + if (m_regmap[regnum].is_int_register()) + UML_DMOV(block, ireg(m_regmap[regnum].ireg() - REG_I0), mem(&m_core->r[regnum])); } @@ -332,13 +129,13 @@ INLINE void load_fast_iregs(mips3_state *mips3, drcuml_block *block) registers -------------------------------------------------*/ -INLINE void save_fast_iregs(mips3_state *mips3, drcuml_block *block) +inline void mips3_device::save_fast_iregs(drcuml_block *block) { int regnum; - for (regnum = 0; regnum < ARRAY_LENGTH(mips3->impstate->regmap); regnum++) - if (mips3->impstate->regmap[regnum].is_int_register()) - UML_DMOV(block, mem(&mips3->r[regnum]), ireg(mips3->impstate->regmap[regnum].ireg() - REG_I0)); + for (regnum = 0; regnum < ARRAY_LENGTH(m_regmap); regnum++) + if (m_regmap[regnum].is_int_register()) + UML_DMOV(block, mem(&m_core->r[regnum]), ireg(m_regmap[regnum].ireg() - REG_I0)); } @@ -348,266 +145,13 @@ INLINE void save_fast_iregs(mips3_state *mips3, drcuml_block *block) ***************************************************************************/ /*------------------------------------------------- - mips3_init - initialize the processor --------------------------------------------------*/ - -static void mips3_init(mips3_flavor flavor, int bigendian, legacy_cpu_device *device, device_irq_acknowledge_delegate irqcallback) -{ - mips3_state *mips3; - drc_cache *cache; - drcbe_info beinfo; - UINT32 flags = 0; - int regnum; - - /* allocate enough space for the cache and the core */ - cache = auto_alloc(device->machine(), drc_cache(CACHE_SIZE + sizeof(*mips3))); - if (cache == NULL) - fatalerror("Unable to allocate cache of size %d\n", (UINT32)(CACHE_SIZE + sizeof(*mips3))); - - /* allocate the core memory */ - *(mips3_state **)device->token() = mips3 = (mips3_state *)cache->alloc_near(sizeof(*mips3)); - memset(mips3, 0, sizeof(*mips3)); - - /* initialize the core */ - mips3com_init(mips3, flavor, bigendian, device, irqcallback); - - /* allocate the implementation-specific state from the full cache */ - mips3->impstate = (mips3imp_state *)cache->alloc_near(sizeof(*mips3->impstate)); - memset(mips3->impstate, 0, sizeof(*mips3->impstate)); - mips3->impstate->cache = cache; - - /* initialize the UML generator */ - if (LOG_UML) - flags |= DRCUML_OPTION_LOG_UML; - if (LOG_NATIVE) - flags |= DRCUML_OPTION_LOG_NATIVE; - mips3->impstate->drcuml = auto_alloc(device->machine(), drcuml_state(*device, *cache, flags, 8, 32, 2)); - - /* add symbols for our stuff */ - mips3->impstate->drcuml->symbol_add(&mips3->pc, sizeof(mips3->pc), "pc"); - mips3->impstate->drcuml->symbol_add(&mips3->icount, sizeof(mips3->icount), "icount"); - for (regnum = 0; regnum < 32; regnum++) - { - char buf[10]; - sprintf(buf, "r%d", regnum); - mips3->impstate->drcuml->symbol_add(&mips3->r[regnum], sizeof(mips3->r[regnum]), buf); - sprintf(buf, "f%d", regnum); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[1][regnum], sizeof(mips3->cpr[1][regnum]), buf); - } - mips3->impstate->drcuml->symbol_add(&mips3->r[REG_LO], sizeof(mips3->r[REG_LO]), "lo"); - mips3->impstate->drcuml->symbol_add(&mips3->r[REG_HI], sizeof(mips3->r[REG_LO]), "hi"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_Index], sizeof(mips3->cpr[0][COP0_Index]), "Index"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_Random], sizeof(mips3->cpr[0][COP0_Random]), "Random"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_EntryLo0], sizeof(mips3->cpr[0][COP0_EntryLo0]), "EntryLo0"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_EntryLo1], sizeof(mips3->cpr[0][COP0_EntryLo1]), "EntryLo1"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_Context], sizeof(mips3->cpr[0][COP0_Context]), "Context"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_PageMask], sizeof(mips3->cpr[0][COP0_PageMask]), "PageMask"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_Wired], sizeof(mips3->cpr[0][COP0_Wired]), "Wired"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_BadVAddr], sizeof(mips3->cpr[0][COP0_BadVAddr]), "BadVAddr"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_Count], sizeof(mips3->cpr[0][COP0_Count]), "Count"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_EntryHi], sizeof(mips3->cpr[0][COP0_EntryHi]), "EntryHi"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_Compare], sizeof(mips3->cpr[0][COP0_Compare]), "Compare"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_Status], sizeof(mips3->cpr[0][COP0_Status]), "Status"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_Cause], sizeof(mips3->cpr[0][COP0_Cause]), "Cause"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_EPC], sizeof(mips3->cpr[0][COP0_EPC]), "EPC"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_PRId], sizeof(mips3->cpr[0][COP0_PRId]), "PRId"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_Config], sizeof(mips3->cpr[0][COP0_Config]), "Config"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_LLAddr], sizeof(mips3->cpr[0][COP0_LLAddr]), "LLAddr"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_XContext], sizeof(mips3->cpr[0][COP0_XContext]), "XContext"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_ECC], sizeof(mips3->cpr[0][COP0_ECC]), "ECC"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_CacheErr], sizeof(mips3->cpr[0][COP0_CacheErr]), "CacheErr"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_TagLo], sizeof(mips3->cpr[0][COP0_TagLo]), "TagLo"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_TagHi], sizeof(mips3->cpr[0][COP0_TagHi]), "TagHi"); - mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_ErrorPC], sizeof(mips3->cpr[0][COP0_ErrorPC]), "ErrorPC"); - mips3->impstate->drcuml->symbol_add(&mips3->ccr[1][31], sizeof(mips3->cpr[1][31]), "fcr31"); - mips3->impstate->drcuml->symbol_add(&mips3->impstate->mode, sizeof(mips3->impstate->mode), "mode"); - mips3->impstate->drcuml->symbol_add(&mips3->impstate->arg0, sizeof(mips3->impstate->arg0), "arg0"); - mips3->impstate->drcuml->symbol_add(&mips3->impstate->arg1, sizeof(mips3->impstate->arg1), "arg1"); - mips3->impstate->drcuml->symbol_add(&mips3->impstate->numcycles, sizeof(mips3->impstate->numcycles), "numcycles"); - mips3->impstate->drcuml->symbol_add(&mips3->impstate->fpmode, sizeof(mips3->impstate->fpmode), "fpmode"); - - /* initialize the front-end helper */ - mips3->impstate->drcfe = auto_alloc(device->machine(), mips3_frontend(*mips3, COMPILE_BACKWARDS_BYTES, COMPILE_FORWARDS_BYTES, SINGLE_INSTRUCTION_MODE ? 1 : COMPILE_MAX_SEQUENCE)); - - /* allocate memory for cache-local state and initialize it */ - memcpy(mips3->impstate->fpmode, fpmode_source, sizeof(fpmode_source)); - - /* compute the register parameters */ - for (regnum = 0; regnum < 34; regnum++) - { - mips3->impstate->regmap[regnum] = (regnum == 0) ? parameter(0) : parameter::make_memory(&mips3->r[regnum]); - mips3->impstate->regmaplo[regnum] = (regnum == 0) ? parameter(0) : parameter::make_memory(LOPTR(&mips3->r[regnum])); - } - - /* if we have registers to spare, assign r2, r3, r4 to leftovers */ - if (!DISABLE_FAST_REGISTERS) - { - mips3->impstate->drcuml->get_backend_info(beinfo); - if (beinfo.direct_iregs > 4) - { - mips3->impstate->regmap[2] = I4; - mips3->impstate->regmaplo[2] = I4; - } - if (beinfo.direct_iregs > 5) - { - mips3->impstate->regmap[3] = I5; - mips3->impstate->regmaplo[3] = I5; - } - if (beinfo.direct_iregs > 6) - { - mips3->impstate->regmap[4] = I6; - mips3->impstate->regmaplo[4] = I6; - } - } - - /* mark the cache dirty so it is updated on next execute */ - mips3->impstate->cache_dirty = TRUE; -} - - -/*------------------------------------------------- - mips3_reset - reset the processor --------------------------------------------------*/ - -static CPU_RESET( mips3 ) -{ - mips3_state *mips3 = get_safe_token(device); - - /* reset the common code and mark the cache dirty */ - mips3com_reset(mips3); - mips3->impstate->mode = (MODE_KERNEL << 1) | 0; - mips3->impstate->cache_dirty = TRUE; -} - - -/*------------------------------------------------- - mips3_execute - execute the CPU for the - specified number of cycles --------------------------------------------------*/ - -static CPU_EXECUTE( mips3 ) -{ - mips3_state *mips3 = get_safe_token(device); - drcuml_state *drcuml = mips3->impstate->drcuml; - int execute_result; - - /* reset the cache if dirty */ - if (mips3->impstate->cache_dirty) - code_flush_cache(mips3); - mips3->impstate->cache_dirty = FALSE; - - /* execute */ - do - { - /* run as much as we can */ - execute_result = drcuml->execute(*mips3->impstate->entry); - - /* if we need to recompile, do it */ - if (execute_result == EXECUTE_MISSING_CODE) - code_compile_block(mips3, mips3->impstate->mode, mips3->pc); - else if (execute_result == EXECUTE_UNMAPPED_CODE) - fatalerror("Attempted to execute unmapped code at PC=%08X\n", mips3->pc); - else if (execute_result == EXECUTE_RESET_CACHE) - code_flush_cache(mips3); - - } while (execute_result != EXECUTE_OUT_OF_CYCLES); -} - - -/*------------------------------------------------- - mips3_exit - cleanup from execution --------------------------------------------------*/ - -static CPU_EXIT( mips3 ) -{ - mips3_state *mips3 = get_safe_token(device); - mips3com_exit(mips3); - - /* clean up the DRC */ - auto_free(device->machine(), mips3->impstate->drcfe); - auto_free(device->machine(), mips3->impstate->drcuml); - auto_free(device->machine(), mips3->impstate->cache); -} - - -/*------------------------------------------------- - mips3_translate - perform virtual-to-physical - address translation --------------------------------------------------*/ - -static CPU_TRANSLATE( mips3 ) -{ - mips3_state *mips3 = get_safe_token(device); - return mips3com_translate_address(mips3, space, intention, address); -} - - -/*------------------------------------------------- - mips3_dasm - disassemble an instruction --------------------------------------------------*/ - -static CPU_DISASSEMBLE( mips3 ) -{ - mips3_state *mips3 = get_safe_token(device); - return mips3com_dasm(mips3, buffer, pc, oprom, opram); -} - - -/*------------------------------------------------- - mips3_set_info - set information about a given - CPU instance --------------------------------------------------*/ - -static CPU_SET_INFO( mips3 ) -{ - mips3_state *mips3 = get_safe_token(device); - - /* --- everything is handled generically --- */ - mips3com_set_info(mips3, state, info); -} - - -/*------------------------------------------------- - mips3_get_info - return information about a - given CPU instance --------------------------------------------------*/ - -static CPU_GET_INFO( mips3 ) -{ - mips3_state *mips3 = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(mips3_state *); break; - case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(mips3); break; - case CPUINFO_FCT_INIT: /* provided per-CPU */ break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(mips3); break; - case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(mips3); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(mips3); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(mips3);break; - case CPUINFO_FCT_TRANSLATE: info->translate = CPU_TRANSLATE_NAME(mips3); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - - /* --- everything else is handled generically --- */ - default: mips3com_get_info(mips3, state, info); break; - } -} - - -/*------------------------------------------------- mips3drc_set_options - configure DRC options -------------------------------------------------*/ -void mips3drc_set_options(device_t *device, UINT32 options) +void mips3_device::mips3drc_set_options(UINT32 options) { - if (!device->machine().options().drc()) return; - mips3_state *mips3 = get_safe_token(device); - mips3->impstate->drcoptions = options; + if (!machine().options().drc()) return; + m_drcoptions = options; } @@ -616,17 +160,16 @@ void mips3drc_set_options(device_t *device, UINT32 options) region -------------------------------------------------*/ -void mips3drc_add_fastram(device_t *device, offs_t start, offs_t end, UINT8 readonly, void *base) +void mips3_device::mips3drc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base) { - if (!device->machine().options().drc()) return; - mips3_state *mips3 = get_safe_token(device); - if (mips3->impstate->fastram_select < ARRAY_LENGTH(mips3->impstate->fastram)) + if (!machine().options().drc()) return; + if (m_fastram_select < ARRAY_LENGTH(m_fastram)) { - mips3->impstate->fastram[mips3->impstate->fastram_select].start = start; - mips3->impstate->fastram[mips3->impstate->fastram_select].end = end; - mips3->impstate->fastram[mips3->impstate->fastram_select].readonly = readonly; - mips3->impstate->fastram[mips3->impstate->fastram_select].base = base; - mips3->impstate->fastram_select++; + m_fastram[m_fastram_select].start = start; + m_fastram[m_fastram_select].end = end; + m_fastram[m_fastram_select].readonly = readonly; + m_fastram[m_fastram_select].base = base; + m_fastram_select++; } } @@ -635,16 +178,15 @@ void mips3drc_add_fastram(device_t *device, offs_t start, offs_t end, UINT8 read mips3drc_add_hotspot - add a new hotspot -------------------------------------------------*/ -void mips3drc_add_hotspot(device_t *device, offs_t pc, UINT32 opcode, UINT32 cycles) +void mips3_device::mips3drc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles) { - if (!device->machine().options().drc()) return; - mips3_state *mips3 = get_safe_token(device); - if (mips3->impstate->hotspot_select < ARRAY_LENGTH(mips3->impstate->hotspot)) + if (!machine().options().drc()) return; + if (m_hotspot_select < ARRAY_LENGTH(m_hotspot)) { - mips3->impstate->hotspot[mips3->impstate->hotspot_select].pc = pc; - mips3->impstate->hotspot[mips3->impstate->hotspot_select].opcode = opcode; - mips3->impstate->hotspot[mips3->impstate->hotspot_select].cycles = cycles; - mips3->impstate->hotspot_select++; + m_hotspot[m_hotspot_select].pc = pc; + m_hotspot[m_hotspot_select].opcode = opcode; + m_hotspot[m_hotspot_select].cycles = cycles; + m_hotspot_select++; } } @@ -659,53 +201,53 @@ void mips3drc_add_hotspot(device_t *device, offs_t pc, UINT32 opcode, UINT32 cyc regenerate static code -------------------------------------------------*/ -static void code_flush_cache(mips3_state *mips3) +void mips3_device::code_flush_cache() { int mode; /* empty the transient cache contents */ - mips3->impstate->drcuml->reset(); + m_drcuml->reset(); try { /* generate the entry point and out-of-cycles handlers */ - static_generate_entry_point(mips3); - static_generate_nocode_handler(mips3); - static_generate_out_of_cycles(mips3); - static_generate_tlb_mismatch(mips3); + static_generate_entry_point(); + static_generate_nocode_handler(); + static_generate_out_of_cycles(); + static_generate_tlb_mismatch(); /* append exception handlers for various types */ - static_generate_exception(mips3, EXCEPTION_INTERRUPT, TRUE, "exception_interrupt"); - static_generate_exception(mips3, EXCEPTION_INTERRUPT, FALSE, "exception_interrupt_norecover"); - static_generate_exception(mips3, EXCEPTION_TLBMOD, TRUE, "exception_tlbmod"); - static_generate_exception(mips3, EXCEPTION_TLBLOAD, TRUE, "exception_tlbload"); - static_generate_exception(mips3, EXCEPTION_TLBSTORE, TRUE, "exception_tlbstore"); - static_generate_exception(mips3, EXCEPTION_TLBLOAD_FILL, TRUE, "exception_tlbload_fill"); - static_generate_exception(mips3, EXCEPTION_TLBSTORE_FILL, TRUE, "exception_tlbstore_fill"); - static_generate_exception(mips3, EXCEPTION_ADDRLOAD, TRUE, "exception_addrload"); - static_generate_exception(mips3, EXCEPTION_ADDRSTORE, TRUE, "exception_addrstore"); - static_generate_exception(mips3, EXCEPTION_SYSCALL, TRUE, "exception_syscall"); - static_generate_exception(mips3, EXCEPTION_BREAK, TRUE, "exception_break"); - static_generate_exception(mips3, EXCEPTION_INVALIDOP, TRUE, "exception_invalidop"); - static_generate_exception(mips3, EXCEPTION_BADCOP, TRUE, "exception_badcop"); - static_generate_exception(mips3, EXCEPTION_OVERFLOW, TRUE, "exception_overflow"); - static_generate_exception(mips3, EXCEPTION_TRAP, TRUE, "exception_trap"); + static_generate_exception(EXCEPTION_INTERRUPT, TRUE, "exception_interrupt"); + static_generate_exception(EXCEPTION_INTERRUPT, FALSE, "exception_interrupt_norecover"); + static_generate_exception(EXCEPTION_TLBMOD, TRUE, "exception_tlbmod"); + static_generate_exception(EXCEPTION_TLBLOAD, TRUE, "exception_tlbload"); + static_generate_exception(EXCEPTION_TLBSTORE, TRUE, "exception_tlbstore"); + static_generate_exception(EXCEPTION_TLBLOAD_FILL, TRUE, "exception_tlbload_fill"); + static_generate_exception(EXCEPTION_TLBSTORE_FILL, TRUE, "exception_tlbstore_fill"); + static_generate_exception(EXCEPTION_ADDRLOAD, TRUE, "exception_addrload"); + static_generate_exception(EXCEPTION_ADDRSTORE, TRUE, "exception_addrstore"); + static_generate_exception(EXCEPTION_SYSCALL, TRUE, "exception_syscall"); + static_generate_exception(EXCEPTION_BREAK, TRUE, "exception_break"); + static_generate_exception(EXCEPTION_INVALIDOP, TRUE, "exception_invalidop"); + static_generate_exception(EXCEPTION_BADCOP, TRUE, "exception_badcop"); + static_generate_exception(EXCEPTION_OVERFLOW, TRUE, "exception_overflow"); + static_generate_exception(EXCEPTION_TRAP, TRUE, "exception_trap"); /* add subroutines for memory accesses */ for (mode = 0; mode < 3; mode++) { - static_generate_memory_accessor(mips3, mode, 1, FALSE, FALSE, "read8", &mips3->impstate->read8[mode]); - static_generate_memory_accessor(mips3, mode, 1, TRUE, FALSE, "write8", &mips3->impstate->write8[mode]); - static_generate_memory_accessor(mips3, mode, 2, FALSE, FALSE, "read16", &mips3->impstate->read16[mode]); - static_generate_memory_accessor(mips3, mode, 2, TRUE, FALSE, "write16", &mips3->impstate->write16[mode]); - static_generate_memory_accessor(mips3, mode, 4, FALSE, FALSE, "read32", &mips3->impstate->read32[mode]); - static_generate_memory_accessor(mips3, mode, 4, FALSE, TRUE, "read32mask", &mips3->impstate->read32mask[mode]); - static_generate_memory_accessor(mips3, mode, 4, TRUE, FALSE, "write32", &mips3->impstate->write32[mode]); - static_generate_memory_accessor(mips3, mode, 4, TRUE, TRUE, "write32mask", &mips3->impstate->write32mask[mode]); - static_generate_memory_accessor(mips3, mode, 8, FALSE, FALSE, "read64", &mips3->impstate->read64[mode]); - static_generate_memory_accessor(mips3, mode, 8, FALSE, TRUE, "read64mask", &mips3->impstate->read64mask[mode]); - static_generate_memory_accessor(mips3, mode, 8, TRUE, FALSE, "write64", &mips3->impstate->write64[mode]); - static_generate_memory_accessor(mips3, mode, 8, TRUE, TRUE, "write64mask", &mips3->impstate->write64mask[mode]); + static_generate_memory_accessor(mode, 1, FALSE, FALSE, "read8", &m_read8[mode]); + static_generate_memory_accessor(mode, 1, TRUE, FALSE, "write8", &m_write8[mode]); + static_generate_memory_accessor(mode, 2, FALSE, FALSE, "read16", &m_read16[mode]); + static_generate_memory_accessor(mode, 2, TRUE, FALSE, "write16", &m_write16[mode]); + static_generate_memory_accessor(mode, 4, FALSE, FALSE, "read32", &m_read32[mode]); + static_generate_memory_accessor(mode, 4, FALSE, TRUE, "read32mask", &m_read32mask[mode]); + static_generate_memory_accessor(mode, 4, TRUE, FALSE, "write32", &m_write32[mode]); + static_generate_memory_accessor(mode, 4, TRUE, TRUE, "write32mask", &m_write32mask[mode]); + static_generate_memory_accessor(mode, 8, FALSE, FALSE, "read64", &m_read64[mode]); + static_generate_memory_accessor(mode, 8, FALSE, TRUE, "read64mask", &m_read64mask[mode]); + static_generate_memory_accessor(mode, 8, TRUE, FALSE, "write64", &m_write64[mode]); + static_generate_memory_accessor(mode, 8, TRUE, TRUE, "write64mask", &m_write64mask[mode]); } } catch (drcuml_block::abort_compilation &) @@ -720,9 +262,9 @@ static void code_flush_cache(mips3_state *mips3) given mode at the specified pc -------------------------------------------------*/ -static void code_compile_block(mips3_state *mips3, UINT8 mode, offs_t pc) +void mips3_device::code_compile_block(UINT8 mode, offs_t pc) { - drcuml_state *drcuml = mips3->impstate->drcuml; + drcuml_state *drcuml = m_drcuml; compiler_state compiler = { 0 }; const opcode_desc *seqhead, *seqlast; const opcode_desc *desclist; @@ -732,7 +274,7 @@ static void code_compile_block(mips3_state *mips3, UINT8 mode, offs_t pc) g_profiler.start(PROFILER_DRC_COMPILE); /* get a description of this sequence */ - desclist = mips3->impstate->drcfe->describe_code(pc); + desclist = m_drcfe->describe_code(pc); if (LOG_UML || LOG_NATIVE) log_opcode_desc(drcuml, desclist, 0); @@ -777,14 +319,14 @@ static void code_compile_block(mips3_state *mips3, UINT8 mode, offs_t pc) else { UML_LABEL(block, seqhead->pc | 0x80000000); // label seqhead->pc | 0x80000000 - UML_HASHJMP(block, mips3->impstate->mode, seqhead->pc, *mips3->impstate->nocode); + UML_HASHJMP(block, m_core->mode, seqhead->pc, *m_nocode); // hashjmp <mode>,seqhead->pc,nocode continue; } /* validate this code block if we're not pointing into ROM */ - if (mips3->program->get_write_ptr(seqhead->physpc) != NULL) - generate_checksum_block(mips3, block, &compiler, seqhead, seqlast); + if (m_program->get_write_ptr(seqhead->physpc) != NULL) + generate_checksum_block(block, &compiler, seqhead, seqlast); /* label this instruction, if it may be jumped to locally */ if (seqhead->flags & OPFLAG_IS_BRANCH_TARGET) @@ -792,7 +334,7 @@ static void code_compile_block(mips3_state *mips3, UINT8 mode, offs_t pc) /* iterate over instructions in the sequence and compile them */ for (curdesc = seqhead; curdesc != seqlast->next(); curdesc = curdesc->next()) - generate_sequence_instruction(mips3, block, &compiler, curdesc); + generate_sequence_instruction(block, &compiler, curdesc); /* if we need to return to the start, do it */ if (seqlast->flags & OPFLAG_RETURN_TO_START) @@ -803,14 +345,14 @@ static void code_compile_block(mips3_state *mips3, UINT8 mode, offs_t pc) nextpc = seqlast->pc + (seqlast->skipslots + 1) * 4; /* count off cycles and go there */ - generate_update_cycles(mips3, block, &compiler, nextpc, TRUE); // <subtract cycles> + generate_update_cycles(block, &compiler, nextpc, TRUE); // <subtract cycles> /* if the last instruction can change modes, use a variable mode; otherwise, assume the same mode */ if (seqlast->flags & OPFLAG_CAN_CHANGE_MODES) - UML_HASHJMP(block, mem(&mips3->impstate->mode), nextpc, *mips3->impstate->nocode); + UML_HASHJMP(block, mem(&m_core->mode), nextpc, *m_nocode); // hashjmp <mode>,nextpc,nocode else if (seqlast->next() == NULL || seqlast->next()->pc != nextpc) - UML_HASHJMP(block, mips3->impstate->mode, nextpc, *mips3->impstate->nocode); + UML_HASHJMP(block, m_core->mode, nextpc, *m_nocode); // hashjmp <mode>,nextpc,nocode } @@ -821,7 +363,7 @@ static void code_compile_block(mips3_state *mips3, UINT8 mode, offs_t pc) } catch (drcuml_block::abort_compilation &) { - code_flush_cache(mips3); + code_flush_cache(); } } } @@ -832,15 +374,49 @@ static void code_compile_block(mips3_state *mips3, UINT8 mode, offs_t pc) C FUNCTION CALLBACKS ***************************************************************************/ +static void cfunc_mips3com_update_cycle_counting(void *param) +{ + ((mips3_device *)param)->mips3com_update_cycle_counting(); +} + +static void cfunc_mips3com_asid_changed(void *param) +{ + ((mips3_device *)param)->mips3com_asid_changed(); +} + +static void cfunc_mips3com_tlbr(void *param) +{ + ((mips3_device *)param)->mips3com_tlbr(); +} + +static void cfunc_mips3com_tlbwi(void *param) +{ + ((mips3_device *)param)->mips3com_tlbwi(); +} + +static void cfunc_mips3com_tlbwr(void *param) +{ + ((mips3_device *)param)->mips3com_tlbwr(); +} + +static void cfunc_mips3com_tlbp(void *param) +{ + ((mips3_device *)param)->mips3com_tlbp(); +} + /*------------------------------------------------- cfunc_get_cycles - compute the total number of cycles executed so far -------------------------------------------------*/ +void mips3_device::func_get_cycles() +{ + m_core->numcycles = total_cycles(); +} + static void cfunc_get_cycles(void *param) { - mips3_state *mips3 = (mips3_state *)param; - mips3->impstate->numcycles = mips3->device->total_cycles(); + ((mips3_device *)param)->func_get_cycles(); } @@ -849,23 +425,30 @@ static void cfunc_get_cycles(void *param) aren't interrupts -------------------------------------------------*/ -static void cfunc_printf_exception(void *param) +void mips3_device::func_printf_exception() { - mips3_state *mips3 = (mips3_state *)param; - printf("Exception: EPC=%08X Cause=%08X BadVAddr=%08X Jmp=%08X\n", (UINT32)mips3->cpr[0][COP0_EPC], (UINT32)mips3->cpr[0][COP0_Cause], (UINT32)mips3->cpr[0][COP0_BadVAddr], mips3->pc); - cfunc_printf_probe(mips3); + printf("Exception: EPC=%08X Cause=%08X BadVAddr=%08X Jmp=%08X\n", (UINT32)m_core->cpr[0][COP0_EPC], (UINT32)m_core->cpr[0][COP0_Cause], (UINT32)m_core->cpr[0][COP0_BadVAddr], m_core->pc); + func_printf_probe(); } +static void cfunc_printf_exception(void *param) +{ + ((mips3_device *)param)->func_printf_exception(); +} /*------------------------------------------------- cfunc_printf_debug - generic printf for debugging -------------------------------------------------*/ +void mips3_device::func_printf_debug() +{ + printf(m_core->format, m_core->arg0, m_core->arg1); +} + static void cfunc_printf_debug(void *param) { - mips3_state *mips3 = (mips3_state *)param; - printf(mips3->impstate->format, mips3->impstate->arg0, mips3->impstate->arg1); + ((mips3_device *)param)->func_printf_debug(); } @@ -874,68 +457,73 @@ static void cfunc_printf_debug(void *param) state and return -------------------------------------------------*/ -static void cfunc_printf_probe(void *param) +void mips3_device::func_printf_probe() { - mips3_state *mips3 = (mips3_state *)param; - printf(" PC=%08X r1=%08X%08X r2=%08X%08X r3=%08X%08X\n", - mips3->pc, - (UINT32)(mips3->r[1] >> 32), (UINT32)mips3->r[1], - (UINT32)(mips3->r[2] >> 32), (UINT32)mips3->r[2], - (UINT32)(mips3->r[3] >> 32), (UINT32)mips3->r[3]); + m_core->pc, + (UINT32)(m_core->r[1] >> 32), (UINT32)m_core->r[1], + (UINT32)(m_core->r[2] >> 32), (UINT32)m_core->r[2], + (UINT32)(m_core->r[3] >> 32), (UINT32)m_core->r[3]); printf(" r4=%08X%08X r5=%08X%08X r6=%08X%08X r7=%08X%08X\n", - (UINT32)(mips3->r[4] >> 32), (UINT32)mips3->r[4], - (UINT32)(mips3->r[5] >> 32), (UINT32)mips3->r[5], - (UINT32)(mips3->r[6] >> 32), (UINT32)mips3->r[6], - (UINT32)(mips3->r[7] >> 32), (UINT32)mips3->r[7]); + (UINT32)(m_core->r[4] >> 32), (UINT32)m_core->r[4], + (UINT32)(m_core->r[5] >> 32), (UINT32)m_core->r[5], + (UINT32)(m_core->r[6] >> 32), (UINT32)m_core->r[6], + (UINT32)(m_core->r[7] >> 32), (UINT32)m_core->r[7]); printf(" r8=%08X%08X r9=%08X%08X r10=%08X%08X r11=%08X%08X\n", - (UINT32)(mips3->r[8] >> 32), (UINT32)mips3->r[8], - (UINT32)(mips3->r[9] >> 32), (UINT32)mips3->r[9], - (UINT32)(mips3->r[10] >> 32), (UINT32)mips3->r[10], - (UINT32)(mips3->r[11] >> 32), (UINT32)mips3->r[11]); + (UINT32)(m_core->r[8] >> 32), (UINT32)m_core->r[8], + (UINT32)(m_core->r[9] >> 32), (UINT32)m_core->r[9], + (UINT32)(m_core->r[10] >> 32), (UINT32)m_core->r[10], + (UINT32)(m_core->r[11] >> 32), (UINT32)m_core->r[11]); printf("r12=%08X%08X r13=%08X%08X r14=%08X%08X r15=%08X%08X\n", - (UINT32)(mips3->r[12] >> 32), (UINT32)mips3->r[12], - (UINT32)(mips3->r[13] >> 32), (UINT32)mips3->r[13], - (UINT32)(mips3->r[14] >> 32), (UINT32)mips3->r[14], - (UINT32)(mips3->r[15] >> 32), (UINT32)mips3->r[15]); + (UINT32)(m_core->r[12] >> 32), (UINT32)m_core->r[12], + (UINT32)(m_core->r[13] >> 32), (UINT32)m_core->r[13], + (UINT32)(m_core->r[14] >> 32), (UINT32)m_core->r[14], + (UINT32)(m_core->r[15] >> 32), (UINT32)m_core->r[15]); printf("r16=%08X%08X r17=%08X%08X r18=%08X%08X r19=%08X%08X\n", - (UINT32)(mips3->r[16] >> 32), (UINT32)mips3->r[16], - (UINT32)(mips3->r[17] >> 32), (UINT32)mips3->r[17], - (UINT32)(mips3->r[18] >> 32), (UINT32)mips3->r[18], - (UINT32)(mips3->r[19] >> 32), (UINT32)mips3->r[19]); + (UINT32)(m_core->r[16] >> 32), (UINT32)m_core->r[16], + (UINT32)(m_core->r[17] >> 32), (UINT32)m_core->r[17], + (UINT32)(m_core->r[18] >> 32), (UINT32)m_core->r[18], + (UINT32)(m_core->r[19] >> 32), (UINT32)m_core->r[19]); printf("r20=%08X%08X r21=%08X%08X r22=%08X%08X r23=%08X%08X\n", - (UINT32)(mips3->r[20] >> 32), (UINT32)mips3->r[20], - (UINT32)(mips3->r[21] >> 32), (UINT32)mips3->r[21], - (UINT32)(mips3->r[22] >> 32), (UINT32)mips3->r[22], - (UINT32)(mips3->r[23] >> 32), (UINT32)mips3->r[23]); + (UINT32)(m_core->r[20] >> 32), (UINT32)m_core->r[20], + (UINT32)(m_core->r[21] >> 32), (UINT32)m_core->r[21], + (UINT32)(m_core->r[22] >> 32), (UINT32)m_core->r[22], + (UINT32)(m_core->r[23] >> 32), (UINT32)m_core->r[23]); printf("r24=%08X%08X r25=%08X%08X r26=%08X%08X r27=%08X%08X\n", - (UINT32)(mips3->r[24] >> 32), (UINT32)mips3->r[24], - (UINT32)(mips3->r[25] >> 32), (UINT32)mips3->r[25], - (UINT32)(mips3->r[26] >> 32), (UINT32)mips3->r[26], - (UINT32)(mips3->r[27] >> 32), (UINT32)mips3->r[27]); + (UINT32)(m_core->r[24] >> 32), (UINT32)m_core->r[24], + (UINT32)(m_core->r[25] >> 32), (UINT32)m_core->r[25], + (UINT32)(m_core->r[26] >> 32), (UINT32)m_core->r[26], + (UINT32)(m_core->r[27] >> 32), (UINT32)m_core->r[27]); printf("r28=%08X%08X r29=%08X%08X r30=%08X%08X r31=%08X%08X\n", - (UINT32)(mips3->r[28] >> 32), (UINT32)mips3->r[28], - (UINT32)(mips3->r[29] >> 32), (UINT32)mips3->r[29], - (UINT32)(mips3->r[30] >> 32), (UINT32)mips3->r[30], - (UINT32)(mips3->r[31] >> 32), (UINT32)mips3->r[31]); + (UINT32)(m_core->r[28] >> 32), (UINT32)m_core->r[28], + (UINT32)(m_core->r[29] >> 32), (UINT32)m_core->r[29], + (UINT32)(m_core->r[30] >> 32), (UINT32)m_core->r[30], + (UINT32)(m_core->r[31] >> 32), (UINT32)m_core->r[31]); printf(" hi=%08X%08X lo=%08X%08X\n", - (UINT32)(mips3->r[REG_HI] >> 32), (UINT32)mips3->r[REG_HI], - (UINT32)(mips3->r[REG_LO] >> 32), (UINT32)mips3->r[REG_LO]); + (UINT32)(m_core->r[REG_HI] >> 32), (UINT32)m_core->r[REG_HI], + (UINT32)(m_core->r[REG_LO] >> 32), (UINT32)m_core->r[REG_LO]); } +static void cfunc_printf_probe(void *param) +{ + ((mips3_device *)param)->func_printf_probe(); +} /*------------------------------------------------- cfunc_unimplemented - handler for unimplemented opcdes -------------------------------------------------*/ -static void cfunc_unimplemented(void *param) +void mips3_device::func_unimplemented() { - mips3_state *mips3 = (mips3_state *)param; - UINT32 opcode = mips3->impstate->arg0; - fatalerror("PC=%08X: Unimplemented op %08X (%02X,%02X)\n", mips3->pc, opcode, opcode >> 26, opcode & 0x3f); + UINT32 opcode = m_core->arg0; + fatalerror("PC=%08X: Unimplemented op %08X (%02X,%02X)\n", m_core->pc, opcode, opcode >> 26, opcode & 0x3f); } +static void cfunc_unimplemented(void *param) +{ + ((mips3_device *)param)->func_unimplemented(); +} /*************************************************************************** @@ -947,28 +535,28 @@ static void cfunc_unimplemented(void *param) static entry point -------------------------------------------------*/ -static void static_generate_entry_point(mips3_state *mips3) +void mips3_device::static_generate_entry_point() { - drcuml_state *drcuml = mips3->impstate->drcuml; + drcuml_state *drcuml = m_drcuml; code_label skip = 1; drcuml_block *block; block = drcuml->begin_block(20); /* forward references */ - alloc_handle(drcuml, &mips3->impstate->exception_norecover[EXCEPTION_INTERRUPT], "interrupt_norecover"); - alloc_handle(drcuml, &mips3->impstate->nocode, "nocode"); + alloc_handle(drcuml, &m_exception_norecover[EXCEPTION_INTERRUPT], "interrupt_norecover"); + alloc_handle(drcuml, &m_nocode, "nocode"); - alloc_handle(drcuml, &mips3->impstate->entry, "entry"); - UML_HANDLE(block, *mips3->impstate->entry); // handle entry + alloc_handle(drcuml, &m_entry, "entry"); + UML_HANDLE(block, *m_entry); // handle entry /* reset the FPU mode */ UML_AND(block, I0, CCR132(31), 3); // and i0,ccr1[31],3 - UML_LOAD(block, I0, &mips3->impstate->fpmode[0], I0, SIZE_BYTE, SCALE_x1);// load i0,fpmode,i0,byte + UML_LOAD(block, I0, &m_fpmode[0], I0, SIZE_BYTE, SCALE_x1);// load i0,fpmode,i0,byte UML_SETFMOD(block, I0); // setfmod i0 /* load fast integer registers */ - load_fast_iregs(mips3, block); + load_fast_iregs(block); /* check for interrupts */ UML_AND(block, I0, CPR032(COP0_Cause), CPR032(COP0_Status)); // and i0,[Cause],[Status] @@ -978,13 +566,13 @@ static void static_generate_entry_point(mips3_state *mips3) UML_JMPc(block, COND_Z, skip); // jmp skip,Z UML_TEST(block, CPR032(COP0_Status), SR_EXL | SR_ERL); // test [Status],SR_EXL | SR_ERL UML_JMPc(block, COND_NZ, skip); // jmp skip,NZ - UML_MOV(block, I0, mem(&mips3->pc)); // mov i0,pc + UML_MOV(block, I0, mem(&m_core->pc)); // mov i0,pc UML_MOV(block, I1, 0); // mov i1,0 - UML_CALLH(block, *mips3->impstate->exception_norecover[EXCEPTION_INTERRUPT]); // callh exception_norecover + UML_CALLH(block, *m_exception_norecover[EXCEPTION_INTERRUPT]); // callh exception_norecover UML_LABEL(block, skip); // skip: /* generate a hash jump via the current mode and PC */ - UML_HASHJMP(block, mem(&mips3->impstate->mode), mem(&mips3->pc), *mips3->impstate->nocode); + UML_HASHJMP(block, mem(&m_core->mode), mem(&m_core->pc), *m_nocode); // hashjmp <mode>,<pc>,nocode block->end(); } @@ -995,20 +583,20 @@ static void static_generate_entry_point(mips3_state *mips3) exception handler for "out of code" -------------------------------------------------*/ -static void static_generate_nocode_handler(mips3_state *mips3) +void mips3_device::static_generate_nocode_handler() { - drcuml_state *drcuml = mips3->impstate->drcuml; + drcuml_state *drcuml = m_drcuml; drcuml_block *block; /* begin generating */ block = drcuml->begin_block(10); /* generate a hash jump via the current mode and PC */ - alloc_handle(drcuml, &mips3->impstate->nocode, "nocode"); - UML_HANDLE(block, *mips3->impstate->nocode); // handle nocode + alloc_handle(drcuml, &m_nocode, "nocode"); + UML_HANDLE(block, *m_nocode); // handle nocode UML_GETEXP(block, I0); // getexp i0 - UML_MOV(block, mem(&mips3->pc), I0); // mov [pc],i0 - save_fast_iregs(mips3, block); + UML_MOV(block, mem(&m_core->pc), I0); // mov [pc],i0 + save_fast_iregs(block); UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE block->end(); @@ -1020,20 +608,20 @@ static void static_generate_nocode_handler(mips3_state *mips3) out of cycles exception handler -------------------------------------------------*/ -static void static_generate_out_of_cycles(mips3_state *mips3) +void mips3_device::static_generate_out_of_cycles() { - drcuml_state *drcuml = mips3->impstate->drcuml; + drcuml_state *drcuml = m_drcuml; drcuml_block *block; /* begin generating */ block = drcuml->begin_block(10); /* generate a hash jump via the current mode and PC */ - alloc_handle(drcuml, &mips3->impstate->out_of_cycles, "out_of_cycles"); - UML_HANDLE(block, *mips3->impstate->out_of_cycles); // handle out_of_cycles + alloc_handle(drcuml, &m_out_of_cycles, "out_of_cycles"); + UML_HANDLE(block, *m_out_of_cycles); // handle out_of_cycles UML_GETEXP(block, I0); // getexp i0 - UML_MOV(block, mem(&mips3->pc), I0); // mov <pc>,i0 - save_fast_iregs(mips3, block); + UML_MOV(block, mem(&m_core->pc), I0); // mov <pc>,i0 + save_fast_iregs(block); UML_EXIT(block, EXECUTE_OUT_OF_CYCLES); // exit EXECUTE_OUT_OF_CYCLES block->end(); @@ -1045,45 +633,45 @@ static void static_generate_out_of_cycles(mips3_state *mips3) TLB mismatch handler -------------------------------------------------*/ -static void static_generate_tlb_mismatch(mips3_state *mips3) +void mips3_device::static_generate_tlb_mismatch() { - drcuml_state *drcuml = mips3->impstate->drcuml; + drcuml_state *drcuml = m_drcuml; drcuml_block *block; /* forward references */ - alloc_handle(drcuml, &mips3->impstate->exception[EXCEPTION_TLBLOAD], "exception_tlbload"); - alloc_handle(drcuml, &mips3->impstate->exception[EXCEPTION_TLBLOAD_FILL], "exception_tlbload_fill"); + alloc_handle(drcuml, &m_exception[EXCEPTION_TLBLOAD], "exception_tlbload"); + alloc_handle(drcuml, &m_exception[EXCEPTION_TLBLOAD_FILL], "exception_tlbload_fill"); /* begin generating */ block = drcuml->begin_block(20); /* generate a hash jump via the current mode and PC */ - alloc_handle(drcuml, &mips3->impstate->tlb_mismatch, "tlb_mismatch"); - UML_HANDLE(block, *mips3->impstate->tlb_mismatch); // handle tlb_mismatch + alloc_handle(drcuml, &m_tlb_mismatch, "tlb_mismatch"); + UML_HANDLE(block, *m_tlb_mismatch); // handle tlb_mismatch UML_RECOVER(block, I0, MAPVAR_PC); // recover i0,PC - UML_MOV(block, mem(&mips3->pc), I0); // mov <pc>,i0 + UML_MOV(block, mem(&m_core->pc), I0); // mov <pc>,i0 UML_SHR(block, I1, I0, 12); // shr i1,i0,12 - UML_LOAD(block, I1, (void *)vtlb_table(mips3->vtlb), I1, SIZE_DWORD, SCALE_x4);// load i1,[vtlb_table],i1,dword + UML_LOAD(block, I1, (void *)vtlb_table(m_vtlb), I1, SIZE_DWORD, SCALE_x4);// load i1,[vtlb_table],i1,dword if (PRINTF_MMU) { static const char text[] = "TLB mismatch @ %08X (ent=%08X)\n"; - UML_MOV(block, mem(&mips3->impstate->format), (FPTR)text); // mov [format],text - UML_MOV(block, mem(&mips3->impstate->arg0), I0); // mov [arg0],i0 - UML_MOV(block, mem(&mips3->impstate->arg1), I1); // mov [arg1],i1 - UML_CALLC(block, cfunc_printf_debug, mips3); // callc printf_debug + UML_MOV(block, mem(&m_core->format), (FPTR)text); // mov [format],text + UML_MOV(block, mem(&m_core->arg0), I0); // mov [arg0],i0 + UML_MOV(block, mem(&m_core->arg1), I1); // mov [arg1],i1 + UML_CALLC(block, cfunc_printf_debug, this); // callc printf_debug } UML_TEST(block, I1, VTLB_FETCH_ALLOWED); // test i1,VTLB_FETCH_ALLOWED UML_JMPc(block, COND_NZ, 1); // jmp 1,nz UML_TEST(block, I1, VTLB_FLAG_FIXED); // test i1,VTLB_FLAG_FIXED - UML_EXHc(block, COND_NZ, *mips3->impstate->exception[EXCEPTION_TLBLOAD], I0); // exh exception[TLBLOAD],i0,nz - UML_EXH(block, *mips3->impstate->exception[EXCEPTION_TLBLOAD_FILL], I0); // exh exception[TLBLOAD_FILL],i0 + UML_EXHc(block, COND_NZ, *m_exception[EXCEPTION_TLBLOAD], I0); // exh exception[TLBLOAD],i0,nz + UML_EXH(block, *m_exception[EXCEPTION_TLBLOAD_FILL], I0); // exh exception[TLBLOAD_FILL],i0 UML_LABEL(block, 1); // 1: - save_fast_iregs(mips3, block); + save_fast_iregs(block); // the saved PC may be set 1 instruction back with the low bit set to indicate // a delay slot; in this path we want the original instruction address, so recover it - UML_ADD(block, I0, mem(&mips3->pc), 3); // add i0,<pc>,3 - UML_AND(block, mem(&mips3->pc), I0, ~3); // and <pc>,i0,~3 + UML_ADD(block, I0, mem(&m_core->pc), 3); // add i0,<pc>,3 + UML_AND(block, mem(&m_core->pc), I0, ~3); // and <pc>,i0,~3 UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE block->end(); @@ -1095,10 +683,10 @@ static void static_generate_tlb_mismatch(mips3_state *mips3) exception handler -------------------------------------------------*/ -static void static_generate_exception(mips3_state *mips3, UINT8 exception, int recover, const char *name) +void mips3_device::static_generate_exception(UINT8 exception, int recover, const char *name) { - code_handle *&exception_handle = recover ? mips3->impstate->exception[exception] : mips3->impstate->exception_norecover[exception]; - drcuml_state *drcuml = mips3->impstate->drcuml; + code_handle *&exception_handle = recover ? m_exception[exception] : m_exception_norecover[exception]; + drcuml_state *drcuml = m_drcuml; UINT32 offset = 0x180; code_label next = 1; code_label skip = 2; @@ -1163,13 +751,13 @@ static void static_generate_exception(mips3_state *mips3, UINT8 exception, int r /* set EXL in the SR */ UML_OR(block, I0, CPR032(COP0_Status), SR_EXL); // or i0,[Status],SR_EXL UML_MOV(block, CPR032(COP0_Status), I0); // mov [Status],i0 - generate_update_mode(mips3, block); + generate_update_mode(block); /* optionally print exceptions */ if ((PRINTF_EXCEPTIONS && exception != EXCEPTION_INTERRUPT && exception != EXCEPTION_SYSCALL) || (PRINTF_MMU && (exception == EXCEPTION_TLBLOAD || exception == EXCEPTION_TLBSTORE))) { - UML_CALLC(block, cfunc_printf_exception, mips3); // callc cfunc_printf_exception,NULL + UML_CALLC(block, cfunc_printf_exception, this); // callc cfunc_printf_exception,NULL } /* choose our target PC */ @@ -1180,10 +768,10 @@ static void static_generate_exception(mips3_state *mips3, UINT8 exception, int r UML_LABEL(block, skip); // <skip>: /* adjust cycles */ - UML_SUB(block, mem(&mips3->icount), mem(&mips3->icount), I1); // sub icount,icount,cycles,S - UML_EXHc(block, COND_S, *mips3->impstate->out_of_cycles, I0); // exh out_of_cycles,i0 + UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), I1); // sub icount,icount,cycles,S + UML_EXHc(block, COND_S, *m_out_of_cycles, I0); // exh out_of_cycles,i0 - UML_HASHJMP(block, mem(&mips3->impstate->mode), I0, *mips3->impstate->nocode);// hashjmp <mode>,i0,nocode + UML_HASHJMP(block, mem(&m_core->mode), I0, *m_nocode);// hashjmp <mode>,i0,nocode block->end(); } @@ -1193,15 +781,15 @@ static void static_generate_exception(mips3_state *mips3, UINT8 exception, int r static_generate_memory_accessor ------------------------------------------------------------------*/ -static void static_generate_memory_accessor(mips3_state *mips3, int mode, int size, int iswrite, int ismasked, const char *name, code_handle **handleptr) +void mips3_device::static_generate_memory_accessor(int mode, int size, int iswrite, int ismasked, const char *name, code_handle **handleptr) { /* on entry, address is in I0; data for writes is in I1; mask for accesses is in I2 */ /* on exit, read result is in I0 */ /* routine trashes I0-I3 */ - code_handle &exception_tlb = *mips3->impstate->exception[iswrite ? EXCEPTION_TLBSTORE : EXCEPTION_TLBLOAD]; - code_handle &exception_tlbfill = *mips3->impstate->exception[iswrite ? EXCEPTION_TLBSTORE_FILL : EXCEPTION_TLBLOAD_FILL]; - code_handle &exception_addrerr = *mips3->impstate->exception[iswrite ? EXCEPTION_ADDRSTORE : EXCEPTION_ADDRLOAD]; - drcuml_state *drcuml = mips3->impstate->drcuml; + code_handle &exception_tlb = *m_exception[iswrite ? EXCEPTION_TLBSTORE : EXCEPTION_TLBLOAD]; + code_handle &exception_tlbfill = *m_exception[iswrite ? EXCEPTION_TLBSTORE_FILL : EXCEPTION_TLBLOAD_FILL]; + code_handle &exception_addrerr = *m_exception[iswrite ? EXCEPTION_ADDRSTORE : EXCEPTION_ADDRLOAD]; + drcuml_state *drcuml = m_drcuml; drcuml_block *block; int tlbmiss = 0; int label = 1; @@ -1235,25 +823,25 @@ static void static_generate_memory_accessor(mips3_state *mips3, int mode, int si /* general case: assume paging and perform a translation */ UML_SHR(block, I3, I0, 12); // shr i3,i0,12 - UML_LOAD(block, I3, (void *)vtlb_table(mips3->vtlb), I3, SIZE_DWORD, SCALE_x4);// load i3,[vtlb_table],i3,dword + UML_LOAD(block, I3, (void *)vtlb_table(m_vtlb), I3, SIZE_DWORD, SCALE_x4);// load i3,[vtlb_table],i3,dword UML_TEST(block, I3, iswrite ? VTLB_WRITE_ALLOWED : VTLB_READ_ALLOWED);// test i3,iswrite ? VTLB_WRITE_ALLOWED : VTLB_READ_ALLOWED UML_JMPc(block, COND_Z, tlbmiss = label++); // jmp tlbmiss,z UML_ROLINS(block, I0, I3, 0, 0xfffff000); // rolins i0,i3,0,0xfffff000 - if ((mips3->device->machine().debug_flags & DEBUG_FLAG_ENABLED) == 0) + if ((machine().debug_flags & DEBUG_FLAG_ENABLED) == 0) for (ramnum = 0; ramnum < MIPS3_MAX_FASTRAM; ramnum++) - if (mips3->impstate->fastram[ramnum].base != NULL && (!iswrite || !mips3->impstate->fastram[ramnum].readonly)) + if (m_fastram[ramnum].base != NULL && (!iswrite || !m_fastram[ramnum].readonly)) { - void *fastbase = (UINT8 *)mips3->impstate->fastram[ramnum].base - mips3->impstate->fastram[ramnum].start; + void *fastbase = (UINT8 *)m_fastram[ramnum].base - m_fastram[ramnum].start; UINT32 skip = label++; - if (mips3->impstate->fastram[ramnum].end != 0xffffffff) + if (m_fastram[ramnum].end != 0xffffffff) { - UML_CMP(block, I0, mips3->impstate->fastram[ramnum].end); // cmp i0,end + UML_CMP(block, I0, m_fastram[ramnum].end); // cmp i0,end UML_JMPc(block, COND_A, skip); // ja skip } - if (mips3->impstate->fastram[ramnum].start != 0x00000000) + if (m_fastram[ramnum].start != 0x00000000) { - UML_CMP(block, I0, mips3->impstate->fastram[ramnum].start);// cmp i0,fastram_start + UML_CMP(block, I0, m_fastram[ramnum].start);// cmp i0,fastram_start UML_JMPc(block, COND_B, skip); // jb skip } @@ -1261,13 +849,13 @@ static void static_generate_memory_accessor(mips3_state *mips3, int mode, int si { if (size == 1) { - UML_XOR(block, I0, I0, mips3->bigendian ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0)); + UML_XOR(block, I0, I0, m_bigendian ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0)); // xor i0,i0,bytexor UML_LOAD(block, I0, fastbase, I0, SIZE_BYTE, SCALE_x1); // load i0,fastbase,i0,byte } else if (size == 2) { - UML_XOR(block, I0, I0, mips3->bigendian ? WORD_XOR_BE(0) : WORD_XOR_LE(0)); + UML_XOR(block, I0, I0, m_bigendian ? WORD_XOR_BE(0) : WORD_XOR_LE(0)); // xor i0,i0,wordxor UML_LOAD(block, I0, fastbase, I0, SIZE_WORD, SCALE_x1); // load i0,fastbase,i0,word_x1 } @@ -1278,7 +866,7 @@ static void static_generate_memory_accessor(mips3_state *mips3, int mode, int si else if (size == 8) { UML_DLOAD(block, I0, fastbase, I0, SIZE_QWORD, SCALE_x1); // dload i0,fastbase,i0,qword_x1 - UML_DROR(block, I0, I0, 32 * (mips3->bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0))); + UML_DROR(block, I0, I0, 32 * (m_bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0))); // dror i0,i0,32*bytexor } UML_RET(block); // ret @@ -1287,13 +875,13 @@ static void static_generate_memory_accessor(mips3_state *mips3, int mode, int si { if (size == 1) { - UML_XOR(block, I0, I0, mips3->bigendian ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0)); + UML_XOR(block, I0, I0, m_bigendian ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0)); // xor i0,i0,bytexor UML_STORE(block, fastbase, I0, I1, SIZE_BYTE, SCALE_x1);// store fastbase,i0,i1,byte } else if (size == 2) { - UML_XOR(block, I0, I0, mips3->bigendian ? WORD_XOR_BE(0) : WORD_XOR_LE(0)); + UML_XOR(block, I0, I0, m_bigendian ? WORD_XOR_BE(0) : WORD_XOR_LE(0)); // xor i0,i0,wordxor UML_STORE(block, fastbase, I0, I1, SIZE_WORD, SCALE_x1);// store fastbase,i0,i1,word_x1 } @@ -1310,11 +898,11 @@ static void static_generate_memory_accessor(mips3_state *mips3, int mode, int si } else if (size == 8) { - UML_DROR(block, I1, I1, 32 * (mips3->bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0))); + UML_DROR(block, I1, I1, 32 * (m_bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0))); // dror i1,i1,32*bytexor if (ismasked) { - UML_DROR(block, I2, I2, 32 * (mips3->bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0))); + UML_DROR(block, I2, I2, 32 * (m_bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0))); // dror i2,i2,32*bytexor UML_DLOAD(block, I3, fastbase, I0, SIZE_QWORD, SCALE_x1); // dload i3,fastbase,i0,qword_x1 UML_DROLINS(block, I3, I1, 0, I2); // drolins i3,i1,0,i2 @@ -1387,7 +975,7 @@ static void static_generate_memory_accessor(mips3_state *mips3, int mode, int si if (iswrite) { UML_TEST(block, I3, VTLB_READ_ALLOWED); // test i3,VTLB_READ_ALLOWED - UML_EXHc(block, COND_NZ, *mips3->impstate->exception[EXCEPTION_TLBMOD], I0); + UML_EXHc(block, COND_NZ, *m_exception[EXCEPTION_TLBMOD], I0); // exh tlbmod,i0,nz } UML_TEST(block, I3, VTLB_FLAG_FIXED); // test i3,VTLB_FLAG_FIXED @@ -1409,13 +997,13 @@ static void static_generate_memory_accessor(mips3_state *mips3, int mode, int si on a new SR (in i0); trashes i2 -------------------------------------------------*/ -static void generate_update_mode(mips3_state *mips3, drcuml_block *block) +void mips3_device::generate_update_mode(drcuml_block *block) { UML_ROLAND(block, I2, I0, 32-2, 0x06); // roland i2,i0,32-2,0x06 UML_TEST(block, I0, SR_EXL | SR_ERL); // test i0,SR_EXL | SR_ERL UML_MOVc(block, COND_NZ, I2, 0); // mov i2,0,nz UML_ROLINS(block, I2, I0, 32-26, 0x01); // rolins i2,i0,32-26,0x01 - UML_MOV(block, mem(&mips3->impstate->mode), I2); // mov [mode],i2 + UML_MOV(block, mem(&m_core->mode), I2); // mov [mode],i2 } @@ -1425,7 +1013,7 @@ static void generate_update_mode(mips3_state *mips3, drcuml_block *block) an exception if out -------------------------------------------------*/ -static void generate_update_cycles(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, parameter param, int allow_exception) +void mips3_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, parameter param, int allow_exception) { /* check software interrupts if pending */ if (compiler->checksoftints) @@ -1438,7 +1026,7 @@ static void generate_update_cycles(mips3_state *mips3, drcuml_block *block, comp UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z UML_MOV(block, I0, param); // mov i0,nextpc UML_MOV(block, I1, compiler->cycles); // mov i1,cycles - UML_CALLH(block, *mips3->impstate->exception_norecover[EXCEPTION_INTERRUPT]);// callh interrupt_norecover + UML_CALLH(block, *m_exception_norecover[EXCEPTION_INTERRUPT]);// callh interrupt_norecover UML_LABEL(block, skip); // skip: } @@ -1457,17 +1045,17 @@ static void generate_update_cycles(mips3_state *mips3, drcuml_block *block, comp UML_JMPc(block, COND_NZ, skip); // jmp skip,NZ UML_MOV(block, I0, param); // mov i0,nextpc UML_MOV(block, I1, compiler->cycles); // mov i1,cycles - UML_CALLH(block, *mips3->impstate->exception_norecover[EXCEPTION_INTERRUPT]);// callh interrupt_norecover + UML_CALLH(block, *m_exception_norecover[EXCEPTION_INTERRUPT]);// callh interrupt_norecover UML_LABEL(block, skip); // skip: } /* account for cycles */ if (compiler->cycles > 0) { - UML_SUB(block, mem(&mips3->icount), mem(&mips3->icount), MAPVAR_CYCLES); // sub icount,icount,cycles + UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), MAPVAR_CYCLES); // sub icount,icount,cycles UML_MAPVAR(block, MAPVAR_CYCLES, 0); // mapvar cycles,0 if (allow_exception) - UML_EXHc(block, COND_S, *mips3->impstate->out_of_cycles, param); + UML_EXHc(block, COND_S, *m_out_of_cycles, param); // exh out_of_cycles,nextpc } compiler->cycles = 0; @@ -1479,24 +1067,24 @@ static void generate_update_cycles(mips3_state *mips3, drcuml_block *block, comp validate a sequence of opcodes -------------------------------------------------*/ -static void generate_checksum_block(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast) +void mips3_device::generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast) { const opcode_desc *curdesc; if (LOG_UML) block->append_comment("[Validation for %08X]", seqhead->pc); // comment /* loose verify or single instruction: just compare and fail */ - if (!(mips3->impstate->drcoptions & MIPS3DRC_STRICT_VERIFY) || seqhead->next() == NULL) + if (!(m_drcoptions & MIPS3DRC_STRICT_VERIFY) || seqhead->next() == NULL) { if (!(seqhead->flags & OPFLAG_VIRTUAL_NOOP)) { UINT32 sum = seqhead->opptr.l[0]; - void *base = mips3->direct->read_decrypted_ptr(seqhead->physpc); + void *base = m_direct->read_decrypted_ptr(seqhead->physpc); UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,0,dword if (seqhead->delay.first() != NULL && seqhead->physpc != seqhead->delay.first()->physpc) { - base = mips3->direct->read_decrypted_ptr(seqhead->delay.first()->physpc); + base = m_direct->read_decrypted_ptr(seqhead->delay.first()->physpc); UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword UML_ADD(block, I0, I0, I1); // add i0,i0,i1 @@ -1504,7 +1092,7 @@ static void generate_checksum_block(mips3_state *mips3, drcuml_block *block, com } UML_CMP(block, I0, sum); // cmp i0,opptr[0] - UML_EXHc(block, COND_NE, *mips3->impstate->nocode, epc(seqhead)); // exne nocode,seqhead->pc + UML_EXHc(block, COND_NE, *m_nocode, epc(seqhead)); // exne nocode,seqhead->pc } } @@ -1515,34 +1103,34 @@ static void generate_checksum_block(mips3_state *mips3, drcuml_block *block, com for (curdesc = seqhead->next(); curdesc != seqlast->next(); curdesc = curdesc->next()) if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP)) { - void *base = mips3->direct->read_decrypted_ptr(seqhead->physpc); + void *base = m_direct->read_decrypted_ptr(seqhead->physpc); UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,0,dword UML_CMP(block, I0, curdesc->opptr.l[0]); // cmp i0,opptr[0] - UML_EXHc(block, COND_NE, *mips3->impstate->nocode, epc(seqhead)); // exne nocode,seqhead->pc + UML_EXHc(block, COND_NE, *m_nocode, epc(seqhead)); // exne nocode,seqhead->pc } #else UINT32 sum = 0; - void *base = mips3->direct->read_decrypted_ptr(seqhead->physpc); + void *base = m_direct->read_decrypted_ptr(seqhead->physpc); UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,0,dword sum += seqhead->opptr.l[0]; for (curdesc = seqhead->next(); curdesc != seqlast->next(); curdesc = curdesc->next()) if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP)) { - base = mips3->direct->read_decrypted_ptr(curdesc->physpc); + base = m_direct->read_decrypted_ptr(curdesc->physpc); UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword UML_ADD(block, I0, I0, I1); // add i0,i0,i1 sum += curdesc->opptr.l[0]; if (curdesc->delay.first() != NULL && (curdesc == seqlast || (curdesc->next() != NULL && curdesc->next()->physpc != curdesc->delay.first()->physpc))) { - base = mips3->direct->read_decrypted_ptr(curdesc->delay.first()->physpc); + base = m_direct->read_decrypted_ptr(curdesc->delay.first()->physpc); UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword UML_ADD(block, I0, I0, I1); // add i0,i0,i1 sum += curdesc->delay.first()->opptr.l[0]; } } UML_CMP(block, I0, sum); // cmp i0,sum - UML_EXHc(block, COND_NE, *mips3->impstate->nocode, epc(seqhead)); // exne nocode,seqhead->pc + UML_EXHc(block, COND_NE, *m_nocode, epc(seqhead)); // exne nocode,seqhead->pc #endif } } @@ -1553,14 +1141,14 @@ static void generate_checksum_block(mips3_state *mips3, drcuml_block *block, com for a single instruction in a sequence -------------------------------------------------*/ -static void generate_sequence_instruction(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) +void mips3_device::generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) { offs_t expc; int hotnum; /* add an entry for the log */ if (LOG_UML && !(desc->flags & OPFLAG_VIRTUAL_NOOP)) - log_add_disasm_comment(mips3, block, desc->pc, desc->opptr.l[0]); + log_add_disasm_comment(block, desc->pc, desc->opptr.l[0]); /* set the PC map variable */ expc = (desc->flags & OPFLAG_IN_DELAY_SLOT) ? desc->pc - 3 : desc->pc; @@ -1571,9 +1159,9 @@ static void generate_sequence_instruction(mips3_state *mips3, drcuml_block *bloc /* is this a hotspot? */ for (hotnum = 0; hotnum < MIPS3_MAX_HOTSPOTS; hotnum++) - if (mips3->impstate->hotspot[hotnum].pc != 0 && desc->pc == mips3->impstate->hotspot[hotnum].pc && desc->opptr.l[0] == mips3->impstate->hotspot[hotnum].opcode) + if (m_hotspot[hotnum].pc != 0 && desc->pc == m_hotspot[hotnum].pc && desc->opptr.l[0] == m_hotspot[hotnum].opcode) { - compiler->cycles += mips3->impstate->hotspot[hotnum].cycles; + compiler->cycles += m_hotspot[hotnum].cycles; break; } @@ -1583,23 +1171,23 @@ static void generate_sequence_instruction(mips3_state *mips3, drcuml_block *bloc /* if we want a probe, add it here */ if (desc->pc == PROBE_ADDRESS) { - UML_MOV(block, mem(&mips3->pc), desc->pc); // mov [pc],desc->pc - UML_CALLC(block, cfunc_printf_probe, mips3); // callc cfunc_printf_probe,mips3 + UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc + UML_CALLC(block, cfunc_printf_probe, this); // callc cfunc_printf_probe,mips3 } /* if we are debugging, call the debugger */ - if ((mips3->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) + if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) { - UML_MOV(block, mem(&mips3->pc), desc->pc); // mov [pc],desc->pc - save_fast_iregs(mips3, block); + UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc + save_fast_iregs(block); UML_DEBUG(block, desc->pc); // debug desc->pc } /* if we hit an unmapped address, fatal error */ if (desc->flags & OPFLAG_COMPILER_UNMAPPED) { - UML_MOV(block, mem(&mips3->pc), desc->pc); // mov [pc],desc->pc - save_fast_iregs(mips3, block); + UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc + save_fast_iregs(block); UML_EXIT(block, EXECUTE_UNMAPPED_CODE); // exit EXECUTE_UNMAPPED_CODE } @@ -1609,17 +1197,17 @@ static void generate_sequence_instruction(mips3_state *mips3, drcuml_block *bloc if (PRINTF_MMU) { static const char text[] = "Compiler page fault @ %08X"; - UML_MOV(block, mem(&mips3->impstate->format), (FPTR)text); // mov [format],text - UML_MOV(block, mem(&mips3->impstate->arg0), desc->pc); // mov [arg0],desc->pc - UML_CALLC(block, cfunc_printf_debug, mips3); // callc printf_debug + UML_MOV(block, mem(&m_core->format), (FPTR)text); // mov [format],text + UML_MOV(block, mem(&m_core->arg0), desc->pc); // mov [arg0],desc->pc + UML_CALLC(block, cfunc_printf_debug, this); // callc printf_debug } - UML_EXH(block, *mips3->impstate->tlb_mismatch, 0); // exh tlb_mismatch,0 + UML_EXH(block, *m_tlb_mismatch, 0); // exh tlb_mismatch,0 } /* validate our TLB entry at this PC; if we fail, we need to handle it */ if ((desc->flags & OPFLAG_VALIDATE_TLB) && (desc->pc < 0x80000000 || desc->pc >= 0xc0000000)) { - const vtlb_entry *tlbtable = vtlb_table(mips3->vtlb); + const vtlb_entry *tlbtable = vtlb_table(m_vtlb); /* if we currently have a valid TLB read entry, we just verify */ if (tlbtable[desc->pc >> 12] & VTLB_FETCH_ALLOWED) @@ -1627,13 +1215,13 @@ static void generate_sequence_instruction(mips3_state *mips3, drcuml_block *bloc if (PRINTF_MMU) { static const char text[] = "Checking TLB at @ %08X\n"; - UML_MOV(block, mem(&mips3->impstate->format), (FPTR)text); // mov [format],text - UML_MOV(block, mem(&mips3->impstate->arg0), desc->pc); // mov [arg0],desc->pc - UML_CALLC(block, cfunc_printf_debug, mips3); // callc printf_debug + UML_MOV(block, mem(&m_core->format), (FPTR)text); // mov [format],text + UML_MOV(block, mem(&m_core->arg0), desc->pc); // mov [arg0],desc->pc + UML_CALLC(block, cfunc_printf_debug, this); // callc printf_debug } UML_LOAD(block, I0, &tlbtable[desc->pc >> 12], 0, SIZE_DWORD, SCALE_x4); // load i0,tlbtable[desc->pc >> 12],0,dword UML_CMP(block, I0, tlbtable[desc->pc >> 12]); // cmp i0,*tlbentry - UML_EXHc(block, COND_NE, *mips3->impstate->tlb_mismatch, 0); // exh tlb_mismatch,0,NE + UML_EXHc(block, COND_NE, *m_tlb_mismatch, 0); // exh tlb_mismatch,0,NE } /* otherwise, we generate an unconditional exception */ @@ -1642,27 +1230,27 @@ static void generate_sequence_instruction(mips3_state *mips3, drcuml_block *bloc if (PRINTF_MMU) { static const char text[] = "No valid TLB @ %08X\n"; - UML_MOV(block, mem(&mips3->impstate->format), (FPTR)text); // mov [format],text - UML_MOV(block, mem(&mips3->impstate->arg0), desc->pc); // mov [arg0],desc->pc - UML_CALLC(block, cfunc_printf_debug, mips3); // callc printf_debug + UML_MOV(block, mem(&m_core->format), (FPTR)text); // mov [format],text + UML_MOV(block, mem(&m_core->arg0), desc->pc); // mov [arg0],desc->pc + UML_CALLC(block, cfunc_printf_debug, this); // callc printf_debug } - UML_EXH(block, *mips3->impstate->tlb_mismatch, 0); // exh tlb_mismatch,0 + UML_EXH(block, *m_tlb_mismatch, 0); // exh tlb_mismatch,0 } } /* if this is an invalid opcode, generate the exception now */ if (desc->flags & OPFLAG_INVALID_OPCODE) - UML_EXH(block, *mips3->impstate->exception[EXCEPTION_INVALIDOP], 0); // exh invalidop,0 + UML_EXH(block, *m_exception[EXCEPTION_INVALIDOP], 0); // exh invalidop,0 /* otherwise, unless this is a virtual no-op, it's a regular instruction */ else if (!(desc->flags & OPFLAG_VIRTUAL_NOOP)) { /* compile the instruction */ - if (!generate_opcode(mips3, block, compiler, desc)) + if (!generate_opcode(block, compiler, desc)) { - UML_MOV(block, mem(&mips3->pc), desc->pc); // mov [pc],desc->pc - UML_MOV(block, mem(&mips3->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l - UML_CALLC(block, cfunc_unimplemented, mips3); // callc cfunc_unimplemented + UML_MOV(block, mem(&m_core->pc), desc->pc); // mov [pc],desc->pc + UML_MOV(block, mem(&m_core->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_CALLC(block, cfunc_unimplemented, this); // callc cfunc_unimplemented } } } @@ -1672,7 +1260,7 @@ static void generate_sequence_instruction(mips3_state *mips3, drcuml_block *bloc generate_delay_slot_and_branch ------------------------------------------------------------------*/ -static void generate_delay_slot_and_branch(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 linkreg) +void mips3_device::generate_delay_slot_and_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 linkreg) { compiler_state compiler_temp = *compiler; UINT32 op = desc->opptr.l[0]; @@ -1680,7 +1268,7 @@ static void generate_delay_slot_and_branch(mips3_state *mips3, drcuml_block *blo /* fetch the target register if dynamic, in case it is modified by the delay slot */ if (desc->targetpc == BRANCH_TARGET_DYNAMIC) { - UML_MOV(block, mem(&mips3->impstate->jmpdest), R32(RSREG)); // mov [jmpdest],<rsreg> + UML_MOV(block, mem(&m_core->jmpdest), R32(RSREG)); // mov [jmpdest],<rsreg> } @@ -1692,23 +1280,23 @@ static void generate_delay_slot_and_branch(mips3_state *mips3, drcuml_block *blo /* compile the delay slot using temporary compiler state */ assert(desc->delay.first() != NULL); - generate_sequence_instruction(mips3, block, &compiler_temp, desc->delay.first()); // <next instruction> + generate_sequence_instruction(block, &compiler_temp, desc->delay.first()); // <next instruction> /* update the cycles and jump through the hash table to the target */ if (desc->targetpc != BRANCH_TARGET_DYNAMIC) { - generate_update_cycles(mips3, block, &compiler_temp, desc->targetpc, TRUE); // <subtract cycles> + generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE); // <subtract cycles> if (desc->flags & OPFLAG_INTRABLOCK_BRANCH) UML_JMP(block, desc->targetpc | 0x80000000); // jmp desc->targetpc | 0x80000000 else - UML_HASHJMP(block, mips3->impstate->mode, desc->targetpc, *mips3->impstate->nocode); + UML_HASHJMP(block, m_core->mode, desc->targetpc, *m_nocode); // hashjmp <mode>,desc->targetpc,nocode } else { - generate_update_cycles(mips3, block, &compiler_temp, mem(&mips3->impstate->jmpdest), TRUE); + generate_update_cycles(block, &compiler_temp, mem(&m_core->jmpdest), TRUE); // <subtract cycles> - UML_HASHJMP(block, mips3->impstate->mode, mem(&mips3->impstate->jmpdest), *mips3->impstate->nocode); + UML_HASHJMP(block, m_core->mode, mem(&m_core->jmpdest), *m_nocode); // hashjmp <mode>,<rsreg>,nocode } @@ -1726,7 +1314,7 @@ static void generate_delay_slot_and_branch(mips3_state *mips3, drcuml_block *blo opcode -------------------------------------------------*/ -static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) +int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) { int in_delay_slot = ((desc->flags & OPFLAG_IN_DELAY_SLOT) != 0); UINT32 op = desc->opptr.l[0]; @@ -1738,30 +1326,30 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta /* ----- sub-groups ----- */ case 0x00: /* SPECIAL - MIPS I */ - return generate_special(mips3, block, compiler, desc); + return generate_special(block, compiler, desc); case 0x01: /* REGIMM - MIPS I */ - return generate_regimm(mips3, block, compiler, desc); + return generate_regimm(block, compiler, desc); case 0x1c: /* IDT-specific */ - return generate_idt(mips3, block, compiler, desc); + return generate_idt(block, compiler, desc); /* ----- jumps and branches ----- */ case 0x02: /* J - MIPS I */ - generate_delay_slot_and_branch(mips3, block, compiler, desc, 0); // <next instruction + hashjmp> + generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp> return TRUE; case 0x03: /* JAL - MIPS I */ - generate_delay_slot_and_branch(mips3, block, compiler, desc, 31); // <next instruction + hashjmp> + generate_delay_slot_and_branch(block, compiler, desc, 31); // <next instruction + hashjmp> return TRUE; case 0x04: /* BEQ - MIPS I */ case 0x14: /* BEQL - MIPS II */ UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg> UML_JMPc(block, COND_NE, skip = compiler->labelnum++); // jmp skip,NE - generate_delay_slot_and_branch(mips3, block, compiler, desc, 0); // <next instruction + hashjmp> + generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp> UML_LABEL(block, skip); // skip: return TRUE; @@ -1769,7 +1357,7 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta case 0x15: /* BNEL - MIPS II */ UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg> UML_JMPc(block, COND_E, skip = compiler->labelnum++); // jmp skip,E - generate_delay_slot_and_branch(mips3, block, compiler, desc, 0); // <next instruction + hashjmp> + generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp> UML_LABEL(block, skip); // skip: return TRUE; @@ -1779,18 +1367,18 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta { UML_DCMP(block, R64(RSREG), 0); // dcmp <rsreg>,0 UML_JMPc(block, COND_G, skip = compiler->labelnum++); // jmp skip,G - generate_delay_slot_and_branch(mips3, block, compiler, desc, 0); // <next instruction + hashjmp> + generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp> UML_LABEL(block, skip); // skip: } else - generate_delay_slot_and_branch(mips3, block, compiler, desc, 0); // <next instruction + hashjmp> + generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp> return TRUE; case 0x07: /* BGTZ - MIPS I */ case 0x17: /* BGTZL - MIPS II */ UML_DCMP(block, R64(RSREG), 0); // dcmp <rsreg>,0 UML_JMPc(block, COND_LE, skip = compiler->labelnum++); // jmp skip,LE - generate_delay_slot_and_branch(mips3, block, compiler, desc, 0); // <next instruction + hashjmp> + generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp> UML_LABEL(block, skip); // skip: return TRUE; @@ -1804,8 +1392,8 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta case 0x08: /* ADDI - MIPS I */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL - if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS) - UML_EXHc(block, COND_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], 0); + if (m_drcoptions & MIPS3DRC_CHECK_OVERFLOWS) + UML_EXHc(block, COND_V, *m_exception[EXCEPTION_OVERFLOW], 0); // exh overflow,0 if (RTREG != 0) UML_DSEXT(block, R64(RTREG), I0, SIZE_DWORD); // dsext <rtreg>,i0,dword @@ -1821,8 +1409,8 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta case 0x18: /* DADDI - MIPS III */ UML_DADD(block, I0, R64(RSREG), SIMMVAL); // dadd i0,<rsreg>,SIMMVAL - if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS) - UML_EXHc(block, COND_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], 0); + if (m_drcoptions & MIPS3DRC_CHECK_OVERFLOWS) + UML_EXHc(block, COND_V, *m_exception[EXCEPTION_OVERFLOW], 0); // exh overflow,0 if (RTREG != 0) UML_DMOV(block, R64(RTREG), I0); // dmov <rtreg>,i0 @@ -1869,95 +1457,95 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta case 0x20: /* LB - MIPS I */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL - UML_CALLH(block, *mips3->impstate->read8[mips3->impstate->mode >> 1]); // callh read8 + UML_CALLH(block, *m_read8[m_core->mode >> 1]); // callh read8 if (RTREG != 0) UML_DSEXT(block, R64(RTREG), I0, SIZE_BYTE); // dsext <rtreg>,i0,byte if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x21: /* LH - MIPS I */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL - UML_CALLH(block, *mips3->impstate->read16[mips3->impstate->mode >> 1]); // callh read16 + UML_CALLH(block, *m_read16[m_core->mode >> 1]); // callh read16 if (RTREG != 0) UML_DSEXT(block, R64(RTREG), I0, SIZE_WORD); // dsext <rtreg>,i0,word if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x23: /* LW - MIPS I */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL - UML_CALLH(block, *mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh read32 + UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh read32 if (RTREG != 0) UML_DSEXT(block, R64(RTREG), I0, SIZE_DWORD); // dsext <rtreg>,i0 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x30: /* LL - MIPS II */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL - UML_CALLH(block, *mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh read32 + UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh read32 if (RTREG != 0) UML_DSEXT(block, R64(RTREG), I0, SIZE_DWORD); // dsext <rtreg>,i0 - UML_MOV(block, mem(&mips3->llbit), 1); // mov [llbit],1 + UML_MOV(block, mem(&m_core->llbit), 1); // mov [llbit],1 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x24: /* LBU - MIPS I */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL - UML_CALLH(block, *mips3->impstate->read8[mips3->impstate->mode >> 1]); // callh read8 + UML_CALLH(block, *m_read8[m_core->mode >> 1]); // callh read8 if (RTREG != 0) UML_DAND(block, R64(RTREG), I0, 0xff); // dand <rtreg>,i0,0xff if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x25: /* LHU - MIPS I */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL - UML_CALLH(block, *mips3->impstate->read16[mips3->impstate->mode >> 1]); // callh read16 + UML_CALLH(block, *m_read16[m_core->mode >> 1]); // callh read16 if (RTREG != 0) UML_DAND(block, R64(RTREG), I0, 0xffff); // dand <rtreg>,i0,0xffff if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x27: /* LWU - MIPS III */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL - UML_CALLH(block, *mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh read32 + UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh read32 if (RTREG != 0) UML_DAND(block, R64(RTREG), I0, 0xffffffff); // dand <rtreg>,i0,0xffffffff if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x37: /* LD - MIPS III */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL - UML_CALLH(block, *mips3->impstate->read64[mips3->impstate->mode >> 1]); // callh read64 + UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh read64 if (RTREG != 0) UML_DMOV(block, R64(RTREG), I0); // dmov <rtreg>,i0 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x34: /* LLD - MIPS III */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL - UML_CALLH(block, *mips3->impstate->read64[mips3->impstate->mode >> 1]); // callh read64 + UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh read64 if (RTREG != 0) UML_DMOV(block, R64(RTREG), I0); // dmov <rtreg>,i0 - UML_MOV(block, mem(&mips3->llbit), 1); // mov [llbit],1 + UML_MOV(block, mem(&m_core->llbit), 1); // mov [llbit],1 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x22: /* LWL - MIPS I */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_SHL(block, I1, I0, 3); // shl i1,i0,3 UML_AND(block, I0, I0, ~3); // and i0,i0,~3 - if (!mips3->bigendian) + if (!m_bigendian) UML_XOR(block, I1, I1, 0x18); // xor i1,i1,0x18 UML_SHR(block, I2, ~0, I1); // shr i2,~0,i1 - UML_CALLH(block, *mips3->impstate->read32mask[mips3->impstate->mode >> 1]); + UML_CALLH(block, *m_read32mask[m_core->mode >> 1]); // callh read32mask if (RTREG != 0) { @@ -1967,17 +1555,17 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta UML_DSEXT(block, R64(RTREG), I3, SIZE_DWORD); // dsext <rtreg>,i3,dword } if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x26: /* LWR - MIPS I */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_SHL(block, I1, I0, 3); // shl i1,i0,3 UML_AND(block, I0, I0, ~3); // and i0,i0,~3 - if (mips3->bigendian) + if (m_bigendian) UML_XOR(block, I1, I1, 0x18); // xor i1,i1,0x18 UML_SHL(block, I2, ~0, I1); // shl i2,~0,i1 - UML_CALLH(block, *mips3->impstate->read32mask[mips3->impstate->mode >> 1]); + UML_CALLH(block, *m_read32mask[m_core->mode >> 1]); // callh read32mask if (RTREG != 0) { @@ -1988,17 +1576,17 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta UML_DSEXT(block, R64(RTREG), I3, SIZE_DWORD); // dsext <rtreg>,i3,dword } if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x1a: /* LDL - MIPS III */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_SHL(block, I1, I0, 3); // shl i1,i0,3 UML_AND(block, I0, I0, ~7); // and i0,i0,~7 - if (!mips3->bigendian) + if (!m_bigendian) UML_XOR(block, I1, I1, 0x38); // xor i1,i1,0x38 UML_DSHR(block, I2, (UINT64)~0, I1); // dshr i2,~0,i1 - UML_CALLH(block, *mips3->impstate->read64mask[mips3->impstate->mode >> 1]); + UML_CALLH(block, *m_read64mask[m_core->mode >> 1]); // callh read64mask if (RTREG != 0) { @@ -2006,17 +1594,17 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta UML_DROLINS(block, R64(RTREG), I0, I1, I2); // drolins <rtreg>,i0,i1,i2 } if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x1b: /* LDR - MIPS III */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_SHL(block, I1, I0, 3); // shl i1,i0,3 UML_AND(block, I0, I0, ~7); // and i0,i0,~7 - if (mips3->bigendian) + if (m_bigendian) UML_XOR(block, I1, I1, 0x38); // xor i1,i1,0x38 UML_DSHL(block, I2, (UINT64)~0, I1); // dshl i2,~0,i1 - UML_CALLH(block, *mips3->impstate->read64mask[mips3->impstate->mode >> 1]); + UML_CALLH(block, *m_read64mask[m_core->mode >> 1]); // callh read64mask if (RTREG != 0) { @@ -2025,39 +1613,39 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta UML_DROLINS(block, R64(RTREG), I0, I1, I2); // drolins <rtreg>,i0,i1,i2 } if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x31: /* LWC1 - MIPS I */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL - UML_CALLH(block, *mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh read32 + UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh read32 UML_MOV(block, FPR32(RTREG), I0); // mov <cpr1_rt>,i0 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x35: /* LDC1 - MIPS III */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL - UML_CALLH(block, *mips3->impstate->read64[mips3->impstate->mode >> 1]); // callh read64 + UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh read64 UML_DMOV(block, FPR64(RTREG), I0); // dmov <cpr1_rt>,i0 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x32: /* LWC2 - MIPS I */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL - UML_CALLH(block, *mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh read32 + UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh read32 UML_DAND(block, CPR264(RTREG), I0, 0xffffffff); // dand <cpr2_rt>,i0,0xffffffff if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x36: /* LDC2 - MIPS II */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL - UML_CALLH(block, *mips3->impstate->read64[mips3->impstate->mode >> 1]); // callh read64 + UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh read64 UML_DMOV(block, CPR264(RTREG), I0); // dmov <cpr2_rt>,i0 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; @@ -2066,57 +1654,57 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta case 0x28: /* SB - MIPS I */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg> - UML_CALLH(block, *mips3->impstate->write8[mips3->impstate->mode >> 1]); // callh write8 + UML_CALLH(block, *m_write8[m_core->mode >> 1]); // callh write8 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x29: /* SH - MIPS I */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg> - UML_CALLH(block, *mips3->impstate->write16[mips3->impstate->mode >> 1]); // callh write16 + UML_CALLH(block, *m_write16[m_core->mode >> 1]); // callh write16 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x2b: /* SW - MIPS I */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg> - UML_CALLH(block, *mips3->impstate->write32[mips3->impstate->mode >> 1]); // callh write32 + UML_CALLH(block, *m_write32[m_core->mode >> 1]); // callh write32 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x38: /* SC - MIPS II */ - UML_CMP(block, mem(&mips3->llbit), 0); // cmp [llbit],0 + UML_CMP(block, mem(&m_core->llbit), 0); // cmp [llbit],0 UML_JMPc(block, COND_E, skip = compiler->labelnum++); // je skip UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg> - UML_CALLH(block, *mips3->impstate->write32[mips3->impstate->mode >> 1]); // callh write32 + UML_CALLH(block, *m_write32[m_core->mode >> 1]); // callh write32 UML_LABEL(block, skip); // skip: - UML_DSEXT(block, R64(RTREG), mem(&mips3->llbit), SIZE_DWORD); // dsext <rtreg>,[llbit],dword + UML_DSEXT(block, R64(RTREG), mem(&m_core->llbit), SIZE_DWORD); // dsext <rtreg>,[llbit],dword if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x3f: /* SD - MIPS III */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_DMOV(block, I1, R64(RTREG)); // dmov i1,<rtreg> - UML_CALLH(block, *mips3->impstate->write64[mips3->impstate->mode >> 1]); // callh write64 + UML_CALLH(block, *m_write64[m_core->mode >> 1]); // callh write64 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x3c: /* SCD - MIPS III */ - UML_CMP(block, mem(&mips3->llbit), 0); // cmp [llbit],0 + UML_CMP(block, mem(&m_core->llbit), 0); // cmp [llbit],0 UML_JMPc(block, COND_E, skip = compiler->labelnum++); // je skip UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_DMOV(block, I1, R64(RTREG)); // dmov i1,<rtreg> - UML_CALLH(block, *mips3->impstate->write64[mips3->impstate->mode >> 1]); // callh write64 + UML_CALLH(block, *m_write64[m_core->mode >> 1]); // callh write64 UML_LABEL(block, skip); // skip: - UML_DSEXT(block, R64(RTREG), mem(&mips3->llbit), SIZE_DWORD); // dsext <rtreg>,[llbit],dword + UML_DSEXT(block, R64(RTREG), mem(&m_core->llbit), SIZE_DWORD); // dsext <rtreg>,[llbit],dword if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x2a: /* SWL - MIPS I */ @@ -2124,14 +1712,14 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta UML_SHL(block, I3, I0, 3); // shl i3,i0,3 UML_AND(block, I0, I0, ~3); // and i0,i0,~3 UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg> - if (!mips3->bigendian) + if (!m_bigendian) UML_XOR(block, I3, I3, 0x18); // xor i3,i3,0x18 UML_SHR(block, I2, ~0, I3); // shr i2,~0,i3 UML_SHR(block, I1, I1, I3); // shr i1,i1,i3 - UML_CALLH(block, *mips3->impstate->write32mask[mips3->impstate->mode >> 1]); + UML_CALLH(block, *m_write32mask[m_core->mode >> 1]); // callh write32mask if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x2e: /* SWR - MIPS I */ @@ -2139,14 +1727,14 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta UML_SHL(block, I3, I0, 3); // shl i3,i0,3 UML_AND(block, I0, I0, ~3); // and i0,i0,~3 UML_MOV(block, I1, R32(RTREG)); // mov i1,<rtreg> - if (mips3->bigendian) + if (m_bigendian) UML_XOR(block, I3, I3, 0x18); // xor i3,i3,0x18 UML_SHL(block, I2, ~0, I3); // shl i2,~0,i3 UML_SHL(block, I1, I1, I3); // shl i1,i1,i3 - UML_CALLH(block, *mips3->impstate->write32mask[mips3->impstate->mode >> 1]); + UML_CALLH(block, *m_write32mask[m_core->mode >> 1]); // callh write32mask if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x2c: /* SDL - MIPS III */ @@ -2154,14 +1742,14 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta UML_SHL(block, I3, I0, 3); // shl i3,i0,3 UML_AND(block, I0, I0, ~7); // and i0,i0,~7 UML_DMOV(block, I1, R64(RTREG)); // dmov i1,<rtreg> - if (!mips3->bigendian) + if (!m_bigendian) UML_XOR(block, I3, I3, 0x38); // xor i3,i3,0x38 UML_DSHR(block, I2, (UINT64)~0, I3); // dshr i2,~0,i3 UML_DSHR(block, I1, I1, I3); // dshr i1,i1,i3 - UML_CALLH(block, *mips3->impstate->write64mask[mips3->impstate->mode >> 1]); + UML_CALLH(block, *m_write64mask[m_core->mode >> 1]); // callh write64mask if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x2d: /* SDR - MIPS III */ @@ -2169,46 +1757,46 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta UML_SHL(block, I3, I0, 3); // shl i3,i0,3 UML_AND(block, I0, I0, ~7); // and i0,i0,~7 UML_DMOV(block, I1, R64(RTREG)); // dmov i1,<rtreg> - if (mips3->bigendian) + if (m_bigendian) UML_XOR(block, I3, I3, 0x38); // xor i3,i3,0x38 UML_DSHL(block, I2, (UINT64)~0, I3); // dshl i2,~0,i3 UML_DSHL(block, I1, I1, I3); // dshl i1,i1,i3 - UML_CALLH(block, *mips3->impstate->write64mask[mips3->impstate->mode >> 1]); + UML_CALLH(block, *m_write64mask[m_core->mode >> 1]); // callh write64mask if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x39: /* SWC1 - MIPS I */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_MOV(block, I1, FPR32(RTREG)); // mov i1,<cpr1_rt> - UML_CALLH(block, *mips3->impstate->write32[mips3->impstate->mode >> 1]); // callh write32 + UML_CALLH(block, *m_write32[m_core->mode >> 1]); // callh write32 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x3d: /* SDC1 - MIPS III */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_DMOV(block, I1, FPR64(RTREG)); // dmov i1,<cpr1_rt> - UML_CALLH(block, *mips3->impstate->write64[mips3->impstate->mode >> 1]); // callh write64 + UML_CALLH(block, *m_write64[m_core->mode >> 1]); // callh write64 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x3a: /* SWC2 - MIPS I */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_MOV(block, I1, CPR232(RTREG)); // mov i1,<cpr2_rt> - UML_CALLH(block, *mips3->impstate->write32[mips3->impstate->mode >> 1]); // callh write32 + UML_CALLH(block, *m_write32[m_core->mode >> 1]); // callh write32 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x3e: /* SDC2 - MIPS II */ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_DMOV(block, I1, CPR264(RTREG)); // dmov i1,<cpr2_rt> - UML_CALLH(block, *mips3->impstate->write64[mips3->impstate->mode >> 1]); // callh write64 + UML_CALLH(block, *m_write64[m_core->mode >> 1]); // callh write64 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; @@ -2222,16 +1810,16 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta /* ----- coprocessor instructions ----- */ case 0x10: /* COP0 - MIPS I */ - return generate_cop0(mips3, block, compiler, desc); + return generate_cop0(block, compiler, desc); case 0x11: /* COP1 - MIPS I */ - return generate_cop1(mips3, block, compiler, desc); + return generate_cop1(block, compiler, desc); case 0x13: /* COP1X - MIPS IV */ - return generate_cop1x(mips3, block, compiler, desc); + return generate_cop1x(block, compiler, desc); case 0x12: /* COP2 - MIPS I */ - UML_EXH(block, *mips3->impstate->exception[EXCEPTION_INVALIDOP], 0);// exh invalidop,0 + UML_EXH(block, *m_exception[EXCEPTION_INVALIDOP], 0);// exh invalidop,0 return TRUE; @@ -2249,7 +1837,7 @@ static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_sta 'SPECIAL' group -------------------------------------------------*/ -static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) +int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) { UINT32 op = desc->opptr.l[0]; UINT8 opswitch = op & 63; @@ -2355,10 +1943,10 @@ static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_st /* ----- basic arithmetic ----- */ case 0x20: /* ADD - MIPS I */ - if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS) + if (m_drcoptions & MIPS3DRC_CHECK_OVERFLOWS) { UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> - UML_EXHc(block, COND_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], 0); + UML_EXHc(block, COND_V, *m_exception[EXCEPTION_OVERFLOW], 0); // exh overflow,0,V if (RDREG != 0) UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword @@ -2379,10 +1967,10 @@ static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_st return TRUE; case 0x2c: /* DADD - MIPS III */ - if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS) + if (m_drcoptions & MIPS3DRC_CHECK_OVERFLOWS) { UML_DADD(block, I0, R64(RSREG), R64(RTREG)); // dadd i0,<rsreg>,<rtreg> - UML_EXHc(block, COND_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], 0); + UML_EXHc(block, COND_V, *m_exception[EXCEPTION_OVERFLOW], 0); // exh overflow,0,V if (RDREG != 0) UML_DMOV(block, R64(RDREG), I0); // dmov <rdreg>,i0 @@ -2397,10 +1985,10 @@ static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_st return TRUE; case 0x22: /* SUB - MIPS I */ - if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS) + if (m_drcoptions & MIPS3DRC_CHECK_OVERFLOWS) { UML_SUB(block, I0, R32(RSREG), R32(RTREG)); // sub i0,<rsreg>,<rtreg> - UML_EXHc(block, COND_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], 0); + UML_EXHc(block, COND_V, *m_exception[EXCEPTION_OVERFLOW], 0); // exh overflow,0,V if (RDREG != 0) UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD); // dsext <rdreg>,i0,dword @@ -2421,10 +2009,10 @@ static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_st return TRUE; case 0x2e: /* DSUB - MIPS III */ - if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS) + if (m_drcoptions & MIPS3DRC_CHECK_OVERFLOWS) { UML_DSUB(block, I0, R64(RSREG), R64(RTREG)); // dsub i0,<rsreg>,<rtreg> - UML_EXHc(block, COND_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], 0); + UML_EXHc(block, COND_V, *m_exception[EXCEPTION_OVERFLOW], 0); // exh overflow,0,V if (RDREG != 0) UML_DMOV(block, R64(RDREG), I0); // dmov <rdreg>,i0 @@ -2528,32 +2116,32 @@ static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_st case 0x30: /* TGE - MIPS II */ UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg> - UML_EXHc(block, COND_GE, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,GE + UML_EXHc(block, COND_GE, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,GE return TRUE; case 0x31: /* TGEU - MIPS II */ UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg> - UML_EXHc(block, COND_AE, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,AE + UML_EXHc(block, COND_AE, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,AE return TRUE; case 0x32: /* TLT - MIPS II */ UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg> - UML_EXHc(block, COND_L, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,LT + UML_EXHc(block, COND_L, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,LT return TRUE; case 0x33: /* TLTU - MIPS II */ UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg> - UML_EXHc(block, COND_B, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,B + UML_EXHc(block, COND_B, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,B return TRUE; case 0x34: /* TEQ - MIPS II */ UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg> - UML_EXHc(block, COND_E, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,E + UML_EXHc(block, COND_E, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,E return TRUE; case 0x36: /* TNE - MIPS II */ UML_DCMP(block, R64(RSREG), R64(RTREG)); // dcmp <rsreg>,<rtreg> - UML_EXHc(block, COND_NE, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,NE + UML_EXHc(block, COND_NE, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,NE return TRUE; @@ -2588,22 +2176,22 @@ static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_st /* ----- jumps and branches ----- */ case 0x08: /* JR - MIPS I */ - generate_delay_slot_and_branch(mips3, block, compiler, desc, 0); // <next instruction + hashjmp> + generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp> return TRUE; case 0x09: /* JALR - MIPS I */ - generate_delay_slot_and_branch(mips3, block, compiler, desc, RDREG); // <next instruction + hashjmp> + generate_delay_slot_and_branch(block, compiler, desc, RDREG); // <next instruction + hashjmp> return TRUE; /* ----- system calls ----- */ case 0x0c: /* SYSCALL - MIPS I */ - UML_EXH(block, *mips3->impstate->exception[EXCEPTION_SYSCALL], 0); // exh syscall,0 + UML_EXH(block, *m_exception[EXCEPTION_SYSCALL], 0); // exh syscall,0 return TRUE; case 0x0d: /* BREAK - MIPS I */ - UML_EXH(block, *mips3->impstate->exception[EXCEPTION_BREAK], 0); // exh break,0 + UML_EXH(block, *m_exception[EXCEPTION_BREAK], 0); // exh break,0 return TRUE; @@ -2642,7 +2230,7 @@ static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_st 'REGIMM' group -------------------------------------------------*/ -static int generate_regimm(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) +int mips3_device::generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) { UINT32 op = desc->opptr.l[0]; UINT8 opswitch = RTREG; @@ -2658,7 +2246,7 @@ static int generate_regimm(mips3_state *mips3, drcuml_block *block, compiler_sta { UML_DCMP(block, R64(RSREG), 0); // dcmp <rsreg>,0 UML_JMPc(block, COND_GE, skip = compiler->labelnum++); // jmp skip,GE - generate_delay_slot_and_branch(mips3, block, compiler, desc, (opswitch & 0x10) ? 31 : 0); + generate_delay_slot_and_branch(block, compiler, desc, (opswitch & 0x10) ? 31 : 0); // <next instruction + hashjmp> UML_LABEL(block, skip); // skip: } @@ -2672,43 +2260,43 @@ static int generate_regimm(mips3_state *mips3, drcuml_block *block, compiler_sta { UML_DCMP(block, R64(RSREG), 0); // dcmp <rsreg>,0 UML_JMPc(block, COND_L, skip = compiler->labelnum++); // jmp skip,L - generate_delay_slot_and_branch(mips3, block, compiler, desc, (opswitch & 0x10) ? 31 : 0); + generate_delay_slot_and_branch(block, compiler, desc, (opswitch & 0x10) ? 31 : 0); // <next instruction + hashjmp> UML_LABEL(block, skip); // skip: } else - generate_delay_slot_and_branch(mips3, block, compiler, desc, (opswitch & 0x10) ? 31 : 0); + generate_delay_slot_and_branch(block, compiler, desc, (opswitch & 0x10) ? 31 : 0); // <next instruction + hashjmp> return TRUE; case 0x08: /* TGEI */ UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL - UML_EXHc(block, COND_GE, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,GE + UML_EXHc(block, COND_GE, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,GE return TRUE; case 0x09: /* TGEIU */ UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL - UML_EXHc(block, COND_AE, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,AE + UML_EXHc(block, COND_AE, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,AE return TRUE; case 0x0a: /* TLTI */ UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL - UML_EXHc(block, COND_L, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,L + UML_EXHc(block, COND_L, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,L return TRUE; case 0x0b: /* TLTIU */ UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL - UML_EXHc(block, COND_B, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,B + UML_EXHc(block, COND_B, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,B return TRUE; case 0x0c: /* TEQI */ UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL - UML_EXHc(block, COND_E, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,E + UML_EXHc(block, COND_E, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,E return TRUE; case 0x0e: /* TNEI */ UML_DCMP(block, R64(RSREG), SIMMVAL); // dcmp <rsreg>,SIMMVAL - UML_EXHc(block, COND_NE, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh trap,0,NE + UML_EXHc(block, COND_NE, *m_exception[EXCEPTION_TRAP], 0);// exh trap,0,NE return TRUE; } return FALSE; @@ -2720,13 +2308,13 @@ static int generate_regimm(mips3_state *mips3, drcuml_block *block, compiler_sta specific group -------------------------------------------------*/ -static int generate_idt(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) +int mips3_device::generate_idt(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) { UINT32 op = desc->opptr.l[0]; UINT8 opswitch = op & 0x1f; /* only enabled on IDT processors */ - if (mips3->flavor != MIPS3_TYPE_R4650) + if (m_flavor != MIPS3_TYPE_R4650) return FALSE; switch (opswitch) @@ -2770,7 +2358,7 @@ static int generate_idt(mips3_state *mips3, drcuml_block *block, compiler_state handle special COP0 registers -------------------------------------------------*/ -static int generate_set_cop0_reg(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 reg) +int mips3_device::generate_set_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 reg) { int in_delay_slot = ((desc->flags & OPFLAG_IN_DELAY_SLOT) != 0); code_label link; @@ -2781,39 +2369,39 @@ static int generate_set_cop0_reg(mips3_state *mips3, drcuml_block *block, compil UML_ROLINS(block, CPR032(COP0_Cause), I0, 0, ~0xfc00); // rolins [Cause],i0,0,~0xfc00 compiler->checksoftints = TRUE; if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case COP0_Status: - generate_update_cycles(mips3, block, compiler, desc->pc, !in_delay_slot); // <subtract cycles> + generate_update_cycles(block, compiler, desc->pc, !in_delay_slot); // <subtract cycles> UML_MOV(block, I1, CPR032(COP0_Status)); // mov i1,[Status] UML_MOV(block, CPR032(COP0_Status), I0); // mov [Status],i0 - generate_update_mode(mips3, block); // <update mode> + generate_update_mode(block); // <update mode> UML_XOR(block, I0, I0, I1); // xor i0,i0,i1 UML_TEST(block, I0, 0x8000); // test i0,0x8000 - UML_CALLCc(block, COND_NZ, (c_function)mips3com_update_cycle_counting, mips3); // callc mips3com_update_cycle_counting,mips.core,NZ + UML_CALLCc(block, COND_NZ, cfunc_mips3com_update_cycle_counting, this); // callc mips3com_update_cycle_counting,mips.core,NZ compiler->checkints = TRUE; if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case COP0_Count: - generate_update_cycles(mips3, block, compiler, desc->pc, !in_delay_slot); // <subtract cycles> + generate_update_cycles(block, compiler, desc->pc, !in_delay_slot); // <subtract cycles> UML_MOV(block, CPR032(COP0_Count), I0); // mov [Count],i0 - UML_CALLC(block, cfunc_get_cycles, mips3); // callc cfunc_get_cycles,mips3 + UML_CALLC(block, cfunc_get_cycles, this); // callc cfunc_get_cycles,mips3 UML_DAND(block, I0, I0, 0xffffffff); // and i0,i0,0xffffffff UML_DADD(block, I0, I0, I0); // dadd i0,i0,i0 - UML_DSUB(block, mem(&mips3->count_zero_time), mem(&mips3->impstate->numcycles), I0); - // dsub [count_zero_time],[mips3->impstate->numcycles],i0 - UML_CALLC(block, (c_function)mips3com_update_cycle_counting, mips3); // callc mips3com_update_cycle_counting,mips.core + UML_DSUB(block, mem(&m_core->count_zero_time), mem(&m_core->numcycles), I0); + // dsub [count_zero_time],[m_numcycles],i0 + UML_CALLC(block, cfunc_mips3com_update_cycle_counting, this); // callc mips3com_update_cycle_counting,mips.core return TRUE; case COP0_Compare: - UML_MOV(block, mem(&mips3->compare_armed), 1); // mov [compare_armed],1 - generate_update_cycles(mips3, block, compiler, desc->pc, !in_delay_slot); // <subtract cycles> + UML_MOV(block, mem(&m_core->compare_armed), 1); // mov [compare_armed],1 + generate_update_cycles(block, compiler, desc->pc, !in_delay_slot); // <subtract cycles> UML_MOV(block, CPR032(COP0_Compare), I0); // mov [Compare],i0 UML_AND(block, CPR032(COP0_Cause), CPR032(COP0_Cause), ~0x8000); // and [Cause],[Cause],~0x8000 - UML_CALLC(block, (c_function)mips3com_update_cycle_counting, mips3); // callc mips3com_update_cycle_counting,mips.core + UML_CALLC(block, cfunc_mips3com_update_cycle_counting, this); // callc mips3com_update_cycle_counting,mips.core return TRUE; case COP0_PRId: @@ -2828,7 +2416,7 @@ static int generate_set_cop0_reg(mips3_state *mips3, drcuml_block *block, compil UML_MOV(block, CPR032(reg), I0); // mov cpr0[reg],i0 UML_TEST(block, I1, 0xff); // test i1,0xff UML_JMPc(block, COND_Z, link = compiler->labelnum++); // jmp link,z - UML_CALLC(block, (c_function)mips3com_asid_changed, mips3); // callc mips3com_asid_changed + UML_CALLC(block, cfunc_mips3com_asid_changed, this); // callc mips3com_asid_changed UML_LABEL(block, link); // link: return TRUE; @@ -2844,25 +2432,25 @@ static int generate_set_cop0_reg(mips3_state *mips3, drcuml_block *block, compil read special COP0 registers -------------------------------------------------*/ -static int generate_get_cop0_reg(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 reg) +int mips3_device::generate_get_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 reg) { code_label link1, link2; switch (reg) { case COP0_Count: - generate_update_cycles(mips3, block, compiler, desc->pc, FALSE); // <subtract cycles> - UML_CALLC(block, cfunc_get_cycles, mips3); // callc cfunc_get_cycles,mips3 - UML_DSUB(block, I0, mem(&mips3->impstate->numcycles), mem(&mips3->count_zero_time)); + generate_update_cycles(block, compiler, desc->pc, FALSE); // <subtract cycles> + UML_CALLC(block, cfunc_get_cycles, this); // callc cfunc_get_cycles,mips3 + UML_DSUB(block, I0, mem(&m_core->numcycles), mem(&m_core->count_zero_time)); // dsub i0,[numcycles],[count_zero_time] UML_DSHR(block, I0, I0, 1); // dshr i0,i0,1 UML_DSEXT(block, I0, I0, SIZE_DWORD); // dsext i0,i0,dword return TRUE; case COP0_Random: - generate_update_cycles(mips3, block, compiler, desc->pc, FALSE); // <subtract cycles> - UML_CALLC(block, cfunc_get_cycles, mips3); // callc cfunc_get_cycles,mips3 - UML_DSUB(block, I0, mem(&mips3->impstate->numcycles), mem(&mips3->count_zero_time)); + generate_update_cycles(block, compiler, desc->pc, FALSE); // <subtract cycles> + UML_CALLC(block, cfunc_get_cycles, this); // callc cfunc_get_cycles,mips3 + UML_DSUB(block, I0, mem(&m_core->numcycles), mem(&m_core->count_zero_time)); // dsub i0,[numcycles],[count_zero_time] UML_AND(block, I1, CPR032(COP0_Wired), 0x3f); // and i1,[Wired],0x3f UML_SUB(block, I2, 48, I1); // sub i2,48,i1 @@ -2888,17 +2476,17 @@ static int generate_get_cop0_reg(mips3_state *mips3, drcuml_block *block, compil generate_cop0 - compile COP0 opcodes -------------------------------------------------*/ -static int generate_cop0(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) +int mips3_device::generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) { UINT32 op = desc->opptr.l[0]; UINT8 opswitch = RSREG; int skip; /* generate an exception if COP0 is disabled unless we are in kernel mode */ - if ((mips3->impstate->mode >> 1) != MODE_KERNEL) + if ((m_core->mode >> 1) != MODE_KERNEL) { UML_TEST(block, CPR032(COP0_Status), SR_COP0); // test [Status],SR_COP0 - UML_EXHc(block, COND_Z, *mips3->impstate->exception[EXCEPTION_BADCOP], 0);// exh cop,0,Z + UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], 0);// exh cop,0,Z } switch (opswitch) @@ -2906,7 +2494,7 @@ static int generate_cop0(mips3_state *mips3, drcuml_block *block, compiler_state case 0x00: /* MFCz */ if (RTREG != 0) { - generate_get_cop0_reg(mips3, block, compiler, desc, RDREG); // <get cop0 reg> + generate_get_cop0_reg(block, compiler, desc, RDREG); // <get cop0 reg> UML_DSEXT(block, R64(RTREG), I0, SIZE_DWORD); // dsext <rtreg>,i0,dword } return TRUE; @@ -2914,7 +2502,7 @@ static int generate_cop0(mips3_state *mips3, drcuml_block *block, compiler_state case 0x01: /* DMFCz */ if (RTREG != 0) { - generate_get_cop0_reg(mips3, block, compiler, desc, RDREG); // <get cop0 reg> + generate_get_cop0_reg(block, compiler, desc, RDREG); // <get cop0 reg> UML_DMOV(block, R64(RTREG), I0); // dmov <rtreg>,i0 } return TRUE; @@ -2926,12 +2514,12 @@ static int generate_cop0(mips3_state *mips3, drcuml_block *block, compiler_state case 0x04: /* MTCz */ UML_DSEXT(block, I0, R32(RTREG), SIZE_DWORD); // dsext i0,<rtreg>,dword - generate_set_cop0_reg(mips3, block, compiler, desc, RDREG); // <set cop0 reg> + generate_set_cop0_reg(block, compiler, desc, RDREG); // <set cop0 reg> return TRUE; case 0x05: /* DMTCz */ UML_DMOV(block, I0, R64(RTREG)); // dmov i0,<rtreg> - generate_set_cop0_reg(mips3, block, compiler, desc, RDREG); // <set cop0 reg> + generate_set_cop0_reg(block, compiler, desc, RDREG); // <set cop0 reg> return TRUE; case 0x06: /* CTCz */ @@ -2957,41 +2545,41 @@ static int generate_cop0(mips3_state *mips3, drcuml_block *block, compiler_state switch (op & 0x01ffffff) { case 0x01: /* TLBR */ - UML_CALLC(block, (c_function)mips3com_tlbr, mips3); // callc mips3com_tlbr,mips3 + UML_CALLC(block, cfunc_mips3com_tlbr, this); // callc mips3com_tlbr,mips3 return TRUE; case 0x02: /* TLBWI */ - UML_CALLC(block, (c_function)mips3com_tlbwi, mips3); // callc mips3com_tlbwi,mips3 + UML_CALLC(block, cfunc_mips3com_tlbwi, this); // callc mips3com_tlbwi,mips3 return TRUE; case 0x06: /* TLBWR */ - UML_CALLC(block, (c_function)mips3com_tlbwr, mips3); // callc mips3com_tlbwr,mips3 + UML_CALLC(block, cfunc_mips3com_tlbwr, this); // callc mips3com_tlbwr,mips3 return TRUE; case 0x08: /* TLBP */ - UML_CALLC(block, (c_function)mips3com_tlbp, mips3); // callc mips3com_tlbp,mips3 + UML_CALLC(block, cfunc_mips3com_tlbp, this); // callc mips3com_tlbp,mips3 return TRUE; case 0x18: /* ERET */ - UML_MOV(block, mem(&mips3->llbit), 0); // mov [llbit],0 + UML_MOV(block, mem(&m_core->llbit), 0); // mov [llbit],0 UML_MOV(block, I0, CPR032(COP0_Status)); // mov i0,[Status] UML_TEST(block, I0, SR_ERL); // test i0,SR_ERL UML_JMPc(block, COND_NZ, skip = compiler->labelnum++); // jmp skip,nz UML_AND(block, I0, I0, ~SR_EXL); // and i0,i0,~SR_EXL UML_MOV(block, CPR032(COP0_Status), I0); // mov [Status],i0 - generate_update_mode(mips3, block); + generate_update_mode(block); compiler->checkints = TRUE; - generate_update_cycles(mips3, block, compiler, CPR032(COP0_EPC), TRUE);// <subtract cycles> - UML_HASHJMP(block, mem(&mips3->impstate->mode), CPR032(COP0_EPC), *mips3->impstate->nocode); + generate_update_cycles(block, compiler, CPR032(COP0_EPC), TRUE);// <subtract cycles> + UML_HASHJMP(block, mem(&m_core->mode), CPR032(COP0_EPC), *m_nocode); // hashjmp <mode>,[EPC],nocode UML_LABEL(block, skip); // skip: UML_AND(block, I0, I0, ~SR_ERL); // and i0,i0,~SR_ERL UML_MOV(block, CPR032(COP0_Status), I0); // mov [Status],i0 - generate_update_mode(mips3, block); + generate_update_mode(block); compiler->checkints = TRUE; - generate_update_cycles(mips3, block, compiler, CPR032(COP0_ErrorPC), TRUE); + generate_update_cycles(block, compiler, CPR032(COP0_ErrorPC), TRUE); // <subtract cycles> - UML_HASHJMP(block, mem(&mips3->impstate->mode), CPR032(COP0_ErrorPC), *mips3->impstate->nocode); + UML_HASHJMP(block, mem(&m_core->mode), CPR032(COP0_ErrorPC), *m_nocode); // hashjmp <mode>,[EPC],nocode return TRUE; @@ -3014,17 +2602,17 @@ static int generate_cop0(mips3_state *mips3, drcuml_block *block, compiler_state generate_cop1 - compile COP1 opcodes -------------------------------------------------*/ -static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) +int mips3_device::generate_cop1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) { UINT32 op = desc->opptr.l[0]; code_label skip; condition_t condition; /* generate an exception if COP1 is disabled */ - if (mips3->impstate->drcoptions & MIPS3DRC_STRICT_COP1) + if (m_drcoptions & MIPS3DRC_STRICT_COP1) { UML_TEST(block, CPR032(COP0_Status), SR_COP1); // test [Status],SR_COP1 - UML_EXHc(block, COND_Z, *mips3->impstate->exception[EXCEPTION_BADCOP], 1);// exh cop,1,Z + UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], 1);// exh cop,1,Z } switch (RSREG) @@ -3062,7 +2650,7 @@ static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state UML_TEST(block, I0, 3); // test i0,3 UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z UML_AND(block, I0, CCR132(31), 3); // and i0,ccr1[31],3 - UML_LOAD(block, I0, &mips3->impstate->fpmode[0], I0, SIZE_BYTE, SCALE_x1);// load i0,fpmode,i0,byte + UML_LOAD(block, I0, &m_fpmode[0], I0, SIZE_BYTE, SCALE_x1);// load i0,fpmode,i0,byte UML_SETFMOD(block, I0); // setfmod i0 UML_LABEL(block, skip); // skip: } @@ -3075,7 +2663,7 @@ static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state case 0x02: /* BCzFL - MIPS II */ UML_TEST(block, CCR132(31), FCCMASK(op >> 18)); // test ccr1[31],fccmask[which] UML_JMPc(block, COND_NZ, skip = compiler->labelnum++); // jmp skip,NZ - generate_delay_slot_and_branch(mips3, block, compiler, desc, 0);// <next instruction + hashjmp> + generate_delay_slot_and_branch(block, compiler, desc, 0);// <next instruction + hashjmp> UML_LABEL(block, skip); // skip: return TRUE; @@ -3083,7 +2671,7 @@ static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state case 0x03: /* BCzTL - MIPS II */ UML_TEST(block, CCR132(31), FCCMASK(op >> 18)); // test ccr1[31],fccmask[which] UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z - generate_delay_slot_and_branch(mips3, block, compiler, desc, 0);// <next instruction + hashjmp> + generate_delay_slot_and_branch(block, compiler, desc, 0);// <next instruction + hashjmp> UML_LABEL(block, skip); // skip: return TRUE; } @@ -3390,49 +2978,49 @@ static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state generate_cop1x - compile COP1X opcodes -------------------------------------------------*/ -static int generate_cop1x(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) +int mips3_device::generate_cop1x(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc) { int in_delay_slot = ((desc->flags & OPFLAG_IN_DELAY_SLOT) != 0); UINT32 op = desc->opptr.l[0]; - if (mips3->impstate->drcoptions & MIPS3DRC_STRICT_COP1) + if (m_drcoptions & MIPS3DRC_STRICT_COP1) { UML_TEST(block, CPR032(COP0_Status), SR_COP1); // test [Status],SR_COP1 - UML_EXHc(block, COND_Z, *mips3->impstate->exception[EXCEPTION_BADCOP], 1);// exh cop,1,Z + UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], 1);// exh cop,1,Z } switch (op & 0x3f) { case 0x00: /* LWXC1 - MIPS IV */ UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> - UML_CALLH(block, *mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh read32 + UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh read32 UML_MOV(block, FPR32(FDREG), I0); // mov <cpr1_fd>,i0 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x01: /* LDXC1 - MIPS IV */ UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> - UML_CALLH(block, *mips3->impstate->read64[mips3->impstate->mode >> 1]); // callh read64 + UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh read64 UML_DMOV(block, FPR64(FDREG), I0); // dmov <cpr1_fd>,i0 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x08: /* SWXC1 - MIPS IV */ UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> UML_MOV(block, I1, FPR32(FSREG)); // mov i1,<cpr1_fs> - UML_CALLH(block, *mips3->impstate->write32[mips3->impstate->mode >> 1]); // callh write32 + UML_CALLH(block, *m_write32[m_core->mode >> 1]); // callh write32 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x09: /* SDXC1 - MIPS IV */ UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg> UML_DMOV(block, I1, FPR64(FSREG)); // dmov i1,<cpr1_fs> - UML_CALLH(block, *mips3->impstate->write64[mips3->impstate->mode >> 1]); // callh write64 + UML_CALLH(block, *m_write64[m_core->mode >> 1]); // callh write64 if (!in_delay_slot) - generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE); + generate_update_cycles(block, compiler, desc->pc + 4, TRUE); return TRUE; case 0x0f: /* PREFX */ @@ -3498,7 +3086,7 @@ static int generate_cop1x(mips3_state *mips3, drcuml_block *block, compiler_stat including disassembly of a MIPS instruction -------------------------------------------------*/ -static void log_add_disasm_comment(mips3_state *mips3, drcuml_block *block, UINT32 pc, UINT32 op) +void mips3_device::log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op) { #if (LOG_UML) char buffer[100]; @@ -3514,7 +3102,7 @@ static void log_add_disasm_comment(mips3_state *mips3, drcuml_block *block, UINT flags -------------------------------------------------*/ -static const char *log_desc_flags_to_string(UINT32 flags) +const char *mips3_device::log_desc_flags_to_string(UINT32 flags) { static char tempbuf[30]; char *dest = tempbuf; @@ -3568,7 +3156,7 @@ static const char *log_desc_flags_to_string(UINT32 flags) log_register_list - log a list of GPR registers -------------------------------------------------*/ -static void log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist) +void mips3_device::log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist) { int count = 0; int regnum; @@ -3622,7 +3210,7 @@ static void log_register_list(drcuml_state *drcuml, const char *string, const UI log_opcode_desc - log a list of descriptions -------------------------------------------------*/ -static void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent) +void mips3_device::log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent) { /* open the file, creating it if necessary */ if (indent == 0) @@ -3659,439 +3247,3 @@ static void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, i } } -/*************************************************************************** - NEC VR4300 VARIANTS -***************************************************************************/ - -// NEC VR4300 series is MIPS III with 32-bit address bus and slightly custom COP0/TLB -static CPU_INIT( vr4300be ) -{ - mips3_init(MIPS3_TYPE_VR4300, TRUE, device, irqcallback); -} - -static CPU_INIT( vr4300le ) -{ - mips3_init(MIPS3_TYPE_VR4300, FALSE, device, irqcallback); -} - -CPU_GET_INFO( vr4300be_drc ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(vr4300be); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "VR4300 (big) DRC"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "vr4300be_drc"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -CPU_GET_INFO( vr4300le_drc ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(vr4300le); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "VR4300 (little) DRC"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "vr4300le_drc"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -// VR4310 = VR4300 with different speed bin -CPU_GET_INFO( vr4310be_drc ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(vr4300be); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "VR4310 (big) DRC"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "vr4310be_drc"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -CPU_GET_INFO( vr4310le_drc ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(vr4300le); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "VR4310 (little) DRC"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "vr4310le_drc"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - - -/*************************************************************************** - R4600 VARIANTS -***************************************************************************/ - -static CPU_INIT( r4600be ) -{ - mips3_init(MIPS3_TYPE_R4600, TRUE, device, irqcallback); -} - -static CPU_INIT( r4600le ) -{ - mips3_init(MIPS3_TYPE_R4600, FALSE, device, irqcallback); -} - -CPU_GET_INFO( r4600be_drc ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(r4600be); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "R4600 (big) DRC"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "r4600be_drc"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -CPU_GET_INFO( r4600le_drc ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(r4600le); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "R4600 (little) DRC"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "r4600le_drc"); break; - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - - - -/*************************************************************************** - R4650 VARIANTS -***************************************************************************/ - -static CPU_INIT( r4650be ) -{ - mips3_init(MIPS3_TYPE_R4650, TRUE, device, irqcallback); -} - -static CPU_INIT( r4650le ) -{ - mips3_init(MIPS3_TYPE_R4650, FALSE, device, irqcallback); -} - -CPU_GET_INFO( r4650be_drc ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(r4650be); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "IDT R4650 (big) DRC"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "r4650be_drc"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -CPU_GET_INFO( r4650le_drc ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(r4650le); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "IDT R4650 (little) DRC"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "r4650le_drc"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - - - -/*************************************************************************** - R4700 VARIANTS -***************************************************************************/ - -static CPU_INIT( r4700be ) -{ - mips3_init(MIPS3_TYPE_R4700, TRUE, device, irqcallback); -} - -static CPU_INIT( r4700le ) -{ - mips3_init(MIPS3_TYPE_R4700, FALSE, device, irqcallback); -} - -CPU_GET_INFO( r4700be_drc ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(r4700be); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "R4700 (big) DRC"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "r4700be_drc"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -CPU_GET_INFO( r4700le_drc ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(r4700le); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "R4700 (little) DRC"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "r4700le_drc"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - - - -/*************************************************************************** - R5000 VARIANTS -***************************************************************************/ - -static CPU_INIT( r5000be ) -{ - mips3_init(MIPS3_TYPE_R5000, TRUE, device, irqcallback); -} - -static CPU_INIT( r5000le ) -{ - mips3_init(MIPS3_TYPE_R5000, FALSE, device, irqcallback); -} - -CPU_GET_INFO( r5000be_drc ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(r5000be); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "R5000 (big) DRC"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "r5000be_drc"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -CPU_GET_INFO( r5000le_drc ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(r5000le); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "R5000 (little) DRC"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "r5000le_drc"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - - - -/*************************************************************************** - QED5271 VARIANTS -***************************************************************************/ - -static CPU_INIT( qed5271be ) -{ - mips3_init(MIPS3_TYPE_QED5271, TRUE, device, irqcallback); -} - -static CPU_INIT( qed5271le ) -{ - mips3_init(MIPS3_TYPE_QED5271, FALSE, device, irqcallback); -} - -CPU_GET_INFO( qed5271be_drc ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(qed5271be); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "QED5271 (big) DRC"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "qed5271be_drc"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -CPU_GET_INFO( qed5271le_drc ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(qed5271le); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "QED5271 (little) DRC"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "qed5271le_drc"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - - - -/*************************************************************************** - RM7000 VARIANTS -***************************************************************************/ - -static CPU_INIT( rm7000be ) -{ - mips3_init(MIPS3_TYPE_RM7000, TRUE, device, irqcallback); -} - -static CPU_INIT( rm7000le ) -{ - mips3_init(MIPS3_TYPE_RM7000, FALSE, device, irqcallback); -} - -CPU_GET_INFO( rm7000be_drc ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(rm7000be); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "RM7000 (big) DRC"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "rm7000be_drc"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -CPU_GET_INFO( rm7000le_drc ) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(rm7000le); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "RM7000 (little) DRC"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "rm7000le_drc"); break; - - /* --- everything else is handled generically --- */ - default: CPU_GET_INFO_CALL(mips3); break; - } -} - -DEFINE_LEGACY_CPU_DEVICE(VR4300BE_DRC, vr4300be_drc); -DEFINE_LEGACY_CPU_DEVICE(VR4300LE_DRC, vr4300le_drc); -DEFINE_LEGACY_CPU_DEVICE(VR4310BE_DRC, vr4310be_drc); -DEFINE_LEGACY_CPU_DEVICE(VR4310LE_DRC, vr4310le_drc); - -DEFINE_LEGACY_CPU_DEVICE(R4600BE_DRC, r4600be_drc); -DEFINE_LEGACY_CPU_DEVICE(R4600LE_DRC, r4600le_drc); - -DEFINE_LEGACY_CPU_DEVICE(R4650BE_DRC, r4650be_drc); -DEFINE_LEGACY_CPU_DEVICE(R4650LE_DRC, r4650le_drc); - -DEFINE_LEGACY_CPU_DEVICE(R4700BE_DRC, r4700be_drc); -DEFINE_LEGACY_CPU_DEVICE(R4700LE_DRC, r4700le_drc); - -DEFINE_LEGACY_CPU_DEVICE(R5000BE_DRC, r5000be_drc); -DEFINE_LEGACY_CPU_DEVICE(R5000LE_DRC, r5000le_drc); - -DEFINE_LEGACY_CPU_DEVICE(QED5271BE_DRC, qed5271be_drc); -DEFINE_LEGACY_CPU_DEVICE(QED5271LE_DRC, qed5271le_drc); - -DEFINE_LEGACY_CPU_DEVICE(RM7000BE_DRC, rm7000be_drc); -DEFINE_LEGACY_CPU_DEVICE(RM7000LE_DRC, rm7000le_drc); diff --git a/src/emu/cpu/mips/mips3fe.c b/src/emu/cpu/mips/mips3fe.c index c8b5df15cf1..da713856e65 100644 --- a/src/emu/cpu/mips/mips3fe.c +++ b/src/emu/cpu/mips/mips3fe.c @@ -21,9 +21,9 @@ // mips3_frontend - constructor //------------------------------------------------- -mips3_frontend::mips3_frontend(mips3_state &state, UINT32 window_start, UINT32 window_end, UINT32 max_sequence) - : drc_frontend(*state.device, window_start, window_end, max_sequence), - m_context(state) +mips3_frontend::mips3_frontend(mips3_device *mips3, UINT32 window_start, UINT32 window_end, UINT32 max_sequence) + : drc_frontend(*mips3, window_start, window_end, max_sequence), + m_mips3(mips3) { } @@ -39,7 +39,7 @@ bool mips3_frontend::describe(opcode_desc &desc, const opcode_desc *prev) // compute the physical PC assert((desc.physpc & 3) == 0); - if (!mips3com_translate_address(&m_context, AS_PROGRAM, TRANSLATE_FETCH, &desc.physpc)) + if (!m_mips3->memory_translate(AS_PROGRAM, TRANSLATE_FETCH, desc.physpc)) { // uh-oh: a page fault; leave the description empty and just if this is the first instruction, leave it empty and // mark as needing to validate; otherwise, just end the sequence here @@ -49,7 +49,7 @@ bool mips3_frontend::describe(opcode_desc &desc, const opcode_desc *prev) // fetch the opcode assert((desc.physpc & 3) == 0); - op = desc.opptr.l[0] = m_context.direct->read_decrypted_dword(desc.physpc); + op = desc.opptr.l[0] = m_mips3->m_direct->read_decrypted_dword(desc.physpc); // all instructions are 4 bytes and default to a single cycle each desc.length = 4; @@ -75,7 +75,7 @@ bool mips3_frontend::describe(opcode_desc &desc, const opcode_desc *prev) return describe_cop2(op, desc); case 0x13: // COP1X - MIPS IV - if (m_context.flavor < MIPS3_TYPE_MIPS_IV) + if (m_mips3->m_flavor < mips3_device::MIPS3_TYPE_MIPS_IV) return false; return describe_cop1x(op, desc); @@ -214,7 +214,7 @@ bool mips3_frontend::describe(opcode_desc &desc, const opcode_desc *prev) return true; case 0x33: // PREF - if (m_context.flavor < MIPS3_TYPE_MIPS_IV) + if (m_mips3->m_flavor < mips3_device::MIPS3_TYPE_MIPS_IV) return false; case 0x2f: // CACHE // effective no-op @@ -249,7 +249,7 @@ bool mips3_frontend::describe_special(UINT32 op, opcode_desc &desc) case 0x0a: // MOVZ - MIPS IV case 0x0b: // MOVN - MIPS IV - if (m_context.flavor < MIPS3_TYPE_MIPS_IV) + if (m_mips3->m_flavor < mips3_device::MIPS3_TYPE_MIPS_IV) return false; desc.regin[0] |= REGFLAG_R(RDREG); case 0x04: // SLLV @@ -292,7 +292,7 @@ bool mips3_frontend::describe_special(UINT32 op, opcode_desc &desc) return true; case 0x01: // MOVF - MIPS IV - if (m_context.flavor < MIPS3_TYPE_MIPS_IV) + if (m_mips3->m_flavor < mips3_device::MIPS3_TYPE_MIPS_IV) return false; desc.regin[0] |= REGFLAG_R(RSREG); desc.regin[2] |= REGFLAG_FCC; @@ -441,7 +441,7 @@ bool mips3_frontend::describe_regimm(UINT32 op, opcode_desc &desc) bool mips3_frontend::describe_idt(UINT32 op, opcode_desc &desc) { // only on the R4650 - if (m_context.flavor != MIPS3_TYPE_R4650) + if (m_mips3->m_flavor != mips3_device::MIPS3_TYPE_R4650) return false; switch (op & 0x1f) @@ -593,7 +593,7 @@ bool mips3_frontend::describe_cop1(UINT32 op, opcode_desc &desc) { case 0x12: // MOVZ - MIPS IV case 0x13: // MOVN - MIPS IV - if (m_context.flavor < MIPS3_TYPE_MIPS_IV) + if (m_mips3->m_flavor < mips3_device::MIPS3_TYPE_MIPS_IV) return false; case 0x00: // ADD case 0x01: // SUB @@ -605,7 +605,7 @@ bool mips3_frontend::describe_cop1(UINT32 op, opcode_desc &desc) case 0x15: // RECIP - MIPS IV case 0x16: // RSQRT - MIPS IV - if (m_context.flavor < MIPS3_TYPE_MIPS_IV) + if (m_mips3->m_flavor < mips3_device::MIPS3_TYPE_MIPS_IV) return false; case 0x04: // SQRT case 0x05: // ABS @@ -628,7 +628,7 @@ bool mips3_frontend::describe_cop1(UINT32 op, opcode_desc &desc) return true; case 0x11: // MOVT/F - MIPS IV - if (m_context.flavor < MIPS3_TYPE_MIPS_IV) + if (m_mips3->m_flavor < mips3_device::MIPS3_TYPE_MIPS_IV) return false; desc.regin[1] |= REGFLAG_CPR1(FSREG); desc.regin[2] |= REGFLAG_FCC; diff --git a/src/emu/cpu/mips/mips3fe.h b/src/emu/cpu/mips/mips3fe.h index 9df332eeee3..15e90c922e0 100644 --- a/src/emu/cpu/mips/mips3fe.h +++ b/src/emu/cpu/mips/mips3fe.h @@ -13,9 +13,6 @@ #ifndef __MIPS3FE_H__ #define __MIPS3FE_H__ -#include "mips3com.h" -#include "cpu/drcfe.h" - //************************************************************************** // MACROS @@ -33,34 +30,4 @@ #define REGFLAG_FCC (1 << 2) - -//************************************************************************** -// TYPE DEFINITIONS -//************************************************************************** - -class mips3_frontend : public drc_frontend -{ -public: - // construction/destruction - mips3_frontend(mips3_state &state, UINT32 window_start, UINT32 window_end, UINT32 max_sequence); - -protected: - // required overrides - virtual bool describe(opcode_desc &desc, const opcode_desc *prev); - -private: - // internal helpers - bool describe_special(UINT32 op, opcode_desc &desc); - bool describe_regimm(UINT32 op, opcode_desc &desc); - bool describe_idt(UINT32 op, opcode_desc &desc); - bool describe_cop0(UINT32 op, opcode_desc &desc); - bool describe_cop1(UINT32 op, opcode_desc &desc); - bool describe_cop1x(UINT32 op, opcode_desc &desc); - bool describe_cop2(UINT32 op, opcode_desc &desc); - - // internal state - mips3_state &m_context; -}; - - #endif /* __MIPS3FE_H__ */ diff --git a/src/mame/drivers/aleck64.c b/src/mame/drivers/aleck64.c index e38857616c8..a1976d6f013 100644 --- a/src/mame/drivers/aleck64.c +++ b/src/mame/drivers/aleck64.c @@ -810,19 +810,14 @@ static INPUT_PORTS_START( srmvs ) PORT_DIPSETTING( 0x00000000, DEF_STR( On ) ) INPUT_PORTS_END -/* ?? */ -static const mips3_config vr4300_config = -{ - 16384, /* code cache size */ - 8192, /* data cache size */ - 62500000 /* system clock */ -}; static MACHINE_CONFIG_START( aleck64, aleck64_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", VR4300BE, 93750000) - MCFG_CPU_CONFIG(vr4300_config) + MCFG_MIPS3_ICACHE_SIZE(16384) + MCFG_MIPS3_DCACHE_SIZE(8192) + MCFG_MIPS3_SYSTEM_CLOCK(62500000) MCFG_CPU_PROGRAM_MAP(n64_map) MCFG_CPU_ADD("rsp", RSP, 62500000) diff --git a/src/mame/drivers/atlantis.c b/src/mame/drivers/atlantis.c index 8da50e43c25..bf0971073aa 100644 --- a/src/mame/drivers/atlantis.c +++ b/src/mame/drivers/atlantis.c @@ -51,7 +51,7 @@ public: virtual void machine_start(); virtual void machine_reset(); UINT32 screen_update_mwskins(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); - required_device<cpu_device> m_maincpu; + required_device<mips3_device> m_maincpu; required_device<dcs2_audio_denver_device> m_dcs; }; @@ -65,7 +65,7 @@ public: void atlantis_state::machine_start() { /* set the fastest DRC options */ - mips3drc_set_options(m_maincpu, MIPS3DRC_FASTEST_OPTIONS); + m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS); } @@ -130,17 +130,12 @@ INPUT_PORTS_END * *************************************/ -static const mips3_config r4310_config = -{ - 16384, /* code cache size */ - 16384 /* data cache size */ -}; - static MACHINE_CONFIG_START( mwskins, atlantis_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", VR4310LE, 166666666) // clock is TRUSTED - MCFG_CPU_CONFIG(r4310_config) + MCFG_MIPS3_ICACHE_SIZE(16384) + MCFG_MIPS3_DCACHE_SIZE(16384) MCFG_CPU_PROGRAM_MAP(main_map) diff --git a/src/mame/drivers/hng64.c b/src/mame/drivers/hng64.c index b76bd7259bf..8ad47f7ca60 100644 --- a/src/mame/drivers/hng64.c +++ b/src/mame/drivers/hng64.c @@ -1833,13 +1833,6 @@ DRIVER_INIT_MEMBER(hng64_state,hng64_shoot) } -/* ?? */ -static const mips3_config vr4300_config = -{ - 16384, /* code cache size */ - 16384 /* data cache size */ -}; - void hng64_state::m_set_irq(UINT32 irq_vector) { /* @@ -1902,12 +1895,12 @@ TIMER_DEVICE_CALLBACK_MEMBER(hng64_state::hng64_irq) void hng64_state::machine_start() { /* set the fastest DRC options */ - mips3drc_set_options(m_maincpu, MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY); + m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY); /* configure fast RAM regions for DRC */ - mips3drc_add_fastram(m_maincpu, 0x00000000, 0x00ffffff, FALSE, m_mainram); - mips3drc_add_fastram(m_maincpu, 0x04000000, 0x05ffffff, TRUE, m_cart); - mips3drc_add_fastram(m_maincpu, 0x1fc00000, 0x1fc7ffff, TRUE, m_rombase); + m_maincpu->mips3drc_add_fastram(0x00000000, 0x00ffffff, FALSE, m_mainram); + m_maincpu->mips3drc_add_fastram(0x04000000, 0x05ffffff, TRUE, m_cart); + m_maincpu->mips3drc_add_fastram(0x1fc00000, 0x1fc7ffff, TRUE, m_rombase); m_comm_rom = memregion("user2")->base(); m_comm_ram = auto_alloc_array(machine(),UINT8,0x10000); @@ -1942,7 +1935,8 @@ static MACHINE_CONFIG_START( hng64, hng64_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", VR4300BE, MASTER_CLOCK) // actually R4300 - MCFG_CPU_CONFIG(vr4300_config) + MCFG_MIPS3_ICACHE_SIZE(16384) + MCFG_MIPS3_DCACHE_SIZE(16384) MCFG_CPU_PROGRAM_MAP(hng_map) MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", hng64_state, hng64_irq, "screen", 0, 1) diff --git a/src/mame/drivers/iteagle.c b/src/mame/drivers/iteagle.c index 9b4f0a78796..9cb6ff3e3bb 100644 --- a/src/mame/drivers/iteagle.c +++ b/src/mame/drivers/iteagle.c @@ -102,7 +102,7 @@ public: m_voodoo(*this, "voodoo") {} - required_device<cpu_device> m_maincpu; + required_device<mips3_device> m_maincpu; required_device<device_t> m_voodoo; DECLARE_DRIVER_INIT(iteagle); @@ -122,7 +122,7 @@ public: void iteagle_state::machine_start() { /* set the fastest DRC options */ - mips3drc_set_options(m_maincpu, MIPS3DRC_FASTEST_OPTIONS); + m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS); } @@ -181,17 +181,12 @@ INPUT_PORTS_END * *************************************/ -static const mips3_config r4310_config = -{ - 16384, /* code cache size */ - 16384 /* data cache size */ -}; - static MACHINE_CONFIG_START( gtfore, iteagle_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", VR4310LE, 166666666) - MCFG_CPU_CONFIG(r4310_config) + MCFG_MIPS3_ICACHE_SIZE(16384) + MCFG_MIPS3_DCACHE_SIZE(16384) MCFG_CPU_PROGRAM_MAP(main_map) MCFG_ATA_INTERFACE_ADD("ata", ata_devices, "hdd", NULL, true) diff --git a/src/mame/drivers/kinst.c b/src/mame/drivers/kinst.c index 1d4e5e228c6..f613c7f8a0d 100644 --- a/src/mame/drivers/kinst.c +++ b/src/mame/drivers/kinst.c @@ -177,7 +177,7 @@ public: virtual void machine_reset(); UINT32 screen_update_kinst(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); INTERRUPT_GEN_MEMBER(irq0_start); - required_device<cpu_device> m_maincpu; + required_device<mips3_device> m_maincpu; required_device<ata_interface_device> m_ata; required_device<dcs_audio_2k_device> m_dcs; @@ -201,12 +201,12 @@ protected: void kinst_state::machine_start() { /* set the fastest DRC options */ - mips3drc_set_options(m_maincpu, MIPS3DRC_FASTEST_OPTIONS); + m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS); /* configure fast RAM regions for DRC */ - mips3drc_add_fastram(m_maincpu, 0x08000000, 0x087fffff, FALSE, m_rambase2); - mips3drc_add_fastram(m_maincpu, 0x00000000, 0x0007ffff, FALSE, m_rambase); - mips3drc_add_fastram(m_maincpu, 0x1fc00000, 0x1fc7ffff, TRUE, m_rombase); + m_maincpu->mips3drc_add_fastram(0x08000000, 0x087fffff, FALSE, m_rambase2); + m_maincpu->mips3drc_add_fastram(0x00000000, 0x0007ffff, FALSE, m_rambase); + m_maincpu->mips3drc_add_fastram(0x1fc00000, 0x1fc7ffff, TRUE, m_rombase); } @@ -669,17 +669,12 @@ INPUT_PORTS_END * *************************************/ -static const mips3_config r4600_config = -{ - 16384, /* code cache size */ - 16384 /* data cache size */ -}; - static MACHINE_CONFIG_START( kinst, kinst_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", R4600LE, MASTER_CLOCK*2) - MCFG_CPU_CONFIG(r4600_config) + MCFG_MIPS3_ICACHE_SIZE(16384) + MCFG_MIPS3_DCACHE_SIZE(16384) MCFG_CPU_PROGRAM_MAP(main_map) MCFG_CPU_VBLANK_INT_DRIVER("screen", kinst_state, irq0_start) diff --git a/src/mame/drivers/namcops2.c b/src/mame/drivers/namcops2.c index a9056d87e75..7244548c73d 100644 --- a/src/mame/drivers/namcops2.c +++ b/src/mame/drivers/namcops2.c @@ -128,16 +128,11 @@ ADDRESS_MAP_END static INPUT_PORTS_START( system246 ) INPUT_PORTS_END -static const mips3_config r5000_config = -{ - 16384, /* code cache size - probably wrong */ - 16384 /* data cache size */ -}; - static MACHINE_CONFIG_START( system246, namcops2_state ) MCFG_CPU_ADD("maincpu", R5000LE, 294000000) // actually R5900 @ 294 MHz + MCFG_MIPS3_ICACHE_SIZE(16384) + MCFG_MIPS3_DCACHE_SIZE(16384) MCFG_CPU_PROGRAM_MAP(ps2_map) - MCFG_CPU_CONFIG(r5000_config) /* video hardware */ MCFG_SCREEN_ADD("screen", RASTER) diff --git a/src/mame/drivers/namcos23.c b/src/mame/drivers/namcos23.c index e20163ff6a4..dcde2786fd4 100644 --- a/src/mame/drivers/namcos23.c +++ b/src/mame/drivers/namcos23.c @@ -1379,7 +1379,7 @@ public: m_generic_paletteram_32(*this, "paletteram") { } - required_device<cpu_device> m_maincpu; + required_device<mips3_device> m_maincpu; required_device<h83002_device> m_subcpu; required_device<h8_adc_device> m_adc; optional_device<h83334_device> m_iocpu; @@ -3222,7 +3222,7 @@ void namcos23_state::machine_start() m_c361.timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(namcos23_state::c361_timer_cb),this)); m_c361.timer->adjust(attotime::never); - mips3drc_add_fastram(m_maincpu, 0, m_mainram.bytes()-1, FALSE, reinterpret_cast<UINT32 *>(memshare("mainram")->ptr())); + m_maincpu->mips3drc_add_fastram(0, m_mainram.bytes()-1, FALSE, reinterpret_cast<UINT32 *>(memshare("mainram")->ptr())); } @@ -3315,19 +3315,12 @@ static GFXDECODE_START( namcos23 ) GFXDECODE_END -static const mips3_config r4650_config = -{ - 8192, /* code cache size - VERIFIED */ - 8192 /* data cache size - VERIFIED */ -}; - - - static MACHINE_CONFIG_START( gorgon, namcos23_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", R4650BE, BUSCLOCK*4) - MCFG_CPU_CONFIG(r4650_config) + MCFG_MIPS3_ICACHE_SIZE(8192) // VERIFIED + MCFG_MIPS3_DCACHE_SIZE(8192) // VERIFIED MCFG_CPU_PROGRAM_MAP(gorgon_map) MCFG_CPU_VBLANK_INT_DRIVER("screen", namcos23_state, interrupt) @@ -3395,7 +3388,8 @@ static MACHINE_CONFIG_START( s23, namcos23_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", R4650BE, BUSCLOCK*4) - MCFG_CPU_CONFIG(r4650_config) + MCFG_MIPS3_ICACHE_SIZE(8192) // VERIFIED + MCFG_MIPS3_DCACHE_SIZE(8192) // VERIFIED MCFG_CPU_PROGRAM_MAP(s23_map) MCFG_CPU_VBLANK_INT_DRIVER("screen", namcos23_state, interrupt) @@ -3483,7 +3477,8 @@ static MACHINE_CONFIG_START( ss23, namcos23_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", R4650BE, BUSCLOCK*5) - MCFG_CPU_CONFIG(r4650_config) + MCFG_MIPS3_ICACHE_SIZE(8192) // VERIFIED + MCFG_MIPS3_DCACHE_SIZE(8192) // VERIFIED MCFG_CPU_PROGRAM_MAP(s23_map) MCFG_CPU_VBLANK_INT_DRIVER("screen", namcos23_state, interrupt) diff --git a/src/mame/drivers/pyson.c b/src/mame/drivers/pyson.c index f43c78b0408..6150b8539fa 100644 --- a/src/mame/drivers/pyson.c +++ b/src/mame/drivers/pyson.c @@ -190,16 +190,11 @@ ADDRESS_MAP_END static INPUT_PORTS_START( pyson ) INPUT_PORTS_END -static const mips3_config r5000_config = -{ - 16384, /* code cache size - probably wrong */ - 16384 /* data cache size */ -}; - static MACHINE_CONFIG_START( pyson, pyson_state ) MCFG_CPU_ADD("maincpu", R5000LE, 294000000) // imported from namcops2.c driver + MCFG_MIPS3_ICACHE_SIZE(16384) + MCFG_MIPS3_DCACHE_SIZE(16384) MCFG_CPU_PROGRAM_MAP(ps2_map) - MCFG_CPU_CONFIG(r5000_config) /* video hardware */ MCFG_SCREEN_ADD("screen", RASTER) diff --git a/src/mame/drivers/seattle.c b/src/mame/drivers/seattle.c index 12aab45df14..76acfaccd17 100644 --- a/src/mame/drivers/seattle.c +++ b/src/mame/drivers/seattle.c @@ -446,7 +446,7 @@ public: required_shared_ptr<UINT32> m_interrupt_config; required_shared_ptr<UINT32> m_asic_reset; required_shared_ptr<UINT32> m_rombase; - required_device<cpu_device> m_maincpu; + required_device<mips3_device> m_maincpu; required_device<bus_master_ide_controller_device> m_ide; optional_device<smc91c94_device> m_ethernet; optional_device<atari_cage_seattle_device> m_cage; @@ -564,11 +564,11 @@ void seattle_state::machine_start() m_galileo.timer[3].timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(seattle_state::galileo_timer_callback),this)); /* set the fastest DRC options, but strict verification */ - mips3drc_set_options(m_maincpu, MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY); + m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY); /* configure fast RAM regions for DRC */ - mips3drc_add_fastram(m_maincpu, 0x00000000, 0x007fffff, FALSE, m_rambase); - mips3drc_add_fastram(m_maincpu, 0x1fc00000, 0x1fc7ffff, TRUE, m_rombase); + m_maincpu->mips3drc_add_fastram(0x00000000, 0x007fffff, FALSE, m_rambase); + m_maincpu->mips3drc_add_fastram(0x1fc00000, 0x1fc7ffff, TRUE, m_rombase); /* register for save states */ save_item(NAME(m_galileo.reg)); @@ -2506,18 +2506,13 @@ INPUT_PORTS_END * *************************************/ -static const mips3_config r5000_config = -{ - 16384, /* code cache size */ - 16384, /* data cache size */ - SYSTEM_CLOCK /* system clock rate */ -}; - static MACHINE_CONFIG_START( seattle_common, seattle_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", R5000LE, SYSTEM_CLOCK*3) - MCFG_CPU_CONFIG(r5000_config) + MCFG_MIPS3_ICACHE_SIZE(16384) + MCFG_MIPS3_DCACHE_SIZE(16384) + MCFG_MIPS3_SYSTEM_CLOCK(SYSTEM_CLOCK) MCFG_CPU_PROGRAM_MAP(seattle_map) MCFG_NVRAM_ADD_1FILL("nvram") @@ -2546,14 +2541,18 @@ MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( phoenixsa, seattle_common ) MCFG_CPU_REPLACE("maincpu", R4700LE, SYSTEM_CLOCK*2) - MCFG_CPU_CONFIG(r5000_config) + MCFG_MIPS3_ICACHE_SIZE(16384) + MCFG_MIPS3_DCACHE_SIZE(16384) + MCFG_MIPS3_SYSTEM_CLOCK(SYSTEM_CLOCK) MCFG_CPU_PROGRAM_MAP(seattle_map) MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( seattle150, seattle_common ) MCFG_CPU_REPLACE("maincpu", R5000LE, SYSTEM_CLOCK*3) - MCFG_CPU_CONFIG(r5000_config) + MCFG_MIPS3_ICACHE_SIZE(16384) + MCFG_MIPS3_DCACHE_SIZE(16384) + MCFG_MIPS3_SYSTEM_CLOCK(SYSTEM_CLOCK) MCFG_CPU_PROGRAM_MAP(seattle_map) MACHINE_CONFIG_END @@ -2566,7 +2565,9 @@ MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( seattle200, seattle_common ) MCFG_CPU_REPLACE("maincpu", R5000LE, SYSTEM_CLOCK*4) - MCFG_CPU_CONFIG(r5000_config) + MCFG_MIPS3_ICACHE_SIZE(16384) + MCFG_MIPS3_DCACHE_SIZE(16384) + MCFG_MIPS3_SYSTEM_CLOCK(SYSTEM_CLOCK) MCFG_CPU_PROGRAM_MAP(seattle_map) MACHINE_CONFIG_END @@ -2578,7 +2579,9 @@ MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( flagstaff, seattle_common ) MCFG_CPU_REPLACE("maincpu", R5000LE, SYSTEM_CLOCK*4) - MCFG_CPU_CONFIG(r5000_config) + MCFG_MIPS3_ICACHE_SIZE(16384) + MCFG_MIPS3_DCACHE_SIZE(16384) + MCFG_MIPS3_SYSTEM_CLOCK(SYSTEM_CLOCK) MCFG_CPU_PROGRAM_MAP(seattle_map) MCFG_SMC91C94_ADD("ethernet") @@ -3003,9 +3006,9 @@ DRIVER_INIT_MEMBER(seattle_state,wg3dh) init_common(PHOENIX_CONFIG); /* speedups */ - mips3drc_add_hotspot(m_maincpu, 0x8004413C, 0x0C0054B4, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x80094930, 0x00A2102B, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x80092984, 0x3C028011, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x8004413C, 0x0C0054B4, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x80094930, 0x00A2102B, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x80092984, 0x3C028011, 250); /* confirmed */ } @@ -3014,7 +3017,7 @@ DRIVER_INIT_MEMBER(seattle_state,mace) init_common(SEATTLE_CONFIG); /* speedups */ - mips3drc_add_hotspot(m_maincpu, 0x800108F8, 0x8C420000, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x800108F8, 0x8C420000, 250); /* confirmed */ } @@ -3023,9 +3026,9 @@ DRIVER_INIT_MEMBER(seattle_state,sfrush) init_common(FLAGSTAFF_CONFIG); /* speedups */ - mips3drc_add_hotspot(m_maincpu, 0x80059F34, 0x3C028012, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x800A5AF4, 0x8E300010, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x8004C260, 0x3C028012, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x80059F34, 0x3C028012, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x800A5AF4, 0x8E300010, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x8004C260, 0x3C028012, 250); /* confirmed */ } @@ -3034,10 +3037,10 @@ DRIVER_INIT_MEMBER(seattle_state,sfrushrk) init_common(FLAGSTAFF_CONFIG); /* speedups */ - mips3drc_add_hotspot(m_maincpu, 0x800343E8, 0x3C028012, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x8008F4F0, 0x3C028012, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x800A365C, 0x8E300014, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x80051DAC, 0x3C028012, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x800343E8, 0x3C028012, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x8008F4F0, 0x3C028012, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x800A365C, 0x8E300014, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x80051DAC, 0x3C028012, 250); /* confirmed */ } @@ -3046,8 +3049,8 @@ DRIVER_INIT_MEMBER(seattle_state,calspeed) init_common(SEATTLE_WIDGET_CONFIG); /* speedups */ - mips3drc_add_hotspot(m_maincpu, 0x80032534, 0x02221024, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x800B1BE4, 0x8E110014, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x80032534, 0x02221024, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x800B1BE4, 0x8E110014, 250); /* confirmed */ } @@ -3056,9 +3059,9 @@ DRIVER_INIT_MEMBER(seattle_state,vaportrx) init_common(SEATTLE_WIDGET_CONFIG); /* speedups */ - mips3drc_add_hotspot(m_maincpu, 0x80049F14, 0x3C028020, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x8004859C, 0x3C028020, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x8005922C, 0x8E020014, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x80049F14, 0x3C028020, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x8004859C, 0x3C028020, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x8005922C, 0x8E020014, 250); /* confirmed */ } @@ -3076,8 +3079,8 @@ DRIVER_INIT_MEMBER(seattle_state,blitz) m_rombase[0x934/4] += 4; /* main CPU speedups */ - mips3drc_add_hotspot(m_maincpu, 0x80135510, 0x3C028024, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x800087DC, 0x8E820010, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x80135510, 0x3C028024, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x800087DC, 0x8E820010, 250); /* confirmed */ } @@ -3086,8 +3089,8 @@ DRIVER_INIT_MEMBER(seattle_state,blitz99) init_common(SEATTLE_CONFIG); /* speedups */ - mips3drc_add_hotspot(m_maincpu, 0x8014E41C, 0x3C038025, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x80011F10, 0x8E020018, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x8014E41C, 0x3C038025, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x80011F10, 0x8E020018, 250); /* confirmed */ } @@ -3096,8 +3099,8 @@ DRIVER_INIT_MEMBER(seattle_state,blitz2k) init_common(SEATTLE_CONFIG); /* speedups */ - mips3drc_add_hotspot(m_maincpu, 0x8015773C, 0x3C038025, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x80012CA8, 0x8E020018, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x8015773C, 0x3C038025, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x80012CA8, 0x8E020018, 250); /* confirmed */ } @@ -3109,8 +3112,8 @@ DRIVER_INIT_MEMBER(seattle_state,carnevil) m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x16800000, 0x1680001f, read32_delegate(FUNC(seattle_state::carnevil_gun_r),this), write32_delegate(FUNC(seattle_state::carnevil_gun_w),this)); /* speedups */ - mips3drc_add_hotspot(m_maincpu, 0x8015176C, 0x3C03801A, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x80011FBC, 0x8E020018, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x8015176C, 0x3C03801A, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x80011FBC, 0x8E020018, 250); /* confirmed */ } @@ -3119,9 +3122,9 @@ DRIVER_INIT_MEMBER(seattle_state,hyprdriv) init_common(SEATTLE_WIDGET_CONFIG); /* speedups */ - mips3drc_add_hotspot(m_maincpu, 0x801643BC, 0x3C03801B, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x80011FB8, 0x8E020018, 250); /* confirmed */ - //mips3drc_add_hotspot(m_maincpu, 0x80136A80, 0x3C02801D, 250); /* potential */ + m_maincpu->mips3drc_add_hotspot(0x801643BC, 0x3C03801B, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x80011FB8, 0x8E020018, 250); /* confirmed */ + //m_maincpu->mips3drc_add_hotspot(0x80136A80, 0x3C02801D, 250); /* potential */ } diff --git a/src/mame/drivers/vegas.c b/src/mame/drivers/vegas.c index 92515bf749b..18613700250 100644 --- a/src/mame/drivers/vegas.c +++ b/src/mame/drivers/vegas.c @@ -466,7 +466,7 @@ public: m_dcs(*this, "dcs"), m_ioasic(*this, "ioasic") { } - required_device<cpu_device> m_maincpu; + required_device<mips3_device> m_maincpu; required_device<m48t37_device> m_timekeeper; required_device<bus_master_ide_controller_device> m_ide; required_device<smc91c94_device> m_ethernet; @@ -593,11 +593,11 @@ void vegas_state::machine_start() m_dcs_idma_cs = 0; /* set the fastest DRC options, but strict verification */ - mips3drc_set_options(m_maincpu, MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY + MIPS3DRC_FLUSH_PC); + m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY + MIPS3DRC_FLUSH_PC); /* configure fast RAM regions for DRC */ - mips3drc_add_fastram(m_maincpu, 0x00000000, m_rambase.bytes() - 1, FALSE, m_rambase); - mips3drc_add_fastram(m_maincpu, 0x1fc00000, 0x1fc7ffff, TRUE, m_rombase); + m_maincpu->mips3drc_add_fastram(0x00000000, m_rambase.bytes() - 1, FALSE, m_rambase); + m_maincpu->mips3drc_add_fastram(0x1fc00000, 0x1fc7ffff, TRUE, m_rombase); /* register for save states */ save_item(NAME(m_nile_irq_state)); @@ -2206,18 +2206,13 @@ INPUT_PORTS_END * *************************************/ -static const mips3_config r5000_config = -{ - 16384, /* code cache size */ - 16384, /* data cache size */ - SYSTEM_CLOCK /* system clock rate */ -}; - static MACHINE_CONFIG_START( vegascore, vegas_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", R5000LE, SYSTEM_CLOCK*2) - MCFG_CPU_CONFIG(r5000_config) + MCFG_MIPS3_ICACHE_SIZE(16384) + MCFG_MIPS3_DCACHE_SIZE(16384) + MCFG_MIPS3_SYSTEM_CLOCK(SYSTEM_CLOCK) MCFG_CPU_PROGRAM_MAP(vegas_map_8mb) MCFG_M48T37_ADD("timekeeper") @@ -2276,7 +2271,9 @@ MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( vegasv3, vegas32m ) MCFG_CPU_REPLACE("maincpu", RM7000LE, SYSTEM_CLOCK*2.5) - MCFG_CPU_CONFIG(r5000_config) + MCFG_MIPS3_ICACHE_SIZE(16384) + MCFG_MIPS3_DCACHE_SIZE(16384) + MCFG_MIPS3_SYSTEM_CLOCK(SYSTEM_CLOCK) MCFG_CPU_PROGRAM_MAP(vegas_map_8mb) MCFG_DEVICE_REMOVE("voodoo") @@ -2290,7 +2287,9 @@ MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( denver, vegascore ) MCFG_CPU_REPLACE("maincpu", RM7000LE, SYSTEM_CLOCK*2.5) - MCFG_CPU_CONFIG(r5000_config) + MCFG_MIPS3_ICACHE_SIZE(16384) + MCFG_MIPS3_DCACHE_SIZE(16384) + MCFG_MIPS3_SYSTEM_CLOCK(SYSTEM_CLOCK) MCFG_CPU_PROGRAM_MAP(vegas_map_32mb) MCFG_DEVICE_REMOVE("voodoo") @@ -2602,37 +2601,37 @@ ROM_END DRIVER_INIT_MEMBER(vegas_state,gauntleg) { /* speedups */ - mips3drc_add_hotspot(m_maincpu, 0x80015430, 0x8CC38060, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x80015464, 0x3C09801E, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x800C8918, 0x8FA2004C, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x800C8890, 0x8FA20024, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x80015430, 0x8CC38060, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x80015464, 0x3C09801E, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x800C8918, 0x8FA2004C, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x800C8890, 0x8FA20024, 250); /* confirmed */ } DRIVER_INIT_MEMBER(vegas_state,gauntdl) { /* speedups */ - mips3drc_add_hotspot(m_maincpu, 0x800158B8, 0x8CC3CC40, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x800158EC, 0x3C0C8022, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x800D40C0, 0x8FA2004C, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x800D4038, 0x8FA20024, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x800158B8, 0x8CC3CC40, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x800158EC, 0x3C0C8022, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x800D40C0, 0x8FA2004C, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x800D4038, 0x8FA20024, 250); /* confirmed */ } DRIVER_INIT_MEMBER(vegas_state,warfa) { /* speedups */ - mips3drc_add_hotspot(m_maincpu, 0x8009436C, 0x0C031663, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x8009436C, 0x0C031663, 250); /* confirmed */ } DRIVER_INIT_MEMBER(vegas_state,tenthdeg) { /* speedups */ - mips3drc_add_hotspot(m_maincpu, 0x80051CD8, 0x0C023C15, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x8005E674, 0x3C028017, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x8002DBCC, 0x8FA2002C, 250); /* confirmed */ - mips3drc_add_hotspot(m_maincpu, 0x80015930, 0x8FC20244, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x80051CD8, 0x0C023C15, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x8005E674, 0x3C028017, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x8002DBCC, 0x8FA2002C, 250); /* confirmed */ + m_maincpu->mips3drc_add_hotspot(0x80015930, 0x8FC20244, 250); /* confirmed */ } diff --git a/src/mame/drivers/vp101.c b/src/mame/drivers/vp101.c index d9e7f2e133c..464815f9253 100644 --- a/src/mame/drivers/vp101.c +++ b/src/mame/drivers/vp101.c @@ -34,7 +34,7 @@ public: protected: // devices - required_device<cpu_device> m_maincpu; + required_device<mips3_device> m_maincpu; // driver_device overrides virtual void video_start(); @@ -74,16 +74,12 @@ ADDRESS_MAP_END static INPUT_PORTS_START( vp101 ) INPUT_PORTS_END -static const mips3_config r5000_config = -{ - 32768, /* code cache size */ - 32768, /* data cache size */ - 100000000 /* system (bus) clock */ -}; static MACHINE_CONFIG_START( vp101, vp10x_state ) MCFG_CPU_ADD("maincpu", R5000LE, 300000000) /* actually VR5500 with added NEC VR-series custom instructions */ - MCFG_CPU_CONFIG(r5000_config) + MCFG_MIPS3_ICACHE_SIZE(32768) + MCFG_MIPS3_DCACHE_SIZE(32768) + MCFG_MIPS3_SYSTEM_CLOCK(100000000) MCFG_CPU_PROGRAM_MAP(main_map) MCFG_SCREEN_ADD("screen", RASTER) diff --git a/src/mame/includes/hng64.h b/src/mame/includes/hng64.h index f9610f8d3bc..771e4000e7c 100644 --- a/src/mame/includes/hng64.h +++ b/src/mame/includes/hng64.h @@ -1,4 +1,5 @@ #include "machine/msm6242.h" +#include "cpu/mips/mips3.h" enum { @@ -41,7 +42,7 @@ public: m_generic_paletteram_32(*this, "paletteram") { } - required_device<cpu_device> m_maincpu; + required_device<mips3_device> m_maincpu; required_device<cpu_device> m_audiocpu; required_device<cpu_device> m_comm; required_device<msm6242_device> m_rtc; diff --git a/src/mame/machine/n64.c b/src/mame/machine/n64.c index 190c4273f42..037cf447199 100644 --- a/src/mame/machine/n64.c +++ b/src/mame/machine/n64.c @@ -2412,10 +2412,10 @@ void n64_state::machine_start() rsp_imem = reinterpret_cast<UINT32 *>(memshare("rsp_imem")->ptr()); rsp_dmem = reinterpret_cast<UINT32 *>(memshare("rsp_dmem")->ptr()); - mips3drc_set_options(machine().device("maincpu"), MIPS3DRC_COMPATIBLE_OPTIONS); + dynamic_cast<mips3_device *>(machine().device("maincpu"))->mips3drc_set_options(MIPS3DRC_COMPATIBLE_OPTIONS); /* configure fast RAM regions for DRC */ - mips3drc_add_fastram(machine().device("maincpu"), 0x00000000, 0x007fffff, FALSE, rdram); + dynamic_cast<mips3_device *>(machine().device("maincpu"))->mips3drc_add_fastram(0x00000000, 0x007fffff, FALSE, rdram); rspdrc_set_options(machine().device("rsp"), RSPDRC_STRICT_VERIFY); rspdrc_flush_drc_cache(machine().device("rsp")); diff --git a/src/mess/drivers/ip22.c b/src/mess/drivers/ip22.c index 870dd3fecf4..4710ad2393b 100644 --- a/src/mess/drivers/ip22.c +++ b/src/mess/drivers/ip22.c @@ -112,7 +112,7 @@ public: { } - required_device<cpu_device> m_maincpu; + required_device<mips3_device> m_maincpu; required_device<wd33c93_device> m_wd33c93; required_shared_ptr<UINT32> m_unkpbus0; required_shared_ptr<UINT32> m_mainram; @@ -1222,7 +1222,7 @@ void ip22_state::machine_reset() m_PBUS_DMA.nActive = 0; - mips3drc_set_options(m_maincpu, MIPS3DRC_COMPATIBLE_OPTIONS | MIPS3DRC_CHECK_OVERFLOWS); + m_maincpu->mips3drc_set_options(MIPS3DRC_COMPATIBLE_OPTIONS | MIPS3DRC_CHECK_OVERFLOWS); } void ip22_state::dump_chain(address_space &space, UINT32 ch_base) |