diff options
-rw-r--r-- | src/emu/cpu/tms32025/tms32025.c | 2854 | ||||
-rw-r--r-- | src/emu/cpu/tms32025/tms32025.h | 298 |
2 files changed, 1646 insertions, 1506 deletions
diff --git a/src/emu/cpu/tms32025/tms32025.c b/src/emu/cpu/tms32025/tms32025.c index 1d0c5cf91b0..316c1e80b45 100644 --- a/src/emu/cpu/tms32025/tms32025.c +++ b/src/emu/cpu/tms32025/tms32025.c @@ -125,99 +125,24 @@ Table 3-2. TMS32025/26 Memory Blocks -#define SET_PC(x) do { cpustate->PC = (x); } while (0) - -#define P_IN(A) (cpustate->io->read_word((A)<<1)) -#define P_OUT(A,V) (cpustate->io->write_word(((A)<<1),(V))) -#define S_IN(A) (cpustate->io->read_word((A)<<1)) -#define S_OUT(A,V) (cpustate->io->write_word(((A)<<1),(V))) - -#define M_RDOP(A) ((cpustate->pgmmap[(A) >> 7]) ? (cpustate->pgmmap[(A) >> 7][(A) & 0x7f]) : cpustate->direct->read_decrypted_word((A)<<1)) -#define M_RDOP_ARG(A) ((cpustate->pgmmap[(A) >> 7]) ? (cpustate->pgmmap[(A) >> 7][(A) & 0x7f]) : cpustate->direct->read_decrypted_word((A)<<1)) - - - -struct tms32025_state -{ - /******************** CPU Internal Registers *******************/ - UINT16 PREVPC; /* previous program counter */ - UINT16 PC; - UINT16 PFC; - UINT16 STR0, STR1; - UINT8 IFR; - UINT8 RPTC; - PAIR ACC; - PAIR Preg; - UINT16 Treg; - UINT16 AR[8]; - UINT16 STACK[8]; - PAIR ALU; - UINT16 *intRAM; - UINT8 timerover; - - /********************** Status data ****************************/ - PAIR opcode; - int idle; - int hold; - int external_mem_access; /** required for hold mode. Implement it ! */ - int init_load_addr; /* 0=No, 1=Yes, 2=Once for repeat mode */ - int tms32025_irq_cycles; - int tms32025_dec_cycles; - device_irq_acknowledge_callback irq_callback; - - PAIR oldacc; - UINT32 memaccess; - int icount; - int mHackIgnoreARP; /* special handling for lst, lst1 instructions */ - int waiting_for_serial_frame; - - legacy_cpu_device *device; - address_space *program; - direct_read_data *direct; - address_space *data; - address_space *io; - - UINT16 *pgmmap[0x200]; - UINT16 *datamap[0x200]; -}; - -INLINE tms32025_state *get_safe_token(device_t *device) -{ - assert(device != NULL); - assert(device->type() == TMS32025 || - device->type() == TMS32026); - return (tms32025_state *)downcast<legacy_cpu_device *>(device)->token(); -} +#define SET_PC(x) do { m_PC = (x); } while (0) -/* opcode table entry */ -struct tms32025_opcode -{ - UINT8 cycles; - void (*function)(tms32025_state *); -}; -/* opcode table entry (Opcode CE has sub-opcodes) */ -struct tms32025_opcode_CE -{ - UINT8 cycles; - void (*function)(tms32025_state *); -}; -/* opcode table entry (Opcode Dx has sub-opcodes) */ -struct tms32025_opcode_Dx -{ - UINT8 cycles; - void (*function)(tms32025_state *); -}; +#define P_IN(A) (m_io->read_word((A)<<1)) +#define P_OUT(A,V) (m_io->write_word(((A)<<1),(V))) +#define S_IN(A) (m_io->read_word((A)<<1)) +#define S_OUT(A,V) (m_io->write_word(((A)<<1),(V))) +#define M_RDOP(A) ((m_pgmmap[(A) >> 7]) ? (m_pgmmap[(A) >> 7][(A) & 0x7f]) : m_direct->read_decrypted_word((A)<<1)) +#define M_RDOP_ARG(A) ((m_pgmmap[(A) >> 7]) ? (m_pgmmap[(A) >> 7][(A) & 0x7f]) : m_direct->read_decrypted_word((A)<<1)) /************************** Memory mapped registers ****************/ -#define DRR cpustate->intRAM[0] -#define DXR cpustate->intRAM[1] -#define TIM cpustate->intRAM[2] -#define PRD cpustate->intRAM[3] -#define IMR cpustate->intRAM[4] -#define GREG cpustate->intRAM[5] - +#define DRR m_intRAM[0] +#define DXR m_intRAM[1] +#define TIM m_intRAM[2] +#define PRD m_intRAM[3] +#define IMR m_intRAM[4] +#define GREG m_intRAM[5] /**************************************************************************** @@ -255,100 +180,136 @@ struct tms32025_opcode_Dx #define PM_REG 0x0003 /* PM (Product shift Mode) */ -#define OV ( cpustate->STR0 & OV_FLAG) /* OV (Overflow flag) */ -#define OVM ( cpustate->STR0 & OVM_FLAG) /* OVM (Overflow Mode bit) 1 indicates an overflow */ -#define INTM ( cpustate->STR0 & INTM_FLAG) /* INTM (Interrupt enable flag) 0 enables maskable interrupts */ -#define ARP ((cpustate->STR0 & ARP_REG) >> 13) /* ARP (Auxiliary Register Pointer) */ -#define DP ((cpustate->STR0 & DP_REG) << 7) /* DP (Data memory Pointer bit) */ -#define ARB ( cpustate->STR1 & ARB_REG) /* ARB (Backup Auxiliary Register pointer) */ -#define CNF0 ( cpustate->STR1 & CNF0_REG) /* CNF0 (Onchip Ram Config register) */ -#define TC ( cpustate->STR1 & TC_FLAG) /* TC (Test Control Flag) */ -#define SXM ( cpustate->STR1 & SXM_FLAG) /* SXM (Sign Extension Mode) */ -#define CARRY ( cpustate->STR1 & C_FLAG) /* C (Carry Flag for accumulator) */ -#define HM ( cpustate->STR1 & HM_FLAG) /* HM (Processor Hold Mode) */ -#define FSM ( cpustate->STR1 & FSM_FLAG) /* FSM (Frame Synchronization Mode - for serial port) */ -#define XF ( cpustate->STR1 & FSM_FLAG) /* XF (XF output pin status) */ -#define FO ( cpustate->STR1 & FO_FLAG) /* FO (Serial port Format In/Out mode) */ -#define TXM ( cpustate->STR1 & TXM_FLAG) /* TXM (Transmit Mode - for serial port) */ -#define PM ( cpustate->STR1 & PM_REG) /* PM (P register shift Mode. See SHIFT_Preg_TO_ALU below )*/ +#define OV ( m_STR0 & OV_FLAG) /* OV (Overflow flag) */ +#define OVM ( m_STR0 & OVM_FLAG) /* OVM (Overflow Mode bit) 1 indicates an overflow */ +#define INTM ( m_STR0 & INTM_FLAG) /* INTM (Interrupt enable flag) 0 enables maskable interrupts */ +#define ARP ((m_STR0 & ARP_REG) >> 13) /* ARP (Auxiliary Register Pointer) */ +#define DP ((m_STR0 & DP_REG) << 7) /* DP (Data memory Pointer bit) */ +#define ARB ( m_STR1 & ARB_REG) /* ARB (Backup Auxiliary Register pointer) */ +#define CNF0 ( m_STR1 & CNF0_REG) /* CNF0 (Onchip Ram Config register) */ +#define TC ( m_STR1 & TC_FLAG) /* TC (Test Control Flag) */ +#define SXM ( m_STR1 & SXM_FLAG) /* SXM (Sign Extension Mode) */ +#define CARRY ( m_STR1 & C_FLAG) /* C (Carry Flag for accumulator) */ +#define HM ( m_STR1 & HM_FLAG) /* HM (Processor Hold Mode) */ +#define FSM ( m_STR1 & FSM_FLAG) /* FSM (Frame Synchronization Mode - for serial port) */ +#define XF ( m_STR1 & FSM_FLAG) /* XF (XF output pin status) */ +#define FO ( m_STR1 & FO_FLAG) /* FO (Serial port Format In/Out mode) */ +#define TXM ( m_STR1 & TXM_FLAG) /* TXM (Transmit Mode - for serial port) */ +#define PM ( m_STR1 & PM_REG) /* PM (P register shift Mode. See SHIFT_Preg_TO_ALU below )*/ + +#define DMA (DP | (m_opcode.b.l & 0x7f)) /* address used in direct memory access operations */ +#define DMApg0 (m_opcode.b.l & 0x7f) /* address used in direct memory access operations for sst instruction */ +#define IND m_AR[ARP] /* address used in indirect memory access operations */ -#define DMA (DP | (cpustate->opcode.b.l & 0x7f)) /* address used in direct memory access operations */ -#define DMApg0 (cpustate->opcode.b.l & 0x7f) /* address used in direct memory access operations for sst instruction */ -#define IND cpustate->AR[ARP] /* address used in indirect memory access operations */ -INLINE void CLR0(tms32025_state *cpustate, UINT16 flag) { cpustate->STR0 &= ~flag; cpustate->STR0 |= 0x0400; } -INLINE void SET0(tms32025_state *cpustate, UINT16 flag) { cpustate->STR0 |= flag; cpustate->STR0 |= 0x0400; } -INLINE void CLR1(tms32025_state *cpustate, UINT16 flag) { cpustate->STR1 &= ~flag; cpustate->STR1 |= 0x0180; } -INLINE void SET1(tms32025_state *cpustate, UINT16 flag) { cpustate->STR1 |= flag; cpustate->STR1 |= 0x0180; } +const device_type TMS32025 = &device_creator<tms32025_device>; +const device_type TMS32026 = &device_creator<tms32026_device>; -INLINE void MODIFY_DP(tms32025_state *cpustate, int data) + +tms32025_device::tms32025_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : cpu_device(mconfig, TMS32025, "TMS32025", tag, owner, clock, "tms32025", __FILE__) + , m_program_config("program", ENDIANNESS_BIG, 16, 16, -1) + , m_data_config("data", ENDIANNESS_BIG, 16, 16, -1) + , m_io_config("io", ENDIANNESS_BIG, 16, 17, -1) { - cpustate->STR0 &= ~DP_REG; - cpustate->STR0 |= (data & DP_REG); - cpustate->STR0 |= 0x0400; } -INLINE void MODIFY_PM(tms32025_state *cpustate, int data) + + +tms32025_device::tms32025_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) + : cpu_device(mconfig, type, name, tag, owner, clock, shortname, source) + , m_program_config("program", ENDIANNESS_BIG, 16, 16, -1) + , m_data_config("data", ENDIANNESS_BIG, 16, 16, -1) + , m_io_config("io", ENDIANNESS_BIG, 16, 16, -1) { - cpustate->STR1 &= ~PM_REG; - cpustate->STR1 |= (data & PM_REG); - cpustate->STR1 |= 0x0180; } -INLINE void MODIFY_ARP(tms32025_state *cpustate, int data) + + +tms32026_device::tms32026_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : tms32025_device(mconfig, TMS32026, "TMS32026", tag, owner, clock, "tms32026", __FILE__) +{ +} + + +offs_t tms32025_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { - cpustate->STR1 &= ~ARB_REG; - cpustate->STR1 |= (cpustate->STR0 & ARP_REG); - cpustate->STR1 |= 0x0180; - cpustate->STR0 &= ~ARP_REG; - cpustate->STR0 |= ((data << 13) & ARP_REG); - cpustate->STR0 |= 0x0400; + extern CPU_DISASSEMBLE( tms32025 ); + return CPU_DISASSEMBLE_NAME(tms32025)(this, buffer, pc, oprom, opram, options); } -INLINE UINT16 M_RDROM(tms32025_state *cpustate, offs_t addr) + +void tms32025_device::CLR0(UINT16 flag) { m_STR0 &= ~flag; m_STR0 |= 0x0400; } +void tms32025_device::SET0(UINT16 flag) { m_STR0 |= flag; m_STR0 |= 0x0400; } +void tms32025_device::CLR1(UINT16 flag) { m_STR1 &= ~flag; m_STR1 |= 0x0180; } +void tms32025_device::SET1(UINT16 flag) { m_STR1 |= flag; m_STR1 |= 0x0180; } + +void tms32025_device::MODIFY_DP(int data) +{ + m_STR0 &= ~DP_REG; + m_STR0 |= (data & DP_REG); + m_STR0 |= 0x0400; +} +void tms32025_device::MODIFY_PM(int data) +{ + m_STR1 &= ~PM_REG; + m_STR1 |= (data & PM_REG); + m_STR1 |= 0x0180; +} +void tms32025_device::MODIFY_ARP(int data) +{ + m_STR1 &= ~ARB_REG; + m_STR1 |= (m_STR0 & ARP_REG); + m_STR1 |= 0x0180; + m_STR0 &= ~ARP_REG; + m_STR0 |= ((data << 13) & ARP_REG); + m_STR0 |= 0x0400; +} + +UINT16 tms32025_device::M_RDROM(offs_t addr) { UINT16 *ram; addr &= 0xffff; - ram = cpustate->pgmmap[addr >> 7]; + ram = m_pgmmap[addr >> 7]; if (ram) return ram[addr & 0x7f]; - return cpustate->program->read_word(addr << 1); + return m_program->read_word(addr << 1); } -INLINE void M_WRTROM(tms32025_state *cpustate, offs_t addr, UINT16 data) +void tms32025_device::M_WRTROM(offs_t addr, UINT16 data) { UINT16 *ram; addr &= 0xffff; - ram = cpustate->pgmmap[addr >> 7]; + ram = m_pgmmap[addr >> 7]; if (ram) { ram[addr & 0x7f] = data; } - else cpustate->program->write_word(addr << 1, data); + else m_program->write_word(addr << 1, data); } -INLINE UINT16 M_RDRAM(tms32025_state *cpustate, offs_t addr) +UINT16 tms32025_device::M_RDRAM(offs_t addr) { UINT16 *ram; addr &= 0xffff; - ram = cpustate->datamap[addr >> 7]; + ram = m_datamap[addr >> 7]; if (ram) return ram[addr & 0x7f]; - return cpustate->data->read_word(addr << 1); + return m_data->read_word(addr << 1); } -INLINE void M_WRTRAM(tms32025_state *cpustate, offs_t addr, UINT16 data) +void tms32025_device::M_WRTRAM(offs_t addr, UINT16 data) { UINT16 *ram; addr &= 0xffff; - ram = cpustate->datamap[addr >> 7]; + ram = m_datamap[addr >> 7]; if (ram) { ram[addr & 0x7f] = data; - if(addr == 1 && ram == cpustate->intRAM && TXM) { + if(addr == 1 && ram == m_intRAM && TXM) { if(FSM) - cpustate->waiting_for_serial_frame = 1; + m_waiting_for_serial_frame = 1; else - cpustate->IFR |= 0x20; + m_IFR |= 0x20; } } - else cpustate->data->write_word(addr << 1, data); + else m_data->write_word(addr << 1, data); } -static UINT16 reverse_carry_add(UINT16 arg0, UINT16 arg1 ) +UINT16 tms32025_device::reverse_carry_add(UINT16 arg0, UINT16 arg1 ) { UINT16 result = 0; int carry = 0; @@ -364,186 +325,186 @@ static UINT16 reverse_carry_add(UINT16 arg0, UINT16 arg1 ) return result; } -INLINE void MODIFY_AR_ARP(tms32025_state *cpustate) +void tms32025_device::MODIFY_AR_ARP() { /* modify address register referenced by ARP */ - switch (cpustate->opcode.b.l & 0x70) /* Cases ordered by predicted useage */ + switch (m_opcode.b.l & 0x70) /* Cases ordered by predicted useage */ { case 0x00: /* 000 nop */ break; case 0x10: /* 001 *- */ - cpustate->AR[ARP] -- ; + m_AR[ARP] -- ; break; case 0x20: /* 010 *+ */ - cpustate->AR[ARP] ++ ; + m_AR[ARP] ++ ; break; case 0x30: /* 011 reserved */ break; case 0x40: /* 100 *BR0- */ - cpustate->AR[ARP] = reverse_carry_add(cpustate->AR[ARP],-cpustate->AR[0]); + m_AR[ARP] = reverse_carry_add(m_AR[ARP],-m_AR[0]); break; case 0x50: /* 101 *0- */ - cpustate->AR[ARP] -= cpustate->AR[0]; + m_AR[ARP] -= m_AR[0]; break; case 0x60: /* 110 *0+ */ - cpustate->AR[ARP] += cpustate->AR[0]; + m_AR[ARP] += m_AR[0]; break; case 0x70: /* 111 *BR0+ */ - cpustate->AR[ARP] += reverse_carry_add(cpustate->AR[ARP],cpustate->AR[0]); + m_AR[ARP] += reverse_carry_add(m_AR[ARP],m_AR[0]); break; } - if( !cpustate->mHackIgnoreARP ) + if( !m_mHackIgnoreARP ) { - if (cpustate->opcode.b.l & 8) + if (m_opcode.b.l & 8) { /* bit 3 determines if new value is loaded into ARP */ - MODIFY_ARP(cpustate, (cpustate->opcode.b.l & 7) ); + MODIFY_ARP((m_opcode.b.l & 7) ); } } } -INLINE void CALCULATE_ADD_CARRY(tms32025_state *cpustate) +void tms32025_device::CALCULATE_ADD_CARRY() { - if ( (UINT32)(cpustate->oldacc.d) > (UINT32)(cpustate->ACC.d) ) { - SET1(cpustate, C_FLAG); + if ( (UINT32)(m_oldacc.d) > (UINT32)(m_ACC.d) ) { + SET1(C_FLAG); } else { - CLR1(cpustate, C_FLAG); + CLR1(C_FLAG); } } -INLINE void CALCULATE_SUB_CARRY(tms32025_state *cpustate) +void tms32025_device::CALCULATE_SUB_CARRY() { - if ( (UINT32)(cpustate->oldacc.d) < (UINT32)(cpustate->ACC.d) ) { - CLR1(cpustate, C_FLAG); + if ( (UINT32)(m_oldacc.d) < (UINT32)(m_ACC.d) ) { + CLR1(C_FLAG); } else { - SET1(cpustate, C_FLAG); + SET1(C_FLAG); } } -INLINE void CALCULATE_ADD_OVERFLOW(tms32025_state *cpustate, INT32 addval) +void tms32025_device::CALCULATE_ADD_OVERFLOW(INT32 addval) { - if ((INT32)((cpustate->ACC.d ^ addval) & (cpustate->oldacc.d ^ cpustate->ACC.d)) < 0) + if ((INT32)((m_ACC.d ^ addval) & (m_oldacc.d ^ m_ACC.d)) < 0) { - SET0(cpustate, OV_FLAG); + SET0(OV_FLAG); if (OVM) { - cpustate->ACC.d = ((INT32)cpustate->oldacc.d < 0) ? 0x80000000 : 0x7fffffff; + m_ACC.d = ((INT32)m_oldacc.d < 0) ? 0x80000000 : 0x7fffffff; } } } -INLINE void CALCULATE_SUB_OVERFLOW(tms32025_state *cpustate, INT32 subval) +void tms32025_device::CALCULATE_SUB_OVERFLOW(INT32 subval) { - if ((INT32)((cpustate->oldacc.d ^ subval) & (cpustate->oldacc.d ^ cpustate->ACC.d)) < 0) + if ((INT32)((m_oldacc.d ^ subval) & (m_oldacc.d ^ m_ACC.d)) < 0) { - SET0(cpustate, OV_FLAG); + SET0(OV_FLAG); if (OVM) { - cpustate->ACC.d = ((INT32)cpustate->oldacc.d < 0) ? 0x80000000 : 0x7fffffff; + m_ACC.d = ((INT32)m_oldacc.d < 0) ? 0x80000000 : 0x7fffffff; } } } -INLINE UINT16 POP_STACK(tms32025_state *cpustate) +UINT16 tms32025_device::POP_STACK() { - UINT16 data = cpustate->STACK[7]; - cpustate->STACK[7] = cpustate->STACK[6]; - cpustate->STACK[6] = cpustate->STACK[5]; - cpustate->STACK[5] = cpustate->STACK[4]; - cpustate->STACK[4] = cpustate->STACK[3]; - cpustate->STACK[3] = cpustate->STACK[2]; - cpustate->STACK[2] = cpustate->STACK[1]; - cpustate->STACK[1] = cpustate->STACK[0]; + UINT16 data = m_STACK[7]; + m_STACK[7] = m_STACK[6]; + m_STACK[6] = m_STACK[5]; + m_STACK[5] = m_STACK[4]; + m_STACK[4] = m_STACK[3]; + m_STACK[3] = m_STACK[2]; + m_STACK[2] = m_STACK[1]; + m_STACK[1] = m_STACK[0]; return data; } -INLINE void PUSH_STACK(tms32025_state *cpustate, UINT16 data) +void tms32025_device::PUSH_STACK(UINT16 data) { - cpustate->STACK[0] = cpustate->STACK[1]; - cpustate->STACK[1] = cpustate->STACK[2]; - cpustate->STACK[2] = cpustate->STACK[3]; - cpustate->STACK[3] = cpustate->STACK[4]; - cpustate->STACK[4] = cpustate->STACK[5]; - cpustate->STACK[5] = cpustate->STACK[6]; - cpustate->STACK[6] = cpustate->STACK[7]; - cpustate->STACK[7] = data; + m_STACK[0] = m_STACK[1]; + m_STACK[1] = m_STACK[2]; + m_STACK[2] = m_STACK[3]; + m_STACK[3] = m_STACK[4]; + m_STACK[4] = m_STACK[5]; + m_STACK[5] = m_STACK[6]; + m_STACK[6] = m_STACK[7]; + m_STACK[7] = data; } -INLINE void SHIFT_Preg_TO_ALU(tms32025_state *cpustate) +void tms32025_device::SHIFT_Preg_TO_ALU() { switch(PM) /* PM (in STR1) is the shift mode for Preg */ { - case 0: cpustate->ALU.d = cpustate->Preg.d; break; - case 1: cpustate->ALU.d = (cpustate->Preg.d << 1); break; - case 2: cpustate->ALU.d = (cpustate->Preg.d << 4); break; - case 3: cpustate->ALU.d = (cpustate->Preg.d >> 6); if (cpustate->Preg.d & 0x80000000) cpustate->ALU.d |= 0xfc000000; break; + case 0: m_ALU.d = m_Preg.d; break; + case 1: m_ALU.d = (m_Preg.d << 1); break; + case 2: m_ALU.d = (m_Preg.d << 4); break; + case 3: m_ALU.d = (m_Preg.d >> 6); if (m_Preg.d & 0x80000000) m_ALU.d |= 0xfc000000; break; default: break; } } -INLINE void GETDATA(tms32025_state *cpustate, int shift,int signext) +void tms32025_device::GETDATA(int shift,int signext) { - if (cpustate->opcode.b.l & 0x80) + if (m_opcode.b.l & 0x80) { /* indirect memory access */ - cpustate->memaccess = IND; + m_memaccess = IND; } else { /* direct memory address */ - cpustate->memaccess = DMA; + m_memaccess = DMA; } - if (cpustate->memaccess >= 0x800) + if (m_memaccess >= 0x800) { - cpustate->external_mem_access = 1; /* Pause if hold pin is active */ + m_external_mem_access = 1; /* Pause if hold pin is active */ } else { - cpustate->external_mem_access = 0; + m_external_mem_access = 0; } - cpustate->ALU.d = (UINT16)M_RDRAM(cpustate, cpustate->memaccess); - if (signext) cpustate->ALU.d = (INT16)cpustate->ALU.d; - cpustate->ALU.d <<= shift; + m_ALU.d = (UINT16)M_RDRAM(m_memaccess); + if (signext) m_ALU.d = (INT16)m_ALU.d; + m_ALU.d <<= shift; /* next ARP */ - if (cpustate->opcode.b.l & 0x80) MODIFY_AR_ARP(cpustate); + if (m_opcode.b.l & 0x80) MODIFY_AR_ARP(); } -INLINE void PUTDATA(tms32025_state *cpustate, UINT16 data) +void tms32025_device::PUTDATA(UINT16 data) { - if (cpustate->opcode.b.l & 0x80) { - if (cpustate->memaccess >= 0x800) cpustate->external_mem_access = 1; /* Pause if hold pin is active */ - else cpustate->external_mem_access = 0; + if (m_opcode.b.l & 0x80) { + if (m_memaccess >= 0x800) m_external_mem_access = 1; /* Pause if hold pin is active */ + else m_external_mem_access = 0; - M_WRTRAM(cpustate, IND, data); - MODIFY_AR_ARP(cpustate); + M_WRTRAM(IND, data); + MODIFY_AR_ARP(); } else { - if (cpustate->memaccess >= 0x800) cpustate->external_mem_access = 1; /* Pause if hold pin is active */ - else cpustate->external_mem_access = 0; + if (m_memaccess >= 0x800) m_external_mem_access = 1; /* Pause if hold pin is active */ + else m_external_mem_access = 0; - M_WRTRAM(cpustate, DMA, data); + M_WRTRAM(DMA, data); } } -INLINE void PUTDATA_SST(tms32025_state *cpustate, UINT16 data) +void tms32025_device::PUTDATA_SST(UINT16 data) { - if (cpustate->opcode.b.l & 0x80) cpustate->memaccess = IND; - else cpustate->memaccess = DMApg0; + if (m_opcode.b.l & 0x80) m_memaccess = IND; + else m_memaccess = DMApg0; - if (cpustate->memaccess >= 0x800) cpustate->external_mem_access = 1; /* Pause if hold pin is active */ - else cpustate->external_mem_access = 0; + if (m_memaccess >= 0x800) m_external_mem_access = 1; /* Pause if hold pin is active */ + else m_external_mem_access = 0; - if (cpustate->opcode.b.l & 0x80) { - cpustate->opcode.b.l &= 0xf7; /* Stop ARP changes */ - MODIFY_AR_ARP(cpustate); + if (m_opcode.b.l & 0x80) { + m_opcode.b.l &= 0xf7; /* Stop ARP changes */ + MODIFY_AR_ARP(); } - M_WRTRAM(cpustate, cpustate->memaccess, data); + M_WRTRAM(m_memaccess, data); } @@ -554,1032 +515,1032 @@ INLINE void PUTDATA_SST(tms32025_state *cpustate, UINT16 data) /* The following functions are here to fill the void for the */ /* opcode call functions. These functions are never actually called. */ -static void opcodes_CE(tms32025_state *cpustate) { } -static void opcodes_Dx(tms32025_state *cpustate) { } +void tms32025_device::opcodes_CE() { fatalerror("Should never get here!\n"); } +void tms32025_device::opcodes_Dx() { fatalerror("Should never get here!\n"); } -static void illegal(tms32025_state *cpustate) +void tms32025_device::illegal() { - logerror("TMS32025: PC = %04x, Illegal opcode = %04x\n", (cpustate->PC-1), cpustate->opcode.w.l); + logerror("TMS32025: PC = %04x, Illegal opcode = %04x\n", (m_PC-1), m_opcode.w.l); } -static void abst(tms32025_state *cpustate) +void tms32025_device::abst() { - if ( (INT32)(cpustate->ACC.d) < 0 ) { - cpustate->ACC.d = -cpustate->ACC.d; - if (cpustate->ACC.d == 0x80000000) { - SET0(cpustate, OV_FLAG); - if (OVM) cpustate->ACC.d-- ; + if ( (INT32)(m_ACC.d) < 0 ) { + m_ACC.d = -m_ACC.d; + if (m_ACC.d == 0x80000000) { + SET0(OV_FLAG); + if (OVM) m_ACC.d-- ; } } - CLR1(cpustate, C_FLAG); + CLR1(C_FLAG); } -static void add(tms32025_state *cpustate) +void tms32025_device::add() { - cpustate->oldacc.d = cpustate->ACC.d; - GETDATA(cpustate, (cpustate->opcode.b.h & 0xf), SXM); - cpustate->ACC.d += cpustate->ALU.d; - CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_ADD_CARRY(cpustate); + m_oldacc.d = m_ACC.d; + GETDATA((m_opcode.b.h & 0xf), SXM); + m_ACC.d += m_ALU.d; + CALCULATE_ADD_OVERFLOW(m_ALU.d); + CALCULATE_ADD_CARRY(); } -static void addc(tms32025_state *cpustate) +void tms32025_device::addc() { - cpustate->oldacc.d = cpustate->ACC.d; - GETDATA(cpustate, 0, 0); - if (CARRY) cpustate->ACC.d++; - cpustate->ACC.d += cpustate->ALU.d; - CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d); - if (cpustate->ACC.d == cpustate->oldacc.d) {} /* edge case, carry remains same */ - else CALCULATE_ADD_CARRY(cpustate); + m_oldacc.d = m_ACC.d; + GETDATA(0, 0); + if (CARRY) m_ACC.d++; + m_ACC.d += m_ALU.d; + CALCULATE_ADD_OVERFLOW(m_ALU.d); + if (m_ACC.d == m_oldacc.d) {} /* edge case, carry remains same */ + else CALCULATE_ADD_CARRY(); } -static void addh(tms32025_state *cpustate) +void tms32025_device::addh() { - cpustate->oldacc.d = cpustate->ACC.d; - GETDATA(cpustate, 0, 0); - cpustate->ACC.w.h += cpustate->ALU.w.l; - if ( (UINT16)(cpustate->oldacc.w.h) > (UINT16)(cpustate->ACC.w.h) ) { - SET1(cpustate, C_FLAG); /* Carry flag is not cleared, if no carry occurred */ + m_oldacc.d = m_ACC.d; + GETDATA(0, 0); + m_ACC.w.h += m_ALU.w.l; + if ( (UINT16)(m_oldacc.w.h) > (UINT16)(m_ACC.w.h) ) { + SET1(C_FLAG); /* Carry flag is not cleared, if no carry occurred */ } - if ((INT16)((cpustate->ACC.w.h ^ cpustate->ALU.w.l) & (cpustate->oldacc.w.h ^ cpustate->ACC.w.h)) < 0) { - SET0(cpustate, OV_FLAG); - if (OVM) cpustate->ACC.w.h = ((INT16)cpustate->oldacc.w.h < 0) ? 0x8000 : 0x7fff; + if ((INT16)((m_ACC.w.h ^ m_ALU.w.l) & (m_oldacc.w.h ^ m_ACC.w.h)) < 0) { + SET0(OV_FLAG); + if (OVM) m_ACC.w.h = ((INT16)m_oldacc.w.h < 0) ? 0x8000 : 0x7fff; } } -static void addk(tms32025_state *cpustate) +void tms32025_device::addk() { - cpustate->oldacc.d = cpustate->ACC.d; - cpustate->ALU.d = (UINT8)cpustate->opcode.b.l; - cpustate->ACC.d += cpustate->ALU.d; - CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_ADD_CARRY(cpustate); + m_oldacc.d = m_ACC.d; + m_ALU.d = (UINT8)m_opcode.b.l; + m_ACC.d += m_ALU.d; + CALCULATE_ADD_OVERFLOW(m_ALU.d); + CALCULATE_ADD_CARRY(); } -static void adds(tms32025_state *cpustate) +void tms32025_device::adds() { - cpustate->oldacc.d = cpustate->ACC.d; - GETDATA(cpustate, 0, 0); - cpustate->ACC.d += cpustate->ALU.d; - CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_ADD_CARRY(cpustate); + m_oldacc.d = m_ACC.d; + GETDATA(0, 0); + m_ACC.d += m_ALU.d; + CALCULATE_ADD_OVERFLOW(m_ALU.d); + CALCULATE_ADD_CARRY(); } -static void addt(tms32025_state *cpustate) +void tms32025_device::addt() { - cpustate->oldacc.d = cpustate->ACC.d; - GETDATA(cpustate, (cpustate->Treg & 0xf), SXM); - cpustate->ACC.d += cpustate->ALU.d; - CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_ADD_CARRY(cpustate); + m_oldacc.d = m_ACC.d; + GETDATA((m_Treg & 0xf), SXM); + m_ACC.d += m_ALU.d; + CALCULATE_ADD_OVERFLOW(m_ALU.d); + CALCULATE_ADD_CARRY(); } -static void adlk(tms32025_state *cpustate) +void tms32025_device::adlk() { - cpustate->oldacc.d = cpustate->ACC.d; - if (SXM) cpustate->ALU.d = (INT16)M_RDOP_ARG(cpustate->PC); - else cpustate->ALU.d = (UINT16)M_RDOP_ARG(cpustate->PC); - cpustate->PC++; - cpustate->ALU.d <<= (cpustate->opcode.b.h & 0xf); - cpustate->ACC.d += cpustate->ALU.d; - CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_ADD_CARRY(cpustate); + m_oldacc.d = m_ACC.d; + if (SXM) m_ALU.d = (INT16)M_RDOP_ARG(m_PC); + else m_ALU.d = (UINT16)M_RDOP_ARG(m_PC); + m_PC++; + m_ALU.d <<= (m_opcode.b.h & 0xf); + m_ACC.d += m_ALU.d; + CALCULATE_ADD_OVERFLOW(m_ALU.d); + CALCULATE_ADD_CARRY(); } -static void adrk(tms32025_state *cpustate) +void tms32025_device::adrk() { - cpustate->AR[ARP] += cpustate->opcode.b.l; + m_AR[ARP] += m_opcode.b.l; } -static void and_(tms32025_state *cpustate) +void tms32025_device::and_() { - GETDATA(cpustate, 0, 0); - cpustate->ACC.d &= cpustate->ALU.d; + GETDATA(0, 0); + m_ACC.d &= m_ALU.d; } -static void andk(tms32025_state *cpustate) +void tms32025_device::andk() { - cpustate->oldacc.d = cpustate->ACC.d; - cpustate->ALU.d = (UINT16)M_RDOP_ARG(cpustate->PC); - cpustate->PC++; - cpustate->ALU.d <<= (cpustate->opcode.b.h & 0xf); - cpustate->ACC.d &= cpustate->ALU.d; + m_oldacc.d = m_ACC.d; + m_ALU.d = (UINT16)M_RDOP_ARG(m_PC); + m_PC++; + m_ALU.d <<= (m_opcode.b.h & 0xf); + m_ACC.d &= m_ALU.d; } -static void apac(tms32025_state *cpustate) +void tms32025_device::apac() { - cpustate->oldacc.d = cpustate->ACC.d; - SHIFT_Preg_TO_ALU(cpustate); - cpustate->ACC.d += cpustate->ALU.d; - CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_ADD_CARRY(cpustate); + m_oldacc.d = m_ACC.d; + SHIFT_Preg_TO_ALU(); + m_ACC.d += m_ALU.d; + CALCULATE_ADD_OVERFLOW(m_ALU.d); + CALCULATE_ADD_CARRY(); } -static void br(tms32025_state *cpustate) +void tms32025_device::br() { - SET_PC(M_RDOP_ARG(cpustate->PC)); - MODIFY_AR_ARP(cpustate); + SET_PC(M_RDOP_ARG(m_PC)); + MODIFY_AR_ARP(); } -static void bacc(tms32025_state *cpustate) +void tms32025_device::bacc() { - SET_PC(cpustate->ACC.w.l); + SET_PC(m_ACC.w.l); } -static void banz(tms32025_state *cpustate) +void tms32025_device::banz() { - if (cpustate->AR[ARP]) SET_PC(M_RDOP_ARG(cpustate->PC)); - else cpustate->PC++ ; - MODIFY_AR_ARP(cpustate); + if (m_AR[ARP]) SET_PC(M_RDOP_ARG(m_PC)); + else m_PC++ ; + MODIFY_AR_ARP(); } -static void bbnz(tms32025_state *cpustate) +void tms32025_device::bbnz() { - if (TC) SET_PC(M_RDOP_ARG(cpustate->PC)); - else cpustate->PC++ ; - MODIFY_AR_ARP(cpustate); + if (TC) SET_PC(M_RDOP_ARG(m_PC)); + else m_PC++ ; + MODIFY_AR_ARP(); } -static void bbz(tms32025_state *cpustate) +void tms32025_device::bbz() { - if (TC == 0) SET_PC(M_RDOP_ARG(cpustate->PC)); - else cpustate->PC++ ; - MODIFY_AR_ARP(cpustate); + if (TC == 0) SET_PC(M_RDOP_ARG(m_PC)); + else m_PC++ ; + MODIFY_AR_ARP(); } -static void bc(tms32025_state *cpustate) +void tms32025_device::bc() { - if (CARRY) SET_PC(M_RDOP_ARG(cpustate->PC)); - else cpustate->PC++ ; - MODIFY_AR_ARP(cpustate); + if (CARRY) SET_PC(M_RDOP_ARG(m_PC)); + else m_PC++ ; + MODIFY_AR_ARP(); } -static void bgez(tms32025_state *cpustate) +void tms32025_device::bgez() { - if ( (INT32)(cpustate->ACC.d) >= 0 ) SET_PC(M_RDOP_ARG(cpustate->PC)); - else cpustate->PC++ ; - MODIFY_AR_ARP(cpustate); + if ( (INT32)(m_ACC.d) >= 0 ) SET_PC(M_RDOP_ARG(m_PC)); + else m_PC++ ; + MODIFY_AR_ARP(); } -static void bgz(tms32025_state *cpustate) +void tms32025_device::bgz() { - if ( (INT32)(cpustate->ACC.d) > 0 ) SET_PC(M_RDOP_ARG(cpustate->PC)); - else cpustate->PC++ ; - MODIFY_AR_ARP(cpustate); + if ( (INT32)(m_ACC.d) > 0 ) SET_PC(M_RDOP_ARG(m_PC)); + else m_PC++ ; + MODIFY_AR_ARP(); } -static void bioz(tms32025_state *cpustate) +void tms32025_device::bioz() { - if (S_IN(TMS32025_BIO) != CLEAR_LINE) SET_PC(M_RDOP_ARG(cpustate->PC)); - else cpustate->PC++ ; - MODIFY_AR_ARP(cpustate); + if (S_IN(TMS32025_BIO) != CLEAR_LINE) SET_PC(M_RDOP_ARG(m_PC)); + else m_PC++ ; + MODIFY_AR_ARP(); } -static void bit(tms32025_state *cpustate) +void tms32025_device::bit() { - GETDATA(cpustate, 0, 0); - if (cpustate->ALU.d & (0x8000 >> (cpustate->opcode.b.h & 0xf))) SET1(cpustate, TC_FLAG); - else CLR1(cpustate, TC_FLAG); + GETDATA(0, 0); + if (m_ALU.d & (0x8000 >> (m_opcode.b.h & 0xf))) SET1(TC_FLAG); + else CLR1(TC_FLAG); } -static void bitt(tms32025_state *cpustate) +void tms32025_device::bitt() { - GETDATA(cpustate, 0, 0); - if (cpustate->ALU.d & (0x8000 >> (cpustate->Treg & 0xf))) SET1(cpustate, TC_FLAG); - else CLR1(cpustate, TC_FLAG); + GETDATA(0, 0); + if (m_ALU.d & (0x8000 >> (m_Treg & 0xf))) SET1(TC_FLAG); + else CLR1(TC_FLAG); } -static void blez(tms32025_state *cpustate) +void tms32025_device::blez() { - if ( (INT32)(cpustate->ACC.d) <= 0 ) SET_PC(M_RDOP_ARG(cpustate->PC)); - else cpustate->PC++ ; - MODIFY_AR_ARP(cpustate); + if ( (INT32)(m_ACC.d) <= 0 ) SET_PC(M_RDOP_ARG(m_PC)); + else m_PC++ ; + MODIFY_AR_ARP(); } -static void blkd(tms32025_state *cpustate) +void tms32025_device::blkd() { /** Fix cycle timing **/ - if (cpustate->init_load_addr) { - cpustate->PFC = M_RDOP_ARG(cpustate->PC); - cpustate->PC++; + if (m_init_load_addr) { + m_PFC = M_RDOP_ARG(m_PC); + m_PC++; } - cpustate->ALU.d = M_RDRAM(cpustate, cpustate->PFC); - PUTDATA(cpustate, cpustate->ALU.d); - cpustate->PFC++; - cpustate->tms32025_dec_cycles += (1*CLK); + m_ALU.d = M_RDRAM(m_PFC); + PUTDATA(m_ALU.d); + m_PFC++; + m_tms32025_dec_cycles += (1*CLK); } -static void blkp(tms32025_state *cpustate) +void tms32025_device::blkp() { /** Fix cycle timing **/ - if (cpustate->init_load_addr) { - cpustate->PFC = M_RDOP_ARG(cpustate->PC); - cpustate->PC++; + if (m_init_load_addr) { + m_PFC = M_RDOP_ARG(m_PC); + m_PC++; } - cpustate->ALU.d = M_RDROM(cpustate, cpustate->PFC); - PUTDATA(cpustate, cpustate->ALU.d); - cpustate->PFC++; - cpustate->tms32025_dec_cycles += (2*CLK); + m_ALU.d = M_RDROM(m_PFC); + PUTDATA(m_ALU.d); + m_PFC++; + m_tms32025_dec_cycles += (2*CLK); } -static void blz(tms32025_state *cpustate) +void tms32025_device::blz() { - if ( (INT32)(cpustate->ACC.d) < 0 ) SET_PC(M_RDOP_ARG(cpustate->PC)); - else cpustate->PC++ ; - MODIFY_AR_ARP(cpustate); + if ( (INT32)(m_ACC.d) < 0 ) SET_PC(M_RDOP_ARG(m_PC)); + else m_PC++ ; + MODIFY_AR_ARP(); } -static void bnc(tms32025_state *cpustate) +void tms32025_device::bnc() { - if (CARRY == 0) SET_PC(M_RDOP_ARG(cpustate->PC)); - else cpustate->PC++ ; - MODIFY_AR_ARP(cpustate); + if (CARRY == 0) SET_PC(M_RDOP_ARG(m_PC)); + else m_PC++ ; + MODIFY_AR_ARP(); } -static void bnv(tms32025_state *cpustate) +void tms32025_device::bnv() { - if (OV == 0) SET_PC(M_RDOP_ARG(cpustate->PC)); + if (OV == 0) SET_PC(M_RDOP_ARG(m_PC)); else { - cpustate->PC++ ; - CLR0(cpustate, OV_FLAG); + m_PC++ ; + CLR0(OV_FLAG); } - MODIFY_AR_ARP(cpustate); + MODIFY_AR_ARP(); } -static void bnz(tms32025_state *cpustate) +void tms32025_device::bnz() { - if (cpustate->ACC.d != 0) SET_PC(M_RDOP_ARG(cpustate->PC)); - else cpustate->PC++ ; - MODIFY_AR_ARP(cpustate); + if (m_ACC.d != 0) SET_PC(M_RDOP_ARG(m_PC)); + else m_PC++ ; + MODIFY_AR_ARP(); } -static void bv(tms32025_state *cpustate) +void tms32025_device::bv() { if (OV) { - SET_PC(M_RDOP_ARG(cpustate->PC)); - CLR0(cpustate, OV_FLAG); + SET_PC(M_RDOP_ARG(m_PC)); + CLR0(OV_FLAG); } - else cpustate->PC++ ; - MODIFY_AR_ARP(cpustate); + else m_PC++ ; + MODIFY_AR_ARP(); } -static void bz(tms32025_state *cpustate) +void tms32025_device::bz() { - if (cpustate->ACC.d == 0) SET_PC(M_RDOP_ARG(cpustate->PC)); - else cpustate->PC++ ; - MODIFY_AR_ARP(cpustate); + if (m_ACC.d == 0) SET_PC(M_RDOP_ARG(m_PC)); + else m_PC++ ; + MODIFY_AR_ARP(); } -static void cala(tms32025_state *cpustate) +void tms32025_device::cala() { - PUSH_STACK(cpustate, cpustate->PC); - SET_PC(cpustate->ACC.w.l); + PUSH_STACK(m_PC); + SET_PC(m_ACC.w.l); } -static void call(tms32025_state *cpustate) +void tms32025_device::call() { - cpustate->PC++ ; - PUSH_STACK(cpustate, cpustate->PC); - SET_PC(M_RDOP_ARG((cpustate->PC - 1))); - MODIFY_AR_ARP(cpustate); + m_PC++ ; + PUSH_STACK(m_PC); + SET_PC(M_RDOP_ARG((m_PC - 1))); + MODIFY_AR_ARP(); } -static void cmpl(tms32025_state *cpustate) +void tms32025_device::cmpl() { - cpustate->ACC.d = (~cpustate->ACC.d); + m_ACC.d = (~m_ACC.d); } -static void cmpr(tms32025_state *cpustate) +void tms32025_device::cmpr() { - switch (cpustate->opcode.b.l & 3) + switch (m_opcode.b.l & 3) { - case 00: if ( (UINT16)(cpustate->AR[ARP]) == (UINT16)(cpustate->AR[0]) ) SET1(cpustate, TC_FLAG); - else CLR1(cpustate, TC_FLAG); + case 00: if ( (UINT16)(m_AR[ARP]) == (UINT16)(m_AR[0]) ) SET1(TC_FLAG); + else CLR1(TC_FLAG); break; - case 01: if ( (UINT16)(cpustate->AR[ARP]) < (UINT16)(cpustate->AR[0]) ) SET1(cpustate, TC_FLAG); - else CLR1(cpustate, TC_FLAG); + case 01: if ( (UINT16)(m_AR[ARP]) < (UINT16)(m_AR[0]) ) SET1(TC_FLAG); + else CLR1(TC_FLAG); break; - case 02: if ( (UINT16)(cpustate->AR[ARP]) > (UINT16)(cpustate->AR[0]) ) SET1(cpustate, TC_FLAG); - else CLR1(cpustate, TC_FLAG); + case 02: if ( (UINT16)(m_AR[ARP]) > (UINT16)(m_AR[0]) ) SET1(TC_FLAG); + else CLR1(TC_FLAG); break; - case 03: if ( (UINT16)(cpustate->AR[ARP]) != (UINT16)(cpustate->AR[0]) ) SET1(cpustate, TC_FLAG); - else CLR1(cpustate, TC_FLAG); + case 03: if ( (UINT16)(m_AR[ARP]) != (UINT16)(m_AR[0]) ) SET1(TC_FLAG); + else CLR1(TC_FLAG); break; } } -static void cnfd(tms32025_state *cpustate) /** next two fetches need to use previous CNF value ! **/ +void tms32025_device::cnfd() /** next two fetches need to use previous CNF value ! **/ { - CLR1(cpustate, CNF0_REG); - cpustate->datamap[4] = &cpustate->intRAM[0x200]; /* B0 */ - cpustate->datamap[5] = &cpustate->intRAM[0x280]; /* B0 */ - cpustate->pgmmap[510] = NULL; - cpustate->pgmmap[511] = NULL; + CLR1(CNF0_REG); + m_datamap[4] = &m_intRAM[0x200]; /* B0 */ + m_datamap[5] = &m_intRAM[0x280]; /* B0 */ + m_pgmmap[510] = NULL; + m_pgmmap[511] = NULL; } -static void cnfp(tms32025_state *cpustate) /** next two fetches need to use previous CNF value ! **/ +void tms32025_device::cnfp() /** next two fetches need to use previous CNF value ! **/ { - SET1(cpustate, CNF0_REG); - cpustate->datamap[4] = NULL; /* B0 */ - cpustate->datamap[5] = NULL; /* B0 */ - cpustate->pgmmap[510] = &cpustate->intRAM[0x200]; - cpustate->pgmmap[511] = &cpustate->intRAM[0x280]; + SET1(CNF0_REG); + m_datamap[4] = NULL; /* B0 */ + m_datamap[5] = NULL; /* B0 */ + m_pgmmap[510] = &m_intRAM[0x200]; + m_pgmmap[511] = &m_intRAM[0x280]; } -static void conf(tms32025_state *cpustate) /** Need to reconfigure the memory blocks */ +void tms32025_device::conf() /** Need to reconfigure the memory blocks */ { - switch (cpustate->opcode.b.l & 3) + switch (m_opcode.b.l & 3) { - case 00: CLR1(cpustate, CNF1_REG); CLR1(cpustate, CNF0_REG); - cpustate->datamap[4] = &cpustate->intRAM[0x200]; /* B0 */ - cpustate->datamap[5] = &cpustate->intRAM[0x280]; /* B0 */ - cpustate->datamap[6] = &cpustate->intRAM[0x300]; /* B0 */ - cpustate->datamap[7] = &cpustate->intRAM[0x380]; /* B0 */ - cpustate->datamap[8] = &cpustate->intRAM[0x400]; /* B1 */ - cpustate->datamap[9] = &cpustate->intRAM[0x480]; /* B1 */ - cpustate->datamap[10] = &cpustate->intRAM[0x500]; /* B1 */ - cpustate->datamap[11] = &cpustate->intRAM[0x580]; /* B1 */ - cpustate->datamap[12] = &cpustate->intRAM[0x600]; /* B3 */ - cpustate->datamap[13] = &cpustate->intRAM[0x680]; /* B3 */ - cpustate->datamap[14] = &cpustate->intRAM[0x700]; /* B3 */ - cpustate->datamap[15] = &cpustate->intRAM[0x780]; /* B3 */ - cpustate->pgmmap[500] = NULL; - cpustate->pgmmap[501] = NULL; - cpustate->pgmmap[502] = NULL; - cpustate->pgmmap[503] = NULL; - cpustate->pgmmap[504] = NULL; - cpustate->pgmmap[505] = NULL; - cpustate->pgmmap[506] = NULL; - cpustate->pgmmap[507] = NULL; - cpustate->pgmmap[508] = NULL; - cpustate->pgmmap[509] = NULL; - cpustate->pgmmap[510] = NULL; - cpustate->pgmmap[511] = NULL; + case 00: CLR1(CNF1_REG); CLR1(CNF0_REG); + m_datamap[4] = &m_intRAM[0x200]; /* B0 */ + m_datamap[5] = &m_intRAM[0x280]; /* B0 */ + m_datamap[6] = &m_intRAM[0x300]; /* B0 */ + m_datamap[7] = &m_intRAM[0x380]; /* B0 */ + m_datamap[8] = &m_intRAM[0x400]; /* B1 */ + m_datamap[9] = &m_intRAM[0x480]; /* B1 */ + m_datamap[10] = &m_intRAM[0x500]; /* B1 */ + m_datamap[11] = &m_intRAM[0x580]; /* B1 */ + m_datamap[12] = &m_intRAM[0x600]; /* B3 */ + m_datamap[13] = &m_intRAM[0x680]; /* B3 */ + m_datamap[14] = &m_intRAM[0x700]; /* B3 */ + m_datamap[15] = &m_intRAM[0x780]; /* B3 */ + m_pgmmap[500] = NULL; + m_pgmmap[501] = NULL; + m_pgmmap[502] = NULL; + m_pgmmap[503] = NULL; + m_pgmmap[504] = NULL; + m_pgmmap[505] = NULL; + m_pgmmap[506] = NULL; + m_pgmmap[507] = NULL; + m_pgmmap[508] = NULL; + m_pgmmap[509] = NULL; + m_pgmmap[510] = NULL; + m_pgmmap[511] = NULL; break; - case 01: CLR1(cpustate, CNF1_REG); SET1(cpustate, CNF0_REG); - cpustate->datamap[4] = NULL; - cpustate->datamap[5] = NULL; - cpustate->datamap[6] = NULL; - cpustate->datamap[7] = NULL; - cpustate->datamap[8] = &cpustate->intRAM[0x400]; /* B1 */ - cpustate->datamap[9] = &cpustate->intRAM[0x480]; /* B1 */ - cpustate->datamap[10] = &cpustate->intRAM[0x500]; /* B1 */ - cpustate->datamap[11] = &cpustate->intRAM[0x580]; /* B1 */ - cpustate->datamap[12] = &cpustate->intRAM[0x600]; /* B3 */ - cpustate->datamap[13] = &cpustate->intRAM[0x680]; /* B3 */ - cpustate->datamap[14] = &cpustate->intRAM[0x700]; /* B3 */ - cpustate->datamap[15] = &cpustate->intRAM[0x780]; /* B3 */ - cpustate->pgmmap[500] = &cpustate->intRAM[0x200]; /* B0 */ - cpustate->pgmmap[501] = &cpustate->intRAM[0x280]; /* B0 */ - cpustate->pgmmap[502] = &cpustate->intRAM[0x300]; /* B0 */ - cpustate->pgmmap[503] = &cpustate->intRAM[0x380]; /* B0 */ - cpustate->pgmmap[504] = NULL; - cpustate->pgmmap[505] = NULL; - cpustate->pgmmap[506] = NULL; - cpustate->pgmmap[507] = NULL; - cpustate->pgmmap[508] = NULL; - cpustate->pgmmap[509] = NULL; - cpustate->pgmmap[510] = NULL; - cpustate->pgmmap[511] = NULL; + case 01: CLR1(CNF1_REG); SET1(CNF0_REG); + m_datamap[4] = NULL; + m_datamap[5] = NULL; + m_datamap[6] = NULL; + m_datamap[7] = NULL; + m_datamap[8] = &m_intRAM[0x400]; /* B1 */ + m_datamap[9] = &m_intRAM[0x480]; /* B1 */ + m_datamap[10] = &m_intRAM[0x500]; /* B1 */ + m_datamap[11] = &m_intRAM[0x580]; /* B1 */ + m_datamap[12] = &m_intRAM[0x600]; /* B3 */ + m_datamap[13] = &m_intRAM[0x680]; /* B3 */ + m_datamap[14] = &m_intRAM[0x700]; /* B3 */ + m_datamap[15] = &m_intRAM[0x780]; /* B3 */ + m_pgmmap[500] = &m_intRAM[0x200]; /* B0 */ + m_pgmmap[501] = &m_intRAM[0x280]; /* B0 */ + m_pgmmap[502] = &m_intRAM[0x300]; /* B0 */ + m_pgmmap[503] = &m_intRAM[0x380]; /* B0 */ + m_pgmmap[504] = NULL; + m_pgmmap[505] = NULL; + m_pgmmap[506] = NULL; + m_pgmmap[507] = NULL; + m_pgmmap[508] = NULL; + m_pgmmap[509] = NULL; + m_pgmmap[510] = NULL; + m_pgmmap[511] = NULL; break; - case 02: SET1(cpustate, CNF1_REG); CLR1(cpustate, CNF0_REG); - cpustate->datamap[4] = NULL; - cpustate->datamap[5] = NULL; - cpustate->datamap[6] = NULL; - cpustate->datamap[7] = NULL; - cpustate->datamap[8] = NULL; - cpustate->datamap[9] = NULL; - cpustate->datamap[10] = NULL; - cpustate->datamap[11] = NULL; - cpustate->datamap[12] = &cpustate->intRAM[0x600]; /* B3 */ - cpustate->datamap[13] = &cpustate->intRAM[0x680]; /* B3 */ - cpustate->datamap[14] = &cpustate->intRAM[0x700]; /* B3 */ - cpustate->datamap[15] = &cpustate->intRAM[0x780]; /* B3 */ - cpustate->pgmmap[500] = &cpustate->intRAM[0x200]; /* B0 */ - cpustate->pgmmap[501] = &cpustate->intRAM[0x280]; /* B0 */ - cpustate->pgmmap[502] = &cpustate->intRAM[0x300]; /* B0 */ - cpustate->pgmmap[503] = &cpustate->intRAM[0x380]; /* B0 */ - cpustate->pgmmap[504] = &cpustate->intRAM[0x400]; /* B1 */ - cpustate->pgmmap[505] = &cpustate->intRAM[0x480]; /* B1 */ - cpustate->pgmmap[506] = &cpustate->intRAM[0x500]; /* B1 */ - cpustate->pgmmap[507] = &cpustate->intRAM[0x580]; /* B1 */ - cpustate->pgmmap[508] = NULL; - cpustate->pgmmap[509] = NULL; - cpustate->pgmmap[510] = NULL; - cpustate->pgmmap[511] = NULL; + case 02: SET1(CNF1_REG); CLR1(CNF0_REG); + m_datamap[4] = NULL; + m_datamap[5] = NULL; + m_datamap[6] = NULL; + m_datamap[7] = NULL; + m_datamap[8] = NULL; + m_datamap[9] = NULL; + m_datamap[10] = NULL; + m_datamap[11] = NULL; + m_datamap[12] = &m_intRAM[0x600]; /* B3 */ + m_datamap[13] = &m_intRAM[0x680]; /* B3 */ + m_datamap[14] = &m_intRAM[0x700]; /* B3 */ + m_datamap[15] = &m_intRAM[0x780]; /* B3 */ + m_pgmmap[500] = &m_intRAM[0x200]; /* B0 */ + m_pgmmap[501] = &m_intRAM[0x280]; /* B0 */ + m_pgmmap[502] = &m_intRAM[0x300]; /* B0 */ + m_pgmmap[503] = &m_intRAM[0x380]; /* B0 */ + m_pgmmap[504] = &m_intRAM[0x400]; /* B1 */ + m_pgmmap[505] = &m_intRAM[0x480]; /* B1 */ + m_pgmmap[506] = &m_intRAM[0x500]; /* B1 */ + m_pgmmap[507] = &m_intRAM[0x580]; /* B1 */ + m_pgmmap[508] = NULL; + m_pgmmap[509] = NULL; + m_pgmmap[510] = NULL; + m_pgmmap[511] = NULL; break; - case 03: SET1(cpustate, CNF1_REG); SET1(cpustate, CNF0_REG); - cpustate->datamap[4] = NULL; - cpustate->datamap[5] = NULL; - cpustate->datamap[6] = NULL; - cpustate->datamap[7] = NULL; - cpustate->datamap[8] = NULL; - cpustate->datamap[9] = NULL; - cpustate->datamap[10] = NULL; - cpustate->datamap[11] = NULL; - cpustate->datamap[12] = NULL; - cpustate->datamap[13] = NULL; - cpustate->datamap[14] = NULL; - cpustate->datamap[15] = NULL; - cpustate->pgmmap[500] = &cpustate->intRAM[0x200]; /* B0 */ - cpustate->pgmmap[501] = &cpustate->intRAM[0x280]; /* B0 */ - cpustate->pgmmap[502] = &cpustate->intRAM[0x300]; /* B0 */ - cpustate->pgmmap[503] = &cpustate->intRAM[0x380]; /* B0 */ - cpustate->pgmmap[504] = &cpustate->intRAM[0x400]; /* B1 */ - cpustate->pgmmap[505] = &cpustate->intRAM[0x480]; /* B1 */ - cpustate->pgmmap[506] = &cpustate->intRAM[0x500]; /* B1 */ - cpustate->pgmmap[507] = &cpustate->intRAM[0x580]; /* B1 */ - cpustate->pgmmap[508] = &cpustate->intRAM[0x600]; /* B3 */ - cpustate->pgmmap[509] = &cpustate->intRAM[0x680]; /* B3 */ - cpustate->pgmmap[510] = &cpustate->intRAM[0x700]; /* B3 */ - cpustate->pgmmap[511] = &cpustate->intRAM[0x780]; /* B3 */ + case 03: SET1(CNF1_REG); SET1(CNF0_REG); + m_datamap[4] = NULL; + m_datamap[5] = NULL; + m_datamap[6] = NULL; + m_datamap[7] = NULL; + m_datamap[8] = NULL; + m_datamap[9] = NULL; + m_datamap[10] = NULL; + m_datamap[11] = NULL; + m_datamap[12] = NULL; + m_datamap[13] = NULL; + m_datamap[14] = NULL; + m_datamap[15] = NULL; + m_pgmmap[500] = &m_intRAM[0x200]; /* B0 */ + m_pgmmap[501] = &m_intRAM[0x280]; /* B0 */ + m_pgmmap[502] = &m_intRAM[0x300]; /* B0 */ + m_pgmmap[503] = &m_intRAM[0x380]; /* B0 */ + m_pgmmap[504] = &m_intRAM[0x400]; /* B1 */ + m_pgmmap[505] = &m_intRAM[0x480]; /* B1 */ + m_pgmmap[506] = &m_intRAM[0x500]; /* B1 */ + m_pgmmap[507] = &m_intRAM[0x580]; /* B1 */ + m_pgmmap[508] = &m_intRAM[0x600]; /* B3 */ + m_pgmmap[509] = &m_intRAM[0x680]; /* B3 */ + m_pgmmap[510] = &m_intRAM[0x700]; /* B3 */ + m_pgmmap[511] = &m_intRAM[0x780]; /* B3 */ break; } } -static void dint(tms32025_state *cpustate) +void tms32025_device::dint() { - SET0(cpustate, INTM_FLAG); + SET0(INTM_FLAG); } -static void dmov(tms32025_state *cpustate) /** Careful with how memory is configured !! */ +void tms32025_device::dmov() /** Careful with how memory is configured !! */ { - GETDATA(cpustate, 0, 0); - M_WRTRAM(cpustate, (cpustate->memaccess + 1), cpustate->ALU.w.l); + GETDATA(0, 0); + M_WRTRAM((m_memaccess + 1), m_ALU.w.l); } -static void eint(tms32025_state *cpustate) +void tms32025_device::eint() { - CLR0(cpustate, INTM_FLAG); + CLR0(INTM_FLAG); } -static void fort(tms32025_state *cpustate) +void tms32025_device::fort() { - if (cpustate->opcode.b.l & 1) SET1(cpustate, FO_FLAG); - else CLR1(cpustate, FO_FLAG); + if (m_opcode.b.l & 1) SET1(FO_FLAG); + else CLR1(FO_FLAG); } -static void idle(tms32025_state *cpustate) +void tms32025_device::idle() { - CLR0(cpustate, INTM_FLAG); - cpustate->idle = 1; + CLR0(INTM_FLAG); + m_idle = 1; } -static void in(tms32025_state *cpustate) +void tms32025_device::in() { - cpustate->ALU.w.l = P_IN( (cpustate->opcode.b.h & 0xf) ); - PUTDATA(cpustate, cpustate->ALU.w.l); + m_ALU.w.l = P_IN( (m_opcode.b.h & 0xf) ); + PUTDATA(m_ALU.w.l); } -static void lac(tms32025_state *cpustate) +void tms32025_device::lac() { - GETDATA(cpustate, (cpustate->opcode.b.h & 0xf), SXM); - cpustate->ACC.d = cpustate->ALU.d; + GETDATA((m_opcode.b.h & 0xf), SXM); + m_ACC.d = m_ALU.d; } -static void lack(tms32025_state *cpustate) /* ZAC is a subset of this instruction */ +void tms32025_device::lack() /* ZAC is a subset of this instruction */ { - cpustate->ACC.d = (UINT8)cpustate->opcode.b.l; + m_ACC.d = (UINT8)m_opcode.b.l; } -static void lact(tms32025_state *cpustate) +void tms32025_device::lact() { - GETDATA(cpustate, (cpustate->Treg & 0xf), SXM); - cpustate->ACC.d = cpustate->ALU.d; + GETDATA((m_Treg & 0xf), SXM); + m_ACC.d = m_ALU.d; } -static void lalk(tms32025_state *cpustate) +void tms32025_device::lalk() { - if (SXM) cpustate->ALU.d = (INT16)M_RDOP_ARG(cpustate->PC); - else cpustate->ALU.d = (UINT16)M_RDOP_ARG(cpustate->PC); - cpustate->PC++; - cpustate->ALU.d <<= (cpustate->opcode.b.h & 0xf); - cpustate->ACC.d = cpustate->ALU.d; + if (SXM) m_ALU.d = (INT16)M_RDOP_ARG(m_PC); + else m_ALU.d = (UINT16)M_RDOP_ARG(m_PC); + m_PC++; + m_ALU.d <<= (m_opcode.b.h & 0xf); + m_ACC.d = m_ALU.d; } -static void lar_ar0(tms32025_state *cpustate) { GETDATA(cpustate, 0, 0); cpustate->AR[0] = cpustate->ALU.w.l; } -static void lar_ar1(tms32025_state *cpustate) { GETDATA(cpustate, 0, 0); cpustate->AR[1] = cpustate->ALU.w.l; } -static void lar_ar2(tms32025_state *cpustate) { GETDATA(cpustate, 0, 0); cpustate->AR[2] = cpustate->ALU.w.l; } -static void lar_ar3(tms32025_state *cpustate) { GETDATA(cpustate, 0, 0); cpustate->AR[3] = cpustate->ALU.w.l; } -static void lar_ar4(tms32025_state *cpustate) { GETDATA(cpustate, 0, 0); cpustate->AR[4] = cpustate->ALU.w.l; } -static void lar_ar5(tms32025_state *cpustate) { GETDATA(cpustate, 0, 0); cpustate->AR[5] = cpustate->ALU.w.l; } -static void lar_ar6(tms32025_state *cpustate) { GETDATA(cpustate, 0, 0); cpustate->AR[6] = cpustate->ALU.w.l; } -static void lar_ar7(tms32025_state *cpustate) { GETDATA(cpustate, 0, 0); cpustate->AR[7] = cpustate->ALU.w.l; } -static void lark_ar0(tms32025_state *cpustate) { cpustate->AR[0] = cpustate->opcode.b.l; } -static void lark_ar1(tms32025_state *cpustate) { cpustate->AR[1] = cpustate->opcode.b.l; } -static void lark_ar2(tms32025_state *cpustate) { cpustate->AR[2] = cpustate->opcode.b.l; } -static void lark_ar3(tms32025_state *cpustate) { cpustate->AR[3] = cpustate->opcode.b.l; } -static void lark_ar4(tms32025_state *cpustate) { cpustate->AR[4] = cpustate->opcode.b.l; } -static void lark_ar5(tms32025_state *cpustate) { cpustate->AR[5] = cpustate->opcode.b.l; } -static void lark_ar6(tms32025_state *cpustate) { cpustate->AR[6] = cpustate->opcode.b.l; } -static void lark_ar7(tms32025_state *cpustate) { cpustate->AR[7] = cpustate->opcode.b.l; } -static void ldp(tms32025_state *cpustate) +void tms32025_device::lar_ar0() { GETDATA(0, 0); m_AR[0] = m_ALU.w.l; } +void tms32025_device::lar_ar1() { GETDATA(0, 0); m_AR[1] = m_ALU.w.l; } +void tms32025_device::lar_ar2() { GETDATA(0, 0); m_AR[2] = m_ALU.w.l; } +void tms32025_device::lar_ar3() { GETDATA(0, 0); m_AR[3] = m_ALU.w.l; } +void tms32025_device::lar_ar4() { GETDATA(0, 0); m_AR[4] = m_ALU.w.l; } +void tms32025_device::lar_ar5() { GETDATA(0, 0); m_AR[5] = m_ALU.w.l; } +void tms32025_device::lar_ar6() { GETDATA(0, 0); m_AR[6] = m_ALU.w.l; } +void tms32025_device::lar_ar7() { GETDATA(0, 0); m_AR[7] = m_ALU.w.l; } +void tms32025_device::lark_ar0() { m_AR[0] = m_opcode.b.l; } +void tms32025_device::lark_ar1() { m_AR[1] = m_opcode.b.l; } +void tms32025_device::lark_ar2() { m_AR[2] = m_opcode.b.l; } +void tms32025_device::lark_ar3() { m_AR[3] = m_opcode.b.l; } +void tms32025_device::lark_ar4() { m_AR[4] = m_opcode.b.l; } +void tms32025_device::lark_ar5() { m_AR[5] = m_opcode.b.l; } +void tms32025_device::lark_ar6() { m_AR[6] = m_opcode.b.l; } +void tms32025_device::lark_ar7() { m_AR[7] = m_opcode.b.l; } +void tms32025_device::ldp() { - GETDATA(cpustate, 0, 0); - MODIFY_DP(cpustate, cpustate->ALU.d & 0x1ff); + GETDATA(0, 0); + MODIFY_DP(m_ALU.d & 0x1ff); } -static void ldpk(tms32025_state *cpustate) +void tms32025_device::ldpk() { - MODIFY_DP(cpustate, cpustate->opcode.w.l & 0x1ff); + MODIFY_DP(m_opcode.w.l & 0x1ff); } -static void lph(tms32025_state *cpustate) +void tms32025_device::lph() { - GETDATA(cpustate, 0, 0); - cpustate->Preg.w.h = cpustate->ALU.w.l; + GETDATA(0, 0); + m_Preg.w.h = m_ALU.w.l; } -static void lrlk(tms32025_state *cpustate) +void tms32025_device::lrlk() { - cpustate->ALU.d = (UINT16)M_RDOP_ARG(cpustate->PC); - cpustate->PC++; - cpustate->AR[cpustate->opcode.b.h & 7] = cpustate->ALU.w.l; + m_ALU.d = (UINT16)M_RDOP_ARG(m_PC); + m_PC++; + m_AR[m_opcode.b.h & 7] = m_ALU.w.l; } -static void lst(tms32025_state *cpustate) +void tms32025_device::lst() { - cpustate->mHackIgnoreARP = 1; - GETDATA(cpustate, 0, 0); - cpustate->mHackIgnoreARP = 0; + m_mHackIgnoreARP = 1; + GETDATA(0, 0); + m_mHackIgnoreARP = 0; - cpustate->ALU.w.l &= (~INTM_FLAG); - cpustate->STR0 &= INTM_FLAG; - cpustate->STR0 |= cpustate->ALU.w.l; /* Must not affect INTM */ - cpustate->STR0 |= 0x0400; + m_ALU.w.l &= (~INTM_FLAG); + m_STR0 &= INTM_FLAG; + m_STR0 |= m_ALU.w.l; /* Must not affect INTM */ + m_STR0 |= 0x0400; } -static void lst1(tms32025_state *cpustate) +void tms32025_device::lst1() { - cpustate->mHackIgnoreARP = 1; - GETDATA(cpustate, 0, 0); - cpustate->mHackIgnoreARP = 0; + m_mHackIgnoreARP = 1; + GETDATA(0, 0); + m_mHackIgnoreARP = 0; - cpustate->STR1 = cpustate->ALU.w.l; - cpustate->STR1 |= 0x0180; - cpustate->STR0 &= (~ARP_REG); /* ARB also gets copied to ARP */ - cpustate->STR0 |= (cpustate->STR1 & ARB_REG); + m_STR1 = m_ALU.w.l; + m_STR1 |= 0x0180; + m_STR0 &= (~ARP_REG); /* ARB also gets copied to ARP */ + m_STR0 |= (m_STR1 & ARB_REG); } -static void lt(tms32025_state *cpustate) +void tms32025_device::lt() { - GETDATA(cpustate, 0, 0); - cpustate->Treg = cpustate->ALU.w.l; + GETDATA(0, 0); + m_Treg = m_ALU.w.l; } -static void lta(tms32025_state *cpustate) +void tms32025_device::lta() { - cpustate->oldacc.d = cpustate->ACC.d; - GETDATA(cpustate, 0, 0); - cpustate->Treg = cpustate->ALU.w.l; - SHIFT_Preg_TO_ALU(cpustate); - cpustate->ACC.d += cpustate->ALU.d; - CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_ADD_CARRY(cpustate); + m_oldacc.d = m_ACC.d; + GETDATA(0, 0); + m_Treg = m_ALU.w.l; + SHIFT_Preg_TO_ALU(); + m_ACC.d += m_ALU.d; + CALCULATE_ADD_OVERFLOW(m_ALU.d); + CALCULATE_ADD_CARRY(); } -static void ltd(tms32025_state *cpustate) /** Careful with how memory is configured !! */ +void tms32025_device::ltd() /** Careful with how memory is configured !! */ { - cpustate->oldacc.d = cpustate->ACC.d; - GETDATA(cpustate, 0, 0); - cpustate->Treg = cpustate->ALU.w.l; - M_WRTRAM(cpustate, (cpustate->memaccess+1), cpustate->ALU.w.l); - SHIFT_Preg_TO_ALU(cpustate); - cpustate->ACC.d += cpustate->ALU.d; - CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_ADD_CARRY(cpustate); + m_oldacc.d = m_ACC.d; + GETDATA(0, 0); + m_Treg = m_ALU.w.l; + M_WRTRAM((m_memaccess+1), m_ALU.w.l); + SHIFT_Preg_TO_ALU(); + m_ACC.d += m_ALU.d; + CALCULATE_ADD_OVERFLOW(m_ALU.d); + CALCULATE_ADD_CARRY(); } -static void ltp(tms32025_state *cpustate) +void tms32025_device::ltp() { - cpustate->oldacc.d = cpustate->ACC.d; - GETDATA(cpustate, 0, 0); - cpustate->Treg = cpustate->ALU.w.l; - SHIFT_Preg_TO_ALU(cpustate); - cpustate->ACC.d = cpustate->ALU.d; -} -static void lts(tms32025_state *cpustate) -{ - cpustate->oldacc.d = cpustate->ACC.d; - GETDATA(cpustate, 0, 0); - cpustate->Treg = cpustate->ALU.w.l; - SHIFT_Preg_TO_ALU(cpustate); - cpustate->ACC.d -= cpustate->ALU.d; - CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_SUB_CARRY(cpustate); -} -static void mac(tms32025_state *cpustate) /** RAM blocks B0,B1,B2 may be important ! */ + m_oldacc.d = m_ACC.d; + GETDATA(0, 0); + m_Treg = m_ALU.w.l; + SHIFT_Preg_TO_ALU(); + m_ACC.d = m_ALU.d; +} +void tms32025_device::lts() +{ + m_oldacc.d = m_ACC.d; + GETDATA(0, 0); + m_Treg = m_ALU.w.l; + SHIFT_Preg_TO_ALU(); + m_ACC.d -= m_ALU.d; + CALCULATE_SUB_OVERFLOW(m_ALU.d); + CALCULATE_SUB_CARRY(); +} +void tms32025_device::mac() /** RAM blocks B0,B1,B2 may be important ! */ { /** Fix cycle timing **/ - cpustate->oldacc.d = cpustate->ACC.d; - if (cpustate->init_load_addr) { - cpustate->PFC = M_RDOP_ARG(cpustate->PC); - cpustate->PC++; + m_oldacc.d = m_ACC.d; + if (m_init_load_addr) { + m_PFC = M_RDOP_ARG(m_PC); + m_PC++; } - SHIFT_Preg_TO_ALU(cpustate); - cpustate->ACC.d += cpustate->ALU.d; - CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_ADD_CARRY(cpustate); - GETDATA(cpustate, 0, 0); - cpustate->Treg = cpustate->ALU.w.l; - cpustate->Preg.d = ( (INT16)cpustate->ALU.w.l * (INT16)M_RDROM(cpustate, cpustate->PFC) ); - cpustate->PFC++; - cpustate->tms32025_dec_cycles += (2*CLK); -} -static void macd(tms32025_state *cpustate) /** RAM blocks B0,B1,B2 may be important ! */ + SHIFT_Preg_TO_ALU(); + m_ACC.d += m_ALU.d; + CALCULATE_ADD_OVERFLOW(m_ALU.d); + CALCULATE_ADD_CARRY(); + GETDATA(0, 0); + m_Treg = m_ALU.w.l; + m_Preg.d = ( (INT16)m_ALU.w.l * (INT16)M_RDROM(m_PFC) ); + m_PFC++; + m_tms32025_dec_cycles += (2*CLK); +} +void tms32025_device::macd() /** RAM blocks B0,B1,B2 may be important ! */ { /** Fix cycle timing **/ - cpustate->oldacc.d = cpustate->ACC.d; - if (cpustate->init_load_addr) { - cpustate->PFC = M_RDOP_ARG(cpustate->PC); - cpustate->PC++; + m_oldacc.d = m_ACC.d; + if (m_init_load_addr) { + m_PFC = M_RDOP_ARG(m_PC); + m_PC++; } - SHIFT_Preg_TO_ALU(cpustate); - cpustate->ACC.d += cpustate->ALU.d; - CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_ADD_CARRY(cpustate); - GETDATA(cpustate, 0, 0); - if ( (cpustate->opcode.b.l & 0x80) || cpustate->init_load_addr ) { /* No writing during repitition, or DMA mode */ - M_WRTRAM(cpustate, (cpustate->memaccess+1), cpustate->ALU.w.l); + SHIFT_Preg_TO_ALU(); + m_ACC.d += m_ALU.d; + CALCULATE_ADD_OVERFLOW(m_ALU.d); + CALCULATE_ADD_CARRY(); + GETDATA(0, 0); + if ( (m_opcode.b.l & 0x80) || m_init_load_addr ) { /* No writing during repitition, or DMA mode */ + M_WRTRAM((m_memaccess+1), m_ALU.w.l); } - cpustate->Treg = cpustate->ALU.w.l; - cpustate->Preg.d = ( (INT16)cpustate->ALU.w.l * (INT16)M_RDROM(cpustate, cpustate->PFC) ); - cpustate->PFC++; - cpustate->tms32025_dec_cycles += (2*CLK); + m_Treg = m_ALU.w.l; + m_Preg.d = ( (INT16)m_ALU.w.l * (INT16)M_RDROM(m_PFC) ); + m_PFC++; + m_tms32025_dec_cycles += (2*CLK); } -static void mar(tms32025_state *cpustate) /* LARP and NOP are a subset of this instruction */ +void tms32025_device::mar() /* LARP and NOP are a subset of this instruction */ { - if (cpustate->opcode.b.l & 0x80) MODIFY_AR_ARP(cpustate); + if (m_opcode.b.l & 0x80) MODIFY_AR_ARP(); } -static void mpy(tms32025_state *cpustate) +void tms32025_device::mpy() { - GETDATA(cpustate, 0, 0); - cpustate->Preg.d = (INT16)(cpustate->ALU.w.l) * (INT16)(cpustate->Treg); + GETDATA(0, 0); + m_Preg.d = (INT16)(m_ALU.w.l) * (INT16)(m_Treg); } -static void mpya(tms32025_state *cpustate) +void tms32025_device::mpya() { - cpustate->oldacc.d = cpustate->ACC.d; - SHIFT_Preg_TO_ALU(cpustate); - cpustate->ACC.d += cpustate->ALU.d; - CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_ADD_CARRY(cpustate); - GETDATA(cpustate, 0, 0); - cpustate->Preg.d = (INT16)(cpustate->ALU.w.l) * (INT16)(cpustate->Treg); + m_oldacc.d = m_ACC.d; + SHIFT_Preg_TO_ALU(); + m_ACC.d += m_ALU.d; + CALCULATE_ADD_OVERFLOW(m_ALU.d); + CALCULATE_ADD_CARRY(); + GETDATA(0, 0); + m_Preg.d = (INT16)(m_ALU.w.l) * (INT16)(m_Treg); } -static void mpyk(tms32025_state *cpustate) +void tms32025_device::mpyk() { - cpustate->Preg.d = (INT16)cpustate->Treg * ((INT16)(cpustate->opcode.w.l << 3) >> 3); + m_Preg.d = (INT16)m_Treg * ((INT16)(m_opcode.w.l << 3) >> 3); } -static void mpys(tms32025_state *cpustate) +void tms32025_device::mpys() { - cpustate->oldacc.d = cpustate->ACC.d; - SHIFT_Preg_TO_ALU(cpustate); - cpustate->ACC.d -= cpustate->ALU.d; - CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_SUB_CARRY(cpustate); - GETDATA(cpustate, 0, 0); - cpustate->Preg.d = (INT16)(cpustate->ALU.w.l) * (INT16)(cpustate->Treg); + m_oldacc.d = m_ACC.d; + SHIFT_Preg_TO_ALU(); + m_ACC.d -= m_ALU.d; + CALCULATE_SUB_OVERFLOW(m_ALU.d); + CALCULATE_SUB_CARRY(); + GETDATA(0, 0); + m_Preg.d = (INT16)(m_ALU.w.l) * (INT16)(m_Treg); } -static void mpyu(tms32025_state *cpustate) +void tms32025_device::mpyu() { - GETDATA(cpustate, 0, 0); - cpustate->Preg.d = (UINT16)(cpustate->ALU.w.l) * (UINT16)(cpustate->Treg); + GETDATA(0, 0); + m_Preg.d = (UINT16)(m_ALU.w.l) * (UINT16)(m_Treg); } -static void neg(tms32025_state *cpustate) +void tms32025_device::neg() { - if (cpustate->ACC.d == 0x80000000) { - SET0(cpustate, OV_FLAG); - if (OVM) cpustate->ACC.d = 0x7fffffff; + if (m_ACC.d == 0x80000000) { + SET0(OV_FLAG); + if (OVM) m_ACC.d = 0x7fffffff; } - else cpustate->ACC.d = -cpustate->ACC.d; - if (cpustate->ACC.d) CLR0(cpustate, C_FLAG); - else SET0(cpustate, C_FLAG); + else m_ACC.d = -m_ACC.d; + if (m_ACC.d) CLR0(C_FLAG); + else SET0(C_FLAG); } /* -static void nop(tms32025_state *cpustate) { } // NOP is a subset of the MAR instruction +void tms32025_device::nop() { } // NOP is a subset of the MAR instruction */ -static void norm(tms32025_state *cpustate) +void tms32025_device::norm() { - if (cpustate->ACC.d !=0 && (INT32)(cpustate->ACC.d ^ (cpustate->ACC.d << 1)) >= 0) + if (m_ACC.d !=0 && (INT32)(m_ACC.d ^ (m_ACC.d << 1)) >= 0) { - CLR1(cpustate, TC_FLAG); - cpustate->ACC.d <<= 1; - MODIFY_AR_ARP(cpustate); + CLR1(TC_FLAG); + m_ACC.d <<= 1; + MODIFY_AR_ARP(); } - else SET1(cpustate, TC_FLAG); + else SET1(TC_FLAG); } -static void or_(tms32025_state *cpustate) +void tms32025_device::or_() { - GETDATA(cpustate, 0, 0); - cpustate->ACC.w.l |= cpustate->ALU.w.l; + GETDATA(0, 0); + m_ACC.w.l |= m_ALU.w.l; } -static void ork(tms32025_state *cpustate) +void tms32025_device::ork() { - cpustate->ALU.d = (UINT16)M_RDOP_ARG(cpustate->PC); - cpustate->PC++; - cpustate->ALU.d <<= (cpustate->opcode.b.h & 0xf); - cpustate->ACC.d |= (cpustate->ALU.d); + m_ALU.d = (UINT16)M_RDOP_ARG(m_PC); + m_PC++; + m_ALU.d <<= (m_opcode.b.h & 0xf); + m_ACC.d |= (m_ALU.d); } -static void out(tms32025_state *cpustate) +void tms32025_device::out() { - GETDATA(cpustate, 0, 0); - P_OUT( (cpustate->opcode.b.h & 0xf), cpustate->ALU.w.l ); + GETDATA(0, 0); + P_OUT( (m_opcode.b.h & 0xf), m_ALU.w.l ); } -static void pac(tms32025_state *cpustate) +void tms32025_device::pac() { - SHIFT_Preg_TO_ALU(cpustate); - cpustate->ACC.d = cpustate->ALU.d; + SHIFT_Preg_TO_ALU(); + m_ACC.d = m_ALU.d; } -static void pop(tms32025_state *cpustate) +void tms32025_device::pop() { - cpustate->ACC.d = (UINT16)POP_STACK(cpustate); + m_ACC.d = (UINT16)POP_STACK(); } -static void popd(tms32025_state *cpustate) +void tms32025_device::popd() { - cpustate->ALU.d = (UINT16)POP_STACK(cpustate); - PUTDATA(cpustate, cpustate->ALU.w.l); + m_ALU.d = (UINT16)POP_STACK(); + PUTDATA(m_ALU.w.l); } -static void pshd(tms32025_state *cpustate) +void tms32025_device::pshd() { - GETDATA(cpustate, 0, 0); - PUSH_STACK(cpustate, cpustate->ALU.w.l); + GETDATA(0, 0); + PUSH_STACK(m_ALU.w.l); } -static void push(tms32025_state *cpustate) +void tms32025_device::push() { - PUSH_STACK(cpustate, cpustate->ACC.w.l); + PUSH_STACK(m_ACC.w.l); } -static void rc(tms32025_state *cpustate) +void tms32025_device::rc() { - CLR1(cpustate, C_FLAG); + CLR1(C_FLAG); } -static void ret(tms32025_state *cpustate) +void tms32025_device::ret() { - SET_PC(POP_STACK(cpustate)); + SET_PC(POP_STACK()); } -static void rfsm(tms32025_state *cpustate) /** serial port mode */ +void tms32025_device::rfsm() /** serial port mode */ { - CLR1(cpustate, FSM_FLAG); + CLR1(FSM_FLAG); } -static void rhm(tms32025_state *cpustate) +void tms32025_device::rhm() { - CLR1(cpustate, HM_FLAG); + CLR1(HM_FLAG); } -static void rol(tms32025_state *cpustate) +void tms32025_device::rol() { - cpustate->ALU.d = cpustate->ACC.d; - cpustate->ACC.d <<= 1; - if (CARRY) cpustate->ACC.d |= 1; - if (cpustate->ALU.d & 0x80000000) SET1(cpustate, C_FLAG); - else CLR1(cpustate, C_FLAG); + m_ALU.d = m_ACC.d; + m_ACC.d <<= 1; + if (CARRY) m_ACC.d |= 1; + if (m_ALU.d & 0x80000000) SET1(C_FLAG); + else CLR1(C_FLAG); } -static void ror(tms32025_state *cpustate) +void tms32025_device::ror() { - cpustate->ALU.d = cpustate->ACC.d; - cpustate->ACC.d >>= 1; - if (CARRY) cpustate->ACC.d |= 0x80000000; - if (cpustate->ALU.d & 1) SET1(cpustate, C_FLAG); - else CLR1(cpustate, C_FLAG); + m_ALU.d = m_ACC.d; + m_ACC.d >>= 1; + if (CARRY) m_ACC.d |= 0x80000000; + if (m_ALU.d & 1) SET1(C_FLAG); + else CLR1(C_FLAG); } -static void rovm(tms32025_state *cpustate) +void tms32025_device::rovm() { - CLR0(cpustate, OVM_FLAG); + CLR0(OVM_FLAG); } -static void rpt(tms32025_state *cpustate) +void tms32025_device::rpt() { - GETDATA(cpustate, 0, 0); - cpustate->RPTC = cpustate->ALU.b.l; - cpustate->init_load_addr = 2; /* Initiate repeat mode */ + GETDATA(0, 0); + m_RPTC = m_ALU.b.l; + m_init_load_addr = 2; /* Initiate repeat mode */ } -static void rptk(tms32025_state *cpustate) +void tms32025_device::rptk() { - cpustate->RPTC = cpustate->opcode.b.l; - cpustate->init_load_addr = 2; /* Initiate repeat mode */ + m_RPTC = m_opcode.b.l; + m_init_load_addr = 2; /* Initiate repeat mode */ } -static void rsxm(tms32025_state *cpustate) +void tms32025_device::rsxm() { - CLR1(cpustate, SXM_FLAG); + CLR1(SXM_FLAG); } -static void rtc(tms32025_state *cpustate) +void tms32025_device::rtc() { - CLR1(cpustate, TC_FLAG); + CLR1(TC_FLAG); } -static void rtxm(tms32025_state *cpustate) /** Serial port stuff */ +void tms32025_device::rtxm() /** Serial port stuff */ { - CLR1(cpustate, TXM_FLAG); + CLR1(TXM_FLAG); } -static void rxf(tms32025_state *cpustate) +void tms32025_device::rxf() { - CLR1(cpustate, XF_FLAG); + CLR1(XF_FLAG); S_OUT(TMS32025_XF,CLEAR_LINE); } -static void sach(tms32025_state *cpustate) +void tms32025_device::sach() { - cpustate->ALU.d = (cpustate->ACC.d << (cpustate->opcode.b.h & 7)); - PUTDATA(cpustate, cpustate->ALU.w.h); + m_ALU.d = (m_ACC.d << (m_opcode.b.h & 7)); + PUTDATA(m_ALU.w.h); } -static void sacl(tms32025_state *cpustate) +void tms32025_device::sacl() { - cpustate->ALU.d = (cpustate->ACC.d << (cpustate->opcode.b.h & 7)); - PUTDATA(cpustate, cpustate->ALU.w.l); + m_ALU.d = (m_ACC.d << (m_opcode.b.h & 7)); + PUTDATA(m_ALU.w.l); } -static void sar_ar0(tms32025_state *cpustate) { PUTDATA(cpustate, cpustate->AR[0]); } -static void sar_ar1(tms32025_state *cpustate) { PUTDATA(cpustate, cpustate->AR[1]); } -static void sar_ar2(tms32025_state *cpustate) { PUTDATA(cpustate, cpustate->AR[2]); } -static void sar_ar3(tms32025_state *cpustate) { PUTDATA(cpustate, cpustate->AR[3]); } -static void sar_ar4(tms32025_state *cpustate) { PUTDATA(cpustate, cpustate->AR[4]); } -static void sar_ar5(tms32025_state *cpustate) { PUTDATA(cpustate, cpustate->AR[5]); } -static void sar_ar6(tms32025_state *cpustate) { PUTDATA(cpustate, cpustate->AR[6]); } -static void sar_ar7(tms32025_state *cpustate) { PUTDATA(cpustate, cpustate->AR[7]); } +void tms32025_device::sar_ar0() { PUTDATA(m_AR[0]); } +void tms32025_device::sar_ar1() { PUTDATA(m_AR[1]); } +void tms32025_device::sar_ar2() { PUTDATA(m_AR[2]); } +void tms32025_device::sar_ar3() { PUTDATA(m_AR[3]); } +void tms32025_device::sar_ar4() { PUTDATA(m_AR[4]); } +void tms32025_device::sar_ar5() { PUTDATA(m_AR[5]); } +void tms32025_device::sar_ar6() { PUTDATA(m_AR[6]); } +void tms32025_device::sar_ar7() { PUTDATA(m_AR[7]); } -static void sblk(tms32025_state *cpustate) +void tms32025_device::sblk() { - cpustate->oldacc.d = cpustate->ACC.d; - if (SXM) cpustate->ALU.d = (INT16)M_RDOP_ARG(cpustate->PC); - else cpustate->ALU.d = (UINT16)M_RDOP_ARG(cpustate->PC); - cpustate->PC++; - cpustate->ALU.d <<= (cpustate->opcode.b.h & 0xf); - cpustate->ACC.d -= cpustate->ALU.d; - CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_SUB_CARRY(cpustate); + m_oldacc.d = m_ACC.d; + if (SXM) m_ALU.d = (INT16)M_RDOP_ARG(m_PC); + else m_ALU.d = (UINT16)M_RDOP_ARG(m_PC); + m_PC++; + m_ALU.d <<= (m_opcode.b.h & 0xf); + m_ACC.d -= m_ALU.d; + CALCULATE_SUB_OVERFLOW(m_ALU.d); + CALCULATE_SUB_CARRY(); } -static void sbrk_ar(tms32025_state *cpustate) +void tms32025_device::sbrk_ar() { - cpustate->AR[ARP] -= cpustate->opcode.b.l; + m_AR[ARP] -= m_opcode.b.l; } -static void sc(tms32025_state *cpustate) +void tms32025_device::sc() { - SET1(cpustate, C_FLAG); + SET1(C_FLAG); } -static void sfl(tms32025_state *cpustate) +void tms32025_device::sfl() { - cpustate->ALU.d = cpustate->ACC.d; - cpustate->ACC.d <<= 1; - if (cpustate->ALU.d & 0x80000000) SET1(cpustate, C_FLAG); - else CLR1(cpustate, C_FLAG); + m_ALU.d = m_ACC.d; + m_ACC.d <<= 1; + if (m_ALU.d & 0x80000000) SET1(C_FLAG); + else CLR1(C_FLAG); } -static void sfr(tms32025_state *cpustate) +void tms32025_device::sfr() { - cpustate->ALU.d = cpustate->ACC.d; - cpustate->ACC.d >>= 1; + m_ALU.d = m_ACC.d; + m_ACC.d >>= 1; if (SXM) { - if (cpustate->ALU.d & 0x80000000) cpustate->ACC.d |= 0x80000000; + if (m_ALU.d & 0x80000000) m_ACC.d |= 0x80000000; } - if (cpustate->ALU.d & 1) SET1(cpustate, C_FLAG); - else CLR1(cpustate, C_FLAG); + if (m_ALU.d & 1) SET1(C_FLAG); + else CLR1(C_FLAG); } -static void sfsm(tms32025_state *cpustate) /** Serial port mode */ +void tms32025_device::sfsm() /** Serial port mode */ { - SET1(cpustate, FSM_FLAG); + SET1(FSM_FLAG); } -static void shm(tms32025_state *cpustate) +void tms32025_device::shm() { - SET1(cpustate, HM_FLAG); + SET1(HM_FLAG); } -static void sovm(tms32025_state *cpustate) +void tms32025_device::sovm() { - SET0(cpustate, OVM_FLAG); + SET0(OVM_FLAG); } -static void spac(tms32025_state *cpustate) +void tms32025_device::spac() { - cpustate->oldacc.d = cpustate->ACC.d; - SHIFT_Preg_TO_ALU(cpustate); - cpustate->ACC.d -= cpustate->ALU.d; - CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_SUB_CARRY(cpustate); + m_oldacc.d = m_ACC.d; + SHIFT_Preg_TO_ALU(); + m_ACC.d -= m_ALU.d; + CALCULATE_SUB_OVERFLOW(m_ALU.d); + CALCULATE_SUB_CARRY(); } -static void sph(tms32025_state *cpustate) +void tms32025_device::sph() { - SHIFT_Preg_TO_ALU(cpustate); - PUTDATA(cpustate, cpustate->ALU.w.h); + SHIFT_Preg_TO_ALU(); + PUTDATA(m_ALU.w.h); } -static void spl(tms32025_state *cpustate) +void tms32025_device::spl() { - SHIFT_Preg_TO_ALU(cpustate); - PUTDATA(cpustate, cpustate->ALU.w.l); + SHIFT_Preg_TO_ALU(); + PUTDATA(m_ALU.w.l); } -static void spm(tms32025_state *cpustate) +void tms32025_device::spm() { - MODIFY_PM(cpustate, (cpustate->opcode.b.l & 3) ); + MODIFY_PM((m_opcode.b.l & 3) ); } -static void sqra(tms32025_state *cpustate) +void tms32025_device::sqra() { - cpustate->oldacc.d = cpustate->ACC.d; - SHIFT_Preg_TO_ALU(cpustate); - cpustate->ACC.d += cpustate->ALU.d; - CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_ADD_CARRY(cpustate); - GETDATA(cpustate, 0, 0); - cpustate->Treg = cpustate->ALU.w.l; - cpustate->Preg.d = ((INT16)cpustate->ALU.w.l * (INT16)cpustate->ALU.w.l); + m_oldacc.d = m_ACC.d; + SHIFT_Preg_TO_ALU(); + m_ACC.d += m_ALU.d; + CALCULATE_ADD_OVERFLOW(m_ALU.d); + CALCULATE_ADD_CARRY(); + GETDATA(0, 0); + m_Treg = m_ALU.w.l; + m_Preg.d = ((INT16)m_ALU.w.l * (INT16)m_ALU.w.l); } -static void sqrs(tms32025_state *cpustate) +void tms32025_device::sqrs() { - cpustate->oldacc.d = cpustate->ACC.d; - SHIFT_Preg_TO_ALU(cpustate); - cpustate->ACC.d -= cpustate->ALU.d; - CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_SUB_CARRY(cpustate); - GETDATA(cpustate, 0, 0); - cpustate->Treg = cpustate->ALU.w.l; - cpustate->Preg.d = ((INT16)cpustate->ALU.w.l * (INT16)cpustate->ALU.w.l); + m_oldacc.d = m_ACC.d; + SHIFT_Preg_TO_ALU(); + m_ACC.d -= m_ALU.d; + CALCULATE_SUB_OVERFLOW(m_ALU.d); + CALCULATE_SUB_CARRY(); + GETDATA(0, 0); + m_Treg = m_ALU.w.l; + m_Preg.d = ((INT16)m_ALU.w.l * (INT16)m_ALU.w.l); } -static void sst(tms32025_state *cpustate) +void tms32025_device::sst() { - PUTDATA_SST(cpustate, cpustate->STR0); + PUTDATA_SST(m_STR0); } -static void sst1(tms32025_state *cpustate) +void tms32025_device::sst1() { - PUTDATA_SST(cpustate, cpustate->STR1); + PUTDATA_SST(m_STR1); } -static void ssxm(tms32025_state *cpustate) +void tms32025_device::ssxm() { - SET1(cpustate, SXM_FLAG); + SET1(SXM_FLAG); } -static void stc(tms32025_state *cpustate) +void tms32025_device::stc() { - SET1(cpustate, TC_FLAG); + SET1(TC_FLAG); } -static void stxm(tms32025_state *cpustate) /** Serial port stuff */ +void tms32025_device::stxm() /** Serial port stuff */ { - SET1(cpustate, TXM_FLAG); + SET1(TXM_FLAG); } -static void sub(tms32025_state *cpustate) +void tms32025_device::sub() { - cpustate->oldacc.d = cpustate->ACC.d; - GETDATA(cpustate, (cpustate->opcode.b.h & 0xf), SXM); - cpustate->ACC.d -= cpustate->ALU.d; - CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_SUB_CARRY(cpustate); + m_oldacc.d = m_ACC.d; + GETDATA((m_opcode.b.h & 0xf), SXM); + m_ACC.d -= m_ALU.d; + CALCULATE_SUB_OVERFLOW(m_ALU.d); + CALCULATE_SUB_CARRY(); } -static void subb(tms32025_state *cpustate) +void tms32025_device::subb() { - cpustate->oldacc.d = cpustate->ACC.d; - GETDATA(cpustate, 0, 0); - if (CARRY == 0) cpustate->ACC.d--; - cpustate->ACC.d -= cpustate->ALU.d; - CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d); - if (cpustate->ACC.d == cpustate->oldacc.d) {} /* edge case, carry remains same */ - else CALCULATE_SUB_CARRY(cpustate); + m_oldacc.d = m_ACC.d; + GETDATA(0, 0); + if (CARRY == 0) m_ACC.d--; + m_ACC.d -= m_ALU.d; + CALCULATE_SUB_OVERFLOW(m_ALU.d); + if (m_ACC.d == m_oldacc.d) {} /* edge case, carry remains same */ + else CALCULATE_SUB_CARRY(); } -static void subc(tms32025_state *cpustate) +void tms32025_device::subc() { - cpustate->oldacc.d = cpustate->ACC.d; - GETDATA(cpustate, 15, SXM); - cpustate->ACC.d -= cpustate->ALU.d; /* Temporary switch to ACC. Actual calculation is done as (ACC)-[mem] -> ALU, will be preserved later on. */ - if ((INT32)((cpustate->oldacc.d ^ cpustate->ALU.d) & (cpustate->oldacc.d ^ cpustate->ACC.d)) < 0) { - SET0(cpustate, OV_FLAG); /* Not affected by OVM */ + m_oldacc.d = m_ACC.d; + GETDATA(15, SXM); + m_ACC.d -= m_ALU.d; /* Temporary switch to ACC. Actual calculation is done as (ACC)-[mem] -> ALU, will be preserved later on. */ + if ((INT32)((m_oldacc.d ^ m_ALU.d) & (m_oldacc.d ^ m_ACC.d)) < 0) { + SET0(OV_FLAG); /* Not affected by OVM */ } - CALCULATE_SUB_CARRY(cpustate); - if( cpustate->oldacc.d >= cpustate->ALU.d ) { - cpustate->ALU.d = cpustate->ACC.d; - cpustate->ACC.d = cpustate->ACC.d << 1 | 1; + CALCULATE_SUB_CARRY(); + if( m_oldacc.d >= m_ALU.d ) { + m_ALU.d = m_ACC.d; + m_ACC.d = m_ACC.d << 1 | 1; } else { - cpustate->ALU.d = cpustate->ACC.d; - cpustate->ACC.d = cpustate->oldacc.d << 1; + m_ALU.d = m_ACC.d; + m_ACC.d = m_oldacc.d << 1; } } -static void subh(tms32025_state *cpustate) +void tms32025_device::subh() { - cpustate->oldacc.d = cpustate->ACC.d; - GETDATA(cpustate, 0, 0); - cpustate->ACC.w.h -= cpustate->ALU.w.l; - if ( (UINT16)(cpustate->oldacc.w.h) < (UINT16)(cpustate->ACC.w.h) ) { - CLR1(cpustate, C_FLAG); /* Carry flag is not affected, if no borrow occurred */ + m_oldacc.d = m_ACC.d; + GETDATA(0, 0); + m_ACC.w.h -= m_ALU.w.l; + if ( (UINT16)(m_oldacc.w.h) < (UINT16)(m_ACC.w.h) ) { + CLR1(C_FLAG); /* Carry flag is not affected, if no borrow occurred */ } - if ((INT16)((cpustate->oldacc.w.h ^ cpustate->ALU.w.l) & (cpustate->oldacc.w.h ^ cpustate->ACC.w.h)) < 0) { - SET0(cpustate, OV_FLAG); - if (OVM) cpustate->ACC.w.h = ((INT16)cpustate->oldacc.w.h < 0) ? 0x8000 : 0x7fff; + if ((INT16)((m_oldacc.w.h ^ m_ALU.w.l) & (m_oldacc.w.h ^ m_ACC.w.h)) < 0) { + SET0(OV_FLAG); + if (OVM) m_ACC.w.h = ((INT16)m_oldacc.w.h < 0) ? 0x8000 : 0x7fff; } } -static void subk(tms32025_state *cpustate) +void tms32025_device::subk() { - cpustate->oldacc.d = cpustate->ACC.d; - cpustate->ALU.d = (UINT8)cpustate->opcode.b.l; - cpustate->ACC.d -= cpustate->ALU.b.l; - CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_SUB_CARRY(cpustate); + m_oldacc.d = m_ACC.d; + m_ALU.d = (UINT8)m_opcode.b.l; + m_ACC.d -= m_ALU.b.l; + CALCULATE_SUB_OVERFLOW(m_ALU.d); + CALCULATE_SUB_CARRY(); } -static void subs(tms32025_state *cpustate) +void tms32025_device::subs() { - cpustate->oldacc.d = cpustate->ACC.d; - GETDATA(cpustate, 0, 0); - cpustate->ACC.d -= cpustate->ALU.w.l; - CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_SUB_CARRY(cpustate); + m_oldacc.d = m_ACC.d; + GETDATA(0, 0); + m_ACC.d -= m_ALU.w.l; + CALCULATE_SUB_OVERFLOW(m_ALU.d); + CALCULATE_SUB_CARRY(); } -static void subt(tms32025_state *cpustate) +void tms32025_device::subt() { - cpustate->oldacc.d = cpustate->ACC.d; - GETDATA(cpustate, (cpustate->Treg & 0xf), SXM); - cpustate->ACC.d -= cpustate->ALU.d; - CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d); - CALCULATE_SUB_CARRY(cpustate); + m_oldacc.d = m_ACC.d; + GETDATA((m_Treg & 0xf), SXM); + m_ACC.d -= m_ALU.d; + CALCULATE_SUB_OVERFLOW(m_ALU.d); + CALCULATE_SUB_CARRY(); } -static void sxf(tms32025_state *cpustate) +void tms32025_device::sxf() { - SET1(cpustate, XF_FLAG); + SET1(XF_FLAG); S_OUT(TMS32025_XF,ASSERT_LINE); } -static void tblr(tms32025_state *cpustate) +void tms32025_device::tblr() { - if (cpustate->init_load_addr) { - cpustate->PFC = cpustate->ACC.w.l; + if (m_init_load_addr) { + m_PFC = m_ACC.w.l; } - cpustate->ALU.w.l = M_RDROM(cpustate, cpustate->PFC); - if ( (CNF0) && ( (UINT16)(cpustate->PFC) >= 0xff00 ) ) {} /** TMS32025 only */ - else cpustate->tms32025_dec_cycles += (1*CLK); - PUTDATA(cpustate, cpustate->ALU.w.l); - cpustate->PFC++; + m_ALU.w.l = M_RDROM(m_PFC); + if ( (CNF0) && ( (UINT16)(m_PFC) >= 0xff00 ) ) {} /** TMS32025 only */ + else m_tms32025_dec_cycles += (1*CLK); + PUTDATA(m_ALU.w.l); + m_PFC++; } -static void tblw(tms32025_state *cpustate) +void tms32025_device::tblw() { - if (cpustate->init_load_addr) { - cpustate->PFC = cpustate->ACC.w.l; + if (m_init_load_addr) { + m_PFC = m_ACC.w.l; } - cpustate->tms32025_dec_cycles += (1*CLK); - GETDATA(cpustate, 0, 0); - if (cpustate->external_mem_access) cpustate->tms32025_dec_cycles += (1*CLK); - M_WRTROM(cpustate, cpustate->PFC, cpustate->ALU.w.l); - cpustate->PFC++; + m_tms32025_dec_cycles += (1*CLK); + GETDATA(0, 0); + if (m_external_mem_access) m_tms32025_dec_cycles += (1*CLK); + M_WRTROM(m_PFC, m_ALU.w.l); + m_PFC++; } -static void trap(tms32025_state *cpustate) +void tms32025_device::trap() { - PUSH_STACK(cpustate, cpustate->PC); + PUSH_STACK(m_PC); SET_PC(0x001E); /* Trap vector */ } -static void xor_(tms32025_state *cpustate) +void tms32025_device::xor_() { - GETDATA(cpustate, 0, 0); - cpustate->ACC.w.l ^= cpustate->ALU.w.l; + GETDATA(0, 0); + m_ACC.w.l ^= m_ALU.w.l; } -static void xork(tms32025_state *cpustate) +void tms32025_device::xork() { - cpustate->ALU.d = M_RDOP_ARG(cpustate->PC); - cpustate->PC++; - cpustate->ALU.d <<= (cpustate->opcode.b.h & 0xf); - cpustate->ACC.d ^= cpustate->ALU.d; + m_ALU.d = M_RDOP_ARG(m_PC); + m_PC++; + m_ALU.d <<= (m_opcode.b.h & 0xf); + m_ACC.d ^= m_ALU.d; } -static void zalh(tms32025_state *cpustate) +void tms32025_device::zalh() { - GETDATA(cpustate, 0, 0); - cpustate->ACC.w.h = cpustate->ALU.w.l; - cpustate->ACC.w.l = 0x0000; + GETDATA(0, 0); + m_ACC.w.h = m_ALU.w.l; + m_ACC.w.l = 0x0000; } -static void zalr(tms32025_state *cpustate) +void tms32025_device::zalr() { - GETDATA(cpustate, 0, 0); - cpustate->ACC.w.h = cpustate->ALU.w.l; - cpustate->ACC.w.l = 0x8000; + GETDATA(0, 0); + m_ACC.w.h = m_ALU.w.l; + m_ACC.w.l = 0x8000; } -static void zals(tms32025_state *cpustate) +void tms32025_device::zals() { - GETDATA(cpustate, 0, 0); - cpustate->ACC.w.l = cpustate->ALU.w.l; - cpustate->ACC.w.h = 0x0000; + GETDATA(0, 0); + m_ACC.w.l = m_ALU.w.l; + m_ACC.w.h = 0x0000; } @@ -1587,81 +1548,81 @@ static void zals(tms32025_state *cpustate) * Opcode Table (Cycles, Instruction) ***********************************************************************/ -static const tms32025_opcode opcode_main[256]= -{ -/*00*/ {1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add }, -/*08*/ {1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add }, -/*10*/ {1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub }, -/*18*/ {1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub }, -/*20*/ {1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac }, -/*28*/ {1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac }, -/*30*/ {1*CLK, lar_ar0 },{1*CLK, lar_ar1 },{1*CLK, lar_ar2 },{1*CLK, lar_ar3 },{1*CLK, lar_ar4 },{1*CLK, lar_ar5 },{1*CLK, lar_ar6 },{1*CLK, lar_ar7 }, -/*38*/ {1*CLK, mpy },{1*CLK, sqra },{1*CLK, mpya },{1*CLK, mpys },{1*CLK, lt },{1*CLK, lta },{1*CLK, ltp },{1*CLK, ltd }, -/*40*/ {1*CLK, zalh },{1*CLK, zals },{1*CLK, lact },{1*CLK, addc },{1*CLK, subh },{1*CLK, subs },{1*CLK, subt },{1*CLK, subc }, -/*48*/ {1*CLK, addh },{1*CLK, adds },{1*CLK, addt },{1*CLK, rpt },{1*CLK, xor_ },{1*CLK, or_ },{1*CLK, and_ },{1*CLK, subb }, -/*50*/ {1*CLK, lst },{1*CLK, lst1 },{1*CLK, ldp },{1*CLK, lph },{1*CLK, pshd },{1*CLK, mar },{1*CLK, dmov },{1*CLK, bitt }, -/*58*/ {3*CLK, tblr },{2*CLK, tblw },{1*CLK, sqrs },{1*CLK, lts },{2*CLK, macd },{2*CLK, mac },{2*CLK, bc },{2*CLK, bnc }, -/*60*/ {1*CLK, sacl },{1*CLK, sacl },{1*CLK, sacl },{1*CLK, sacl },{1*CLK, sacl },{1*CLK, sacl },{1*CLK, sacl },{1*CLK, sacl }, -/*68*/ {1*CLK, sach },{1*CLK, sach },{1*CLK, sach },{1*CLK, sach },{1*CLK, sach },{1*CLK, sach },{1*CLK, sach },{1*CLK, sach }, -/*70*/ {1*CLK, sar_ar0 },{1*CLK, sar_ar1 },{1*CLK, sar_ar2 },{1*CLK, sar_ar3 },{1*CLK, sar_ar4 },{1*CLK, sar_ar5 },{1*CLK, sar_ar6 },{1*CLK, sar_ar7 }, -/*78*/ {1*CLK, sst },{1*CLK, sst1 },{1*CLK, popd },{1*CLK, zalr },{1*CLK, spl },{1*CLK, sph },{1*CLK, adrk },{1*CLK, sbrk_ar }, -/*80*/ {2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in }, -/*88*/ {2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in }, -/*90*/ {1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit }, -/*98*/ {1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit }, -/*A0*/ {1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk }, -/*A8*/ {1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk }, -/*B0*/ {1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk }, -/*B8*/ {1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk }, -/*C0*/ {1*CLK, lark_ar0 },{1*CLK, lark_ar1 },{1*CLK, lark_ar2 },{1*CLK, lark_ar3 },{1*CLK, lark_ar4 },{1*CLK, lark_ar5 },{1*CLK, lark_ar6 },{1*CLK, lark_ar7 }, -/*C8*/ {1*CLK, ldpk },{1*CLK, ldpk },{1*CLK, lack },{1*CLK, rptk },{1*CLK, addk },{1*CLK, subk },{1*CLK, opcodes_CE},{1*CLK, mpyu }, -/*D0*/ {1*CLK,opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{0*CLK, opcodes_Dx}, -/*D8*/ {1*CLK,opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx}, -/*E0*/ {2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out }, -/*E8*/ {2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out }, -/*F0*/ {2*CLK, bv },{2*CLK, bgz },{2*CLK, blez },{2*CLK, blz },{2*CLK, bgez },{2*CLK, bnz },{2*CLK, bz },{2*CLK, bnv }, -/*F8*/ {2*CLK, bbz },{2*CLK, bbnz },{2*CLK, bioz },{2*CLK, banz },{2*CLK, blkp },{2*CLK, blkd },{2*CLK, call },{2*CLK, br } +const tms32025_device::tms32025_opcode tms32025_device::s_opcode_main[256]= +{ +/*00*/ {1*CLK, &tms32025_device::add },{1*CLK, &tms32025_device::add },{1*CLK, &tms32025_device::add },{1*CLK, &tms32025_device::add },{1*CLK, &tms32025_device::add },{1*CLK, &tms32025_device::add },{1*CLK, &tms32025_device::add },{1*CLK, &tms32025_device::add }, +/*08*/ {1*CLK, &tms32025_device::add },{1*CLK, &tms32025_device::add },{1*CLK, &tms32025_device::add },{1*CLK, &tms32025_device::add },{1*CLK, &tms32025_device::add },{1*CLK, &tms32025_device::add },{1*CLK, &tms32025_device::add },{1*CLK, &tms32025_device::add }, +/*10*/ {1*CLK, &tms32025_device::sub },{1*CLK, &tms32025_device::sub },{1*CLK, &tms32025_device::sub },{1*CLK, &tms32025_device::sub },{1*CLK, &tms32025_device::sub },{1*CLK, &tms32025_device::sub },{1*CLK, &tms32025_device::sub },{1*CLK, &tms32025_device::sub }, +/*18*/ {1*CLK, &tms32025_device::sub },{1*CLK, &tms32025_device::sub },{1*CLK, &tms32025_device::sub },{1*CLK, &tms32025_device::sub },{1*CLK, &tms32025_device::sub },{1*CLK, &tms32025_device::sub },{1*CLK, &tms32025_device::sub },{1*CLK, &tms32025_device::sub }, +/*20*/ {1*CLK, &tms32025_device::lac },{1*CLK, &tms32025_device::lac },{1*CLK, &tms32025_device::lac },{1*CLK, &tms32025_device::lac },{1*CLK, &tms32025_device::lac },{1*CLK, &tms32025_device::lac },{1*CLK, &tms32025_device::lac },{1*CLK, &tms32025_device::lac }, +/*28*/ {1*CLK, &tms32025_device::lac },{1*CLK, &tms32025_device::lac },{1*CLK, &tms32025_device::lac },{1*CLK, &tms32025_device::lac },{1*CLK, &tms32025_device::lac },{1*CLK, &tms32025_device::lac },{1*CLK, &tms32025_device::lac },{1*CLK, &tms32025_device::lac }, +/*30*/ {1*CLK, &tms32025_device::lar_ar0 },{1*CLK, &tms32025_device::lar_ar1 },{1*CLK, &tms32025_device::lar_ar2 },{1*CLK, &tms32025_device::lar_ar3 },{1*CLK, &tms32025_device::lar_ar4 },{1*CLK, &tms32025_device::lar_ar5 },{1*CLK, &tms32025_device::lar_ar6 },{1*CLK, &tms32025_device::lar_ar7 }, +/*38*/ {1*CLK, &tms32025_device::mpy },{1*CLK, &tms32025_device::sqra },{1*CLK, &tms32025_device::mpya },{1*CLK, &tms32025_device::mpys },{1*CLK, &tms32025_device::lt },{1*CLK, &tms32025_device::lta },{1*CLK, &tms32025_device::ltp },{1*CLK, &tms32025_device::ltd }, +/*40*/ {1*CLK, &tms32025_device::zalh },{1*CLK, &tms32025_device::zals },{1*CLK, &tms32025_device::lact },{1*CLK, &tms32025_device::addc },{1*CLK, &tms32025_device::subh },{1*CLK, &tms32025_device::subs },{1*CLK, &tms32025_device::subt },{1*CLK, &tms32025_device::subc }, +/*48*/ {1*CLK, &tms32025_device::addh },{1*CLK, &tms32025_device::adds },{1*CLK, &tms32025_device::addt },{1*CLK, &tms32025_device::rpt },{1*CLK, &tms32025_device::xor_ },{1*CLK, &tms32025_device::or_ },{1*CLK, &tms32025_device::and_ },{1*CLK, &tms32025_device::subb }, +/*50*/ {1*CLK, &tms32025_device::lst },{1*CLK, &tms32025_device::lst1 },{1*CLK, &tms32025_device::ldp },{1*CLK, &tms32025_device::lph },{1*CLK, &tms32025_device::pshd },{1*CLK, &tms32025_device::mar },{1*CLK, &tms32025_device::dmov },{1*CLK, &tms32025_device::bitt }, +/*58*/ {3*CLK, &tms32025_device::tblr },{2*CLK, &tms32025_device::tblw },{1*CLK, &tms32025_device::sqrs },{1*CLK, &tms32025_device::lts },{2*CLK, &tms32025_device::macd },{2*CLK, &tms32025_device::mac },{2*CLK, &tms32025_device::bc },{2*CLK, &tms32025_device::bnc }, +/*60*/ {1*CLK, &tms32025_device::sacl },{1*CLK, &tms32025_device::sacl },{1*CLK, &tms32025_device::sacl },{1*CLK, &tms32025_device::sacl },{1*CLK, &tms32025_device::sacl },{1*CLK, &tms32025_device::sacl },{1*CLK, &tms32025_device::sacl },{1*CLK, &tms32025_device::sacl }, +/*68*/ {1*CLK, &tms32025_device::sach },{1*CLK, &tms32025_device::sach },{1*CLK, &tms32025_device::sach },{1*CLK, &tms32025_device::sach },{1*CLK, &tms32025_device::sach },{1*CLK, &tms32025_device::sach },{1*CLK, &tms32025_device::sach },{1*CLK, &tms32025_device::sach }, +/*70*/ {1*CLK, &tms32025_device::sar_ar0 },{1*CLK, &tms32025_device::sar_ar1 },{1*CLK, &tms32025_device::sar_ar2 },{1*CLK, &tms32025_device::sar_ar3 },{1*CLK, &tms32025_device::sar_ar4 },{1*CLK, &tms32025_device::sar_ar5 },{1*CLK, &tms32025_device::sar_ar6 },{1*CLK, &tms32025_device::sar_ar7 }, +/*78*/ {1*CLK, &tms32025_device::sst },{1*CLK, &tms32025_device::sst1 },{1*CLK, &tms32025_device::popd },{1*CLK, &tms32025_device::zalr },{1*CLK, &tms32025_device::spl },{1*CLK, &tms32025_device::sph },{1*CLK, &tms32025_device::adrk },{1*CLK, &tms32025_device::sbrk_ar }, +/*80*/ {2*CLK, &tms32025_device::in },{2*CLK, &tms32025_device::in },{2*CLK, &tms32025_device::in },{2*CLK, &tms32025_device::in },{2*CLK, &tms32025_device::in },{2*CLK, &tms32025_device::in },{2*CLK, &tms32025_device::in },{2*CLK, &tms32025_device::in }, +/*88*/ {2*CLK, &tms32025_device::in },{2*CLK, &tms32025_device::in },{2*CLK, &tms32025_device::in },{2*CLK, &tms32025_device::in },{2*CLK, &tms32025_device::in },{2*CLK, &tms32025_device::in },{2*CLK, &tms32025_device::in },{2*CLK, &tms32025_device::in }, +/*90*/ {1*CLK, &tms32025_device::bit },{1*CLK, &tms32025_device::bit },{1*CLK, &tms32025_device::bit },{1*CLK, &tms32025_device::bit },{1*CLK, &tms32025_device::bit },{1*CLK, &tms32025_device::bit },{1*CLK, &tms32025_device::bit },{1*CLK, &tms32025_device::bit }, +/*98*/ {1*CLK, &tms32025_device::bit },{1*CLK, &tms32025_device::bit },{1*CLK, &tms32025_device::bit },{1*CLK, &tms32025_device::bit },{1*CLK, &tms32025_device::bit },{1*CLK, &tms32025_device::bit },{1*CLK, &tms32025_device::bit },{1*CLK, &tms32025_device::bit }, +/*A0*/ {1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk }, +/*A8*/ {1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk }, +/*B0*/ {1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk }, +/*B8*/ {1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk },{1*CLK, &tms32025_device::mpyk }, +/*C0*/ {1*CLK, &tms32025_device::lark_ar0 },{1*CLK, &tms32025_device::lark_ar1 },{1*CLK, &tms32025_device::lark_ar2 },{1*CLK, &tms32025_device::lark_ar3 },{1*CLK, &tms32025_device::lark_ar4 },{1*CLK, &tms32025_device::lark_ar5 },{1*CLK, &tms32025_device::lark_ar6 },{1*CLK, &tms32025_device::lark_ar7 }, +/*C8*/ {1*CLK, &tms32025_device::ldpk },{1*CLK, &tms32025_device::ldpk },{1*CLK, &tms32025_device::lack },{1*CLK, &tms32025_device::rptk },{1*CLK, &tms32025_device::addk },{1*CLK, &tms32025_device::subk },{1*CLK, &tms32025_device::opcodes_CE},{1*CLK, &tms32025_device::mpyu }, +/*D0*/ {1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{0*CLK, &tms32025_device::opcodes_Dx}, +/*D8*/ {1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx},{1*CLK, &tms32025_device::opcodes_Dx}, +/*E0*/ {2*CLK, &tms32025_device::out },{2*CLK, &tms32025_device::out },{2*CLK, &tms32025_device::out },{2*CLK, &tms32025_device::out },{2*CLK, &tms32025_device::out },{2*CLK, &tms32025_device::out },{2*CLK, &tms32025_device::out },{2*CLK, &tms32025_device::out }, +/*E8*/ {2*CLK, &tms32025_device::out },{2*CLK, &tms32025_device::out },{2*CLK, &tms32025_device::out },{2*CLK, &tms32025_device::out },{2*CLK, &tms32025_device::out },{2*CLK, &tms32025_device::out },{2*CLK, &tms32025_device::out },{2*CLK, &tms32025_device::out }, +/*F0*/ {2*CLK, &tms32025_device::bv },{2*CLK, &tms32025_device::bgz },{2*CLK, &tms32025_device::blez },{2*CLK, &tms32025_device::blz },{2*CLK, &tms32025_device::bgez },{2*CLK, &tms32025_device::bnz },{2*CLK, &tms32025_device::bz },{2*CLK, &tms32025_device::bnv }, +/*F8*/ {2*CLK, &tms32025_device::bbz },{2*CLK, &tms32025_device::bbnz },{2*CLK, &tms32025_device::bioz },{2*CLK, &tms32025_device::banz },{2*CLK, &tms32025_device::blkp },{2*CLK, &tms32025_device::blkd },{2*CLK, &tms32025_device::call },{2*CLK, &tms32025_device::br } }; -static const tms32025_opcode_CE opcode_CE_subset[256]= /* Instructions living under the CExx opcode */ -{ -/*00*/ {1*CLK, eint },{1*CLK, dint },{1*CLK, rovm },{1*CLK, sovm },{1*CLK, cnfd },{1*CLK, cnfp },{1*CLK, rsxm },{1*CLK, ssxm }, -/*08*/ {1*CLK, spm },{1*CLK, spm },{1*CLK, spm },{1*CLK, spm },{1*CLK, rxf },{1*CLK, sxf },{1*CLK, fort },{1*CLK, fort }, -/*10*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{1*CLK, pac },{1*CLK, apac },{1*CLK, spac },{0*CLK, illegal }, -/*18*/ {1*CLK, sfl },{1*CLK, sfr },{0*CLK, illegal },{1*CLK, abst },{1*CLK, push },{1*CLK, pop },{2*CLK, trap },{3*CLK, idle }, -/*20*/ {1*CLK, rtxm },{1*CLK, stxm },{0*CLK, illegal },{1*CLK, neg },{2*CLK, cala },{2*CLK, bacc },{2*CLK, ret },{1*CLK, cmpl }, -/*28*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*30*/ {1*CLK, rc },{1*CLK, sc },{1*CLK, rtc },{1*CLK, stc },{1*CLK, rol },{1*CLK, ror },{1*CLK, rfsm },{1*CLK, sfsm }, -/*38*/ {1*CLK, rhm },{1*CLK, shm },{0*CLK, illegal },{0*CLK, illegal },{1*CLK, conf },{1*CLK, conf },{1*CLK, conf },{1*CLK, conf }, -/*40*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*48*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*50*/ {1*CLK, cmpr },{1*CLK, cmpr },{1*CLK, cmpr },{1*CLK, cmpr },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*58*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*60*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*68*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*70*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*78*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*80*/ {0*CLK, illegal },{0*CLK, illegal },{1*CLK, norm },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*88*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*90*/ {0*CLK, illegal },{0*CLK, illegal },{1*CLK, norm },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*98*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*A0*/ {0*CLK, illegal },{0*CLK, illegal },{1*CLK, norm },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*A8*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*B0*/ {0*CLK, illegal },{0*CLK, illegal },{1*CLK, norm },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*B8*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*C0*/ {0*CLK, illegal },{0*CLK, illegal },{1*CLK, norm },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*C8*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*D0*/ {0*CLK, illegal },{0*CLK, illegal },{1*CLK, norm },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*D8*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*E0*/ {0*CLK, illegal },{0*CLK, illegal },{1*CLK, norm },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*E8*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*F0*/ {0*CLK, illegal },{0*CLK, illegal },{1*CLK, norm },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }, -/*F8*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal } +const tms32025_device::tms32025_opcode tms32025_device::s_opcode_CE_subset[256]= /* Instructions living under the CExx opcode */ +{ +/*00*/ {1*CLK, &tms32025_device::eint },{1*CLK, &tms32025_device::dint },{1*CLK, &tms32025_device::rovm },{1*CLK, &tms32025_device::sovm },{1*CLK, &tms32025_device::cnfd },{1*CLK, &tms32025_device::cnfp },{1*CLK, &tms32025_device::rsxm },{1*CLK, &tms32025_device::ssxm }, +/*08*/ {1*CLK, &tms32025_device::spm },{1*CLK, &tms32025_device::spm },{1*CLK, &tms32025_device::spm },{1*CLK, &tms32025_device::spm },{1*CLK, &tms32025_device::rxf },{1*CLK, &tms32025_device::sxf },{1*CLK, &tms32025_device::fort },{1*CLK, &tms32025_device::fort }, +/*10*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{1*CLK, &tms32025_device::pac },{1*CLK, &tms32025_device::apac },{1*CLK, &tms32025_device::spac },{0*CLK, &tms32025_device::illegal }, +/*18*/ {1*CLK, &tms32025_device::sfl },{1*CLK, &tms32025_device::sfr },{0*CLK, &tms32025_device::illegal },{1*CLK, &tms32025_device::abst },{1*CLK, &tms32025_device::push },{1*CLK, &tms32025_device::pop },{2*CLK, &tms32025_device::trap },{3*CLK, &tms32025_device::idle }, +/*20*/ {1*CLK, &tms32025_device::rtxm },{1*CLK, &tms32025_device::stxm },{0*CLK, &tms32025_device::illegal },{1*CLK, &tms32025_device::neg },{2*CLK, &tms32025_device::cala },{2*CLK, &tms32025_device::bacc },{2*CLK, &tms32025_device::ret },{1*CLK, &tms32025_device::cmpl }, +/*28*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*30*/ {1*CLK, &tms32025_device::rc },{1*CLK, &tms32025_device::sc },{1*CLK, &tms32025_device::rtc },{1*CLK, &tms32025_device::stc },{1*CLK, &tms32025_device::rol },{1*CLK, &tms32025_device::ror },{1*CLK, &tms32025_device::rfsm },{1*CLK, &tms32025_device::sfsm }, +/*38*/ {1*CLK, &tms32025_device::rhm },{1*CLK, &tms32025_device::shm },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{1*CLK, &tms32025_device::conf },{1*CLK, &tms32025_device::conf },{1*CLK, &tms32025_device::conf },{1*CLK, &tms32025_device::conf }, +/*40*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*48*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*50*/ {1*CLK, &tms32025_device::cmpr },{1*CLK, &tms32025_device::cmpr },{1*CLK, &tms32025_device::cmpr },{1*CLK, &tms32025_device::cmpr },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*58*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*60*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*68*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*70*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*78*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*80*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{1*CLK, &tms32025_device::norm },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*88*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*90*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{1*CLK, &tms32025_device::norm },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*98*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*A0*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{1*CLK, &tms32025_device::norm },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*A8*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*B0*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{1*CLK, &tms32025_device::norm },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*B8*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*C0*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{1*CLK, &tms32025_device::norm },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*C8*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*D0*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{1*CLK, &tms32025_device::norm },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*D8*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*E0*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{1*CLK, &tms32025_device::norm },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*E8*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*F0*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{1*CLK, &tms32025_device::norm },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal }, +/*F8*/ {0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal },{0*CLK, &tms32025_device::illegal } }; -static const tms32025_opcode_Dx opcode_Dx_subset[8]= /* Instructions living under the Dxxx opcode */ +const tms32025_device::tms32025_opcode tms32025_device::s_opcode_Dx_subset[8]= /* Instructions living under the Dxxx opcode */ { -/*00*/ {2*CLK, lrlk },{2*CLK, lalk },{2*CLK, adlk },{2*CLK, sblk },{2*CLK, andk },{2*CLK, ork },{2*CLK, xork },{0*CLK, illegal } +/*00*/ {2*CLK, &tms32025_device::lrlk },{2*CLK, &tms32025_device::lalk },{2*CLK, &tms32025_device::adlk },{2*CLK, &tms32025_device::sblk },{2*CLK, &tms32025_device::andk },{2*CLK, &tms32025_device::ork },{2*CLK, &tms32025_device::xork },{0*CLK, &tms32025_device::illegal } }; @@ -1669,73 +1630,220 @@ static const tms32025_opcode_Dx opcode_Dx_subset[8]= /* Instructions living u /**************************************************************************** * Initialise the CPU emulation ****************************************************************************/ -static CPU_INIT( tms32025 ) -{ - tms32025_state *cpustate = get_safe_token(device); - - cpustate->intRAM = auto_alloc_array(device->machine(), UINT16, 0x800); - cpustate->irq_callback = irqcallback; - cpustate->device = device; - cpustate->program = &device->space(AS_PROGRAM); - cpustate->direct = &cpustate->program->direct(); - cpustate->data = &device->space(AS_DATA); - cpustate->io = &device->space(AS_IO); - - device->save_item(NAME(cpustate->PC)); - device->save_item(NAME(cpustate->STR0)); - device->save_item(NAME(cpustate->STR1)); - device->save_item(NAME(cpustate->PFC)); - device->save_item(NAME(cpustate->IFR)); - device->save_item(NAME(cpustate->RPTC)); - device->save_item(NAME(cpustate->ACC.d)); - device->save_item(NAME(cpustate->ALU.d)); - device->save_item(NAME(cpustate->Preg.d)); - device->save_item(NAME(cpustate->Treg)); - device->save_item(NAME(cpustate->AR[0])); - device->save_item(NAME(cpustate->AR[1])); - device->save_item(NAME(cpustate->AR[2])); - device->save_item(NAME(cpustate->AR[3])); - device->save_item(NAME(cpustate->AR[4])); - device->save_item(NAME(cpustate->AR[5])); - device->save_item(NAME(cpustate->AR[6])); - device->save_item(NAME(cpustate->AR[7])); - device->save_item(NAME(cpustate->STACK[0])); - device->save_item(NAME(cpustate->STACK[1])); - device->save_item(NAME(cpustate->STACK[2])); - device->save_item(NAME(cpustate->STACK[3])); - device->save_item(NAME(cpustate->STACK[4])); - device->save_item(NAME(cpustate->STACK[5])); - device->save_item(NAME(cpustate->STACK[6])); - device->save_item(NAME(cpustate->STACK[7])); - - device->save_item(NAME(cpustate->oldacc)); - device->save_item(NAME(cpustate->memaccess)); - device->save_item(NAME(cpustate->icount)); - device->save_item(NAME(cpustate->mHackIgnoreARP)); - - device->save_item(NAME(cpustate->idle)); - device->save_item(NAME(cpustate->hold)); - device->save_item(NAME(cpustate->external_mem_access)); - device->save_item(NAME(cpustate->init_load_addr)); - device->save_item(NAME(cpustate->PREVPC)); - -// device->save_pointer(NAME(cpustate->intRAM), 0x800*2); +void tms32025_device::device_start() +{ + m_program = &space(AS_PROGRAM); + m_direct = &m_program->direct(); + m_data = &space(AS_DATA); + m_io = &space(AS_IO); + + m_PREVPC = 0; + m_PFC = 0; + m_STR0 = 0; + m_STR1 = 0; + m_ACC.d = 0; + m_Preg.d = 0; + m_Treg = 0; + m_AR[0] = m_AR[1] = m_AR[2] = m_AR[3] = m_AR[4] = m_AR[5] = m_AR[6] = m_AR[7] = 0; + m_STACK[0] = m_STACK[1] = m_STACK[2] = m_STACK[3] = m_STACK[4] = m_STACK[5] = m_STACK[6] = m_STACK[7] = 0; + m_ALU.d = 0; + memset(m_intRAM, 0, sizeof(m_intRAM)); + m_timerover = 0; + m_opcode.d = 0; + m_external_mem_access = 0; + m_tms32025_irq_cycles = 0; + m_oldacc.d = 0; + m_memaccess = 0; + m_mHackIgnoreARP = 0; + m_waiting_for_serial_frame = 0; + + save_item(NAME(m_PC)); + save_item(NAME(m_STR0)); + save_item(NAME(m_STR1)); + save_item(NAME(m_PFC)); + save_item(NAME(m_IFR)); + save_item(NAME(m_RPTC)); + save_item(NAME(m_ACC.d)); + save_item(NAME(m_ALU.d)); + save_item(NAME(m_Preg.d)); + save_item(NAME(m_Treg)); + save_item(NAME(m_AR[0])); + save_item(NAME(m_AR[1])); + save_item(NAME(m_AR[2])); + save_item(NAME(m_AR[3])); + save_item(NAME(m_AR[4])); + save_item(NAME(m_AR[5])); + save_item(NAME(m_AR[6])); + save_item(NAME(m_AR[7])); + save_item(NAME(m_STACK[0])); + save_item(NAME(m_STACK[1])); + save_item(NAME(m_STACK[2])); + save_item(NAME(m_STACK[3])); + save_item(NAME(m_STACK[4])); + save_item(NAME(m_STACK[5])); + save_item(NAME(m_STACK[6])); + save_item(NAME(m_STACK[7])); + + save_item(NAME(m_oldacc)); + save_item(NAME(m_memaccess)); + save_item(NAME(m_icount)); + save_item(NAME(m_mHackIgnoreARP)); + + save_item(NAME(m_idle)); + save_item(NAME(m_hold)); + save_item(NAME(m_external_mem_access)); + save_item(NAME(m_init_load_addr)); + save_item(NAME(m_PREVPC)); + + save_item(NAME(m_intRAM)); + + state_add( TMS32025_PC, "PC", m_PC).formatstr("%04X"); + state_add( TMS32025_STR0, "STR0", m_STR0).formatstr("%04X"); + state_add( TMS32025_STR1, "STR1", m_STR1).formatstr("%04X"); + state_add( TMS32025_IFR, "IFR", m_IFR).formatstr("%04X"); + state_add( TMS32025_RPTC, "RPTC", m_RPTC).formatstr("%02X"); + state_add( TMS32025_STK7, "STK7", m_STACK[7]).formatstr("%04X"); + state_add( TMS32025_STK6, "STK6", m_STACK[6]).formatstr("%04X"); + state_add( TMS32025_STK5, "STK5", m_STACK[5]).formatstr("%04X"); + state_add( TMS32025_STK4, "STK4", m_STACK[4]).formatstr("%04X"); + state_add( TMS32025_STK3, "STK3", m_STACK[3]).formatstr("%04X"); + state_add( TMS32025_STK2, "STK2", m_STACK[2]).formatstr("%04X"); + state_add( TMS32025_STK1, "STK1", m_STACK[1]).formatstr("%04X"); + state_add( TMS32025_STK0, "STK0", m_STACK[0]).formatstr("%04X"); + state_add( TMS32025_ACC, "ACC", m_ACC.d).formatstr("%08X"); + state_add( TMS32025_PREG, "P", m_Preg.d).formatstr("%08X"); + state_add( TMS32025_TREG, "T", m_Treg).formatstr("%04X"); + state_add( TMS32025_AR0, "AR0", m_AR[0]).formatstr("%04X"); + state_add( TMS32025_AR1, "AR1", m_AR[1]).formatstr("%04X"); + state_add( TMS32025_AR2, "AR2", m_AR[2]).formatstr("%04X"); + state_add( TMS32025_AR3, "AR3", m_AR[3]).formatstr("%04X"); + state_add( TMS32025_AR4, "AR4", m_AR[4]).formatstr("%04X"); + state_add( TMS32025_AR5, "AR5", m_AR[5]).formatstr("%04X"); + state_add( TMS32025_AR6, "AR6", m_AR[6]).formatstr("%04X"); + state_add( TMS32025_AR7, "AR7", m_AR[7]).formatstr("%04X"); + state_add( TMS32025_DRR, "DRR", m_debugger_temp).callimport().callexport().formatstr("%04X"); + state_add( TMS32025_DXR, "DXR", m_debugger_temp).callimport().callexport().formatstr("%04X"); + state_add( TMS32025_TIM, "TIM", m_debugger_temp).callimport().callexport().formatstr("%04X"); + state_add( TMS32025_PRD, "PRD", m_debugger_temp).callimport().callexport().formatstr("%04X"); + state_add( TMS32025_IMR, "IMR", m_debugger_temp).callimport().callexport().formatstr("%04X"); + state_add( TMS32025_GREG, "GREG", m_debugger_temp).callimport().callexport().formatstr("%04X"); + + state_add(STATE_GENPC, "GENPC", m_PC).formatstr("%04X").noshow(); + /* This is actually not a stack pointer, but the stack contents */ + state_add(STATE_GENSP, "GENSP", m_STACK[7]).formatstr("%04X").noshow(); + state_add(STATE_GENFLAGS, "GENFLAGS", m_STR0).formatstr("%33s").noshow(); + state_add(STATE_GENPCBASE, "GENPCBASE", m_PREVPC).formatstr("%04X").noshow(); + + m_icountptr = &m_icount; +} + + +void tms32025_device::state_import(const device_state_entry &entry) +{ + switch (entry.index()) + { + case TMS32025_DRR: + M_WRTRAM(0, m_debugger_temp); + break; + + case TMS32025_DXR: + M_WRTRAM(1, m_debugger_temp); + break; + + case TMS32025_TIM: + M_WRTRAM(2, m_debugger_temp); + break; + + case TMS32025_PRD: + M_WRTRAM(3, m_debugger_temp); + break; + + case TMS32025_IMR: + M_WRTRAM(4,m_debugger_temp); + break; + + case TMS32025_GREG: + M_WRTRAM(5, m_debugger_temp); + break; + } +} + + +void tms32025_device::state_export(const device_state_entry &entry) +{ + switch (entry.index()) + { + case TMS32025_DRR: + m_debugger_temp = M_RDRAM(0); + break; + + case TMS32025_DXR: + m_debugger_temp = M_RDRAM(1); + break; + + case TMS32025_TIM: + m_debugger_temp = M_RDRAM(2); + break; + + case TMS32025_PRD: + m_debugger_temp = M_RDRAM(3); + break; + + case TMS32025_IMR: + m_debugger_temp = M_RDRAM(4); + break; + + case TMS32025_GREG: + m_debugger_temp = M_RDRAM(5); + break; + } +} + + +void tms32025_device::state_string_export(const device_state_entry &entry, astring &string) +{ + switch (entry.index()) + { + case STATE_GENFLAGS: + string.printf("arp%d%c%c%c%cdp%03x arb%d%c%c%c%c%c%c%c%c%c%c%cpm%d", + (m_STR0 & 0xe000) >> 13, + m_STR0 & 0x1000 ? 'O':'.', + m_STR0 & 0x0800 ? 'M':'.', + m_STR0 & 0x0400 ? '.':'?', + m_STR0 & 0x0200 ? 'I':'.', + (m_STR0 & 0x01ff), + + (m_STR1 & 0xe000) >> 13, + m_STR1 & 0x1000 ? 'P':'D', + m_STR1 & 0x0800 ? 'T':'.', + m_STR1 & 0x0400 ? 'S':'.', + m_STR1 & 0x0200 ? 'C':'?', + m_STR0 & 0x0100 ? '.':'?', + m_STR1 & 0x0080 ? '.':'?', + m_STR1 & 0x0040 ? 'H':'.', + m_STR1 & 0x0020 ? 'F':'.', + m_STR1 & 0x0010 ? 'X':'.', + m_STR1 & 0x0008 ? 'f':'.', + m_STR1 & 0x0004 ? 'o':'i', + (m_STR1 & 0x0003) + ); + break; + } } + /**************************************************************************** * Reset registers to their initial values ****************************************************************************/ -static CPU_RESET( tms32025 ) +void tms32025_device::device_reset() { - tms32025_state *cpustate = get_safe_token(device); - SET_PC(0); /* Starting address on a reset */ - cpustate->STR0 |= 0x0600; /* INTM and unused bit set to 1 */ - cpustate->STR0 &= 0xefff; /* OV cleared to 0. Remaining bits undefined */ - cpustate->STR1 |= 0x07f0; /* SXM, C, HM, FSM, XF and unused bits set to 1 */ - cpustate->STR1 &= 0xeff0; /* CNF, FO, TXM, PM bits cleared to 0. Remaining bits undefined */ - cpustate->RPTC = 0; /* Reset repeat counter to 0 */ - cpustate->IFR = 0; /* IRQ pending flags */ + m_STR0 |= 0x0600; /* INTM and unused bit set to 1 */ + m_STR0 &= 0xefff; /* OV cleared to 0. Remaining bits undefined */ + m_STR1 |= 0x07f0; /* SXM, C, HM, FSM, XF and unused bits set to 1 */ + m_STR1 &= 0xeff0; /* CNF, FO, TXM, PM bits cleared to 0. Remaining bits undefined */ + m_RPTC = 0; /* Reset repeat counter to 0 */ + m_IFR = 0; /* IRQ pending flags */ S_OUT(TMS32025_XF,ASSERT_LINE); /* XF flag is high. Must set the pin */ @@ -1745,152 +1853,125 @@ static CPU_RESET( tms32025 ) PRD = 0xffff; IMR = 0xffc0; - cpustate->idle = 0; - cpustate->hold = 0; - cpustate->tms32025_dec_cycles = 0; - cpustate->init_load_addr = 1; + m_idle = 0; + m_hold = 0; + m_tms32025_dec_cycles = 0; + m_init_load_addr = 1; /* Reset the Data/Program address banks */ - memset(cpustate->pgmmap, 0, sizeof(cpustate->pgmmap)); - memset(cpustate->datamap, 0, sizeof(cpustate->datamap)); + memset(m_pgmmap, 0, sizeof(m_pgmmap)); + memset(m_datamap, 0, sizeof(m_datamap)); - cpustate->datamap[0] = &cpustate->intRAM[0x000]; /* B2 */ - cpustate->datamap[4] = &cpustate->intRAM[0x200]; /* B0 */ - cpustate->datamap[5] = &cpustate->intRAM[0x280]; /* B0 */ - cpustate->datamap[6] = &cpustate->intRAM[0x300]; /* B1 */ - cpustate->datamap[7] = &cpustate->intRAM[0x380]; /* B1 */ + m_datamap[0] = &m_intRAM[0x000]; /* B2 */ + m_datamap[4] = &m_intRAM[0x200]; /* B0 */ + m_datamap[5] = &m_intRAM[0x280]; /* B0 */ + m_datamap[6] = &m_intRAM[0x300]; /* B1 */ + m_datamap[7] = &m_intRAM[0x380]; /* B1 */ } -static CPU_RESET( tms32026 ) +void tms32026_device::device_reset() { - tms32025_state *cpustate = get_safe_token(device); + tms32025_device::device_reset(); - CPU_RESET_CALL(tms32025); - - /* Reset the Data/Program address banks */ - memset(cpustate->pgmmap, 0, sizeof(cpustate->pgmmap)); - memset(cpustate->datamap, 0, sizeof(cpustate->datamap)); - - cpustate->datamap[0] = &cpustate->intRAM[0x000]; /* B2 */ - cpustate->datamap[4] = &cpustate->intRAM[0x200]; /* B0 */ - cpustate->datamap[5] = &cpustate->intRAM[0x280]; /* B0 */ - cpustate->datamap[6] = &cpustate->intRAM[0x300]; /* B0 */ - cpustate->datamap[7] = &cpustate->intRAM[0x380]; /* B0 */ - cpustate->datamap[8] = &cpustate->intRAM[0x400]; /* B1 */ - cpustate->datamap[9] = &cpustate->intRAM[0x480]; /* B1 */ - cpustate->datamap[10] = &cpustate->intRAM[0x500]; /* B1 */ - cpustate->datamap[11] = &cpustate->intRAM[0x580]; /* B1 */ - cpustate->datamap[12] = &cpustate->intRAM[0x600]; /* B3 */ - cpustate->datamap[13] = &cpustate->intRAM[0x680]; /* B3 */ - cpustate->datamap[14] = &cpustate->intRAM[0x700]; /* B3 */ - cpustate->datamap[15] = &cpustate->intRAM[0x780]; /* B3 */ -} - - -/**************************************************************************** - * Shut down CPU emulation - ****************************************************************************/ -static CPU_EXIT( tms32025 ) -{ + m_datamap[8] = &m_intRAM[0x400]; /* B1 */ + m_datamap[9] = &m_intRAM[0x480]; /* B1 */ + m_datamap[10] = &m_intRAM[0x500]; /* B1 */ + m_datamap[11] = &m_intRAM[0x580]; /* B1 */ + m_datamap[12] = &m_intRAM[0x600]; /* B3 */ + m_datamap[13] = &m_intRAM[0x680]; /* B3 */ + m_datamap[14] = &m_intRAM[0x700]; /* B3 */ + m_datamap[15] = &m_intRAM[0x780]; /* B3 */ } /**************************************************************************** * Issue an interrupt if necessary ****************************************************************************/ -INLINE int process_IRQs(tms32025_state *cpustate) +int tms32025_device::process_IRQs() { /********** Interrupt Flag Register (IFR) ********** | 5 | 4 | 3 | 2 | 1 | 0 | | XINT| RINT| TINT| INT2| INT1| INT0| */ - cpustate->tms32025_irq_cycles = 0; + m_tms32025_irq_cycles = 0; /* Dont service Interrupts if masked, or prev instruction was EINT ! */ - if ( (INTM == 0) && (cpustate->opcode.w.l != 0xce00) && (cpustate->IFR & IMR) ) + if ( (INTM == 0) && (m_opcode.w.l != 0xce00) && (m_IFR & IMR) ) { - cpustate->tms32025_irq_cycles = (3*CLK); /* 3 clock cycles used due to PUSH and DINT operation ? */ - PUSH_STACK(cpustate, cpustate->PC); + m_tms32025_irq_cycles = (3*CLK); /* 3 clock cycles used due to PUSH and DINT operation ? */ + PUSH_STACK(m_PC); - if ((cpustate->IFR & 0x01) && (IMR & 0x01)) { /* IRQ line 0 */ + if ((m_IFR & 0x01) && (IMR & 0x01)) { /* IRQ line 0 */ //logerror("TMS32025: Active INT0\n"); SET_PC(0x0002); - (*cpustate->irq_callback)(cpustate->device, 0); - cpustate->idle = 0; - cpustate->IFR &= (~0x01); - SET0(cpustate, INTM_FLAG); - return cpustate->tms32025_irq_cycles; + standard_irq_callback(0); + m_idle = 0; + m_IFR &= (~0x01); + SET0(INTM_FLAG); + return m_tms32025_irq_cycles; } - if ((cpustate->IFR & 0x02) && (IMR & 0x02)) { /* IRQ line 1 */ + if ((m_IFR & 0x02) && (IMR & 0x02)) { /* IRQ line 1 */ //logerror("TMS32025: Active INT1\n"); SET_PC(0x0004); - (*cpustate->irq_callback)(cpustate->device, 1); - cpustate->idle = 0; - cpustate->IFR &= (~0x02); - SET0(cpustate, INTM_FLAG); - return cpustate->tms32025_irq_cycles; + standard_irq_callback(1); + m_idle = 0; + m_IFR &= (~0x02); + SET0(INTM_FLAG); + return m_tms32025_irq_cycles; } - if ((cpustate->IFR & 0x04) && (IMR & 0x04)) { /* IRQ line 2 */ + if ((m_IFR & 0x04) && (IMR & 0x04)) { /* IRQ line 2 */ //logerror("TMS32025: Active INT2\n"); SET_PC(0x0006); - (*cpustate->irq_callback)(cpustate->device, 2); - cpustate->idle = 0; - cpustate->IFR &= (~0x04); - SET0(cpustate, INTM_FLAG); - return cpustate->tms32025_irq_cycles; + standard_irq_callback(2); + m_idle = 0; + m_IFR &= (~0x04); + SET0(INTM_FLAG); + return m_tms32025_irq_cycles; } - if ((cpustate->IFR & 0x08) && (IMR & 0x08)) { /* Timer IRQ (internal) */ + if ((m_IFR & 0x08) && (IMR & 0x08)) { /* Timer IRQ (internal) */ // logerror("TMS32025: Active TINT (Timer)\n"); SET_PC(0x0018); - cpustate->idle = 0; - cpustate->IFR &= (~0x08); - SET0(cpustate, INTM_FLAG); - return cpustate->tms32025_irq_cycles; + m_idle = 0; + m_IFR &= (~0x08); + SET0(INTM_FLAG); + return m_tms32025_irq_cycles; } - if ((cpustate->IFR & 0x10) && (IMR & 0x10)) { /* Serial port receive IRQ (internal) */ + if ((m_IFR & 0x10) && (IMR & 0x10)) { /* Serial port receive IRQ (internal) */ // logerror("TMS32025: Active RINT (Serial receive)\n"); DRR = S_IN(TMS32025_DR); SET_PC(0x001A); - cpustate->idle = 0; - cpustate->IFR &= (~0x10); - SET0(cpustate, INTM_FLAG); - return cpustate->tms32025_irq_cycles; + m_idle = 0; + m_IFR &= (~0x10); + SET0(INTM_FLAG); + return m_tms32025_irq_cycles; } - if ((cpustate->IFR & 0x20) && (IMR & 0x20)) { /* Serial port transmit IRQ (internal) */ + if ((m_IFR & 0x20) && (IMR & 0x20)) { /* Serial port transmit IRQ (internal) */ // logerror("TMS32025: Active XINT (Serial transmit)\n"); S_OUT(TMS32025_DX,DXR); SET_PC(0x001C); - cpustate->idle = 0; - cpustate->IFR &= (~0x20); - SET0(cpustate, INTM_FLAG); - return cpustate->tms32025_irq_cycles; + m_idle = 0; + m_IFR &= (~0x20); + SET0(INTM_FLAG); + return m_tms32025_irq_cycles; } } - return cpustate->tms32025_irq_cycles; + return m_tms32025_irq_cycles; } -static void set_fsx_line(tms32025_state *cpustate, int state) -{ - if (state != CLEAR_LINE && cpustate->waiting_for_serial_frame) - { - cpustate->waiting_for_serial_frame = 0; - cpustate->IFR = 0x20; - } -} -INLINE void process_timer(tms32025_state *cpustate, int clocks) +void tms32025_device::process_timer(int clocks) { int preclocks, ticks; /* easy case: no actual ticks */ again: - preclocks = CLK - cpustate->timerover; + preclocks = CLK - m_timerover; if (clocks < preclocks) { - cpustate->timerover += clocks; - cpustate->icount -= clocks; + m_timerover += clocks; + m_icount -= clocks; return; } @@ -1898,20 +1979,20 @@ again: ticks = 1 + (clocks - preclocks) / CLK; if (ticks <= TIM) { - cpustate->icount -= clocks; - cpustate->timerover = clocks - (ticks - 1) * CLK - preclocks; + m_icount -= clocks; + m_timerover = clocks - (ticks - 1) * CLK - preclocks; TIM -= ticks; } /* otherwise, overflow the timer and signal an interrupt */ else { - cpustate->icount -= preclocks + CLK * TIM; - cpustate->timerover = 0; + m_icount -= preclocks + CLK * TIM; + m_timerover = 0; TIM = PRD; - cpustate->IFR |= 0x08; - clocks = process_IRQs(cpustate); /* Handle Timer IRQ */ + m_IFR |= 0x08; + clocks = process_IRQs(); /* Handle Timer IRQ */ goto again; } } @@ -1920,77 +2001,74 @@ again: /**************************************************************************** * Execute ICount cycles. Exit when 0 or less ****************************************************************************/ -static CPU_EXECUTE( tms32025 ) +void tms32025_device::execute_run() { - tms32025_state *cpustate = get_safe_token(device); - - /**** Respond to external hold signal */ if (S_IN(TMS32025_HOLD) == ASSERT_LINE) { - if (cpustate->hold == 0) { + if (m_hold == 0) { S_OUT(TMS32025_HOLDA,ASSERT_LINE); /* Hold-Ack (active low) */ } - cpustate->hold = 1; + m_hold = 1; if (HM) { - cpustate->icount = 0; /* Exit */ + m_icount = 0; /* Exit */ } else { - if (cpustate->external_mem_access) { - cpustate->icount = 0; /* Exit */ + if (m_external_mem_access) { + m_icount = 0; /* Exit */ } } } else { - if (cpustate->hold == 1) { + if (m_hold == 1) { S_OUT(TMS32025_HOLDA,CLEAR_LINE); /* Hold-Ack (active low) */ - process_timer(cpustate, 3); + process_timer(3); } - cpustate->hold = 0; + m_hold = 0; } /**** If idling, update timer and/or exit execution, but test for irqs first */ - if (cpustate->idle && cpustate->IFR && cpustate->icount > 0) - cpustate->icount -= process_IRQs(cpustate); + if (m_idle && m_IFR && m_icount > 0) + m_icount -= process_IRQs(); - while (cpustate->idle && cpustate->icount > 0) - process_timer(cpustate, cpustate->icount); + while (m_idle && m_icount > 0) + process_timer(m_icount); - if (cpustate->icount <= 0) debugger_instruction_hook(device, cpustate->PC); + if (m_icount <= 0) debugger_instruction_hook(this, m_PC); - while (cpustate->icount > 0) + while (m_icount > 0) { - cpustate->tms32025_dec_cycles = 0; + m_tms32025_dec_cycles = 0; - if (cpustate->IFR) { /* Check IRQ Flag Register for pending IRQs */ - cpustate->tms32025_dec_cycles += process_IRQs(cpustate); + if (m_IFR) { /* Check IRQ Flag Register for pending IRQs */ + m_tms32025_dec_cycles += process_IRQs(); } - cpustate->PREVPC = cpustate->PC; + m_PREVPC = m_PC; - debugger_instruction_hook(device, cpustate->PC); + debugger_instruction_hook(this, m_PC); - cpustate->opcode.d = M_RDOP(cpustate->PC); - cpustate->PC++; + m_opcode.d = M_RDOP(m_PC); + m_PC++; - if (cpustate->opcode.b.h == 0xCE) /* Opcode 0xCExx has many sub-opcodes in its minor byte */ + if (m_opcode.b.h == 0xCE) /* Opcode 0xCExx has many sub-opcodes in its minor byte */ { - cpustate->tms32025_dec_cycles += opcode_CE_subset[cpustate->opcode.b.l].cycles; - (*opcode_CE_subset[cpustate->opcode.b.l].function)(cpustate); + m_tms32025_dec_cycles += s_opcode_CE_subset[m_opcode.b.l].cycles; + (this->*s_opcode_CE_subset[m_opcode.b.l].function)(); } - else if ((cpustate->opcode.w.l & 0xf0f8) == 0xd000) /* Opcode 0xDxxx has many sub-opcodes in its minor byte */ + else if ((m_opcode.w.l & 0xf0f8) == 0xd000) /* Opcode 0xDxxx has many sub-opcodes in its minor byte */ { - cpustate->tms32025_dec_cycles += opcode_Dx_subset[cpustate->opcode.b.l].cycles; - (*opcode_Dx_subset[cpustate->opcode.b.l].function)(cpustate); + m_tms32025_dec_cycles += s_opcode_Dx_subset[m_opcode.b.l].cycles; + (this->*s_opcode_Dx_subset[m_opcode.b.l].function)(); } else /* Do all opcodes except the CExx and Dxxx ones */ { - cpustate->tms32025_dec_cycles += opcode_main[cpustate->opcode.b.h].cycles; - (*opcode_main[cpustate->opcode.b.h].function)(cpustate); + m_tms32025_dec_cycles += s_opcode_main[m_opcode.b.h].cycles; + (this->*s_opcode_main[m_opcode.b.h].function)(); } - if (cpustate->init_load_addr == 2) { /* Repeat next instruction */ + if (m_init_load_addr == 2) { /* Repeat next instruction */ /****************************************************\ ******* These instructions are not repeatable ******** ** ADLK, ANDK, LALK, LRLK, ORK, SBLK, XORK ** @@ -2000,55 +2078,55 @@ static CPU_EXECUTE( tms32025 ) ** B, BANZ, BBNZ, BBZ, BC, BGEZ, BGZ, BIOZ ** ** BNC, BNV, BNZ, BV, BZ, CALL, BLEZ, BLZ ** \****************************************************/ - cpustate->PREVPC = cpustate->PC; + m_PREVPC = m_PC; - debugger_instruction_hook(device, cpustate->PC); + debugger_instruction_hook(this, m_PC); - cpustate->opcode.d = M_RDOP(cpustate->PC); - cpustate->PC++; - cpustate->tms32025_dec_cycles += (1*CLK); + m_opcode.d = M_RDOP(m_PC); + m_PC++; + m_tms32025_dec_cycles += (1*CLK); do { - if (cpustate->opcode.b.h == 0xCE) + if (m_opcode.b.h == 0xCE) { /* Do all 0xCExx Opcodes */ - if (cpustate->init_load_addr) { - cpustate->tms32025_dec_cycles += (1*CLK); + if (m_init_load_addr) { + m_tms32025_dec_cycles += (1*CLK); } else { - cpustate->tms32025_dec_cycles += (1*CLK); + m_tms32025_dec_cycles += (1*CLK); } - (*opcode_CE_subset[cpustate->opcode.b.l].function)(cpustate); + (this->*s_opcode_CE_subset[m_opcode.b.l].function)(); } else { /* Do all other opcodes */ - if (cpustate->init_load_addr) { - cpustate->tms32025_dec_cycles += (1*CLK); + if (m_init_load_addr) { + m_tms32025_dec_cycles += (1*CLK); } else { - cpustate->tms32025_dec_cycles += (1*CLK); + m_tms32025_dec_cycles += (1*CLK); } - (*opcode_main[cpustate->opcode.b.h].function)(cpustate); + (this->*s_opcode_main[m_opcode.b.h].function)(); } - cpustate->init_load_addr = 0; - cpustate->RPTC-- ; - } while ((INT8)(cpustate->RPTC) != -1); - cpustate->RPTC = 0; - cpustate->PFC = cpustate->PC; - cpustate->init_load_addr = 1; + m_init_load_addr = 0; + m_RPTC-- ; + } while ((INT8)(m_RPTC) != -1); + m_RPTC = 0; + m_PFC = m_PC; + m_init_load_addr = 1; } - process_timer(cpustate, cpustate->tms32025_dec_cycles); + process_timer(m_tms32025_dec_cycles); /**** If device is put into idle mode, exit and wait for an interrupt */ - while (cpustate->idle && cpustate->icount > 0) - process_timer(cpustate, cpustate->icount); + while (m_idle && m_icount > 0) + process_timer(m_icount); /**** If hold pin is active, exit if accessing external memory or if HM is set */ - if (cpustate->hold) { - if (cpustate->external_mem_access || (HM)) { - if (cpustate->icount > 0) { - cpustate->icount = 0; + if (m_hold) { + if (m_external_mem_access || (HM)) { + if (m_icount > 0) { + m_icount = 0; } } } @@ -2060,13 +2138,22 @@ static CPU_EXECUTE( tms32025 ) /**************************************************************************** * Set IRQ line state ****************************************************************************/ -static void set_irq_line(tms32025_state *cpustate, int irqline, int state) +void tms32025_device::execute_set_input(int irqline, int state) { - /* Pending IRQs cannot be cleared */ - - if (state != CLEAR_LINE) + if ( irqline == TMS32025_FSX ) { + if (state != CLEAR_LINE && m_waiting_for_serial_frame) + { + m_waiting_for_serial_frame = 0; + m_IFR = 0x20; + } + } + else { - cpustate->IFR |= (1 << irqline); + /* Pending IRQs cannot be cleared */ + if (state != CLEAR_LINE) + { + m_IFR |= (1 << irqline); + } } } @@ -2074,23 +2161,21 @@ static void set_irq_line(tms32025_state *cpustate, int irqline, int state) /**************************************************************************** * Opcode fetcher ****************************************************************************/ -static CPU_READOP( tms32025 ) +bool tms32025_device::memory_readop(offs_t offset, int size, UINT64 &value) { - tms32025_state *cpustate = get_safe_token(device); - void *ptr; /* skip if not custom */ - if (!cpustate->pgmmap[offset >> 8]) + if (!m_pgmmap[offset >> 8]) return 0; - ptr = &((UINT8 *)&cpustate->pgmmap[offset >> 8])[offset & 0xff]; + ptr = &((UINT8 *)&m_pgmmap[offset >> 8])[offset & 0xff]; switch (size) { - case 1: *value = *((UINT8 *) ptr); - case 2: *value = *((UINT16 *) ptr); - case 4: *value = *((UINT32 *) ptr); - case 8: *value = *((UINT64 *) ptr); + case 1: value = *((UINT8 *) ptr); + case 2: value = *((UINT16 *) ptr); + case 4: value = *((UINT32 *) ptr); + case 8: value = *((UINT64 *) ptr); } return 1; } @@ -2099,23 +2184,21 @@ static CPU_READOP( tms32025 ) /**************************************************************************** * Memory reader ****************************************************************************/ -static CPU_READ( tms32025 ) +bool tms32025_device::memory_read(address_spacenum spacenum, offs_t offset, int size, UINT64 &value) { - tms32025_state *cpustate = get_safe_token(device); - void *ptr = NULL; UINT64 temp = 0; - switch (space) + switch (spacenum) { case AS_PROGRAM: - ptr = cpustate->pgmmap[offset >> 8]; + ptr = m_pgmmap[offset >> 8]; if (!ptr) return 0; break; case AS_DATA: - ptr = cpustate->datamap[offset >> 8]; + ptr = m_datamap[offset >> 8]; if (!ptr) return 0; break; @@ -2128,22 +2211,22 @@ static CPU_READ( tms32025 ) switch (size) { case 1: - *value = ((UINT8 *)ptr)[BYTE_XOR_BE(offset & 0xff)]; + value = ((UINT8 *)ptr)[BYTE_XOR_BE(offset & 0xff)]; break; case 2: - *value = ((UINT16 *)ptr)[(offset & 0xff) / 2]; + value = ((UINT16 *)ptr)[(offset & 0xff) / 2]; break; case 4: - CPU_READ_NAME(tms32025)(device, space, offset + 0, 2, &temp); - *value = temp << 16; - CPU_READ_NAME(tms32025)(device, space, offset + 2, 2, &temp); - *value |= temp & 0xffff; + memory_read(spacenum, offset + 0, 2, temp); + value = temp << 16; + memory_read(spacenum, offset + 2, 2, temp); + value |= temp & 0xffff; break; case 8: - CPU_READ_NAME(tms32025)(device, space, offset + 0, 4, &temp); - *value = temp << 32; - CPU_READ_NAME(tms32025)(device, space, offset + 4, 4, &temp); - *value |= temp & 0xffffffff; + memory_read(spacenum, offset + 0, 4, temp); + value = temp << 32; + memory_read(spacenum, offset + 4, 4, temp); + value |= temp & 0xffffffff; break; } return 1; @@ -2153,22 +2236,20 @@ static CPU_READ( tms32025 ) /**************************************************************************** * Memory writer ****************************************************************************/ -static CPU_WRITE( tms32025 ) +bool tms32025_device::memory_write(address_spacenum spacenum, offs_t offset, int size, UINT64 value) { - tms32025_state *cpustate = get_safe_token(device); - void *ptr = NULL; - switch (space) + switch (spacenum) { case AS_PROGRAM: - ptr = cpustate->pgmmap[offset >> 8]; + ptr = m_pgmmap[offset >> 8]; if (!ptr) return 0; break; case AS_DATA: - ptr = cpustate->datamap[offset >> 8]; + ptr = m_datamap[offset >> 8]; if (!ptr) return 0; break; @@ -2187,248 +2268,15 @@ static CPU_WRITE( tms32025 ) ((UINT16 *)ptr)[(offset & 0xff) / 2] = value; break; case 4: - CPU_WRITE_NAME(tms32025)(device, space, offset + 0, 2, value >> 16); - CPU_WRITE_NAME(tms32025)(device, space, offset + 2, 2, value); + memory_write(spacenum, offset + 0, 2, value >> 16); + memory_write(spacenum, offset + 2, 2, value); break; case 8: - CPU_WRITE_NAME(tms32025)(device, space, offset + 0, 4, value >> 32); - CPU_WRITE_NAME(tms32025)(device, space, offset + 4, 4, value); + memory_write(spacenum, offset + 0, 4, value >> 32); + memory_write(spacenum, offset + 4, 4, value); break; } return 1; } - -/************************************************************************** - * Generic set_info - **************************************************************************/ - -static CPU_SET_INFO( tms32025 ) -{ - tms32025_state *cpustate = get_safe_token(device); - - switch (state) - { - /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + TMS32025_INT0: set_irq_line(cpustate, TMS32025_INT0, info->i); break; - case CPUINFO_INT_INPUT_STATE + TMS32025_INT1: set_irq_line(cpustate, TMS32025_INT1, info->i); break; - case CPUINFO_INT_INPUT_STATE + TMS32025_INT2: set_irq_line(cpustate, TMS32025_INT2, info->i); break; - case CPUINFO_INT_INPUT_STATE + TMS32025_TINT: set_irq_line(cpustate, TMS32025_TINT, info->i); break; - case CPUINFO_INT_INPUT_STATE + TMS32025_RINT: set_irq_line(cpustate, TMS32025_RINT, info->i); break; - case CPUINFO_INT_INPUT_STATE + TMS32025_XINT: set_irq_line(cpustate, TMS32025_XINT, info->i); break; - case CPUINFO_INT_INPUT_STATE + TMS32025_FSX: set_fsx_line(cpustate, info->i); break; - - case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + TMS32025_PC: cpustate->PC = info->i; break; - /* This is actually not a stack pointer, but the stack contents */ - case CPUINFO_INT_SP: - case CPUINFO_INT_REGISTER + TMS32025_STK7: cpustate->STACK[7] = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_STK6: cpustate->STACK[6] = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_STK5: cpustate->STACK[5] = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_STK4: cpustate->STACK[4] = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_STK3: cpustate->STACK[3] = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_STK2: cpustate->STACK[2] = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_STK1: cpustate->STACK[1] = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_STK0: cpustate->STACK[0] = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_STR0: cpustate->STR0 = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_STR1: cpustate->STR1 = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_IFR: cpustate->IFR = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_RPTC: cpustate->RPTC = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_ACC: cpustate->ACC.d = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_PREG: cpustate->Preg.d = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_TREG: cpustate->Treg = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_AR0: cpustate->AR[0] = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_AR1: cpustate->AR[1] = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_AR2: cpustate->AR[2] = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_AR3: cpustate->AR[3] = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_AR4: cpustate->AR[4] = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_AR5: cpustate->AR[5] = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_AR6: cpustate->AR[6] = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_AR7: cpustate->AR[7] = info->i; break; - case CPUINFO_INT_REGISTER + TMS32025_DRR: M_WRTRAM(cpustate, 0,info->i); break; - case CPUINFO_INT_REGISTER + TMS32025_DXR: M_WRTRAM(cpustate, 1,info->i); break; - case CPUINFO_INT_REGISTER + TMS32025_TIM: M_WRTRAM(cpustate, 2,info->i); break; - case CPUINFO_INT_REGISTER + TMS32025_PRD: M_WRTRAM(cpustate, 3,info->i); break; - case CPUINFO_INT_REGISTER + TMS32025_IMR: M_WRTRAM(cpustate, 4,info->i); break; - case CPUINFO_INT_REGISTER + TMS32025_GREG: M_WRTRAM(cpustate, 5,info->i); break; - } -} - - - -/************************************************************************** - * Generic get_info - **************************************************************************/ - -CPU_GET_INFO( tms32025 ) -{ - tms32025_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(tms32025_state); break; - case CPUINFO_INT_INPUT_LINES: info->i = 6; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1*CLK; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 5*CLK; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = -1; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = -1; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 17; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = -1; break; - - case CPUINFO_INT_INPUT_STATE + TMS32025_INT0: info->i = (cpustate->IFR & 0x01) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + TMS32025_INT1: info->i = (cpustate->IFR & 0x02) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + TMS32025_INT2: info->i = (cpustate->IFR & 0x04) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + TMS32025_TINT: info->i = (cpustate->IFR & 0x08) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + TMS32025_RINT: info->i = (cpustate->IFR & 0x10) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + TMS32025_XINT: info->i = (cpustate->IFR & 0x20) ? ASSERT_LINE : CLEAR_LINE; break; - - case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->PREVPC; break; - - case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + TMS32025_PC: info->i = cpustate->PC; break; - /* This is actually not a stack pointer, but the stack contents */ - case CPUINFO_INT_SP: - case CPUINFO_INT_REGISTER + TMS32025_STK7: info->i = cpustate->STACK[7]; break; - case CPUINFO_INT_REGISTER + TMS32025_STK6: info->i = cpustate->STACK[6]; break; - case CPUINFO_INT_REGISTER + TMS32025_STK5: info->i = cpustate->STACK[5]; break; - case CPUINFO_INT_REGISTER + TMS32025_STK4: info->i = cpustate->STACK[4]; break; - case CPUINFO_INT_REGISTER + TMS32025_STK3: info->i = cpustate->STACK[3]; break; - case CPUINFO_INT_REGISTER + TMS32025_STK2: info->i = cpustate->STACK[2]; break; - case CPUINFO_INT_REGISTER + TMS32025_STK1: info->i = cpustate->STACK[1]; break; - case CPUINFO_INT_REGISTER + TMS32025_STK0: info->i = cpustate->STACK[0]; break; - case CPUINFO_INT_REGISTER + TMS32025_STR0: info->i = cpustate->STR0; break; - case CPUINFO_INT_REGISTER + TMS32025_STR1: info->i = cpustate->STR1; break; - case CPUINFO_INT_REGISTER + TMS32025_IFR: info->i = cpustate->IFR; break; - case CPUINFO_INT_REGISTER + TMS32025_RPTC: info->i = cpustate->RPTC; break; - case CPUINFO_INT_REGISTER + TMS32025_ACC: info->i = cpustate->ACC.d; break; - case CPUINFO_INT_REGISTER + TMS32025_PREG: info->i = cpustate->Preg.d; break; - case CPUINFO_INT_REGISTER + TMS32025_TREG: info->i = cpustate->Treg; break; - case CPUINFO_INT_REGISTER + TMS32025_AR0: info->i = cpustate->AR[0]; break; - case CPUINFO_INT_REGISTER + TMS32025_AR1: info->i = cpustate->AR[1]; break; - case CPUINFO_INT_REGISTER + TMS32025_AR2: info->i = cpustate->AR[2]; break; - case CPUINFO_INT_REGISTER + TMS32025_AR3: info->i = cpustate->AR[3]; break; - case CPUINFO_INT_REGISTER + TMS32025_AR4: info->i = cpustate->AR[4]; break; - case CPUINFO_INT_REGISTER + TMS32025_AR5: info->i = cpustate->AR[5]; break; - case CPUINFO_INT_REGISTER + TMS32025_AR6: info->i = cpustate->AR[6]; break; - case CPUINFO_INT_REGISTER + TMS32025_AR7: info->i = cpustate->AR[7]; break; - case CPUINFO_INT_REGISTER + TMS32025_DRR: info->i = M_RDRAM(cpustate, 0); break; - case CPUINFO_INT_REGISTER + TMS32025_DXR: info->i = M_RDRAM(cpustate, 1); break; - case CPUINFO_INT_REGISTER + TMS32025_TIM: info->i = M_RDRAM(cpustate, 2); break; - case CPUINFO_INT_REGISTER + TMS32025_PRD: info->i = M_RDRAM(cpustate, 3); break; - case CPUINFO_INT_REGISTER + TMS32025_IMR: info->i = M_RDRAM(cpustate, 4); break; - case CPUINFO_INT_REGISTER + TMS32025_GREG: info->i = M_RDRAM(cpustate, 5); break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(tms32025); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(tms32025); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(tms32025); break; - case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(tms32025); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(tms32025); break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(tms32025); break; - case CPUINFO_FCT_READ: info->read = CPU_READ_NAME(tms32025); break; - case CPUINFO_FCT_WRITE: info->write = CPU_WRITE_NAME(tms32025); break; - case CPUINFO_FCT_READOP: info->readop = CPU_READOP_NAME(tms32025); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "TMS32025"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "tms32025"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "Texas Instruments TMS320x25"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "1.10"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Tony La Porta"); break; - - case CPUINFO_STR_FLAGS: - sprintf(info->s, "arp%d%c%c%c%cdp%03x arb%d%c%c%c%c%c%c%c%c%c%c%cpm%d", - (cpustate->STR0 & 0xe000) >> 13, - cpustate->STR0 & 0x1000 ? 'O':'.', - cpustate->STR0 & 0x0800 ? 'M':'.', - cpustate->STR0 & 0x0400 ? '.':'?', - cpustate->STR0 & 0x0200 ? 'I':'.', - (cpustate->STR0 & 0x01ff), - - (cpustate->STR1 & 0xe000) >> 13, - cpustate->STR1 & 0x1000 ? 'P':'D', - cpustate->STR1 & 0x0800 ? 'T':'.', - cpustate->STR1 & 0x0400 ? 'S':'.', - cpustate->STR1 & 0x0200 ? 'C':'?', - cpustate->STR0 & 0x0100 ? '.':'?', - cpustate->STR1 & 0x0080 ? '.':'?', - cpustate->STR1 & 0x0040 ? 'H':'.', - cpustate->STR1 & 0x0020 ? 'F':'.', - cpustate->STR1 & 0x0010 ? 'X':'.', - cpustate->STR1 & 0x0008 ? 'f':'.', - cpustate->STR1 & 0x0004 ? 'o':'i', - (cpustate->STR1 & 0x0003) ); - break; - - case CPUINFO_STR_REGISTER + TMS32025_PC: sprintf(info->s, "PC:%04X", cpustate->PC); break; - case CPUINFO_STR_REGISTER + TMS32025_STR0: sprintf(info->s, "STR0:%04X", cpustate->STR0); break; - case CPUINFO_STR_REGISTER + TMS32025_STR1: sprintf(info->s, "STR1:%04X", cpustate->STR1); break; - case CPUINFO_STR_REGISTER + TMS32025_IFR: sprintf(info->s, "IFR:%04X", cpustate->IFR); break; - case CPUINFO_STR_REGISTER + TMS32025_RPTC: sprintf(info->s, "RPTC:%02X", cpustate->RPTC); break; - case CPUINFO_STR_REGISTER + TMS32025_STK7: sprintf(info->s, "STK7:%04X", cpustate->STACK[7]); break; - case CPUINFO_STR_REGISTER + TMS32025_STK6: sprintf(info->s, "STK6:%04X", cpustate->STACK[6]); break; - case CPUINFO_STR_REGISTER + TMS32025_STK5: sprintf(info->s, "STK5:%04X", cpustate->STACK[5]); break; - case CPUINFO_STR_REGISTER + TMS32025_STK4: sprintf(info->s, "STK4:%04X", cpustate->STACK[4]); break; - case CPUINFO_STR_REGISTER + TMS32025_STK3: sprintf(info->s, "STK3:%04X", cpustate->STACK[3]); break; - case CPUINFO_STR_REGISTER + TMS32025_STK2: sprintf(info->s, "STK2:%04X", cpustate->STACK[2]); break; - case CPUINFO_STR_REGISTER + TMS32025_STK1: sprintf(info->s, "STK1:%04X", cpustate->STACK[1]); break; - case CPUINFO_STR_REGISTER + TMS32025_STK0: sprintf(info->s, "STK0:%04X", cpustate->STACK[0]); break; - case CPUINFO_STR_REGISTER + TMS32025_ACC: sprintf(info->s, "ACC:%08X", cpustate->ACC.d); break; - case CPUINFO_STR_REGISTER + TMS32025_PREG: sprintf(info->s, "P:%08X", cpustate->Preg.d); break; - case CPUINFO_STR_REGISTER + TMS32025_TREG: sprintf(info->s, "T:%04X", cpustate->Treg); break; - case CPUINFO_STR_REGISTER + TMS32025_AR0: sprintf(info->s, "AR0:%04X", cpustate->AR[0]); break; - case CPUINFO_STR_REGISTER + TMS32025_AR1: sprintf(info->s, "AR1:%04X", cpustate->AR[1]); break; - case CPUINFO_STR_REGISTER + TMS32025_AR2: sprintf(info->s, "AR2:%04X", cpustate->AR[2]); break; - case CPUINFO_STR_REGISTER + TMS32025_AR3: sprintf(info->s, "AR3:%04X", cpustate->AR[3]); break; - case CPUINFO_STR_REGISTER + TMS32025_AR4: sprintf(info->s, "AR4:%04X", cpustate->AR[4]); break; - case CPUINFO_STR_REGISTER + TMS32025_AR5: sprintf(info->s, "AR5:%04X", cpustate->AR[5]); break; - case CPUINFO_STR_REGISTER + TMS32025_AR6: sprintf(info->s, "AR6:%04X", cpustate->AR[6]); break; - case CPUINFO_STR_REGISTER + TMS32025_AR7: sprintf(info->s, "AR7:%04X", cpustate->AR[7]); break; - case CPUINFO_STR_REGISTER + TMS32025_DRR: sprintf(info->s, "DRR:%04X", M_RDRAM(cpustate, 0)); break; - case CPUINFO_STR_REGISTER + TMS32025_DXR: sprintf(info->s, "DXR:%04X", M_RDRAM(cpustate, 1)); break; - case CPUINFO_STR_REGISTER + TMS32025_TIM: sprintf(info->s, "TIM:%04X", M_RDRAM(cpustate, 2)); break; - case CPUINFO_STR_REGISTER + TMS32025_PRD: sprintf(info->s, "PRD:%04X", M_RDRAM(cpustate, 3)); break; - case CPUINFO_STR_REGISTER + TMS32025_IMR: sprintf(info->s, "IMR:%04X", M_RDRAM(cpustate, 4)); break; - case CPUINFO_STR_REGISTER + TMS32025_GREG: sprintf(info->s, "GREG:%04X", M_RDRAM(cpustate, 5)); break; - } -} - - -/************************************************************************** - * CPU-specific set_info - **************************************************************************/ - -CPU_GET_INFO( tms32026 ) -{ - switch (state) - { - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(tms32026); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "TMS32026"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "tms32026"); break; - - default: CPU_GET_INFO_CALL(tms32025); break; - } -} - -DEFINE_LEGACY_CPU_DEVICE(TMS32025, tms32025); -DEFINE_LEGACY_CPU_DEVICE(TMS32026, tms32026); diff --git a/src/emu/cpu/tms32025/tms32025.h b/src/emu/cpu/tms32025/tms32025.h index 92034c9a694..8c1cb44d40e 100644 --- a/src/emu/cpu/tms32025/tms32025.h +++ b/src/emu/cpu/tms32025/tms32025.h @@ -66,9 +66,301 @@ enum * Public Functions */ -DECLARE_LEGACY_CPU_DEVICE(TMS32025, tms32025); -DECLARE_LEGACY_CPU_DEVICE(TMS32026, tms32026); -CPU_DISASSEMBLE( tms32025 ); +class tms32025_device : public cpu_device +{ +public: + // construction/destruction + tms32025_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + tms32025_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source); + +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const { return 4; } + virtual UINT32 execute_max_cycles() const { return 20; } + virtual UINT32 execute_input_lines() const { return 6; } + virtual void execute_run(); + virtual void execute_set_input(int inputnum, int state); + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ) ); } + virtual bool memory_read(address_spacenum spacenum, offs_t offset, int size, UINT64 &value); + virtual bool memory_write(address_spacenum spacenum, offs_t offset, int size, UINT64 value); + virtual bool memory_readop(offs_t offset, int size, UINT64 &value); + + // device_state_interface overrides + virtual void state_import(const device_state_entry &entry); + virtual void state_export(const device_state_entry &entry); + void state_string_export(const device_state_entry &entry, astring &string); + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const { return 2; } + virtual UINT32 disasm_max_opcode_bytes() const { return 4; } + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + +private: + address_space_config m_program_config; + address_space_config m_data_config; + address_space_config m_io_config; + + typedef void ( tms32025_device::*opcode_func ) (); + struct tms32025_opcode + { + UINT8 cycles; + opcode_func function; + }; + static const tms32025_opcode s_opcode_main[256]; + static const tms32025_opcode s_opcode_CE_subset[256]; + static const tms32025_opcode s_opcode_Dx_subset[8]; + + + /******************** CPU Internal Registers *******************/ + UINT16 m_PREVPC; /* previous program counter */ + UINT16 m_PC; + UINT16 m_PFC; + UINT16 m_STR0, m_STR1; + UINT8 m_IFR; + UINT8 m_RPTC; + PAIR m_ACC; + PAIR m_Preg; + UINT16 m_Treg; + UINT16 m_AR[8]; + UINT16 m_STACK[8]; + PAIR m_ALU; +protected: + UINT16 m_intRAM[0x800]; +private: + UINT8 m_timerover; + + /********************** Status data ****************************/ + PAIR m_opcode; + int m_idle; + int m_hold; + int m_external_mem_access; /** required for hold mode. Implement it ! */ + int m_init_load_addr; /* 0=No, 1=Yes, 2=Once for repeat mode */ + int m_tms32025_irq_cycles; + int m_tms32025_dec_cycles; + + PAIR m_oldacc; + UINT32 m_memaccess; + int m_icount; + int m_mHackIgnoreARP; /* special handling for lst, lst1 instructions */ + int m_waiting_for_serial_frame; + + address_space *m_program; + direct_read_data *m_direct; + address_space *m_data; + address_space *m_io; + + UINT16 *m_pgmmap[0x200]; +protected: + UINT16 *m_datamap[0x200]; + +private: + UINT32 m_debugger_temp; + + inline void CLR0(UINT16 flag); + inline void SET0(UINT16 flag); + inline void CLR1(UINT16 flag); + inline void SET1(UINT16 flag); + inline void MODIFY_DP(int data); + inline void MODIFY_PM(int data); + inline void MODIFY_ARP(int data); + inline UINT16 M_RDROM(offs_t addr); + inline void M_WRTROM(offs_t addr, UINT16 data); + inline UINT16 M_RDRAM(offs_t addr); + inline void M_WRTRAM(offs_t addr, UINT16 data); + UINT16 reverse_carry_add(UINT16 arg0, UINT16 arg1 ); + inline void MODIFY_AR_ARP(); + inline void CALCULATE_ADD_CARRY(); + inline void CALCULATE_SUB_CARRY(); + inline void CALCULATE_ADD_OVERFLOW(INT32 addval); + inline void CALCULATE_SUB_OVERFLOW(INT32 subval); + inline UINT16 POP_STACK(); + inline void PUSH_STACK(UINT16 data); + inline void SHIFT_Preg_TO_ALU(); + inline void GETDATA(int shift,int signext); + inline void PUTDATA(UINT16 data); + inline void PUTDATA_SST(UINT16 data); + void opcodes_CE(); + void opcodes_Dx(); + void illegal(); + void abst(); + void add(); + void addc(); + void addh(); + void addk(); + void adds(); + void addt(); + void adlk(); + void adrk(); + void and_(); + void andk(); + void apac(); + void br(); + void bacc(); + void banz(); + void bbnz(); + void bbz(); + void bc(); + void bgez(); + void bgz(); + void bioz(); + void bit(); + void bitt(); + void blez(); + void blkd(); + void blkp(); + void blz(); + void bnc(); + void bnv(); + void bnz(); + void bv(); + void bz(); + void cala(); + void call(); + void cmpl(); + void cmpr(); + void cnfd(); + void cnfp(); + void conf(); + void dint(); + void dmov(); + void eint(); + void fort(); + void idle(); + void in(); + void lac(); + void lack(); + void lact(); + void lalk(); + void lar_ar0(); + void lar_ar1(); + void lar_ar2(); + void lar_ar3(); + void lar_ar4(); + void lar_ar5(); + void lar_ar6(); + void lar_ar7(); + void lark_ar0(); + void lark_ar1(); + void lark_ar2(); + void lark_ar3(); + void lark_ar4(); + void lark_ar5(); + void lark_ar6(); + void lark_ar7(); + void ldp(); + void ldpk(); + void lph(); + void lrlk(); + void lst(); + void lst1(); + void lt(); + void lta(); + void ltd(); + void ltp(); + void lts(); + void mac(); + void macd(); + void mar(); + void mpy(); + void mpya(); + void mpyk(); + void mpys(); + void mpyu(); + void neg(); + void nop(); + void norm(); + void or_(); + void ork(); + void out(); + void pac(); + void pop(); + void popd(); + void pshd(); + void push(); + void rc(); + void ret(); + void rfsm(); + void rhm(); + void rol(); + void ror(); + void rovm(); + void rpt(); + void rptk(); + void rsxm(); + void rtc(); + void rtxm(); + void rxf(); + void sach(); + void sacl(); + void sar_ar0(); + void sar_ar1(); + void sar_ar2(); + void sar_ar3(); + void sar_ar4(); + void sar_ar5(); + void sar_ar6(); + void sar_ar7(); + void sblk(); + void sbrk_ar(); + void sc(); + void sfl(); + void sfr(); + void sfsm(); + void shm(); + void sovm(); + void spac(); + void sph(); + void spl(); + void spm(); + void sqra(); + void sqrs(); + void sst(); + void sst1(); + void ssxm(); + void stc(); + void stxm(); + void sub(); + void subb(); + void subc(); + void subh(); + void subk(); + void subs(); + void subt(); + void sxf(); + void tblr(); + void tblw(); + void trap(); + void xor_(); + void xork(); + void zalh(); + void zalr(); + void zals(); + inline int process_IRQs(); + inline void process_timer(int clocks); + +}; + + +class tms32026_device : public tms32025_device +{ +public: + // construction/destruction + tms32026_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + +protected: + virtual void device_reset(); +}; + + +extern const device_type TMS32025; +extern const device_type TMS32026; + #endif /* __TMS32025_H__ */ |