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-rw-r--r--src/devices/cpu/z180/z180.cpp89
-rw-r--r--src/devices/cpu/z180/z180.h12
-rw-r--r--src/devices/cpu/z180/z180dasm.cpp4
-rw-r--r--src/devices/cpu/z180/z180dd.hxx2
-rw-r--r--src/devices/cpu/z180/z180fd.hxx2
5 files changed, 51 insertions, 58 deletions
diff --git a/src/devices/cpu/z180/z180.cpp b/src/devices/cpu/z180/z180.cpp
index b95edbb20ca..f9f15f0d834 100644
--- a/src/devices/cpu/z180/z180.cpp
+++ b/src/devices/cpu/z180/z180.cpp
@@ -1786,9 +1786,7 @@ void z180_device::device_start()
save_item(NAME(m_nmi_pending));
save_item(NAME(m_irq_state));
save_item(NAME(m_int_pending));
- save_item(NAME(m_timer_cnt));
- save_item(NAME(m_dma0_cnt));
- save_item(NAME(m_dma1_cnt));
+ save_item(NAME(m_frc_prescale));
save_item(NAME(m_after_EI));
save_item(NAME(m_read_tcr_tmdr));
@@ -1906,9 +1904,8 @@ void z180_device::device_reset()
m_int_pending[i] = 0;
}
- m_timer_cnt = 0;
- m_dma0_cnt = 0;
- m_dma1_cnt = 0;
+ m_frc = 0xff;
+ m_frc_prescale = 0;
/* reset io registers */
m_asci_cntla[0] = (m_asci_cntla[0] & Z180_CNTLA0_MPBR_EFR) | Z180_CNTLA0_RTS0;
@@ -1949,52 +1946,42 @@ void z8s180_device::device_reset()
/* Handle PRT timers, decreasing them after 20 clocks and returning the new icount base that needs to be used for the next check */
void z180_device::clock_timers()
{
- m_timer_cnt++;
- if (m_timer_cnt >= 20)
+ /* Programmable Reload Timer 0 */
+ if(m_tcr & Z180_TCR_TDE0)
{
- m_timer_cnt = 0;
- /* Programmable Reload Timer 0 */
- if(m_tcr & Z180_TCR_TDE0)
+ if(m_tmdr_value[0] == 0)
{
- if(m_tmdr_value[0] == 0)
- {
- m_tmdr_value[0] = m_rldr[0].w;
- m_tcr |= Z180_TCR_TIF0;
- }
- else
- m_tmdr_value[0]--;
- }
-
- /* Programmable Reload Timer 1 */
- if(m_tcr & Z180_TCR_TDE1)
- {
- if(m_tmdr_value[1] == 0)
- {
- m_tmdr_value[1] = m_rldr[1].w;
- m_tcr |= Z180_TCR_TIF1;
- }
- else
- m_tmdr_value[1]--;
+ m_tmdr_value[0] = m_rldr[0].w;
+ m_tcr |= Z180_TCR_TIF0;
}
+ else
+ m_tmdr_value[0]--;
+ }
- if((m_tcr & Z180_TCR_TIE0) && (m_tcr & Z180_TCR_TIF0))
+ /* Programmable Reload Timer 1 */
+ if(m_tcr & Z180_TCR_TDE1)
+ {
+ if(m_tmdr_value[1] == 0)
{
- // check if we can take the interrupt
- if(m_IFF1 && !m_after_EI)
- {
- m_int_pending[Z180_INT_PRT0] = 1;
- }
+ m_tmdr_value[1] = m_rldr[1].w;
+ m_tcr |= Z180_TCR_TIF1;
}
+ else
+ m_tmdr_value[1]--;
+ }
- if((m_tcr & Z180_TCR_TIE1) && (m_tcr & Z180_TCR_TIF1))
- {
- // check if we can take the interrupt
- if(m_IFF1 && !m_after_EI)
- {
- m_int_pending[Z180_INT_PRT1] = 1;
- }
- }
+ if((m_tcr & Z180_TCR_TIE0) && (m_tcr & Z180_TCR_TIF0))
+ {
+ // check if we can take the interrupt
+ if(m_IFF1 && !m_after_EI)
+ m_int_pending[Z180_INT_PRT0] = 1;
+ }
+ if((m_tcr & Z180_TCR_TIE1) && (m_tcr & Z180_TCR_TIF1))
+ {
+ // check if we can take the interrupt
+ if(m_IFF1 && !m_after_EI)
+ m_int_pending[Z180_INT_PRT1] = 1;
}
}
@@ -2035,7 +2022,17 @@ void z180_device::handle_io_timers(int cycles)
{
while (cycles-- > 0)
{
- clock_timers();
+ // FRC counts down by 1 every 10 cycles
+ m_frc_prescale++;
+ if (m_frc_prescale >= 10)
+ {
+ m_frc_prescale = 0;
+ m_frc--;
+
+ // Programmable reload timers are clocked once every 20 cycles
+ if ((m_frc & 1) == 0)
+ clock_timers();
+ }
}
}
@@ -2096,7 +2093,6 @@ again:
if (!m_HALT)
{
m_R++;
- m_frc++; /* Added FRC counting, not implemented yet */
m_extra_cycles = 0;
curcycles = exec_op(ROP());
curcycles += m_extra_cycles;
@@ -2155,7 +2151,6 @@ again:
if (!m_HALT)
{
m_R++;
- m_frc++; /* Added FRC counting, not implemented yet */
m_extra_cycles = 0;
curcycles = exec_op(ROP());
curcycles += m_extra_cycles;
diff --git a/src/devices/cpu/z180/z180.h b/src/devices/cpu/z180/z180.h
index 5153c5e1f89..4dd8821991d 100644
--- a/src/devices/cpu/z180/z180.h
+++ b/src/devices/cpu/z180/z180.h
@@ -171,10 +171,11 @@ private:
uint8_t m_asci_rdr[2]; // ASCI receive data register 0-1
uint8_t m_csio_cntr; // CSI/O control/status register
uint8_t m_csio_trdr; // CSI/O transmit/receive register
- PAIR16 m_tmdr[2]; // TIMER data register ch 0-1
- PAIR16 m_rldr[2]; // TIMER reload register ch 0-1
- uint8_t m_tcr; // TIMER control register
- uint8_t m_frc; // free running counter
+ PAIR16 m_tmdr[2]; // PRT data register ch 0-1
+ PAIR16 m_rldr[2]; // PRT reload register ch 0-1
+ uint8_t m_tcr; // PRT control register
+ uint8_t m_frc; // free running counter (also time base for ASCI, CSI/O & PRT)
+ uint8_t m_frc_prescale; // divide CPU clock by 10
PAIR m_dma_sar0; // DMA source address register ch 0
PAIR m_dma_dar0; // DMA destination address register ch 0
PAIR16 m_dma_bcr[2]; // DMA byte register ch 0-1
@@ -200,9 +201,6 @@ private:
uint8_t m_int_pending[11 + 1]; // interrupt pending
uint8_t m_after_EI; // are we in the EI shadow?
uint32_t m_ea;
- uint8_t m_timer_cnt; // timer counter / divide by 20
- uint8_t m_dma0_cnt; // DMA0 counter / divide by 20
- uint8_t m_dma1_cnt; // DMA1 counter / divide by 20
memory_access<20, 0, 0, ENDIANNESS_LITTLE>::cache m_cprogram, m_copcodes;
memory_access<20, 0, 0, ENDIANNESS_LITTLE>::specific m_program;
memory_access<16, 0, 0, ENDIANNESS_LITTLE>::specific m_io;
diff --git a/src/devices/cpu/z180/z180dasm.cpp b/src/devices/cpu/z180/z180dasm.cpp
index f8d332eca15..c6dc3ea1706 100644
--- a/src/devices/cpu/z180/z180dasm.cpp
+++ b/src/devices/cpu/z180/z180dasm.cpp
@@ -402,7 +402,7 @@ offs_t z180_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat
if( op1 == 0xcb )
{
offset = (int8_t) params.r8(pos++);
- op1 = params.r8(pos++); /* fourth byte from opbase.ram! */
+ op1 = opcodes.r8(pos++); // M1 fetch, unlike Z80
d = &mnemonic_xx_cb[op1];
}
else d = &mnemonic_xx[op1];
@@ -413,7 +413,7 @@ offs_t z180_disassembler::disassemble(std::ostream &stream, offs_t pc, const dat
if( op1 == 0xcb )
{
offset = (int8_t) params.r8(pos++);
- op1 = params.r8(pos++); /* fourth byte from opbase.ram! */
+ op1 = opcodes.r8(pos++); // M1 fetch, unlike Z80
d = &mnemonic_xx_cb[op1];
}
else d = &mnemonic_xx[op1];
diff --git a/src/devices/cpu/z180/z180dd.hxx b/src/devices/cpu/z180/z180dd.hxx
index 48c9cc497f2..d73c9720cf3 100644
--- a/src/devices/cpu/z180/z180dd.hxx
+++ b/src/devices/cpu/z180/z180dd.hxx
@@ -236,7 +236,7 @@ OP(dd,c7) { illegal_1(); op_c7(); } /*
OP(dd,c8) { illegal_1(); op_c8(); } /* DB DD */
OP(dd,c9) { illegal_1(); op_c9(); } /* DB DD */
OP(dd,ca) { illegal_1(); op_ca(); } /* DB DD */
-OP(dd,cb) { m_R++; EAX(); m_extra_cycles += exec_xycb(ARG()); } /* ** DD CB xx */
+OP(dd,cb) { m_R++; EAX(); m_extra_cycles += exec_xycb(ROP()); } /* ** DD CB xx */
OP(dd,cc) { illegal_1(); op_cc(); } /* DB DD */
OP(dd,cd) { illegal_1(); op_cd(); } /* DB DD */
OP(dd,ce) { illegal_1(); op_ce(); } /* DB DD */
diff --git a/src/devices/cpu/z180/z180fd.hxx b/src/devices/cpu/z180/z180fd.hxx
index 66697a9b997..c34e6876e68 100644
--- a/src/devices/cpu/z180/z180fd.hxx
+++ b/src/devices/cpu/z180/z180fd.hxx
@@ -231,7 +231,7 @@ OP(fd,c7) { illegal_1(); op_c7(); } /* DB FD
OP(fd,c8) { illegal_1(); op_c8(); } /* DB FD */
OP(fd,c9) { illegal_1(); op_c9(); } /* DB FD */
OP(fd,ca) { illegal_1(); op_ca(); } /* DB FD */
-OP(fd,cb) { m_R++; EAY(); m_extra_cycles += exec_xycb(ARG()); } /* ** FD CB xx */
+OP(fd,cb) { m_R++; EAY(); m_extra_cycles += exec_xycb(ROP()); } /* ** FD CB xx */
OP(fd,cc) { illegal_1(); op_cc(); } /* DB FD */
OP(fd,cd) { illegal_1(); op_cd(); } /* DB FD */
OP(fd,ce) { illegal_1(); op_ce(); } /* DB FD */