diff options
| author | 2014-08-26 21:00:27 +0000 | |
|---|---|---|
| committer | 2014-08-26 21:00:27 +0000 | |
| commit | ef41f2d392da4ff232e51c6d293fcf79eaa108d0 (patch) | |
| tree | 0df7bc2b01395cab126968ef66813b7cbc1a6b20 /src/emu | |
| parent | f3d5b94895539b0e740f088c493dbe177826109c (diff) | |
mips3drc: Throw badcop exceptions on COP1 accesses while the COP1 status bit is
not enabled [MarathonMan]
Diffstat (limited to 'src/emu')
| -rw-r--r-- | src/emu/cpu/mips/mips3drc.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/emu/cpu/mips/mips3drc.c b/src/emu/cpu/mips/mips3drc.c index fa05e149f35..83a098da129 100644 --- a/src/emu/cpu/mips/mips3drc.c +++ b/src/emu/cpu/mips/mips3drc.c @@ -1617,6 +1617,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler, return TRUE; case 0x31: /* LWC1 - MIPS I */ + UML_TEST(block, CPR032(COP0_Status), SR_COP1); // test [Status],SR_COP1 + UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], 1); // exh cop,1,Z UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh read32 UML_MOV(block, FPR32(RTREG), I0); // mov <cpr1_rt>,i0 @@ -1625,6 +1627,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler, return TRUE; case 0x35: /* LDC1 - MIPS III */ + UML_TEST(block, CPR032(COP0_Status), SR_COP1); // test [Status],SR_COP1 + UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], 1); // exh cop,1,Z UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh read64 UML_DMOV(block, FPR64(RTREG), I0); // dmov <cpr1_rt>,i0 @@ -1768,6 +1772,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler, return TRUE; case 0x39: /* SWC1 - MIPS I */ + UML_TEST(block, CPR032(COP0_Status), SR_COP1); // test [Status],SR_COP1 + UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], 1); // exh cop,1,Z UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_MOV(block, I1, FPR32(RTREG)); // mov i1,<cpr1_rt> UML_CALLH(block, *m_write32[m_core->mode >> 1]); // callh write32 @@ -1776,6 +1782,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler, return TRUE; case 0x3d: /* SDC1 - MIPS III */ + UML_TEST(block, CPR032(COP0_Status), SR_COP1); // test [Status],SR_COP1 + UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], 1); // exh cop,1,Z UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL UML_DMOV(block, I1, FPR64(RTREG)); // dmov i1,<cpr1_rt> UML_CALLH(block, *m_write64[m_core->mode >> 1]); // callh write64 |
