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author Miodrag Milanovic <mmicko@gmail.com>2011-10-08 18:03:57 +0000
committer Miodrag Milanovic <mmicko@gmail.com>2011-10-08 18:03:57 +0000
commitec6a340d1ddd5dafb9765d48e47aa99743959a55 (patch)
treeaaf4e491481d14dba7047b7a2a0eee4bdae2827b /src/emu
parentdb67f05d6fa08fdf669a28ae75957995432eaf55 (diff)
More interrupt work by Haze (no whatsnew)
Diffstat (limited to 'src/emu')
-rw-r--r--src/emu/cpu/sh4/sh3comn.c59
-rw-r--r--src/emu/cpu/sh4/sh3comn.h1
-rw-r--r--src/emu/cpu/sh4/sh4.c3
-rw-r--r--src/emu/cpu/sh4/sh4comn.c9
-rw-r--r--src/emu/cpu/sh4/sh4comn.h2
5 files changed, 68 insertions, 6 deletions
diff --git a/src/emu/cpu/sh4/sh3comn.c b/src/emu/cpu/sh4/sh3comn.c
index c9b9d9a90e3..0b2dc4bf443 100644
--- a/src/emu/cpu/sh4/sh3comn.c
+++ b/src/emu/cpu/sh4/sh3comn.c
@@ -153,6 +153,30 @@ READ32_HANDLER( sh3_internal_r )
break;
+ case IRR0_IRR1:
+ {
+ {
+ if (mem_mask & 0xff000000)
+ {
+ logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
+ return sh4->m_sh3internal_lower[offset];
+ }
+
+ if (mem_mask & 0x0000ff00)
+ {
+ logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR1)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
+ return sh4->m_sh3internal_lower[offset];
+ }
+
+ if (mem_mask & 0x00ff00ff);
+ {
+ fatalerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0/1 unused bits)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
+ }
+
+ }
+ }
+ break;
+
case PEDR_PFDR:
{
if (mem_mask & 0xffff0000)
@@ -224,8 +248,34 @@ WRITE32_HANDLER( sh3_internal_w )
switch (offset)
{
+ case IRR0_IRR1:
+ {
+ {
+ if (mem_mask & 0xff000000)
+ {
+ logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
+ // not sure if this is how we should clear lines in this core...
+ if (!(data & 0x01000000)) sh4_set_irq_line(sh4, 0, CLEAR_LINE);
+ if (!(data & 0x02000000)) sh4_set_irq_line(sh4, 1, CLEAR_LINE);
+ if (!(data & 0x04000000)) sh4_set_irq_line(sh4, 2, CLEAR_LINE);
+ if (!(data & 0x08000000)) sh4_set_irq_line(sh4, 3, CLEAR_LINE);
+
+ }
+ if (mem_mask & 0x0000ff00)
+ {
+ logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR1)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
+ }
+ if (mem_mask & 0x00ff00ff)
+ {
+ fatalerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0/1 unused bits)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
+ }
+ }
+ }
+ break;
+
case PINTER_IPRC:
{
+
if (mem_mask & 0xffff0000)
{
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PINTER)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
@@ -233,7 +283,14 @@ WRITE32_HANDLER( sh3_internal_w )
if (mem_mask & 0x0000ffff)
{
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IPRC)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
+ data &= 0xffff; mem_mask &= 0xffff;
+ COMBINE_DATA(&sh4->SH4_IPRC);
+ logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (IPRC)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
+ sh4->exception_priority[SH4_INTC_IRL0] = INTPRI((sh4->SH4_IPRC & 0x000f)>>0, SH4_INTC_IRL0);
+ sh4->exception_priority[SH4_INTC_IRL1] = INTPRI((sh4->SH4_IPRC & 0x00f0)>>4, SH4_INTC_IRL1);
+ sh4->exception_priority[SH4_INTC_IRL2] = INTPRI((sh4->SH4_IPRC & 0x0f00)>>8, SH4_INTC_IRL2);
+ sh4->exception_priority[SH4_INTC_IRL3] = INTPRI((sh4->SH4_IPRC & 0xf000)>>12,SH4_INTC_IRL3);
+ sh4_exception_recompute(sh4);
}
}
break;
diff --git a/src/emu/cpu/sh4/sh3comn.h b/src/emu/cpu/sh4/sh3comn.h
index 3c97fde5637..6c1271b68c2 100644
--- a/src/emu/cpu/sh4/sh3comn.h
+++ b/src/emu/cpu/sh4/sh3comn.h
@@ -9,6 +9,7 @@
#define SH3_LOWER_REGEND (0x07ffffff)
#define INTEVT2 ((0x4000000 - SH3_LOWER_REGBASE)/4)
+#define IRR0_IRR1 ((0x4000004 - SH3_LOWER_REGBASE)/4)
#define PINTER_IPRC ((0x4000014 - SH3_LOWER_REGBASE)/4)
#define PCCR_PDCR ((0x4000104 - SH3_LOWER_REGBASE)/4)
#define PECR_PFCR ((0x4000108 - SH3_LOWER_REGBASE)/4)
diff --git a/src/emu/cpu/sh4/sh4.c b/src/emu/cpu/sh4/sh4.c
index 4dc2ac67646..93735b5f9c2 100644
--- a/src/emu/cpu/sh4/sh4.c
+++ b/src/emu/cpu/sh4/sh4.c
@@ -1718,7 +1718,7 @@ INLINE void TRAPA(sh4_state *sh4, UINT32 i)
else /* SH3 */
{
sh4->m_sh3internal_upper[SH3_TRA_ADDR] = imm << 2;
- }
+ }
sh4->ssr = sh4->sr;
@@ -3548,6 +3548,7 @@ static CPU_INIT( sh4 )
device->save_item(NAME(sh4->SH4_IPRA));
+ device->save_item(NAME(sh4->SH4_IPRC));
diff --git a/src/emu/cpu/sh4/sh4comn.c b/src/emu/cpu/sh4/sh4comn.c
index 45c767eaecf..340e318555f 100644
--- a/src/emu/cpu/sh4/sh4comn.c
+++ b/src/emu/cpu/sh4/sh4comn.c
@@ -188,10 +188,11 @@ static const int sh3_intevt2_exception_codes[] =
-1, /* D */
-1, /* E */
- -1, /* SH4_INTC_IRL0 */
- -1, /* SH4_INTC_IRL1 */
- -1, /* SH4_INTC_IRL2 */
- -1, /* SH4_INTC_IRL3 */
+ 0x600, /* SH4_INTC_IRL0 */
+ 0x620, /* SH4_INTC_IRL1 */
+ 0x640, /* SH4_INTC_IRL2 */
+ 0x660, /* SH4_INTC_IRL3 */
+ /* todo: SH3 should have lines 4+5 too? */
-1, /* HUDI */
-1, /* SH4_INTC_GPOI */
diff --git a/src/emu/cpu/sh4/sh4comn.h b/src/emu/cpu/sh4/sh4comn.h
index 37bfdbaac20..76476a7202f 100644
--- a/src/emu/cpu/sh4/sh4comn.h
+++ b/src/emu/cpu/sh4/sh4comn.h
@@ -99,6 +99,8 @@ typedef struct
// INTC regs
UINT32 SH4_IPRA;
+ UINT32 SH4_IPRC;
+
// sh3 internal
UINT32 m_sh3internal_upper[0x3000/4];