diff options
author | 2011-09-30 03:33:36 +0000 | |
---|---|---|
committer | 2011-09-30 03:33:36 +0000 | |
commit | c67a422620c093027b7e68f24de5d10b52016831 (patch) | |
tree | bac17afb31d2182e270a329c480119e5658f3b23 /src/emu | |
parent | 259a42d69e210c6c1eaab02511d35bbfabed3109 (diff) |
m68k: preliminary support for ColdFire family and MCF5206E
Diffstat (limited to 'src/emu')
-rw-r--r-- | src/emu/cpu/m68000/m68000.h | 4 | ||||
-rw-r--r-- | src/emu/cpu/m68000/m68k_in.c | 1242 | ||||
-rw-r--r-- | src/emu/cpu/m68000/m68kcpu.c | 138 | ||||
-rw-r--r-- | src/emu/cpu/m68000/m68kcpu.h | 11 | ||||
-rw-r--r-- | src/emu/cpu/m68000/m68kdasm.c | 97 | ||||
-rw-r--r-- | src/emu/cpu/m68000/m68kmake.c | 48 | ||||
-rw-r--r-- | src/emu/cpu/m68000/m68kmmu.h | 87 |
7 files changed, 991 insertions, 636 deletions
diff --git a/src/emu/cpu/m68000/m68000.h b/src/emu/cpu/m68000/m68000.h index 2d28ac16312..7013d465aa6 100644 --- a/src/emu/cpu/m68000/m68000.h +++ b/src/emu/cpu/m68000/m68000.h @@ -34,7 +34,8 @@ enum M68K_CPU_TYPE_68LC040, M68K_CPU_TYPE_68040, M68K_CPU_TYPE_SCC68070, - M68K_CPU_TYPE_68340 + M68K_CPU_TYPE_68340, + M68K_CPU_TYPE_COLDFIRE }; // function codes @@ -105,6 +106,7 @@ DECLARE_LEGACY_CPU_DEVICE(M68LC040, m68lc040); DECLARE_LEGACY_CPU_DEVICE(M68040, m68040); DECLARE_LEGACY_CPU_DEVICE(SCC68070, scc68070); DECLARE_LEGACY_CPU_DEVICE(M68340, m68340); +DECLARE_LEGACY_CPU_DEVICE(MCF5206E, mcf5206e); void m68k_set_encrypted_opcode_range(device_t *device, offs_t start, offs_t end); diff --git a/src/emu/cpu/m68000/m68k_in.c b/src/emu/cpu/m68000/m68k_in.c index aadb1096a62..8775ab1a161 100644 --- a/src/emu/cpu/m68000/m68k_in.c +++ b/src/emu/cpu/m68000/m68k_in.c @@ -8,7 +8,7 @@ must fix: /* ======================================================================== */ /* * MUSASHI - * Version 4.80 + * Version 4.90 * * A portable Motorola M68xxx processor emulation engine. * Copyright Karl Stenerud. All rights reserved. @@ -122,7 +122,7 @@ M68KMAKE_TABLE_HEADER #include "m68kops.h" -#define NUM_CPU_TYPES 6 +#define NUM_CPU_TYPES 7 void (*m68ki_instruction_jump_table[NUM_CPU_TYPES][0x10000])(m68ki_cpu_core *m68k); /* opcode handler jump table */ unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */ @@ -344,530 +344,530 @@ cpu cycles: Base number of cycles required to execute this opcode on the */ - spec spec allowed ea mode 3 cpu cycles -name size proc ea bit pattern A+-DXWLdxI 0 1 2 3 4 2 000 010 020 030 040 340 comments -====== ==== ==== ==== ================ ========== = = = = = = === === === === === === ========== -M68KMAKE_TABLE_START -1010 0 . . 1010............ .......... U U U U U U 4 4 4 4 4 4 -1111 0 . . 1111............ .......... U U U U U U 4 4 4 4 4 4 -040fpu0 32 . . 11110010........ .......... . . . U U U . . . 0 0 0 -040fpu1 32 . . 11110011........ .......... . . . U U U . . . 0 0 0 -abcd 8 rr . 1100...100000... .......... U U U U U U 6 6 4 4 4 4 -abcd 8 mm ax7 1100111100001... .......... U U U U U U 18 18 16 16 16 16 -abcd 8 mm ay7 1100...100001111 .......... U U U U U U 18 18 16 16 16 16 -abcd 8 mm axy7 1100111100001111 .......... U U U U U U 18 18 16 16 16 16 -abcd 8 mm . 1100...100001... .......... U U U U U U 18 18 16 16 16 16 -add 8 er d 1101...000000... .......... U U U U U U 4 4 2 2 2 2 -add 8 er . 1101...000...... A+-DXWLdxI U U U U U U 4 4 2 2 2 2 -add 16 er d 1101...001000... .......... U U U U U U 4 4 2 2 2 2 -add 16 er a 1101...001001... .......... U U U U U U 4 4 2 2 2 2 -add 16 er . 1101...001...... A+-DXWLdxI U U U U U U 4 4 2 2 2 2 -add 32 er d 1101...010000... .......... U U U U U U 6 6 2 2 2 2 -add 32 er a 1101...010001... .......... U U U U U U 6 6 2 2 2 2 -add 32 er . 1101...010...... A+-DXWLdxI U U U U U U 6 6 2 2 2 2 -add 8 re . 1101...100...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -add 16 re . 1101...101...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -add 32 re . 1101...110...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -adda 16 . d 1101...011000... .......... U U U U U U 8 8 2 2 2 2 -adda 16 . a 1101...011001... .......... U U U U U U 8 8 2 2 2 2 -adda 16 . . 1101...011...... A+-DXWLdxI U U U U U U 8 8 2 2 2 2 -adda 32 . d 1101...111000... .......... U U U U U U 6 6 2 2 2 2 -adda 32 . a 1101...111001... .......... U U U U U U 6 6 2 2 2 2 -adda 32 . . 1101...111...... A+-DXWLdxI U U U U U U 6 6 2 2 2 2 -addi 8 . d 0000011000000... .......... U U U U U U 8 8 2 2 2 2 -addi 8 . . 0000011000...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -addi 16 . d 0000011001000... .......... U U U U U U 8 8 2 2 2 2 -addi 16 . . 0000011001...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -addi 32 . d 0000011010000... .......... U U U U U U 16 14 2 2 2 2 -addi 32 . . 0000011010...... A+-DXWL... U U U U U U 20 20 4 4 4 4 -addq 8 . d 0101...000000... .......... U U U U U U 4 4 2 2 2 2 -addq 8 . . 0101...000...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -addq 16 . d 0101...001000... .......... U U U U U U 4 4 2 2 2 2 -addq 16 . a 0101...001001... .......... U U U U U U 4 4 2 2 2 2 -addq 16 . . 0101...001...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -addq 32 . d 0101...010000... .......... U U U U U U 8 8 2 2 2 2 -addq 32 . a 0101...010001... .......... U U U U U U 8 8 2 2 2 2 -addq 32 . . 0101...010...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -addx 8 rr . 1101...100000... .......... U U U U U U 4 4 2 2 2 2 -addx 16 rr . 1101...101000... .......... U U U U U U 4 4 2 2 2 2 -addx 32 rr . 1101...110000... .......... U U U U U U 8 6 2 2 2 2 -addx 8 mm ax7 1101111100001... .......... U U U U U U 18 18 12 12 12 12 -addx 8 mm ay7 1101...100001111 .......... U U U U U U 18 18 12 12 12 12 -addx 8 mm axy7 1101111100001111 .......... U U U U U U 18 18 12 12 12 12 -addx 8 mm . 1101...100001... .......... U U U U U U 18 18 12 12 12 12 -addx 16 mm . 1101...101001... .......... U U U U U U 18 18 12 12 12 12 -addx 32 mm . 1101...110001... .......... U U U U U U 30 30 12 12 12 12 -and 8 er d 1100...000000... .......... U U U U U U 4 4 2 2 2 2 -and 8 er . 1100...000...... A+-DXWLdxI U U U U U U 4 4 2 2 2 2 -and 16 er d 1100...001000... .......... U U U U U U 4 4 2 2 2 2 -and 16 er . 1100...001...... A+-DXWLdxI U U U U U U 4 4 2 2 2 2 -and 32 er d 1100...010000... .......... U U U U U U 6 6 2 2 2 2 -and 32 er . 1100...010...... A+-DXWLdxI U U U U U U 6 6 2 2 2 2 -and 8 re . 1100...100...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -and 16 re . 1100...101...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -and 32 re . 1100...110...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -andi 16 toc . 0000001000111100 .......... U U U U U U 20 16 12 12 12 12 -andi 16 tos . 0000001001111100 .......... S S S S S S 20 16 12 12 12 12 -andi 8 . d 0000001000000... .......... U U U U U U 8 8 2 2 2 2 -andi 8 . . 0000001000...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -andi 16 . d 0000001001000... .......... U U U U U U 8 8 2 2 2 2 -andi 16 . . 0000001001...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -andi 32 . d 0000001010000... .......... U U U U U U 14 14 2 2 2 2 -andi 32 . . 0000001010...... A+-DXWL... U U U U U U 20 20 4 4 4 4 -asr 8 s . 1110...000000... .......... U U U U U U 6 6 6 6 6 6 -asr 16 s . 1110...001000... .......... U U U U U U 6 6 6 6 6 6 -asr 32 s . 1110...010000... .......... U U U U U U 8 8 6 6 6 6 -asr 8 r . 1110...000100... .......... U U U U U U 6 6 6 6 6 6 -asr 16 r . 1110...001100... .......... U U U U U U 6 6 6 6 6 6 -asr 32 r . 1110...010100... .......... U U U U U U 8 8 6 6 6 6 -asr 16 . . 1110000011...... A+-DXWL... U U U U U U 8 8 5 5 5 5 -asl 8 s . 1110...100000... .......... U U U U U U 6 6 8 8 8 8 -asl 16 s . 1110...101000... .......... U U U U U U 6 6 8 8 8 8 -asl 32 s . 1110...110000... .......... U U U U U U 8 8 8 8 8 8 -asl 8 r . 1110...100100... .......... U U U U U U 6 6 8 8 8 8 -asl 16 r . 1110...101100... .......... U U U U U U 6 6 8 8 8 8 -asl 32 r . 1110...110100... .......... U U U U U U 8 8 8 8 8 8 -asl 16 . . 1110000111...... A+-DXWL... U U U U U U 8 8 6 6 6 6 -bcc 8 . . 0110............ .......... U U U U U U 10 10 6 6 6 6 -bcc 16 . . 0110....00000000 .......... U U U U U U 10 10 6 6 6 6 -bcc 32 . . 0110....11111111 .......... U U U U U U 10 10 6 6 6 6 -bchg 8 r . 0000...101...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -bchg 32 r d 0000...101000... .......... U U U U U U 8 8 4 4 4 4 -bchg 8 s . 0000100001...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -bchg 32 s d 0000100001000... .......... U U U U U U 12 12 4 4 4 4 -bclr 8 r . 0000...110...... A+-DXWL... U U U U U U 8 10 4 4 4 4 -bclr 32 r d 0000...110000... .......... U U U U U U 10 10 4 4 4 4 -bclr 8 s . 0000100010...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -bclr 32 s d 0000100010000... .......... U U U U U U 14 14 4 4 4 4 -bfchg 32 . d 1110101011000... .......... . . U U U U . . 12 12 12 12 timing not quite correct -bfchg 32 . . 1110101011...... A..DXWL... . . U U U U . . 20 20 20 20 -bfclr 32 . d 1110110011000... .......... . . U U U U . . 12 12 12 12 -bfclr 32 . . 1110110011...... A..DXWL... . . U U U U . . 20 20 20 20 -bfexts 32 . d 1110101111000... .......... . . U U U U . . 8 8 8 8 -bfexts 32 . . 1110101111...... A..DXWLdx. . . U U U U . . 15 15 15 15 -bfextu 32 . d 1110100111000... .......... . . U U U U . . 8 8 8 8 -bfextu 32 . . 1110100111...... A..DXWLdx. . . U U U U . . 15 15 15 15 -bfffo 32 . d 1110110111000... .......... . . U U U U . . 18 18 18 18 -bfffo 32 . . 1110110111...... A..DXWLdx. . . U U U U . . 28 28 28 28 -bfins 32 . d 1110111111000... .......... . . U U U U . . 10 10 10 10 -bfins 32 . . 1110111111...... A..DXWL... . . U U U U . . 17 17 17 17 -bfset 32 . d 1110111011000... .......... . . U U U U . . 12 12 12 12 -bfset 32 . . 1110111011...... A..DXWL... . . U U U U . . 20 20 20 20 -bftst 32 . d 1110100011000... .......... . . U U U U . . 6 6 6 6 -bftst 32 . . 1110100011...... A..DXWLdx. . . U U U U . . 13 13 13 13 -bkpt 0 . . 0100100001001... .......... . U U U U U . 10 10 10 10 10 -bra 8 . . 01100000........ .......... U U U U U U 10 10 10 10 10 10 -bra 16 . . 0110000000000000 .......... U U U U U U 10 10 10 10 10 10 -bra 32 . . 0110000011111111 .......... U U U U U U 10 10 10 10 10 10 -bset 32 r d 0000...111000... .......... U U U U U U 8 8 4 4 4 4 -bset 8 r . 0000...111...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -bset 8 s . 0000100011...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -bset 32 s d 0000100011000... .......... U U U U U U 12 12 4 4 4 4 -bsr 8 . . 01100001........ .......... U U U U U U 18 18 7 7 7 7 -bsr 16 . . 0110000100000000 .......... U U U U U U 18 18 7 7 7 7 -bsr 32 . . 0110000111111111 .......... U U U U U U 18 18 7 7 7 7 -btst 8 r . 0000...100...... A+-DXWLdxI U U U U U U 4 4 4 4 4 4 -btst 32 r d 0000...100000... .......... U U U U U U 6 6 4 4 4 4 -btst 8 s . 0000100000...... A+-DXWLdx. U U U U U U 8 8 4 4 4 4 -btst 32 s d 0000100000000... .......... U U U U U U 10 10 4 4 4 4 -callm 32 . . 0000011011...... A..DXWLdx. . . U U U U . . 60 60 60 60 not properly emulated -cas 8 . . 0000101011...... A+-DXWL... . . U U U U . . 12 12 12 12 -cas 16 . . 0000110011...... A+-DXWL... . . U U U U . . 12 12 12 12 -cas 32 . . 0000111011...... A+-DXWL... . . U U U U . . 12 12 12 12 -cas2 16 . . 0000110011111100 .......... . . U U U U . . 12 12 12 12 -cas2 32 . . 0000111011111100 .......... . . U U U U . . 12 12 12 12 -chk 16 . d 0100...110000... .......... U U U U U U 10 8 8 8 8 8 -chk 16 . . 0100...110...... A+-DXWLdxI U U U U U U 10 8 8 8 8 8 -chk 32 . d 0100...100000... .......... . . U U U U . . 8 8 8 8 -chk 32 . . 0100...100...... A+-DXWLdxI . . U U U U . . 8 8 8 8 -chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U U U . . 23 23 23 23 -chk2cmp2 8 . pcix 0000000011111011 .......... . . U U U U . . 23 23 23 23 -chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U U U . . 18 18 18 18 -chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U U U . . 23 23 23 23 -chk2cmp2 16 . pcix 0000001011111011 .......... . . U U U U . . 23 23 23 23 -chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U U U . . 18 18 18 18 -chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U U U . . 23 23 23 23 -chk2cmp2 32 . pcix 0000010011111011 .......... . . U U U U . . 23 23 23 23 -chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U U U . . 18 18 18 18 -clr 8 . d 0100001000000... .......... U U U U U U 4 4 2 2 2 2 -clr 8 . . 0100001000...... A+-DXWL... U U U U U U 8 4 4 4 4 4 -clr 16 . d 0100001001000... .......... U U U U U U 4 4 2 2 2 2 -clr 16 . . 0100001001...... A+-DXWL... U U U U U U 8 4 4 4 4 4 -clr 32 . d 0100001010000... .......... U U U U U U 6 6 2 2 2 2 -clr 32 . . 0100001010...... A+-DXWL... U U U U U U 12 6 4 4 4 4 -cmp 8 . d 1011...000000... .......... U U U U U U 4 4 2 2 2 2 -cmp 8 . . 1011...000...... A+-DXWLdxI U U U U U U 4 4 2 2 2 2 -cmp 16 . d 1011...001000... .......... U U U U U U 4 4 2 2 2 2 -cmp 16 . a 1011...001001... .......... U U U U U U 4 4 2 2 2 2 -cmp 16 . . 1011...001...... A+-DXWLdxI U U U U U U 4 4 2 2 2 2 -cmp 32 . d 1011...010000... .......... U U U U U U 6 6 2 2 2 2 -cmp 32 . a 1011...010001... .......... U U U U U U 6 6 2 2 2 2 -cmp 32 . . 1011...010...... A+-DXWLdxI U U U U U U 6 6 2 2 2 2 -cmpa 16 . d 1011...011000... .......... U U U U U U 6 6 4 4 4 4 -cmpa 16 . a 1011...011001... .......... U U U U U U 6 6 4 4 4 4 -cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U U U 6 6 4 4 4 4 -cmpa 32 . d 1011...111000... .......... U U U U U U 6 6 4 4 4 4 -cmpa 32 . a 1011...111001... .......... U U U U U U 6 6 4 4 4 4 -cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U U U 6 6 4 4 4 4 -cmpi 8 . d 0000110000000... .......... U U U U U U 8 8 2 2 2 2 -cmpi 8 . . 0000110000...... A+-DXWL... U U U U U U 8 8 2 2 2 2 -cmpi 8 . pcdi 0000110000111010 .......... . . U U U U . . 7 7 7 7 -cmpi 8 . pcix 0000110000111011 .......... . . U U U U . . 9 9 9 9 -cmpi 16 . d 0000110001000... .......... U U U U U U 8 8 2 2 2 2 -cmpi 16 . . 0000110001...... A+-DXWL... U U U U U U 8 8 2 2 2 2 -cmpi 16 . pcdi 0000110001111010 .......... . . U U U U . . 7 7 7 7 -cmpi 16 . pcix 0000110001111011 .......... . . U U U U . . 9 9 9 9 -cmpi 32 . d 0000110010000... .......... U U U U U U 14 12 2 2 2 2 -cmpi 32 . . 0000110010...... A+-DXWL... U U U U U U 12 12 2 2 2 2 -cmpi 32 . pcdi 0000110010111010 .......... . . U U U U . . 7 7 7 7 -cmpi 32 . pcix 0000110010111011 .......... . . U U U U . . 9 9 9 9 -cmpm 8 . ax7 1011111100001... .......... U U U U U U 12 12 9 9 9 9 -cmpm 8 . ay7 1011...100001111 .......... U U U U U U 12 12 9 9 9 9 -cmpm 8 . axy7 1011111100001111 .......... U U U U U U 12 12 9 9 9 9 -cmpm 8 . . 1011...100001... .......... U U U U U U 12 12 9 9 9 9 -cmpm 16 . . 1011...101001... .......... U U U U U U 12 12 9 9 9 9 -cmpm 32 . . 1011...110001... .......... U U U U U U 20 20 9 9 9 9 -cinv 32 . . 11110100..0..... .......... . . . . U . . . . . 16 . 040 only -cpush 32 . . 11110100..1..... .......... . . . . U . . . . . 16 . 040 only -cpbcc 32 . . 1111...01....... .......... . . U U . . . . 4 4 . . cpXXX only for 020/030, not on 040! -cpdbcc 32 . . 1111...001001... .......... . . U U . . . . 4 4 . . -cpgen 32 . . 1111...000...... .......... . . U U . . . . 4 4 . . -cpscc 32 . . 1111...001...... .......... . . U U . . . . 4 4 . . -cptrapcc 32 . . 1111...001111... .......... . . U U . . . . 4 4 . . -dbt 16 . . 0101000011001... .......... U U U U U U 12 12 6 6 6 6 -dbf 16 . . 0101000111001... .......... U U U U U U 12 12 6 6 6 6 -dbcc 16 . . 0101....11001... .......... U U U U U U 12 12 6 6 6 6 -divs 16 . d 1000...111000... .......... U U U U U U 158 122 56 56 56 56 -divs 16 . . 1000...111...... A+-DXWLdxI U U U U U U 158 122 56 56 56 56 -divu 16 . d 1000...011000... .......... U U U U U U 140 108 44 44 44 44 -divu 16 . . 1000...011...... A+-DXWLdxI U U U U U U 140 108 44 44 44 44 -divl 32 . d 0100110001000... .......... . . U U U U . . 84 84 84 84 -divl 32 . . 0100110001...... A+-DXWLdxI . . U U U U . . 84 84 84 84 -eor 8 . d 1011...100000... .......... U U U U U U 4 4 2 2 2 2 -eor 8 . . 1011...100...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -eor 16 . d 1011...101000... .......... U U U U U U 4 4 2 2 2 2 -eor 16 . . 1011...101...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -eor 32 . d 1011...110000... .......... U U U U U U 8 6 2 2 2 2 -eor 32 . . 1011...110...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -eori 16 toc . 0000101000111100 .......... U U U U U U 20 16 12 12 12 12 -eori 16 tos . 0000101001111100 .......... S S S S S S 20 16 12 12 12 12 -eori 8 . d 0000101000000... .......... U U U U U U 8 8 2 2 2 2 -eori 8 . . 0000101000...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -eori 16 . d 0000101001000... .......... U U U U U U 8 8 2 2 2 2 -eori 16 . . 0000101001...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -eori 32 . d 0000101010000... .......... U U U U U U 16 14 2 2 2 2 -eori 32 . . 0000101010...... A+-DXWL... U U U U U U 20 20 4 4 4 4 -exg 32 dd . 1100...101000... .......... U U U U U U 6 6 2 2 2 2 -exg 32 aa . 1100...101001... .......... U U U U U U 6 6 2 2 2 2 -exg 32 da . 1100...110001... .......... U U U U U U 6 6 2 2 2 2 -ext 16 . . 0100100010000... .......... U U U U U U 4 4 4 4 4 4 -ext 32 . . 0100100011000... .......... U U U U U U 4 4 4 4 4 4 -extb 32 . . 0100100111000... .......... . . U U U U . . 4 4 4 4 -illegal 0 . . 0100101011111100 .......... U U U U U U 4 4 4 4 4 4 -jmp 32 . . 0100111011...... A..DXWLdx. U U U U U U 4 4 0 0 0 0 -jsr 32 . . 0100111010...... A..DXWLdx. U U U U U U 12 12 0 0 0 0 -lea 32 . . 0100...111...... A..DXWLdx. U U U U U U 0 0 2 2 2 2 -link 16 . a7 0100111001010111 .......... U U U U U U 16 16 5 5 5 5 -link 16 . . 0100111001010... .......... U U U U U U 16 16 5 5 5 5 -link 32 . a7 0100100000001111 .......... . . U U U U . . 6 6 6 6 -link 32 . . 0100100000001... .......... . . U U U U . . 6 6 6 6 -lsr 8 s . 1110...000001... .......... U U U U U U 6 6 4 4 4 4 -lsr 16 s . 1110...001001... .......... U U U U U U 6 6 4 4 4 4 -lsr 32 s . 1110...010001... .......... U U U U U U 8 8 4 4 4 4 -lsr 8 r . 1110...000101... .......... U U U U U U 6 6 6 6 6 6 -lsr 16 r . 1110...001101... .......... U U U U U U 6 6 6 6 6 6 -lsr 32 r . 1110...010101... .......... U U U U U U 8 8 6 6 6 6 -lsr 16 . . 1110001011...... A+-DXWL... U U U U U U 8 8 5 5 5 5 -lsl 8 s . 1110...100001... .......... U U U U U U 6 6 4 4 4 4 -lsl 16 s . 1110...101001... .......... U U U U U U 6 6 4 4 4 4 -lsl 32 s . 1110...110001... .......... U U U U U U 8 8 4 4 4 4 -lsl 8 r . 1110...100101... .......... U U U U U U 6 6 6 6 6 6 -lsl 16 r . 1110...101101... .......... U U U U U U 6 6 6 6 6 6 -lsl 32 r . 1110...110101... .......... U U U U U U 8 8 6 6 6 6 -lsl 16 . . 1110001111...... A+-DXWL... U U U U U U 8 8 5 5 5 5 -move 8 d d 0001...000000... .......... U U U U U U 4 4 2 2 2 2 -move 8 d . 0001...000...... A+-DXWLdxI U U U U U U 4 4 2 2 2 2 -move 8 ai d 0001...010000... .......... U U U U U U 8 8 4 4 4 4 -move 8 ai . 0001...010...... A+-DXWLdxI U U U U U U 8 8 4 4 4 4 -move 8 pi d 0001...011000... .......... U U U U U U 8 8 4 4 4 4 -move 8 pi . 0001...011...... A+-DXWLdxI U U U U U U 8 8 4 4 4 4 -move 8 pi7 d 0001111011000... .......... U U U U U U 8 8 4 4 4 4 -move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U U U 8 8 4 4 4 4 -move 8 pd d 0001...100000... .......... U U U U U U 8 8 5 5 5 5 -move 8 pd . 0001...100...... A+-DXWLdxI U U U U U U 8 8 5 5 5 5 -move 8 pd7 d 0001111100000... .......... U U U U U U 8 8 5 5 5 5 -move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U U U 8 8 5 5 5 5 -move 8 di d 0001...101000... .......... U U U U U U 12 12 5 5 5 5 -move 8 di . 0001...101...... A+-DXWLdxI U U U U U U 12 12 5 5 5 5 -move 8 ix d 0001...110000... .......... U U U U U U 14 14 7 7 7 7 -move 8 ix . 0001...110...... A+-DXWLdxI U U U U U U 14 14 7 7 7 7 -move 8 aw d 0001000111000... .......... U U U U U U 12 12 4 4 4 4 -move 8 aw . 0001000111...... A+-DXWLdxI U U U U U U 12 12 4 4 4 4 -move 8 al d 0001001111000... .......... U U U U U U 16 16 6 6 6 6 -move 8 al . 0001001111...... A+-DXWLdxI U U U U U U 16 16 6 6 6 6 -move 16 d d 0011...000000... .......... U U U U U U 4 4 2 2 2 2 -move 16 d a 0011...000001... .......... U U U U U U 4 4 2 2 2 2 -move 16 d . 0011...000...... A+-DXWLdxI U U U U U U 4 4 2 2 2 2 -move 16 ai d 0011...010000... .......... U U U U U U 8 8 4 4 4 4 -move 16 ai a 0011...010001... .......... U U U U U U 8 8 4 4 4 4 -move 16 ai . 0011...010...... A+-DXWLdxI U U U U U U 8 8 4 4 4 4 -move 16 pi d 0011...011000... .......... U U U U U U 8 8 4 4 4 4 -move 16 pi a 0011...011001... .......... U U U U U U 8 8 4 4 4 4 -move 16 pi . 0011...011...... A+-DXWLdxI U U U U U U 8 8 4 4 4 4 -move 16 pd d 0011...100000... .......... U U U U U U 8 8 5 5 5 5 -move 16 pd a 0011...100001... .......... U U U U U U 8 8 5 5 5 5 -move 16 pd . 0011...100...... A+-DXWLdxI U U U U U U 8 8 5 5 5 5 -move 16 di d 0011...101000... .......... U U U U U U 12 12 5 5 5 5 -move 16 di a 0011...101001... .......... U U U U U U 12 12 5 5 5 5 -move 16 di . 0011...101...... A+-DXWLdxI U U U U U U 12 12 5 5 5 5 -move 16 ix d 0011...110000... .......... U U U U U U 14 14 7 7 7 7 -move 16 ix a 0011...110001... .......... U U U U U U 14 14 7 7 7 7 -move 16 ix . 0011...110...... A+-DXWLdxI U U U U U U 14 14 7 7 7 7 -move 16 aw d 0011000111000... .......... U U U U U U 12 12 4 4 4 4 -move 16 aw a 0011000111001... .......... U U U U U U 12 12 4 4 4 4 -move 16 aw . 0011000111...... A+-DXWLdxI U U U U U U 12 12 4 4 4 4 -move 16 al d 0011001111000... .......... U U U U U U 16 16 6 6 6 6 -move 16 al a 0011001111001... .......... U U U U U U 16 16 6 6 6 6 -move 16 al . 0011001111...... A+-DXWLdxI U U U U U U 16 16 6 6 6 6 -move 32 d d 0010...000000... .......... U U U U U U 4 4 2 2 2 2 -move 32 d a 0010...000001... .......... U U U U U U 4 4 2 2 2 2 -move 32 d . 0010...000...... A+-DXWLdxI U U U U U U 4 4 2 2 2 2 -move 32 ai d 0010...010000... .......... U U U U U U 12 12 4 4 4 4 -move 32 ai a 0010...010001... .......... U U U U U U 12 12 4 4 4 4 -move 32 ai . 0010...010...... A+-DXWLdxI U U U U U U 12 12 4 4 4 4 -move 32 pi d 0010...011000... .......... U U U U U U 12 12 4 4 4 4 -move 32 pi a 0010...011001... .......... U U U U U U 12 12 4 4 4 4 -move 32 pi . 0010...011...... A+-DXWLdxI U U U U U U 12 12 4 4 4 4 -move 32 pd d 0010...100000... .......... U U U U U U 12 14 5 5 5 5 -move 32 pd a 0010...100001... .......... U U U U U U 12 14 5 5 5 5 -move 32 pd . 0010...100...... A+-DXWLdxI U U U U U U 12 14 5 5 5 5 -move 32 di d 0010...101000... .......... U U U U U U 16 16 5 5 5 5 -move 32 di a 0010...101001... .......... U U U U U U 16 16 5 5 5 5 -move 32 di . 0010...101...... A+-DXWLdxI U U U U U U 16 16 5 5 5 5 -move 32 ix d 0010...110000... .......... U U U U U U 18 18 7 7 7 7 -move 32 ix a 0010...110001... .......... U U U U U U 18 18 7 7 7 7 -move 32 ix . 0010...110...... A+-DXWLdxI U U U U U U 18 18 7 7 7 7 -move 32 aw d 0010000111000... .......... U U U U U U 16 16 4 4 4 4 -move 32 aw a 0010000111001... .......... U U U U U U 16 16 4 4 4 4 -move 32 aw . 0010000111...... A+-DXWLdxI U U U U U U 16 16 4 4 4 4 -move 32 al d 0010001111000... .......... U U U U U U 20 20 6 6 6 6 -move 32 al a 0010001111001... .......... U U U U U U 20 20 6 6 6 6 -move 32 al . 0010001111...... A+-DXWLdxI U U U U U U 20 20 6 6 6 6 -movea 16 . d 0011...001000... .......... U U U U U U 4 4 2 2 2 2 -movea 16 . a 0011...001001... .......... U U U U U U 4 4 2 2 2 2 -movea 16 . . 0011...001...... A+-DXWLdxI U U U U U U 4 4 2 2 2 2 -movea 32 . d 0010...001000... .......... U U U U U U 4 4 2 2 2 2 -movea 32 . a 0010...001001... .......... U U U U U U 4 4 2 2 2 2 -movea 32 . . 0010...001...... A+-DXWLdxI U U U U U U 4 4 2 2 2 2 -move 16 frc d 0100001011000... .......... . U U U U U . 4 4 4 4 4 -move 16 frc . 0100001011...... A+-DXWL... . U U U U U . 8 4 4 4 4 -move 16 toc d 0100010011000... .......... U U U U U U 12 12 4 4 4 4 -move 16 toc . 0100010011...... A+-DXWLdxI U U U U U U 12 12 4 4 4 4 -move 16 frs d 0100000011000... .......... U S S S S S 6 4 8 8 8 8 U only for 000 -move 16 frs . 0100000011...... A+-DXWL... U S S S S S 8 8 8 8 8 8 U only for 000 -move 16 tos d 0100011011000... .......... S S S S S S 12 12 8 8 8 8 -move 16 tos . 0100011011...... A+-DXWLdxI S S S S S S 12 12 8 8 8 8 -move 32 fru . 0100111001101... .......... S S S S S S 4 6 2 2 2 2 -move 32 tou . 0100111001100... .......... S S S S S S 4 6 2 2 2 2 -movec 32 cr . 0100111001111010 .......... . S S S S S . 12 6 6 6 6 -movec 32 rc . 0100111001111011 .......... . S S S S S . 10 12 12 12 12 -movem 16 re pd 0100100010100... .......... U U U U U U 8 8 4 4 4 4 -movem 16 re . 0100100010...... A..DXWL... U U U U U U 8 8 4 4 4 4 -movem 32 re pd 0100100011100... .......... U U U U U U 8 8 4 4 4 4 -movem 32 re . 0100100011...... A..DXWL... U U U U U U 8 8 4 4 4 4 -movem 16 er pi 0100110010011... .......... U U U U U U 12 12 8 8 8 8 -movem 16 er pcdi 0100110010111010 .......... U U U U U U 16 16 9 9 9 9 -movem 16 er pcix 0100110010111011 .......... U U U U U U 18 18 11 11 11 11 -movem 16 er . 0100110010...... A..DXWL... U U U U U U 12 12 8 8 8 8 -movem 32 er pi 0100110011011... .......... U U U U U U 12 12 8 8 8 8 -movem 32 er pcdi 0100110011111010 .......... U U U U U U 16 16 9 9 9 9 -movem 32 er pcix 0100110011111011 .......... U U U U U U 18 18 11 11 11 11 -movem 32 er . 0100110011...... A..DXWL... U U U U U U 12 12 8 8 8 8 -movep 16 er . 0000...100001... .......... U U U U U U 16 16 12 12 12 12 -movep 32 er . 0000...101001... .......... U U U U U U 24 24 18 18 18 18 -movep 16 re . 0000...110001... .......... U U U U U U 16 16 11 11 11 11 -movep 32 re . 0000...111001... .......... U U U U U U 24 24 17 17 17 17 -moveq 32 . . 0111...0........ .......... U U U U U U 4 4 2 2 2 2 -moves 8 . . 0000111000...... A+-DXWL... . S S S S S . 14 5 5 5 5 -moves 16 . . 0000111001...... A+-DXWL... . S S S S S . 14 5 5 5 5 -moves 32 . . 0000111010...... A+-DXWL... . S S S S S . 16 5 5 5 5 -move16 32 . . 1111011000100... .......... . . . . U U . . . . 4 4 TODO: correct timing -muls 16 . d 1100...111000... .......... U U U U U U 54 32 27 27 27 27 -muls 16 . . 1100...111...... A+-DXWLdxI U U U U U U 54 32 27 27 27 27 -mulu 16 . d 1100...011000... .......... U U U U U U 54 30 27 27 27 27 -mulu 16 . . 1100...011...... A+-DXWLdxI U U U U U U 54 30 27 27 27 27 -mull 32 . d 0100110000000... .......... . . U U U U . . 43 43 43 43 -mull 32 . . 0100110000...... A+-DXWLdxI . . U U U U . . 43 43 43 43 -nbcd 8 . d 0100100000000... .......... U U U U U U 6 6 6 6 6 6 -nbcd 8 . . 0100100000...... A+-DXWL... U U U U U U 8 8 6 6 6 6 -neg 8 . d 0100010000000... .......... U U U U U U 4 4 2 2 2 2 -neg 8 . . 0100010000...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -neg 16 . d 0100010001000... .......... U U U U U U 4 4 2 2 2 2 -neg 16 . . 0100010001...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -neg 32 . d 0100010010000... .......... U U U U U U 6 6 2 2 2 2 -neg 32 . . 0100010010...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -negx 8 . d 0100000000000... .......... U U U U U U 4 4 2 2 2 2 -negx 8 . . 0100000000...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -negx 16 . d 0100000001000... .......... U U U U U U 4 4 2 2 2 2 -negx 16 . . 0100000001...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -negx 32 . d 0100000010000... .......... U U U U U U 6 6 2 2 2 2 -negx 32 . . 0100000010...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -nop 0 . . 0100111001110001 .......... U U U U U U 4 4 2 2 2 2 -not 8 . d 0100011000000... .......... U U U U U U 4 4 2 2 2 2 -not 8 . . 0100011000...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -not 16 . d 0100011001000... .......... U U U U U U 4 4 2 2 2 2 -not 16 . . 0100011001...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -not 32 . d 0100011010000... .......... U U U U U U 6 6 2 2 2 2 -not 32 . . 0100011010...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -or 8 er d 1000...000000... .......... U U U U U U 4 4 2 2 2 2 -or 8 er . 1000...000...... A+-DXWLdxI U U U U U U 4 4 2 2 2 2 -or 16 er d 1000...001000... .......... U U U U U U 4 4 2 2 2 2 -or 16 er . 1000...001...... A+-DXWLdxI U U U U U U 4 4 2 2 2 2 -or 32 er d 1000...010000... .......... U U U U U U 6 6 2 2 2 2 -or 32 er . 1000...010...... A+-DXWLdxI U U U U U U 6 6 2 2 2 2 -or 8 re . 1000...100...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -or 16 re . 1000...101...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -or 32 re . 1000...110...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -ori 16 toc . 0000000000111100 .......... U U U U U U 20 16 12 12 12 12 -ori 16 tos . 0000000001111100 .......... S S S S S S 20 16 12 12 12 12 -ori 8 . d 0000000000000... .......... U U U U U U 8 8 2 2 2 2 -ori 8 . . 0000000000...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -ori 16 . d 0000000001000... .......... U U U U U U 8 8 2 2 2 2 -ori 16 . . 0000000001...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -ori 32 . d 0000000010000... .......... U U U U U U 16 14 2 2 2 2 -ori 32 . . 0000000010...... A+-DXWL... U U U U U U 20 20 4 4 4 4 -pack 16 rr . 1000...101000... .......... . . U U U U . . 6 6 6 6 -pack 16 mm ax7 1000111101001... .......... . . U U U U . . 13 13 13 13 -pack 16 mm ay7 1000...101001111 .......... . . U U U U . . 13 13 13 13 -pack 16 mm axy7 1000111101001111 .......... . . U U U U . . 13 13 13 13 -pack 16 mm . 1000...101001... .......... . . U U U U . . 13 13 13 13 -pea 32 . . 0100100001...... A..DXWLdx. U U U U U U 6 6 5 5 5 5 -pflush 32 . . 1111010100011000 .......... . . . . S S . . . . 4 4 TODO: correct timing -pmmu 32 . . 1111000......... .......... . . S S S S . . 8 8 8 8 -reset 0 . . 0100111001110000 .......... S S S S S S 0 0 0 0 0 0 -ror 8 s . 1110...000011... .......... U U U U U U 6 6 8 8 8 8 -ror 16 s . 1110...001011... .......... U U U U U U 6 6 8 8 8 8 -ror 32 s . 1110...010011... .......... U U U U U U 8 8 8 8 8 8 -ror 8 r . 1110...000111... .......... U U U U U U 6 6 8 8 8 8 -ror 16 r . 1110...001111... .......... U U U U U U 6 6 8 8 8 8 -ror 32 r . 1110...010111... .......... U U U U U U 8 8 8 8 8 8 -ror 16 . . 1110011011...... A+-DXWL... U U U U U U 8 8 7 7 7 7 -rol 8 s . 1110...100011... .......... U U U U U U 6 6 8 8 8 8 -rol 16 s . 1110...101011... .......... U U U U U U 6 6 8 8 8 8 -rol 32 s . 1110...110011... .......... U U U U U U 8 8 8 8 8 8 -rol 8 r . 1110...100111... .......... U U U U U U 6 6 8 8 8 8 -rol 16 r . 1110...101111... .......... U U U U U U 6 6 8 8 8 8 -rol 32 r . 1110...110111... .......... U U U U U U 8 8 8 8 8 8 -rol 16 . . 1110011111...... A+-DXWL... U U U U U U 8 8 7 7 7 7 -roxr 8 s . 1110...000010... .......... U U U U U U 6 6 12 12 12 12 -roxr 16 s . 1110...001010... .......... U U U U U U 6 6 12 12 12 12 -roxr 32 s . 1110...010010... .......... U U U U U U 8 8 12 12 12 12 -roxr 8 r . 1110...000110... .......... U U U U U U 6 6 12 12 12 12 -roxr 16 r . 1110...001110... .......... U U U U U U 6 6 12 12 12 12 -roxr 32 r . 1110...010110... .......... U U U U U U 8 8 12 12 12 12 -roxr 16 . . 1110010011...... A+-DXWL... U U U U U U 8 8 5 5 5 5 -roxl 8 s . 1110...100010... .......... U U U U U U 6 6 12 12 12 12 -roxl 16 s . 1110...101010... .......... U U U U U U 6 6 12 12 12 12 -roxl 32 s . 1110...110010... .......... U U U U U U 8 8 12 12 12 12 -roxl 8 r . 1110...100110... .......... U U U U U U 6 6 12 12 12 12 -roxl 16 r . 1110...101110... .......... U U U U U U 6 6 12 12 12 12 -roxl 32 r . 1110...110110... .......... U U U U U U 8 8 12 12 12 12 -roxl 16 . . 1110010111...... A+-DXWL... U U U U U U 8 8 5 5 5 5 -rtd 32 . . 0100111001110100 .......... . U U U U U . 16 10 10 10 10 -rte 32 . . 0100111001110011 .......... S S S S S S 20 24 20 20 20 20 bus fault not emulated -rtm 32 . . 000001101100.... .......... . . U U U U . . 19 19 19 19 not properly emulated -rtr 32 . . 0100111001110111 .......... U U U U U U 20 20 14 14 14 14 -rts 32 . . 0100111001110101 .......... U U U U U U 16 16 10 10 10 10 -sbcd 8 rr . 1000...100000... .......... U U U U U U 6 6 4 4 4 4 -sbcd 8 mm ax7 1000111100001... .......... U U U U U U 18 18 16 16 16 16 -sbcd 8 mm ay7 1000...100001111 .......... U U U U U U 18 18 16 16 16 16 -sbcd 8 mm axy7 1000111100001111 .......... U U U U U U 18 18 16 16 16 16 -sbcd 8 mm . 1000...100001... .......... U U U U U U 18 18 16 16 16 16 -st 8 . d 0101000011000... .......... U U U U U U 6 4 4 4 4 4 -st 8 . . 0101000011...... A+-DXWL... U U U U U U 8 8 6 6 6 6 -sf 8 . d 0101000111000... .......... U U U U U U 4 4 4 4 4 4 -sf 8 . . 0101000111...... A+-DXWL... U U U U U U 8 8 6 6 6 6 -scc 8 . d 0101....11000... .......... U U U U U U 4 4 4 4 4 4 -scc 8 . . 0101....11...... A+-DXWL... U U U U U U 8 8 6 6 6 6 -stop 0 . . 0100111001110010 .......... S S S S S S 4 4 8 8 8 8 -sub 8 er d 1001...000000... .......... U U U U U U 4 4 2 2 2 2 -sub 8 er . 1001...000...... A+-DXWLdxI U U U U U U 4 4 2 2 2 2 -sub 16 er d 1001...001000... .......... U U U U U U 4 4 2 2 2 2 -sub 16 er a 1001...001001... .......... U U U U U U 4 4 2 2 2 2 -sub 16 er . 1001...001...... A+-DXWLdxI U U U U U U 4 4 2 2 2 2 -sub 32 er d 1001...010000... .......... U U U U U U 6 6 2 2 2 2 -sub 32 er a 1001...010001... .......... U U U U U U 6 6 2 2 2 2 -sub 32 er . 1001...010...... A+-DXWLdxI U U U U U U 6 6 2 2 2 2 -sub 8 re . 1001...100...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -sub 16 re . 1001...101...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -sub 32 re . 1001...110...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -suba 16 . d 1001...011000... .......... U U U U U U 8 8 2 2 2 2 -suba 16 . a 1001...011001... .......... U U U U U U 8 8 2 2 2 2 -suba 16 . . 1001...011...... A+-DXWLdxI U U U U U U 8 8 2 2 2 2 -suba 32 . d 1001...111000... .......... U U U U U U 6 6 2 2 2 2 -suba 32 . a 1001...111001... .......... U U U U U U 6 6 2 2 2 2 -suba 32 . . 1001...111...... A+-DXWLdxI U U U U U U 6 6 2 2 2 2 -subi 8 . d 0000010000000... .......... U U U U U U 8 8 2 2 2 2 -subi 8 . . 0000010000...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -subi 16 . d 0000010001000... .......... U U U U U U 8 8 2 2 2 2 -subi 16 . . 0000010001...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -subi 32 . d 0000010010000... .......... U U U U U U 16 14 2 2 2 2 -subi 32 . . 0000010010...... A+-DXWL... U U U U U U 20 20 4 4 4 4 -subq 8 . d 0101...100000... .......... U U U U U U 4 4 2 2 2 2 -subq 8 . . 0101...100...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -subq 16 . d 0101...101000... .......... U U U U U U 4 4 2 2 2 2 -subq 16 . a 0101...101001... .......... U U U U U U 8 4 2 2 2 2 -subq 16 . . 0101...101...... A+-DXWL... U U U U U U 8 8 4 4 4 4 -subq 32 . d 0101...110000... .......... U U U U U U 8 8 2 2 2 2 -subq 32 . a 0101...110001... .......... U U U U U U 8 8 2 2 2 2 -subq 32 . . 0101...110...... A+-DXWL... U U U U U U 12 12 4 4 4 4 -subx 8 rr . 1001...100000... .......... U U U U U U 4 4 2 2 2 2 -subx 16 rr . 1001...101000... .......... U U U U U U 4 4 2 2 2 2 -subx 32 rr . 1001...110000... .......... U U U U U U 8 6 2 2 2 2 -subx 8 mm ax7 1001111100001... .......... U U U U U U 18 18 12 12 12 12 -subx 8 mm ay7 1001...100001111 .......... U U U U U U 18 18 12 12 12 12 -subx 8 mm axy7 1001111100001111 .......... U U U U U U 18 18 12 12 12 12 -subx 8 mm . 1001...100001... .......... U U U U U U 18 18 12 12 12 12 -subx 16 mm . 1001...101001... .......... U U U U U U 18 18 12 12 12 12 -subx 32 mm . 1001...110001... .......... U U U U U U 30 30 12 12 12 12 -swap 32 . . 0100100001000... .......... U U U U U U 4 4 4 4 4 4 -tas 8 . d 0100101011000... .......... U U U U U U 4 4 4 4 4 4 -tas 8 . . 0100101011...... A+-DXWL... U U U U U U 14 14 12 12 12 12 -trap 0 . . 010011100100.... .......... U U U U U U 4 4 4 4 4 4 -trapt 0 . . 0101000011111100 .......... . . U U U U . . 4 4 4 4 -trapt 16 . . 0101000011111010 .......... . . U U U U . . 6 6 6 6 -trapt 32 . . 0101000011111011 .......... . . U U U U . . 8 8 8 8 -trapf 0 . . 0101000111111100 .......... . . U U U U . . 4 4 4 4 -trapf 16 . . 0101000111111010 .......... . . U U U U . . 6 6 6 6 -trapf 32 . . 0101000111111011 .......... . . U U U U . . 8 8 8 8 -trapcc 0 . . 0101....11111100 .......... . . U U U U . . 4 4 4 4 -trapcc 16 . . 0101....11111010 .......... . . U U U U . . 6 6 6 6 -trapcc 32 . . 0101....11111011 .......... . . U U U U . . 8 8 8 8 -trapv 0 . . 0100111001110110 .......... U U U U U U 4 4 4 4 4 4 -tst 8 . d 0100101000000... .......... U U U U U U 4 4 2 2 2 2 -tst 8 . . 0100101000...... A+-DXWL... U U U U U U 4 4 2 2 2 2 -tst 8 . pcdi 0100101000111010 .......... . . U U U U . . 7 7 7 7 -tst 8 . pcix 0100101000111011 .......... . . U U U U . . 9 9 9 9 -tst 8 . i 0100101000111100 .......... . . U U U U . . 6 6 6 6 -tst 16 . d 0100101001000... .......... U U U U U U 4 4 2 2 2 2 -tst 16 . a 0100101001001... .......... . . U U U U . . 2 2 2 2 -tst 16 . . 0100101001...... A+-DXWL... U U U U U U 4 4 2 2 2 2 -tst 16 . pcdi 0100101001111010 .......... . . U U U U . . 7 7 7 7 -tst 16 . pcix 0100101001111011 .......... . . U U U U . . 9 9 9 9 -tst 16 . i 0100101001111100 .......... . . U U U U . . 6 6 6 6 -tst 32 . d 0100101010000... .......... U U U U U U 4 4 2 2 2 2 -tst 32 . a 0100101010001... .......... . . U U U U . . 2 2 2 2 -tst 32 . . 0100101010...... A+-DXWL... U U U U U U 4 4 2 2 2 2 -tst 32 . pcdi 0100101010111010 .......... . . U U U U . . 7 7 7 7 -tst 32 . pcix 0100101010111011 .......... . . U U U U . . 9 9 9 9 -tst 32 . i 0100101010111100 .......... . . U U U U . . 6 6 6 6 -unlk 32 . a7 0100111001011111 .......... U U U U U U 12 12 6 6 6 6 -unlk 32 . . 0100111001011... .......... U U U U U U 12 12 6 6 6 6 -unpk 16 rr . 1000...110000... .......... . . U U U U . . 8 8 8 8 -unpk 16 mm ax7 1000111110001... .......... . . U U U U . . 13 13 13 13 -unpk 16 mm ay7 1000...110001111 .......... . . U U U U . . 13 13 13 13 -unpk 16 mm axy7 1000111110001111 .......... . . U U U U . . 13 13 13 13 -unpk 16 mm . 1000...110001... .......... . . U U U U . . 13 13 13 13 + spec spec allowed ea mode 3 C cpu cycles +name size proc ea bit pattern A+-DXWLdxI 0 1 2 3 4 2 F 000 010 020 030 040 340 CLF comments +====== ==== ==== ==== ================ ========== = = = = = = = === === === === === === === ========== +M68KMAKE_TABLE_START +1010 0 . . 1010............ .......... U U U U U U U 4 4 4 4 4 4 4 +1111 0 . . 1111............ .......... U U U U U U U 4 4 4 4 4 4 4 +040fpu0 32 . . 11110010........ .......... . . . U U U . . . . 0 0 0 . +040fpu1 32 . . 11110011........ .......... . . . U U U . . . . 0 0 0 . +abcd 8 rr . 1100...100000... .......... U U U U U U U 6 6 4 4 4 4 4 +abcd 8 mm ax7 1100111100001... .......... U U U U U U U 18 18 16 16 16 16 16 +abcd 8 mm ay7 1100...100001111 .......... U U U U U U U 18 18 16 16 16 16 16 +abcd 8 mm axy7 1100111100001111 .......... U U U U U U U 18 18 16 16 16 16 16 +abcd 8 mm . 1100...100001... .......... U U U U U U U 18 18 16 16 16 16 16 +add 8 er d 1101...000000... .......... U U U U U U U 4 4 2 2 2 2 2 +add 8 er . 1101...000...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2 +add 16 er d 1101...001000... .......... U U U U U U U 4 4 2 2 2 2 2 +add 16 er a 1101...001001... .......... U U U U U U U 4 4 2 2 2 2 2 +add 16 er . 1101...001...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2 +add 32 er d 1101...010000... .......... U U U U U U U 6 6 2 2 2 2 2 +add 32 er a 1101...010001... .......... U U U U U U U 6 6 2 2 2 2 2 +add 32 er . 1101...010...... A+-DXWLdxI U U U U U U U 6 6 2 2 2 2 2 +add 8 re . 1101...100...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +add 16 re . 1101...101...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +add 32 re . 1101...110...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +adda 16 . d 1101...011000... .......... U U U U U U U 8 8 2 2 2 2 2 +adda 16 . a 1101...011001... .......... U U U U U U U 8 8 2 2 2 2 2 +adda 16 . . 1101...011...... A+-DXWLdxI U U U U U U U 8 8 2 2 2 2 2 +adda 32 . d 1101...111000... .......... U U U U U U U 6 6 2 2 2 2 2 +adda 32 . a 1101...111001... .......... U U U U U U U 6 6 2 2 2 2 2 +adda 32 . . 1101...111...... A+-DXWLdxI U U U U U U U 6 6 2 2 2 2 2 +addi 8 . d 0000011000000... .......... U U U U U U U 8 8 2 2 2 2 2 +addi 8 . . 0000011000...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +addi 16 . d 0000011001000... .......... U U U U U U U 8 8 2 2 2 2 2 +addi 16 . . 0000011001...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +addi 32 . d 0000011010000... .......... U U U U U U U 16 14 2 2 2 2 2 +addi 32 . . 0000011010...... A+-DXWL... U U U U U U U 20 20 4 4 4 4 4 +addq 8 . d 0101...000000... .......... U U U U U U U 4 4 2 2 2 2 2 +addq 8 . . 0101...000...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +addq 16 . d 0101...001000... .......... U U U U U U U 4 4 2 2 2 2 2 +addq 16 . a 0101...001001... .......... U U U U U U U 4 4 2 2 2 2 2 +addq 16 . . 0101...001...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +addq 32 . d 0101...010000... .......... U U U U U U U 8 8 2 2 2 2 2 +addq 32 . a 0101...010001... .......... U U U U U U U 8 8 2 2 2 2 2 +addq 32 . . 0101...010...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +addx 8 rr . 1101...100000... .......... U U U U U U U 4 4 2 2 2 2 2 +addx 16 rr . 1101...101000... .......... U U U U U U U 4 4 2 2 2 2 2 +addx 32 rr . 1101...110000... .......... U U U U U U U 8 6 2 2 2 2 2 +addx 8 mm ax7 1101111100001... .......... U U U U U U U 18 18 12 12 12 12 12 +addx 8 mm ay7 1101...100001111 .......... U U U U U U U 18 18 12 12 12 12 12 +addx 8 mm axy7 1101111100001111 .......... U U U U U U U 18 18 12 12 12 12 12 +addx 8 mm . 1101...100001... .......... U U U U U U U 18 18 12 12 12 12 12 +addx 16 mm . 1101...101001... .......... U U U U U U U 18 18 12 12 12 12 12 +addx 32 mm . 1101...110001... .......... U U U U U U U 30 30 12 12 12 12 12 +and 8 er d 1100...000000... .......... U U U U U U U 4 4 2 2 2 2 2 +and 8 er . 1100...000...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2 +and 16 er d 1100...001000... .......... U U U U U U U 4 4 2 2 2 2 2 +and 16 er . 1100...001...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2 +and 32 er d 1100...010000... .......... U U U U U U U 6 6 2 2 2 2 2 +and 32 er . 1100...010...... A+-DXWLdxI U U U U U U U 6 6 2 2 2 2 2 +and 8 re . 1100...100...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +and 16 re . 1100...101...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +and 32 re . 1100...110...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +andi 16 toc . 0000001000111100 .......... U U U U U U U 20 16 12 12 12 12 12 +andi 16 tos . 0000001001111100 .......... S S S S S S S 20 16 12 12 12 12 12 +andi 8 . d 0000001000000... .......... U U U U U U U 8 8 2 2 2 2 2 +andi 8 . . 0000001000...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +andi 16 . d 0000001001000... .......... U U U U U U U 8 8 2 2 2 2 2 +andi 16 . . 0000001001...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +andi 32 . d 0000001010000... .......... U U U U U U U 14 14 2 2 2 2 2 +andi 32 . . 0000001010...... A+-DXWL... U U U U U U U 20 20 4 4 4 4 4 +asr 8 s . 1110...000000... .......... U U U U U U U 6 6 6 6 6 6 6 +asr 16 s . 1110...001000... .......... U U U U U U U 6 6 6 6 6 6 6 +asr 32 s . 1110...010000... .......... U U U U U U U 8 8 6 6 6 6 6 +asr 8 r . 1110...000100... .......... U U U U U U U 6 6 6 6 6 6 6 +asr 16 r . 1110...001100... .......... U U U U U U U 6 6 6 6 6 6 6 +asr 32 r . 1110...010100... .......... U U U U U U U 8 8 6 6 6 6 6 +asr 16 . . 1110000011...... A+-DXWL... U U U U U U U 8 8 5 5 5 5 5 +asl 8 s . 1110...100000... .......... U U U U U U U 6 6 8 8 8 8 8 +asl 16 s . 1110...101000... .......... U U U U U U U 6 6 8 8 8 8 8 +asl 32 s . 1110...110000... .......... U U U U U U U 8 8 8 8 8 8 8 +asl 8 r . 1110...100100... .......... U U U U U U U 6 6 8 8 8 8 8 +asl 16 r . 1110...101100... .......... U U U U U U U 6 6 8 8 8 8 8 +asl 32 r . 1110...110100... .......... U U U U U U U 8 8 8 8 8 8 8 +asl 16 . . 1110000111...... A+-DXWL... U U U U U U U 8 8 6 6 6 6 6 +bcc 8 . . 0110............ .......... U U U U U U U 10 10 6 6 6 6 6 +bcc 16 . . 0110....00000000 .......... U U U U U U U 10 10 6 6 6 6 6 +bcc 32 . . 0110....11111111 .......... U U U U U U U 10 10 6 6 6 6 6 +bchg 8 r . 0000...101...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +bchg 32 r d 0000...101000... .......... U U U U U U U 8 8 4 4 4 4 4 +bchg 8 s . 0000100001...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +bchg 32 s d 0000100001000... .......... U U U U U U U 12 12 4 4 4 4 4 +bclr 8 r . 0000...110...... A+-DXWL... U U U U U U U 8 10 4 4 4 4 4 +bclr 32 r d 0000...110000... .......... U U U U U U U 10 10 4 4 4 4 4 +bclr 8 s . 0000100010...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +bclr 32 s d 0000100010000... .......... U U U U U U U 14 14 4 4 4 4 4 +bfchg 32 . d 1110101011000... .......... . . U U U U U . . 12 12 12 12 12 timing not quite correct +bfchg 32 . . 1110101011...... A..DXWL... . . U U U U U . . 20 20 20 20 20 +bfclr 32 . d 1110110011000... .......... . . U U U U U . . 12 12 12 12 12 +bfclr 32 . . 1110110011...... A..DXWL... . . U U U U U . . 20 20 20 20 20 +bfexts 32 . d 1110101111000... .......... . . U U U U U . . 8 8 8 8 8 +bfexts 32 . . 1110101111...... A..DXWLdx. . . U U U U U . . 15 15 15 15 15 +bfextu 32 . d 1110100111000... .......... . . U U U U U . . 8 8 8 8 8 +bfextu 32 . . 1110100111...... A..DXWLdx. . . U U U U U . . 15 15 15 15 15 +bfffo 32 . d 1110110111000... .......... . . U U U U U . . 18 18 18 18 18 +bfffo 32 . . 1110110111...... A..DXWLdx. . . U U U U U . . 28 28 28 28 28 +bfins 32 . d 1110111111000... .......... . . U U U U U . . 10 10 10 10 10 +bfins 32 . . 1110111111...... A..DXWL... . . U U U U U . . 17 17 17 17 17 +bfset 32 . d 1110111011000... .......... . . U U U U U . . 12 12 12 12 12 +bfset 32 . . 1110111011...... A..DXWL... . . U U U U U . . 20 20 20 20 20 +bftst 32 . d 1110100011000... .......... . . U U U U U . . 6 6 6 6 6 +bftst 32 . . 1110100011...... A..DXWLdx. . . U U U U U . . 13 13 13 13 13 +bkpt 0 . . 0100100001001... .......... . U U U U U U . 10 10 10 10 10 10 +bra 8 . . 01100000........ .......... U U U U U U U 10 10 10 10 10 10 10 +bra 16 . . 0110000000000000 .......... U U U U U U U 10 10 10 10 10 10 10 +bra 32 . . 0110000011111111 .......... U U U U U U U 10 10 10 10 10 10 10 +bset 32 r d 0000...111000... .......... U U U U U U U 8 8 4 4 4 4 4 +bset 8 r . 0000...111...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +bset 8 s . 0000100011...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +bset 32 s d 0000100011000... .......... U U U U U U U 12 12 4 4 4 4 4 +bsr 8 . . 01100001........ .......... U U U U U U U 18 18 7 7 7 7 7 +bsr 16 . . 0110000100000000 .......... U U U U U U U 18 18 7 7 7 7 7 +bsr 32 . . 0110000111111111 .......... U U U U U U U 18 18 7 7 7 7 7 +btst 8 r . 0000...100...... A+-DXWLdxI U U U U U U U 4 4 4 4 4 4 4 +btst 32 r d 0000...100000... .......... U U U U U U U 6 6 4 4 4 4 4 +btst 8 s . 0000100000...... A+-DXWLdx. U U U U U U U 8 8 4 4 4 4 4 +btst 32 s d 0000100000000... .......... U U U U U U U 10 10 4 4 4 4 4 +callm 32 . . 0000011011...... A..DXWLdx. . . U U U U U . . 60 60 60 60 60 not properly emulated +cas 8 . . 0000101011...... A+-DXWL... . . U U U U U . . 12 12 12 12 12 +cas 16 . . 0000110011...... A+-DXWL... . . U U U U U . . 12 12 12 12 12 +cas 32 . . 0000111011...... A+-DXWL... . . U U U U U . . 12 12 12 12 12 +cas2 16 . . 0000110011111100 .......... . . U U U U U . . 12 12 12 12 12 +cas2 32 . . 0000111011111100 .......... . . U U U U U . . 12 12 12 12 12 +chk 16 . d 0100...110000... .......... U U U U U U U 10 8 8 8 8 8 8 +chk 16 . . 0100...110...... A+-DXWLdxI U U U U U U U 10 8 8 8 8 8 8 +chk 32 . d 0100...100000... .......... . . U U U U U . . 8 8 8 8 8 +chk 32 . . 0100...100...... A+-DXWLdxI . . U U U U U . . 8 8 8 8 8 +chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U U U U . . 23 23 23 23 23 +chk2cmp2 8 . pcix 0000000011111011 .......... . . U U U U U . . 23 23 23 23 23 +chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U U U U . . 18 18 18 18 18 +chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U U U U . . 23 23 23 23 23 +chk2cmp2 16 . pcix 0000001011111011 .......... . . U U U U U . . 23 23 23 23 23 +chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U U U U . . 18 18 18 18 18 +chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U U U U . . 23 23 23 23 23 +chk2cmp2 32 . pcix 0000010011111011 .......... . . U U U U U . . 23 23 23 23 23 +chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U U U U . . 18 18 18 18 18 +clr 8 . d 0100001000000... .......... U U U U U U U 4 4 2 2 2 2 2 +clr 8 . . 0100001000...... A+-DXWL... U U U U U U U 8 4 4 4 4 4 4 +clr 16 . d 0100001001000... .......... U U U U U U U 4 4 2 2 2 2 2 +clr 16 . . 0100001001...... A+-DXWL... U U U U U U U 8 4 4 4 4 4 4 +clr 32 . d 0100001010000... .......... U U U U U U U 6 6 2 2 2 2 2 +clr 32 . . 0100001010...... A+-DXWL... U U U U U U U 12 6 4 4 4 4 4 +cmp 8 . d 1011...000000... .......... U U U U U U U 4 4 2 2 2 2 2 +cmp 8 . . 1011...000...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2 +cmp 16 . d 1011...001000... .......... U U U U U U U 4 4 2 2 2 2 2 +cmp 16 . a 1011...001001... .......... U U U U U U U 4 4 2 2 2 2 2 +cmp 16 . . 1011...001...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2 +cmp 32 . d 1011...010000... .......... U U U U U U U 6 6 2 2 2 2 2 +cmp 32 . a 1011...010001... .......... U U U U U U U 6 6 2 2 2 2 2 +cmp 32 . . 1011...010...... A+-DXWLdxI U U U U U U U 6 6 2 2 2 2 2 +cmpa 16 . d 1011...011000... .......... U U U U U U U 6 6 4 4 4 4 4 +cmpa 16 . a 1011...011001... .......... U U U U U U U 6 6 4 4 4 4 4 +cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U U U U 6 6 4 4 4 4 4 +cmpa 32 . d 1011...111000... .......... U U U U U U U 6 6 4 4 4 4 4 +cmpa 32 . a 1011...111001... .......... U U U U U U U 6 6 4 4 4 4 4 +cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U U U U 6 6 4 4 4 4 4 +cmpi 8 . d 0000110000000... .......... U U U U U U U 8 8 2 2 2 2 2 +cmpi 8 . . 0000110000...... A+-DXWL... U U U U U U U 8 8 2 2 2 2 2 +cmpi 8 . pcdi 0000110000111010 .......... . . U U U U U . . 7 7 7 7 7 +cmpi 8 . pcix 0000110000111011 .......... . . U U U U U . . 9 9 9 9 9 +cmpi 16 . d 0000110001000... .......... U U U U U U U 8 8 2 2 2 2 2 +cmpi 16 . . 0000110001...... A+-DXWL... U U U U U U U 8 8 2 2 2 2 2 +cmpi 16 . pcdi 0000110001111010 .......... . . U U U U U . . 7 7 7 7 7 +cmpi 16 . pcix 0000110001111011 .......... . . U U U U U . . 9 9 9 9 9 +cmpi 32 . d 0000110010000... .......... U U U U U U U 14 12 2 2 2 2 2 +cmpi 32 . . 0000110010...... A+-DXWL... U U U U U U U 12 12 2 2 2 2 2 +cmpi 32 . pcdi 0000110010111010 .......... . . U U U U U . . 7 7 7 7 7 +cmpi 32 . pcix 0000110010111011 .......... . . U U U U U . . 9 9 9 9 9 +cmpm 8 . ax7 1011111100001... .......... U U U U U U U 12 12 9 9 9 9 9 +cmpm 8 . ay7 1011...100001111 .......... U U U U U U U 12 12 9 9 9 9 9 +cmpm 8 . axy7 1011111100001111 .......... U U U U U U U 12 12 9 9 9 9 9 +cmpm 8 . . 1011...100001... .......... U U U U U U U 12 12 9 9 9 9 9 +cmpm 16 . . 1011...101001... .......... U U U U U U U 12 12 9 9 9 9 9 +cmpm 32 . . 1011...110001... .......... U U U U U U U 20 20 9 9 9 9 9 +cinv 32 . . 11110100..0..... .......... . . . . U . . . . . . 16 . . 040 only +cpush 32 . . 11110100..1..... .......... . . . . U . . . . . . 16 . . 040 only +cpbcc 32 . . 1111...01....... .......... . . U U . . U . . 4 4 . . . cpXXX only for 020/030, not on 040! +cpdbcc 32 . . 1111...001001... .......... . . U U . . U . . 4 4 . . . +cpgen 32 . . 1111...000...... .......... . . U U . . U . . 4 4 . . . +cpscc 32 . . 1111...001...... .......... . . U U . . U . . 4 4 . . . +cptrapcc 32 . . 1111...001111... .......... . . U U . . U . . 4 4 . . . +dbt 16 . . 0101000011001... .......... U U U U U U U 12 12 6 6 6 6 6 +dbf 16 . . 0101000111001... .......... U U U U U U U 12 12 6 6 6 6 6 +dbcc 16 . . 0101....11001... .......... U U U U U U U 12 12 6 6 6 6 6 +divs 16 . d 1000...111000... .......... U U U U U U U 158 122 56 56 56 56 56 +divs 16 . . 1000...111...... A+-DXWLdxI U U U U U U U 158 122 56 56 56 56 56 +divu 16 . d 1000...011000... .......... U U U U U U U 140 108 44 44 44 44 44 +divu 16 . . 1000...011...... A+-DXWLdxI U U U U U U U 140 108 44 44 44 44 44 +divl 32 . d 0100110001000... .......... . . U U U U U . . 84 84 84 84 84 +divl 32 . . 0100110001...... A+-DXWLdxI . . U U U U U . . 84 84 84 84 84 +eor 8 . d 1011...100000... .......... U U U U U U U 4 4 2 2 2 2 2 +eor 8 . . 1011...100...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +eor 16 . d 1011...101000... .......... U U U U U U U 4 4 2 2 2 2 2 +eor 16 . . 1011...101...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +eor 32 . d 1011...110000... .......... U U U U U U U 8 6 2 2 2 2 2 +eor 32 . . 1011...110...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +eori 16 toc . 0000101000111100 .......... U U U U U U U 20 16 12 12 12 12 12 +eori 16 tos . 0000101001111100 .......... S S S S S S S 20 16 12 12 12 12 12 +eori 8 . d 0000101000000... .......... U U U U U U U 8 8 2 2 2 2 2 +eori 8 . . 0000101000...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +eori 16 . d 0000101001000... .......... U U U U U U U 8 8 2 2 2 2 2 +eori 16 . . 0000101001...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +eori 32 . d 0000101010000... .......... U U U U U U U 16 14 2 2 2 2 2 +eori 32 . . 0000101010...... A+-DXWL... U U U U U U U 20 20 4 4 4 4 4 +exg 32 dd . 1100...101000... .......... U U U U U U U 6 6 2 2 2 2 2 +exg 32 aa . 1100...101001... .......... U U U U U U U 6 6 2 2 2 2 2 +exg 32 da . 1100...110001... .......... U U U U U U U 6 6 2 2 2 2 2 +ext 16 . . 0100100010000... .......... U U U U U U U 4 4 4 4 4 4 4 +ext 32 . . 0100100011000... .......... U U U U U U U 4 4 4 4 4 4 4 +extb 32 . . 0100100111000... .......... . . U U U U U . . 4 4 4 4 4 +illegal 0 . . 0100101011111100 .......... U U U U U U U 4 4 4 4 4 4 4 +jmp 32 . . 0100111011...... A..DXWLdx. U U U U U U U 4 4 0 0 0 0 0 +jsr 32 . . 0100111010...... A..DXWLdx. U U U U U U U 12 12 0 0 0 0 0 +lea 32 . . 0100...111...... A..DXWLdx. U U U U U U U 0 0 2 2 2 2 2 +link 16 . a7 0100111001010111 .......... U U U U U U U 16 16 5 5 5 5 5 +link 16 . . 0100111001010... .......... U U U U U U U 16 16 5 5 5 5 5 +link 32 . a7 0100100000001111 .......... . . U U U U U . . 6 6 6 6 6 +link 32 . . 0100100000001... .......... . . U U U U U . . 6 6 6 6 6 +lsr 8 s . 1110...000001... .......... U U U U U U U 6 6 4 4 4 4 4 +lsr 16 s . 1110...001001... .......... U U U U U U U 6 6 4 4 4 4 4 +lsr 32 s . 1110...010001... .......... U U U U U U U 8 8 4 4 4 4 4 +lsr 8 r . 1110...000101... .......... U U U U U U U 6 6 6 6 6 6 6 +lsr 16 r . 1110...001101... .......... U U U U U U U 6 6 6 6 6 6 6 +lsr 32 r . 1110...010101... .......... U U U U U U U 8 8 6 6 6 6 6 +lsr 16 . . 1110001011...... A+-DXWL... U U U U U U U 8 8 5 5 5 5 5 +lsl 8 s . 1110...100001... .......... U U U U U U U 6 6 4 4 4 4 4 +lsl 16 s . 1110...101001... .......... U U U U U U U 6 6 4 4 4 4 4 +lsl 32 s . 1110...110001... .......... U U U U U U U 8 8 4 4 4 4 4 +lsl 8 r . 1110...100101... .......... U U U U U U U 6 6 6 6 6 6 6 +lsl 16 r . 1110...101101... .......... U U U U U U U 6 6 6 6 6 6 6 +lsl 32 r . 1110...110101... .......... U U U U U U U 8 8 6 6 6 6 6 +lsl 16 . . 1110001111...... A+-DXWL... U U U U U U U 8 8 5 5 5 5 5 +move 8 d d 0001...000000... .......... U U U U U U U 4 4 2 2 2 2 2 +move 8 d . 0001...000...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2 +move 8 ai d 0001...010000... .......... U U U U U U U 8 8 4 4 4 4 4 +move 8 ai . 0001...010...... A+-DXWLdxI U U U U U U U 8 8 4 4 4 4 4 +move 8 pi d 0001...011000... .......... U U U U U U U 8 8 4 4 4 4 4 +move 8 pi . 0001...011...... A+-DXWLdxI U U U U U U U 8 8 4 4 4 4 4 +move 8 pi7 d 0001111011000... .......... U U U U U U U 8 8 4 4 4 4 4 +move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U U U U 8 8 4 4 4 4 4 +move 8 pd d 0001...100000... .......... U U U U U U U 8 8 5 5 5 5 5 +move 8 pd . 0001...100...... A+-DXWLdxI U U U U U U U 8 8 5 5 5 5 5 +move 8 pd7 d 0001111100000... .......... U U U U U U U 8 8 5 5 5 5 5 +move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U U U U 8 8 5 5 5 5 5 +move 8 di d 0001...101000... .......... U U U U U U U 12 12 5 5 5 5 5 +move 8 di . 0001...101...... A+-DXWLdxI U U U U U U U 12 12 5 5 5 5 5 +move 8 ix d 0001...110000... .......... U U U U U U U 14 14 7 7 7 7 7 +move 8 ix . 0001...110...... A+-DXWLdxI U U U U U U U 14 14 7 7 7 7 7 +move 8 aw d 0001000111000... .......... U U U U U U U 12 12 4 4 4 4 4 +move 8 aw . 0001000111...... A+-DXWLdxI U U U U U U U 12 12 4 4 4 4 4 +move 8 al d 0001001111000... .......... U U U U U U U 16 16 6 6 6 6 6 +move 8 al . 0001001111...... A+-DXWLdxI U U U U U U U 16 16 6 6 6 6 6 +move 16 d d 0011...000000... .......... U U U U U U U 4 4 2 2 2 2 2 +move 16 d a 0011...000001... .......... U U U U U U U 4 4 2 2 2 2 2 +move 16 d . 0011...000...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2 +move 16 ai d 0011...010000... .......... U U U U U U U 8 8 4 4 4 4 4 +move 16 ai a 0011...010001... .......... U U U U U U U 8 8 4 4 4 4 4 +move 16 ai . 0011...010...... A+-DXWLdxI U U U U U U U 8 8 4 4 4 4 4 +move 16 pi d 0011...011000... .......... U U U U U U U 8 8 4 4 4 4 4 +move 16 pi a 0011...011001... .......... U U U U U U U 8 8 4 4 4 4 4 +move 16 pi . 0011...011...... A+-DXWLdxI U U U U U U U 8 8 4 4 4 4 4 +move 16 pd d 0011...100000... .......... U U U U U U U 8 8 5 5 5 5 5 +move 16 pd a 0011...100001... .......... U U U U U U U 8 8 5 5 5 5 5 +move 16 pd . 0011...100...... A+-DXWLdxI U U U U U U U 8 8 5 5 5 5 5 +move 16 di d 0011...101000... .......... U U U U U U U 12 12 5 5 5 5 5 +move 16 di a 0011...101001... .......... U U U U U U U 12 12 5 5 5 5 5 +move 16 di . 0011...101...... A+-DXWLdxI U U U U U U U 12 12 5 5 5 5 5 +move 16 ix d 0011...110000... .......... U U U U U U U 14 14 7 7 7 7 7 +move 16 ix a 0011...110001... .......... U U U U U U U 14 14 7 7 7 7 7 +move 16 ix . 0011...110...... A+-DXWLdxI U U U U U U U 14 14 7 7 7 7 7 +move 16 aw d 0011000111000... .......... U U U U U U U 12 12 4 4 4 4 4 +move 16 aw a 0011000111001... .......... U U U U U U U 12 12 4 4 4 4 4 +move 16 aw . 0011000111...... A+-DXWLdxI U U U U U U U 12 12 4 4 4 4 4 +move 16 al d 0011001111000... .......... U U U U U U U 16 16 6 6 6 6 6 +move 16 al a 0011001111001... .......... U U U U U U U 16 16 6 6 6 6 6 +move 16 al . 0011001111...... A+-DXWLdxI U U U U U U U 16 16 6 6 6 6 6 +move 32 d d 0010...000000... .......... U U U U U U U 4 4 2 2 2 2 2 +move 32 d a 0010...000001... .......... U U U U U U U 4 4 2 2 2 2 2 +move 32 d . 0010...000...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2 +move 32 ai d 0010...010000... .......... U U U U U U U 12 12 4 4 4 4 4 +move 32 ai a 0010...010001... .......... U U U U U U U 12 12 4 4 4 4 4 +move 32 ai . 0010...010...... A+-DXWLdxI U U U U U U U 12 12 4 4 4 4 4 +move 32 pi d 0010...011000... .......... U U U U U U U 12 12 4 4 4 4 4 +move 32 pi a 0010...011001... .......... U U U U U U U 12 12 4 4 4 4 4 +move 32 pi . 0010...011...... A+-DXWLdxI U U U U U U U 12 12 4 4 4 4 4 +move 32 pd d 0010...100000... .......... U U U U U U U 12 14 5 5 5 5 5 +move 32 pd a 0010...100001... .......... U U U U U U U 12 14 5 5 5 5 5 +move 32 pd . 0010...100...... A+-DXWLdxI U U U U U U U 12 14 5 5 5 5 5 +move 32 di d 0010...101000... .......... U U U U U U U 16 16 5 5 5 5 5 +move 32 di a 0010...101001... .......... U U U U U U U 16 16 5 5 5 5 5 +move 32 di . 0010...101...... A+-DXWLdxI U U U U U U U 16 16 5 5 5 5 5 +move 32 ix d 0010...110000... .......... U U U U U U U 18 18 7 7 7 7 7 +move 32 ix a 0010...110001... .......... U U U U U U U 18 18 7 7 7 7 7 +move 32 ix . 0010...110...... A+-DXWLdxI U U U U U U U 18 18 7 7 7 7 7 +move 32 aw d 0010000111000... .......... U U U U U U U 16 16 4 4 4 4 4 +move 32 aw a 0010000111001... .......... U U U U U U U 16 16 4 4 4 4 4 +move 32 aw . 0010000111...... A+-DXWLdxI U U U U U U U 16 16 4 4 4 4 4 +move 32 al d 0010001111000... .......... U U U U U U U 20 20 6 6 6 6 6 +move 32 al a 0010001111001... .......... U U U U U U U 20 20 6 6 6 6 6 +move 32 al . 0010001111...... A+-DXWLdxI U U U U U U U 20 20 6 6 6 6 6 +movea 16 . d 0011...001000... .......... U U U U U U U 4 4 2 2 2 2 2 +movea 16 . a 0011...001001... .......... U U U U U U U 4 4 2 2 2 2 2 +movea 16 . . 0011...001...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2 +movea 32 . d 0010...001000... .......... U U U U U U U 4 4 2 2 2 2 2 +movea 32 . a 0010...001001... .......... U U U U U U U 4 4 2 2 2 2 2 +movea 32 . . 0010...001...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2 +move 16 frc d 0100001011000... .......... . U U U U U U . 4 4 4 4 4 4 +move 16 frc . 0100001011...... A+-DXWL... . U U U U U U . 8 4 4 4 4 4 +move 16 toc d 0100010011000... .......... U U U U U U U 12 12 4 4 4 4 4 +move 16 toc . 0100010011...... A+-DXWLdxI U U U U U U U 12 12 4 4 4 4 4 +move 16 frs d 0100000011000... .......... U S S S S S S 6 4 8 8 8 8 8 U only for 000 +move 16 frs . 0100000011...... A+-DXWL... U S S S S S S 8 8 8 8 8 8 8 U only for 000 +move 16 tos d 0100011011000... .......... S S S S S S S 12 12 8 8 8 8 8 +move 16 tos . 0100011011...... A+-DXWLdxI S S S S S S S 12 12 8 8 8 8 8 +move 32 fru . 0100111001101... .......... S S S S S S S 4 6 2 2 2 2 2 +move 32 tou . 0100111001100... .......... S S S S S S S 4 6 2 2 2 2 2 +movec 32 cr . 0100111001111010 .......... . S S S S S S . 12 6 6 6 6 6 +movec 32 rc . 0100111001111011 .......... . S S S S S S . 10 12 12 12 12 12 +movem 16 re pd 0100100010100... .......... U U U U U U U 8 8 4 4 4 4 4 +movem 16 re . 0100100010...... A..DXWL... U U U U U U U 8 8 4 4 4 4 4 +movem 32 re pd 0100100011100... .......... U U U U U U U 8 8 4 4 4 4 4 +movem 32 re . 0100100011...... A..DXWL... U U U U U U U 8 8 4 4 4 4 4 +movem 16 er pi 0100110010011... .......... U U U U U U U 12 12 8 8 8 8 8 +movem 16 er pcdi 0100110010111010 .......... U U U U U U U 16 16 9 9 9 9 9 +movem 16 er pcix 0100110010111011 .......... U U U U U U U 18 18 11 11 11 11 11 +movem 16 er . 0100110010...... A..DXWL... U U U U U U U 12 12 8 8 8 8 8 +movem 32 er pi 0100110011011... .......... U U U U U U U 12 12 8 8 8 8 8 +movem 32 er pcdi 0100110011111010 .......... U U U U U U U 16 16 9 9 9 9 9 +movem 32 er pcix 0100110011111011 .......... U U U U U U U 18 18 11 11 11 11 11 +movem 32 er . 0100110011...... A..DXWL... U U U U U U U 12 12 8 8 8 8 8 +movep 16 er . 0000...100001... .......... U U U U U U U 16 16 12 12 12 12 12 +movep 32 er . 0000...101001... .......... U U U U U U U 24 24 18 18 18 18 18 +movep 16 re . 0000...110001... .......... U U U U U U U 16 16 11 11 11 11 11 +movep 32 re . 0000...111001... .......... U U U U U U U 24 24 17 17 17 17 17 +moveq 32 . . 0111...0........ .......... U U U U U U U 4 4 2 2 2 2 2 +moves 8 . . 0000111000...... A+-DXWL... . S S S S S S . 14 5 5 5 5 5 +moves 16 . . 0000111001...... A+-DXWL... . S S S S S S . 14 5 5 5 5 5 +moves 32 . . 0000111010...... A+-DXWL... . S S S S S S . 16 5 5 5 5 5 +move16 32 . . 1111011000100... .......... . . . . U U . . . . . 4 4 4 TODO: correct timing +muls 16 . d 1100...111000... .......... U U U U U U U 54 32 27 27 27 27 27 +muls 16 . . 1100...111...... A+-DXWLdxI U U U U U U U 54 32 27 27 27 27 27 +mulu 16 . d 1100...011000... .......... U U U U U U U 54 30 27 27 27 27 27 +mulu 16 . . 1100...011...... A+-DXWLdxI U U U U U U U 54 30 27 27 27 27 27 +mull 32 . d 0100110000000... .......... . . U U U U U . . 43 43 43 43 43 +mull 32 . . 0100110000...... A+-DXWLdxI . . U U U U U . . 43 43 43 43 43 +nbcd 8 . d 0100100000000... .......... U U U U U U U 6 6 6 6 6 6 6 +nbcd 8 . . 0100100000...... A+-DXWL... U U U U U U U 8 8 6 6 6 6 6 +neg 8 . d 0100010000000... .......... U U U U U U U 4 4 2 2 2 2 2 +neg 8 . . 0100010000...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +neg 16 . d 0100010001000... .......... U U U U U U U 4 4 2 2 2 2 2 +neg 16 . . 0100010001...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +neg 32 . d 0100010010000... .......... U U U U U U U 6 6 2 2 2 2 2 +neg 32 . . 0100010010...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +negx 8 . d 0100000000000... .......... U U U U U U U 4 4 2 2 2 2 2 +negx 8 . . 0100000000...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +negx 16 . d 0100000001000... .......... U U U U U U U 4 4 2 2 2 2 2 +negx 16 . . 0100000001...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +negx 32 . d 0100000010000... .......... U U U U U U U 6 6 2 2 2 2 2 +negx 32 . . 0100000010...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +nop 0 . . 0100111001110001 .......... U U U U U U U 4 4 2 2 2 2 2 +not 8 . d 0100011000000... .......... U U U U U U U 4 4 2 2 2 2 2 +not 8 . . 0100011000...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +not 16 . d 0100011001000... .......... U U U U U U U 4 4 2 2 2 2 2 +not 16 . . 0100011001...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +not 32 . d 0100011010000... .......... U U U U U U U 6 6 2 2 2 2 2 +not 32 . . 0100011010...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +or 8 er d 1000...000000... .......... U U U U U U U 4 4 2 2 2 2 2 +or 8 er . 1000...000...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2 +or 16 er d 1000...001000... .......... U U U U U U U 4 4 2 2 2 2 2 +or 16 er . 1000...001...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2 +or 32 er d 1000...010000... .......... U U U U U U U 6 6 2 2 2 2 2 +or 32 er . 1000...010...... A+-DXWLdxI U U U U U U U 6 6 2 2 2 2 2 +or 8 re . 1000...100...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +or 16 re . 1000...101...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +or 32 re . 1000...110...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +ori 16 toc . 0000000000111100 .......... U U U U U U U 20 16 12 12 12 12 12 +ori 16 tos . 0000000001111100 .......... S S S S S S S 20 16 12 12 12 12 12 +ori 8 . d 0000000000000... .......... U U U U U U U 8 8 2 2 2 2 2 +ori 8 . . 0000000000...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +ori 16 . d 0000000001000... .......... U U U U U U U 8 8 2 2 2 2 2 +ori 16 . . 0000000001...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +ori 32 . d 0000000010000... .......... U U U U U U U 16 14 2 2 2 2 2 +ori 32 . . 0000000010...... A+-DXWL... U U U U U U U 20 20 4 4 4 4 4 +pack 16 rr . 1000...101000... .......... . . U U U U U . . 6 6 6 6 6 +pack 16 mm ax7 1000111101001... .......... . . U U U U U . . 13 13 13 13 13 +pack 16 mm ay7 1000...101001111 .......... . . U U U U U . . 13 13 13 13 13 +pack 16 mm axy7 1000111101001111 .......... . . U U U U U . . 13 13 13 13 13 +pack 16 mm . 1000...101001... .......... . . U U U U U . . 13 13 13 13 13 +pea 32 . . 0100100001...... A..DXWLdx. U U U U U U U 6 6 5 5 5 5 5 +pflush 32 . . 1111010100011000 .......... . . . . S S . . . . . 4 4 4 TODO: correct timing +pmmu 32 . . 1111000......... .......... . . S S S S S . . 8 8 8 8 8 +reset 0 . . 0100111001110000 .......... S S S S S S S 0 0 0 0 0 0 0 +ror 8 s . 1110...000011... .......... U U U U U U U 6 6 8 8 8 8 8 +ror 16 s . 1110...001011... .......... U U U U U U U 6 6 8 8 8 8 8 +ror 32 s . 1110...010011... .......... U U U U U U U 8 8 8 8 8 8 8 +ror 8 r . 1110...000111... .......... U U U U U U U 6 6 8 8 8 8 8 +ror 16 r . 1110...001111... .......... U U U U U U U 6 6 8 8 8 8 8 +ror 32 r . 1110...010111... .......... U U U U U U U 8 8 8 8 8 8 8 +ror 16 . . 1110011011...... A+-DXWL... U U U U U U U 8 8 7 7 7 7 7 +rol 8 s . 1110...100011... .......... U U U U U U U 6 6 8 8 8 8 8 +rol 16 s . 1110...101011... .......... U U U U U U U 6 6 8 8 8 8 8 +rol 32 s . 1110...110011... .......... U U U U U U U 8 8 8 8 8 8 8 +rol 8 r . 1110...100111... .......... U U U U U U U 6 6 8 8 8 8 8 +rol 16 r . 1110...101111... .......... U U U U U U U 6 6 8 8 8 8 8 +rol 32 r . 1110...110111... .......... U U U U U U U 8 8 8 8 8 8 8 +rol 16 . . 1110011111...... A+-DXWL... U U U U U U U 8 8 7 7 7 7 7 +roxr 8 s . 1110...000010... .......... U U U U U U U 6 6 12 12 12 12 12 +roxr 16 s . 1110...001010... .......... U U U U U U U 6 6 12 12 12 12 12 +roxr 32 s . 1110...010010... .......... U U U U U U U 8 8 12 12 12 12 12 +roxr 8 r . 1110...000110... .......... U U U U U U U 6 6 12 12 12 12 12 +roxr 16 r . 1110...001110... .......... U U U U U U U 6 6 12 12 12 12 12 +roxr 32 r . 1110...010110... .......... U U U U U U U 8 8 12 12 12 12 12 +roxr 16 . . 1110010011...... A+-DXWL... U U U U U U U 8 8 5 5 5 5 5 +roxl 8 s . 1110...100010... .......... U U U U U U U 6 6 12 12 12 12 12 +roxl 16 s . 1110...101010... .......... U U U U U U U 6 6 12 12 12 12 12 +roxl 32 s . 1110...110010... .......... U U U U U U U 8 8 12 12 12 12 12 +roxl 8 r . 1110...100110... .......... U U U U U U U 6 6 12 12 12 12 12 +roxl 16 r . 1110...101110... .......... U U U U U U U 6 6 12 12 12 12 12 +roxl 32 r . 1110...110110... .......... U U U U U U U 8 8 12 12 12 12 12 +roxl 16 . . 1110010111...... A+-DXWL... U U U U U U U 8 8 5 5 5 5 5 +rtd 32 . . 0100111001110100 .......... . U U U U U U . 16 10 10 10 10 10 +rte 32 . . 0100111001110011 .......... S S S S S S S 20 24 20 20 20 20 20 bus fault not emulated +rtm 32 . . 000001101100.... .......... . . U U U U U . . 19 19 19 19 19 not properly emulated +rtr 32 . . 0100111001110111 .......... U U U U U U U 20 20 14 14 14 14 14 +rts 32 . . 0100111001110101 .......... U U U U U U U 16 16 10 10 10 10 10 +sbcd 8 rr . 1000...100000... .......... U U U U U U U 6 6 4 4 4 4 4 +sbcd 8 mm ax7 1000111100001... .......... U U U U U U U 18 18 16 16 16 16 16 +sbcd 8 mm ay7 1000...100001111 .......... U U U U U U U 18 18 16 16 16 16 16 +sbcd 8 mm axy7 1000111100001111 .......... U U U U U U U 18 18 16 16 16 16 16 +sbcd 8 mm . 1000...100001... .......... U U U U U U U 18 18 16 16 16 16 16 +st 8 . d 0101000011000... .......... U U U U U U U 6 4 4 4 4 4 4 +st 8 . . 0101000011...... A+-DXWL... U U U U U U U 8 8 6 6 6 6 6 +sf 8 . d 0101000111000... .......... U U U U U U U 4 4 4 4 4 4 4 +sf 8 . . 0101000111...... A+-DXWL... U U U U U U U 8 8 6 6 6 6 6 +scc 8 . d 0101....11000... .......... U U U U U U U 4 4 4 4 4 4 4 +scc 8 . . 0101....11...... A+-DXWL... U U U U U U U 8 8 6 6 6 6 6 +stop 0 . . 0100111001110010 .......... S S S S S S S 4 4 8 8 8 8 8 +sub 8 er d 1001...000000... .......... U U U U U U U 4 4 2 2 2 2 2 +sub 8 er . 1001...000...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2 +sub 16 er d 1001...001000... .......... U U U U U U U 4 4 2 2 2 2 2 +sub 16 er a 1001...001001... .......... U U U U U U U 4 4 2 2 2 2 2 +sub 16 er . 1001...001...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2 +sub 32 er d 1001...010000... .......... U U U U U U U 6 6 2 2 2 2 2 +sub 32 er a 1001...010001... .......... U U U U U U U 6 6 2 2 2 2 2 +sub 32 er . 1001...010...... A+-DXWLdxI U U U U U U U 6 6 2 2 2 2 2 +sub 8 re . 1001...100...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +sub 16 re . 1001...101...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +sub 32 re . 1001...110...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +suba 16 . d 1001...011000... .......... U U U U U U U 8 8 2 2 2 2 2 +suba 16 . a 1001...011001... .......... U U U U U U U 8 8 2 2 2 2 2 +suba 16 . . 1001...011...... A+-DXWLdxI U U U U U U U 8 8 2 2 2 2 2 +suba 32 . d 1001...111000... .......... U U U U U U U 6 6 2 2 2 2 2 +suba 32 . a 1001...111001... .......... U U U U U U U 6 6 2 2 2 2 2 +suba 32 . . 1001...111...... A+-DXWLdxI U U U U U U U 6 6 2 2 2 2 2 +subi 8 . d 0000010000000... .......... U U U U U U U 8 8 2 2 2 2 2 +subi 8 . . 0000010000...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +subi 16 . d 0000010001000... .......... U U U U U U U 8 8 2 2 2 2 2 +subi 16 . . 0000010001...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +subi 32 . d 0000010010000... .......... U U U U U U U 16 14 2 2 2 2 2 +subi 32 . . 0000010010...... A+-DXWL... U U U U U U U 20 20 4 4 4 4 4 +subq 8 . d 0101...100000... .......... U U U U U U U 4 4 2 2 2 2 2 +subq 8 . . 0101...100...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +subq 16 . d 0101...101000... .......... U U U U U U U 4 4 2 2 2 2 2 +subq 16 . a 0101...101001... .......... U U U U U U U 8 4 2 2 2 2 2 +subq 16 . . 0101...101...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4 +subq 32 . d 0101...110000... .......... U U U U U U U 8 8 2 2 2 2 2 +subq 32 . a 0101...110001... .......... U U U U U U U 8 8 2 2 2 2 2 +subq 32 . . 0101...110...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4 +subx 8 rr . 1001...100000... .......... U U U U U U U 4 4 2 2 2 2 2 +subx 16 rr . 1001...101000... .......... U U U U U U U 4 4 2 2 2 2 2 +subx 32 rr . 1001...110000... .......... U U U U U U U 8 6 2 2 2 2 2 +subx 8 mm ax7 1001111100001... .......... U U U U U U U 18 18 12 12 12 12 12 +subx 8 mm ay7 1001...100001111 .......... U U U U U U U 18 18 12 12 12 12 12 +subx 8 mm axy7 1001111100001111 .......... U U U U U U U 18 18 12 12 12 12 12 +subx 8 mm . 1001...100001... .......... U U U U U U U 18 18 12 12 12 12 12 +subx 16 mm . 1001...101001... .......... U U U U U U U 18 18 12 12 12 12 12 +subx 32 mm . 1001...110001... .......... U U U U U U U 30 30 12 12 12 12 12 +swap 32 . . 0100100001000... .......... U U U U U U U 4 4 4 4 4 4 4 +tas 8 . d 0100101011000... .......... U U U U U U U 4 4 4 4 4 4 4 +tas 8 . . 0100101011...... A+-DXWL... U U U U U U U 14 14 12 12 12 12 12 +trap 0 . . 010011100100.... .......... U U U U U U U 4 4 4 4 4 4 4 +trapt 0 . . 0101000011111100 .......... . . U U U U U . . 4 4 4 4 4 +trapt 16 . . 0101000011111010 .......... . . U U U U U . . 6 6 6 6 6 +trapt 32 . . 0101000011111011 .......... . . U U U U U . . 8 8 8 8 8 +trapf 0 . . 0101000111111100 .......... . . U U U U U . . 4 4 4 4 4 +trapf 16 . . 0101000111111010 .......... . . U U U U U . . 6 6 6 6 6 +trapf 32 . . 0101000111111011 .......... . . U U U U U . . 8 8 8 8 8 +trapcc 0 . . 0101....11111100 .......... . . U U U U U . . 4 4 4 4 4 +trapcc 16 . . 0101....11111010 .......... . . U U U U U . . 6 6 6 6 6 +trapcc 32 . . 0101....11111011 .......... . . U U U U U . . 8 8 8 8 8 +trapv 0 . . 0100111001110110 .......... U U U U U U U 4 4 4 4 4 4 4 +tst 8 . d 0100101000000... .......... U U U U U U U 4 4 2 2 2 2 2 +tst 8 . . 0100101000...... A+-DXWL... U U U U U U U 4 4 2 2 2 2 2 +tst 8 . pcdi 0100101000111010 .......... . . U U U U U . . 7 7 7 7 7 +tst 8 . pcix 0100101000111011 .......... . . U U U U U . . 9 9 9 9 9 +tst 8 . i 0100101000111100 .......... . . U U U U U . . 6 6 6 6 6 +tst 16 . d 0100101001000... .......... U U U U U U U 4 4 2 2 2 2 2 +tst 16 . a 0100101001001... .......... . . U U U U U . . 2 2 2 2 2 +tst 16 . . 0100101001...... A+-DXWL... U U U U U U U 4 4 2 2 2 2 2 +tst 16 . pcdi 0100101001111010 .......... . . U U U U U . . 7 7 7 7 7 +tst 16 . pcix 0100101001111011 .......... . . U U U U U . . 9 9 9 9 9 +tst 16 . i 0100101001111100 .......... . . U U U U U . . 6 6 6 6 6 +tst 32 . d 0100101010000... .......... U U U U U U U 4 4 2 2 2 2 2 +tst 32 . a 0100101010001... .......... . . U U U U U . . 2 2 2 2 2 +tst 32 . . 0100101010...... A+-DXWL... U U U U U U U 4 4 2 2 2 2 2 +tst 32 . pcdi 0100101010111010 .......... . . U U U U U . . 7 7 7 7 7 +tst 32 . pcix 0100101010111011 .......... . . U U U U U . . 9 9 9 9 9 +tst 32 . i 0100101010111100 .......... . . U U U U U . . 6 6 6 6 6 +unlk 32 . a7 0100111001011111 .......... U U U U U U U 12 12 6 6 6 6 6 +unlk 32 . . 0100111001011... .......... U U U U U U U 12 12 6 6 6 6 6 +unpk 16 rr . 1000...110000... .......... . . U U U U U . . 8 8 8 8 8 +unpk 16 mm ax7 1000111110001... .......... . . U U U U U . . 13 13 13 13 13 +unpk 16 mm ay7 1000...110001111 .......... . . U U U U U . . 13 13 13 13 13 +unpk 16 mm axy7 1000111110001111 .......... . . U U U U U . . 13 13 13 13 13 +unpk 16 mm . 1000...110001... .......... . . U U U U U . . 13 13 13 13 13 @@ -4397,7 +4397,7 @@ M68KMAKE_OP(cpdbcc, 32, ., .) M68KMAKE_OP(cpgen, 32, ., .) { - if(CPU_TYPE_IS_EC020_PLUS((mc68kcpu)->cpu_type) && (mc68kcpu->has_fpu || mc68kcpu->has_pmmu)) + if(CPU_TYPE_IS_EC020_PLUS((mc68kcpu)->cpu_type)) { logerror("%s at %08x: called unimplemented instruction %04x (cpgen)\n", (mc68kcpu)->device->tag(), REG_PC(mc68kcpu) - 2, (mc68kcpu)->ir); @@ -6591,18 +6591,28 @@ M68KMAKE_OP(movec, 32, cr, .) } m68ki_exception_illegal(mc68kcpu); return; - case 0x004: /* ITT0 */ + case 0x004: /* ITT0 (040+, ACR0 on ColdFire) */ if(CPU_TYPE_IS_040_PLUS((mc68kcpu)->cpu_type)) { - /* TODO */ + REG_DA(mc68kcpu)[(word2 >> 12) & 15] = mc68kcpu->mmu_itt0; + return; + } + else if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + REG_DA(mc68kcpu)[(word2 >> 12) & 15] = mc68kcpu->mmu_acr0; return; } m68ki_exception_illegal(mc68kcpu); return; - case 0x005: /* ITT1 */ + case 0x005: /* ITT1 (040+, ACR1 on ColdFire) */ if(CPU_TYPE_IS_040_PLUS((mc68kcpu)->cpu_type)) { - /* TODO */ + REG_DA(mc68kcpu)[(word2 >> 12) & 15] = mc68kcpu->mmu_itt1; + return; + } + else if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + REG_DA(mc68kcpu)[(word2 >> 12) & 15] = mc68kcpu->mmu_acr1; return; } m68ki_exception_illegal(mc68kcpu); @@ -6610,7 +6620,12 @@ M68KMAKE_OP(movec, 32, cr, .) case 0x006: /* DTT0 */ if(CPU_TYPE_IS_040_PLUS((mc68kcpu)->cpu_type)) { - /* TODO */ + REG_DA(mc68kcpu)[(word2 >> 12) & 15] = mc68kcpu->mmu_dtt0; + return; + } + else if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + REG_DA(mc68kcpu)[(word2 >> 12) & 15] = mc68kcpu->mmu_acr2; return; } m68ki_exception_illegal(mc68kcpu); @@ -6618,7 +6633,12 @@ M68KMAKE_OP(movec, 32, cr, .) case 0x007: /* DTT1 */ if(CPU_TYPE_IS_040_PLUS((mc68kcpu)->cpu_type)) { - /* TODO */ + REG_DA(mc68kcpu)[(word2 >> 12) & 15] = mc68kcpu->mmu_dtt1; + return; + } + else if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + REG_DA(mc68kcpu)[(word2 >> 12) & 15] = mc68kcpu->mmu_acr3; return; } m68ki_exception_illegal(mc68kcpu); @@ -6647,6 +6667,70 @@ M68KMAKE_OP(movec, 32, cr, .) } m68ki_exception_illegal(mc68kcpu); return; + case 0xc00: // ROMBAR0 + if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(mc68kcpu); + return; + case 0xc01: // ROMBAR1 + if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(mc68kcpu); + return; + case 0xc04: // RAMBAR0 + if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(mc68kcpu); + return; + case 0xc05: // RAMBAR1 + if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(mc68kcpu); + return; + case 0xc0c: // MPCR + if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(mc68kcpu); + return; + case 0xc0d: // EDRAMBAR + if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(mc68kcpu); + return; + case 0xc0e: // SECMBAR + if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(mc68kcpu); + return; + case 0xc0f: // MBAR + if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(mc68kcpu); + return; default: m68ki_exception_illegal(mc68kcpu); return; @@ -6755,7 +6839,12 @@ M68KMAKE_OP(movec, 32, rc, .) case 0x004: /* ITT0 */ if (CPU_TYPE_IS_040_PLUS((mc68kcpu)->cpu_type)) { - /* TODO */ + mc68kcpu->mmu_itt0 = REG_DA(mc68kcpu)[(word2 >> 12) & 15]; + return; + } + else if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + mc68kcpu->mmu_acr0 = REG_DA(mc68kcpu)[(word2 >> 12) & 15]; return; } m68ki_exception_illegal(mc68kcpu); @@ -6763,7 +6852,12 @@ M68KMAKE_OP(movec, 32, rc, .) case 0x005: /* ITT1 */ if (CPU_TYPE_IS_040_PLUS((mc68kcpu)->cpu_type)) { - /* TODO */ + mc68kcpu->mmu_itt1 = REG_DA(mc68kcpu)[(word2 >> 12) & 15]; + return; + } + else if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + mc68kcpu->mmu_acr1 = REG_DA(mc68kcpu)[(word2 >> 12) & 15]; return; } m68ki_exception_illegal(mc68kcpu); @@ -6771,7 +6865,12 @@ M68KMAKE_OP(movec, 32, rc, .) case 0x006: /* DTT0 */ if (CPU_TYPE_IS_040_PLUS((mc68kcpu)->cpu_type)) { - /* TODO */ + mc68kcpu->mmu_dtt0 = REG_DA(mc68kcpu)[(word2 >> 12) & 15]; + return; + } + else if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + mc68kcpu->mmu_acr2 = REG_DA(mc68kcpu)[(word2 >> 12) & 15]; return; } m68ki_exception_illegal(mc68kcpu); @@ -6779,7 +6878,12 @@ M68KMAKE_OP(movec, 32, rc, .) case 0x007: /* DTT1 */ if (CPU_TYPE_IS_040_PLUS((mc68kcpu)->cpu_type)) { - /* TODO */ + mc68kcpu->mmu_dtt1 = REG_DA(mc68kcpu)[(word2 >> 12) & 15]; + return; + } + else if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + mc68kcpu->mmu_acr3 = REG_DA(mc68kcpu)[(word2 >> 12) & 15]; return; } m68ki_exception_illegal(mc68kcpu); @@ -6808,6 +6912,70 @@ M68KMAKE_OP(movec, 32, rc, .) } m68ki_exception_illegal(mc68kcpu); return; + case 0xc00: // ROMBAR0 + if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(mc68kcpu); + return; + case 0xc01: // ROMBAR1 + if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(mc68kcpu); + return; + case 0xc04: // RAMBAR0 + if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(mc68kcpu); + return; + case 0xc05: // RAMBAR1 + if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(mc68kcpu); + return; + case 0xc0c: // MPCR + if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(mc68kcpu); + return; + case 0xc0d: // EDRAMBAR + if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(mc68kcpu); + return; + case 0xc0e: // SECMBAR + if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(mc68kcpu); + return; + case 0xc0f: // MBAR + if(CPU_TYPE_IS_COLDFIRE((mc68kcpu)->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(mc68kcpu); + return; default: m68ki_exception_illegal(mc68kcpu); return; diff --git a/src/emu/cpu/m68000/m68kcpu.c b/src/emu/cpu/m68000/m68kcpu.c index 09ea02d9199..712d46ccc70 100644 --- a/src/emu/cpu/m68000/m68kcpu.c +++ b/src/emu/cpu/m68000/m68kcpu.c @@ -5,8 +5,8 @@ #if 0 static const char copyright_notice[] = "MUSASHI\n" -"Version 4.80 (2010-08-27)\n" -"A portable Motorola M68xxx processor emulation engine.\n" +"Version 4.90 (2011-09-22)\n" +"A portable Motorola M68xxx/CPU32/ColdFire processor emulation engine.\n" "Copyright Karl Stenerud. All rights reserved.\n" "\n" "This code may be freely used for non-commercial purpooses as long as this\n" @@ -89,7 +89,7 @@ const UINT32 m68ki_shift_32_table[65] = /* Number of clock cycles to use for exception processing. * I used 4 for any vectors that are undocumented for processing times. */ -const UINT8 m68ki_exception_cycle_table[6][256] = +const UINT8 m68ki_exception_cycle_table[7][256] = { { /* 000 */ 40, /* 0: Reset - Initial Stack Pointer */ @@ -529,6 +529,79 @@ const UINT8 m68ki_exception_cycle_table[6][256] = 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4 }, + { /* ColdFire - not correct */ + 4, /* 0: Reset - Initial Stack Pointer */ + 4, /* 1: Reset - Initial Program Counter */ + 50, /* 2: Bus Error (unemulated) */ + 50, /* 3: Address Error (unemulated) */ + 20, /* 4: Illegal Instruction */ + 38, /* 5: Divide by Zero */ + 40, /* 6: CHK */ + 20, /* 7: TRAPV */ + 34, /* 8: Privilege Violation */ + 25, /* 9: Trace */ + 20, /* 10: 1010 */ + 20, /* 11: 1111 */ + 4, /* 12: RESERVED */ + 4, /* 13: Coprocessor Protocol Violation (unemulated) */ + 4, /* 14: Format Error */ + 30, /* 15: Uninitialized Interrupt */ + 4, /* 16: RESERVED */ + 4, /* 17: RESERVED */ + 4, /* 18: RESERVED */ + 4, /* 19: RESERVED */ + 4, /* 20: RESERVED */ + 4, /* 21: RESERVED */ + 4, /* 22: RESERVED */ + 4, /* 23: RESERVED */ + 30, /* 24: Spurious Interrupt */ + 30, /* 25: Level 1 Interrupt Autovector */ + 30, /* 26: Level 2 Interrupt Autovector */ + 30, /* 27: Level 3 Interrupt Autovector */ + 30, /* 28: Level 4 Interrupt Autovector */ + 30, /* 29: Level 5 Interrupt Autovector */ + 30, /* 30: Level 6 Interrupt Autovector */ + 30, /* 31: Level 7 Interrupt Autovector */ + 20, /* 32: TRAP #0 */ + 20, /* 33: TRAP #1 */ + 20, /* 34: TRAP #2 */ + 20, /* 35: TRAP #3 */ + 20, /* 36: TRAP #4 */ + 20, /* 37: TRAP #5 */ + 20, /* 38: TRAP #6 */ + 20, /* 39: TRAP #7 */ + 20, /* 40: TRAP #8 */ + 20, /* 41: TRAP #9 */ + 20, /* 42: TRAP #10 */ + 20, /* 43: TRAP #11 */ + 20, /* 44: TRAP #12 */ + 20, /* 45: TRAP #13 */ + 20, /* 46: TRAP #14 */ + 20, /* 47: TRAP #15 */ + 4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */ + 4, /* 49: FP Inexact Result (unemulated) */ + 4, /* 50: FP Divide by Zero (unemulated) */ + 4, /* 51: FP Underflow (unemulated) */ + 4, /* 52: FP Operand Error (unemulated) */ + 4, /* 53: FP Overflow (unemulated) */ + 4, /* 54: FP Signaling NAN (unemulated) */ + 4, /* 55: FP Unimplemented Data Type (unemulated) */ + 4, /* 56: MMU Configuration Error (unemulated) */ + 4, /* 57: MMU Illegal Operation Error (unemulated) */ + 4, /* 58: MMU Access Level Violation Error (unemulated) */ + 4, /* 59: RESERVED */ + 4, /* 60: RESERVED */ + 4, /* 61: RESERVED */ + 4, /* 62: RESERVED */ + 4, /* 63: RESERVED */ + /* 64-255: User Defined */ + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4 + }, }; const UINT8 m68ki_ea_idx_cycle_table[64] = @@ -581,6 +654,7 @@ INLINE m68ki_cpu_core *get_safe_token(device_t *device) device->type() == M68EC040 || device->type() == M68040 || device->type() == SCC68070 || + device->type() == COLDFIRE || device->type() == M68340); return (m68ki_cpu_core *)downcast<legacy_cpu_device *>(device)->token(); } @@ -1154,7 +1228,7 @@ static CPU_GET_INFO( m68k ) /* --- the following bits of info are returned as NULL-terminated strings --- */ case DEVINFO_STR_NAME: /* set per-core */ break; case DEVINFO_STR_FAMILY: strcpy(info->s, "Motorola 68K"); break; - case DEVINFO_STR_VERSION: strcpy(info->s, "4.60"); break; + case DEVINFO_STR_VERSION: strcpy(info->s, "4.90"); break; case DEVINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; case DEVINFO_STR_CREDITS: strcpy(info->s, "Copyright Karl Stenerud. All rights reserved. (2.1 fixes HJB, FPU+MMU by RB+HO)"); break; } @@ -2367,7 +2441,62 @@ CPU_GET_INFO( m68340 ) } } +/* + ColdFire + +*/ +static CPU_INIT( coldfire ) +{ + m68ki_cpu_core *m68k = get_safe_token(device); + + CPU_INIT_CALL(m68k); + + m68k->cpu_type = CPU_TYPE_COLDFIRE; + m68k->dasm_type = M68K_CPU_TYPE_COLDFIRE; +// hack alert: we use placement new to ensure we are properly initialized +// because we live in the device state which is allocated as bytes +// remove me when we have a real C++ device + new(&m68k->memory) m68k_memory_interface; + m68k->memory.init32(*m68k->program); + m68k->sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */ + m68k->jump_table = m68ki_instruction_jump_table[6]; + m68k->cyc_instruction = m68ki_cycles[6]; + m68k->cyc_exception = m68ki_exception_cycle_table[6]; + m68k->cyc_bcc_notake_b = -2; + m68k->cyc_bcc_notake_w = 0; + m68k->cyc_dbcc_f_noexp = 0; + m68k->cyc_dbcc_f_exp = 4; + m68k->cyc_scc_r_true = 0; + m68k->cyc_movem_w = 2; + m68k->cyc_movem_l = 2; + m68k->cyc_shift = 0; + m68k->cyc_reset = 518; + + define_state(device); +} + +CPU_GET_INFO( mcf5206e ) +{ + switch (state) + { + /* --- the following bits of info are returned as 64-bit signed integers --- */ + case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 20; break; + case CPUINFO_INT_MIN_CYCLES: info->i = 2; break; + case CPUINFO_INT_MAX_CYCLES: info->i = 158; break; + + case DEVINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 32; break; + case DEVINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break; + + /* --- the following bits of info are returned as pointers to data or functions --- */ + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(coldfire); break; + + /* --- the following bits of info are returned as NULL-terminated strings --- */ + case DEVINFO_STR_NAME: strcpy(info->s, "MCF5206E"); break; + + default: CPU_GET_INFO_CALL(m68k); break; + } +} DEFINE_LEGACY_CPU_DEVICE(M68000, m68000); DEFINE_LEGACY_CPU_DEVICE(M68008, m68008); @@ -2383,4 +2512,5 @@ DEFINE_LEGACY_CPU_DEVICE(M68LC040, m68lc040); DEFINE_LEGACY_CPU_DEVICE(M68040, m68040); DEFINE_LEGACY_CPU_DEVICE(SCC68070, scc68070); DEFINE_LEGACY_CPU_DEVICE(M68340, m68340); +DEFINE_LEGACY_CPU_DEVICE(MCF5206E, mcf5206e); diff --git a/src/emu/cpu/m68000/m68kcpu.h b/src/emu/cpu/m68000/m68kcpu.h index 5ea17526079..f1d1dde725d 100644 --- a/src/emu/cpu/m68000/m68kcpu.h +++ b/src/emu/cpu/m68000/m68kcpu.h @@ -87,6 +87,7 @@ typedef struct _m68ki_cpu_core m68ki_cpu_core; #define CPU_TYPE_040 (0x00000200) #define CPU_TYPE_SCC070 (0x00000400) #define CPU_TYPE_68340 (0x00000800) +#define CPU_TYPE_COLDFIRE (0x00001000) /* Different ways to stop the CPU */ #define STOP_LEVEL_STOP 1 @@ -234,22 +235,24 @@ typedef struct _m68ki_cpu_core m68ki_cpu_core; /* These defines are dependant on the configuration defines in m68kconf.h */ /* Disable certain comparisons if we're not using all CPU types */ +#define CPU_TYPE_IS_COLDFIRE(A) ((A) & (CPU_TYPE_COLDFIRE)) + #define CPU_TYPE_IS_040_PLUS(A) ((A) & (CPU_TYPE_040 | CPU_TYPE_EC040)) #define CPU_TYPE_IS_040_LESS(A) 1 #define CPU_TYPE_IS_030_PLUS(A) ((A) & (CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040)) #define CPU_TYPE_IS_030_LESS(A) 1 -#define CPU_TYPE_IS_020_PLUS(A) ((A) & (CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_68340)) +#define CPU_TYPE_IS_020_PLUS(A) ((A) & (CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_68340 | CPU_TYPE_COLDFIRE)) #define CPU_TYPE_IS_020_LESS(A) 1 #define CPU_TYPE_IS_020_VARIANT(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_68340)) -#define CPU_TYPE_IS_EC020_PLUS(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_68340)) +#define CPU_TYPE_IS_EC020_PLUS(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_68340 | CPU_TYPE_COLDFIRE)) #define CPU_TYPE_IS_EC020_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010 | CPU_TYPE_EC020)) #define CPU_TYPE_IS_010(A) ((A) == CPU_TYPE_010) -#define CPU_TYPE_IS_010_PLUS(A) ((A) & (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_EC030 | CPU_TYPE_030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_68340)) +#define CPU_TYPE_IS_010_PLUS(A) ((A) & (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_EC030 | CPU_TYPE_030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_68340 | CPU_TYPE_COLDFIRE)) #define CPU_TYPE_IS_010_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010)) #define CPU_TYPE_IS_000(A) ((A) == CPU_TYPE_000 || (A) == CPU_TYPE_008) @@ -694,6 +697,8 @@ public: UINT32 mmu_atc_tag[MMU_ATC_ENTRIES], mmu_atc_data[MMU_ATC_ENTRIES]; UINT32 mmu_atc_rr; UINT32 mmu_tt0, mmu_tt1; + UINT32 mmu_itt0, mmu_itt1, mmu_dtt0, mmu_dtt1; + UINT32 mmu_acr0, mmu_acr1, mmu_acr2, mmu_acr3; UINT16 mmu_tmp_sr; /* temporary hack: status code for ptest and to handle write protection */ UINT16 mmu_tmp_fc; /* temporary hack: function code for the mmu (moves) */ diff --git a/src/emu/cpu/m68000/m68kdasm.c b/src/emu/cpu/m68000/m68kdasm.c index 05ebb1c87d0..94b4ccf5c5d 100644 --- a/src/emu/cpu/m68000/m68kdasm.c +++ b/src/emu/cpu/m68000/m68kdasm.c @@ -82,17 +82,18 @@ #define TYPE_68020 8 #define TYPE_68030 16 #define TYPE_68040 32 -#define TYPE_68340 64 +#define TYPE_68340 64 // (CPU32) +#define TYPE_COLDFIRE 128 #define M68000_ONLY (TYPE_68000 | TYPE_68008) #define M68010_ONLY TYPE_68010 #define M68010_LESS (TYPE_68000 | TYPE_68008 | TYPE_68010) -#define M68010_PLUS (TYPE_68010 | TYPE_68020 | TYPE_68030 | TYPE_68040 | TYPE_68340) +#define M68010_PLUS (TYPE_68010 | TYPE_68020 | TYPE_68030 | TYPE_68040 | TYPE_68340 | TYPE_COLDFIRE) #define M68020_ONLY (TYPE_68020 | TYPE_68340) #define M68020_LESS (TYPE_68010 | TYPE_68020 | TYPE_68340) -#define M68020_PLUS (TYPE_68020 | TYPE_68030 | TYPE_68040 | TYPE_68340) +#define M68020_PLUS (TYPE_68020 | TYPE_68030 | TYPE_68040 | TYPE_68340 | TYPE_COLDFIRE) #define M68030_ONLY TYPE_68030 #define M68030_LESS (TYPE_68010 | TYPE_68020 | TYPE_68030 | TYPE_68340 ) @@ -100,6 +101,7 @@ #define M68040_PLUS TYPE_68040 +#define COLDFIRE TYPE_COLDFIRE /* Extension word formats */ #define EXT_8BIT_DISPLACEMENT(A) ((A)&0xff) @@ -2133,20 +2135,52 @@ static void d68010_movec(void) processor = "4+"; break; case 0x004: - reg_name = "ITT0"; - processor = "4+"; + if(g_cpu_type & COLDFIRE) + { + reg_name = "ACR0"; + processor = "CF"; + } + else + { + reg_name = "ITT0"; + processor = "4+"; + } break; case 0x005: - reg_name = "ITT1"; - processor = "4+"; + if(g_cpu_type & COLDFIRE) + { + reg_name = "ACR1"; + processor = "CF"; + } + else + { + reg_name = "ITT1"; + processor = "4+"; + } break; case 0x006: - reg_name = "DTT0"; - processor = "4+"; + if(g_cpu_type & COLDFIRE) + { + reg_name = "ACR2"; + processor = "CF"; + } + else + { + reg_name = "DTT0"; + processor = "4+"; + } break; case 0x007: - reg_name = "DTT1"; - processor = "4+"; + if(g_cpu_type & COLDFIRE) + { + reg_name = "ACR3"; + processor = "CF"; + } + else + { + reg_name = "DTT1"; + processor = "4+"; + } break; case 0x805: reg_name = "MMUSR"; @@ -2160,6 +2194,38 @@ static void d68010_movec(void) reg_name = "SRP"; processor = "4+"; break; + case 0xc00: + reg_name = "ROMBAR0"; + processor = "CF"; + break; + case 0xc01: + reg_name = "ROMBAR1"; + processor = "CF"; + break; + case 0xc04: + reg_name = "RAMBAR0"; + processor = "CF"; + break; + case 0xc05: + reg_name = "RAMBAR1"; + processor = "CF"; + break; + case 0xc0c: + reg_name = "MPCR"; + processor = "CF"; + break; + case 0xc0d: + reg_name = "EDRAMBAR"; + processor = "CF"; + break; + case 0xc0e: + reg_name = "SECMBAR"; + processor = "CF"; + break; + case 0xc0f: + reg_name = "MBAR"; + processor = "CF"; + break; default: reg_name = make_signed_hex_str_16(extension & 0xfff); processor = "?"; @@ -3759,6 +3825,9 @@ static unsigned int m68k_disassemble(char* str_buff, unsigned int pc, unsigned i case M68K_CPU_TYPE_68340: g_cpu_type = TYPE_68340; break; + case M68K_CPU_TYPE_COLDFIRE: + g_cpu_type = TYPE_COLDFIRE; + break; default: return 0; } @@ -3951,6 +4020,7 @@ unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cp case M68K_CPU_TYPE_68030: case M68K_CPU_TYPE_68EC030: case M68K_CPU_TYPE_68340: + case M68K_CPU_TYPE_COLDFIRE: if(g_instruction_table[instruction] == d68040_cinv) return 0; if(g_instruction_table[instruction] == d68040_cpush) @@ -4035,7 +4105,10 @@ CPU_DISASSEMBLE( m68340 ) return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68340); } -// f028 2215 0008 +CPU_DISASSEMBLE( coldfire ) +{ + return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_COLDFIRE); +} /* ======================================================================== */ /* ============================== END OF FILE ============================= */ diff --git a/src/emu/cpu/m68000/m68kmake.c b/src/emu/cpu/m68000/m68kmake.c index 0981322ed7c..e7b6858cb21 100644 --- a/src/emu/cpu/m68000/m68kmake.c +++ b/src/emu/cpu/m68000/m68kmake.c @@ -3,11 +3,10 @@ /* ======================================================================== */ /* * MUSASHI - * Version 4.80 + * Version 4.90 * * A portable Motorola M680x0 processor emulation engine. * Copyright Karl Stenerud. All rights reserved. - * FPU and MMU by R. Belmont. * * This code may be freely used for non-commercial purposes as long as this * copyright notice remains unaltered in the source code and any binary files @@ -21,11 +20,10 @@ */ /* - * Modified For OpenVMS By: Robert Alan Byer - * byer@mail.ourservers.net - * * 68030 and PMMU by R. Belmont and Hans Ostermeyer - * 68040 and FPU by Ville Linde, R. Belmont, and Hans Ostermeyer + * 68040 and FPU by Ville Linde, R. Belmont, and Hans Ostermeyer + * CPU32 by David Haywood. ColdFire by R. Belmont. + * */ @@ -56,7 +54,7 @@ */ -static const char g_version[] = "4.80"; +static const char g_version[] = "4.90"; /* ======================================================================== */ /* =============================== INCLUDES =============================== */ @@ -139,6 +137,7 @@ enum CPU_TYPE_030, // 3 CPU_TYPE_040, // 4 CPU_TYPE_68340, // 5 + CPU_TYPE_COLDFIRE, // 6 NUM_CPUS }; @@ -1079,9 +1078,11 @@ static void populate_table(void) buff[0] = 0; /* Find the start of the table */ - while(strcmp(buff, ID_TABLE_START) != 0) + while (strncmp(buff, ID_TABLE_START, strlen(ID_TABLE_START)) != 0) + { if(fgetline(buff, MAX_LINE_LENGTH, g_input_file) < 0) error_exit("(table_start) Premature EOF while reading table"); + } /* Process the entire table */ for(op = g_opcode_input_table;;op++) @@ -1246,8 +1247,8 @@ int main(int argc, char *argv[]) int table_body_read = 0; int ophandler_body_read = 0; - printf("\n\tMusashi v%s 68000, 68008, 68010, 68EC020, 68020, 68EC030, 68030, 68EC040, 68040 emulator\n", g_version); - printf("\tCopyright Karl Stenerud\n\n"); + printf("\n\tMusashi v%s 680x0, CPU32, and ColdFire emulator\n", g_version); + printf("\tCopyright Karl Stenerud and the MAME team.\n\n"); /* Check if output path and source for the input file are given */ if(argc > 1) @@ -1257,45 +1258,22 @@ int main(int argc, char *argv[]) for(ptr = strchr(output_path, '\\'); ptr; ptr = strchr(ptr, '\\')) *ptr = '/'; - -#if !(defined(__DECC) && defined(VMS)) - if(output_path[strlen(output_path)-1] != '/') - strcat(output_path, "/"); -#endif } strcpy(g_input_filename, (argc > 2) ? argv[2] : FILENAME_INPUT); -#if defined(__DECC) && defined(VMS) - - /* Open the files we need */ - sprintf(filename, "%s%s", output_path, FILENAME_PROTOTYPE); - if((g_prototype_file = fopen(filename, "w")) == NULL) - perror_exit("Unable to create prototype file (%s)\n", filename); - - sprintf(filename, "%s%s", output_path, FILENAME_TABLE); - if((g_table_file = fopen(filename, "w")) == NULL) - perror_exit("Unable to create table file (%s)\n", filename); - - if((g_input_file=fopen(g_input_filename, "r")) == NULL) - perror_exit("can't open %s for input", g_input_filename); - -#else - - /* Open the files we need */ - sprintf(filename, "%s%s", output_path, FILENAME_PROTOTYPE); + sprintf(filename, "%s/%s", output_path, FILENAME_PROTOTYPE); if((g_prototype_file = fopen(filename, "wt")) == NULL) perror_exit("Unable to create prototype file (%s)\n", filename); - sprintf(filename, "%s%s", output_path, FILENAME_TABLE); + sprintf(filename, "%s/%s", output_path, FILENAME_TABLE); if((g_table_file = fopen(filename, "wt")) == NULL) perror_exit("Unable to create table file (%s)\n", filename); if((g_input_file=fopen(g_input_filename, "rt")) == NULL) perror_exit("can't open %s for input", g_input_filename); -#endif /* Get to the first section of the input file */ section_id[0] = 0; diff --git a/src/emu/cpu/m68000/m68kmmu.h b/src/emu/cpu/m68000/m68kmmu.h index d00f142e66d..7ccf50a7cd1 100644 --- a/src/emu/cpu/m68000/m68kmmu.h +++ b/src/emu/cpu/m68000/m68kmmu.h @@ -148,7 +148,7 @@ void pmmu_atc_add(m68ki_cpu_core *m68k, UINT32 logical, UINT32 physical, int fc) } // add the entry - // logerror("ATC[%2d] add: log %08x -> phys %08x (fc=%d)\n", found, (logical>>ps) << ps, (physical >> ps) << ps, fc); + // printf("ATC[%2d] add: log %08x -> phys %08x (fc=%d)\n", found, (logical>>ps) << ps, (physical >> ps) << ps, fc); m68k->mmu_atc_tag[found] = atc_tag; m68k->mmu_atc_data[found] = (physical >> ps) << (ps-8); @@ -166,7 +166,7 @@ void pmmu_atc_add(m68ki_cpu_core *m68k, UINT32 logical, UINT32 physical, int fc) void pmmu_atc_flush(m68ki_cpu_core *m68k) { int i; - // logerror("ATC flush: pc=%08x\n", REG_PPC(m68k)); + // printf("ATC flush: pc=%08x\n", REG_PPC(m68k)); for (i = 0; i < MMU_ATC_ENTRIES; i++) { @@ -255,13 +255,13 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 fc, U UINT32 address_mask = ((m68k->mmu_tt0 << 8) & 0xff000000) ^ 0xff000000; if ((addr_in & address_mask) == address_base) { -// logerror("PMMU: pc=%x TT0 fc=%x addr_in=%08x address_mask=%08x address_base=%08x\n", m68k->ppc, fc, addr_in, address_mask, address_base); +// printf("PMMU: pc=%x TT0 fc=%x addr_in=%08x address_mask=%08x address_base=%08x\n", m68k->ppc, fc, addr_in, address_mask, address_base); return addr_in; } } // if ((++pmmu_access_count % 10000000) == 0) { -// logerror("pmmu_translate_addr_with_fc: atc usage = %d%%\n", pmmu_atc_count*100/pmmu_access_count); +// printf("pmmu_translate_addr_with_fc: atc usage = %d%%\n", pmmu_atc_count*100/pmmu_access_count); // pmmu_atc_count = pmmu_access_count = 0; // } @@ -298,7 +298,7 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 fc, U m68k->mmu_tmp_sr = M68K_MMU_SR_MODIFIED; } addr_out = (m68k->mmu_atc_data[i] << 8) | (addr_in & ~(~0 << ps)); -// logerror("ATC[%2d] hit: log %08x -> phys %08x pc=%08x fc=%d\n", i, addr_in, addr_out, REG_PPC(m68k), fc); +// printf("ATC[%2d] hit: log %08x -> phys %08x pc=%08x fc=%d\n", i, addr_in, addr_out, REG_PPC(m68k), fc); // pmmu_atc_count++; return addr_out; } @@ -323,7 +323,7 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 fc, U bbits = (m68k->mmu_tc >> 8) & 0xf; cbits = (m68k->mmu_tc >> 4) & 0xf; -// logerror("PMMU: tcr %08x limit %08x aptr %08x is %x abits %d bbits %d cbits %d\n", m68k->mmu_tc, root_limit, root_aptr, is, abits, bbits, cbits); +// printf("PMMU: tcr %08x limit %08x aptr %08x is %x abits %d bbits %d cbits %d\n", m68k->mmu_tc, root_limit, root_aptr, is, abits, bbits, cbits); // get table A offset tofs = (addr_in<<is)>>(32-abits); @@ -338,23 +338,23 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 fc, U case M68K_MMU_DF_DT1: // page descriptor, will cause direct mapping addr_out = tptr + addr_in; -// logerror("PMMU: PC=%x root mode %d (addr_in %08x -> %08x)\n", m68k->ppc, M68K_MMU_DF_DT1, addr_in, addr_out); +// printf("PMMU: PC=%x root mode %d (addr_in %08x -> %08x)\n", m68k->ppc, M68K_MMU_DF_DT1, addr_in, addr_out); return addr_out; case M68K_MMU_DF_DT2: // valid 4 byte descriptors tofs *= 4; -// if (verbose) logerror("PMMU: reading table A entry at %08x\n", tofs + tptr); +// if (verbose) printf("PMMU: reading table A entry at %08x\n", tofs + tptr); tbl_entry = get_dt2_table_entry(m68k, tptr + tofs, ptest); tamode = tbl_entry & M68K_MMU_DF_DT; -// if (verbose) logerror("PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tamode, tofs); +// if (verbose) printf("PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tamode, tofs); break; case M68K_MMU_DF_DT3: // valid 8 byte descriptors tofs *= 8; -// if (verbose) logerror("PMMU: reading table A entries at %08x\n", tofs + tptr); +// if (verbose) printf("PMMU: reading table A entries at %08x\n", tofs + tptr); tbl_entry = get_dt3_table_entry(m68k, tofs + tptr, fc, ptest); tamode = tbl_entry & M68K_MMU_DF_DT; -// if (verbose) logerror("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tamode, tofs); +// if (verbose) printf("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tamode, tofs); break; } @@ -376,19 +376,19 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 fc, U case M68K_MMU_DF_DT2: // 4-byte table B descriptor tofs *= 4; -// if (verbose) logerror("PMMU: reading table B entry at %08x\n", tofs + tptr); +// if (verbose) printf("PMMU: reading table B entry at %08x\n", tofs + tptr); tbl_entry = get_dt2_table_entry(m68k, tptr + tofs, ptest); tbmode = tbl_entry & M68K_MMU_DF_DT; -// if (verbose) logerror("PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tbmode, tofs); +// if (verbose) printf("PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tbmode, tofs); break; case M68K_MMU_DF_DT3: // 8-byte table B descriptor tofs *= 8; -// if (verbose) logerror("PMMU: reading table B entries at %08x\n", tofs + tptr); +// if (verbose) printf("PMMU: reading table B entries at %08x\n", tofs + tptr); tbl_entry = get_dt3_table_entry(m68k, tptr + tofs, fc, ptest); tbmode = tbl_entry & M68K_MMU_DF_DT; tbl_entry &= ~M68K_MMU_DF_DT; -// if (verbose) logerror("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tbmode, tofs); +// if (verbose) printf("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tbmode, tofs); break; case M68K_MMU_DF_DT1: // early termination descriptor @@ -420,18 +420,18 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 fc, U case M68K_MMU_DF_DT2: // 4-byte table C descriptor tofs *= 4; -// if (verbose) logerror("PMMU: reading table C entry at %08x\n", tofs + tptr); +// if (verbose) printf("PMMU: reading table C entry at %08x\n", tofs + tptr); tbl_entry = get_dt2_table_entry(m68k, tptr + tofs, ptest); tcmode = tbl_entry & M68K_MMU_DF_DT; -// if (verbose) logerror("PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tbmode, tofs); +// if (verbose) printf("PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tbmode, tofs); break; case M68K_MMU_DF_DT3: // 8-byte table C descriptor tofs *= 8; -// if (verbose) logerror("PMMU: reading table C entries at %08x\n", tofs + tptr); +// if (verbose) printf("PMMU: reading table C entries at %08x\n", tofs + tptr); tbl_entry = get_dt3_table_entry(m68k, tptr+ tofs, fc, ptest); tcmode = tbl_entry & M68K_MMU_DF_DT; -// if (verbose) logerror("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tcmode, tofs); +// if (verbose) printf("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tcmode, tofs); break; case M68K_MMU_DF_DT1: // termination descriptor @@ -500,7 +500,7 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 fc, U } } - //logerror("PMMU: [%08x] => [%08x]\n", addr_in, addr_out); + //printf("PMMU: [%08x] => [%08x]\n", addr_in, addr_out); return addr_out; } @@ -513,7 +513,7 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 fc, U UINT32 addr_out = pmmu_translate_addr_with_fc(m68k, addr_in, m68k->mmu_tmp_fc, 0); // if (m68k->mmu_tmp_buserror_occurred > 0) { -// logerror("PMMU: pc=%08x sp=%08x va=%08x pa=%08x - invalid Table mode for level=%d (buserror %d)\n", +// printf("PMMU: pc=%08x sp=%08x va=%08x pa=%08x - invalid Table mode for level=%d (buserror %d)\n", // REG_PPC(m68k), REG_A(m68k)[7], addr_in, addr_out, m68k->mmu_tmp_sr & M68K_MMU_SR_LEVEL_3, // m68k->mmu_tmp_buserror_occurred); // } @@ -532,16 +532,15 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k) UINT32 ea = m68k->ir & 0x3f; UINT64 temp64; - // catch the 2 "weird" encodings up front (PBcc) if ((m68k->ir & 0xffc0) == 0xf0c0) { - logerror("680x0: unhandled PBcc\n"); + printf("680x0: unhandled PBcc\n"); return; } else if ((m68k->ir & 0xffc0) == 0xf080) { - logerror("680x0: unhandled PBcc\n"); + printf("680x0: unhandled PBcc\n"); return; } else // the rest are 1111000xxxXXXXXX where xxx is the instruction family @@ -562,7 +561,7 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k) ptmp = pmmu_translate_addr_with_fc(m68k, ltmp, modes & 0x07, 0); } - logerror("680x0: PLOADing ATC with logical %08x => phys %08x\n", ltmp, ptmp); + printf("680x0: PLOADing ATC with logical %08x => phys %08x\n", ltmp, ptmp); // FIXME: rw bit? pmmu_atc_add(m68k, ltmp, ptmp, modes & 0x07); return; @@ -579,12 +578,12 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k) } else if (modes == 0x2800) // PVALID (FORMAT 1) { - logerror("680x0: unhandled PVALID1\n"); + printf("680x0: unhandled PVALID1\n"); return; } else if ((modes & 0xfff8) == 0x2c00) // PVALID (FORMAT 2) { - logerror("680x0: unhandled PVALID2\n"); + printf("680x0: unhandled PVALID2\n"); return; } else if ((modes & 0xe000) == 0x8000) // PTEST @@ -607,7 +606,7 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k) p_addr = pmmu_translate_addr_with_fc(m68k, v_addr, fc, 1); m68k->mmu_sr = m68k->mmu_tmp_sr; -// logerror("PMMU: pc=%08x sp=%08x va=%08x pa=%08x PTEST fc=%x level=%x mmu_sr=%04x\n", +// printf("PMMU: pc=%08x sp=%08x va=%08x pa=%08x PTEST fc=%x level=%x mmu_sr=%04x\n", // m68k->ppc, REG_A(m68k)[7], v_addr, p_addr, fc, (modes >> 10) & 0x07, m68k->mmu_sr); if (modes & 0x100) @@ -629,29 +628,29 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k) { case 0x02: // transparent translation register 0 WRITE_EA_32(m68k, ea, m68k->mmu_tt0); -// logerror("PMMU: pc=%x PMOVE from mmu_tt0=%08x\n", m68k->ppc, m68k->mmu_tt0); +// printf("PMMU: pc=%x PMOVE from mmu_tt0=%08x\n", m68k->ppc, m68k->mmu_tt0); break; case 0x03: // transparent translation register 1 WRITE_EA_32(m68k, ea, m68k->mmu_tt1); -// logerror("PMMU: pc=%x PMOVE from mmu_tt1=%08x\n", m68k->ppc, m68k->mmu_tt1); +// printf("PMMU: pc=%x PMOVE from mmu_tt1=%08x\n", m68k->ppc, m68k->mmu_tt1); break; case 0x10: // translation control register WRITE_EA_32(m68k, ea, m68k->mmu_tc); -// logerror("PMMU: pc=%x PMOVE from mmu_tc=%08x\n", m68k->ppc, m68k->mmu_tc); +// printf("PMMU: pc=%x PMOVE from mmu_tc=%08x\n", m68k->ppc, m68k->mmu_tc); break; case 0x12: // supervisor root pointer WRITE_EA_64(m68k, ea, (UINT64)m68k->mmu_srp_limit<<32 | (UINT64)m68k->mmu_srp_aptr); -// logerror("PMMU: pc=%x PMOVE from SRP limit = %08x, aptr = %08x\n", REG_PPC(m68k), m68k->mmu_srp_limit, m68k->mmu_srp_aptr); +// printf("PMMU: pc=%x PMOVE from SRP limit = %08x, aptr = %08x\n", REG_PPC(m68k), m68k->mmu_srp_limit, m68k->mmu_srp_aptr); break; case 0x13: // CPU root pointer WRITE_EA_64(m68k, ea, (UINT64)m68k->mmu_crp_limit<<32 | (UINT64)m68k->mmu_crp_aptr); -// logerror("PMMU: pc=%x PMOVE from CRP limit = %08x, aptr = %08x\n", REG_PPC(m68k), m68k->mmu_crp_limit, m68k->mmu_crp_aptr); +// printf("PMMU: pc=%x PMOVE from CRP limit = %08x, aptr = %08x\n", REG_PPC(m68k), m68k->mmu_crp_limit, m68k->mmu_crp_aptr); break; default: - logerror("680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, m68k->pc); + printf("680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, m68k->pc); break; } @@ -676,7 +675,7 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k) break; case 1: - logerror("680x0: unknown PMOVE case 1, PC %x\n", m68k->pc); + printf("680x0: unknown PMOVE case 1, PC %x\n", m68k->pc); break; case 2: @@ -684,17 +683,17 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k) { case 0: // translation control register m68k->mmu_tc = READ_EA_32(m68k, ea); -// logerror("PMMU: TC = %08x\n", m68k->mmu_tc); +// printf("PMMU: TC = %08x\n", m68k->mmu_tc); if (m68k->mmu_tc & 0x80000000) { m68k->pmmu_enabled = 1; -// logerror("PMMU enabled\n"); +// printf("PMMU enabled\n"); } else { m68k->pmmu_enabled = 0; -// logerror("PMMU disabled\n"); +// printf("PMMU disabled\n"); } if (!(modes & 0x100)) // flush ATC on moves to TC, SRP, CRP with FD bit clear @@ -707,7 +706,7 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k) temp64 = READ_EA_64(m68k, ea); m68k->mmu_srp_limit = (temp64>>32) & 0xffffffff; m68k->mmu_srp_aptr = temp64 & 0xffffffff; -// logerror("PMMU: SRP limit = %08x aptr = %08x\n", m68k->mmu_srp_limit, m68k->mmu_srp_aptr); +// printf("PMMU: SRP limit = %08x aptr = %08x\n", m68k->mmu_srp_limit, m68k->mmu_srp_aptr); if (!(modes & 0x100)) { pmmu_atc_flush(m68k); @@ -718,7 +717,7 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k) temp64 = READ_EA_64(m68k, ea); m68k->mmu_crp_limit = (temp64>>32) & 0xffffffff; m68k->mmu_crp_aptr = temp64 & 0xffffffff; -// logerror("PMMU: CRP limit = %08x aptr = %08x\n", m68k->mmu_crp_limit, m68k->mmu_crp_aptr); +// printf("PMMU: CRP limit = %08x aptr = %08x\n", m68k->mmu_crp_limit, m68k->mmu_crp_aptr); if (!(modes & 0x100)) { pmmu_atc_flush(m68k); @@ -726,7 +725,7 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k) break; default: - logerror("680x0: PMOVE to unknown MMU register %x, PC %x\n", (modes>>10) & 7, m68k->pc); + printf("680x0: PMOVE to unknown MMU register %x, PC %x\n", (modes>>10) & 7, m68k->pc); break; } break; @@ -734,7 +733,7 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k) case 3: // MMU status { UINT32 temp = READ_EA_32(m68k, ea); - logerror("680x0: unsupported PMOVE %x to MMU status, PC %x\n", temp, m68k->pc); + printf("680x0: unsupported PMOVE %x to MMU status, PC %x\n", temp, m68k->pc); } break; } @@ -753,7 +752,7 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k) break; default: - logerror("680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes>>13) & 0x7, modes, m68k->pc); + printf("680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes>>13) & 0x7, modes, m68k->pc); break; } @@ -761,7 +760,7 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k) break; default: - logerror("680x0: unknown PMMU instruction group %d\n", (m68k->ir>>9) & 0x7); + printf("680x0: unknown PMMU instruction group %d\n", (m68k->ir>>9) & 0x7); break; } } |