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author mooglyguy <rholtz@batcountryentertainment.com>2014-11-04 14:14:26 +0100
committer mooglyguy <rholtz@batcountryentertainment.com>2014-11-04 14:14:26 +0100
commitbe464dfbfe8ef4a2698d0d479a31ad413412f5c8 (patch)
treee0ea7d4aa1b92500f601e5ab979ea17a275179c6 /src/emu
parent71079121569cf9d5c660ef87571feb68a6c073ad (diff)
mips3: Fixed left-shift-of-signed-value issues. [MooglyGuy]
rsp: Fixed left-shift-of-signed-value issues. [MooglyGuy]
Diffstat (limited to 'src/emu')
-rw-r--r--src/emu/cpu/mips/mips3drc.c2
-rw-r--r--src/emu/cpu/mips/mips3fe.c14
-rw-r--r--src/emu/cpu/rsp/rspfe.c8
3 files changed, 12 insertions, 12 deletions
diff --git a/src/emu/cpu/mips/mips3drc.c b/src/emu/cpu/mips/mips3drc.c
index a6ab28cd68a..8727bc18bd9 100644
--- a/src/emu/cpu/mips/mips3drc.c
+++ b/src/emu/cpu/mips/mips3drc.c
@@ -1387,7 +1387,7 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
case 0x0f: /* LUI - MIPS I */
if (RTREG != 0)
- UML_DMOV(block, R64(RTREG), SIMMVAL << 16); // dmov <rtreg>,SIMMVAL << 16
+ UML_DMOV(block, R64(RTREG), UIMMVAL << 16); // dmov <rtreg>,UIMMVAL << 16
return TRUE;
case 0x08: /* ADDI - MIPS I */
diff --git a/src/emu/cpu/mips/mips3fe.c b/src/emu/cpu/mips/mips3fe.c
index da713856e65..7d031c32407 100644
--- a/src/emu/cpu/mips/mips3fe.c
+++ b/src/emu/cpu/mips/mips3fe.c
@@ -106,7 +106,7 @@ bool mips3_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
desc.regin[0] |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
}
- desc.targetpc = desc.pc + 4 + (SIMMVAL << 2);
+ desc.targetpc = desc.pc + 4 + SIMMVAL * 4;
desc.delayslots = 1;
desc.skipslots = (opswitch & 0x10) ? 1 : 0;
return true;
@@ -122,7 +122,7 @@ bool mips3_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
desc.regin[0] |= REGFLAG_R(RSREG);
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
}
- desc.targetpc = desc.pc + 4 + (SIMMVAL << 2);
+ desc.targetpc = desc.pc + 4 + SIMMVAL * 4;
desc.delayslots = 1;
desc.skipslots = (opswitch & 0x10) ? 1 : 0;
return true;
@@ -396,7 +396,7 @@ bool mips3_frontend::describe_regimm(UINT32 op, opcode_desc &desc)
desc.regin[0] |= REGFLAG_R(RSREG);
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
}
- desc.targetpc = desc.pc + 4 + (SIMMVAL << 2);
+ desc.targetpc = desc.pc + 4 + SIMMVAL * 4;
desc.delayslots = 1;
desc.skipslots = (RTREG & 0x02) ? 1 : 0;
return true;
@@ -423,7 +423,7 @@ bool mips3_frontend::describe_regimm(UINT32 op, opcode_desc &desc)
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
}
desc.regout[0] |= REGFLAG_R(31);
- desc.targetpc = desc.pc + 4 + (SIMMVAL << 2);
+ desc.targetpc = desc.pc + 4 + SIMMVAL * 4;
desc.delayslots = 1;
desc.skipslots = (RTREG & 0x02) ? 1 : 0;
return true;
@@ -508,7 +508,7 @@ bool mips3_frontend::describe_cop0(UINT32 op, opcode_desc &desc)
case 0x00: // BCzF
case 0x01: // BCzT
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
- desc.targetpc = desc.pc + 4 + (SIMMVAL << 2);
+ desc.targetpc = desc.pc + 4 + SIMMVAL * 4;
desc.delayslots = 1;
return true;
}
@@ -580,7 +580,7 @@ bool mips3_frontend::describe_cop1(UINT32 op, opcode_desc &desc)
case 0x03: // BCzTL
desc.regin[2] |= REGFLAG_FCC;
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
- desc.targetpc = desc.pc + 4 + (SIMMVAL << 2);
+ desc.targetpc = desc.pc + 4 + SIMMVAL * 4;
desc.delayslots = 1;
desc.skipslots = (RTREG & 0x02) ? 1 : 0;
return true;
@@ -730,7 +730,7 @@ bool mips3_frontend::describe_cop2(UINT32 op, opcode_desc &desc)
case 0x00: // BCzF
case 0x01: // BCzT
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
- desc.targetpc = desc.pc + 4 + (SIMMVAL << 2);
+ desc.targetpc = desc.pc + 4 + SIMMVAL * 4;
desc.delayslots = 1;
return true;
}
diff --git a/src/emu/cpu/rsp/rspfe.c b/src/emu/cpu/rsp/rspfe.c
index 2d7ae7ae538..bd610bca661 100644
--- a/src/emu/cpu/rsp/rspfe.c
+++ b/src/emu/cpu/rsp/rspfe.c
@@ -83,7 +83,7 @@ bool rsp_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
desc.regin[0] |= REGFLAG_R(RSREG) | REGFLAG_R(RTREG);
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
}
- desc.targetpc = ((desc.pc + 4 + (SIMMVAL << 2)) & 0x00000fff) | 0x1000;
+ desc.targetpc = ((desc.pc + 4 + SIMMVAL * 4) & 0x00000fff) | 0x1000;
desc.delayslots = 1;
desc.skipslots = (opswitch & 0x10) ? 1 : 0;
return true;
@@ -97,7 +97,7 @@ bool rsp_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
desc.regin[0] |= REGFLAG_R(RSREG);
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
}
- desc.targetpc = ((desc.pc + 4 + (SIMMVAL << 2)) & 0x00000fff) | 0x1000;
+ desc.targetpc = ((desc.pc + 4 + SIMMVAL * 4) & 0x00000fff) | 0x1000;
desc.delayslots = 1;
desc.skipslots = (opswitch & 0x10) ? 1 : 0;
return true;
@@ -234,7 +234,7 @@ bool rsp_frontend::describe_regimm(UINT32 op, opcode_desc &desc)
desc.regin[0] |= REGFLAG_R(RSREG);
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
}
- desc.targetpc = ((desc.pc + 4 + (SIMMVAL << 2)) & 0x00000fff) | 0x1000;
+ desc.targetpc = ((desc.pc + 4 + SIMMVAL * 4) & 0x00000fff) | 0x1000;
desc.delayslots = 1;
desc.skipslots = (RTREG & 0x02) ? 1 : 0;
return true;
@@ -249,7 +249,7 @@ bool rsp_frontend::describe_regimm(UINT32 op, opcode_desc &desc)
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
}
desc.regout[0] |= REGFLAG_R(31);
- desc.targetpc = ((desc.pc + 4 + (SIMMVAL << 2)) & 0x00000fff) | 0x1000;
+ desc.targetpc = ((desc.pc + 4 + SIMMVAL * 4) & 0x00000fff) | 0x1000;
desc.delayslots = 1;
desc.skipslots = (RTREG & 0x02) ? 1 : 0;
return true;