diff options
author | 2011-10-10 03:25:08 +0000 | |
---|---|---|
committer | 2011-10-10 03:25:08 +0000 | |
commit | 7df085e6b19a9c6a6809ab0f831649083e08e399 (patch) | |
tree | 32388b9120d95e83b08f0c55b8408391c63bb971 /src/emu | |
parent | b0ea56a2096ba0eb43aef11a7763005286adc0ef (diff) |
Re-hooked inputs from Haze (nw)
Diffstat (limited to 'src/emu')
-rw-r--r-- | src/emu/cpu/sh4/sh3comn.c | 119 | ||||
-rw-r--r-- | src/emu/cpu/sh4/sh3comn.h | 21 |
2 files changed, 131 insertions, 9 deletions
diff --git a/src/emu/cpu/sh4/sh3comn.c b/src/emu/cpu/sh4/sh3comn.c index dbdaaaa3e4e..8e3372c4f8d 100644 --- a/src/emu/cpu/sh4/sh3comn.c +++ b/src/emu/cpu/sh4/sh3comn.c @@ -199,33 +199,82 @@ READ32_HANDLER( sh3_internal_r ) } break; + case PADR_PBDR: + { + if (mem_mask & 0xffff0000) + { + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PADR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); + return sh4->io->read_qword(SH3_PORT_A)<<24; + } + + if (mem_mask & 0x0000ffff) + { + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PBDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); + return sh4->io->read_qword(SH3_PORT_B)<<8; + } + } + break; + + case PCDR_PDDR: + { + if (mem_mask & 0xffff0000) + { + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PCDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); + return sh4->io->read_qword(SH3_PORT_C)<<24; + } + + if (mem_mask & 0x0000ffff) + { + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PDDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); + return sh4->io->read_qword(SH3_PORT_D)<<8; + } + } + break; + case PEDR_PFDR: { if (mem_mask & 0xffff0000) { - logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PEDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return (0x20)<<24; + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PEDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); + return sh4->io->read_qword(SH3_PORT_E)<<24; } if (mem_mask & 0x0000ffff) { - logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PFDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PFDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); + return sh4->io->read_qword(SH3_PORT_F)<<8; } } break; + case PGDR_PHDR: + { + if (mem_mask & 0xffff0000) + { + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PGDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); + return sh4->io->read_qword(SH3_PORT_G)<<24; + } + + if (mem_mask & 0x0000ffff) + { + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PHDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); + return sh4->io->read_qword(SH3_PORT_H)<<8; + } + } + break; case PJDR_PKDR: { if (mem_mask & 0xffff0000) { - logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PJDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return (0x40)<<24; + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PJDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); + return sh4->io->read_qword(SH3_PORT_J)<<24; } if (mem_mask & 0x0000ffff) { - logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PKDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PKDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); + return sh4->io->read_qword(SH3_PORT_K)<<8; } } break; @@ -409,30 +458,82 @@ WRITE32_HANDLER( sh3_internal_w ) } break; + case PADR_PBDR: + { + if (mem_mask & 0xffff0000) + { + sh4->io->write_qword(SH3_PORT_A, (data>>24)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + + if (mem_mask & 0x0000ffff) + { + sh4->io->write_qword(SH3_PORT_B, (data>>8)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + break; + + case PCDR_PDDR: + { + if (mem_mask & 0xffff0000) + { + sh4->io->write_qword(SH3_PORT_C, (data>>24)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + + if (mem_mask & 0x0000ffff) + { + sh4->io->write_qword(SH3_PORT_D, (data>>8)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + break; case PEDR_PFDR: { if (mem_mask & 0xffff0000) { - logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PEDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + sh4->io->write_qword(SH3_PORT_E, (data>>24)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PEDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + + if (mem_mask & 0x0000ffff) + { + sh4->io->write_qword(SH3_PORT_F, (data>>8)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + break; + + case PGDR_PHDR: + { + if (mem_mask & 0xffff0000) + { + sh4->io->write_qword(SH3_PORT_G, (data>>24)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); } if (mem_mask & 0x0000ffff) { - logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + sh4->io->write_qword(SH3_PORT_H, (data>>8)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); } } break; + case PJDR_PKDR: { if (mem_mask & 0xffff0000) { + sh4->io->write_qword(SH3_PORT_J, (data>>24)&0xff); // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); } if (mem_mask & 0x0000ffff) { - logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + sh4->io->write_qword(SH3_PORT_K, (data>>8)&0xff); + //logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); } } break; diff --git a/src/emu/cpu/sh4/sh3comn.h b/src/emu/cpu/sh4/sh3comn.h index f701f3f1bf6..85220ed95dd 100644 --- a/src/emu/cpu/sh4/sh3comn.h +++ b/src/emu/cpu/sh4/sh3comn.h @@ -3,6 +3,23 @@ #ifndef __SH3COMN_H__ #define __SH3COMN_H__ + +// actual port handling is more complex than this +// which should be considered a temporary solution +// just used some arbitrary port nubmers +#define SH3_PORT_A (0x10*8) +#define SH3_PORT_B (0x11*8) +#define SH3_PORT_C (0x12*8) +#define SH3_PORT_D (0x13*8) +#define SH3_PORT_E (0x14*8) +#define SH3_PORT_F (0x15*8) +#define SH3_PORT_G (0x16*8) +#define SH3_PORT_H (0x17*8) +/* no I */ +#define SH3_PORT_J (0x18*8) +#define SH3_PORT_K (0x19*8) +#define SH3_PORT_L (0x1a*8) + /* SH3 lower area regs */ #define SH3_LOWER_REGBASE (0x04000000) @@ -36,7 +53,11 @@ #define PGCR_PHCR ((0x400010c - SH3_LOWER_REGBASE)/4) #define PJCR_PKCR ((0x4000110 - SH3_LOWER_REGBASE)/4) #define PLCR_SCPCR ((0x4000114 - SH3_LOWER_REGBASE)/4) + +#define PADR_PBDR ((0x4000120 - SH3_LOWER_REGBASE)/4) +#define PCDR_PDDR ((0x4000124 - SH3_LOWER_REGBASE)/4) #define PEDR_PFDR ((0x4000128 - SH3_LOWER_REGBASE)/4) +#define PGDR_PHDR ((0x400012c - SH3_LOWER_REGBASE)/4) #define PJDR_PKDR ((0x4000130 - SH3_LOWER_REGBASE)/4) /* SH3 upper area */ |