diff options
author | 2011-10-07 14:19:13 +0000 | |
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committer | 2011-10-07 14:19:13 +0000 | |
commit | 188e8c89bf79397b32a2d942479693c1d9f689c4 (patch) | |
tree | 4c6e58406de8f3997f081bb6e07aaf6f09aff486 /src/emu | |
parent | 56e64fe500334c14aaaa5b417663dbd77023a41c (diff) |
Small timer fix by Haze (no whatsnew)
Diffstat (limited to 'src/emu')
-rw-r--r-- | src/emu/cpu/sh4/sh3comn.c | 12 | ||||
-rw-r--r-- | src/emu/cpu/sh4/sh4tmu.c | 9 |
2 files changed, 15 insertions, 6 deletions
diff --git a/src/emu/cpu/sh4/sh3comn.c b/src/emu/cpu/sh4/sh3comn.c index 1a57ba1caeb..af74162cfd6 100644 --- a/src/emu/cpu/sh4/sh3comn.c +++ b/src/emu/cpu/sh4/sh3comn.c @@ -36,9 +36,9 @@ WRITE32_HANDLER( sh3_internal_high_w ) case SH3_TCNT0_ADDR: sh4_handle_tcnt0_addr_w(sh4, data, mem_mask);break; case SH3_TCNT1_ADDR: sh4_handle_tcnt1_addr_w(sh4, data, mem_mask);break; case SH3_TCNT2_ADDR: sh4_handle_tcnt2_addr_w(sh4, data, mem_mask);break; - case SH3_TCR0_ADDR: sh4_handle_tcr0_addr_w(sh4, data, mem_mask);break; - case SH3_TCR1_ADDR: sh4_handle_tcr1_addr_w(sh4, data, mem_mask);break; - case SH3_TCR2_ADDR: sh4_handle_tcr2_addr_w(sh4, data, mem_mask);break; + case SH3_TCR0_ADDR: sh4_handle_tcr0_addr_w(sh4, data>>16, mem_mask>>16);break; + case SH3_TCR1_ADDR: sh4_handle_tcr1_addr_w(sh4, data>>16, mem_mask>>16);break; + case SH3_TCR2_ADDR: sh4_handle_tcr2_addr_w(sh4, data>>16, mem_mask>>16);break; case SH3_TCPR2_ADDR: sh4_handle_tcpr2_addr_w(sh4,data, mem_mask);break; default: @@ -81,9 +81,9 @@ READ32_HANDLER( sh3_internal_high_r ) case SH3_TCNT0_ADDR: return sh4_handle_tcnt0_addr_r(sh4, mem_mask); case SH3_TCNT1_ADDR: return sh4_handle_tcnt1_addr_r(sh4, mem_mask); case SH3_TCNT2_ADDR: return sh4_handle_tcnt2_addr_r(sh4, mem_mask); - case SH3_TCR0_ADDR: return sh4_handle_tcr0_addr_r(sh4, mem_mask); - case SH3_TCR1_ADDR: return sh4_handle_tcr1_addr_r(sh4, mem_mask); - case SH3_TCR2_ADDR: return sh4_handle_tcr2_addr_r(sh4, mem_mask); + case SH3_TCR0_ADDR: return sh4_handle_tcr0_addr_r(sh4, mem_mask)<<16; + case SH3_TCR1_ADDR: return sh4_handle_tcr1_addr_r(sh4, mem_mask)<<16; + case SH3_TCR2_ADDR: return sh4_handle_tcr2_addr_r(sh4, mem_mask)<<16; case SH3_TCPR2_ADDR: return sh4_handle_tcpr2_addr_r(sh4, mem_mask); diff --git a/src/emu/cpu/sh4/sh4tmu.c b/src/emu/cpu/sh4/sh4tmu.c index 41c62f50eae..318f37ad9d9 100644 --- a/src/emu/cpu/sh4/sh4tmu.c +++ b/src/emu/cpu/sh4/sh4tmu.c @@ -99,17 +99,26 @@ TIMER_CALLBACK( sh4_timer_callback ) { case 0: if (sh4->SH4_TCR0 & 0x20) + { sh4_exception_request(sh4, SH4_INTC_TUNI0); + // logerror("SH4_INTC_TUNI0 requested\n"); + } break; case 1: if (sh4->SH4_TCR1 & 0x20) + { sh4_exception_request(sh4, SH4_INTC_TUNI1); + // logerror("SH4_INTC_TUNI1 requested\n"); + } break; case 2: if (sh4->SH4_TCR2 & 0x20) + { sh4_exception_request(sh4, SH4_INTC_TUNI2); + // logerror("SH4_INTC_TUNI2 requested\n"); + } break; } |