diff options
| author | 2013-09-17 06:47:03 +0000 | |
|---|---|---|
| committer | 2013-09-17 06:47:03 +0000 | |
| commit | 96aa5e1c086b4927456dc88b925d8ec112f0482e (patch) | |
| tree | f59d136c51d4a065f39e3ab0d73981526c4d156b /src/emu/cpu/tms32082 | |
| parent | a7d12daf5b4c3374e8ad47a003ac7fff73d5c8fc (diff) | |
Cleanups and version bumpmame0150
Diffstat (limited to 'src/emu/cpu/tms32082')
| -rw-r--r-- | src/emu/cpu/tms32082/dis_mp.c | 230 | ||||
| -rw-r--r-- | src/emu/cpu/tms32082/dis_pp.c | 142 | ||||
| -rw-r--r-- | src/emu/cpu/tms32082/mp_ops.c | 264 | ||||
| -rw-r--r-- | src/emu/cpu/tms32082/tms32082.c | 46 | ||||
| -rw-r--r-- | src/emu/cpu/tms32082/tms32082.h | 8 |
5 files changed, 345 insertions, 345 deletions
diff --git a/src/emu/cpu/tms32082/dis_mp.c b/src/emu/cpu/tms32082/dis_mp.c index 6c50536ce0a..0bcb5a79788 100644 --- a/src/emu/cpu/tms32082/dis_mp.c +++ b/src/emu/cpu/tms32082/dis_mp.c @@ -16,10 +16,10 @@ static const char *BCND_CONDITION[32] = static const char *BITNUM_CONDITION[32] = { - "eq.b", "ne.b", "gt.b", "le.b", "lt.b", "ge.b", "hi.b", "ls.b", - "lo.b", "hs.b", "eq.h", "ne.h", "gt.h", "le.h", "lt.h", "ge.h", - "hi.h", "ls.h", "lo.h", "hs.h", "eq.w", "ne.w", "gt.w", "le.w", - "lt.w", "ge.w", "hi.w", "ls.w", "lo.w", "hs.w", "?", "?", + "eq.b", "ne.b", "gt.b", "le.b", "lt.b", "ge.b", "hi.b", "ls.b", + "lo.b", "hs.b", "eq.h", "ne.h", "gt.h", "le.h", "lt.h", "ge.h", + "hi.h", "ls.h", "lo.h", "hs.h", "eq.w", "ne.w", "gt.w", "le.w", + "lt.w", "ge.w", "hi.w", "ls.w", "lo.w", "hs.w", "?", "?", }; static const char *MEMOP_S[2] = @@ -156,8 +156,8 @@ static char* format_vector_op(UINT32 op, UINT32 imm32) b += sprintf(b, "vrnd.%s%s 0x%08X, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[pd4], imm32, rs); break; - case 0xca: b += sprintf(b, "vrnd.%s%s R%d, R%d", FLOATOP_PRECISION[2 + p1], FLOATOP_PRECISION[pd2],src1, rs); break; - case 0xcb: b += sprintf(b, "vrnd.%s%s 0x%08X, R%d", FLOATOP_PRECISION[2 + p1], FLOATOP_PRECISION[pd2], imm32, rs); break; + case 0xca: b += sprintf(b, "vrnd.%s%s R%d, R%d", FLOATOP_PRECISION[2 + p1], FLOATOP_PRECISION[pd2],src1, rs); break; + case 0xcb: b += sprintf(b, "vrnd.%s%s 0x%08X, R%d", FLOATOP_PRECISION[2 + p1], FLOATOP_PRECISION[pd2], imm32, rs); break; case 0xcc: case 0xdc: b += sprintf(b, "vmac.ss%s R%d, R%d, %s, %s", FLOATOP_PRECISION[(op >> 9) & 1], src1, rs, z ? "0" : ACC_SEL[acc], (regdest && rd == 0) ? ACC_SEL[acc] : dest); @@ -172,7 +172,7 @@ static char* format_vector_op(UINT32 op, UINT32 imm32) b += sprintf(b, "vmsc.ss%s 0x%08X, R%d, %s, %s", FLOATOP_PRECISION[(op >> 9) & 1], imm32, rs, z ? "0" : ACC_SEL[acc], (regdest && rd == 0) ? ACC_SEL[acc] : dest); break; - default: b += sprintf(b, "?"); break; + default: b += sprintf(b, "?"); break; } // align the line end @@ -183,17 +183,17 @@ static char* format_vector_op(UINT32 op, UINT32 imm32) { b += sprintf(b, " "); } - } + } // optional load/store op switch (vector_ls_bits) { - case 0x01: b += sprintf(b, "|| vst.s R%d", rd); break; - case 0x03: b += sprintf(b, "|| vst.d R%d", rd); break; - case 0x04: b += sprintf(b, "|| vld0.s R%d", rd); break; - case 0x05: b += sprintf(b, "|| vld1.s R%d", rd); break; - case 0x06: b += sprintf(b, "|| vld0.d R%d", rd); break; - case 0x07: b += sprintf(b, "|| vld1.d R%d", rd); break; + case 0x01: b += sprintf(b, "|| vst.s R%d", rd); break; + case 0x03: b += sprintf(b, "|| vst.d R%d", rd); break; + case 0x04: b += sprintf(b, "|| vld0.s R%d", rd); break; + case 0x05: b += sprintf(b, "|| vld1.s R%d", rd); break; + case 0x06: b += sprintf(b, "|| vld0.d R%d", rd); break; + case 0x07: b += sprintf(b, "|| vld1.d R%d", rd); break; } return buffer; @@ -226,30 +226,30 @@ static offs_t tms32082_disasm_mp(char *buffer, offs_t pc, const UINT8 *oprom) switch (subop) { - case 0x00: print("illop0 "); break; - case 0x01: print("trap %d", UIMM15(uimm15)); break; - case 0x02: print("cmnd 0x%04X", UIMM15(uimm15)); break; - case 0x04: print("rdcr %s, R%d", get_creg_name(UIMM15(uimm15)), rd); break; - case 0x05: print("swcr R%d, %s, R%d", rd, get_creg_name(UIMM15(uimm15)), rs); break; - case 0x06: print("brcr %s", get_creg_name(UIMM15(uimm15))); break; - case 0x08: print("shift%s.dz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; - case 0x09: print("shift%s.dm %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; - case 0x0a: print("shift%s.ds %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; - case 0x0b: print("shift%s.ez %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; - case 0x0c: print("shift%s.em %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; - case 0x0d: print("shift%s.es %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; - case 0x0e: print("shift%s.iz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; - case 0x0f: print("shift%s.im %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; - case 0x11: print("and 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; - case 0x12: print("and.tf 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; - case 0x14: print("and.ft 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; - case 0x16: print("xor 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; - case 0x17: print("or 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; - case 0x18: print("and.ff 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; - case 0x19: print("xnor 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; - case 0x1b: print("or.tf 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; - case 0x1d: print("or.ft 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; - case 0x1e: print("or.ff 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; + case 0x00: print("illop0 "); break; + case 0x01: print("trap %d", UIMM15(uimm15)); break; + case 0x02: print("cmnd 0x%04X", UIMM15(uimm15)); break; + case 0x04: print("rdcr %s, R%d", get_creg_name(UIMM15(uimm15)), rd); break; + case 0x05: print("swcr R%d, %s, R%d", rd, get_creg_name(UIMM15(uimm15)), rs); break; + case 0x06: print("brcr %s", get_creg_name(UIMM15(uimm15))); break; + case 0x08: print("shift%s.dz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; + case 0x09: print("shift%s.dm %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; + case 0x0a: print("shift%s.ds %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; + case 0x0b: print("shift%s.ez %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; + case 0x0c: print("shift%s.em %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; + case 0x0d: print("shift%s.es %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; + case 0x0e: print("shift%s.iz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; + case 0x0f: print("shift%s.im %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; + case 0x11: print("and 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; + case 0x12: print("and.tf 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; + case 0x14: print("and.ft 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; + case 0x16: print("xor 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; + case 0x17: print("or 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; + case 0x18: print("and.ff 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; + case 0x19: print("xnor 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; + case 0x1b: print("or.tf 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; + case 0x1d: print("or.ft 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; + case 0x1e: print("or.ff 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break; case 0x24: case 0x20: print("ld.b 0x%04X(R%d%s), R%d", UIMM15(uimm15), rs, MEMOP_M[m], rd); @@ -283,23 +283,23 @@ static offs_t tms32082_disasm_mp(char *buffer, offs_t pc, const UINT8 *oprom) print("st.d R%d, 0x%04X(R%d%s)", rd, UIMM15(uimm15), rs, MEMOP_M[m]); break; - case 0x40: print("bsr 0x%08X, R%d", pc + (SIMM15(uimm15) * 4), link); break; - case 0x41: print("bsr.a 0x%08X, R%d", pc + (SIMM15(uimm15) * 4), link); break; - case 0x44: print("jsr 0x%04X(R%d), R%d", SIMM15(uimm15), rs, link); break; - case 0x45: print("jsr.a 0x%04X(R%d), R%d", SIMM15(uimm15), rs, link); break; - case 0x48: print("bbz 0x%08X, R%d, %s (%d)", pc + (SIMM15(uimm15) * 4), rs, BITNUM_CONDITION[bitnum], bitnum); break; - case 0x49: print("bbz.a 0x%08X, R%d, %s (%d)", pc + (SIMM15(uimm15) * 4), rs, BITNUM_CONDITION[bitnum], bitnum); break; - case 0x4a: print("bbo 0x%08X, R%d, %s (%d)", pc + (SIMM15(uimm15) * 4), rs, BITNUM_CONDITION[bitnum], bitnum); break; - case 0x4b: print("bbo.a 0x%08X, R%d, %s (%d)", pc + (SIMM15(uimm15) * 4), rs, BITNUM_CONDITION[bitnum], bitnum); break; - case 0x4c: print("bcnd 0x%08X, R%d, %s", pc + (SIMM15(uimm15) * 4), rs, BCND_CONDITION[rd]); break; - case 0x4d: print("bcnd.a 0x%08X, R%d, %s", pc + (SIMM15(uimm15) * 4), rs, BCND_CONDITION[rd]); break; - case 0x50: print("cmp 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break; - case 0x58: print("add 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break; - case 0x59: print("addu 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break; - case 0x5a: print("sub 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break; - case 0x5b: print("subu 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break; - - default: print("?"); break; + case 0x40: print("bsr 0x%08X, R%d", pc + (SIMM15(uimm15) * 4), link); break; + case 0x41: print("bsr.a 0x%08X, R%d", pc + (SIMM15(uimm15) * 4), link); break; + case 0x44: print("jsr 0x%04X(R%d), R%d", SIMM15(uimm15), rs, link); break; + case 0x45: print("jsr.a 0x%04X(R%d), R%d", SIMM15(uimm15), rs, link); break; + case 0x48: print("bbz 0x%08X, R%d, %s (%d)", pc + (SIMM15(uimm15) * 4), rs, BITNUM_CONDITION[bitnum], bitnum); break; + case 0x49: print("bbz.a 0x%08X, R%d, %s (%d)", pc + (SIMM15(uimm15) * 4), rs, BITNUM_CONDITION[bitnum], bitnum); break; + case 0x4a: print("bbo 0x%08X, R%d, %s (%d)", pc + (SIMM15(uimm15) * 4), rs, BITNUM_CONDITION[bitnum], bitnum); break; + case 0x4b: print("bbo.a 0x%08X, R%d, %s (%d)", pc + (SIMM15(uimm15) * 4), rs, BITNUM_CONDITION[bitnum], bitnum); break; + case 0x4c: print("bcnd 0x%08X, R%d, %s", pc + (SIMM15(uimm15) * 4), rs, BCND_CONDITION[rd]); break; + case 0x4d: print("bcnd.a 0x%08X, R%d, %s", pc + (SIMM15(uimm15) * 4), rs, BCND_CONDITION[rd]); break; + case 0x50: print("cmp 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break; + case 0x58: print("add 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break; + case 0x59: print("addu 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break; + case 0x5a: print("sub 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break; + case 0x5b: print("subu 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break; + + default: print("?"); break; } break; } @@ -324,16 +324,16 @@ static offs_t tms32082_disasm_mp(char *buffer, offs_t pc, const UINT8 *oprom) switch (subop) { - case 0x02: print("trap %d", src1); break; - case 0x03: print("trap %d", imm32); break; - case 0x04: print("cmnd R%d", src1); break; - case 0x05: print("cmnd 0x%08X", imm32); break; - case 0x08: print("rdcr R%d, R%d,", src1, rd); break; - case 0x09: print("rdcr %s, R%d", get_creg_name(imm32), rd); break; - case 0x0a: print("swcr R%d, R%d, R%d", rd, src1, rs); break; - case 0x0b: print("swcr R%d, %s, R%d", rd, get_creg_name(imm32), rs); break; - case 0x0c: print("brcr R%d", src1); break; - case 0x0d: print("brcr %s", get_creg_name(imm32)); break; + case 0x02: print("trap %d", src1); break; + case 0x03: print("trap %d", imm32); break; + case 0x04: print("cmnd R%d", src1); break; + case 0x05: print("cmnd 0x%08X", imm32); break; + case 0x08: print("rdcr R%d, R%d,", src1, rd); break; + case 0x09: print("rdcr %s, R%d", get_creg_name(imm32), rd); break; + case 0x0a: print("swcr R%d, R%d, R%d", rd, src1, rs); break; + case 0x0b: print("swcr R%d, %s, R%d", rd, get_creg_name(imm32), rs); break; + case 0x0c: print("brcr R%d", src1); break; + case 0x0d: print("brcr %s", get_creg_name(imm32)); break; case 0x10: print("shift%s.dz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; case 0x12: print("shift%s.dm %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break; @@ -434,69 +434,69 @@ static offs_t tms32082_disasm_mp(char *buffer, offs_t pc, const UINT8 *oprom) print("dcache 0x%08X(R%d)", imm32, rs); break; - case 0x80: print("bsr R%d, R%d", src1, link); break; - case 0x81: print("bsr 0x%08X, R%d", imm32, link); break; - case 0x82: print("bsr.a R%d, R%d", src1, rd); break; - case 0x83: print("bsr.a 0x%08X, R%d", imm32, link); break; - case 0x88: print("jsr R%d, R%d", src1, link); break; - case 0x89: print("jsr 0x%08X, R%d", imm32, link); break; - case 0x8a: print("jsr.a R%d, R%d", src1, link); break; - case 0x8b: print("jsr.a 0x%08X, R%d", imm32, link); break; - case 0x90: print("bbz R%d, R%d, %s (%d)", src1, rs, BITNUM_CONDITION[bitnum], bitnum); break; - case 0x91: print("bbz 0x%08X, R%d, %s (%d)", imm32, rs, BITNUM_CONDITION[bitnum], bitnum); break; - case 0x92: print("bbz.a R%d, R%d, %s (%d)", src1, rs, BITNUM_CONDITION[bitnum], bitnum); break; - case 0x93: print("bbz.a 0x%08X, R%d, %s (%d)", imm32, rs, BITNUM_CONDITION[bitnum], bitnum); break; - case 0x94: print("bbo R%d, R%d, %s (%d)", src1, rs, BITNUM_CONDITION[bitnum], bitnum); break; - case 0x95: print("bbo 0x%08X, R%d, %s (%d)", imm32, rs, BITNUM_CONDITION[bitnum], bitnum); break; - case 0x96: print("bbo.a R%d, R%d, %s (%d)", src1, rs, BITNUM_CONDITION[bitnum], bitnum); break; - case 0x97: print("bbo.a 0x%08X, R%d, %s (%d)", imm32, rs, BITNUM_CONDITION[bitnum], bitnum); break; - case 0x98: print("bcnd R%d, R%d, %s", src1, rs, BCND_CONDITION[rd]); break; - case 0x99: print("bcnd 0x%08X, R%d, %s", imm32, rs, BCND_CONDITION[rd]); break; - case 0x9a: print("bcnd.a R%d, R%d, %s", src1, rs, BCND_CONDITION[rd]); break; - case 0x9b: print("bcnd.a 0x%08X, R%d, %s", imm32, rs, BCND_CONDITION[rd]); break; - case 0xa0: print("cmp R%d, R%d, R%d", src1, rs, rd); break; - case 0xa1: print("cmp 0x%08X, R%d, R%d", imm32, rs, rd); break; - case 0xb0: print("add R%d, R%d, R%d", src1, rs, rd); break; - case 0xb1: print("add 0x%08X, R%d, R%d", imm32, rs, rd); break; - case 0xb2: print("addu R%d, R%d, R%d", src1, rs, rd); break; - case 0xb3: print("addu 0x%08X, R%d, R%d", imm32, rs, rd); break; - case 0xb4: print("sub R%d, R%d, R%d", src1, rs, rd); break; - case 0xb5: print("sub 0x%08X, R%d, R%d", imm32, rs, rd); break; - case 0xb6: print("subu R%d, R%d, R%d", src1, rs, rd); break; - case 0xb7: print("subu 0x%08X, R%d, R%d", imm32, rs, rd); break; + case 0x80: print("bsr R%d, R%d", src1, link); break; + case 0x81: print("bsr 0x%08X, R%d", imm32, link); break; + case 0x82: print("bsr.a R%d, R%d", src1, rd); break; + case 0x83: print("bsr.a 0x%08X, R%d", imm32, link); break; + case 0x88: print("jsr R%d, R%d", src1, link); break; + case 0x89: print("jsr 0x%08X, R%d", imm32, link); break; + case 0x8a: print("jsr.a R%d, R%d", src1, link); break; + case 0x8b: print("jsr.a 0x%08X, R%d", imm32, link); break; + case 0x90: print("bbz R%d, R%d, %s (%d)", src1, rs, BITNUM_CONDITION[bitnum], bitnum); break; + case 0x91: print("bbz 0x%08X, R%d, %s (%d)", imm32, rs, BITNUM_CONDITION[bitnum], bitnum); break; + case 0x92: print("bbz.a R%d, R%d, %s (%d)", src1, rs, BITNUM_CONDITION[bitnum], bitnum); break; + case 0x93: print("bbz.a 0x%08X, R%d, %s (%d)", imm32, rs, BITNUM_CONDITION[bitnum], bitnum); break; + case 0x94: print("bbo R%d, R%d, %s (%d)", src1, rs, BITNUM_CONDITION[bitnum], bitnum); break; + case 0x95: print("bbo 0x%08X, R%d, %s (%d)", imm32, rs, BITNUM_CONDITION[bitnum], bitnum); break; + case 0x96: print("bbo.a R%d, R%d, %s (%d)", src1, rs, BITNUM_CONDITION[bitnum], bitnum); break; + case 0x97: print("bbo.a 0x%08X, R%d, %s (%d)", imm32, rs, BITNUM_CONDITION[bitnum], bitnum); break; + case 0x98: print("bcnd R%d, R%d, %s", src1, rs, BCND_CONDITION[rd]); break; + case 0x99: print("bcnd 0x%08X, R%d, %s", imm32, rs, BCND_CONDITION[rd]); break; + case 0x9a: print("bcnd.a R%d, R%d, %s", src1, rs, BCND_CONDITION[rd]); break; + case 0x9b: print("bcnd.a 0x%08X, R%d, %s", imm32, rs, BCND_CONDITION[rd]); break; + case 0xa0: print("cmp R%d, R%d, R%d", src1, rs, rd); break; + case 0xa1: print("cmp 0x%08X, R%d, R%d", imm32, rs, rd); break; + case 0xb0: print("add R%d, R%d, R%d", src1, rs, rd); break; + case 0xb1: print("add 0x%08X, R%d, R%d", imm32, rs, rd); break; + case 0xb2: print("addu R%d, R%d, R%d", src1, rs, rd); break; + case 0xb3: print("addu 0x%08X, R%d, R%d", imm32, rs, rd); break; + case 0xb4: print("sub R%d, R%d, R%d", src1, rs, rd); break; + case 0xb5: print("sub 0x%08X, R%d, R%d", imm32, rs, rd); break; + case 0xb6: print("subu R%d, R%d, R%d", src1, rs, rd); break; + case 0xb7: print("subu 0x%08X, R%d, R%d", imm32, rs, rd); break; case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xd6: case 0xc7: case 0xd7: case 0xc8: case 0xd8: case 0xc9: case 0xd9: - case 0xca: case 0xcb: case 0xcc: case 0xdc: case 0xcd: case 0xdd: case 0xce: case 0xde: + case 0xca: case 0xcb: case 0xcc: case 0xdc: case 0xcd: case 0xdd: case 0xce: case 0xde: case 0xcf: case 0xdf: { print("%s", format_vector_op(op, imm32)); break; } - case 0xe0: print("fadd.%s%s%s R%d, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], src1, rs, rd); break; - case 0xe1: print("fadd.%s%s%s 0x%08X, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], imm32, rs, rd); break; - case 0xe2: print("fsub.%s%s%s R%d, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], src1, rs, rd); break; - case 0xe3: print("fsub.%s%s%s 0x%08X, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], imm32, rs, rd); break; - case 0xe4: print("fmpy.%s%s%s R%d, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], src1, rs, rd); break; - case 0xe5: print("fmpy.%s%s%s 0x%08X, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], imm32, rs, rd); break; - case 0xe6: print("fdiv.%s%s%s R%d, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], src1, rs, rd); break; - case 0xe7: print("fdiv.%s%s%s 0x%08X, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], imm32, rs, rd); break; - case 0xe8: print("frnd%s.%s%s R%d, R%d", FLOATOP_ROUND[rndmode], FLOATOP_PRECISION[p1], FLOATOP_PRECISION[pd], src1, rd); break; - case 0xe9: print("frnd%s.%s%s 0x%08X, R%d", FLOATOP_ROUND[rndmode], FLOATOP_PRECISION[p1], FLOATOP_PRECISION[pd], imm32, rd); break; - case 0xea: print("fcmp R%d, R%d, R%d", src1, rs, rd); break; - case 0xeb: print("fcmp 0x%08X, R%d, R%d", imm32, rs, rd); break; - case 0xee: print("fsqrt R%d, R%d", src1, rd); break; - case 0xef: print("fsqrt 0x%08X, R%d", imm32, rd); break; - case 0xf0: print("lmo R%d, R%d", rs, rd); break; - case 0xf2: print("rmo R%d, R%d", rs, rd); break; - case 0xfc: print("estop "); break; - + case 0xe0: print("fadd.%s%s%s R%d, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], src1, rs, rd); break; + case 0xe1: print("fadd.%s%s%s 0x%08X, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], imm32, rs, rd); break; + case 0xe2: print("fsub.%s%s%s R%d, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], src1, rs, rd); break; + case 0xe3: print("fsub.%s%s%s 0x%08X, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], imm32, rs, rd); break; + case 0xe4: print("fmpy.%s%s%s R%d, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], src1, rs, rd); break; + case 0xe5: print("fmpy.%s%s%s 0x%08X, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], imm32, rs, rd); break; + case 0xe6: print("fdiv.%s%s%s R%d, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], src1, rs, rd); break; + case 0xe7: print("fdiv.%s%s%s 0x%08X, R%d, R%d", FLOATOP_PRECISION[p1], FLOATOP_PRECISION[p2], FLOATOP_PRECISION[pd], imm32, rs, rd); break; + case 0xe8: print("frnd%s.%s%s R%d, R%d", FLOATOP_ROUND[rndmode], FLOATOP_PRECISION[p1], FLOATOP_PRECISION[pd], src1, rd); break; + case 0xe9: print("frnd%s.%s%s 0x%08X, R%d", FLOATOP_ROUND[rndmode], FLOATOP_PRECISION[p1], FLOATOP_PRECISION[pd], imm32, rd); break; + case 0xea: print("fcmp R%d, R%d, R%d", src1, rs, rd); break; + case 0xeb: print("fcmp 0x%08X, R%d, R%d", imm32, rs, rd); break; + case 0xee: print("fsqrt R%d, R%d", src1, rd); break; + case 0xef: print("fsqrt 0x%08X, R%d", imm32, rd); break; + case 0xf0: print("lmo R%d, R%d", rs, rd); break; + case 0xf2: print("rmo R%d, R%d", rs, rd); break; + case 0xfc: print("estop "); break; + case 0xfe: case 0xff: print("illopF "); break; - default: print("?"); break; + default: print("?"); break; } break; } diff --git a/src/emu/cpu/tms32082/dis_pp.c b/src/emu/cpu/tms32082/dis_pp.c index 01397ac39d3..cd63a3c2559 100644 --- a/src/emu/cpu/tms32082/dis_pp.c +++ b/src/emu/cpu/tms32082/dis_pp.c @@ -6,37 +6,37 @@ static const char *REG_NAMES[128] = { // 0 - 15 - "a0", "a1", "a2", "a3", "a4", "???", "a6", "a7", - "a8", "a9", "a10", "a11", "a12", "???", "a14", "a15", + "a0", "a1", "a2", "a3", "a4", "???", "a6", "a7", + "a8", "a9", "a10", "a11", "a12", "???", "a14", "a15", // 16 - 31 - "x0", "x1", "x2", "???", "???", "???", "???", "???", - "x8", "x9", "x10", "???", "???", "???", "???", "???", + "x0", "x1", "x2", "???", "???", "???", "???", "???", + "x8", "x9", "x10", "???", "???", "???", "???", "???", // 32 - 47 - "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", - "???", "sr", "mf", "???", "???", "???", "???", "???", + "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", + "???", "sr", "mf", "???", "???", "???", "???", "???", // 48 - 63 - "???", "???", "???", "???", "???", "???", "???", "???", - "pc/call", "ipa/br", "ipe", "iprs", "inten", "intflg", "comm", "lctl", + "???", "???", "???", "???", "???", "???", "???", "???", + "pc/call", "ipa/br", "ipe", "iprs", "inten", "intflg", "comm", "lctl", // 64 - 79 - "???", "???", "???", "???", "???", "???", "???", "???", - "???", "???", "???", "???", "???", "???", "???", "???", + "???", "???", "???", "???", "???", "???", "???", "???", + "???", "???", "???", "???", "???", "???", "???", "???", // 80 - 95 - "???", "???", "???", "???", "???", "???", "???", "???", - "???", "???", "???", "???", "???", "???", "???", "???", + "???", "???", "???", "???", "???", "???", "???", "???", + "???", "???", "???", "???", "???", "???", "???", "???", // 96 - 111 - "lc0", "lc1", "lc2", "???", "lr0", "lr1", "lr2", "???", - "lrse0", "lrse1", "lrse2", "???", "lrs0", "lrs1", "lrs2", "???", + "lc0", "lc1", "lc2", "???", "lr0", "lr1", "lr2", "???", + "lrse0", "lrse1", "lrse2", "???", "lrs0", "lrs1", "lrs2", "???", // 112 - 127 - "ls0", "ls1", "ls2", "???", "le0", "le1", "le2", "???", - "???", "???", "???", "???", "tag0", "tag1", "tag2", "tag3" + "ls0", "ls1", "ls2", "???", "le0", "le1", "le2", "???", + "???", "???", "???", "???", "tag0", "tag1", "tag2", "tag3" }; static const char *CONDITION_CODES[16] = { - "", "[p] ", "[ls] ", "[hi] ", - "[lt] ", "[le] ", "[ge] ", "[gt] ", - "[hs] ", "[lo] ", "[eq] ", "[ne] ", - "[v] ", "[nv] ", "[n] ", "[nn] " + "", "[p] ", "[ls] ", "[hi] ", + "[lt] ", "[le] ", "[ge] ", "[gt] ", + "[hs] ", "[lo] ", "[eq] ", "[ne] ", + "[v] ", "[nv] ", "[n] ", "[nn] " }; static const char *TRANSFER_SIZE[4] = @@ -103,7 +103,7 @@ static void format_transfer(UINT64 op) switch (gmode) { - case 0x00: // Format 7: Conditional DU || Conditional Move + case 0x00: // Format 7: Conditional DU || Conditional Move { int dstbank = (op >> 18) & 0xf; int srcbank = (op >> 6) & 0xf; @@ -117,14 +117,14 @@ static void format_transfer(UINT64 op) b += sprintf(b, "%s = %s", REG_NAMES[dreg], REG_NAMES[sreg]); break; } - case 0x01: // Format 8: Conditional DU ||Conditional Field Move + case 0x01: // Format 8: Conditional DU ||Conditional Field Move { int dstbank = (op >> 18) & 0xf; int src = (op >> 10) & 0x7; int dst = (op >> 3) & 0x7; int itm = (op >> 22) & 0x3; int size = (op >> 7) & 0x3; - // int e = (op & (1 << 9)); + // int e = (op & (1 << 9)); int dreg = (dstbank << 3) | dst; int sreg = (4 << 3) | src; @@ -133,7 +133,7 @@ static void format_transfer(UINT64 op) b += sprintf(b, "%s = [%s%d]%s", REG_NAMES[dreg], TRANSFER_SIZE[size], itm, REG_NAMES[sreg]); break; } - case 0x02: case 0x03: // Format 10: Conditional Non-D Data Unit + case 0x02: case 0x03: // Format 10: Conditional Non-D Data Unit { int as1bank = (op >> 6) & 0xf; int adstbank = (op >> 18) & 0xf; @@ -156,7 +156,7 @@ static void format_transfer(UINT64 op) } default: { - if (op & 0x4) // Format 9: Conditional DU || Conditional Global + if (op & 0x4) // Format 9: Conditional DU || Conditional Global { int bank = (op >> 18) & 0xf; int le = ((op >> 16) & 2) | ((op >> 9) & 1); @@ -178,7 +178,7 @@ static void format_transfer(UINT64 op) case 3: b += sprintf(b, "%s = &%s%s", REG_NAMES[greg], TRANSFER_SIZE[size], format_address_mode(gmode, ga, s, gimx)); break; } } - else // Format 5: Global (Long Offset) + else // Format 5: Global (Long Offset) { int bank = (op >> 18) & 0xf; int le = ((op >> 16) & 2) | ((op >> 9) & 1); @@ -194,7 +194,7 @@ static void format_transfer(UINT64 op) // sign extend offset if (s && (offset & 0x4000)) offset |= 0xffffc000; - + switch (le) { case 0: b += sprintf(b, "&%s%s = %s", TRANSFER_SIZE[size], format_address_mode(gmode, ga, s, offset), REG_NAMES[greg]); break; @@ -215,17 +215,17 @@ static void format_transfer(UINT64 op) switch (mode) { - case 0x00: // Format 2: Move || Local + case 0x00: // Format 2: Move || Local { b += sprintf(b, "move||local <TODO>"); break; } - case 0x01: // Format 3: Field Move || Local + case 0x01: // Format 3: Field Move || Local { b += sprintf(b, "field move||local <TODO>"); break; } - case 0x02: case 0x03: // Format 6: Non-D DU || Local + case 0x02: case 0x03: // Format 6: Non-D DU || Local { int d = (op >> 32) & 0x7; int s = (op & (1 << 28)); @@ -245,7 +245,7 @@ static void format_transfer(UINT64 op) } break; } - case 0x10: case 0x11: case 0x12: case 0x13: // Format 4: Local (Long Offset) + case 0x10: case 0x11: case 0x12: case 0x13: // Format 4: Local (Long Offset) { int d = (op >> 32) & 0x7; int bank = (op >> 18) & 0xf; @@ -277,7 +277,7 @@ static void format_transfer(UINT64 op) } break; } - case 0x14: case 0x15: case 0x16: case 0x17: // Format 1: Double Parallel + case 0x14: case 0x15: case 0x16: case 0x17: // Format 1: Double Parallel case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: { @@ -329,83 +329,83 @@ static void format_transfer(UINT64 op) static void format_alu_op(int aluop, int a, const char *dst_text, const char *a_text, const char *b_text, const char *c_text) { - if (a) // arithmetic + if (a) // arithmetic { int bits = (aluop & 1) | ((aluop >> 1) & 2) | ((aluop >> 2) & 4) | ((aluop >> 3) & 8); switch (bits) { - case 1: print("%s = %s - %s<1<", dst_text, a_text, b_text); break; - case 2: print("%s = %s + %s<0<", dst_text, a_text, b_text); break; - case 3: print("%s = %s - %s", dst_text, a_text, c_text); break; - case 4: print("%s = %s - %s>1>", dst_text, a_text, b_text); break; - case 5: print("%s = %s - %s", dst_text, a_text, b_text); break; - case 6: print("?"); break; - case 7: print("%s = %s - %s>0>", dst_text, a_text, b_text); break; - case 8: print("%s = %s + %s>0>", dst_text, a_text, b_text); break; - case 9: print("?"); break; - case 10: print("%s = %s + %s", dst_text, a_text, b_text); break; - case 11: print("%s = %s + %s>1>", dst_text, a_text, b_text); break; - case 12: print("%s = %s + %s", dst_text, a_text, c_text); break; - case 13: print("%s = %s - %s<0<", dst_text, a_text, b_text); break; - case 14: print("%s = %s + %s<1<", dst_text, a_text, b_text); break; - case 15: print("%s = field %s + %s", dst_text, a_text, b_text); break; + case 1: print("%s = %s - %s<1<", dst_text, a_text, b_text); break; + case 2: print("%s = %s + %s<0<", dst_text, a_text, b_text); break; + case 3: print("%s = %s - %s", dst_text, a_text, c_text); break; + case 4: print("%s = %s - %s>1>", dst_text, a_text, b_text); break; + case 5: print("%s = %s - %s", dst_text, a_text, b_text); break; + case 6: print("?"); break; + case 7: print("%s = %s - %s>0>", dst_text, a_text, b_text); break; + case 8: print("%s = %s + %s>0>", dst_text, a_text, b_text); break; + case 9: print("?"); break; + case 10: print("%s = %s + %s", dst_text, a_text, b_text); break; + case 11: print("%s = %s + %s>1>", dst_text, a_text, b_text); break; + case 12: print("%s = %s + %s", dst_text, a_text, c_text); break; + case 13: print("%s = %s - %s<0<", dst_text, a_text, b_text); break; + case 14: print("%s = %s + %s<1<", dst_text, a_text, b_text); break; + case 15: print("%s = field %s + %s", dst_text, a_text, b_text); break; } } - else // boolean + else // boolean { switch (aluop) { - case 0xaa: // A & B & C | A & ~B & C | A & B & ~C | A & ~B & ~C = A + case 0xaa: // A & B & C | A & ~B & C | A & B & ~C | A & ~B & ~C = A print("%s = %s", dst_text, a_text); break; - case 0x55: // ~A & B & C | ~A & ~B & C | ~A & B & ~C | ~A & ~B & ~C = ~A + case 0x55: // ~A & B & C | ~A & ~B & C | ~A & B & ~C | ~A & ~B & ~C = ~A print("%s = ~%s", dst_text, a_text); break; - case 0xcc: // A & B & C | ~A & B & C | A & B & ~C | ~A & B & ~C = B + case 0xcc: // A & B & C | ~A & B & C | A & B & ~C | ~A & B & ~C = B print("%s = %s", dst_text, b_text); break; - case 0x33: // A & ~B & C | ~A & ~B & C | A & ~B & ~C | ~A & ~B & ~C = ~B + case 0x33: // A & ~B & C | ~A & ~B & C | A & ~B & ~C | ~A & ~B & ~C = ~B print("%s = %s", dst_text, b_text); break; - case 0xf0: // A & B & C | ~A & B & C | A & ~B & C | ~A & ~B & C = C + case 0xf0: // A & B & C | ~A & B & C | A & ~B & C | ~A & ~B & C = C print("%s = %s", dst_text, c_text); break; - case 0x0f: // A & B & ~C | ~A & B & ~C | A & ~B & ~C | ~A & ~B & ~C = ~C + case 0x0f: // A & B & ~C | ~A & B & ~C | A & ~B & ~C | ~A & ~B & ~C = ~C print("%s = ~%s", dst_text, c_text); break; - case 0x80: // A & B & C + case 0x80: // A & B & C print("%s = %s & %s & %s", dst_text, a_text, b_text, c_text); break; - case 0x88: // A & B & C | A & B & ~C = A & B + case 0x88: // A & B & C | A & B & ~C = A & B print("%s = %s & %s", dst_text, a_text, b_text); break; - case 0xa0: // A & B & C | A & ~B & C = A & C + case 0xa0: // A & B & C | A & ~B & C = A & C print("%s = %s & %s", dst_text, a_text, c_text); break; - case 0xc0: // A & B & C | ~A & B & C = B & C + case 0xc0: // A & B & C | ~A & B & C = B & C print("%s = %s & %s", dst_text, b_text, c_text); break; - case 0xea: // A & B & C | ~A & B & C | A & ~B & C | + case 0xea: // A & B & C | ~A & B & C | A & ~B & C | // A & B & ~C | A & ~B & ~C = A | C print("%s = %s | %s", dst_text, a_text, c_text); break; - case 0xee: // A & B & C | ~A & B & C | A & ~B & C | + case 0xee: // A & B & C | ~A & B & C | A & ~B & C | // A & B & ~C | ~A & B & ~C | A & ~B & ~C = A | B print("%s = %s | %s", dst_text, a_text, b_text); break; - case 0x44: // ~A & B & C | ~A & B & ~C = ~A & B + case 0x44: // ~A & B & C | ~A & B & ~C = ~A & B print("%s = ~%s & %s", dst_text, a_text, b_text); break; @@ -420,14 +420,14 @@ static offs_t tms32082_disasm_pp(char *buffer, offs_t pc, const UINT8 *oprom) { output = buffer; UINT32 flags = 0; - + UINT64 op = ((UINT64)(oprom[0]) << 56) | ((UINT64)(oprom[1]) << 48) | ((UINT64)(oprom[2]) << 40) | ((UINT64)(oprom[3]) << 32) | ((UINT64)(oprom[4]) << 24) | ((UINT64)(oprom[5]) << 16) | ((UINT64)(oprom[6]) << 8) | ((UINT64)(oprom[7])); switch (op >> 60) { case 0x6: - case 0x7: // Six-operand + case 0x7: // Six-operand { print("A: six operand <TODO>"); break; @@ -452,7 +452,7 @@ static offs_t tms32082_disasm_pp(char *buffer, offs_t pc, const UINT8 *oprom) case 0x00: print("nop"); break; case 0x02: print("eint"); break; case 0x03: print("dint"); break; - default: print("<reserved>"); break; + default: print("<reserved>"); break; } format_transfer(parallel_xfer); @@ -467,7 +467,7 @@ static offs_t tms32082_disasm_pp(char *buffer, offs_t pc, const UINT8 *oprom) switch ((op >> 43) & 3) { case 0: - case 1: // Base set ALU (5-bit immediate) + case 1: // Base set ALU (5-bit immediate) { UINT64 parallel_xfer = (op & U64(0x0000007fffffffff)); @@ -545,8 +545,8 @@ static offs_t tms32082_disasm_pp(char *buffer, offs_t pc, const UINT8 *oprom) format_transfer(parallel_xfer); break; } - - case 2: // Base set ALU (reg src2) + + case 2: // Base set ALU (reg src2) { UINT64 parallel_xfer = (op & U64(0x0000007fffffffff)); @@ -625,8 +625,8 @@ static offs_t tms32082_disasm_pp(char *buffer, offs_t pc, const UINT8 *oprom) format_transfer(parallel_xfer); break; } - - case 3: // Base set ALU (32-bit immediate) + + case 3: // Base set ALU (32-bit immediate) { int dst = (op >> 48) & 7; int src1 = (op >> 45) & 7; @@ -709,4 +709,4 @@ static offs_t tms32082_disasm_pp(char *buffer, offs_t pc, const UINT8 *oprom) CPU_DISASSEMBLE(tms32082_pp) { return tms32082_disasm_pp(buffer, pc, oprom); -}
\ No newline at end of file +} diff --git a/src/emu/cpu/tms32082/mp_ops.c b/src/emu/cpu/tms32082/mp_ops.c index b02cc1a5390..5f79cb2379c 100644 --- a/src/emu/cpu/tms32082/mp_ops.c +++ b/src/emu/cpu/tms32082/mp_ops.c @@ -32,7 +32,7 @@ #define SIGN16(x) (((x) & 0x8000) ? 1 : 0) #define SIGN8(x) (((x) & 0x80) ? 1 : 0) -#define SIGN_EXTEND(x, r) ((x) | (((x) & (0x80000000 >> r)) ? ((INT32)(0x80000000) >> r) : 0)) +#define SIGN_EXTEND(x, r) ((x) | (((x) & (0x80000000 >> r)) ? ((INT32)(0x80000000) >> r) : 0)) @@ -95,38 +95,38 @@ UINT32 tms32082_mp_device::calculate_cmp(UINT32 src1, UINT32 src2) UINT32 flags = 0; // 32-bits (bits 20-29) - flags |= ((~c32) & 1) << 29; // higher than or same (C) - flags |= ((c32) & 1) << 28; // lower than (~C) - flags |= ((c32|z32) & 1) << 27; // lower than or same (~C|Z) - flags |= ((~c32&~z32) & 1) << 26; // higher than (C&~Z) - flags |= (((n32&v32)|(~n32&~v32)) & 1) << 25; // greater than or equal (N&V)|(~N&~V) - flags |= (((n32&~v32)|(~n32&v32)) & 1) << 24; // less than (N&~V)|(~N&V) - flags |= (((n32&~v32)|(~n32&v32)|(z32)) & 1) << 23; // less than or equal (N&~V)|(~N&V)|Z - flags |= (((n32&v32&~z32)|(~n32&~v32&~z32)) & 1) << 22; // greater than (N&V&~Z)|(~N&~V&~Z) - flags |= ((~z32) & 1) << 21; // not equal (~Z) - flags |= ((z32) & 1) << 20; // equal (Z) + flags |= ((~c32) & 1) << 29; // higher than or same (C) + flags |= ((c32) & 1) << 28; // lower than (~C) + flags |= ((c32|z32) & 1) << 27; // lower than or same (~C|Z) + flags |= ((~c32&~z32) & 1) << 26; // higher than (C&~Z) + flags |= (((n32&v32)|(~n32&~v32)) & 1) << 25; // greater than or equal (N&V)|(~N&~V) + flags |= (((n32&~v32)|(~n32&v32)) & 1) << 24; // less than (N&~V)|(~N&V) + flags |= (((n32&~v32)|(~n32&v32)|(z32)) & 1) << 23; // less than or equal (N&~V)|(~N&V)|Z + flags |= (((n32&v32&~z32)|(~n32&~v32&~z32)) & 1) << 22; // greater than (N&V&~Z)|(~N&~V&~Z) + flags |= ((~z32) & 1) << 21; // not equal (~Z) + flags |= ((z32) & 1) << 20; // equal (Z) // 16-bits (bits 10-19) - flags |= ((~c16) & 1) << 19; // higher than or same (C) - flags |= ((c16) & 1) << 18; // lower than (~C) - flags |= ((c16|z16) & 1) << 17; // lower than or same (~C|Z) - flags |= ((~c16&~z16) & 1) << 16; // higher than (C&~Z) - flags |= (((n16&v16)|(~n16&~v16)) & 1) << 15; // greater than or equal (N&V)|(~N&~V) - flags |= (((n16&~v16)|(~n16&v16)) & 1) << 14; // less than (N&~V)|(~N&V) - flags |= (((n16&~v16)|(~n16&v16)|(z16)) & 1) << 13; // less than or equal (N&~V)|(~N&V)|Z - flags |= (((n16&v16&~z16)|(~n16&~v16&~z16)) & 1) << 12; // greater than (N&V&~Z)|(~N&~V&~Z) - flags |= ((~z16) & 1) << 11; // not equal (~Z) - flags |= ((z16) & 1) << 10; // equal (Z) + flags |= ((~c16) & 1) << 19; // higher than or same (C) + flags |= ((c16) & 1) << 18; // lower than (~C) + flags |= ((c16|z16) & 1) << 17; // lower than or same (~C|Z) + flags |= ((~c16&~z16) & 1) << 16; // higher than (C&~Z) + flags |= (((n16&v16)|(~n16&~v16)) & 1) << 15; // greater than or equal (N&V)|(~N&~V) + flags |= (((n16&~v16)|(~n16&v16)) & 1) << 14; // less than (N&~V)|(~N&V) + flags |= (((n16&~v16)|(~n16&v16)|(z16)) & 1) << 13; // less than or equal (N&~V)|(~N&V)|Z + flags |= (((n16&v16&~z16)|(~n16&~v16&~z16)) & 1) << 12; // greater than (N&V&~Z)|(~N&~V&~Z) + flags |= ((~z16) & 1) << 11; // not equal (~Z) + flags |= ((z16) & 1) << 10; // equal (Z) // 8-bits (bits 0-9) - flags |= ((~c8) & 1) << 9; // higher than or same (C) - flags |= ((c8) & 1) << 8; // lower than (~C) - flags |= ((c8|z8) & 1) << 7; // lower than or same (~C|Z) - flags |= ((~c8&~z8) & 1) << 6; // higher than (C&~Z) - flags |= (((n8&v8)|(~n8&~v8)) & 1) << 5; // greater than or equal (N&V)|(~N&~V) - flags |= (((n8&~v8)|(~n8&v8)) & 1) << 4; // less than (N&~V)|(~N&V) - flags |= (((n8&~v8)|(~n8&v8)|(z8)) & 1) << 3; // less than or equal (N&~V)|(~N&V)|Z - flags |= (((n8&v8&~z8)|(~n8&~v8&~z8)) & 1) << 2; // greater than (N&V&~Z)|(~N&~V&~Z) - flags |= ((~z8) & 1) << 1; // not equal (~Z) - flags |= ((z8) & 1) << 0; // equal (Z) + flags |= ((~c8) & 1) << 9; // higher than or same (C) + flags |= ((c8) & 1) << 8; // lower than (~C) + flags |= ((c8|z8) & 1) << 7; // lower than or same (~C|Z) + flags |= ((~c8&~z8) & 1) << 6; // higher than (C&~Z) + flags |= (((n8&v8)|(~n8&~v8)) & 1) << 5; // greater than or equal (N&V)|(~N&~V) + flags |= (((n8&~v8)|(~n8&v8)) & 1) << 4; // less than (N&~V)|(~N&V) + flags |= (((n8&~v8)|(~n8&v8)|(z8)) & 1) << 3; // less than or equal (N&~V)|(~N&V)|Z + flags |= (((n8&v8&~z8)|(~n8&~v8&~z8)) & 1) << 2; // greater than (N&V&~Z)|(~N&~V&~Z) + flags |= ((~z8) & 1) << 1; // not equal (~Z) + flags |= ((z8) & 1) << 0; // equal (Z) return flags; } @@ -138,38 +138,38 @@ void tms32082_mp_device::vector_loadstore() switch (vector_ls_bits) { - case 0x01: // vst.s + case 0x01: // vst.s { m_program->write_dword(m_outp, m_reg[rd]); m_outp += 4; break; } - case 0x03: // vst.d + case 0x03: // vst.d { UINT64 data = m_fpair[rd >> 1]; m_program->write_qword(m_outp, data); m_outp += 8; break; } - case 0x04: // vld0.s + case 0x04: // vld0.s { m_reg[rd] = m_program->read_dword(m_in0p); m_in0p += 4; break; } - case 0x05: // vld1.s + case 0x05: // vld1.s { m_reg[rd] = m_program->read_dword(m_in1p); m_in1p += 4; break; } - case 0x06: // vld0.d + case 0x06: // vld0.d { m_fpair[rd >> 1] = m_program->read_qword(m_in0p); m_in0p += 8; break; } - case 0x07: // vld1.d + case 0x07: // vld1.d { m_fpair[rd >> 1] = m_program->read_qword(m_in1p); m_in1p += 8; @@ -186,7 +186,7 @@ void tms32082_mp_device::execute_short_imm() { switch ((m_ir >> 15) & 0x7f) { - case 0x02: // cmnd + case 0x02: // cmnd { UINT32 data = OP_UIMM15(); @@ -220,7 +220,7 @@ void tms32082_mp_device::execute_short_imm() break; } - case 0x06: // brcr + case 0x06: // brcr { int cr = OP_UIMM15(); @@ -233,13 +233,13 @@ void tms32082_mp_device::execute_short_imm() UINT32 data = read_creg(cr); m_fetchpc = data & ~3; - m_ie = (m_ie & ~1) | (data & 1); // global interrupt mask from creg + m_ie = (m_ie & ~1) | (data & 1); // global interrupt mask from creg // TODO: user/supervisor latch from creg } break; } - case 0x08: // shift.dz + case 0x08: // shift.dz { int r = (m_ir & (1 << 10)); int inv = (m_ir & (1 << 11)); @@ -251,14 +251,14 @@ void tms32082_mp_device::execute_short_imm() UINT32 endmask = SHIFT_MASK[end ? end : 32]; if (inv) endmask = ~endmask; - UINT32 compmask = endmask; // shiftmask == 0xffffffff + UINT32 compmask = endmask; // shiftmask == 0xffffffff UINT32 res = 0; - if (r) // right + if (r) // right { res = ROTATE_R(source, rot) & compmask; } - else // left + else // left { res = ROTATE_L(source, rot) & compmask; } @@ -268,7 +268,7 @@ void tms32082_mp_device::execute_short_imm() break; } - case 0x0a: // shift.ds + case 0x0a: // shift.ds { int r = (m_ir & (1 << 10)); int inv = (m_ir & (1 << 11)); @@ -280,15 +280,15 @@ void tms32082_mp_device::execute_short_imm() UINT32 endmask = SHIFT_MASK[end ? end : 32]; if (inv) endmask = ~endmask; - UINT32 compmask = endmask; // shiftmask == 0xffffffff + UINT32 compmask = endmask; // shiftmask == 0xffffffff UINT32 res = 0; - if (r) // right + if (r) // right { res = ROTATE_R(source, rot) & compmask; res = SIGN_EXTEND(res, rot); } - else // left + else // left { res = ROTATE_L(source, rot) & compmask; // sign extend makes no sense to left.. @@ -299,7 +299,7 @@ void tms32082_mp_device::execute_short_imm() break; } - case 0x0b: // shift.ez + case 0x0b: // shift.ez { int r = (m_ir & (1 << 10)); int inv = (m_ir & (1 << 11)); @@ -330,7 +330,7 @@ void tms32082_mp_device::execute_short_imm() break; } - case 0x0c: // shift.em + case 0x0c: // shift.em { int r = (m_ir & (1 << 10)); int inv = (m_ir & (1 << 11)); @@ -346,11 +346,11 @@ void tms32082_mp_device::execute_short_imm() UINT32 compmask = endmask & shiftmask; UINT32 res = 0; - if (r) // right + if (r) // right { res = (ROTATE_R(source, rot) & compmask) | (m_reg[rd] & ~compmask); } - else // left + else // left { res = (ROTATE_L(source, rot) & compmask) | (m_reg[rd] & ~compmask); } @@ -360,7 +360,7 @@ void tms32082_mp_device::execute_short_imm() break; } - case 0x0d: // shift.es + case 0x0d: // shift.es { int r = (m_ir & (1 << 10)); int inv = (m_ir & (1 << 11)); @@ -371,18 +371,18 @@ void tms32082_mp_device::execute_short_imm() UINT32 endmask = SHIFT_MASK[end ? end : 32]; if (inv) endmask = ~endmask; - + int shift = r ? 32-rot : rot; UINT32 shiftmask = SHIFT_MASK[shift ? shift : 32]; UINT32 compmask = endmask & shiftmask; UINT32 res = 0; - if (r) // right + if (r) // right { res = ROTATE_R(source, rot) & compmask; res = SIGN_EXTEND(res, rot); } - else // left + else // left { res = ROTATE_L(source, rot) & compmask; // sign extend makes no sense to left.. @@ -393,7 +393,7 @@ void tms32082_mp_device::execute_short_imm() break; } - case 0x0e: // shift.iz + case 0x0e: // shift.iz { int r = (m_ir & (1 << 10)); int inv = (m_ir & (1 << 11)); @@ -423,7 +423,7 @@ void tms32082_mp_device::execute_short_imm() break; } - case 0x0f: // shift.im + case 0x0f: // shift.im { int r = (m_ir & (1 << 10)); int inv = (m_ir & (1 << 11)); @@ -439,11 +439,11 @@ void tms32082_mp_device::execute_short_imm() UINT32 compmask = endmask & ~shiftmask; UINT32 res = 0; - if (r) // right + if (r) // right { res = (ROTATE_R(source, rot) & compmask) | (m_reg[rd] & ~compmask); } - else // left + else // left { res = (ROTATE_L(source, rot) & compmask) | (m_reg[rd] & ~compmask); } @@ -453,7 +453,7 @@ void tms32082_mp_device::execute_short_imm() break; } - case 0x11: // and + case 0x11: // and { int rd = OP_RD(); int rs = OP_RS(); @@ -464,7 +464,7 @@ void tms32082_mp_device::execute_short_imm() break; } - case 0x14: // and.ft + case 0x14: // and.ft { int rd = OP_RD(); int rs = OP_RS(); @@ -475,7 +475,7 @@ void tms32082_mp_device::execute_short_imm() break; } - case 0x17: // or + case 0x17: // or { int rd = OP_RD(); int rs = OP_RS(); @@ -486,7 +486,7 @@ void tms32082_mp_device::execute_short_imm() break; } - case 0x1d: // or.ft + case 0x1d: // or.ft { int rd = OP_RD(); int rs = OP_RS(); @@ -498,7 +498,7 @@ void tms32082_mp_device::execute_short_imm() } case 0x24: - case 0x20: // ld.b + case 0x20: // ld.b { int rd = OP_RD(); int base = OP_BASE(); @@ -517,7 +517,7 @@ void tms32082_mp_device::execute_short_imm() } case 0x25: - case 0x21: // ld.h + case 0x21: // ld.h { int rd = OP_RD(); int base = OP_BASE(); @@ -536,7 +536,7 @@ void tms32082_mp_device::execute_short_imm() } case 0x26: - case 0x22: // ld + case 0x22: // ld { int rd = OP_RD(); int base = OP_BASE(); @@ -554,7 +554,7 @@ void tms32082_mp_device::execute_short_imm() } case 0x27: - case 0x23: // ld.d + case 0x23: // ld.d { int rd = OP_RD(); int base = OP_BASE(); @@ -576,7 +576,7 @@ void tms32082_mp_device::execute_short_imm() } case 0x28: - case 0x2c: // ld.ub + case 0x2c: // ld.ub { int rd = OP_RD(); int base = OP_BASE(); @@ -594,7 +594,7 @@ void tms32082_mp_device::execute_short_imm() } case 0x2d: - case 0x29: // ld.uh + case 0x29: // ld.uh { int rd = OP_RD(); int base = OP_BASE(); @@ -612,7 +612,7 @@ void tms32082_mp_device::execute_short_imm() } case 0x34: - case 0x30: // st.b + case 0x30: // st.b { int rd = OP_RD(); int base = OP_BASE(); @@ -629,7 +629,7 @@ void tms32082_mp_device::execute_short_imm() } case 0x35: - case 0x31: // st.h + case 0x31: // st.h { int rd = OP_RD(); int base = OP_BASE(); @@ -663,7 +663,7 @@ void tms32082_mp_device::execute_short_imm() } case 0x37: - case 0x33: // st.d + case 0x33: // st.d { int rd = OP_RD(); int base = OP_BASE(); @@ -679,8 +679,8 @@ void tms32082_mp_device::execute_short_imm() m_reg[base] = address; break; } - - case 0x48: // bbz + + case 0x48: // bbz { int bitnum = OP_BITNUM() ^ 0x1f; INT32 offset = OP_SIMM15(); @@ -698,7 +698,7 @@ void tms32082_mp_device::execute_short_imm() break; } - case 0x49: // bbz.a + case 0x49: // bbz.a { int bitnum = OP_BITNUM() ^ 0x1f; INT32 offset = OP_SIMM15(); @@ -711,7 +711,7 @@ void tms32082_mp_device::execute_short_imm() break; } - case 0x4a: // bbo + case 0x4a: // bbo { int bitnum = OP_BITNUM() ^ 0x1f; INT32 offset = OP_SIMM15(); @@ -742,7 +742,7 @@ void tms32082_mp_device::execute_short_imm() break; } - case 0x4c: // bcnd + case 0x4c: // bcnd { INT32 offset = OP_SIMM15(); int code = OP_RD(); @@ -760,7 +760,7 @@ void tms32082_mp_device::execute_short_imm() break; } - case 0x4d: // bcnd.a + case 0x4d: // bcnd.a { INT32 offset = OP_SIMM15(); int code = OP_RD(); @@ -784,7 +784,7 @@ void tms32082_mp_device::execute_short_imm() break; } - case 0x58: // add + case 0x58: // add { INT32 imm = OP_SIMM15(); int rd = OP_RD(); @@ -808,7 +808,7 @@ void tms32082_mp_device::execute_short_imm() break; } - case 0x5a: // sub + case 0x5a: // sub { INT32 imm = OP_SIMM15(); int rd = OP_RD(); @@ -821,7 +821,7 @@ void tms32082_mp_device::execute_short_imm() break; } - case 0x5b: // subu + case 0x5b: // subu { INT32 imm = OP_SIMM15(); int rd = OP_RD(); @@ -887,7 +887,7 @@ void tms32082_mp_device::execute_reg_long_imm() break; } - case 0x1c: // shift.iz + case 0x1c: // shift.iz { int r = (m_ir & (1 << 10)); int inv = (m_ir & (1 << 11)); @@ -919,7 +919,7 @@ void tms32082_mp_device::execute_reg_long_imm() } case 0x22: - case 0x23: // and + case 0x23: // and { int rd = OP_RD(); int rs = OP_RS(); @@ -943,7 +943,7 @@ void tms32082_mp_device::execute_reg_long_imm() } case 0x2c: - case 0x2d: // xor + case 0x2d: // xor { int rd = OP_RD(); int rs = OP_RS(); @@ -967,7 +967,7 @@ void tms32082_mp_device::execute_reg_long_imm() case 0x40: case 0x41: case 0x48: - case 0x49: // ld.b + case 0x49: // ld.b { int m = m_ir & (1 << 15); @@ -977,7 +977,7 @@ void tms32082_mp_device::execute_reg_long_imm() UINT32 address = m_reg[base] + (has_imm ? imm32 : m_reg[OP_SRC1()]); UINT32 r = m_program->read_byte(address); if (r & 0x80) r |= 0xffffff00; - + if (rd) m_reg[rd] = r; @@ -989,7 +989,7 @@ void tms32082_mp_device::execute_reg_long_imm() case 0x42: case 0x4a: case 0x43: - case 0x4b: // ld.h + case 0x4b: // ld.h { int shift = (m_ir & (1 << 11)) ? 1 : 0; int m = m_ir & (1 << 15); @@ -1012,7 +1012,7 @@ void tms32082_mp_device::execute_reg_long_imm() case 0x4c: case 0x44: case 0x4d: - case 0x45: // ld + case 0x45: // ld { int shift = (m_ir & (1 << 11)) ? 2 : 0; int m = m_ir & (1 << 15); @@ -1033,7 +1033,7 @@ void tms32082_mp_device::execute_reg_long_imm() case 0x4e: case 0x4f: case 0x46: - case 0x47: // ld.d + case 0x47: // ld.d { int shift = (m_ir & (1 << 11)) ? 3 : 0; int m = m_ir & (1 << 15); @@ -1054,7 +1054,7 @@ void tms32082_mp_device::execute_reg_long_imm() case 0x58: case 0x59: case 0x50: - case 0x51: // ld.ub + case 0x51: // ld.ub { int m = m_ir & (1 << 15); int base = OP_BASE(); @@ -1074,7 +1074,7 @@ void tms32082_mp_device::execute_reg_long_imm() case 0x5a: case 0x5b: case 0x52: - case 0x53: // ld.uh + case 0x53: // ld.uh { int shift = (m_ir & (1 << 11)) ? 1 : 0; int m = m_ir & (1 << 15); @@ -1095,7 +1095,7 @@ void tms32082_mp_device::execute_reg_long_imm() case 0x60: case 0x61: case 0x68: - case 0x69: // st.b + case 0x69: // st.b { int m = m_ir & (1 << 15); @@ -1112,7 +1112,7 @@ void tms32082_mp_device::execute_reg_long_imm() case 0x62: case 0x63: case 0x6a: - case 0x6b: // st.h + case 0x6b: // st.h { int shift = (m_ir & (1 << 11)) ? 1 : 0; int m = m_ir & (1 << 15); @@ -1130,7 +1130,7 @@ void tms32082_mp_device::execute_reg_long_imm() case 0x6c: case 0x6d: case 0x64: - case 0x65: // st + case 0x65: // st { int shift = (m_ir & (1 << 11)) ? 2 : 0; int m = m_ir & (1 << 15); @@ -1177,7 +1177,7 @@ void tms32082_mp_device::execute_reg_long_imm() } case 0xa0: - case 0xa1: // cmp + case 0xa1: // cmp { int rd = OP_RD(); UINT32 src1 = has_imm ? imm32 : m_reg[OP_SRC1()]; @@ -1200,7 +1200,7 @@ void tms32082_mp_device::execute_reg_long_imm() } case 0xb4: - case 0xb5: // sub + case 0xb5: // sub { int rd = OP_RD(); int rs = OP_RS(); @@ -1213,7 +1213,7 @@ void tms32082_mp_device::execute_reg_long_imm() } case 0xb6: - case 0xb7: // subu + case 0xb7: // subu { int rd = OP_RD(); int rs = OP_RS(); @@ -1226,7 +1226,7 @@ void tms32082_mp_device::execute_reg_long_imm() case 0xc4: case 0xd4: case 0xc5: - case 0xd5: // vmpy + case 0xd5: // vmpy { int p1 = m_ir & (1 << 5); int pd = m_ir & (1 << 7); @@ -1262,7 +1262,7 @@ void tms32082_mp_device::execute_reg_long_imm() case 0xc8: case 0xd8: case 0xc9: - case 0xd9: // vrnd + case 0xd9: // vrnd { int acc = OP_ACC(); int p1 = m_ir & (1 << 5); @@ -1282,7 +1282,7 @@ void tms32082_mp_device::execute_reg_long_imm() case 0: m_reg[rd] = f2u((float)source); break; - case 1: + case 1: m_fpair[rd >> 1] = d2u(source); break; case 2: @@ -1313,7 +1313,7 @@ void tms32082_mp_device::execute_reg_long_imm() case 0xcc: case 0xdc: case 0xcd: - case 0xdd: // vmac + case 0xdd: // vmac { int acc = OP_ACC(); int z = m_ir & (1 << 8); @@ -1356,7 +1356,7 @@ void tms32082_mp_device::execute_reg_long_imm() case 0xce: case 0xde: case 0xcf: - case 0xdf: // vmsc + case 0xdf: // vmsc { int acc = OP_ACC(); int z = m_ir & (1 << 8); @@ -1397,25 +1397,25 @@ void tms32082_mp_device::execute_reg_long_imm() } case 0xe0: - case 0xe1: // fadd + case 0xe1: // fadd { int rd = OP_RD(); int rs = OP_RS(); int src1 = OP_SRC1(); int precision = (m_ir >> 5) & 0x3f; - if (rd) // only calculate if destination register is valid + if (rd) // only calculate if destination register is valid { switch (precision) { - case 0x00: // SP - SP -> SP + case 0x00: // SP - SP -> SP { float s1 = u2f(has_imm ? imm32 : m_reg[src1]); float s2 = u2f(m_reg[rs]); m_reg[rd] = f2u(s1 + s2); break; } - case 0x10: // SP - SP -> DP + case 0x10: // SP - SP -> DP { float s1 = u2f(has_imm ? imm32 : m_reg[src1]); float s2 = u2f(m_reg[rs]); @@ -1423,7 +1423,7 @@ void tms32082_mp_device::execute_reg_long_imm() m_fpair[rd >> 1] = res; break; } - case 0x14: // SP - DP -> DP + case 0x14: // SP - DP -> DP { float s1 = u2f(has_imm ? imm32 : m_reg[src1]); double s2 = u2d(m_fpair[rs >> 1]); @@ -1431,7 +1431,7 @@ void tms32082_mp_device::execute_reg_long_imm() m_fpair[rd >> 1] = res; break; } - case 0x11: // DP - SP -> DP + case 0x11: // DP - SP -> DP { double s1 = u2d(m_fpair[src1 >> 1]); float s2 = u2f(m_reg[rs]); @@ -1439,7 +1439,7 @@ void tms32082_mp_device::execute_reg_long_imm() m_fpair[rd >> 1] = res; break; } - case 0x15: // DP - DP -> DP + case 0x15: // DP - DP -> DP { double s1 = u2d(m_fpair[src1 >> 1]); double s2 = u2d(m_fpair[rs >> 1]); @@ -1455,25 +1455,25 @@ void tms32082_mp_device::execute_reg_long_imm() } case 0xe2: - case 0xe3: // fsub + case 0xe3: // fsub { int rd = OP_RD(); int rs = OP_RS(); int src1 = OP_SRC1(); int precision = (m_ir >> 5) & 0x3f; - if (rd) // only calculate if destination register is valid + if (rd) // only calculate if destination register is valid { switch (precision) { - case 0x00: // SP - SP -> SP + case 0x00: // SP - SP -> SP { float s1 = u2f(has_imm ? imm32 : m_reg[src1]); float s2 = u2f(m_reg[rs]); m_reg[rd] = f2u(s1 - s2); break; } - case 0x10: // SP - SP -> DP + case 0x10: // SP - SP -> DP { float s1 = u2f(has_imm ? imm32 : m_reg[src1]); float s2 = u2f(m_reg[rs]); @@ -1481,7 +1481,7 @@ void tms32082_mp_device::execute_reg_long_imm() m_fpair[rd >> 1] = res; break; } - case 0x14: // SP - DP -> DP + case 0x14: // SP - DP -> DP { float s1 = u2f(has_imm ? imm32 : m_reg[src1]); double s2 = u2d(m_fpair[rs >> 1]); @@ -1489,7 +1489,7 @@ void tms32082_mp_device::execute_reg_long_imm() m_fpair[rd >> 1] = res; break; } - case 0x11: // DP - SP -> DP + case 0x11: // DP - SP -> DP { double s1 = u2d(m_fpair[src1 >> 1]); float s2 = u2f(m_reg[rs]); @@ -1497,7 +1497,7 @@ void tms32082_mp_device::execute_reg_long_imm() m_fpair[rd >> 1] = res; break; } - case 0x15: // DP - DP -> DP + case 0x15: // DP - DP -> DP { double s1 = u2d(m_fpair[src1 >> 1]); double s2 = u2d(m_fpair[rs >> 1]); @@ -1513,25 +1513,25 @@ void tms32082_mp_device::execute_reg_long_imm() } case 0xe4: - case 0xe5: // fmpy + case 0xe5: // fmpy { int rd = OP_RD(); int rs = OP_RS(); int src1 = OP_SRC1(); int precision = (m_ir >> 5) & 0x3f; - if (rd) // only calculate if destination register is valid + if (rd) // only calculate if destination register is valid { switch (precision) { - case 0x00: // SP x SP -> SP + case 0x00: // SP x SP -> SP { float s1 = u2f(has_imm ? imm32 : m_reg[src1]); float s2 = u2f(m_reg[rs]); m_reg[rd] = f2u(s1 * s2); break; } - case 0x10: // SP x SP -> DP + case 0x10: // SP x SP -> DP { float s1 = u2f(has_imm ? imm32 : m_reg[src1]); float s2 = u2f(m_reg[rs]); @@ -1539,7 +1539,7 @@ void tms32082_mp_device::execute_reg_long_imm() m_fpair[rd >> 1] = res; break; } - case 0x14: // SP x DP -> DP + case 0x14: // SP x DP -> DP { float s1 = u2f(has_imm ? imm32 : m_reg[src1]); double s2 = u2d(m_fpair[rs >> 1]); @@ -1547,7 +1547,7 @@ void tms32082_mp_device::execute_reg_long_imm() m_fpair[rd >> 1] = res; break; } - case 0x11: // DP x SP -> DP + case 0x11: // DP x SP -> DP { double s1 = u2d(m_fpair[src1 >> 1]); float s2 = u2f(m_reg[rs]); @@ -1555,7 +1555,7 @@ void tms32082_mp_device::execute_reg_long_imm() m_fpair[rd >> 1] = res; break; } - case 0x15: // DP x DP -> DP + case 0x15: // DP x DP -> DP { double s1 = u2d(m_fpair[src1 >> 1]); double s2 = u2d(m_fpair[rs >> 1]); @@ -1563,12 +1563,12 @@ void tms32082_mp_device::execute_reg_long_imm() m_fpair[rd >> 1] = res; break; } - case 0x2a: // I x I -> I + case 0x2a: // I x I -> I { m_reg[rd] = (INT32)(m_reg[rs]) * (INT32)(has_imm ? imm32 : m_reg[OP_SRC1()]); break; } - case 0x3f: // U x U -> U + case 0x3f: // U x U -> U { m_reg[rd] = (UINT32)(m_reg[rs]) * (UINT32)(has_imm ? imm32 : m_reg[OP_SRC1()]); break; @@ -1581,7 +1581,7 @@ void tms32082_mp_device::execute_reg_long_imm() } case 0xe6: - case 0xe7: // fdiv + case 0xe7: // fdiv { int rd = OP_RD(); int p1 = m_ir & (1 << 5); @@ -1606,7 +1606,7 @@ void tms32082_mp_device::execute_reg_long_imm() } case 0xe8: - case 0xe9: // frnd + case 0xe9: // frnd { //int mode = (m_ir >> 7) & 3; int p1 = (m_ir >> 5) & 3; @@ -1654,9 +1654,9 @@ void tms32082_mp_device::execute_reg_long_imm() } break; } - + case 0xea: - case 0xeb: // fcmp + case 0xeb: // fcmp { int rd = OP_RD(); int p1 = m_ir & (1 << 5); @@ -1689,7 +1689,7 @@ void tms32082_mp_device::execute_reg_long_imm() } case 0xee: - case 0xef: // fsqrt + case 0xef: // fsqrt { int rd = OP_RD(); int src1 = OP_SRC1(); @@ -1709,7 +1709,7 @@ void tms32082_mp_device::execute_reg_long_imm() break; } - case 0xf2: // rmo + case 0xf2: // rmo { UINT32 source = m_reg[OP_RS()]; int rd = OP_RD(); diff --git a/src/emu/cpu/tms32082/tms32082.c b/src/emu/cpu/tms32082/tms32082.c index 914dccc8f86..b591f3fc6ac 100644 --- a/src/emu/cpu/tms32082/tms32082.c +++ b/src/emu/cpu/tms32082/tms32082.c @@ -22,7 +22,7 @@ const device_type TMS32082_PP = &device_creator<tms32082_pp_device>; // internal memory map static ADDRESS_MAP_START(mp_internal_map, AS_PROGRAM, 32, tms32082_mp_device) - AM_RANGE(0x00000000, 0x00000fff) AM_RAM AM_SHARE("pp0_data0") + AM_RANGE(0x00000000, 0x00000fff) AM_RAM AM_SHARE("pp0_data0") AM_RANGE(0x00001000, 0x00001fff) AM_RAM AM_SHARE("pp1_data0") AM_RANGE(0x00008000, 0x00008fff) AM_RAM AM_SHARE("pp0_data1") AM_RANGE(0x00009000, 0x00009fff) AM_RAM AM_SHARE("pp1_data1") @@ -141,7 +141,7 @@ void tms32082_mp_device::device_start() save_item(NAME(m_fetchpc)); save_item(NAME(m_reg)); save_item(NAME(m_acc)); - + save_item(NAME(m_in0p)); save_item(NAME(m_in1p)); save_item(NAME(m_outp)); @@ -256,7 +256,7 @@ void tms32082_mp_device::processor_command(UINT32 command) printf("Task "); if (command & 0x00002000) printf("Msg "); - + printf("to: "); if (command & 0x00000400) @@ -300,28 +300,28 @@ UINT32 tms32082_mp_device::read_creg(int reg) { switch (reg) { - case 0x0: // EPC + case 0x0: // EPC return m_epc; - case 0x1: // EIP + case 0x1: // EIP return m_eip; - case 0x4: // INTPEN + case 0x4: // INTPEN return m_intpen; - case 0x6: // IE + case 0x6: // IE return m_ie; case 0xa: // PPERROR return 0xe0000; - case 0x4000: // IN0P + case 0x4000: // IN0P return m_in0p; - case 0x4001: // IN1P + case 0x4001: // IN1P return m_in1p; - case 0x4002: // OUTP + case 0x4002: // OUTP return m_outp; default: @@ -335,15 +335,15 @@ void tms32082_mp_device::write_creg(int reg, UINT32 data) { switch (reg) { - case 0x0: // EPC + case 0x0: // EPC m_epc = data; break; - case 0x1: // EIP + case 0x1: // EIP m_eip = data; break; - case 0x4: // INTPEN + case 0x4: // INTPEN { for (int i=0; i < 32; i++) { @@ -353,20 +353,20 @@ void tms32082_mp_device::write_creg(int reg, UINT32 data) break; } - case 0x6: // IE + case 0x6: // IE m_ie = data; printf("IE = %08X\n", data); break; - case 0x4000: // IN0P + case 0x4000: // IN0P m_in0p = data; break; - case 0x4001: // IN1P + case 0x4001: // IN1P m_in1p = data; break; - case 0x4002: // OUTP + case 0x4002: // OUTP m_outp = data; break; @@ -378,19 +378,19 @@ void tms32082_mp_device::write_creg(int reg, UINT32 data) void tms32082_mp_device::check_interrupts() { - if (m_ie & 1) // global interrupt mask + if (m_ie & 1) // global interrupt mask { for (int i=1; i < 32; i++) { if (m_ie & m_intpen & (1 << i)) { m_epc = (m_fetchpc & ~3); - m_epc |= (m_ie & 1); // save global interrupt mask + m_epc |= (m_ie & 1); // save global interrupt mask // TODO: user mode bit to EPC m_eip = m_pc; - m_ie &= ~1; // clear global interrupt mask + m_ie &= ~1; // clear global interrupt mask // get new pc from vector table m_fetchpc = m_pc = m_program->read_dword(0x01010180 + (i * 4)); @@ -445,7 +445,7 @@ void tms32082_mp_device::execute_run() while (m_icount > 0) { m_pc = m_fetchpc; - + check_interrupts(); debugger_instruction_hook(this, m_pc); @@ -466,7 +466,7 @@ void tms32082_mp_device::execute_run() // internal memory map static ADDRESS_MAP_START(pp_internal_map, AS_PROGRAM, 32, tms32082_pp_device) - AM_RANGE(0x00000000, 0x00000fff) AM_RAM AM_SHARE("pp0_data0") + AM_RANGE(0x00000000, 0x00000fff) AM_RAM AM_SHARE("pp0_data0") AM_RANGE(0x00001000, 0x00001fff) AM_RAM AM_SHARE("pp1_data0") AM_RANGE(0x00008000, 0x00008fff) AM_RAM AM_SHARE("pp0_data1") AM_RANGE(0x00009000, 0x00009fff) AM_RAM AM_SHARE("pp1_data1") @@ -528,4 +528,4 @@ void tms32082_pp_device::execute_run() m_icount = 0; return; -}
\ No newline at end of file +} diff --git a/src/emu/cpu/tms32082/tms32082.h b/src/emu/cpu/tms32082/tms32082.h index 81dd80296fd..f791e52e157 100644 --- a/src/emu/cpu/tms32082/tms32082.h +++ b/src/emu/cpu/tms32082/tms32082.h @@ -58,10 +58,10 @@ public: enum { - INPUT_X1 = 1, - INPUT_X2 = 2, - INPUT_X3 = 3, - INPUT_X4 = 4, + INPUT_X1 = 1, + INPUT_X2 = 2, + INPUT_X3 = 3, + INPUT_X4 = 4, }; DECLARE_READ32_MEMBER(mp_param_r); |
